From: Ville Syrjala <ville.syrjala@linux.intel.com>
To: intel-gfx@lists.freedesktop.org
Cc: intel-xe@lists.freedesktop.org
Subject: [PATCH 2/7] drm/i915/dp: Don't switch to idle pattern before disable on pre-hsw
Date: Thu, 10 Jul 2025 23:17:13 +0300 [thread overview]
Message-ID: <20250710201718.25310-3-ville.syrjala@linux.intel.com> (raw)
In-Reply-To: <20250710201718.25310-1-ville.syrjala@linux.intel.com>
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
For some reason we are switching over to the idle pattern before
disabling the DP port on pre-hsw. AFAICS this has never been part
of the documented sequence (and on hsw+ the spec explicitly says
not to do this). Get rid of it.
The code goes all the way back to commit 5eb08b69f510 ("drm/i915: enable
DisplayPort support on IGDNG"), and it was accompanied by a 17ms delay
which got changed to vbl wait in commit ab527efc2fea ("drm/i915: use
wait_for_vblank instead of msleep(17)"), and was later completely removed
in commit 93c9c19b3d25 ("drm/i915: remove unexplained vblank wait in
the DP off code").
Smoke tested on g4x/snb/chv.
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/display/g4x_dp.c | 11 -----------
1 file changed, 11 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/g4x_dp.c b/drivers/gpu/drm/i915/display/g4x_dp.c
index 87f6b9602b16..b54edf0d1c23 100644
--- a/drivers/gpu/drm/i915/display/g4x_dp.c
+++ b/drivers/gpu/drm/i915/display/g4x_dp.c
@@ -424,17 +424,6 @@ intel_dp_link_down(struct intel_encoder *encoder,
drm_dbg_kms(display->drm, "\n");
- if ((display->platform.ivybridge && port == PORT_A) ||
- (HAS_PCH_CPT(display) && port != PORT_A)) {
- intel_dp->DP &= ~DP_LINK_TRAIN_MASK_CPT;
- intel_dp->DP |= DP_LINK_TRAIN_PAT_IDLE_CPT;
- } else {
- intel_dp->DP &= ~DP_LINK_TRAIN_MASK;
- intel_dp->DP |= DP_LINK_TRAIN_PAT_IDLE;
- }
- intel_de_write(display, intel_dp->output_reg, intel_dp->DP);
- intel_de_posting_read(display, intel_dp->output_reg);
-
intel_dp->DP &= ~DP_PORT_EN;
intel_de_write(display, intel_dp->output_reg, intel_dp->DP);
intel_de_posting_read(display, intel_dp->output_reg);
--
2.49.0
next prev parent reply other threads:[~2025-07-10 20:17 UTC|newest]
Thread overview: 16+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-07-10 20:17 [PATCH 0/7] drm/i915/dp: DP stuff Ville Syrjala
2025-07-10 20:17 ` [PATCH 1/7] drm/i915/dp: Fix 2.7 Gbps DP_LINK_BW value on g4x Ville Syrjala
2025-07-16 13:20 ` Imre Deak
2025-07-16 18:40 ` Ville Syrjälä
2025-07-16 21:41 ` Imre Deak
2025-07-10 20:17 ` Ville Syrjala [this message]
2025-07-16 13:32 ` [PATCH 2/7] drm/i915/dp: Don't switch to idle pattern before disable on pre-hsw Imre Deak
2025-07-10 20:17 ` [PATCH 3/7] drm/i915/dp: Clear DPCD training pattern before transmitting the idle pattern Ville Syrjala
2025-07-10 20:17 ` [PATCH 4/7] drm/i915/dp: Have intel_dp_get_adjust_train() tell us if anything changed Ville Syrjala
2025-07-10 20:17 ` [PATCH 5/7] drm/i915/dp: Move intel_dp_training_pattern() Ville Syrjala
2025-07-10 20:17 ` [PATCH 6/7] drm/i915/dp: Implement .set_idle_link_train() for everyone Ville Syrjala
2025-07-10 20:17 ` [PATCH 7/7] drm/i915/dp: Make .set_idle_link_train() mandatory Ville Syrjala
2025-07-10 20:54 ` ✓ CI.KUnit: success for drm/i915/dp: DP stuff Patchwork
2025-07-10 21:09 ` ✗ CI.checksparse: warning " Patchwork
2025-07-10 22:02 ` ✓ Xe.CI.BAT: success " Patchwork
2025-07-11 5:26 ` ✗ Xe.CI.Full: failure " Patchwork
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