From: Ville Syrjala <ville.syrjala@linux.intel.com>
To: intel-gfx@lists.freedesktop.org
Cc: intel-xe@lists.freedesktop.org, Imre Deak <imre.deak@intel.com>
Subject: [PATCH 4/7] drm/i915/dp: Have intel_dp_get_adjust_train() tell us if anything changed
Date: Thu, 10 Jul 2025 23:17:15 +0300 [thread overview]
Message-ID: <20250710201718.25310-5-ville.syrjala@linux.intel.com> (raw)
In-Reply-To: <20250710201718.25310-1-ville.syrjala@linux.intel.com>
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
In order to implement the POST_LT_ADJ_REQ sequence we need to
know whether the sink actually requested a changed to the
vswing/pre-emph values.
Tested-by: Imre Deak <imre.deak@intel.com>
Reviewed-by: Imre Deak <imre.deak@intel.com>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
.../drm/i915/display/intel_dp_link_training.c | 18 +++++++++++++-----
.../drm/i915/display/intel_dp_link_training.h | 2 +-
2 files changed, 14 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dp_link_training.c b/drivers/gpu/drm/i915/display/intel_dp_link_training.c
index 322a26c1910c..57b9dc52a98d 100644
--- a/drivers/gpu/drm/i915/display/intel_dp_link_training.c
+++ b/drivers/gpu/drm/i915/display/intel_dp_link_training.c
@@ -478,12 +478,13 @@ static u8 intel_dp_get_lane_adjust_train(struct intel_dp *intel_dp,
_TRAIN_REQ_TX_FFE_ARGS(link_status, 2), \
_TRAIN_REQ_TX_FFE_ARGS(link_status, 3)
-void
+bool
intel_dp_get_adjust_train(struct intel_dp *intel_dp,
const struct intel_crtc_state *crtc_state,
enum drm_dp_phy dp_phy,
const u8 link_status[DP_LINK_STATUS_SIZE])
{
+ bool changed = false;
int lane;
if (intel_dp_is_uhbr(crtc_state)) {
@@ -502,10 +503,17 @@ intel_dp_get_adjust_train(struct intel_dp *intel_dp,
TRAIN_REQ_PREEMPH_ARGS(link_status));
}
- for (lane = 0; lane < 4; lane++)
- intel_dp->train_set[lane] =
- intel_dp_get_lane_adjust_train(intel_dp, crtc_state,
- dp_phy, link_status, lane);
+ for (lane = 0; lane < 4; lane++) {
+ u8 new = intel_dp_get_lane_adjust_train(intel_dp, crtc_state,
+ dp_phy, link_status, lane);
+ if (intel_dp->train_set[lane] == new)
+ continue;
+
+ intel_dp->train_set[lane] = new;
+ changed = true;
+ }
+
+ return changed;
}
static int intel_dp_training_pattern_set_reg(struct intel_dp *intel_dp,
diff --git a/drivers/gpu/drm/i915/display/intel_dp_link_training.h b/drivers/gpu/drm/i915/display/intel_dp_link_training.h
index 46614124569f..1ba22ed6db08 100644
--- a/drivers/gpu/drm/i915/display/intel_dp_link_training.h
+++ b/drivers/gpu/drm/i915/display/intel_dp_link_training.h
@@ -23,7 +23,7 @@ void intel_dp_link_training_set_bw(struct intel_dp *intel_dp,
int link_bw, int rate_select, int lane_count,
bool enhanced_framing);
-void intel_dp_get_adjust_train(struct intel_dp *intel_dp,
+bool intel_dp_get_adjust_train(struct intel_dp *intel_dp,
const struct intel_crtc_state *crtc_state,
enum drm_dp_phy dp_phy,
const u8 link_status[DP_LINK_STATUS_SIZE]);
--
2.49.0
next prev parent reply other threads:[~2025-07-10 20:17 UTC|newest]
Thread overview: 16+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-07-10 20:17 [PATCH 0/7] drm/i915/dp: DP stuff Ville Syrjala
2025-07-10 20:17 ` [PATCH 1/7] drm/i915/dp: Fix 2.7 Gbps DP_LINK_BW value on g4x Ville Syrjala
2025-07-16 13:20 ` Imre Deak
2025-07-16 18:40 ` Ville Syrjälä
2025-07-16 21:41 ` Imre Deak
2025-07-10 20:17 ` [PATCH 2/7] drm/i915/dp: Don't switch to idle pattern before disable on pre-hsw Ville Syrjala
2025-07-16 13:32 ` Imre Deak
2025-07-10 20:17 ` [PATCH 3/7] drm/i915/dp: Clear DPCD training pattern before transmitting the idle pattern Ville Syrjala
2025-07-10 20:17 ` Ville Syrjala [this message]
2025-07-10 20:17 ` [PATCH 5/7] drm/i915/dp: Move intel_dp_training_pattern() Ville Syrjala
2025-07-10 20:17 ` [PATCH 6/7] drm/i915/dp: Implement .set_idle_link_train() for everyone Ville Syrjala
2025-07-10 20:17 ` [PATCH 7/7] drm/i915/dp: Make .set_idle_link_train() mandatory Ville Syrjala
2025-07-10 20:54 ` ✓ CI.KUnit: success for drm/i915/dp: DP stuff Patchwork
2025-07-10 21:09 ` ✗ CI.checksparse: warning " Patchwork
2025-07-10 22:02 ` ✓ Xe.CI.BAT: success " Patchwork
2025-07-11 5:26 ` ✗ Xe.CI.Full: failure " Patchwork
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