From: Ville Syrjala <ville.syrjala@linux.intel.com>
To: intel-gfx@lists.freedesktop.org
Cc: intel-xe@lists.freedesktop.org, Imre Deak <imre.deak@intel.com>
Subject: [PATCH 3/7] drm/i915/dp: Clear DPCD training pattern before transmitting the idle pattern
Date: Thu, 10 Jul 2025 23:17:14 +0300 [thread overview]
Message-ID: <20250710201718.25310-4-ville.syrjala@linux.intel.com> (raw)
In-Reply-To: <20250710201718.25310-1-ville.syrjala@linux.intel.com>
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
We are supposed to switch off the training pattern in DPCD before
we start transmitting the idle pattern. For LTTPRs we do that
correctly, but for the sink DPRX we only do this correctly
for some platforms.
On pre-HSW (where we don't implement the .set_idle_link_train()
hook), we directly switch from transmitting the training pattern
to normal pixel transmission (the hardware should hopefully
guarantee that the minimum number of required idle patters will
be transmitted during this transition). The DPCD write correctly
precedes the actual switch away from the training pattern.
For HSW+ we start transmitting the idle pattern earlier, and only
switch off the DPCD training pattern after we switch from the idle
pattern to normal pixel transmission. Adjust the code to disable
the DPCD training pattern before we start transmitting the idle
pattern.
v2: Tweak the commit message a bit
Tested-by: Imre Deak <imre.deak@intel.com>
Reviewed-by: Imre Deak <imre.deak@intel.com>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/display/intel_dp_link_training.c | 8 ++++++--
1 file changed, 6 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dp_link_training.c b/drivers/gpu/drm/i915/display/intel_dp_link_training.c
index a479b63112ea..322a26c1910c 100644
--- a/drivers/gpu/drm/i915/display/intel_dp_link_training.c
+++ b/drivers/gpu/drm/i915/display/intel_dp_link_training.c
@@ -1130,7 +1130,9 @@ void intel_dp_stop_link_train(struct intel_dp *intel_dp,
intel_dp->link.active = true;
- intel_dp_disable_dpcd_training_pattern(intel_dp, DP_PHY_DPRX);
+ if (!intel_dp->set_idle_link_train)
+ intel_dp_disable_dpcd_training_pattern(intel_dp, DP_PHY_DPRX);
+
intel_dp_program_link_training_pattern(intel_dp, crtc_state, DP_PHY_DPRX,
DP_TRAINING_PATTERN_DISABLE);
@@ -1371,8 +1373,10 @@ intel_dp_link_train_all_phys(struct intel_dp *intel_dp,
if (ret)
ret = intel_dp_link_train_phy(intel_dp, crtc_state, DP_PHY_DPRX);
- if (intel_dp->set_idle_link_train)
+ if (intel_dp->set_idle_link_train) {
+ intel_dp_disable_dpcd_training_pattern(intel_dp, DP_PHY_DPRX);
intel_dp->set_idle_link_train(intel_dp, crtc_state);
+ }
return ret;
}
--
2.49.0
next prev parent reply other threads:[~2025-07-10 20:17 UTC|newest]
Thread overview: 16+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-07-10 20:17 [PATCH 0/7] drm/i915/dp: DP stuff Ville Syrjala
2025-07-10 20:17 ` [PATCH 1/7] drm/i915/dp: Fix 2.7 Gbps DP_LINK_BW value on g4x Ville Syrjala
2025-07-16 13:20 ` Imre Deak
2025-07-16 18:40 ` Ville Syrjälä
2025-07-16 21:41 ` Imre Deak
2025-07-10 20:17 ` [PATCH 2/7] drm/i915/dp: Don't switch to idle pattern before disable on pre-hsw Ville Syrjala
2025-07-16 13:32 ` Imre Deak
2025-07-10 20:17 ` Ville Syrjala [this message]
2025-07-10 20:17 ` [PATCH 4/7] drm/i915/dp: Have intel_dp_get_adjust_train() tell us if anything changed Ville Syrjala
2025-07-10 20:17 ` [PATCH 5/7] drm/i915/dp: Move intel_dp_training_pattern() Ville Syrjala
2025-07-10 20:17 ` [PATCH 6/7] drm/i915/dp: Implement .set_idle_link_train() for everyone Ville Syrjala
2025-07-10 20:17 ` [PATCH 7/7] drm/i915/dp: Make .set_idle_link_train() mandatory Ville Syrjala
2025-07-10 20:54 ` ✓ CI.KUnit: success for drm/i915/dp: DP stuff Patchwork
2025-07-10 21:09 ` ✗ CI.checksparse: warning " Patchwork
2025-07-10 22:02 ` ✓ Xe.CI.BAT: success " Patchwork
2025-07-11 5:26 ` ✗ Xe.CI.Full: failure " Patchwork
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