[CI 00/13] auxccs late flush

[Tvrtko Ursulin <tvrtko.ursulin@igalia.com>]

i915 sets up the async flush which triggers when the atomic commit waits
on the fences. That is later than straight after the pin so lets try
that since we are desperate...

Tvrtko Ursulin (13):
  drm/xe/xelpg: Flush CCS when flushing caches
  drm/xe/xelp: Quiesce memory traffic before invalidating auxccs
  drm/xe/xelp: Support auxccs invalidation on blitter
  drm/xe/xelp: Use MI_FLUSH_DW_CCS on auxccs platforms
  drm/xe/xelp: Wait for AuxCCS invalidation to complete
  drm/xe: Export xe_emit_aux_table_inv
  drm/xe/xelp: Add AuxCCS invalidation to the indirect context
    workarounds
  drm/xe: Flush GGTT writes after populating DPT
  drm/xe: Handle DPT in system memory
  drm/xe/display: Add support for AuxCCS
  drm/xe: Force flush system memory AuxCCS data before scan out
  late flush
  drm/i915/display: Expose AuxCCS frame buffer modifiers for Xe

 drivers/gpu/drm/i915/display/intel_display.c  |  15 +-
 .../drm/i915/display/skl_universal_plane.c    |   6 -
 drivers/gpu/drm/i915/gem/i915_gem_object.h    |   5 +
 .../compat-i915-headers/gem/i915_gem_object.h |   2 +
 drivers/gpu/drm/xe/display/xe_fb_pin.c        | 183 +++++++++++++++---
 .../gpu/drm/xe/instructions/xe_gpu_commands.h |   1 +
 .../gpu/drm/xe/instructions/xe_mi_commands.h  |   6 +
 drivers/gpu/drm/xe/regs/xe_gt_regs.h          |   1 +
 drivers/gpu/drm/xe/xe_bo_types.h              |  14 +-
 drivers/gpu/drm/xe/xe_lrc.c                   |  47 +++++
 drivers/gpu/drm/xe/xe_ring_ops.c              | 161 +++++++--------
 drivers/gpu/drm/xe/xe_ring_ops.h              |   3 +
 drivers/gpu/drm/xe/xe_ring_ops_types.h        |   2 +-
 13 files changed, 328 insertions(+), 118 deletions(-)

-- 
2.48.0