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From: Tvrtko Ursulin <tvrtko.ursulin@igalia.com>
To: intel-xe@lists.freedesktop.org
Subject: [CI 02/13] drm/xe/xelp: Quiesce memory traffic before invalidating auxccs
Date: Tue, 19 Aug 2025 09:55:23 +0100	[thread overview]
Message-ID: <20250819085537.97902-3-tvrtko.ursulin@igalia.com> (raw)
In-Reply-To: <20250819085537.97902-1-tvrtko.ursulin@igalia.com>

According to i915 before invalidating auxccs we must quiesce the memory
traffic by an extra flush.

Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@igalia.com>
---
 drivers/gpu/drm/xe/xe_ring_ops.c       | 7 ++++++-
 drivers/gpu/drm/xe/xe_ring_ops_types.h | 2 +-
 2 files changed, 7 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/xe/xe_ring_ops.c b/drivers/gpu/drm/xe/xe_ring_ops.c
index 761740d7769f..f56506ebbeca 100644
--- a/drivers/gpu/drm/xe/xe_ring_ops.c
+++ b/drivers/gpu/drm/xe/xe_ring_ops.c
@@ -358,10 +358,15 @@ static void __emit_job_gen12_render_compute(struct xe_sched_job *job,
 	struct xe_gt *gt = job->q->gt;
 	struct xe_device *xe = gt_to_xe(gt);
 	bool lacks_render = !(gt->info.engine_mask & XE_HW_ENGINE_RCS_MASK);
+	const bool aux_ccs = has_aux_ccs(xe);
 	u32 mask_flags = 0;
 
 	i = emit_copy_timestamp(lrc, dw, i);
 
+	/* hsdes: 1809175790 */
+	if (aux_ccs)
+		i = emit_render_cache_flush(job, dw, i);
+
 	dw[i++] = preparser_disable(true);
 	if (lacks_render)
 		mask_flags = PIPE_CONTROL_3D_ARCH_FLAGS;
@@ -372,7 +377,7 @@ static void __emit_job_gen12_render_compute(struct xe_sched_job *job,
 	i = emit_pipe_invalidate(mask_flags, job->ring_ops_flush_tlb, dw, i);
 
 	/* hsdes: 1809175790 */
-	if (has_aux_ccs(xe))
+	if (aux_ccs)
 		i = emit_aux_table_inv(gt, CCS_AUX_INV, dw, i);
 
 	dw[i++] = preparser_disable(false);
diff --git a/drivers/gpu/drm/xe/xe_ring_ops_types.h b/drivers/gpu/drm/xe/xe_ring_ops_types.h
index d7e3e150a9a5..477dc7defd72 100644
--- a/drivers/gpu/drm/xe/xe_ring_ops_types.h
+++ b/drivers/gpu/drm/xe/xe_ring_ops_types.h
@@ -8,7 +8,7 @@
 
 struct xe_sched_job;
 
-#define MAX_JOB_SIZE_DW 58
+#define MAX_JOB_SIZE_DW 70
 #define MAX_JOB_SIZE_BYTES (MAX_JOB_SIZE_DW * 4)
 
 /**
-- 
2.48.0


  parent reply	other threads:[~2025-08-19  8:55 UTC|newest]

Thread overview: 18+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2025-08-19  8:55 [CI 00/13] auxccs late flush Tvrtko Ursulin
2025-08-19  8:55 ` [CI 01/13] drm/xe/xelpg: Flush CCS when flushing caches Tvrtko Ursulin
2025-08-19  8:55 ` Tvrtko Ursulin [this message]
2025-08-19  8:55 ` [CI 03/13] drm/xe/xelp: Support auxccs invalidation on blitter Tvrtko Ursulin
2025-08-19  8:55 ` [CI 04/13] drm/xe/xelp: Use MI_FLUSH_DW_CCS on auxccs platforms Tvrtko Ursulin
2025-08-19  8:55 ` [CI 05/13] drm/xe/xelp: Wait for AuxCCS invalidation to complete Tvrtko Ursulin
2025-08-19  8:55 ` [CI 06/13] drm/xe: Export xe_emit_aux_table_inv Tvrtko Ursulin
2025-08-19  8:55 ` [CI 07/13] drm/xe/xelp: Add AuxCCS invalidation to the indirect context workarounds Tvrtko Ursulin
2025-08-19  8:55 ` [CI 08/13] drm/xe: Flush GGTT writes after populating DPT Tvrtko Ursulin
2025-08-19  8:55 ` [CI 09/13] drm/xe: Handle DPT in system memory Tvrtko Ursulin
2025-08-19  8:55 ` [CI 10/13] drm/xe/display: Add support for AuxCCS Tvrtko Ursulin
2025-08-19  8:55 ` [CI 11/13] drm/xe: Force flush system memory AuxCCS data before scan out Tvrtko Ursulin
2025-08-19  8:55 ` [CI 12/13] late flush Tvrtko Ursulin
2025-08-19  8:55 ` [CI 13/13] drm/i915/display: Expose AuxCCS frame buffer modifiers for Xe Tvrtko Ursulin
2025-08-19 14:16 ` ✗ CI.checkpatch: warning for auxccs late flush Patchwork
2025-08-19 14:17 ` ✓ CI.KUnit: success " Patchwork
  -- strict thread matches above, loose matches on Subject: below --
2025-08-19 14:38 [CI 00/13] " Tvrtko Ursulin
2025-08-19 14:38 ` [CI 02/13] drm/xe/xelp: Quiesce memory traffic before invalidating auxccs Tvrtko Ursulin
2025-08-20  9:18 [CI 00/13] auxccs no stolen Tvrtko Ursulin
2025-08-20  9:19 ` [CI 02/13] drm/xe/xelp: Quiesce memory traffic before invalidating auxccs Tvrtko Ursulin

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