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From: Ville Syrjala <ville.syrjala@linux.intel.com>
To: intel-gfx@lists.freedesktop.org
Cc: intel-xe@lists.freedesktop.org
Subject: [PATCH 1/5] drm/i915/vrr: Extract helpers to convert between guardband and pipeline_full values
Date: Wed, 17 Sep 2025 23:34:42 +0300	[thread overview]
Message-ID: <20250917203446.14374-2-ville.syrjala@linux.intel.com> (raw)
In-Reply-To: <20250917203446.14374-1-ville.syrjala@linux.intel.com>

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

I'd like to move towards a world where we can't more or less
pretend that the ICl/TGL VRR hardware works the same way as
ADL+. To that end extract some helpers to convert between
the guardband and pipeline_full representations.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/display/intel_vrr.c | 28 ++++++++++++++++++------
 1 file changed, 21 insertions(+), 7 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_vrr.c b/drivers/gpu/drm/i915/display/intel_vrr.c
index 3eed37f271b0..5fee85b0bc99 100644
--- a/drivers/gpu/drm/i915/display/intel_vrr.c
+++ b/drivers/gpu/drm/i915/display/intel_vrr.c
@@ -119,6 +119,20 @@ static int intel_vrr_vmin_flipline(const struct intel_crtc_state *crtc_state)
 	return crtc_state->vrr.vmin + intel_vrr_flipline_offset(display);
 }
 
+static int intel_vrr_guardband_to_pipeline_full(const struct intel_crtc_state *crtc_state,
+						int guardband)
+{
+	/* hardware imposes one extra scanline somewhere */
+	return guardband - crtc_state->framestart_delay - 1;
+}
+
+static int intel_vrr_pipeline_full_to_guardband(const struct intel_crtc_state *crtc_state,
+						int pipeline_full)
+{
+	/* hardware imposes one extra scanline somewhere */
+	return pipeline_full + crtc_state->framestart_delay + 1;
+}
+
 /*
  * Without VRR registers get latched at:
  *  vblank_start
@@ -142,8 +156,8 @@ static int intel_vrr_vblank_exit_length(const struct intel_crtc_state *crtc_stat
 	if (DISPLAY_VER(display) >= 13)
 		return crtc_state->vrr.guardband;
 	else
-		/* hardware imposes one extra scanline somewhere */
-		return crtc_state->vrr.pipeline_full + crtc_state->framestart_delay + 1;
+		return intel_vrr_pipeline_full_to_guardband(crtc_state,
+							    crtc_state->vrr.pipeline_full);
 }
 
 int intel_vrr_vmin_vtotal(const struct intel_crtc_state *crtc_state)
@@ -417,18 +431,18 @@ void intel_vrr_compute_config_late(struct intel_crtc_state *crtc_state)
 {
 	struct intel_display *display = to_intel_display(crtc_state);
 	const struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode;
+	int guardband;
 
 	if (!intel_vrr_possible(crtc_state))
 		return;
 
+	guardband = crtc_state->vrr.vmin - adjusted_mode->crtc_vblank_start;
+
 	if (DISPLAY_VER(display) >= 13) {
-		crtc_state->vrr.guardband =
-			crtc_state->vrr.vmin - adjusted_mode->crtc_vblank_start;
+		crtc_state->vrr.guardband = guardband;
 	} else {
-		/* hardware imposes one extra scanline somewhere */
 		crtc_state->vrr.pipeline_full =
-			min(255, crtc_state->vrr.vmin - adjusted_mode->crtc_vblank_start -
-			    crtc_state->framestart_delay - 1);
+			min(255, intel_vrr_guardband_to_pipeline_full(crtc_state, guardband));
 
 		/*
 		 * vmin/vmax/flipline also need to be adjusted by
-- 
2.49.1


  reply	other threads:[~2025-09-17 20:34 UTC|newest]

Thread overview: 21+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2025-09-17 20:34 [PATCH 0/5] drm/i915/vrr: Hide icl/tgl idiosyncrasies better Ville Syrjala
2025-09-17 20:34 ` Ville Syrjala [this message]
2025-09-18  9:39   ` [PATCH 1/5] drm/i915/vrr: Extract helpers to convert between guardband and pipeline_full values Nautiyal, Ankit K
2025-09-17 20:34 ` [PATCH 2/5] drm/i915/vrr: Readout framestart_delay earlier Ville Syrjala
2025-09-18  9:40   ` Nautiyal, Ankit K
2025-09-17 20:34 ` [PATCH 3/5] drm/i915/vrr: Store guardband in crtc state even for icl/tgl Ville Syrjala
2025-09-18  9:37   ` Nautiyal, Ankit K
2025-09-18 12:21     ` Ville Syrjälä
2025-09-18 13:59       ` Nautiyal, Ankit K
2025-09-18 18:00   ` Nautiyal, Ankit K
2025-09-17 20:34 ` [PATCH 4/5] drm/i915/vrr: Annotate some functions with "hw" Ville Syrjala
2025-09-18  9:41   ` Nautiyal, Ankit K
2025-09-17 20:34 ` [PATCH 5/5] drm/i915/vrr: Move the TGL SCL manging of vmin/vmax/flipline deeper Ville Syrjala
2025-09-18  9:33   ` Nautiyal, Ankit K
2025-09-18 12:14     ` Ville Syrjälä
2025-09-18 13:42       ` Nautiyal, Ankit K
2025-09-18 14:18         ` Ville Syrjälä
2025-09-18 17:58           ` Nautiyal, Ankit K
2025-09-17 20:48 ` ✓ CI.KUnit: success for drm/i915/vrr: Hide icl/tgl idiosyncrasies better Patchwork
2025-09-17 21:28 ` ✓ Xe.CI.BAT: " Patchwork
2025-09-18  2:13 ` ✗ Xe.CI.Full: failure " Patchwork

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