From: Ville Syrjala <ville.syrjala@linux.intel.com>
To: intel-gfx@lists.freedesktop.org
Cc: intel-xe@lists.freedesktop.org
Subject: [PATCH 2/5] drm/i915/vrr: Readout framestart_delay earlier
Date: Wed, 17 Sep 2025 23:34:43 +0300 [thread overview]
Message-ID: <20250917203446.14374-3-ville.syrjala@linux.intel.com> (raw)
In-Reply-To: <20250917203446.14374-1-ville.syrjala@linux.intel.com>
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
In order to pretend that ICL/TGL VRR hardware has a similar guardband
as on ADL+ we'll need access to framestart_delay already during
intel_vrr_get_config(). Hoist the framestart_delay to an earlier point
to make that possible.
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/display/intel_display.c | 18 +++++++++---------
1 file changed, 9 insertions(+), 9 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index a743d1339550..c7d85fd38890 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -3891,6 +3891,15 @@ static bool hsw_get_pipe_config(struct intel_crtc *crtc,
intel_joiner_get_config(pipe_config);
intel_dsc_get_config(pipe_config);
+ if (!transcoder_is_dsi(pipe_config->cpu_transcoder)) {
+ tmp = intel_de_read(display, CHICKEN_TRANS(display, pipe_config->cpu_transcoder));
+
+ pipe_config->framestart_delay = REG_FIELD_GET(HSW_FRAME_START_DELAY_MASK, tmp) + 1;
+ } else {
+ /* no idea if this is correct */
+ pipe_config->framestart_delay = 1;
+ }
+
if (!transcoder_is_dsi(pipe_config->cpu_transcoder) ||
DISPLAY_VER(display) >= 11)
intel_get_transcoder_timings(crtc, pipe_config);
@@ -3942,15 +3951,6 @@ static bool hsw_get_pipe_config(struct intel_crtc *crtc,
pipe_config->pixel_multiplier = 1;
}
- if (!transcoder_is_dsi(pipe_config->cpu_transcoder)) {
- tmp = intel_de_read(display, CHICKEN_TRANS(display, pipe_config->cpu_transcoder));
-
- pipe_config->framestart_delay = REG_FIELD_GET(HSW_FRAME_START_DELAY_MASK, tmp) + 1;
- } else {
- /* no idea if this is correct */
- pipe_config->framestart_delay = 1;
- }
-
out:
intel_display_power_put_all_in_set(display, &crtc->hw_readout_power_domains);
--
2.49.1
next prev parent reply other threads:[~2025-09-17 20:35 UTC|newest]
Thread overview: 21+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-09-17 20:34 [PATCH 0/5] drm/i915/vrr: Hide icl/tgl idiosyncrasies better Ville Syrjala
2025-09-17 20:34 ` [PATCH 1/5] drm/i915/vrr: Extract helpers to convert between guardband and pipeline_full values Ville Syrjala
2025-09-18 9:39 ` Nautiyal, Ankit K
2025-09-17 20:34 ` Ville Syrjala [this message]
2025-09-18 9:40 ` [PATCH 2/5] drm/i915/vrr: Readout framestart_delay earlier Nautiyal, Ankit K
2025-09-17 20:34 ` [PATCH 3/5] drm/i915/vrr: Store guardband in crtc state even for icl/tgl Ville Syrjala
2025-09-18 9:37 ` Nautiyal, Ankit K
2025-09-18 12:21 ` Ville Syrjälä
2025-09-18 13:59 ` Nautiyal, Ankit K
2025-09-18 18:00 ` Nautiyal, Ankit K
2025-09-17 20:34 ` [PATCH 4/5] drm/i915/vrr: Annotate some functions with "hw" Ville Syrjala
2025-09-18 9:41 ` Nautiyal, Ankit K
2025-09-17 20:34 ` [PATCH 5/5] drm/i915/vrr: Move the TGL SCL manging of vmin/vmax/flipline deeper Ville Syrjala
2025-09-18 9:33 ` Nautiyal, Ankit K
2025-09-18 12:14 ` Ville Syrjälä
2025-09-18 13:42 ` Nautiyal, Ankit K
2025-09-18 14:18 ` Ville Syrjälä
2025-09-18 17:58 ` Nautiyal, Ankit K
2025-09-17 20:48 ` ✓ CI.KUnit: success for drm/i915/vrr: Hide icl/tgl idiosyncrasies better Patchwork
2025-09-17 21:28 ` ✓ Xe.CI.BAT: " Patchwork
2025-09-18 2:13 ` ✗ Xe.CI.Full: failure " Patchwork
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