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From: Ville Syrjala <ville.syrjala@linux.intel.com>
To: intel-gfx@lists.freedesktop.org
Cc: intel-xe@lists.freedesktop.org, Uma Shankar <uma.shankar@intel.com>
Subject: [PATCH v2 2/9] drm/i915: Reject modes with linetime > 64 usec
Date: Tue, 14 Oct 2025 22:18:01 +0300	[thread overview]
Message-ID: <20251014191808.12326-3-ville.syrjala@linux.intel.com> (raw)
In-Reply-To: <20251014191808.12326-1-ville.syrjala@linux.intel.com>

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

Reject modes whose linetime exceeds 64 usec.

First reason being that WM_LINETIME is limited to (nearly) 64 usec.

Additionally knowing the linetime is bounded will help with
determining whether overflows may be a concern during various
calculations.

I decided to round up, and accept the linetime==64 case. We use
various rounding directions for this in other parts of the code,
so I feel this provides the most consistent result all around.

Reviewed-by: Uma Shankar <uma.shankar@intel.com>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/display/intel_display.c | 8 ++++++++
 1 file changed, 8 insertions(+)

diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index d5b2612d4ec2..4395852e9641 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -7972,6 +7972,14 @@ enum drm_mode_status intel_mode_valid(struct drm_device *dev,
 	    mode->vtotal > vtotal_max)
 		return MODE_V_ILLEGAL;
 
+	/*
+	 * WM_LINETIME only goes up to (almost) 64 usec, and also
+	 * knowing that the linetime is always bounded will ease the
+	 * mind during various calculations.
+	 */
+	if (DIV_ROUND_UP(mode->htotal * 1000, mode->clock) > 64)
+		return MODE_H_ILLEGAL;
+
 	return MODE_OK;
 }
 
-- 
2.49.1


  parent reply	other threads:[~2025-10-14 19:18 UTC|newest]

Thread overview: 23+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2025-10-14 19:17 [PATCH v2 0/9] drm/i915/prefill: Introduce helpers for prefill latency calculations Ville Syrjala
2025-10-14 19:18 ` [PATCH v2 1/9] drm/i915/vblank: Add helper to get correct vblank length Ville Syrjala
2025-10-14 19:18 ` Ville Syrjala [this message]
2025-10-14 19:18 ` [PATCH v2 3/9] drm/i915/cdclk: Add prefill helpers for CDCLK Ville Syrjala
2025-10-14 19:18 ` [PATCH v2 4/9] drm/i915/cdclk: Add intel_cdclk_min_cdclk_for_prefill() Ville Syrjala
2025-10-14 19:18 ` [PATCH v2 5/9] drm/i915/dsc: Add prefill helper for DSC Ville Syrjala
2025-10-14 19:18 ` [PATCH v2 6/9] drm/i915/scaler: Add scaler prefill helpers Ville Syrjala
2025-10-15 11:23   ` Shankar, Uma
2025-10-15 12:51     ` Ville Syrjälä
2025-10-15 12:56   ` [PATCH v3 " Ville Syrjala
2025-10-14 19:18 ` [PATCH v2 7/9] drm/i915/wm: Add WM0 " Ville Syrjala
2025-10-14 19:18 ` [PATCH v2 8/9] drm/i915/prefill: Introduce skl_prefill.c Ville Syrjala
2025-10-14 19:18 ` [PATCH v2 9/9] drm/i915/wm: Use skl_prefill Ville Syrjala
2025-10-14 19:24 ` ✗ CI.checkpatch: warning for drm/i915/prefill: Introduce helpers for prefill latency calculations (rev2) Patchwork
2025-10-14 19:25 ` ✓ CI.KUnit: success " Patchwork
2025-10-14 19:43 ` ✗ CI.checksparse: warning " Patchwork
2025-10-14 20:05 ` ✓ Xe.CI.BAT: success " Patchwork
2025-10-15  6:42 ` ✗ Xe.CI.Full: failure " Patchwork
2025-10-15 20:58 ` ✗ CI.checkpatch: warning for drm/i915/prefill: Introduce helpers for prefill latency calculations (rev3) Patchwork
2025-10-15 21:00 ` ✓ CI.KUnit: success " Patchwork
2025-10-15 21:15 ` ✗ CI.checksparse: warning " Patchwork
2025-10-15 21:40 ` ✓ Xe.CI.BAT: success " Patchwork
2025-10-16  8:33 ` ✓ Xe.CI.Full: " Patchwork

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