[PATCH 00/32] drm/i915/display: Add initial support for Xe3p_LPD

[Gustavo Sousa <gustavo.sousa@intel.com>]

This series adds initial support for Xe3p_LPD, Intel's display
architecture with IP version 35.

This series contains basic enabling patches and does not provide
complete support for the display IP yet. More involved features, like
the new PHY implementation and ALPM will come as separate patch series.

Signed-off-by: Gustavo Sousa <gustavo.sousa@intel.com>
---
Ankit Nautiyal (1):
      drm/i915/xe3p_lpd: Drop support for interlace mode

Gustavo Sousa (12):
      drm/i915/display: Use braces for if-ladder in intel_bw_init_hw()
      drm/i915/dram: Add field ecc_impacting_de
      drm/i915/xe3p_lpd: Wait for AUX channel power status
      drm/i915/xe3p_lpd: Always apply level-0 watermark adjustment
      drm/i915/xe3p_lpd: Add CDCLK table
      drm/i915/xe3p_lpd: Load DMC firmware
      drm/i915/xe3p_lpd: Extend Wa_16025573575
      drm/i915/xe3p_lpd: Reload DMC MMIO for pipes C and D
      drm/i915/vbt: Add fields dedicated_external and dyn_port_over_tc
      drm/i915/power: Use intel_encoder_is_tc()
      drm/i915/display: Handle dedicated external ports in intel_encoder_is_tc()
      drm/i915/xe3p_lpd: Extend Type-C flow for static DDI allocation

Jouni Högander (1):
      drm/i915/xe3p_lpd: PSR SU minimum lines is 4

Juha-pekka Heikkila (1):
      drm/i915/xe3p_lpd: Don't allow odd ypan or ysize with semiplanar format

Luca Coelho (1):
      drm/i915/wm: don't use method1 in Xe3p_LPD onwards

Matt Atwood (1):
      drm/i915/xe3p_lpd: Update bandwidth parameters

Matt Roper (2):
      drm/xe/nvl: Define NVL-S platform
      drm/i915/xe3p_lpd: Drop north display reset option programming

Ravi Kumar Vodapalli (1):
      drm/i915/xe3p_lpd: Adapt to updates on MBUS_CTL/DBUF_CTL registers

Sai Teja Pottumuttu (8):
      drm/i915/xe3p_lpd: Add Xe3p_LPD display IP features
      drm/i915/xe3p_lpd: Expand bifield masks dbuf blocks fields
      drm/i915/xe3p_lpd: Support UINT16 formats
      drm/i915/xe3p_lpd: Extend FBC support to UINT16 formats
      drm/i915/xe3p_lpd: Horizontal flip support for linear surfaces
      drm/i915/xe3p_lpd: Underrun debuggability and error codes/hints
      drm/i915/xe3p_lpd: Remove gamma,csc bottom color checks
      drm/i915/nvls: Add NVL-S display support

Vinod Govindapillai (4):
      drm/i915/xe3p_lpd: Enable system caching for FBC
      drm/i915/xe3p_lpd: Introduce pixel normalizer config support
      drm/i915/xe3p_lpd: Add FBC support for FP16 formats
      drm/i915/xe3p_lpd: Enable pixel normalizer for fp16 formats for FBC

 drivers/gpu/drm/i915/display/intel_bios.c          |  20 ++-
 drivers/gpu/drm/i915/display/intel_bios.h          |   2 +
 drivers/gpu/drm/i915/display/intel_bw.c            |  48 ++++--
 drivers/gpu/drm/i915/display/intel_cdclk.c         |  44 +++++-
 drivers/gpu/drm/i915/display/intel_color.c         |  13 +-
 drivers/gpu/drm/i915/display/intel_ddi.c           |   7 +
 drivers/gpu/drm/i915/display/intel_display.c       |  33 ++++-
 .../gpu/drm/i915/display/intel_display_device.c    |   6 +
 .../gpu/drm/i915/display/intel_display_device.h    |   4 +-
 drivers/gpu/drm/i915/display/intel_display_power.c |   3 +
 .../drm/i915/display/intel_display_power_well.c    |  58 ++++++--
 drivers/gpu/drm/i915/display/intel_display_regs.h  |  51 ++++++-
 drivers/gpu/drm/i915/display/intel_display_types.h |   4 +
 drivers/gpu/drm/i915/display/intel_display_wa.c    |   3 +-
 drivers/gpu/drm/i915/display/intel_dmc.c           |  12 +-
 drivers/gpu/drm/i915/display/intel_fbc.c           | 126 +++++++++++++++-
 drivers/gpu/drm/i915/display/intel_fbc.h           |   1 +
 drivers/gpu/drm/i915/display/intel_fbc_regs.h      |   9 ++
 drivers/gpu/drm/i915/display/intel_fifo_underrun.c | 100 ++++++++++++-
 drivers/gpu/drm/i915/display/intel_plane.c         |   3 +
 drivers/gpu/drm/i915/display/intel_psr.c           |  25 ++++
 drivers/gpu/drm/i915/display/intel_tc.c            | 151 ++++++++++++++++++-
 drivers/gpu/drm/i915/display/intel_vbt_defs.h      |   7 +-
 drivers/gpu/drm/i915/display/skl_universal_plane.c | 162 +++++++++++++++------
 .../drm/i915/display/skl_universal_plane_regs.h    |  25 +++-
 drivers/gpu/drm/i915/display/skl_watermark.c       |  25 +++-
 drivers/gpu/drm/i915/display/skl_watermark_regs.h  |  12 +-
 drivers/gpu/drm/i915/i915_reg.h                    |   1 +
 drivers/gpu/drm/i915/soc/intel_dram.c              |   4 +
 drivers/gpu/drm/i915/soc/intel_dram.h              |   1 +
 drivers/gpu/drm/xe/xe_pci.c                        |   9 ++
 drivers/gpu/drm/xe/xe_platform_types.h             |   1 +
 include/drm/intel/pciids.h                         |   9 ++
 33 files changed, 861 insertions(+), 118 deletions(-)
---
base-commit: c6c2a6f0013cf24b117a1dd397c9e0530ff2f4cb
change-id: 20251014-xe3p_lpd-basic-enabling-eb4424698b44

Best regards,
--  
Gustavo Sousa <gustavo.sousa@intel.com>