From: Gustavo Sousa <gustavo.sousa@intel.com>
To: intel-xe@lists.freedesktop.org, intel-gfx@lists.freedesktop.org
Cc: "Ankit Nautiyal" <ankit.k.nautiyal@intel.com>,
"Dnyaneshwar Bhadane" <dnyaneshwar.bhadane@intel.com>,
"Gustavo Sousa" <gustavo.sousa@intel.com>,
"Jouni Högander" <jouni.hogander@intel.com>,
"Juha-pekka Heikkila" <juha-pekka.heikkila@intel.com>,
"Luca Coelho" <luciano.coelho@intel.com>,
"Lucas De Marchi" <lucas.demarchi@intel.com>,
"Matt Atwood" <matthew.s.atwood@intel.com>,
"Matt Roper" <matthew.d.roper@intel.com>,
"Ravi Kumar Vodapalli" <ravi.kumar.vodapalli@intel.com>,
"Sai Teja Pottumuttu" <sai.teja.pottumuttu@intel.com>,
"Shekhar Chauhan" <shekhar.chauhan@intel.com>,
"Vinod Govindapillai" <vinod.govindapillai@intel.com>
Subject: [PATCH 28/32] drm/i915/power: Use intel_encoder_is_tc()
Date: Wed, 15 Oct 2025 00:15:28 -0300 [thread overview]
Message-ID: <20251015-xe3p_lpd-basic-enabling-v1-28-d2d1e26520aa@intel.com> (raw)
In-Reply-To: <20251015-xe3p_lpd-basic-enabling-v1-0-d2d1e26520aa@intel.com>
Starting with Xe3p_LPD, when intel_phy_is_tc() returns true, it does
not necessarily mean that the port is connected to a PHY in the Type-C
subsystem. The reason is that there is now a VBT field called
dedicated_external that will indicate that a Type-C capable port is
connected to a (most likely) combo/dedicated PHY. When that's the case,
we must not do the extra programming required for Type-C connections.
In an upcoming change, we will modify intel_encoder_is_tc() to take the
VBT field dedicated_external into consideration. Update
intel_display_power_well.c to use that function instead of
intel_phy_is_tc().
Note that, even though icl_aux_power_well_{enable,disable} are not part
of Xe3p_LPD's display paths, we modify them anyway for uniformity.
Cc: Shekhar Chauhan <shekhar.chauhan@intel.com>
Signed-off-by: Gustavo Sousa <gustavo.sousa@intel.com>
---
.../drm/i915/display/intel_display_power_well.c | 26 +++++++++++++++-------
1 file changed, 18 insertions(+), 8 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display_power_well.c b/drivers/gpu/drm/i915/display/intel_display_power_well.c
index ba2552adb58b..e8200672dcf3 100644
--- a/drivers/gpu/drm/i915/display/intel_display_power_well.c
+++ b/drivers/gpu/drm/i915/display/intel_display_power_well.c
@@ -256,8 +256,9 @@ aux_ch_to_digital_port(struct intel_display *display,
return NULL;
}
-static enum phy icl_aux_pw_to_phy(struct intel_display *display,
- const struct i915_power_well *power_well)
+static struct intel_encoder *
+icl_aux_pw_to_encoder(struct intel_display *display,
+ const struct i915_power_well *power_well)
{
enum aux_ch aux_ch = icl_aux_pw_to_ch(power_well);
struct intel_digital_port *dig_port = aux_ch_to_digital_port(display, aux_ch);
@@ -269,7 +270,15 @@ static enum phy icl_aux_pw_to_phy(struct intel_display *display,
* as HDMI-only and routed to a combo PHY, the encoder either won't be
* present at all or it will not have an aux_ch assigned.
*/
- return dig_port ? intel_encoder_to_phy(&dig_port->base) : PHY_NONE;
+ return dig_port ? &dig_port->base : NULL;
+}
+
+static enum phy icl_aux_pw_to_phy(struct intel_display *display,
+ const struct i915_power_well *power_well)
+{
+ struct intel_encoder *encoder = icl_aux_pw_to_encoder(display, power_well);
+
+ return encoder ? intel_encoder_to_phy(encoder) : PHY_NONE;
}
static void hsw_wait_for_power_well_enable(struct intel_display *display,
@@ -568,9 +577,9 @@ static void
icl_aux_power_well_enable(struct intel_display *display,
struct i915_power_well *power_well)
{
- enum phy phy = icl_aux_pw_to_phy(display, power_well);
+ struct intel_encoder *encoder = icl_aux_pw_to_encoder(display, power_well);
- if (intel_phy_is_tc(display, phy))
+ if (encoder && intel_encoder_is_tc(encoder))
return icl_tc_phy_aux_power_well_enable(display, power_well);
else if (display->platform.icelake)
return icl_combo_phy_aux_power_well_enable(display,
@@ -583,9 +592,9 @@ static void
icl_aux_power_well_disable(struct intel_display *display,
struct i915_power_well *power_well)
{
- enum phy phy = icl_aux_pw_to_phy(display, power_well);
+ struct intel_encoder *encoder = icl_aux_pw_to_encoder(display, power_well);
- if (intel_phy_is_tc(display, phy))
+ if (encoder && intel_encoder_is_tc(encoder))
return hsw_power_well_disable(display, power_well);
else if (display->platform.icelake)
return icl_combo_phy_aux_power_well_disable(display,
@@ -1847,10 +1856,11 @@ tgl_tc_cold_off_power_well_is_enabled(struct intel_display *display,
static void xelpdp_aux_power_well_enable(struct intel_display *display,
struct i915_power_well *power_well)
{
+ struct intel_encoder *encoder = icl_aux_pw_to_encoder(display, power_well);
enum aux_ch aux_ch = i915_power_well_instance(power_well)->xelpdp.aux_ch;
enum phy phy = icl_aux_pw_to_phy(display, power_well);
- if (intel_phy_is_tc(display, phy))
+ if (encoder && intel_encoder_is_tc(encoder))
icl_tc_port_assert_ref_held(display, power_well,
aux_ch_to_digital_port(display, aux_ch));
--
2.51.0
next prev parent reply other threads:[~2025-10-15 3:18 UTC|newest]
Thread overview: 90+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-10-15 3:15 [PATCH 00/32] drm/i915/display: Add initial support for Xe3p_LPD Gustavo Sousa
2025-10-15 3:15 ` [PATCH 01/32] drm/xe/nvl: Define NVL-S platform Gustavo Sousa
2025-10-15 8:07 ` Shekhar Chauhan
2025-10-15 8:09 ` Shekhar Chauhan
2025-10-15 17:43 ` Lucas De Marchi
2025-10-15 3:15 ` [PATCH 02/32] drm/i915/xe3p_lpd: Add Xe3p_LPD display IP features Gustavo Sousa
2025-10-15 8:11 ` Shekhar Chauhan
2025-10-15 3:15 ` [PATCH 03/32] drm/i915/xe3p_lpd: Drop north display reset option programming Gustavo Sousa
2025-10-15 15:56 ` Matt Atwood
2025-10-15 3:15 ` [PATCH 04/32] drm/i915/display: Use braces for if-ladder in intel_bw_init_hw() Gustavo Sousa
2025-10-15 17:40 ` Matt Roper
2025-10-15 3:15 ` [PATCH 05/32] drm/i915/dram: Add field ecc_impacting_de Gustavo Sousa
2025-10-15 14:46 ` Jani Nikula
2025-10-15 15:54 ` Matt Atwood
2025-10-15 16:13 ` Gustavo Sousa
2025-10-15 16:20 ` Matt Atwood
2025-10-15 3:15 ` [PATCH 06/32] drm/i915/xe3p_lpd: Update bandwidth parameters Gustavo Sousa
2025-10-15 17:48 ` Matt Roper
2025-10-15 18:12 ` Gustavo Sousa
2025-10-15 19:12 ` Matt Roper
2025-10-15 19:51 ` Gustavo Sousa
2025-10-15 3:15 ` [PATCH 07/32] drm/i915/xe3p_lpd: Expand bifield masks dbuf blocks fields Gustavo Sousa
2025-10-15 17:55 ` Matt Roper
2025-10-15 3:15 ` [PATCH 08/32] drm/i915/xe3p_lpd: Support UINT16 formats Gustavo Sousa
2025-10-15 20:23 ` Matt Atwood
2025-10-15 20:55 ` Matt Atwood
2025-10-15 3:15 ` [PATCH 09/32] drm/i915/xe3p_lpd: Extend FBC support to " Gustavo Sousa
2025-10-15 3:15 ` [PATCH 10/32] drm/i915/xe3p_lpd: Horizontal flip support for linear surfaces Gustavo Sousa
2025-10-15 17:58 ` Matt Roper
2025-10-15 3:15 ` [PATCH 11/32] drm/i915/xe3p_lpd: Wait for AUX channel power status Gustavo Sousa
2025-10-15 3:15 ` [PATCH 12/32] drm/i915/xe3p_lpd: Underrun debuggability and error codes/hints Gustavo Sousa
2025-10-15 14:56 ` Jani Nikula
2025-10-15 15:01 ` Ville Syrjälä
2025-10-15 3:15 ` [PATCH 13/32] drm/i915/xe3p_lpd: Remove gamma,csc bottom color checks Gustavo Sousa
2025-10-17 6:02 ` Borah, Chaitanya Kumar
2025-10-15 3:15 ` [PATCH 14/32] drm/i915/xe3p_lpd: Adapt to updates on MBUS_CTL/DBUF_CTL registers Gustavo Sousa
2025-10-15 14:58 ` Jani Nikula
2025-10-16 20:33 ` Gustavo Sousa
2025-10-15 3:15 ` [PATCH 15/32] drm/i915/xe3p_lpd: Always apply level-0 watermark adjustment Gustavo Sousa
2025-10-16 20:53 ` Matt Atwood
2025-10-16 21:03 ` Ville Syrjälä
2025-10-17 18:38 ` Gustavo Sousa
2025-10-15 3:15 ` [PATCH 16/32] drm/i915/xe3p_lpd: Add CDCLK table Gustavo Sousa
2025-10-15 17:39 ` Matt Roper
2025-10-15 17:43 ` Matt Atwood
2025-10-15 3:15 ` [PATCH 17/32] drm/i915/xe3p_lpd: Load DMC firmware Gustavo Sousa
2025-10-15 16:22 ` Matt Atwood
2025-10-15 3:15 ` [PATCH 18/32] drm/i915/xe3p_lpd: Drop support for interlace mode Gustavo Sousa
2025-10-15 4:21 ` Kandpal, Suraj
2025-10-15 3:15 ` [PATCH 19/32] drm/i915/xe3p_lpd: PSR SU minimum lines is 4 Gustavo Sousa
2025-10-15 15:00 ` Jani Nikula
2025-10-15 16:18 ` Gustavo Sousa
2025-10-15 3:15 ` [PATCH 20/32] drm/i915/xe3p_lpd: Enable system caching for FBC Gustavo Sousa
2025-10-15 3:15 ` [PATCH 21/32] drm/i915/xe3p_lpd: Extend Wa_16025573575 Gustavo Sousa
2025-10-15 8:13 ` Shekhar Chauhan
2025-10-15 3:15 ` [PATCH 22/32] drm/i915/xe3p_lpd: Don't allow odd ypan or ysize with semiplanar format Gustavo Sousa
2025-10-16 20:50 ` Matt Atwood
2025-10-15 3:15 ` [PATCH 23/32] drm/i915/xe3p_lpd: Reload DMC MMIO for pipes C and D Gustavo Sousa
2025-10-15 17:47 ` Matt Atwood
2025-10-15 3:15 ` [PATCH 24/32] drm/i915/xe3p_lpd: Introduce pixel normalizer config support Gustavo Sousa
2025-10-15 15:11 ` Jani Nikula
2025-10-20 9:35 ` Govindapillai, Vinod
2025-10-15 3:15 ` [PATCH 25/32] drm/i915/xe3p_lpd: Add FBC support for FP16 formats Gustavo Sousa
2025-10-15 15:13 ` Jani Nikula
2025-10-15 3:15 ` [PATCH 26/32] drm/i915/xe3p_lpd: Enable pixel normalizer for fp16 formats for FBC Gustavo Sousa
2025-10-15 15:15 ` Jani Nikula
2025-10-15 3:15 ` [PATCH 27/32] drm/i915/vbt: Add fields dedicated_external and dyn_port_over_tc Gustavo Sousa
2025-10-15 15:24 ` Jani Nikula
2025-10-17 19:52 ` Gustavo Sousa
2025-10-20 7:45 ` Jani Nikula
2025-10-20 12:43 ` Gustavo Sousa
2025-10-15 15:29 ` Jani Nikula
2025-10-17 20:20 ` Gustavo Sousa
2025-10-21 8:32 ` Jani Nikula
2025-10-15 3:15 ` Gustavo Sousa [this message]
2025-10-15 4:20 ` [PATCH 28/32] drm/i915/power: Use intel_encoder_is_tc() Kandpal, Suraj
2025-10-15 3:15 ` [PATCH 29/32] drm/i915/display: Handle dedicated external ports in intel_encoder_is_tc() Gustavo Sousa
2025-10-15 15:33 ` Jani Nikula
2025-10-15 16:25 ` Gustavo Sousa
2025-10-21 8:36 ` Jani Nikula
2025-10-15 3:15 ` [PATCH 30/32] drm/i915/wm: don't use method1 in Xe3p_LPD onwards Gustavo Sousa
2025-10-15 8:02 ` Shekhar Chauhan
2025-10-21 20:19 ` Gustavo Sousa
2025-10-15 3:15 ` [PATCH 31/32] drm/i915/xe3p_lpd: Extend Type-C flow for static DDI allocation Gustavo Sousa
2025-10-15 3:15 ` [PATCH 32/32] drm/i915/nvls: Add NVL-S display support Gustavo Sousa
2025-10-15 3:29 ` ✗ CI.checkpatch: warning for drm/i915/display: Add initial support for Xe3p_LPD Patchwork
2025-10-15 3:30 ` ✓ CI.KUnit: success " Patchwork
2025-10-15 3:45 ` ✗ CI.checksparse: warning " Patchwork
2025-10-15 4:15 ` ✓ Xe.CI.BAT: success " Patchwork
2025-10-15 13:44 ` ✗ Xe.CI.Full: failure " Patchwork
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