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From: Gustavo Sousa <gustavo.sousa@intel.com>
To: intel-xe@lists.freedesktop.org, intel-gfx@lists.freedesktop.org
Cc: "Ankit Nautiyal" <ankit.k.nautiyal@intel.com>,
	"Dnyaneshwar Bhadane" <dnyaneshwar.bhadane@intel.com>,
	"Gustavo Sousa" <gustavo.sousa@intel.com>,
	"Jouni Högander" <jouni.hogander@intel.com>,
	"Juha-pekka Heikkila" <juha-pekka.heikkila@intel.com>,
	"Luca Coelho" <luciano.coelho@intel.com>,
	"Lucas De Marchi" <lucas.demarchi@intel.com>,
	"Matt Atwood" <matthew.s.atwood@intel.com>,
	"Matt Roper" <matthew.d.roper@intel.com>,
	"Ravi Kumar Vodapalli" <ravi.kumar.vodapalli@intel.com>,
	"Sai Teja Pottumuttu" <sai.teja.pottumuttu@intel.com>,
	"Shekhar Chauhan" <shekhar.chauhan@intel.com>,
	"Vinod Govindapillai" <vinod.govindapillai@intel.com>
Subject: [PATCH 06/32] drm/i915/xe3p_lpd: Update bandwidth parameters
Date: Wed, 15 Oct 2025 00:15:06 -0300	[thread overview]
Message-ID: <20251015-xe3p_lpd-basic-enabling-v1-6-d2d1e26520aa@intel.com> (raw)
In-Reply-To: <20251015-xe3p_lpd-basic-enabling-v1-0-d2d1e26520aa@intel.com>

From: Matt Atwood <matthew.s.atwood@intel.com>

Bandwidth parameters for Xe3p_LPD are basically the same as for Xe3_LPD.
However, now Xe3p_LPD has the ecc_impacting_de field, which could impact
how the derating is defined.

For the cases where that field is true, we use xe3p_lpd_ecc_sa_info,
similarly to what was done for Xe2_HPD.  Note, however, that Bspec
specifies the ECC derating value only for GDDR memory.  For now, we just
re-use the value that was defined for Xe2_HPD, namely 45.  We need to
confirm with the hardware team what would be the correct value(s) to use
for the ECC case.

Bspec: 68859, 69131
Signed-off-by: Matt Atwood <matthew.s.atwood@intel.com>
Signed-off-by: Gustavo Sousa <gustavo.sousa@intel.com>
---
 drivers/gpu/drm/i915/display/intel_bw.c | 21 ++++++++++++++++++++-
 1 file changed, 20 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/display/intel_bw.c b/drivers/gpu/drm/i915/display/intel_bw.c
index 8f5b86cd91b6..f0940ff9d19b 100644
--- a/drivers/gpu/drm/i915/display/intel_bw.c
+++ b/drivers/gpu/drm/i915/display/intel_bw.c
@@ -461,6 +461,20 @@ static const struct intel_sa_info xe3lpd_3002_sa_info = {
 	.derating = 10,
 };
 
+static const struct intel_sa_info xe3p_lpd_ecc_sa_info = {
+	.deburst = 32,
+	.deprogbwlimit = 65, /* GB/s */
+	.displayrtids = 256,
+	/*
+	 * FIXME: The Bspec only shows that derating for ECC should be 45 for
+	 * GDDR memory and does not mention other types of memory.  For now, we
+	 * just re-use that value, but we need to confirm whether that is
+	 * correct or if there are different values depending on the memory
+	 * type.
+	 */
+	.derating = 45,
+};
+
 static int icl_get_bw_info(struct intel_display *display,
 			   const struct dram_info *dram_info,
 			   const struct intel_sa_info *sa)
@@ -812,7 +826,12 @@ void intel_bw_init_hw(struct intel_display *display)
 	if (!HAS_DISPLAY(display))
 		return;
 
-	if (DISPLAY_VERx100(display) >= 3002) {
+	if (DISPLAY_VER(display) >= 35) {
+		if (dram_info->ecc_impacting_de)
+			tgl_get_bw_info(display, dram_info, &xe3p_lpd_ecc_sa_info);
+		else
+			tgl_get_bw_info(display, dram_info, &xe3lpd_sa_info);
+	} else if (DISPLAY_VERx100(display) >= 3002) {
 		tgl_get_bw_info(display, dram_info, &xe3lpd_3002_sa_info);
 	} else if (DISPLAY_VER(display) >= 30) {
 		tgl_get_bw_info(display, dram_info, &xe3lpd_sa_info);

-- 
2.51.0


  parent reply	other threads:[~2025-10-15  3:17 UTC|newest]

Thread overview: 90+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2025-10-15  3:15 [PATCH 00/32] drm/i915/display: Add initial support for Xe3p_LPD Gustavo Sousa
2025-10-15  3:15 ` [PATCH 01/32] drm/xe/nvl: Define NVL-S platform Gustavo Sousa
2025-10-15  8:07   ` Shekhar Chauhan
2025-10-15  8:09     ` Shekhar Chauhan
2025-10-15 17:43       ` Lucas De Marchi
2025-10-15  3:15 ` [PATCH 02/32] drm/i915/xe3p_lpd: Add Xe3p_LPD display IP features Gustavo Sousa
2025-10-15  8:11   ` Shekhar Chauhan
2025-10-15  3:15 ` [PATCH 03/32] drm/i915/xe3p_lpd: Drop north display reset option programming Gustavo Sousa
2025-10-15 15:56   ` Matt Atwood
2025-10-15  3:15 ` [PATCH 04/32] drm/i915/display: Use braces for if-ladder in intel_bw_init_hw() Gustavo Sousa
2025-10-15 17:40   ` Matt Roper
2025-10-15  3:15 ` [PATCH 05/32] drm/i915/dram: Add field ecc_impacting_de Gustavo Sousa
2025-10-15 14:46   ` Jani Nikula
2025-10-15 15:54     ` Matt Atwood
2025-10-15 16:13     ` Gustavo Sousa
2025-10-15 16:20       ` Matt Atwood
2025-10-15  3:15 ` Gustavo Sousa [this message]
2025-10-15 17:48   ` [PATCH 06/32] drm/i915/xe3p_lpd: Update bandwidth parameters Matt Roper
2025-10-15 18:12     ` Gustavo Sousa
2025-10-15 19:12       ` Matt Roper
2025-10-15 19:51         ` Gustavo Sousa
2025-10-15  3:15 ` [PATCH 07/32] drm/i915/xe3p_lpd: Expand bifield masks dbuf blocks fields Gustavo Sousa
2025-10-15 17:55   ` Matt Roper
2025-10-15  3:15 ` [PATCH 08/32] drm/i915/xe3p_lpd: Support UINT16 formats Gustavo Sousa
2025-10-15 20:23   ` Matt Atwood
2025-10-15 20:55     ` Matt Atwood
2025-10-15  3:15 ` [PATCH 09/32] drm/i915/xe3p_lpd: Extend FBC support to " Gustavo Sousa
2025-10-15  3:15 ` [PATCH 10/32] drm/i915/xe3p_lpd: Horizontal flip support for linear surfaces Gustavo Sousa
2025-10-15 17:58   ` Matt Roper
2025-10-15  3:15 ` [PATCH 11/32] drm/i915/xe3p_lpd: Wait for AUX channel power status Gustavo Sousa
2025-10-15  3:15 ` [PATCH 12/32] drm/i915/xe3p_lpd: Underrun debuggability and error codes/hints Gustavo Sousa
2025-10-15 14:56   ` Jani Nikula
2025-10-15 15:01   ` Ville Syrjälä
2025-10-15  3:15 ` [PATCH 13/32] drm/i915/xe3p_lpd: Remove gamma,csc bottom color checks Gustavo Sousa
2025-10-17  6:02   ` Borah, Chaitanya Kumar
2025-10-15  3:15 ` [PATCH 14/32] drm/i915/xe3p_lpd: Adapt to updates on MBUS_CTL/DBUF_CTL registers Gustavo Sousa
2025-10-15 14:58   ` Jani Nikula
2025-10-16 20:33     ` Gustavo Sousa
2025-10-15  3:15 ` [PATCH 15/32] drm/i915/xe3p_lpd: Always apply level-0 watermark adjustment Gustavo Sousa
2025-10-16 20:53   ` Matt Atwood
2025-10-16 21:03   ` Ville Syrjälä
2025-10-17 18:38     ` Gustavo Sousa
2025-10-15  3:15 ` [PATCH 16/32] drm/i915/xe3p_lpd: Add CDCLK table Gustavo Sousa
2025-10-15 17:39   ` Matt Roper
2025-10-15 17:43   ` Matt Atwood
2025-10-15  3:15 ` [PATCH 17/32] drm/i915/xe3p_lpd: Load DMC firmware Gustavo Sousa
2025-10-15 16:22   ` Matt Atwood
2025-10-15  3:15 ` [PATCH 18/32] drm/i915/xe3p_lpd: Drop support for interlace mode Gustavo Sousa
2025-10-15  4:21   ` Kandpal, Suraj
2025-10-15  3:15 ` [PATCH 19/32] drm/i915/xe3p_lpd: PSR SU minimum lines is 4 Gustavo Sousa
2025-10-15 15:00   ` Jani Nikula
2025-10-15 16:18     ` Gustavo Sousa
2025-10-15  3:15 ` [PATCH 20/32] drm/i915/xe3p_lpd: Enable system caching for FBC Gustavo Sousa
2025-10-15  3:15 ` [PATCH 21/32] drm/i915/xe3p_lpd: Extend Wa_16025573575 Gustavo Sousa
2025-10-15  8:13   ` Shekhar Chauhan
2025-10-15  3:15 ` [PATCH 22/32] drm/i915/xe3p_lpd: Don't allow odd ypan or ysize with semiplanar format Gustavo Sousa
2025-10-16 20:50   ` Matt Atwood
2025-10-15  3:15 ` [PATCH 23/32] drm/i915/xe3p_lpd: Reload DMC MMIO for pipes C and D Gustavo Sousa
2025-10-15 17:47   ` Matt Atwood
2025-10-15  3:15 ` [PATCH 24/32] drm/i915/xe3p_lpd: Introduce pixel normalizer config support Gustavo Sousa
2025-10-15 15:11   ` Jani Nikula
2025-10-20  9:35     ` Govindapillai, Vinod
2025-10-15  3:15 ` [PATCH 25/32] drm/i915/xe3p_lpd: Add FBC support for FP16 formats Gustavo Sousa
2025-10-15 15:13   ` Jani Nikula
2025-10-15  3:15 ` [PATCH 26/32] drm/i915/xe3p_lpd: Enable pixel normalizer for fp16 formats for FBC Gustavo Sousa
2025-10-15 15:15   ` Jani Nikula
2025-10-15  3:15 ` [PATCH 27/32] drm/i915/vbt: Add fields dedicated_external and dyn_port_over_tc Gustavo Sousa
2025-10-15 15:24   ` Jani Nikula
2025-10-17 19:52     ` Gustavo Sousa
2025-10-20  7:45       ` Jani Nikula
2025-10-20 12:43         ` Gustavo Sousa
2025-10-15 15:29   ` Jani Nikula
2025-10-17 20:20     ` Gustavo Sousa
2025-10-21  8:32       ` Jani Nikula
2025-10-15  3:15 ` [PATCH 28/32] drm/i915/power: Use intel_encoder_is_tc() Gustavo Sousa
2025-10-15  4:20   ` Kandpal, Suraj
2025-10-15  3:15 ` [PATCH 29/32] drm/i915/display: Handle dedicated external ports in intel_encoder_is_tc() Gustavo Sousa
2025-10-15 15:33   ` Jani Nikula
2025-10-15 16:25     ` Gustavo Sousa
2025-10-21  8:36       ` Jani Nikula
2025-10-15  3:15 ` [PATCH 30/32] drm/i915/wm: don't use method1 in Xe3p_LPD onwards Gustavo Sousa
2025-10-15  8:02   ` Shekhar Chauhan
2025-10-21 20:19     ` Gustavo Sousa
2025-10-15  3:15 ` [PATCH 31/32] drm/i915/xe3p_lpd: Extend Type-C flow for static DDI allocation Gustavo Sousa
2025-10-15  3:15 ` [PATCH 32/32] drm/i915/nvls: Add NVL-S display support Gustavo Sousa
2025-10-15  3:29 ` ✗ CI.checkpatch: warning for drm/i915/display: Add initial support for Xe3p_LPD Patchwork
2025-10-15  3:30 ` ✓ CI.KUnit: success " Patchwork
2025-10-15  3:45 ` ✗ CI.checksparse: warning " Patchwork
2025-10-15  4:15 ` ✓ Xe.CI.BAT: success " Patchwork
2025-10-15 13:44 ` ✗ Xe.CI.Full: failure " Patchwork

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