[PATCH v2 0/7] drm/i915/dp: Fix panel replay in DSC mode

[PATCH v2 0/7] drm/i915/dp: Fix panel replay in DSC mode

[Imre Deak]

This is v2 of [1], addressing Jouni's review comments and fixing the
logic to derermine if DSC is enabled on a UHBR DP-MST link. The latter
can't depend on whether FEC is enabled or not on the link, since FEC is
always (i.e. regardless of DSC) enabled on a UHBR link; so this version
adds an explicit way of tracking whether DSC is enabled for any CRTC on
the link and uses this during a CRTC's state computation to decide if
Panel Replay can be enabled or not for any CRTC on the link.

Cc: Jouni Högander <jouni.hogander@intel.com>

[1] https://lore.kernel.org/all/20251008094108.88242-1-imre.deak@intel.com

Imre Deak (7):
  drm/i915/dsc: Add helper to enable the DSC configuration for a CRTC
  drm/i915/dp: Ensure the FEC state stays disabled for UHBR links
  drm/i915/dp: Export helper to determine if FEC on non-UHBR links is
    required
  drm/i915/dp_mst: Reuse the DP-SST helper function to compute FEC
    config
  drm/i915/dp_mst: Track DSC enabled status on the MST link
  drm/i915/dp_mst: Recompute all MST link CRTCs if DSC gets enabled on
    the link
  drm/i915/dp: Fix panel replay when DSC is enabled

 drivers/gpu/drm/i915/display/icl_dsi.c        |  2 +-
 drivers/gpu/drm/i915/display/intel_display.c  |  2 +-
 .../drm/i915/display/intel_display_types.h    | 11 +++
 drivers/gpu/drm/i915/display/intel_dp.c       | 34 ++++---
 drivers/gpu/drm/i915/display/intel_dp.h       |  2 +
 drivers/gpu/drm/i915/display/intel_dp_mst.c   | 31 ++++---
 drivers/gpu/drm/i915/display/intel_link_bw.c  | 17 ++--
 drivers/gpu/drm/i915/display/intel_link_bw.h  |  2 +-
 drivers/gpu/drm/i915/display/intel_psr.c      | 93 ++++++++++++++++++-
 drivers/gpu/drm/i915/display/intel_vdsc.c     | 16 ++++
 drivers/gpu/drm/i915/display/intel_vdsc.h     |  2 +
 11 files changed, 171 insertions(+), 41 deletions(-)

-- 
2.49.1

[PATCH v2 1/7] drm/i915/dsc: Add helper to enable the DSC configuration for a CRTC

[Imre Deak]

Add a helper to enable the DSC compression configuration for a CRTC.
Follow-up changes will introduce tracking for the same DSC state on the
whole link, which will need to be set whenever DSC is enabled for the
CRTC. Also, according to the above, when querying the DSC state on the
link, both the CRTC's and the link's DSC state must be considered.

Setting the DSC configuration for a CRTC and querying the DSC
configuration for the link (added by follow-up changes) is better done
via helper functions based on the above, prepare for that here.

Signed-off-by: Imre Deak <imre.deak@intel.com>
---
 drivers/gpu/drm/i915/display/icl_dsi.c    | 2 +-
 drivers/gpu/drm/i915/display/intel_dp.c   | 3 ++-
 drivers/gpu/drm/i915/display/intel_vdsc.c | 5 +++++
 drivers/gpu/drm/i915/display/intel_vdsc.h | 1 +
 4 files changed, 9 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/icl_dsi.c b/drivers/gpu/drm/i915/display/icl_dsi.c
index 37faa8f19f6e4..297368ff42a5e 100644
--- a/drivers/gpu/drm/i915/display/icl_dsi.c
+++ b/drivers/gpu/drm/i915/display/icl_dsi.c
@@ -1655,7 +1655,7 @@ static int gen11_dsi_dsc_compute_config(struct intel_encoder *encoder,
 	if (ret)
 		return ret;
 
-	crtc_state->dsc.compression_enable = true;
+	intel_dsc_enable_on_crtc(crtc_state);
 
 	return 0;
 }
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index a723e846321fd..1d3ca1970f25f 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -2475,7 +2475,8 @@ int intel_dp_dsc_compute_config(struct intel_dp *intel_dp,
 		return ret;
 	}
 
-	pipe_config->dsc.compression_enable = true;
+	intel_dsc_enable_on_crtc(pipe_config);
+
 	drm_dbg_kms(display->drm, "DP DSC computed with Input Bpp = %d "
 		    "Compressed Bpp = " FXP_Q4_FMT " Slice Count = %d\n",
 		    pipe_config->pipe_bpp,
diff --git a/drivers/gpu/drm/i915/display/intel_vdsc.c b/drivers/gpu/drm/i915/display/intel_vdsc.c
index 8e799e225af17..64a1e9f0a1893 100644
--- a/drivers/gpu/drm/i915/display/intel_vdsc.c
+++ b/drivers/gpu/drm/i915/display/intel_vdsc.c
@@ -372,6 +372,11 @@ int intel_dsc_compute_params(struct intel_crtc_state *pipe_config)
 	return 0;
 }
 
+void intel_dsc_enable_on_crtc(struct intel_crtc_state *crtc_state)
+{
+	crtc_state->dsc.compression_enable = true;
+}
+
 enum intel_display_power_domain
 intel_dsc_power_domain(struct intel_crtc *crtc, enum transcoder cpu_transcoder)
 {
diff --git a/drivers/gpu/drm/i915/display/intel_vdsc.h b/drivers/gpu/drm/i915/display/intel_vdsc.h
index 9e2812f99dd74..240bef82d3576 100644
--- a/drivers/gpu/drm/i915/display/intel_vdsc.h
+++ b/drivers/gpu/drm/i915/display/intel_vdsc.h
@@ -20,6 +20,7 @@ void intel_uncompressed_joiner_enable(const struct intel_crtc_state *crtc_state)
 void intel_dsc_enable(const struct intel_crtc_state *crtc_state);
 void intel_dsc_disable(const struct intel_crtc_state *crtc_state);
 int intel_dsc_compute_params(struct intel_crtc_state *pipe_config);
+void intel_dsc_enable_on_crtc(struct intel_crtc_state *crtc_state);
 void intel_dsc_get_config(struct intel_crtc_state *crtc_state);
 enum intel_display_power_domain
 intel_dsc_power_domain(struct intel_crtc *crtc, enum transcoder cpu_transcoder);
-- 
2.49.1

[PATCH v2 2/7] drm/i915/dp: Ensure the FEC state stays disabled for UHBR links

[Imre Deak]

Atm, in the DP SST case the FEC state is computed before
intel_crtc_state::port_clock is initialized, hence intel_dp_is_uhbr()
will always return false and the FEC state will be always computed
assuming a non-UHBR link.

This happens to work, since the FEC state is recomputed later in
intel_dp_mtp_tu_compute_config(), where port_clock will be set already,
so intel_crtc_state::fec_enable will be reset as expected for UHBR. This
also depends on link rates being tried in an increasing order (i.e. from
non-UHBR -> UHBR link rates) in dsc_compute_link_config(), thus
intel_crtc_state::fec_enable being set for the non-UHBR rates and
getting reset for the first UHBR rate as expected.

A follow-up change will reuse intel_dp_fec_compute_config() for the DP
MST state computation, prepare for that here, making sure that the
function determines the correct intel_crtc_state::fec_enable=false state
for UHBR link rates based on the above.

The DP SST and MST state computation should be further unified to avoid
computing/setting the intel_crtc_state::fec_enable state multiple times,
but that's left for a follow-up change. For now add only code comments
about this.

Signed-off-by: Imre Deak <imre.deak@intel.com>
---
 drivers/gpu/drm/i915/display/intel_dp.c     | 10 +++++++---
 drivers/gpu/drm/i915/display/intel_dp_mst.c |  5 +++++
 2 files changed, 12 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index 1d3ca1970f25f..b523c4e661412 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -2368,6 +2368,9 @@ static int intel_edp_dsc_compute_pipe_bpp(struct intel_dp *intel_dp,
 static void intel_dp_fec_compute_config(struct intel_dp *intel_dp,
 					struct intel_crtc_state *crtc_state)
 {
+	if (intel_dp_is_uhbr(crtc_state))
+		return;
+
 	if (crtc_state->fec_enable)
 		return;
 
@@ -2379,9 +2382,6 @@ static void intel_dp_fec_compute_config(struct intel_dp *intel_dp,
 	if (intel_dp_is_edp(intel_dp))
 		return;
 
-	if (intel_dp_is_uhbr(crtc_state))
-		return;
-
 	crtc_state->fec_enable = true;
 }
 
@@ -2400,6 +2400,10 @@ int intel_dp_dsc_compute_config(struct intel_dp *intel_dp,
 	bool is_mst = intel_crtc_has_type(pipe_config, INTEL_OUTPUT_DP_MST);
 	int ret;
 
+	/*
+	 * FIXME: set the FEC enabled state once pipe_config->port_clock is
+	 * already known, so the UHBR/non-UHBR mode can be determined.
+	 */
 	intel_dp_fec_compute_config(intel_dp, pipe_config);
 
 	if (!intel_dp_dsc_supports_format(connector, pipe_config->output_format))
diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c b/drivers/gpu/drm/i915/display/intel_dp_mst.c
index f2266b2653046..27e952a67c343 100644
--- a/drivers/gpu/drm/i915/display/intel_dp_mst.c
+++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c
@@ -293,6 +293,11 @@ int intel_dp_mtp_tu_compute_config(struct intel_dp *intel_dp,
 		mst_stream_update_slots(crtc_state, mst_state);
 	}
 
+	/*
+	 * NOTE: The following must reset crtc_state->fec_enable for UHBR/DSC
+	 * after it was set by intel_dp_dsc_compute_config() ->
+	 * intel_dp_fec_compute_config().
+	 */
 	if (dsc) {
 		if (!intel_dp_supports_fec(intel_dp, connector, crtc_state))
 			return -EINVAL;
-- 
2.49.1

[PATCH v2 3/7] drm/i915/dp: Export helper to determine if FEC on non-UHBR links is required

[Imre Deak]

Export the helper function to determine if FEC is required on a non-UHBR
(8b10b) SST or MST link. A follow up change will take this into use for
MST as well.

While at it determine the output type from the CRTC state, which allows
dropping the intel_dp argument. Also make the function return the
required FEC state, instead of setting this in the CRTC state, which
allows only querying this requirement, without changing the state.

Also rename the function to intel_dp_needs_8b10b_fec(), to clarify that
the function determines if FEC is required on an 8b10b link (on 128b132b
links FEC is always enabled by the HW implicitly, so the function will
return false for that case).

Signed-off-by: Imre Deak <imre.deak@intel.com>
---
 drivers/gpu/drm/i915/display/intel_dp.c     | 21 +++++++++++++--------
 drivers/gpu/drm/i915/display/intel_dp.h     |  2 ++
 drivers/gpu/drm/i915/display/intel_dp_mst.c |  2 +-
 3 files changed, 16 insertions(+), 9 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index b523c4e661412..3ffb015004c54 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -2365,24 +2365,29 @@ static int intel_edp_dsc_compute_pipe_bpp(struct intel_dp *intel_dp,
 	return 0;
 }
 
-static void intel_dp_fec_compute_config(struct intel_dp *intel_dp,
-					struct intel_crtc_state *crtc_state)
+/*
+ * Return whether FEC must be enabled for 8b10b SST or MST links. On 128b132b
+ * links FEC is always enabled implicitly by the HW, so this function returns
+ * false for that case.
+ */
+bool intel_dp_needs_8b10b_fec(const struct intel_crtc_state *crtc_state,
+			      bool dsc_enabled_on_crtc)
 {
 	if (intel_dp_is_uhbr(crtc_state))
-		return;
+		return false;
 
 	if (crtc_state->fec_enable)
-		return;
+		return true;
 
 	/*
 	 * Though eDP v1.5 supports FEC with DSC, unlike DP, it is optional.
 	 * Since, FEC is a bandwidth overhead, continue to not enable it for
 	 * eDP. Until, there is a good reason to do so.
 	 */
-	if (intel_dp_is_edp(intel_dp))
-		return;
+	if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP))
+		return false;
 
-	crtc_state->fec_enable = true;
+	return dsc_enabled_on_crtc;
 }
 
 int intel_dp_dsc_compute_config(struct intel_dp *intel_dp,
@@ -2404,7 +2409,7 @@ int intel_dp_dsc_compute_config(struct intel_dp *intel_dp,
 	 * FIXME: set the FEC enabled state once pipe_config->port_clock is
 	 * already known, so the UHBR/non-UHBR mode can be determined.
 	 */
-	intel_dp_fec_compute_config(intel_dp, pipe_config);
+	pipe_config->fec_enable = intel_dp_needs_8b10b_fec(pipe_config, true);
 
 	if (!intel_dp_dsc_supports_format(connector, pipe_config->output_format))
 		return -EINVAL;
diff --git a/drivers/gpu/drm/i915/display/intel_dp.h b/drivers/gpu/drm/i915/display/intel_dp.h
index b379443e0211e..55059bd5c7efb 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.h
+++ b/drivers/gpu/drm/i915/display/intel_dp.h
@@ -73,6 +73,8 @@ void intel_dp_encoder_flush_work(struct drm_encoder *encoder);
 int intel_dp_compute_config(struct intel_encoder *encoder,
 			    struct intel_crtc_state *pipe_config,
 			    struct drm_connector_state *conn_state);
+bool intel_dp_needs_8b10b_fec(const struct intel_crtc_state *crtc_state,
+			      bool dsc_enabled_on_crtc);
 int intel_dp_dsc_compute_config(struct intel_dp *intel_dp,
 				struct intel_crtc_state *pipe_config,
 				struct drm_connector_state *conn_state,
diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c b/drivers/gpu/drm/i915/display/intel_dp_mst.c
index 27e952a67c343..d0590b5ffffd7 100644
--- a/drivers/gpu/drm/i915/display/intel_dp_mst.c
+++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c
@@ -296,7 +296,7 @@ int intel_dp_mtp_tu_compute_config(struct intel_dp *intel_dp,
 	/*
 	 * NOTE: The following must reset crtc_state->fec_enable for UHBR/DSC
 	 * after it was set by intel_dp_dsc_compute_config() ->
-	 * intel_dp_fec_compute_config().
+	 * intel_dp_needs_8b10b_fec().
 	 */
 	if (dsc) {
 		if (!intel_dp_supports_fec(intel_dp, connector, crtc_state))
-- 
2.49.1

[PATCH v2 4/7] drm/i915/dp_mst: Reuse the DP-SST helper function to compute FEC config

[Imre Deak]

Reuse the DP-SST helper to compute the state for the FEC enabled state
for DP-MST as well.

Signed-off-by: Imre Deak <imre.deak@intel.com>
---
 drivers/gpu/drm/i915/display/intel_dp_mst.c | 10 ++++------
 1 file changed, 4 insertions(+), 6 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c b/drivers/gpu/drm/i915/display/intel_dp_mst.c
index d0590b5ffffd7..0cbb4c3a8e22f 100644
--- a/drivers/gpu/drm/i915/display/intel_dp_mst.c
+++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c
@@ -298,12 +298,10 @@ int intel_dp_mtp_tu_compute_config(struct intel_dp *intel_dp,
 	 * after it was set by intel_dp_dsc_compute_config() ->
 	 * intel_dp_needs_8b10b_fec().
 	 */
-	if (dsc) {
-		if (!intel_dp_supports_fec(intel_dp, connector, crtc_state))
-			return -EINVAL;
-
-		crtc_state->fec_enable = !intel_dp_is_uhbr(crtc_state);
-	}
+	crtc_state->fec_enable = intel_dp_needs_8b10b_fec(crtc_state, dsc);
+	if (crtc_state->fec_enable &&
+	    !intel_dp_supports_fec(intel_dp, connector, crtc_state))
+		return -EINVAL;
 
 	max_dpt_bpp_x16 = fxp_q4_from_int(intel_dp_mst_max_dpt_bpp(crtc_state, dsc));
 	if (max_dpt_bpp_x16 && max_bpp_x16 > max_dpt_bpp_x16) {
-- 
2.49.1

[PATCH v2 5/7] drm/i915/dp_mst: Track DSC enabled status on the MST link

[Imre Deak]

Track whether DSC is enabled on any CRTC on a link. On DP-SST (and DSI)
this will always match the CRTC's DSC state, those links having only a
single stream (aka CRTC). For instance, on DP-MST if DSC is enabled for
CRTC#0, but disabled for CRTC#1, the DSC/FEC state for these CRTCs will
be as follows:

CRTC#0:
 - compression_enable = true
 - compression_enabled_on_link = true
 - fec_enable = true for 8b10b, false for 128b132b

CRTC#1:
 - compression_enable = false
 - compression_enabled_on_link = true
 - fec_enable = true for 8b10b, false for 128b132b

This patch only sets compression_enabled_on_link for CRTC#0 above and
enables FEC on CRTC#0 if DSC was enabled on any other CRTC on the 8b10b
MST link. A follow-up change will make sure that the state of all the
CRTCs (CRTC#1 above) on an MST link is recomputed if DSC gets enabled on
any CRTC, setting compression_enabled_on_link and fec_enable for these.

Signed-off-by: Imre Deak <imre.deak@intel.com>
---
 drivers/gpu/drm/i915/display/intel_display_types.h |  2 ++
 drivers/gpu/drm/i915/display/intel_dp.c            |  2 +-
 drivers/gpu/drm/i915/display/intel_vdsc.c          | 11 +++++++++++
 drivers/gpu/drm/i915/display/intel_vdsc.h          |  1 +
 4 files changed, 15 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
index 87b7cec35320f..58308146697ff 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -1277,6 +1277,8 @@ struct intel_crtc_state {
 
 	/* Display Stream compression state */
 	struct {
+		/* Only used for state computation, not read out from the HW. */
+		bool compression_enabled_on_link;
 		bool compression_enable;
 		int num_streams;
 		/* Compressed Bpp in U6.4 format (first 4 bits for fractional part) */
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index 3ffb015004c54..8ba931204cb52 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -2387,7 +2387,7 @@ bool intel_dp_needs_8b10b_fec(const struct intel_crtc_state *crtc_state,
 	if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP))
 		return false;
 
-	return dsc_enabled_on_crtc;
+	return dsc_enabled_on_crtc || intel_dsc_enabled_on_link(crtc_state);
 }
 
 int intel_dp_dsc_compute_config(struct intel_dp *intel_dp,
diff --git a/drivers/gpu/drm/i915/display/intel_vdsc.c b/drivers/gpu/drm/i915/display/intel_vdsc.c
index 64a1e9f0a1893..316753205ac45 100644
--- a/drivers/gpu/drm/i915/display/intel_vdsc.c
+++ b/drivers/gpu/drm/i915/display/intel_vdsc.c
@@ -374,9 +374,20 @@ int intel_dsc_compute_params(struct intel_crtc_state *pipe_config)
 
 void intel_dsc_enable_on_crtc(struct intel_crtc_state *crtc_state)
 {
+	crtc_state->dsc.compression_enabled_on_link = true;
 	crtc_state->dsc.compression_enable = true;
 }
 
+bool intel_dsc_enabled_on_link(const struct intel_crtc_state *crtc_state)
+{
+	struct intel_display *display = to_intel_display(crtc_state);
+
+	drm_WARN_ON(display->drm, crtc_state->dsc.compression_enable &&
+		    !crtc_state->dsc.compression_enabled_on_link);
+
+	return crtc_state->dsc.compression_enabled_on_link;
+}
+
 enum intel_display_power_domain
 intel_dsc_power_domain(struct intel_crtc *crtc, enum transcoder cpu_transcoder)
 {
diff --git a/drivers/gpu/drm/i915/display/intel_vdsc.h b/drivers/gpu/drm/i915/display/intel_vdsc.h
index 240bef82d3576..9c52ece0027c3 100644
--- a/drivers/gpu/drm/i915/display/intel_vdsc.h
+++ b/drivers/gpu/drm/i915/display/intel_vdsc.h
@@ -21,6 +21,7 @@ void intel_dsc_enable(const struct intel_crtc_state *crtc_state);
 void intel_dsc_disable(const struct intel_crtc_state *crtc_state);
 int intel_dsc_compute_params(struct intel_crtc_state *pipe_config);
 void intel_dsc_enable_on_crtc(struct intel_crtc_state *crtc_state);
+bool intel_dsc_enabled_on_link(const struct intel_crtc_state *crtc_state);
 void intel_dsc_get_config(struct intel_crtc_state *crtc_state);
 enum intel_display_power_domain
 intel_dsc_power_domain(struct intel_crtc *crtc, enum transcoder cpu_transcoder);
-- 
2.49.1

[PATCH v2 6/7] drm/i915/dp_mst: Recompute all MST link CRTCs if DSC gets enabled on the link

[Imre Deak]

The state of all the CRTCs on an MST link must be recomputed, if DSC
gets enabled on any of the CRTCs on the link. For instance an MST
docking station's Panel Replay capability may depend on whether DSC is
enabled on any of the dock's streams (aka CRTCs). To assist the Panel
Replay state computation for a CRTC based on the above, track in the
CRTC state if DSC is enabled on any CRTC on an MST link.

The intel_link_bw_limits::force_fec_pipes mask is used for a reason
similar to the above: enable FEC on all CRTCs of a non-UHBR (8b10b) MST
link if DSC is enabled on any of the link's CRTCs. The FEC enabled state
for a CRTC doesn't indicate if DSC is enabled on a UHBR MST link (FEC is
always enabled by the HW for UHBR, hence it's not tracked by the
intel_crtc_state::fec_enable flag for such links, where this flag is
always false).

Based on the above, to be able to determine the DSC state on both
non-UHBR and UHBR MST links, track the more generic DSC-enabled-on-link
state (instead of the FEC-enabled-on-link state) for each CRTC in
intel_link_bw_limits.

Signed-off-by: Imre Deak <imre.deak@intel.com>
---
 drivers/gpu/drm/i915/display/intel_display.c |  2 +-
 drivers/gpu/drm/i915/display/intel_dp_mst.c  | 16 ++++++++--------
 drivers/gpu/drm/i915/display/intel_link_bw.c | 17 +++++++++--------
 drivers/gpu/drm/i915/display/intel_link_bw.h |  2 +-
 4 files changed, 19 insertions(+), 18 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index d5b2612d4ec25..64c0cf34b7af3 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -4601,7 +4601,7 @@ intel_modeset_pipe_config(struct intel_atomic_state *state,
 	if (ret)
 		return ret;
 
-	crtc_state->fec_enable = limits->force_fec_pipes & BIT(crtc->pipe);
+	crtc_state->dsc.compression_enabled_on_link = limits->link_dsc_pipes & BIT(crtc->pipe);
 	crtc_state->max_link_bpp_x16 = limits->max_bpp_x16[crtc->pipe];
 
 	if (crtc_state->pipe_bpp > fxp_q4_to_int(crtc_state->max_link_bpp_x16)) {
diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c b/drivers/gpu/drm/i915/display/intel_dp_mst.c
index 0cbb4c3a8e22f..a845b2612a3fa 100644
--- a/drivers/gpu/drm/i915/display/intel_dp_mst.c
+++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c
@@ -814,14 +814,14 @@ static u8 get_pipes_downstream_of_mst_port(struct intel_atomic_state *state,
 	return mask;
 }
 
-static int intel_dp_mst_check_fec_change(struct intel_atomic_state *state,
+static int intel_dp_mst_check_dsc_change(struct intel_atomic_state *state,
 					 struct drm_dp_mst_topology_mgr *mst_mgr,
 					 struct intel_link_bw_limits *limits)
 {
 	struct intel_display *display = to_intel_display(state);
 	struct intel_crtc *crtc;
 	u8 mst_pipe_mask;
-	u8 fec_pipe_mask = 0;
+	u8 dsc_pipe_mask = 0;
 	int ret;
 
 	mst_pipe_mask = get_pipes_downstream_of_mst_port(state, mst_mgr, NULL);
@@ -834,16 +834,16 @@ static int intel_dp_mst_check_fec_change(struct intel_atomic_state *state,
 		if (drm_WARN_ON(display->drm, !crtc_state))
 			return -EINVAL;
 
-		if (crtc_state->fec_enable)
-			fec_pipe_mask |= BIT(crtc->pipe);
+		if (intel_dsc_enabled_on_link(crtc_state))
+			dsc_pipe_mask |= BIT(crtc->pipe);
 	}
 
-	if (!fec_pipe_mask || mst_pipe_mask == fec_pipe_mask)
+	if (!dsc_pipe_mask || mst_pipe_mask == dsc_pipe_mask)
 		return 0;
 
-	limits->force_fec_pipes |= mst_pipe_mask;
+	limits->link_dsc_pipes |= mst_pipe_mask;
 
-	ret = intel_modeset_pipes_in_mask_early(state, "MST FEC",
+	ret = intel_modeset_pipes_in_mask_early(state, "MST DSC",
 						mst_pipe_mask);
 
 	return ret ? : -EAGAIN;
@@ -897,7 +897,7 @@ int intel_dp_mst_atomic_check_link(struct intel_atomic_state *state,
 	int i;
 
 	for_each_new_mst_mgr_in_state(&state->base, mgr, mst_state, i) {
-		ret = intel_dp_mst_check_fec_change(state, mgr, limits);
+		ret = intel_dp_mst_check_dsc_change(state, mgr, limits);
 		if (ret)
 			return ret;
 
diff --git a/drivers/gpu/drm/i915/display/intel_link_bw.c b/drivers/gpu/drm/i915/display/intel_link_bw.c
index f52dee0ea412f..d2862de894fa7 100644
--- a/drivers/gpu/drm/i915/display/intel_link_bw.c
+++ b/drivers/gpu/drm/i915/display/intel_link_bw.c
@@ -20,6 +20,7 @@
 #include "intel_dp_tunnel.h"
 #include "intel_fdi.h"
 #include "intel_link_bw.h"
+#include "intel_vdsc.h"
 
 static int get_forced_link_bpp_x16(struct intel_atomic_state *state,
 				   const struct intel_crtc *crtc)
@@ -55,7 +56,7 @@ void intel_link_bw_init_limits(struct intel_atomic_state *state,
 	struct intel_display *display = to_intel_display(state);
 	enum pipe pipe;
 
-	limits->force_fec_pipes = 0;
+	limits->link_dsc_pipes = 0;
 	limits->bpp_limit_reached_pipes = 0;
 	for_each_pipe(display, pipe) {
 		struct intel_crtc *crtc = intel_crtc_for_pipe(display, pipe);
@@ -65,8 +66,8 @@ void intel_link_bw_init_limits(struct intel_atomic_state *state,
 
 		if (state->base.duplicated && crtc_state) {
 			limits->max_bpp_x16[pipe] = crtc_state->max_link_bpp_x16;
-			if (crtc_state->fec_enable)
-				limits->force_fec_pipes |= BIT(pipe);
+			if (intel_dsc_enabled_on_link(crtc_state))
+				limits->link_dsc_pipes |= BIT(pipe);
 		} else {
 			limits->max_bpp_x16[pipe] = INT_MAX;
 		}
@@ -265,10 +266,10 @@ assert_link_limit_change_valid(struct intel_display *display,
 	bool bpps_changed = false;
 	enum pipe pipe;
 
-	/* FEC can't be forced off after it was forced on. */
+	/* DSC can't be disabled after it was enabled. */
 	if (drm_WARN_ON(display->drm,
-			(old_limits->force_fec_pipes & new_limits->force_fec_pipes) !=
-			old_limits->force_fec_pipes))
+			(old_limits->link_dsc_pipes & new_limits->link_dsc_pipes) !=
+			old_limits->link_dsc_pipes))
 		return false;
 
 	for_each_pipe(display, pipe) {
@@ -286,8 +287,8 @@ assert_link_limit_change_valid(struct intel_display *display,
 	/* At least one limit must change. */
 	if (drm_WARN_ON(display->drm,
 			!bpps_changed &&
-			new_limits->force_fec_pipes ==
-			old_limits->force_fec_pipes))
+			new_limits->link_dsc_pipes ==
+			old_limits->link_dsc_pipes))
 		return false;
 
 	return true;
diff --git a/drivers/gpu/drm/i915/display/intel_link_bw.h b/drivers/gpu/drm/i915/display/intel_link_bw.h
index 95ab7c50c61d0..cb18e171037cf 100644
--- a/drivers/gpu/drm/i915/display/intel_link_bw.h
+++ b/drivers/gpu/drm/i915/display/intel_link_bw.h
@@ -15,7 +15,7 @@ struct intel_connector;
 struct intel_crtc_state;
 
 struct intel_link_bw_limits {
-	u8 force_fec_pipes;
+	u8 link_dsc_pipes;
 	u8 bpp_limit_reached_pipes;
 	/* in 1/16 bpp units */
 	int max_bpp_x16[I915_MAX_PIPES];
-- 
2.49.1

[PATCH v2 7/7] drm/i915/dp: Fix panel replay when DSC is enabled

[Imre Deak]

Prevent enabling panel replay if the sink doesn't support this due to
DSC being enabled.

Panel replay has two modes, updating full frames or only selected
regions of the frame. If the sink doesn't support Panel Replay in full
frame update mode with DSC prevent Panel Replay completely if DSC is
enabled. If the sink doesn't support Panel Replay only in the selective
update mode while DSC is enabled, it will still support Panel Replay in
the full frame update mode, so only prevent selective updates in this
case.

v2:
- Use Panel Replay instead of PR in debug prints. (Jouni)
- Rebase on change tracking the link DSC state in the crtc state.

Cc: Jouni Högander <jouni.hogander@intel.com>
Closes: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/14869
Signed-off-by: Imre Deak <imre.deak@intel.com>
---
 .../drm/i915/display/intel_display_types.h    |  9 ++
 drivers/gpu/drm/i915/display/intel_dp.c       |  2 +
 drivers/gpu/drm/i915/display/intel_psr.c      | 93 ++++++++++++++++++-
 3 files changed, 99 insertions(+), 5 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
index 58308146697ff..67386daecc16d 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -955,6 +955,12 @@ struct intel_csc_matrix {
 	u16 postoff[3];
 };
 
+enum intel_panel_replay_dsc_support {
+	INTEL_DP_PANEL_REPLAY_DSC_NOT_SUPPORTED,
+	INTEL_DP_PANEL_REPLAY_DSC_FULL_FRAME_ONLY,
+	INTEL_DP_PANEL_REPLAY_DSC_SELECTIVE_UPDATE,
+};
+
 struct intel_crtc_state {
 	/*
 	 * uapi (drm) state. This is the software state shown to userspace.
@@ -1133,6 +1139,8 @@ struct intel_crtc_state {
 	bool has_panel_replay;
 	bool wm_level_disabled;
 	bool pkg_c_latency_used;
+	/* Only used for state verification. */
+	enum intel_panel_replay_dsc_support panel_replay_dsc_support;
 	u32 dc3co_exitline;
 	u16 su_y_granularity;
 	u8 active_non_psr_pipes;
@@ -1704,6 +1712,7 @@ struct intel_psr {
 	bool source_panel_replay_support;
 	bool sink_panel_replay_support;
 	bool sink_panel_replay_su_support;
+	enum intel_panel_replay_dsc_support sink_panel_replay_dsc_support;
 	bool panel_replay_enabled;
 	u32 dc3co_exitline;
 	u32 dc3co_exit_delay;
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index 8ba931204cb52..799e69a65e712 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -6053,6 +6053,8 @@ intel_dp_detect(struct drm_connector *_connector,
 		memset(connector->dp.dsc_dpcd, 0, sizeof(connector->dp.dsc_dpcd));
 		intel_dp->psr.sink_panel_replay_support = false;
 		intel_dp->psr.sink_panel_replay_su_support = false;
+		intel_dp->psr.sink_panel_replay_dsc_support =
+			INTEL_DP_PANEL_REPLAY_DSC_NOT_SUPPORTED;
 
 		intel_dp_mst_disconnect(intel_dp);
 
diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c
index 2131473cead6d..c266807f5d36f 100644
--- a/drivers/gpu/drm/i915/display/intel_psr.c
+++ b/drivers/gpu/drm/i915/display/intel_psr.c
@@ -29,6 +29,7 @@
 #include <drm/drm_vblank.h>
 
 #include "i915_reg.h"
+#include "i915_utils.h"
 #include "intel_alpm.h"
 #include "intel_atomic.h"
 #include "intel_crtc.h"
@@ -50,6 +51,7 @@
 #include "intel_snps_phy.h"
 #include "intel_step.h"
 #include "intel_vblank.h"
+#include "intel_vdsc.h"
 #include "intel_vrr.h"
 #include "skl_universal_plane.h"
 
@@ -580,6 +582,44 @@ static void intel_dp_get_su_granularity(struct intel_dp *intel_dp)
 	intel_dp->psr.su_y_granularity = y;
 }
 
+static enum intel_panel_replay_dsc_support
+compute_pr_dsc_support(struct intel_dp *intel_dp)
+{
+	u8 pr_dsc_mode;
+	u8 val;
+
+	val = intel_dp->pr_dpcd[INTEL_PR_DPCD_INDEX(DP_PANEL_REPLAY_CAP_CAPABILITY)];
+	pr_dsc_mode = REG_FIELD_GET8(DP_PANEL_REPLAY_DSC_DECODE_CAPABILITY_IN_PR_MASK, val);
+
+	switch (pr_dsc_mode) {
+	case DP_DSC_DECODE_CAPABILITY_IN_PR_FULL_FRAME_ONLY:
+		return INTEL_DP_PANEL_REPLAY_DSC_FULL_FRAME_ONLY;
+	case DP_DSC_DECODE_CAPABILITY_IN_PR_SUPPORTED:
+		return INTEL_DP_PANEL_REPLAY_DSC_SELECTIVE_UPDATE;
+	default:
+		MISSING_CASE(pr_dsc_mode);
+		fallthrough;
+	case DP_DSC_DECODE_CAPABILITY_IN_PR_NOT_SUPPORTED:
+	case DP_DSC_DECODE_CAPABILITY_IN_PR_RESERVED:
+		return INTEL_DP_PANEL_REPLAY_DSC_NOT_SUPPORTED;
+	}
+}
+
+static const char *panel_replay_dsc_support_str(enum intel_panel_replay_dsc_support dsc_support)
+{
+	switch (dsc_support) {
+	case INTEL_DP_PANEL_REPLAY_DSC_NOT_SUPPORTED:
+		return "not supported";
+	case INTEL_DP_PANEL_REPLAY_DSC_FULL_FRAME_ONLY:
+		return "full frame only";
+	case INTEL_DP_PANEL_REPLAY_DSC_SELECTIVE_UPDATE:
+		return "selective update";
+	default:
+		MISSING_CASE(dsc_support);
+		return "n/a";
+	};
+}
+
 static void _panel_replay_init_dpcd(struct intel_dp *intel_dp)
 {
 	struct intel_display *display = to_intel_display(intel_dp);
@@ -615,10 +655,13 @@ static void _panel_replay_init_dpcd(struct intel_dp *intel_dp)
 	    DP_PANEL_REPLAY_SU_SUPPORT)
 		intel_dp->psr.sink_panel_replay_su_support = true;
 
+	intel_dp->psr.sink_panel_replay_dsc_support = compute_pr_dsc_support(intel_dp);
+
 	drm_dbg_kms(display->drm,
-		    "Panel replay %sis supported by panel\n",
+		    "Panel replay %sis supported by panel (in DSC mode: %s)\n",
 		    intel_dp->psr.sink_panel_replay_su_support ?
-		    "selective_update " : "");
+		    "selective_update " : "",
+		    panel_replay_dsc_support_str(intel_dp->psr.sink_panel_replay_dsc_support));
 }
 
 static void _psr_init_dpcd(struct intel_dp *intel_dp)
@@ -1537,9 +1580,21 @@ static bool intel_sel_update_config_valid(struct intel_dp *intel_dp,
 		goto unsupported;
 	}
 
-	if (crtc_state->has_panel_replay && (DISPLAY_VER(display) < 14 ||
-					     !intel_dp->psr.sink_panel_replay_su_support))
-		goto unsupported;
+	if (crtc_state->has_panel_replay) {
+		if (DISPLAY_VER(display) < 14)
+			goto unsupported;
+
+		if (!intel_dp->psr.sink_panel_replay_su_support)
+			goto unsupported;
+
+		if (intel_dsc_enabled_on_link(crtc_state) &&
+		    intel_dp->psr.sink_panel_replay_dsc_support !=
+		    INTEL_DP_PANEL_REPLAY_DSC_SELECTIVE_UPDATE) {
+			drm_dbg_kms(display->drm,
+				    "Selective update with Panel Replay not enabled because it's not supported with DSC\n");
+			goto unsupported;
+		}
+	}
 
 	if (crtc_state->crc_enabled) {
 		drm_dbg_kms(display->drm,
@@ -1616,6 +1671,14 @@ _panel_replay_compute_config(struct intel_dp *intel_dp,
 		return false;
 	}
 
+	if (intel_dsc_enabled_on_link(crtc_state) &&
+	    intel_dp->psr.sink_panel_replay_dsc_support ==
+	    INTEL_DP_PANEL_REPLAY_DSC_NOT_SUPPORTED) {
+		drm_dbg_kms(display->drm,
+			    "Panel Replay not enabled because it's not supported with DSC\n");
+		return false;
+	}
+
 	if (!intel_dp_is_edp(intel_dp))
 		return true;
 
@@ -1696,6 +1759,8 @@ void intel_psr_compute_config(struct intel_dp *intel_dp,
 		return;
 	}
 
+	/* Only used for state verification. */
+	crtc_state->panel_replay_dsc_support = intel_dp->psr.sink_panel_replay_dsc_support;
 	crtc_state->has_panel_replay = _panel_replay_compute_config(intel_dp,
 								    crtc_state,
 								    conn_state);
@@ -2955,6 +3020,20 @@ void intel_psr_pre_plane_update(struct intel_atomic_state *state,
 	}
 }
 
+static void
+verify_panel_replay_dsc_state(const struct intel_crtc_state *crtc_state)
+{
+	struct intel_display *display = to_intel_display(crtc_state);
+
+	if (!crtc_state->has_panel_replay)
+		return;
+
+	drm_WARN_ON(display->drm,
+		    intel_dsc_enabled_on_link(crtc_state) &&
+		    crtc_state->panel_replay_dsc_support ==
+		    INTEL_DP_PANEL_REPLAY_DSC_NOT_SUPPORTED);
+}
+
 void intel_psr_post_plane_update(struct intel_atomic_state *state,
 				 struct intel_crtc *crtc)
 {
@@ -2966,6 +3045,8 @@ void intel_psr_post_plane_update(struct intel_atomic_state *state,
 	if (!crtc_state->has_psr)
 		return;
 
+	verify_panel_replay_dsc_state(crtc_state);
+
 	for_each_intel_encoder_mask_with_psr(state->base.dev, encoder,
 					     crtc_state->uapi.encoder_mask) {
 		struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
@@ -3995,6 +4076,8 @@ static void intel_psr_sink_capability(struct intel_dp *intel_dp,
 	seq_printf(m, ", Panel Replay = %s", str_yes_no(psr->sink_panel_replay_support));
 	seq_printf(m, ", Panel Replay Selective Update = %s",
 		   str_yes_no(psr->sink_panel_replay_su_support));
+	seq_printf(m, ", Panel Replay DSC support = %s",
+		   panel_replay_dsc_support_str(psr->sink_panel_replay_dsc_support));
 	if (intel_dp->pr_dpcd[INTEL_PR_DPCD_INDEX(DP_PANEL_REPLAY_CAP_SUPPORT)] &
 	    DP_PANEL_REPLAY_EARLY_TRANSPORT_SUPPORT)
 		seq_printf(m, " (Early Transport)");
-- 
2.49.1

✓ CI.KUnit: success for drm/i915/dp: Fix panel replay in DSC mode (rev2)

[Patchwork]

== Series Details ==

Series: drm/i915/dp: Fix panel replay in DSC mode (rev2)
URL   : https://patchwork.freedesktop.org/series/155586/
State : success

== Summary ==

+ trap cleanup EXIT
+ /kernel/tools/testing/kunit/kunit.py run --kunitconfig /kernel/drivers/gpu/drm/xe/.kunitconfig
[01:51:12] Configuring KUnit Kernel ...
Generating .config ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
[01:51:17] Building KUnit Kernel ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
Building with:
$ make all compile_commands.json scripts_gdb ARCH=um O=.kunit --jobs=48
[01:51:47] Starting KUnit Kernel (1/1)...
[01:51:47] ============================================================
Running tests with:
$ .kunit/linux kunit.enable=1 mem=1G console=tty kunit_shutdown=halt
[01:51:47] ================== guc_buf (11 subtests) ===================
[01:51:47] [PASSED] test_smallest
[01:51:47] [PASSED] test_largest
[01:51:47] [PASSED] test_granular
[01:51:47] [PASSED] test_unique
[01:51:47] [PASSED] test_overlap
[01:51:47] [PASSED] test_reusable
[01:51:47] [PASSED] test_too_big
[01:51:47] [PASSED] test_flush
[01:51:47] [PASSED] test_lookup
[01:51:47] [PASSED] test_data
[01:51:47] [PASSED] test_class
[01:51:47] ===================== [PASSED] guc_buf =====================
[01:51:47] =================== guc_dbm (7 subtests) ===================
[01:51:47] [PASSED] test_empty
[01:51:47] [PASSED] test_default
[01:51:47] ======================== test_size  ========================
[01:51:47] [PASSED] 4
[01:51:47] [PASSED] 8
[01:51:47] [PASSED] 32
[01:51:47] [PASSED] 256
[01:51:47] ==================== [PASSED] test_size ====================
[01:51:47] ======================= test_reuse  ========================
[01:51:47] [PASSED] 4
[01:51:47] [PASSED] 8
[01:51:47] [PASSED] 32
[01:51:47] [PASSED] 256
[01:51:47] =================== [PASSED] test_reuse ====================
[01:51:47] =================== test_range_overlap  ====================
[01:51:47] [PASSED] 4
[01:51:47] [PASSED] 8
[01:51:47] [PASSED] 32
[01:51:47] [PASSED] 256
[01:51:47] =============== [PASSED] test_range_overlap ================
[01:51:47] =================== test_range_compact  ====================
[01:51:47] [PASSED] 4
[01:51:47] [PASSED] 8
[01:51:47] [PASSED] 32
[01:51:47] [PASSED] 256
[01:51:47] =============== [PASSED] test_range_compact ================
[01:51:47] ==================== test_range_spare  =====================
[01:51:47] [PASSED] 4
[01:51:47] [PASSED] 8
[01:51:47] [PASSED] 32
[01:51:47] [PASSED] 256
[01:51:47] ================ [PASSED] test_range_spare =================
[01:51:47] ===================== [PASSED] guc_dbm =====================
[01:51:47] =================== guc_idm (6 subtests) ===================
[01:51:47] [PASSED] bad_init
[01:51:47] [PASSED] no_init
[01:51:47] [PASSED] init_fini
[01:51:47] [PASSED] check_used
[01:51:47] [PASSED] check_quota
[01:51:47] [PASSED] check_all
[01:51:47] ===================== [PASSED] guc_idm =====================
[01:51:47] ================== no_relay (3 subtests) ===================
[01:51:47] [PASSED] xe_drops_guc2pf_if_not_ready
[01:51:47] [PASSED] xe_drops_guc2vf_if_not_ready
[01:51:47] [PASSED] xe_rejects_send_if_not_ready
[01:51:47] ==================== [PASSED] no_relay =====================
[01:51:47] ================== pf_relay (14 subtests) ==================
[01:51:47] [PASSED] pf_rejects_guc2pf_too_short
[01:51:47] [PASSED] pf_rejects_guc2pf_too_long
[01:51:47] [PASSED] pf_rejects_guc2pf_no_payload
[01:51:47] [PASSED] pf_fails_no_payload
[01:51:47] [PASSED] pf_fails_bad_origin
[01:51:47] [PASSED] pf_fails_bad_type
[01:51:47] [PASSED] pf_txn_reports_error
[01:51:47] [PASSED] pf_txn_sends_pf2guc
[01:51:47] [PASSED] pf_sends_pf2guc
[01:51:47] [SKIPPED] pf_loopback_nop
[01:51:47] [SKIPPED] pf_loopback_echo
[01:51:47] [SKIPPED] pf_loopback_fail
[01:51:47] [SKIPPED] pf_loopback_busy
[01:51:47] [SKIPPED] pf_loopback_retry
[01:51:47] ==================== [PASSED] pf_relay =====================
[01:51:47] ================== vf_relay (3 subtests) ===================
[01:51:47] [PASSED] vf_rejects_guc2vf_too_short
[01:51:47] [PASSED] vf_rejects_guc2vf_too_long
[01:51:47] [PASSED] vf_rejects_guc2vf_no_payload
[01:51:47] ==================== [PASSED] vf_relay =====================
[01:51:47] ===================== lmtt (1 subtest) =====================
[01:51:47] ======================== test_ops  =========================
[01:51:47] [PASSED] 2-level
[01:51:47] [PASSED] multi-level
[01:51:47] ==================== [PASSED] test_ops =====================
[01:51:47] ====================== [PASSED] lmtt =======================
[01:51:47] ================= pf_service (11 subtests) =================
[01:51:47] [PASSED] pf_negotiate_any
[01:51:47] [PASSED] pf_negotiate_base_match
[01:51:47] [PASSED] pf_negotiate_base_newer
[01:51:47] [PASSED] pf_negotiate_base_next
[01:51:47] [SKIPPED] pf_negotiate_base_older
[01:51:47] [PASSED] pf_negotiate_base_prev
[01:51:47] [PASSED] pf_negotiate_latest_match
[01:51:47] [PASSED] pf_negotiate_latest_newer
[01:51:47] [PASSED] pf_negotiate_latest_next
[01:51:47] [SKIPPED] pf_negotiate_latest_older
[01:51:47] [SKIPPED] pf_negotiate_latest_prev
[01:51:47] =================== [PASSED] pf_service ====================
[01:51:47] ================= xe_guc_g2g (2 subtests) ==================
[01:51:47] ============== xe_live_guc_g2g_kunit_default  ==============
[01:51:47] ========= [SKIPPED] xe_live_guc_g2g_kunit_default ==========
[01:51:47] ============== xe_live_guc_g2g_kunit_allmem  ===============
[01:51:47] ========== [SKIPPED] xe_live_guc_g2g_kunit_allmem ==========
[01:51:47] =================== [SKIPPED] xe_guc_g2g ===================
[01:51:47] =================== xe_mocs (2 subtests) ===================
[01:51:47] ================ xe_live_mocs_kernel_kunit  ================
[01:51:47] =========== [SKIPPED] xe_live_mocs_kernel_kunit ============
[01:51:47] ================ xe_live_mocs_reset_kunit  =================
[01:51:47] ============ [SKIPPED] xe_live_mocs_reset_kunit ============
[01:51:47] ==================== [SKIPPED] xe_mocs =====================
[01:51:47] ================= xe_migrate (2 subtests) ==================
[01:51:47] ================= xe_migrate_sanity_kunit  =================
[01:51:47] ============ [SKIPPED] xe_migrate_sanity_kunit =============
[01:51:47] ================== xe_validate_ccs_kunit  ==================
[01:51:47] ============= [SKIPPED] xe_validate_ccs_kunit ==============
[01:51:47] =================== [SKIPPED] xe_migrate ===================
[01:51:47] ================== xe_dma_buf (1 subtest) ==================
[01:51:47] ==================== xe_dma_buf_kunit  =====================
[01:51:47] ================ [SKIPPED] xe_dma_buf_kunit ================
[01:51:47] =================== [SKIPPED] xe_dma_buf ===================
[01:51:47] ================= xe_bo_shrink (1 subtest) =================
[01:51:47] =================== xe_bo_shrink_kunit  ====================
[01:51:47] =============== [SKIPPED] xe_bo_shrink_kunit ===============
[01:51:47] ================== [SKIPPED] xe_bo_shrink ==================
[01:51:47] ==================== xe_bo (2 subtests) ====================
[01:51:47] ================== xe_ccs_migrate_kunit  ===================
[01:51:47] ============== [SKIPPED] xe_ccs_migrate_kunit ==============
[01:51:47] ==================== xe_bo_evict_kunit  ====================
[01:51:47] =============== [SKIPPED] xe_bo_evict_kunit ================
[01:51:47] ===================== [SKIPPED] xe_bo ======================
[01:51:47] ==================== args (11 subtests) ====================
[01:51:47] [PASSED] count_args_test
[01:51:47] [PASSED] call_args_example
[01:51:47] [PASSED] call_args_test
[01:51:47] [PASSED] drop_first_arg_example
[01:51:47] [PASSED] drop_first_arg_test
[01:51:47] [PASSED] first_arg_example
[01:51:47] [PASSED] first_arg_test
[01:51:47] [PASSED] last_arg_example
[01:51:47] [PASSED] last_arg_test
[01:51:47] [PASSED] pick_arg_example
[01:51:47] [PASSED] sep_comma_example
[01:51:47] ====================== [PASSED] args =======================
[01:51:47] =================== xe_pci (3 subtests) ====================
[01:51:47] ==================== check_graphics_ip  ====================
[01:51:47] [PASSED] 12.00 Xe_LP
[01:51:47] [PASSED] 12.10 Xe_LP+
[01:51:47] [PASSED] 12.55 Xe_HPG
[01:51:47] [PASSED] 12.60 Xe_HPC
[01:51:47] [PASSED] 12.70 Xe_LPG
[01:51:47] [PASSED] 12.71 Xe_LPG
[01:51:47] [PASSED] 12.74 Xe_LPG+
[01:51:47] [PASSED] 20.01 Xe2_HPG
[01:51:47] [PASSED] 20.02 Xe2_HPG
[01:51:47] [PASSED] 20.04 Xe2_LPG
[01:51:47] [PASSED] 30.00 Xe3_LPG
[01:51:47] [PASSED] 30.01 Xe3_LPG
[01:51:47] [PASSED] 30.03 Xe3_LPG
[01:51:47] ================ [PASSED] check_graphics_ip ================
[01:51:47] ===================== check_media_ip  ======================
[01:51:47] [PASSED] 12.00 Xe_M
[01:51:47] [PASSED] 12.55 Xe_HPM
[01:51:47] [PASSED] 13.00 Xe_LPM+
[01:51:47] [PASSED] 13.01 Xe2_HPM
[01:51:47] [PASSED] 20.00 Xe2_LPM
[01:51:47] [PASSED] 30.00 Xe3_LPM
[01:51:47] [PASSED] 30.02 Xe3_LPM
[01:51:47] ================= [PASSED] check_media_ip ==================
[01:51:47] ================= check_platform_gt_count  =================
[01:51:47] [PASSED] 0x9A60 (TIGERLAKE)
[01:51:47] [PASSED] 0x9A68 (TIGERLAKE)
[01:51:47] [PASSED] 0x9A70 (TIGERLAKE)
[01:51:47] [PASSED] 0x9A40 (TIGERLAKE)
[01:51:47] [PASSED] 0x9A49 (TIGERLAKE)
[01:51:47] [PASSED] 0x9A59 (TIGERLAKE)
[01:51:47] [PASSED] 0x9A78 (TIGERLAKE)
[01:51:47] [PASSED] 0x9AC0 (TIGERLAKE)
[01:51:47] [PASSED] 0x9AC9 (TIGERLAKE)
[01:51:47] [PASSED] 0x9AD9 (TIGERLAKE)
[01:51:47] [PASSED] 0x9AF8 (TIGERLAKE)
[01:51:47] [PASSED] 0x4C80 (ROCKETLAKE)
[01:51:47] [PASSED] 0x4C8A (ROCKETLAKE)
[01:51:47] [PASSED] 0x4C8B (ROCKETLAKE)
[01:51:47] [PASSED] 0x4C8C (ROCKETLAKE)
[01:51:47] [PASSED] 0x4C90 (ROCKETLAKE)
[01:51:47] [PASSED] 0x4C9A (ROCKETLAKE)
[01:51:47] [PASSED] 0x4680 (ALDERLAKE_S)
[01:51:47] [PASSED] 0x4682 (ALDERLAKE_S)
[01:51:47] [PASSED] 0x4688 (ALDERLAKE_S)
[01:51:47] [PASSED] 0x468A (ALDERLAKE_S)
[01:51:47] [PASSED] 0x468B (ALDERLAKE_S)
[01:51:47] [PASSED] 0x4690 (ALDERLAKE_S)
[01:51:47] [PASSED] 0x4692 (ALDERLAKE_S)
[01:51:47] [PASSED] 0x4693 (ALDERLAKE_S)
[01:51:47] [PASSED] 0x46A0 (ALDERLAKE_P)
[01:51:47] [PASSED] 0x46A1 (ALDERLAKE_P)
[01:51:47] [PASSED] 0x46A2 (ALDERLAKE_P)
[01:51:47] [PASSED] 0x46A3 (ALDERLAKE_P)
[01:51:47] [PASSED] 0x46A6 (ALDERLAKE_P)
[01:51:47] [PASSED] 0x46A8 (ALDERLAKE_P)
[01:51:47] [PASSED] 0x46AA (ALDERLAKE_P)
[01:51:47] [PASSED] 0x462A (ALDERLAKE_P)
[01:51:47] [PASSED] 0x4626 (ALDERLAKE_P)
[01:51:47] [PASSED] 0x4628 (ALDERLAKE_P)
[01:51:47] [PASSED] 0x46B0 (ALDERLAKE_P)
[01:51:47] [PASSED] 0x46B1 (ALDERLAKE_P)
[01:51:47] [PASSED] 0x46B2 (ALDERLAKE_P)
[01:51:47] [PASSED] 0x46B3 (ALDERLAKE_P)
[01:51:47] [PASSED] 0x46C0 (ALDERLAKE_P)
[01:51:47] [PASSED] 0x46C1 (ALDERLAKE_P)
[01:51:47] [PASSED] 0x46C2 (ALDERLAKE_P)
[01:51:47] [PASSED] 0x46C3 (ALDERLAKE_P)
[01:51:47] [PASSED] 0x46D0 (ALDERLAKE_N)
[01:51:47] [PASSED] 0x46D1 (ALDERLAKE_N)
[01:51:47] [PASSED] 0x46D2 (ALDERLAKE_N)
[01:51:47] [PASSED] 0x46D3 (ALDERLAKE_N)
[01:51:47] [PASSED] 0x46D4 (ALDERLAKE_N)
[01:51:47] [PASSED] 0xA721 (ALDERLAKE_P)
[01:51:47] [PASSED] 0xA7A1 (ALDERLAKE_P)
[01:51:47] [PASSED] 0xA7A9 (ALDERLAKE_P)
[01:51:47] [PASSED] 0xA7AC (ALDERLAKE_P)
[01:51:47] [PASSED] 0xA7AD (ALDERLAKE_P)
[01:51:47] [PASSED] 0xA720 (ALDERLAKE_P)
[01:51:47] [PASSED] 0xA7A0 (ALDERLAKE_P)
[01:51:47] [PASSED] 0xA7A8 (ALDERLAKE_P)
[01:51:47] [PASSED] 0xA7AA (ALDERLAKE_P)
[01:51:47] [PASSED] 0xA7AB (ALDERLAKE_P)
[01:51:47] [PASSED] 0xA780 (ALDERLAKE_S)
[01:51:47] [PASSED] 0xA781 (ALDERLAKE_S)
[01:51:47] [PASSED] 0xA782 (ALDERLAKE_S)
[01:51:47] [PASSED] 0xA783 (ALDERLAKE_S)
[01:51:47] [PASSED] 0xA788 (ALDERLAKE_S)
[01:51:47] [PASSED] 0xA789 (ALDERLAKE_S)
[01:51:47] [PASSED] 0xA78A (ALDERLAKE_S)
[01:51:47] [PASSED] 0xA78B (ALDERLAKE_S)
[01:51:47] [PASSED] 0x4905 (DG1)
[01:51:47] [PASSED] 0x4906 (DG1)
[01:51:47] [PASSED] 0x4907 (DG1)
[01:51:47] [PASSED] 0x4908 (DG1)
[01:51:47] [PASSED] 0x4909 (DG1)
[01:51:47] [PASSED] 0x56C0 (DG2)
[01:51:47] [PASSED] 0x56C2 (DG2)
[01:51:47] [PASSED] 0x56C1 (DG2)
[01:51:47] [PASSED] 0x7D51 (METEORLAKE)
[01:51:47] [PASSED] 0x7DD1 (METEORLAKE)
[01:51:47] [PASSED] 0x7D41 (METEORLAKE)
[01:51:47] [PASSED] 0x7D67 (METEORLAKE)
[01:51:47] [PASSED] 0xB640 (METEORLAKE)
[01:51:47] [PASSED] 0x56A0 (DG2)
[01:51:47] [PASSED] 0x56A1 (DG2)
[01:51:47] [PASSED] 0x56A2 (DG2)
[01:51:47] [PASSED] 0x56BE (DG2)
[01:51:47] [PASSED] 0x56BF (DG2)
[01:51:47] [PASSED] 0x5690 (DG2)
[01:51:47] [PASSED] 0x5691 (DG2)
[01:51:47] [PASSED] 0x5692 (DG2)
[01:51:47] [PASSED] 0x56A5 (DG2)
[01:51:47] [PASSED] 0x56A6 (DG2)
[01:51:47] [PASSED] 0x56B0 (DG2)
[01:51:47] [PASSED] 0x56B1 (DG2)
[01:51:47] [PASSED] 0x56BA (DG2)
[01:51:47] [PASSED] 0x56BB (DG2)
[01:51:47] [PASSED] 0x56BC (DG2)
[01:51:47] [PASSED] 0x56BD (DG2)
[01:51:47] [PASSED] 0x5693 (DG2)
[01:51:47] [PASSED] 0x5694 (DG2)
[01:51:47] [PASSED] 0x5695 (DG2)
[01:51:47] [PASSED] 0x56A3 (DG2)
[01:51:47] [PASSED] 0x56A4 (DG2)
[01:51:47] [PASSED] 0x56B2 (DG2)
[01:51:47] [PASSED] 0x56B3 (DG2)
[01:51:47] [PASSED] 0x5696 (DG2)
[01:51:47] [PASSED] 0x5697 (DG2)
[01:51:47] [PASSED] 0xB69 (PVC)
[01:51:47] [PASSED] 0xB6E (PVC)
[01:51:47] [PASSED] 0xBD4 (PVC)
[01:51:47] [PASSED] 0xBD5 (PVC)
[01:51:47] [PASSED] 0xBD6 (PVC)
[01:51:47] [PASSED] 0xBD7 (PVC)
[01:51:47] [PASSED] 0xBD8 (PVC)
[01:51:47] [PASSED] 0xBD9 (PVC)
[01:51:47] [PASSED] 0xBDA (PVC)
[01:51:47] [PASSED] 0xBDB (PVC)
[01:51:47] [PASSED] 0xBE0 (PVC)
[01:51:47] [PASSED] 0xBE1 (PVC)
[01:51:47] [PASSED] 0xBE5 (PVC)
[01:51:47] [PASSED] 0x7D40 (METEORLAKE)
[01:51:47] [PASSED] 0x7D45 (METEORLAKE)
[01:51:47] [PASSED] 0x7D55 (METEORLAKE)
[01:51:47] [PASSED] 0x7D60 (METEORLAKE)
[01:51:47] [PASSED] 0x7DD5 (METEORLAKE)
[01:51:47] [PASSED] 0x6420 (LUNARLAKE)
[01:51:47] [PASSED] 0x64A0 (LUNARLAKE)
[01:51:47] [PASSED] 0x64B0 (LUNARLAKE)
[01:51:47] [PASSED] 0xE202 (BATTLEMAGE)
[01:51:47] [PASSED] 0xE209 (BATTLEMAGE)
[01:51:47] [PASSED] 0xE20B (BATTLEMAGE)
[01:51:47] [PASSED] 0xE20C (BATTLEMAGE)
[01:51:47] [PASSED] 0xE20D (BATTLEMAGE)
[01:51:47] [PASSED] 0xE210 (BATTLEMAGE)
[01:51:47] [PASSED] 0xE211 (BATTLEMAGE)
[01:51:47] [PASSED] 0xE212 (BATTLEMAGE)
[01:51:47] [PASSED] 0xE216 (BATTLEMAGE)
[01:51:47] [PASSED] 0xE220 (BATTLEMAGE)
[01:51:47] [PASSED] 0xE221 (BATTLEMAGE)
[01:51:47] [PASSED] 0xE222 (BATTLEMAGE)
[01:51:47] [PASSED] 0xE223 (BATTLEMAGE)
[01:51:47] [PASSED] 0xB080 (PANTHERLAKE)
[01:51:47] [PASSED] 0xB081 (PANTHERLAKE)
[01:51:47] [PASSED] 0xB082 (PANTHERLAKE)
[01:51:47] [PASSED] 0xB083 (PANTHERLAKE)
[01:51:47] [PASSED] 0xB084 (PANTHERLAKE)
[01:51:47] [PASSED] 0xB085 (PANTHERLAKE)
[01:51:47] [PASSED] 0xB086 (PANTHERLAKE)
[01:51:47] [PASSED] 0xB087 (PANTHERLAKE)
[01:51:47] [PASSED] 0xB08F (PANTHERLAKE)
[01:51:47] [PASSED] 0xB090 (PANTHERLAKE)
[01:51:47] [PASSED] 0xB0A0 (PANTHERLAKE)
[01:51:47] [PASSED] 0xB0B0 (PANTHERLAKE)
[01:51:47] [PASSED] 0xFD80 (PANTHERLAKE)
[01:51:47] [PASSED] 0xFD81 (PANTHERLAKE)
[01:51:47] ============= [PASSED] check_platform_gt_count =============
[01:51:47] ===================== [PASSED] xe_pci ======================
[01:51:47] =================== xe_rtp (2 subtests) ====================
[01:51:47] =============== xe_rtp_process_to_sr_tests  ================
[01:51:47] [PASSED] coalesce-same-reg
[01:51:47] [PASSED] no-match-no-add
[01:51:47] [PASSED] match-or
[01:51:47] [PASSED] match-or-xfail
[01:51:47] [PASSED] no-match-no-add-multiple-rules
[01:51:47] [PASSED] two-regs-two-entries
[01:51:47] [PASSED] clr-one-set-other
[01:51:47] [PASSED] set-field
[01:51:47] [PASSED] conflict-duplicate
[01:51:47] [PASSED] conflict-not-disjoint
[01:51:47] [PASSED] conflict-reg-type
[01:51:47] =========== [PASSED] xe_rtp_process_to_sr_tests ============
[01:51:47] ================== xe_rtp_process_tests  ===================
[01:51:47] [PASSED] active1
[01:51:47] [PASSED] active2
[01:51:47] [PASSED] active-inactive
[01:51:47] [PASSED] inactive-active
[01:51:47] [PASSED] inactive-1st_or_active-inactive
[01:51:47] [PASSED] inactive-2nd_or_active-inactive
[01:51:47] [PASSED] inactive-last_or_active-inactive
[01:51:47] [PASSED] inactive-no_or_active-inactive
[01:51:47] ============== [PASSED] xe_rtp_process_tests ===============
[01:51:47] ===================== [PASSED] xe_rtp ======================
[01:51:47] ==================== xe_wa (1 subtest) =====================
[01:51:47] ======================== xe_wa_gt  =========================
[01:51:47] [PASSED] TIGERLAKE B0
[01:51:47] [PASSED] DG1 A0
[01:51:47] [PASSED] DG1 B0
[01:51:47] [PASSED] ALDERLAKE_S A0
[01:51:47] [PASSED] ALDERLAKE_S B0
stty: 'standard input': Inappropriate ioctl for device
[01:51:47] [PASSED] ALDERLAKE_S C0
[01:51:47] [PASSED] ALDERLAKE_S D0
[01:51:47] [PASSED] ALDERLAKE_P A0
[01:51:47] [PASSED] ALDERLAKE_P B0
[01:51:47] [PASSED] ALDERLAKE_P C0
[01:51:47] [PASSED] ALDERLAKE_S RPLS D0
[01:51:47] [PASSED] ALDERLAKE_P RPLU E0
[01:51:47] [PASSED] DG2 G10 C0
[01:51:47] [PASSED] DG2 G11 B1
[01:51:47] [PASSED] DG2 G12 A1
[01:51:47] [PASSED] METEORLAKE 12.70(Xe_LPG) A0 13.00(Xe_LPM+) A0
[01:51:47] [PASSED] METEORLAKE 12.71(Xe_LPG) A0 13.00(Xe_LPM+) A0
[01:51:47] [PASSED] METEORLAKE 12.74(Xe_LPG+) A0 13.00(Xe_LPM+) A0
[01:51:47] [PASSED] LUNARLAKE 20.04(Xe2_LPG) A0 20.00(Xe2_LPM) A0
[01:51:47] [PASSED] LUNARLAKE 20.04(Xe2_LPG) B0 20.00(Xe2_LPM) A0
[01:51:47] [PASSED] BATTLEMAGE 20.01(Xe2_HPG) A0 13.01(Xe2_HPM) A1
[01:51:47] [PASSED] PANTHERLAKE 30.00(Xe3_LPG) A0 30.00(Xe3_LPM) A0
[01:51:47] ==================== [PASSED] xe_wa_gt =====================
[01:51:47] ====================== [PASSED] xe_wa ======================
[01:51:47] ============================================================
[01:51:47] Testing complete. Ran 306 tests: passed: 288, skipped: 18
[01:51:47] Elapsed time: 35.100s total, 4.270s configuring, 30.464s building, 0.339s running

+ /kernel/tools/testing/kunit/kunit.py run --kunitconfig /kernel/drivers/gpu/drm/tests/.kunitconfig
[01:51:48] Configuring KUnit Kernel ...
Regenerating .config ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
[01:51:49] Building KUnit Kernel ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
Building with:
$ make all compile_commands.json scripts_gdb ARCH=um O=.kunit --jobs=48
[01:52:14] Starting KUnit Kernel (1/1)...
[01:52:14] ============================================================
Running tests with:
$ .kunit/linux kunit.enable=1 mem=1G console=tty kunit_shutdown=halt
[01:52:14] ============ drm_test_pick_cmdline (2 subtests) ============
[01:52:14] [PASSED] drm_test_pick_cmdline_res_1920_1080_60
[01:52:14] =============== drm_test_pick_cmdline_named  ===============
[01:52:14] [PASSED] NTSC
[01:52:14] [PASSED] NTSC-J
[01:52:14] [PASSED] PAL
[01:52:14] [PASSED] PAL-M
[01:52:14] =========== [PASSED] drm_test_pick_cmdline_named ===========
[01:52:14] ============== [PASSED] drm_test_pick_cmdline ==============
[01:52:14] == drm_test_atomic_get_connector_for_encoder (1 subtest) ===
[01:52:14] [PASSED] drm_test_drm_atomic_get_connector_for_encoder
[01:52:14] ==== [PASSED] drm_test_atomic_get_connector_for_encoder ====
[01:52:14] =========== drm_validate_clone_mode (2 subtests) ===========
[01:52:14] ============== drm_test_check_in_clone_mode  ===============
[01:52:14] [PASSED] in_clone_mode
[01:52:14] [PASSED] not_in_clone_mode
[01:52:14] ========== [PASSED] drm_test_check_in_clone_mode ===========
[01:52:14] =============== drm_test_check_valid_clones  ===============
[01:52:14] [PASSED] not_in_clone_mode
[01:52:14] [PASSED] valid_clone
[01:52:14] [PASSED] invalid_clone
[01:52:14] =========== [PASSED] drm_test_check_valid_clones ===========
[01:52:14] ============= [PASSED] drm_validate_clone_mode =============
[01:52:14] ============= drm_validate_modeset (1 subtest) =============
[01:52:14] [PASSED] drm_test_check_connector_changed_modeset
[01:52:14] ============== [PASSED] drm_validate_modeset ===============
[01:52:14] ====== drm_test_bridge_get_current_state (2 subtests) ======
[01:52:14] [PASSED] drm_test_drm_bridge_get_current_state_atomic
[01:52:14] [PASSED] drm_test_drm_bridge_get_current_state_legacy
[01:52:14] ======== [PASSED] drm_test_bridge_get_current_state ========
[01:52:14] ====== drm_test_bridge_helper_reset_crtc (3 subtests) ======
[01:52:14] [PASSED] drm_test_drm_bridge_helper_reset_crtc_atomic
[01:52:14] [PASSED] drm_test_drm_bridge_helper_reset_crtc_atomic_disabled
[01:52:14] [PASSED] drm_test_drm_bridge_helper_reset_crtc_legacy
[01:52:14] ======== [PASSED] drm_test_bridge_helper_reset_crtc ========
[01:52:14] ============== drm_bridge_alloc (2 subtests) ===============
[01:52:14] [PASSED] drm_test_drm_bridge_alloc_basic
[01:52:14] [PASSED] drm_test_drm_bridge_alloc_get_put
[01:52:14] ================ [PASSED] drm_bridge_alloc =================
[01:52:14] ================== drm_buddy (8 subtests) ==================
[01:52:14] [PASSED] drm_test_buddy_alloc_limit
[01:52:14] [PASSED] drm_test_buddy_alloc_optimistic
[01:52:14] [PASSED] drm_test_buddy_alloc_pessimistic
[01:52:14] [PASSED] drm_test_buddy_alloc_pathological
[01:52:14] [PASSED] drm_test_buddy_alloc_contiguous
[01:52:14] [PASSED] drm_test_buddy_alloc_clear
[01:52:14] [PASSED] drm_test_buddy_alloc_range_bias
[01:52:14] [PASSED] drm_test_buddy_fragmentation_performance
[01:52:14] ==================== [PASSED] drm_buddy ====================
[01:52:14] ============= drm_cmdline_parser (40 subtests) =============
[01:52:14] [PASSED] drm_test_cmdline_force_d_only
[01:52:14] [PASSED] drm_test_cmdline_force_D_only_dvi
[01:52:14] [PASSED] drm_test_cmdline_force_D_only_hdmi
[01:52:14] [PASSED] drm_test_cmdline_force_D_only_not_digital
[01:52:14] [PASSED] drm_test_cmdline_force_e_only
[01:52:14] [PASSED] drm_test_cmdline_res
[01:52:14] [PASSED] drm_test_cmdline_res_vesa
[01:52:14] [PASSED] drm_test_cmdline_res_vesa_rblank
[01:52:14] [PASSED] drm_test_cmdline_res_rblank
[01:52:14] [PASSED] drm_test_cmdline_res_bpp
[01:52:14] [PASSED] drm_test_cmdline_res_refresh
[01:52:14] [PASSED] drm_test_cmdline_res_bpp_refresh
[01:52:14] [PASSED] drm_test_cmdline_res_bpp_refresh_interlaced
[01:52:14] [PASSED] drm_test_cmdline_res_bpp_refresh_margins
[01:52:14] [PASSED] drm_test_cmdline_res_bpp_refresh_force_off
[01:52:14] [PASSED] drm_test_cmdline_res_bpp_refresh_force_on
[01:52:14] [PASSED] drm_test_cmdline_res_bpp_refresh_force_on_analog
[01:52:14] [PASSED] drm_test_cmdline_res_bpp_refresh_force_on_digital
[01:52:14] [PASSED] drm_test_cmdline_res_bpp_refresh_interlaced_margins_force_on
[01:52:14] [PASSED] drm_test_cmdline_res_margins_force_on
[01:52:14] [PASSED] drm_test_cmdline_res_vesa_margins
[01:52:14] [PASSED] drm_test_cmdline_name
[01:52:14] [PASSED] drm_test_cmdline_name_bpp
[01:52:14] [PASSED] drm_test_cmdline_name_option
[01:52:14] [PASSED] drm_test_cmdline_name_bpp_option
[01:52:14] [PASSED] drm_test_cmdline_rotate_0
[01:52:14] [PASSED] drm_test_cmdline_rotate_90
[01:52:14] [PASSED] drm_test_cmdline_rotate_180
[01:52:14] [PASSED] drm_test_cmdline_rotate_270
[01:52:14] [PASSED] drm_test_cmdline_hmirror
[01:52:14] [PASSED] drm_test_cmdline_vmirror
[01:52:14] [PASSED] drm_test_cmdline_margin_options
[01:52:14] [PASSED] drm_test_cmdline_multiple_options
[01:52:14] [PASSED] drm_test_cmdline_bpp_extra_and_option
[01:52:14] [PASSED] drm_test_cmdline_extra_and_option
[01:52:14] [PASSED] drm_test_cmdline_freestanding_options
[01:52:14] [PASSED] drm_test_cmdline_freestanding_force_e_and_options
[01:52:14] [PASSED] drm_test_cmdline_panel_orientation
[01:52:14] ================ drm_test_cmdline_invalid  =================
[01:52:14] [PASSED] margin_only
[01:52:14] [PASSED] interlace_only
[01:52:14] [PASSED] res_missing_x
[01:52:14] [PASSED] res_missing_y
[01:52:14] [PASSED] res_bad_y
[01:52:14] [PASSED] res_missing_y_bpp
[01:52:14] [PASSED] res_bad_bpp
[01:52:14] [PASSED] res_bad_refresh
[01:52:14] [PASSED] res_bpp_refresh_force_on_off
[01:52:14] [PASSED] res_invalid_mode
[01:52:14] [PASSED] res_bpp_wrong_place_mode
[01:52:14] [PASSED] name_bpp_refresh
[01:52:14] [PASSED] name_refresh
[01:52:14] [PASSED] name_refresh_wrong_mode
[01:52:14] [PASSED] name_refresh_invalid_mode
[01:52:14] [PASSED] rotate_multiple
[01:52:14] [PASSED] rotate_invalid_val
[01:52:14] [PASSED] rotate_truncated
[01:52:14] [PASSED] invalid_option
[01:52:14] [PASSED] invalid_tv_option
[01:52:14] [PASSED] truncated_tv_option
[01:52:14] ============ [PASSED] drm_test_cmdline_invalid =============
[01:52:14] =============== drm_test_cmdline_tv_options  ===============
[01:52:14] [PASSED] NTSC
[01:52:14] [PASSED] NTSC_443
[01:52:14] [PASSED] NTSC_J
[01:52:14] [PASSED] PAL
[01:52:14] [PASSED] PAL_M
[01:52:14] [PASSED] PAL_N
[01:52:14] [PASSED] SECAM
[01:52:14] [PASSED] MONO_525
[01:52:14] [PASSED] MONO_625
[01:52:14] =========== [PASSED] drm_test_cmdline_tv_options ===========
[01:52:14] =============== [PASSED] drm_cmdline_parser ================
[01:52:14] ========== drmm_connector_hdmi_init (20 subtests) ==========
[01:52:14] [PASSED] drm_test_connector_hdmi_init_valid
[01:52:14] [PASSED] drm_test_connector_hdmi_init_bpc_8
[01:52:14] [PASSED] drm_test_connector_hdmi_init_bpc_10
[01:52:14] [PASSED] drm_test_connector_hdmi_init_bpc_12
[01:52:14] [PASSED] drm_test_connector_hdmi_init_bpc_invalid
[01:52:14] [PASSED] drm_test_connector_hdmi_init_bpc_null
[01:52:14] [PASSED] drm_test_connector_hdmi_init_formats_empty
[01:52:14] [PASSED] drm_test_connector_hdmi_init_formats_no_rgb
[01:52:14] === drm_test_connector_hdmi_init_formats_yuv420_allowed  ===
[01:52:14] [PASSED] supported_formats=0x9 yuv420_allowed=1
[01:52:14] [PASSED] supported_formats=0x9 yuv420_allowed=0
[01:52:14] [PASSED] supported_formats=0x3 yuv420_allowed=1
[01:52:14] [PASSED] supported_formats=0x3 yuv420_allowed=0
[01:52:14] === [PASSED] drm_test_connector_hdmi_init_formats_yuv420_allowed ===
[01:52:14] [PASSED] drm_test_connector_hdmi_init_null_ddc
[01:52:14] [PASSED] drm_test_connector_hdmi_init_null_product
[01:52:14] [PASSED] drm_test_connector_hdmi_init_null_vendor
[01:52:14] [PASSED] drm_test_connector_hdmi_init_product_length_exact
[01:52:14] [PASSED] drm_test_connector_hdmi_init_product_length_too_long
[01:52:14] [PASSED] drm_test_connector_hdmi_init_product_valid
[01:52:14] [PASSED] drm_test_connector_hdmi_init_vendor_length_exact
[01:52:14] [PASSED] drm_test_connector_hdmi_init_vendor_length_too_long
[01:52:14] [PASSED] drm_test_connector_hdmi_init_vendor_valid
[01:52:14] ========= drm_test_connector_hdmi_init_type_valid  =========
[01:52:14] [PASSED] HDMI-A
[01:52:14] [PASSED] HDMI-B
[01:52:14] ===== [PASSED] drm_test_connector_hdmi_init_type_valid =====
[01:52:14] ======== drm_test_connector_hdmi_init_type_invalid  ========
[01:52:14] [PASSED] Unknown
[01:52:14] [PASSED] VGA
[01:52:14] [PASSED] DVI-I
[01:52:14] [PASSED] DVI-D
[01:52:14] [PASSED] DVI-A
[01:52:14] [PASSED] Composite
[01:52:14] [PASSED] SVIDEO
[01:52:14] [PASSED] LVDS
[01:52:14] [PASSED] Component
[01:52:14] [PASSED] DIN
[01:52:14] [PASSED] DP
[01:52:14] [PASSED] TV
[01:52:14] [PASSED] eDP
[01:52:14] [PASSED] Virtual
[01:52:14] [PASSED] DSI
[01:52:14] [PASSED] DPI
[01:52:14] [PASSED] Writeback
[01:52:14] [PASSED] SPI
[01:52:14] [PASSED] USB
[01:52:14] ==== [PASSED] drm_test_connector_hdmi_init_type_invalid ====
[01:52:14] ============ [PASSED] drmm_connector_hdmi_init =============
[01:52:14] ============= drmm_connector_init (3 subtests) =============
[01:52:14] [PASSED] drm_test_drmm_connector_init
[01:52:14] [PASSED] drm_test_drmm_connector_init_null_ddc
[01:52:14] ========= drm_test_drmm_connector_init_type_valid  =========
[01:52:14] [PASSED] Unknown
[01:52:14] [PASSED] VGA
[01:52:14] [PASSED] DVI-I
[01:52:14] [PASSED] DVI-D
[01:52:14] [PASSED] DVI-A
[01:52:14] [PASSED] Composite
[01:52:14] [PASSED] SVIDEO
[01:52:14] [PASSED] LVDS
[01:52:14] [PASSED] Component
[01:52:14] [PASSED] DIN
[01:52:14] [PASSED] DP
[01:52:14] [PASSED] HDMI-A
[01:52:14] [PASSED] HDMI-B
[01:52:14] [PASSED] TV
[01:52:14] [PASSED] eDP
[01:52:14] [PASSED] Virtual
[01:52:14] [PASSED] DSI
[01:52:14] [PASSED] DPI
[01:52:14] [PASSED] Writeback
[01:52:14] [PASSED] SPI
[01:52:14] [PASSED] USB
[01:52:14] ===== [PASSED] drm_test_drmm_connector_init_type_valid =====
[01:52:14] =============== [PASSED] drmm_connector_init ===============
[01:52:14] ========= drm_connector_dynamic_init (6 subtests) ==========
[01:52:14] [PASSED] drm_test_drm_connector_dynamic_init
[01:52:14] [PASSED] drm_test_drm_connector_dynamic_init_null_ddc
[01:52:14] [PASSED] drm_test_drm_connector_dynamic_init_not_added
[01:52:14] [PASSED] drm_test_drm_connector_dynamic_init_properties
[01:52:14] ===== drm_test_drm_connector_dynamic_init_type_valid  ======
[01:52:14] [PASSED] Unknown
[01:52:14] [PASSED] VGA
[01:52:14] [PASSED] DVI-I
[01:52:14] [PASSED] DVI-D
[01:52:14] [PASSED] DVI-A
[01:52:14] [PASSED] Composite
[01:52:14] [PASSED] SVIDEO
[01:52:14] [PASSED] LVDS
[01:52:14] [PASSED] Component
[01:52:14] [PASSED] DIN
[01:52:14] [PASSED] DP
[01:52:14] [PASSED] HDMI-A
[01:52:14] [PASSED] HDMI-B
[01:52:14] [PASSED] TV
[01:52:14] [PASSED] eDP
[01:52:14] [PASSED] Virtual
[01:52:14] [PASSED] DSI
[01:52:14] [PASSED] DPI
[01:52:14] [PASSED] Writeback
[01:52:14] [PASSED] SPI
[01:52:14] [PASSED] USB
[01:52:14] = [PASSED] drm_test_drm_connector_dynamic_init_type_valid ==
[01:52:14] ======== drm_test_drm_connector_dynamic_init_name  =========
[01:52:14] [PASSED] Unknown
[01:52:14] [PASSED] VGA
[01:52:14] [PASSED] DVI-I
[01:52:14] [PASSED] DVI-D
[01:52:14] [PASSED] DVI-A
[01:52:14] [PASSED] Composite
[01:52:14] [PASSED] SVIDEO
[01:52:14] [PASSED] LVDS
[01:52:14] [PASSED] Component
[01:52:14] [PASSED] DIN
[01:52:14] [PASSED] DP
[01:52:14] [PASSED] HDMI-A
[01:52:14] [PASSED] HDMI-B
[01:52:14] [PASSED] TV
[01:52:14] [PASSED] eDP
[01:52:14] [PASSED] Virtual
[01:52:14] [PASSED] DSI
[01:52:14] [PASSED] DPI
[01:52:14] [PASSED] Writeback
[01:52:14] [PASSED] SPI
[01:52:14] [PASSED] USB
[01:52:14] ==== [PASSED] drm_test_drm_connector_dynamic_init_name =====
[01:52:14] =========== [PASSED] drm_connector_dynamic_init ============
[01:52:14] ==== drm_connector_dynamic_register_early (4 subtests) =====
[01:52:14] [PASSED] drm_test_drm_connector_dynamic_register_early_on_list
[01:52:14] [PASSED] drm_test_drm_connector_dynamic_register_early_defer
[01:52:14] [PASSED] drm_test_drm_connector_dynamic_register_early_no_init
[01:52:14] [PASSED] drm_test_drm_connector_dynamic_register_early_no_mode_object
[01:52:14] ====== [PASSED] drm_connector_dynamic_register_early =======
[01:52:14] ======= drm_connector_dynamic_register (7 subtests) ========
[01:52:14] [PASSED] drm_test_drm_connector_dynamic_register_on_list
[01:52:14] [PASSED] drm_test_drm_connector_dynamic_register_no_defer
[01:52:14] [PASSED] drm_test_drm_connector_dynamic_register_no_init
[01:52:14] [PASSED] drm_test_drm_connector_dynamic_register_mode_object
[01:52:14] [PASSED] drm_test_drm_connector_dynamic_register_sysfs
[01:52:14] [PASSED] drm_test_drm_connector_dynamic_register_sysfs_name
[01:52:14] [PASSED] drm_test_drm_connector_dynamic_register_debugfs
[01:52:14] ========= [PASSED] drm_connector_dynamic_register ==========
[01:52:14] = drm_connector_attach_broadcast_rgb_property (2 subtests) =
[01:52:14] [PASSED] drm_test_drm_connector_attach_broadcast_rgb_property
[01:52:14] [PASSED] drm_test_drm_connector_attach_broadcast_rgb_property_hdmi_connector
[01:52:14] === [PASSED] drm_connector_attach_broadcast_rgb_property ===
[01:52:14] ========== drm_get_tv_mode_from_name (2 subtests) ==========
[01:52:14] ========== drm_test_get_tv_mode_from_name_valid  ===========
[01:52:14] [PASSED] NTSC
[01:52:14] [PASSED] NTSC-443
[01:52:14] [PASSED] NTSC-J
[01:52:14] [PASSED] PAL
[01:52:14] [PASSED] PAL-M
[01:52:14] [PASSED] PAL-N
[01:52:14] [PASSED] SECAM
[01:52:14] [PASSED] Mono
[01:52:14] ====== [PASSED] drm_test_get_tv_mode_from_name_valid =======
[01:52:14] [PASSED] drm_test_get_tv_mode_from_name_truncated
[01:52:14] ============ [PASSED] drm_get_tv_mode_from_name ============
[01:52:14] = drm_test_connector_hdmi_compute_mode_clock (12 subtests) =
[01:52:14] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb
[01:52:14] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_10bpc
[01:52:14] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_10bpc_vic_1
[01:52:14] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_12bpc
[01:52:14] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_12bpc_vic_1
[01:52:14] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_double
[01:52:14] = drm_test_connector_hdmi_compute_mode_clock_yuv420_valid  =
[01:52:14] [PASSED] VIC 96
[01:52:14] [PASSED] VIC 97
[01:52:14] [PASSED] VIC 101
[01:52:14] [PASSED] VIC 102
[01:52:14] [PASSED] VIC 106
[01:52:14] [PASSED] VIC 107
[01:52:14] === [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv420_valid ===
[01:52:14] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv420_10_bpc
[01:52:14] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv420_12_bpc
[01:52:14] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv422_8_bpc
[01:52:14] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv422_10_bpc
[01:52:14] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv422_12_bpc
[01:52:14] === [PASSED] drm_test_connector_hdmi_compute_mode_clock ====
[01:52:14] == drm_hdmi_connector_get_broadcast_rgb_name (2 subtests) ==
[01:52:14] === drm_test_drm_hdmi_connector_get_broadcast_rgb_name  ====
[01:52:14] [PASSED] Automatic
[01:52:14] [PASSED] Full
[01:52:14] [PASSED] Limited 16:235
[01:52:14] === [PASSED] drm_test_drm_hdmi_connector_get_broadcast_rgb_name ===
[01:52:14] [PASSED] drm_test_drm_hdmi_connector_get_broadcast_rgb_name_invalid
[01:52:14] ==== [PASSED] drm_hdmi_connector_get_broadcast_rgb_name ====
[01:52:14] == drm_hdmi_connector_get_output_format_name (2 subtests) ==
[01:52:14] === drm_test_drm_hdmi_connector_get_output_format_name  ====
[01:52:14] [PASSED] RGB
[01:52:14] [PASSED] YUV 4:2:0
[01:52:14] [PASSED] YUV 4:2:2
[01:52:14] [PASSED] YUV 4:4:4
[01:52:14] === [PASSED] drm_test_drm_hdmi_connector_get_output_format_name ===
[01:52:14] [PASSED] drm_test_drm_hdmi_connector_get_output_format_name_invalid
[01:52:14] ==== [PASSED] drm_hdmi_connector_get_output_format_name ====
[01:52:14] ============= drm_damage_helper (21 subtests) ==============
[01:52:14] [PASSED] drm_test_damage_iter_no_damage
[01:52:14] [PASSED] drm_test_damage_iter_no_damage_fractional_src
[01:52:14] [PASSED] drm_test_damage_iter_no_damage_src_moved
[01:52:14] [PASSED] drm_test_damage_iter_no_damage_fractional_src_moved
[01:52:14] [PASSED] drm_test_damage_iter_no_damage_not_visible
[01:52:14] [PASSED] drm_test_damage_iter_no_damage_no_crtc
[01:52:14] [PASSED] drm_test_damage_iter_no_damage_no_fb
[01:52:14] [PASSED] drm_test_damage_iter_simple_damage
[01:52:14] [PASSED] drm_test_damage_iter_single_damage
[01:52:14] [PASSED] drm_test_damage_iter_single_damage_intersect_src
[01:52:14] [PASSED] drm_test_damage_iter_single_damage_outside_src
[01:52:14] [PASSED] drm_test_damage_iter_single_damage_fractional_src
[01:52:14] [PASSED] drm_test_damage_iter_single_damage_intersect_fractional_src
[01:52:14] [PASSED] drm_test_damage_iter_single_damage_outside_fractional_src
[01:52:14] [PASSED] drm_test_damage_iter_single_damage_src_moved
[01:52:14] [PASSED] drm_test_damage_iter_single_damage_fractional_src_moved
[01:52:14] [PASSED] drm_test_damage_iter_damage
[01:52:14] [PASSED] drm_test_damage_iter_damage_one_intersect
[01:52:14] [PASSED] drm_test_damage_iter_damage_one_outside
[01:52:14] [PASSED] drm_test_damage_iter_damage_src_moved
[01:52:14] [PASSED] drm_test_damage_iter_damage_not_visible
[01:52:14] ================ [PASSED] drm_damage_helper ================
[01:52:14] ============== drm_dp_mst_helper (3 subtests) ==============
[01:52:14] ============== drm_test_dp_mst_calc_pbn_mode  ==============
[01:52:14] [PASSED] Clock 154000 BPP 30 DSC disabled
[01:52:14] [PASSED] Clock 234000 BPP 30 DSC disabled
[01:52:14] [PASSED] Clock 297000 BPP 24 DSC disabled
[01:52:14] [PASSED] Clock 332880 BPP 24 DSC enabled
[01:52:14] [PASSED] Clock 324540 BPP 24 DSC enabled
[01:52:14] ========== [PASSED] drm_test_dp_mst_calc_pbn_mode ==========
[01:52:14] ============== drm_test_dp_mst_calc_pbn_div  ===============
[01:52:14] [PASSED] Link rate 2000000 lane count 4
[01:52:14] [PASSED] Link rate 2000000 lane count 2
[01:52:14] [PASSED] Link rate 2000000 lane count 1
[01:52:14] [PASSED] Link rate 1350000 lane count 4
[01:52:14] [PASSED] Link rate 1350000 lane count 2
[01:52:14] [PASSED] Link rate 1350000 lane count 1
[01:52:14] [PASSED] Link rate 1000000 lane count 4
[01:52:14] [PASSED] Link rate 1000000 lane count 2
[01:52:14] [PASSED] Link rate 1000000 lane count 1
[01:52:14] [PASSED] Link rate 810000 lane count 4
[01:52:14] [PASSED] Link rate 810000 lane count 2
[01:52:14] [PASSED] Link rate 810000 lane count 1
[01:52:14] [PASSED] Link rate 540000 lane count 4
[01:52:14] [PASSED] Link rate 540000 lane count 2
[01:52:14] [PASSED] Link rate 540000 lane count 1
[01:52:14] [PASSED] Link rate 270000 lane count 4
[01:52:14] [PASSED] Link rate 270000 lane count 2
[01:52:14] [PASSED] Link rate 270000 lane count 1
[01:52:14] [PASSED] Link rate 162000 lane count 4
[01:52:14] [PASSED] Link rate 162000 lane count 2
[01:52:14] [PASSED] Link rate 162000 lane count 1
[01:52:14] ========== [PASSED] drm_test_dp_mst_calc_pbn_div ===========
[01:52:14] ========= drm_test_dp_mst_sideband_msg_req_decode  =========
[01:52:14] [PASSED] DP_ENUM_PATH_RESOURCES with port number
[01:52:14] [PASSED] DP_POWER_UP_PHY with port number
[01:52:14] [PASSED] DP_POWER_DOWN_PHY with port number
[01:52:14] [PASSED] DP_ALLOCATE_PAYLOAD with SDP stream sinks
[01:52:14] [PASSED] DP_ALLOCATE_PAYLOAD with port number
[01:52:14] [PASSED] DP_ALLOCATE_PAYLOAD with VCPI
[01:52:14] [PASSED] DP_ALLOCATE_PAYLOAD with PBN
[01:52:14] [PASSED] DP_QUERY_PAYLOAD with port number
[01:52:14] [PASSED] DP_QUERY_PAYLOAD with VCPI
[01:52:14] [PASSED] DP_REMOTE_DPCD_READ with port number
[01:52:14] [PASSED] DP_REMOTE_DPCD_READ with DPCD address
[01:52:14] [PASSED] DP_REMOTE_DPCD_READ with max number of bytes
[01:52:14] [PASSED] DP_REMOTE_DPCD_WRITE with port number
[01:52:14] [PASSED] DP_REMOTE_DPCD_WRITE with DPCD address
[01:52:14] [PASSED] DP_REMOTE_DPCD_WRITE with data array
[01:52:14] [PASSED] DP_REMOTE_I2C_READ with port number
[01:52:14] [PASSED] DP_REMOTE_I2C_READ with I2C device ID
[01:52:14] [PASSED] DP_REMOTE_I2C_READ with transactions array
[01:52:14] [PASSED] DP_REMOTE_I2C_WRITE with port number
[01:52:14] [PASSED] DP_REMOTE_I2C_WRITE with I2C device ID
[01:52:14] [PASSED] DP_REMOTE_I2C_WRITE with data array
[01:52:14] [PASSED] DP_QUERY_STREAM_ENC_STATUS with stream ID
[01:52:14] [PASSED] DP_QUERY_STREAM_ENC_STATUS with client ID
[01:52:14] [PASSED] DP_QUERY_STREAM_ENC_STATUS with stream event
[01:52:14] [PASSED] DP_QUERY_STREAM_ENC_STATUS with valid stream event
[01:52:14] [PASSED] DP_QUERY_STREAM_ENC_STATUS with stream behavior
[01:52:14] [PASSED] DP_QUERY_STREAM_ENC_STATUS with a valid stream behavior
[01:52:14] ===== [PASSED] drm_test_dp_mst_sideband_msg_req_decode =====
[01:52:14] ================ [PASSED] drm_dp_mst_helper ================
[01:52:14] ================== drm_exec (7 subtests) ===================
[01:52:14] [PASSED] sanitycheck
[01:52:14] [PASSED] test_lock
[01:52:14] [PASSED] test_lock_unlock
[01:52:14] [PASSED] test_duplicates
[01:52:14] [PASSED] test_prepare
[01:52:14] [PASSED] test_prepare_array
[01:52:14] [PASSED] test_multiple_loops
[01:52:14] ==================== [PASSED] drm_exec =====================
[01:52:14] =========== drm_format_helper_test (17 subtests) ===========
[01:52:14] ============== drm_test_fb_xrgb8888_to_gray8  ==============
[01:52:14] [PASSED] single_pixel_source_buffer
[01:52:14] [PASSED] single_pixel_clip_rectangle
[01:52:14] [PASSED] well_known_colors
[01:52:14] [PASSED] destination_pitch
[01:52:14] ========== [PASSED] drm_test_fb_xrgb8888_to_gray8 ==========
[01:52:14] ============= drm_test_fb_xrgb8888_to_rgb332  ==============
[01:52:14] [PASSED] single_pixel_source_buffer
[01:52:14] [PASSED] single_pixel_clip_rectangle
[01:52:14] [PASSED] well_known_colors
[01:52:14] [PASSED] destination_pitch
[01:52:14] ========= [PASSED] drm_test_fb_xrgb8888_to_rgb332 ==========
[01:52:14] ============= drm_test_fb_xrgb8888_to_rgb565  ==============
[01:52:14] [PASSED] single_pixel_source_buffer
[01:52:14] [PASSED] single_pixel_clip_rectangle
[01:52:14] [PASSED] well_known_colors
[01:52:14] [PASSED] destination_pitch
[01:52:14] ========= [PASSED] drm_test_fb_xrgb8888_to_rgb565 ==========
[01:52:14] ============ drm_test_fb_xrgb8888_to_xrgb1555  =============
[01:52:14] [PASSED] single_pixel_source_buffer
[01:52:14] [PASSED] single_pixel_clip_rectangle
[01:52:14] [PASSED] well_known_colors
[01:52:14] [PASSED] destination_pitch
[01:52:14] ======== [PASSED] drm_test_fb_xrgb8888_to_xrgb1555 =========
[01:52:14] ============ drm_test_fb_xrgb8888_to_argb1555  =============
[01:52:14] [PASSED] single_pixel_source_buffer
[01:52:14] [PASSED] single_pixel_clip_rectangle
[01:52:14] [PASSED] well_known_colors
[01:52:14] [PASSED] destination_pitch
[01:52:14] ======== [PASSED] drm_test_fb_xrgb8888_to_argb1555 =========
[01:52:14] ============ drm_test_fb_xrgb8888_to_rgba5551  =============
[01:52:14] [PASSED] single_pixel_source_buffer
[01:52:14] [PASSED] single_pixel_clip_rectangle
[01:52:14] [PASSED] well_known_colors
[01:52:14] [PASSED] destination_pitch
[01:52:14] ======== [PASSED] drm_test_fb_xrgb8888_to_rgba5551 =========
[01:52:14] ============= drm_test_fb_xrgb8888_to_rgb888  ==============
[01:52:14] [PASSED] single_pixel_source_buffer
[01:52:14] [PASSED] single_pixel_clip_rectangle
[01:52:14] [PASSED] well_known_colors
[01:52:14] [PASSED] destination_pitch
[01:52:14] ========= [PASSED] drm_test_fb_xrgb8888_to_rgb888 ==========
[01:52:14] ============= drm_test_fb_xrgb8888_to_bgr888  ==============
[01:52:14] [PASSED] single_pixel_source_buffer
[01:52:14] [PASSED] single_pixel_clip_rectangle
[01:52:14] [PASSED] well_known_colors
[01:52:14] [PASSED] destination_pitch
[01:52:14] ========= [PASSED] drm_test_fb_xrgb8888_to_bgr888 ==========
[01:52:14] ============ drm_test_fb_xrgb8888_to_argb8888  =============
[01:52:14] [PASSED] single_pixel_source_buffer
[01:52:14] [PASSED] single_pixel_clip_rectangle
[01:52:14] [PASSED] well_known_colors
[01:52:14] [PASSED] destination_pitch
[01:52:14] ======== [PASSED] drm_test_fb_xrgb8888_to_argb8888 =========
[01:52:14] =========== drm_test_fb_xrgb8888_to_xrgb2101010  ===========
[01:52:14] [PASSED] single_pixel_source_buffer
[01:52:14] [PASSED] single_pixel_clip_rectangle
[01:52:14] [PASSED] well_known_colors
[01:52:14] [PASSED] destination_pitch
[01:52:14] ======= [PASSED] drm_test_fb_xrgb8888_to_xrgb2101010 =======
[01:52:14] =========== drm_test_fb_xrgb8888_to_argb2101010  ===========
[01:52:14] [PASSED] single_pixel_source_buffer
[01:52:14] [PASSED] single_pixel_clip_rectangle
[01:52:14] [PASSED] well_known_colors
[01:52:14] [PASSED] destination_pitch
[01:52:14] ======= [PASSED] drm_test_fb_xrgb8888_to_argb2101010 =======
[01:52:14] ============== drm_test_fb_xrgb8888_to_mono  ===============
[01:52:14] [PASSED] single_pixel_source_buffer
[01:52:14] [PASSED] single_pixel_clip_rectangle
[01:52:14] [PASSED] well_known_colors
[01:52:14] [PASSED] destination_pitch
[01:52:14] ========== [PASSED] drm_test_fb_xrgb8888_to_mono ===========
[01:52:14] ==================== drm_test_fb_swab  =====================
[01:52:14] [PASSED] single_pixel_source_buffer
[01:52:14] [PASSED] single_pixel_clip_rectangle
[01:52:14] [PASSED] well_known_colors
[01:52:14] [PASSED] destination_pitch
[01:52:14] ================ [PASSED] drm_test_fb_swab =================
[01:52:14] ============ drm_test_fb_xrgb8888_to_xbgr8888  =============
[01:52:14] [PASSED] single_pixel_source_buffer
[01:52:14] [PASSED] single_pixel_clip_rectangle
[01:52:14] [PASSED] well_known_colors
[01:52:14] [PASSED] destination_pitch
[01:52:14] ======== [PASSED] drm_test_fb_xrgb8888_to_xbgr8888 =========
[01:52:14] ============ drm_test_fb_xrgb8888_to_abgr8888  =============
[01:52:14] [PASSED] single_pixel_source_buffer
[01:52:14] [PASSED] single_pixel_clip_rectangle
[01:52:14] [PASSED] well_known_colors
[01:52:14] [PASSED] destination_pitch
[01:52:14] ======== [PASSED] drm_test_fb_xrgb8888_to_abgr8888 =========
[01:52:14] ================= drm_test_fb_clip_offset  =================
[01:52:14] [PASSED] pass through
[01:52:14] [PASSED] horizontal offset
[01:52:14] [PASSED] vertical offset
[01:52:14] [PASSED] horizontal and vertical offset
[01:52:14] [PASSED] horizontal offset (custom pitch)
[01:52:14] [PASSED] vertical offset (custom pitch)
[01:52:14] [PASSED] horizontal and vertical offset (custom pitch)
[01:52:14] ============= [PASSED] drm_test_fb_clip_offset =============
[01:52:14] =================== drm_test_fb_memcpy  ====================
[01:52:14] [PASSED] single_pixel_source_buffer: XR24 little-endian (0x34325258)
[01:52:14] [PASSED] single_pixel_source_buffer: XRA8 little-endian (0x38415258)
[01:52:14] [PASSED] single_pixel_source_buffer: YU24 little-endian (0x34325559)
[01:52:14] [PASSED] single_pixel_clip_rectangle: XB24 little-endian (0x34324258)
[01:52:14] [PASSED] single_pixel_clip_rectangle: XRA8 little-endian (0x38415258)
[01:52:14] [PASSED] single_pixel_clip_rectangle: YU24 little-endian (0x34325559)
[01:52:14] [PASSED] well_known_colors: XB24 little-endian (0x34324258)
[01:52:14] [PASSED] well_known_colors: XRA8 little-endian (0x38415258)
[01:52:14] [PASSED] well_known_colors: YU24 little-endian (0x34325559)
[01:52:14] [PASSED] destination_pitch: XB24 little-endian (0x34324258)
[01:52:14] [PASSED] destination_pitch: XRA8 little-endian (0x38415258)
[01:52:14] [PASSED] destination_pitch: YU24 little-endian (0x34325559)
[01:52:14] =============== [PASSED] drm_test_fb_memcpy ================
[01:52:14] ============= [PASSED] drm_format_helper_test ==============
[01:52:14] ================= drm_format (18 subtests) =================
[01:52:14] [PASSED] drm_test_format_block_width_invalid
[01:52:14] [PASSED] drm_test_format_block_width_one_plane
[01:52:14] [PASSED] drm_test_format_block_width_two_plane
[01:52:14] [PASSED] drm_test_format_block_width_three_plane
[01:52:14] [PASSED] drm_test_format_block_width_tiled
[01:52:14] [PASSED] drm_test_format_block_height_invalid
[01:52:14] [PASSED] drm_test_format_block_height_one_plane
[01:52:14] [PASSED] drm_test_format_block_height_two_plane
[01:52:14] [PASSED] drm_test_format_block_height_three_plane
[01:52:14] [PASSED] drm_test_format_block_height_tiled
[01:52:14] [PASSED] drm_test_format_min_pitch_invalid
[01:52:14] [PASSED] drm_test_format_min_pitch_one_plane_8bpp
[01:52:14] [PASSED] drm_test_format_min_pitch_one_plane_16bpp
[01:52:14] [PASSED] drm_test_format_min_pitch_one_plane_24bpp
[01:52:14] [PASSED] drm_test_format_min_pitch_one_plane_32bpp
[01:52:14] [PASSED] drm_test_format_min_pitch_two_plane
[01:52:14] [PASSED] drm_test_format_min_pitch_three_plane_8bpp
[01:52:14] [PASSED] drm_test_format_min_pitch_tiled
[01:52:14] =================== [PASSED] drm_format ====================
[01:52:14] ============== drm_framebuffer (10 subtests) ===============
[01:52:14] ========== drm_test_framebuffer_check_src_coords  ==========
[01:52:14] [PASSED] Success: source fits into fb
[01:52:14] [PASSED] Fail: overflowing fb with x-axis coordinate
[01:52:14] [PASSED] Fail: overflowing fb with y-axis coordinate
[01:52:14] [PASSED] Fail: overflowing fb with source width
[01:52:14] [PASSED] Fail: overflowing fb with source height
[01:52:14] ====== [PASSED] drm_test_framebuffer_check_src_coords ======
[01:52:14] [PASSED] drm_test_framebuffer_cleanup
[01:52:14] =============== drm_test_framebuffer_create  ===============
[01:52:14] [PASSED] ABGR8888 normal sizes
[01:52:14] [PASSED] ABGR8888 max sizes
[01:52:14] [PASSED] ABGR8888 pitch greater than min required
[01:52:14] [PASSED] ABGR8888 pitch less than min required
[01:52:14] [PASSED] ABGR8888 Invalid width
[01:52:14] [PASSED] ABGR8888 Invalid buffer handle
[01:52:14] [PASSED] No pixel format
[01:52:14] [PASSED] ABGR8888 Width 0
[01:52:14] [PASSED] ABGR8888 Height 0
[01:52:14] [PASSED] ABGR8888 Out of bound height * pitch combination
[01:52:14] [PASSED] ABGR8888 Large buffer offset
[01:52:14] [PASSED] ABGR8888 Buffer offset for inexistent plane
[01:52:14] [PASSED] ABGR8888 Invalid flag
[01:52:14] [PASSED] ABGR8888 Set DRM_MODE_FB_MODIFIERS without modifiers
[01:52:14] [PASSED] ABGR8888 Valid buffer modifier
[01:52:14] [PASSED] ABGR8888 Invalid buffer modifier(DRM_FORMAT_MOD_SAMSUNG_64_32_TILE)
[01:52:14] [PASSED] ABGR8888 Extra pitches without DRM_MODE_FB_MODIFIERS
[01:52:14] [PASSED] ABGR8888 Extra pitches with DRM_MODE_FB_MODIFIERS
[01:52:14] [PASSED] NV12 Normal sizes
[01:52:14] [PASSED] NV12 Max sizes
[01:52:14] [PASSED] NV12 Invalid pitch
[01:52:14] [PASSED] NV12 Invalid modifier/missing DRM_MODE_FB_MODIFIERS flag
[01:52:14] [PASSED] NV12 different  modifier per-plane
[01:52:14] [PASSED] NV12 with DRM_FORMAT_MOD_SAMSUNG_64_32_TILE
[01:52:14] [PASSED] NV12 Valid modifiers without DRM_MODE_FB_MODIFIERS
[01:52:14] [PASSED] NV12 Modifier for inexistent plane
[01:52:14] [PASSED] NV12 Handle for inexistent plane
[01:52:14] [PASSED] NV12 Handle for inexistent plane without DRM_MODE_FB_MODIFIERS
[01:52:14] [PASSED] YVU420 DRM_MODE_FB_MODIFIERS set without modifier
[01:52:14] [PASSED] YVU420 Normal sizes
[01:52:14] [PASSED] YVU420 Max sizes
[01:52:14] [PASSED] YVU420 Invalid pitch
[01:52:14] [PASSED] YVU420 Different pitches
[01:52:14] [PASSED] YVU420 Different buffer offsets/pitches
[01:52:14] [PASSED] YVU420 Modifier set just for plane 0, without DRM_MODE_FB_MODIFIERS
[01:52:14] [PASSED] YVU420 Modifier set just for planes 0, 1, without DRM_MODE_FB_MODIFIERS
[01:52:14] [PASSED] YVU420 Modifier set just for plane 0, 1, with DRM_MODE_FB_MODIFIERS
[01:52:14] [PASSED] YVU420 Valid modifier
[01:52:14] [PASSED] YVU420 Different modifiers per plane
[01:52:14] [PASSED] YVU420 Modifier for inexistent plane
[01:52:14] [PASSED] YUV420_10BIT Invalid modifier(DRM_FORMAT_MOD_LINEAR)
[01:52:14] [PASSED] X0L2 Normal sizes
[01:52:14] [PASSED] X0L2 Max sizes
[01:52:14] [PASSED] X0L2 Invalid pitch
[01:52:14] [PASSED] X0L2 Pitch greater than minimum required
[01:52:14] [PASSED] X0L2 Handle for inexistent plane
[01:52:14] [PASSED] X0L2 Offset for inexistent plane, without DRM_MODE_FB_MODIFIERS set
[01:52:14] [PASSED] X0L2 Modifier without DRM_MODE_FB_MODIFIERS set
[01:52:14] [PASSED] X0L2 Valid modifier
[01:52:14] [PASSED] X0L2 Modifier for inexistent plane
[01:52:14] =========== [PASSED] drm_test_framebuffer_create ===========
[01:52:14] [PASSED] drm_test_framebuffer_free
[01:52:14] [PASSED] drm_test_framebuffer_init
[01:52:14] [PASSED] drm_test_framebuffer_init_bad_format
[01:52:14] [PASSED] drm_test_framebuffer_init_dev_mismatch
[01:52:14] [PASSED] drm_test_framebuffer_lookup
[01:52:14] [PASSED] drm_test_framebuffer_lookup_inexistent
[01:52:14] [PASSED] drm_test_framebuffer_modifiers_not_supported
[01:52:14] ================= [PASSED] drm_framebuffer =================
[01:52:14] ================ drm_gem_shmem (8 subtests) ================
[01:52:14] [PASSED] drm_gem_shmem_test_obj_create
[01:52:14] [PASSED] drm_gem_shmem_test_obj_create_private
[01:52:14] [PASSED] drm_gem_shmem_test_pin_pages
[01:52:14] [PASSED] drm_gem_shmem_test_vmap
[01:52:14] [PASSED] drm_gem_shmem_test_get_pages_sgt
[01:52:14] [PASSED] drm_gem_shmem_test_get_sg_table
[01:52:14] [PASSED] drm_gem_shmem_test_madvise
[01:52:14] [PASSED] drm_gem_shmem_test_purge
[01:52:14] ================== [PASSED] drm_gem_shmem ==================
[01:52:14] === drm_atomic_helper_connector_hdmi_check (27 subtests) ===
[01:52:14] [PASSED] drm_test_check_broadcast_rgb_auto_cea_mode
[01:52:14] [PASSED] drm_test_check_broadcast_rgb_auto_cea_mode_vic_1
[01:52:14] [PASSED] drm_test_check_broadcast_rgb_full_cea_mode
[01:52:14] [PASSED] drm_test_check_broadcast_rgb_full_cea_mode_vic_1
[01:52:14] [PASSED] drm_test_check_broadcast_rgb_limited_cea_mode
[01:52:14] [PASSED] drm_test_check_broadcast_rgb_limited_cea_mode_vic_1
[01:52:14] ====== drm_test_check_broadcast_rgb_cea_mode_yuv420  =======
[01:52:14] [PASSED] Automatic
[01:52:14] [PASSED] Full
[01:52:14] [PASSED] Limited 16:235
[01:52:14] == [PASSED] drm_test_check_broadcast_rgb_cea_mode_yuv420 ===
[01:52:14] [PASSED] drm_test_check_broadcast_rgb_crtc_mode_changed
[01:52:14] [PASSED] drm_test_check_broadcast_rgb_crtc_mode_not_changed
[01:52:14] [PASSED] drm_test_check_disable_connector
[01:52:14] [PASSED] drm_test_check_hdmi_funcs_reject_rate
[01:52:14] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_rgb
[01:52:14] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_yuv420
[01:52:14] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_ignore_yuv422
[01:52:14] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_ignore_yuv420
[01:52:14] [PASSED] drm_test_check_driver_unsupported_fallback_yuv420
[01:52:14] [PASSED] drm_test_check_output_bpc_crtc_mode_changed
[01:52:14] [PASSED] drm_test_check_output_bpc_crtc_mode_not_changed
[01:52:14] [PASSED] drm_test_check_output_bpc_dvi
[01:52:14] [PASSED] drm_test_check_output_bpc_format_vic_1
[01:52:14] [PASSED] drm_test_check_output_bpc_format_display_8bpc_only
[01:52:14] [PASSED] drm_test_check_output_bpc_format_display_rgb_only
[01:52:14] [PASSED] drm_test_check_output_bpc_format_driver_8bpc_only
[01:52:14] [PASSED] drm_test_check_output_bpc_format_driver_rgb_only
[01:52:14] [PASSED] drm_test_check_tmds_char_rate_rgb_8bpc
[01:52:14] [PASSED] drm_test_check_tmds_char_rate_rgb_10bpc
[01:52:14] [PASSED] drm_test_check_tmds_char_rate_rgb_12bpc
[01:52:14] ===== [PASSED] drm_atomic_helper_connector_hdmi_check ======
[01:52:14] === drm_atomic_helper_connector_hdmi_reset (6 subtests) ====
[01:52:14] [PASSED] drm_test_check_broadcast_rgb_value
[01:52:14] [PASSED] drm_test_check_bpc_8_value
[01:52:14] [PASSED] drm_test_check_bpc_10_value
[01:52:14] [PASSED] drm_test_check_bpc_12_value
[01:52:14] [PASSED] drm_test_check_format_value
[01:52:14] [PASSED] drm_test_check_tmds_char_value
[01:52:14] ===== [PASSED] drm_atomic_helper_connector_hdmi_reset ======
[01:52:14] = drm_atomic_helper_connector_hdmi_mode_valid (4 subtests) =
[01:52:14] [PASSED] drm_test_check_mode_valid
[01:52:14] [PASSED] drm_test_check_mode_valid_reject
[01:52:14] [PASSED] drm_test_check_mode_valid_reject_rate
[01:52:14] [PASSED] drm_test_check_mode_valid_reject_max_clock
[01:52:14] === [PASSED] drm_atomic_helper_connector_hdmi_mode_valid ===
[01:52:14] ================= drm_managed (2 subtests) =================
[01:52:14] [PASSED] drm_test_managed_release_action
[01:52:14] [PASSED] drm_test_managed_run_action
[01:52:14] =================== [PASSED] drm_managed ===================
[01:52:14] =================== drm_mm (6 subtests) ====================
[01:52:14] [PASSED] drm_test_mm_init
[01:52:14] [PASSED] drm_test_mm_debug
[01:52:14] [PASSED] drm_test_mm_align32
[01:52:14] [PASSED] drm_test_mm_align64
[01:52:14] [PASSED] drm_test_mm_lowest
[01:52:14] [PASSED] drm_test_mm_highest
[01:52:14] ===================== [PASSED] drm_mm ======================
[01:52:14] ============= drm_modes_analog_tv (5 subtests) =============
[01:52:14] [PASSED] drm_test_modes_analog_tv_mono_576i
[01:52:14] [PASSED] drm_test_modes_analog_tv_ntsc_480i
[01:52:14] [PASSED] drm_test_modes_analog_tv_ntsc_480i_inlined
[01:52:14] [PASSED] drm_test_modes_analog_tv_pal_576i
[01:52:14] [PASSED] drm_test_modes_analog_tv_pal_576i_inlined
[01:52:14] =============== [PASSED] drm_modes_analog_tv ===============
[01:52:14] ============== drm_plane_helper (2 subtests) ===============
[01:52:14] =============== drm_test_check_plane_state  ================
[01:52:14] [PASSED] clipping_simple
[01:52:14] [PASSED] clipping_rotate_reflect
[01:52:14] [PASSED] positioning_simple
[01:52:14] [PASSED] upscaling
[01:52:14] [PASSED] downscaling
[01:52:14] [PASSED] rounding1
[01:52:14] [PASSED] rounding2
[01:52:14] [PASSED] rounding3
[01:52:14] [PASSED] rounding4
[01:52:14] =========== [PASSED] drm_test_check_plane_state ============
[01:52:14] =========== drm_test_check_invalid_plane_state  ============
[01:52:14] [PASSED] positioning_invalid
[01:52:14] [PASSED] upscaling_invalid
[01:52:14] [PASSED] downscaling_invalid
[01:52:14] ======= [PASSED] drm_test_check_invalid_plane_state ========
[01:52:14] ================ [PASSED] drm_plane_helper =================
[01:52:14] ====== drm_connector_helper_tv_get_modes (1 subtest) =======
[01:52:14] ====== drm_test_connector_helper_tv_get_modes_check  =======
[01:52:14] [PASSED] None
[01:52:14] [PASSED] PAL
[01:52:14] [PASSED] NTSC
[01:52:14] [PASSED] Both, NTSC Default
[01:52:14] [PASSED] Both, PAL Default
[01:52:14] [PASSED] Both, NTSC Default, with PAL on command-line
[01:52:14] [PASSED] Both, PAL Default, with NTSC on command-line
[01:52:14] == [PASSED] drm_test_connector_helper_tv_get_modes_check ===
[01:52:14] ======== [PASSED] drm_connector_helper_tv_get_modes ========
[01:52:14] ================== drm_rect (9 subtests) ===================
[01:52:14] [PASSED] drm_test_rect_clip_scaled_div_by_zero
[01:52:14] [PASSED] drm_test_rect_clip_scaled_not_clipped
[01:52:14] [PASSED] drm_test_rect_clip_scaled_clipped
[01:52:14] [PASSED] drm_test_rect_clip_scaled_signed_vs_unsigned
[01:52:14] ================= drm_test_rect_intersect  =================
[01:52:14] [PASSED] top-left x bottom-right: 2x2+1+1 x 2x2+0+0
[01:52:14] [PASSED] top-right x bottom-left: 2x2+0+0 x 2x2+1-1
[01:52:14] [PASSED] bottom-left x top-right: 2x2+1-1 x 2x2+0+0
[01:52:14] [PASSED] bottom-right x top-left: 2x2+0+0 x 2x2+1+1
[01:52:14] [PASSED] right x left: 2x1+0+0 x 3x1+1+0
[01:52:14] [PASSED] left x right: 3x1+1+0 x 2x1+0+0
[01:52:14] [PASSED] up x bottom: 1x2+0+0 x 1x3+0-1
[01:52:14] [PASSED] bottom x up: 1x3+0-1 x 1x2+0+0
[01:52:14] [PASSED] touching corner: 1x1+0+0 x 2x2+1+1
[01:52:14] [PASSED] touching side: 1x1+0+0 x 1x1+1+0
[01:52:14] [PASSED] equal rects: 2x2+0+0 x 2x2+0+0
[01:52:14] [PASSED] inside another: 2x2+0+0 x 1x1+1+1
[01:52:14] [PASSED] far away: 1x1+0+0 x 1x1+3+6
[01:52:14] [PASSED] points intersecting: 0x0+5+10 x 0x0+5+10
[01:52:14] [PASSED] points not intersecting: 0x0+0+0 x 0x0+5+10
[01:52:14] ============= [PASSED] drm_test_rect_intersect =============
[01:52:14] ================ drm_test_rect_calc_hscale  ================
[01:52:14] [PASSED] normal use
[01:52:14] [PASSED] out of max range
[01:52:14] [PASSED] out of min range
[01:52:14] [PASSED] zero dst
[01:52:14] [PASSED] negative src
[01:52:14] [PASSED] negative dst
[01:52:14] ============ [PASSED] drm_test_rect_calc_hscale ============
[01:52:14] ================ drm_test_rect_calc_vscale  ================
[01:52:14] [PASSED] normal use
stty: 'standard input': Inappropriate ioctl for device
[01:52:14] [PASSED] out of max range
[01:52:14] [PASSED] out of min range
[01:52:14] [PASSED] zero dst
[01:52:14] [PASSED] negative src
[01:52:14] [PASSED] negative dst
[01:52:14] ============ [PASSED] drm_test_rect_calc_vscale ============
[01:52:14] ================== drm_test_rect_rotate  ===================
[01:52:14] [PASSED] reflect-x
[01:52:14] [PASSED] reflect-y
[01:52:14] [PASSED] rotate-0
[01:52:14] [PASSED] rotate-90
[01:52:14] [PASSED] rotate-180
[01:52:14] [PASSED] rotate-270
[01:52:14] ============== [PASSED] drm_test_rect_rotate ===============
[01:52:14] ================ drm_test_rect_rotate_inv  =================
[01:52:14] [PASSED] reflect-x
[01:52:14] [PASSED] reflect-y
[01:52:14] [PASSED] rotate-0
[01:52:14] [PASSED] rotate-90
[01:52:14] [PASSED] rotate-180
[01:52:14] [PASSED] rotate-270
[01:52:14] ============ [PASSED] drm_test_rect_rotate_inv =============
[01:52:14] ==================== [PASSED] drm_rect =====================
[01:52:14] ============ drm_sysfb_modeset_test (1 subtest) ============
[01:52:14] ============ drm_test_sysfb_build_fourcc_list  =============
[01:52:14] [PASSED] no native formats
[01:52:14] [PASSED] XRGB8888 as native format
[01:52:14] [PASSED] remove duplicates
[01:52:14] [PASSED] convert alpha formats
[01:52:14] [PASSED] random formats
[01:52:14] ======== [PASSED] drm_test_sysfb_build_fourcc_list =========
[01:52:14] ============= [PASSED] drm_sysfb_modeset_test ==============
[01:52:14] ============================================================
[01:52:14] Testing complete. Ran 622 tests: passed: 622
[01:52:15] Elapsed time: 26.968s total, 1.698s configuring, 24.852s building, 0.389s running

+ /kernel/tools/testing/kunit/kunit.py run --kunitconfig /kernel/drivers/gpu/drm/ttm/tests/.kunitconfig
[01:52:15] Configuring KUnit Kernel ...
Regenerating .config ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
[01:52:16] Building KUnit Kernel ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
Building with:
$ make all compile_commands.json scripts_gdb ARCH=um O=.kunit --jobs=48
[01:52:26] Starting KUnit Kernel (1/1)...
[01:52:26] ============================================================
Running tests with:
$ .kunit/linux kunit.enable=1 mem=1G console=tty kunit_shutdown=halt
[01:52:26] ================= ttm_device (5 subtests) ==================
[01:52:26] [PASSED] ttm_device_init_basic
[01:52:26] [PASSED] ttm_device_init_multiple
[01:52:26] [PASSED] ttm_device_fini_basic
[01:52:26] [PASSED] ttm_device_init_no_vma_man
[01:52:26] ================== ttm_device_init_pools  ==================
[01:52:26] [PASSED] No DMA allocations, no DMA32 required
[01:52:26] [PASSED] DMA allocations, DMA32 required
[01:52:26] [PASSED] No DMA allocations, DMA32 required
[01:52:26] [PASSED] DMA allocations, no DMA32 required
[01:52:26] ============== [PASSED] ttm_device_init_pools ==============
[01:52:26] =================== [PASSED] ttm_device ====================
[01:52:26] ================== ttm_pool (8 subtests) ===================
[01:52:26] ================== ttm_pool_alloc_basic  ===================
[01:52:26] [PASSED] One page
[01:52:26] [PASSED] More than one page
[01:52:26] [PASSED] Above the allocation limit
[01:52:26] [PASSED] One page, with coherent DMA mappings enabled
[01:52:26] [PASSED] Above the allocation limit, with coherent DMA mappings enabled
[01:52:26] ============== [PASSED] ttm_pool_alloc_basic ===============
[01:52:26] ============== ttm_pool_alloc_basic_dma_addr  ==============
[01:52:26] [PASSED] One page
[01:52:26] [PASSED] More than one page
[01:52:26] [PASSED] Above the allocation limit
[01:52:26] [PASSED] One page, with coherent DMA mappings enabled
[01:52:26] [PASSED] Above the allocation limit, with coherent DMA mappings enabled
[01:52:26] ========== [PASSED] ttm_pool_alloc_basic_dma_addr ==========
[01:52:26] [PASSED] ttm_pool_alloc_order_caching_match
[01:52:26] [PASSED] ttm_pool_alloc_caching_mismatch
[01:52:26] [PASSED] ttm_pool_alloc_order_mismatch
[01:52:26] [PASSED] ttm_pool_free_dma_alloc
[01:52:26] [PASSED] ttm_pool_free_no_dma_alloc
[01:52:26] [PASSED] ttm_pool_fini_basic
[01:52:26] ==================== [PASSED] ttm_pool =====================
[01:52:26] ================ ttm_resource (8 subtests) =================
[01:52:26] ================= ttm_resource_init_basic  =================
[01:52:26] [PASSED] Init resource in TTM_PL_SYSTEM
[01:52:26] [PASSED] Init resource in TTM_PL_VRAM
[01:52:26] [PASSED] Init resource in a private placement
[01:52:26] [PASSED] Init resource in TTM_PL_SYSTEM, set placement flags
[01:52:26] ============= [PASSED] ttm_resource_init_basic =============
[01:52:26] [PASSED] ttm_resource_init_pinned
[01:52:26] [PASSED] ttm_resource_fini_basic
[01:52:26] [PASSED] ttm_resource_manager_init_basic
[01:52:26] [PASSED] ttm_resource_manager_usage_basic
[01:52:26] [PASSED] ttm_resource_manager_set_used_basic
[01:52:26] [PASSED] ttm_sys_man_alloc_basic
[01:52:26] [PASSED] ttm_sys_man_free_basic
[01:52:26] ================== [PASSED] ttm_resource ===================
[01:52:26] =================== ttm_tt (15 subtests) ===================
[01:52:26] ==================== ttm_tt_init_basic  ====================
[01:52:26] [PASSED] Page-aligned size
[01:52:26] [PASSED] Extra pages requested
[01:52:26] ================ [PASSED] ttm_tt_init_basic ================
[01:52:26] [PASSED] ttm_tt_init_misaligned
[01:52:26] [PASSED] ttm_tt_fini_basic
[01:52:26] [PASSED] ttm_tt_fini_sg
[01:52:26] [PASSED] ttm_tt_fini_shmem
[01:52:26] [PASSED] ttm_tt_create_basic
[01:52:26] [PASSED] ttm_tt_create_invalid_bo_type
[01:52:26] [PASSED] ttm_tt_create_ttm_exists
[01:52:26] [PASSED] ttm_tt_create_failed
[01:52:26] [PASSED] ttm_tt_destroy_basic
[01:52:26] [PASSED] ttm_tt_populate_null_ttm
[01:52:26] [PASSED] ttm_tt_populate_populated_ttm
[01:52:26] [PASSED] ttm_tt_unpopulate_basic
[01:52:26] [PASSED] ttm_tt_unpopulate_empty_ttm
[01:52:26] [PASSED] ttm_tt_swapin_basic
[01:52:26] ===================== [PASSED] ttm_tt ======================
[01:52:26] =================== ttm_bo (14 subtests) ===================
[01:52:26] =========== ttm_bo_reserve_optimistic_no_ticket  ===========
[01:52:26] [PASSED] Cannot be interrupted and sleeps
[01:52:26] [PASSED] Cannot be interrupted, locks straight away
[01:52:26] [PASSED] Can be interrupted, sleeps
[01:52:26] ======= [PASSED] ttm_bo_reserve_optimistic_no_ticket =======
[01:52:26] [PASSED] ttm_bo_reserve_locked_no_sleep
[01:52:26] [PASSED] ttm_bo_reserve_no_wait_ticket
[01:52:26] [PASSED] ttm_bo_reserve_double_resv
[01:52:26] [PASSED] ttm_bo_reserve_interrupted
[01:52:26] [PASSED] ttm_bo_reserve_deadlock
[01:52:26] [PASSED] ttm_bo_unreserve_basic
[01:52:26] [PASSED] ttm_bo_unreserve_pinned
[01:52:26] [PASSED] ttm_bo_unreserve_bulk
[01:52:26] [PASSED] ttm_bo_fini_basic
[01:52:26] [PASSED] ttm_bo_fini_shared_resv
[01:52:26] [PASSED] ttm_bo_pin_basic
[01:52:26] [PASSED] ttm_bo_pin_unpin_resource
[01:52:26] [PASSED] ttm_bo_multiple_pin_one_unpin
[01:52:26] ===================== [PASSED] ttm_bo ======================
[01:52:26] ============== ttm_bo_validate (21 subtests) ===============
[01:52:26] ============== ttm_bo_init_reserved_sys_man  ===============
[01:52:26] [PASSED] Buffer object for userspace
[01:52:26] [PASSED] Kernel buffer object
[01:52:26] [PASSED] Shared buffer object
[01:52:26] ========== [PASSED] ttm_bo_init_reserved_sys_man ===========
[01:52:26] ============== ttm_bo_init_reserved_mock_man  ==============
[01:52:26] [PASSED] Buffer object for userspace
[01:52:26] [PASSED] Kernel buffer object
[01:52:26] [PASSED] Shared buffer object
[01:52:26] ========== [PASSED] ttm_bo_init_reserved_mock_man ==========
[01:52:26] [PASSED] ttm_bo_init_reserved_resv
[01:52:26] ================== ttm_bo_validate_basic  ==================
[01:52:26] [PASSED] Buffer object for userspace
[01:52:26] [PASSED] Kernel buffer object
[01:52:26] [PASSED] Shared buffer object
[01:52:26] ============== [PASSED] ttm_bo_validate_basic ==============
[01:52:26] [PASSED] ttm_bo_validate_invalid_placement
[01:52:26] ============= ttm_bo_validate_same_placement  ==============
[01:52:26] [PASSED] System manager
[01:52:26] [PASSED] VRAM manager
[01:52:26] ========= [PASSED] ttm_bo_validate_same_placement ==========
[01:52:26] [PASSED] ttm_bo_validate_failed_alloc
[01:52:26] [PASSED] ttm_bo_validate_pinned
[01:52:26] [PASSED] ttm_bo_validate_busy_placement
[01:52:26] ================ ttm_bo_validate_multihop  =================
[01:52:26] [PASSED] Buffer object for userspace
[01:52:26] [PASSED] Kernel buffer object
[01:52:26] [PASSED] Shared buffer object
[01:52:26] ============ [PASSED] ttm_bo_validate_multihop =============
[01:52:26] ========== ttm_bo_validate_no_placement_signaled  ==========
[01:52:26] [PASSED] Buffer object in system domain, no page vector
[01:52:26] [PASSED] Buffer object in system domain with an existing page vector
[01:52:26] ====== [PASSED] ttm_bo_validate_no_placement_signaled ======
[01:52:26] ======== ttm_bo_validate_no_placement_not_signaled  ========
[01:52:26] [PASSED] Buffer object for userspace
[01:52:26] [PASSED] Kernel buffer object
[01:52:26] [PASSED] Shared buffer object
[01:52:26] ==== [PASSED] ttm_bo_validate_no_placement_not_signaled ====
[01:52:26] [PASSED] ttm_bo_validate_move_fence_signaled
[01:52:26] ========= ttm_bo_validate_move_fence_not_signaled  =========
[01:52:26] [PASSED] Waits for GPU
[01:52:26] [PASSED] Tries to lock straight away
[01:52:26] ===== [PASSED] ttm_bo_validate_move_fence_not_signaled =====
[01:52:26] [PASSED] ttm_bo_validate_happy_evict
[01:52:26] [PASSED] ttm_bo_validate_all_pinned_evict
[01:52:26] [PASSED] ttm_bo_validate_allowed_only_evict
[01:52:26] [PASSED] ttm_bo_validate_deleted_evict
[01:52:26] [PASSED] ttm_bo_validate_busy_domain_evict
[01:52:26] [PASSED] ttm_bo_validate_evict_gutting
[01:52:26] [PASSED] ttm_bo_validate_recrusive_evict
stty: 'standard input': Inappropriate ioctl for device
[01:52:26] ================= [PASSED] ttm_bo_validate =================
[01:52:26] ============================================================
[01:52:26] Testing complete. Ran 101 tests: passed: 101
[01:52:26] Elapsed time: 11.335s total, 1.701s configuring, 9.367s building, 0.225s running

+ cleanup
++ stat -c %u:%g /kernel
+ chown -R 1003:1003 /kernel

✓ Xe.CI.BAT: success for drm/i915/dp: Fix panel replay in DSC mode (rev2)

[Patchwork]

[-- Attachment #1: Type: text/plain, Size: 871 bytes --]

== Series Details ==

Series: drm/i915/dp: Fix panel replay in DSC mode (rev2)
URL   : https://patchwork.freedesktop.org/series/155586/
State : success

== Summary ==

CI Bug Log - changes from xe-3928-f019aaad58112f89234f7b68557c831846437008_BAT -> xe-pw-155586v2_BAT
====================================================

Summary
-------

  **SUCCESS**

  No regressions found.

  

Participating hosts (11 -> 11)
------------------------------

  No changes in participating hosts


Changes
-------

  No changes found


Build changes
-------------

  * Linux: xe-3928-f019aaad58112f89234f7b68557c831846437008 -> xe-pw-155586v2

  IGT_8587: 8587
  xe-3928-f019aaad58112f89234f7b68557c831846437008: f019aaad58112f89234f7b68557c831846437008
  xe-pw-155586v2: 155586v2

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155586v2/index.html

[-- Attachment #2: Type: text/html, Size: 1419 bytes --]

Re: [PATCH v2 7/7] drm/i915/dp: Fix panel replay when DSC is enabled

[Hogander, Jouni]

On Wed, 2025-10-15 at 19:19 +0300, Imre Deak wrote:
> Prevent enabling panel replay if the sink doesn't support this due to
> DSC being enabled.
> 
> Panel replay has two modes, updating full frames or only selected
> regions of the frame. If the sink doesn't support Panel Replay in
> full
> frame update mode with DSC prevent Panel Replay completely if DSC is
> enabled. If the sink doesn't support Panel Replay only in the
> selective
> update mode while DSC is enabled, it will still support Panel Replay
> in
> the full frame update mode, so only prevent selective updates in this
> case.
> 
> v2:
> - Use Panel Replay instead of PR in debug prints. (Jouni)
> - Rebase on change tracking the link DSC state in the crtc state.
> 
> Cc: Jouni Högander <jouni.hogander@intel.com>
> Closes: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/14869
> Signed-off-by: Imre Deak <imre.deak@intel.com>

Reviewed-by: Jouni Högander <jouni.hogander@intel.com>

> ---
>  .../drm/i915/display/intel_display_types.h    |  9 ++
>  drivers/gpu/drm/i915/display/intel_dp.c       |  2 +
>  drivers/gpu/drm/i915/display/intel_psr.c      | 93
> ++++++++++++++++++-
>  3 files changed, 99 insertions(+), 5 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h
> b/drivers/gpu/drm/i915/display/intel_display_types.h
> index 58308146697ff..67386daecc16d 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_types.h
> +++ b/drivers/gpu/drm/i915/display/intel_display_types.h
> @@ -955,6 +955,12 @@ struct intel_csc_matrix {
>  	u16 postoff[3];
>  };
>  
> +enum intel_panel_replay_dsc_support {
> +	INTEL_DP_PANEL_REPLAY_DSC_NOT_SUPPORTED,
> +	INTEL_DP_PANEL_REPLAY_DSC_FULL_FRAME_ONLY,
> +	INTEL_DP_PANEL_REPLAY_DSC_SELECTIVE_UPDATE,
> +};
> +
>  struct intel_crtc_state {
>  	/*
>  	 * uapi (drm) state. This is the software state shown to
> userspace.
> @@ -1133,6 +1139,8 @@ struct intel_crtc_state {
>  	bool has_panel_replay;
>  	bool wm_level_disabled;
>  	bool pkg_c_latency_used;
> +	/* Only used for state verification. */
> +	enum intel_panel_replay_dsc_support
> panel_replay_dsc_support;
>  	u32 dc3co_exitline;
>  	u16 su_y_granularity;
>  	u8 active_non_psr_pipes;
> @@ -1704,6 +1712,7 @@ struct intel_psr {
>  	bool source_panel_replay_support;
>  	bool sink_panel_replay_support;
>  	bool sink_panel_replay_su_support;
> +	enum intel_panel_replay_dsc_support
> sink_panel_replay_dsc_support;
>  	bool panel_replay_enabled;
>  	u32 dc3co_exitline;
>  	u32 dc3co_exit_delay;
> diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
> b/drivers/gpu/drm/i915/display/intel_dp.c
> index 8ba931204cb52..799e69a65e712 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> @@ -6053,6 +6053,8 @@ intel_dp_detect(struct drm_connector
> *_connector,
>  		memset(connector->dp.dsc_dpcd, 0, sizeof(connector-
> >dp.dsc_dpcd));
>  		intel_dp->psr.sink_panel_replay_support = false;
>  		intel_dp->psr.sink_panel_replay_su_support = false;
> +		intel_dp->psr.sink_panel_replay_dsc_support =
> +			INTEL_DP_PANEL_REPLAY_DSC_NOT_SUPPORTED;
>  
>  		intel_dp_mst_disconnect(intel_dp);
>  
> diff --git a/drivers/gpu/drm/i915/display/intel_psr.c
> b/drivers/gpu/drm/i915/display/intel_psr.c
> index 2131473cead6d..c266807f5d36f 100644
> --- a/drivers/gpu/drm/i915/display/intel_psr.c
> +++ b/drivers/gpu/drm/i915/display/intel_psr.c
> @@ -29,6 +29,7 @@
>  #include <drm/drm_vblank.h>
>  
>  #include "i915_reg.h"
> +#include "i915_utils.h"
>  #include "intel_alpm.h"
>  #include "intel_atomic.h"
>  #include "intel_crtc.h"
> @@ -50,6 +51,7 @@
>  #include "intel_snps_phy.h"
>  #include "intel_step.h"
>  #include "intel_vblank.h"
> +#include "intel_vdsc.h"
>  #include "intel_vrr.h"
>  #include "skl_universal_plane.h"
>  
> @@ -580,6 +582,44 @@ static void intel_dp_get_su_granularity(struct
> intel_dp *intel_dp)
>  	intel_dp->psr.su_y_granularity = y;
>  }
>  
> +static enum intel_panel_replay_dsc_support
> +compute_pr_dsc_support(struct intel_dp *intel_dp)
> +{
> +	u8 pr_dsc_mode;
> +	u8 val;
> +
> +	val = intel_dp-
> >pr_dpcd[INTEL_PR_DPCD_INDEX(DP_PANEL_REPLAY_CAP_CAPABILITY)];
> +	pr_dsc_mode =
> REG_FIELD_GET8(DP_PANEL_REPLAY_DSC_DECODE_CAPABILITY_IN_PR_MASK,
> val);
> +
> +	switch (pr_dsc_mode) {
> +	case DP_DSC_DECODE_CAPABILITY_IN_PR_FULL_FRAME_ONLY:
> +		return INTEL_DP_PANEL_REPLAY_DSC_FULL_FRAME_ONLY;
> +	case DP_DSC_DECODE_CAPABILITY_IN_PR_SUPPORTED:
> +		return INTEL_DP_PANEL_REPLAY_DSC_SELECTIVE_UPDATE;
> +	default:
> +		MISSING_CASE(pr_dsc_mode);
> +		fallthrough;
> +	case DP_DSC_DECODE_CAPABILITY_IN_PR_NOT_SUPPORTED:
> +	case DP_DSC_DECODE_CAPABILITY_IN_PR_RESERVED:
> +		return INTEL_DP_PANEL_REPLAY_DSC_NOT_SUPPORTED;
> +	}
> +}
> +
> +static const char *panel_replay_dsc_support_str(enum
> intel_panel_replay_dsc_support dsc_support)
> +{
> +	switch (dsc_support) {
> +	case INTEL_DP_PANEL_REPLAY_DSC_NOT_SUPPORTED:
> +		return "not supported";
> +	case INTEL_DP_PANEL_REPLAY_DSC_FULL_FRAME_ONLY:
> +		return "full frame only";
> +	case INTEL_DP_PANEL_REPLAY_DSC_SELECTIVE_UPDATE:
> +		return "selective update";
> +	default:
> +		MISSING_CASE(dsc_support);
> +		return "n/a";
> +	};
> +}
> +
>  static void _panel_replay_init_dpcd(struct intel_dp *intel_dp)
>  {
>  	struct intel_display *display = to_intel_display(intel_dp);
> @@ -615,10 +655,13 @@ static void _panel_replay_init_dpcd(struct
> intel_dp *intel_dp)
>  	    DP_PANEL_REPLAY_SU_SUPPORT)
>  		intel_dp->psr.sink_panel_replay_su_support = true;
>  
> +	intel_dp->psr.sink_panel_replay_dsc_support =
> compute_pr_dsc_support(intel_dp);
> +
>  	drm_dbg_kms(display->drm,
> -		    "Panel replay %sis supported by panel\n",
> +		    "Panel replay %sis supported by panel (in DSC
> mode: %s)\n",
>  		    intel_dp->psr.sink_panel_replay_su_support ?
> -		    "selective_update " : "");
> +		    "selective_update " : "",
> +		    panel_replay_dsc_support_str(intel_dp-
> >psr.sink_panel_replay_dsc_support));
>  }
>  
>  static void _psr_init_dpcd(struct intel_dp *intel_dp)
> @@ -1537,9 +1580,21 @@ static bool
> intel_sel_update_config_valid(struct intel_dp *intel_dp,
>  		goto unsupported;
>  	}
>  
> -	if (crtc_state->has_panel_replay && (DISPLAY_VER(display) <
> 14 ||
> -					     !intel_dp-
> >psr.sink_panel_replay_su_support))
> -		goto unsupported;
> +	if (crtc_state->has_panel_replay) {
> +		if (DISPLAY_VER(display) < 14)
> +			goto unsupported;
> +
> +		if (!intel_dp->psr.sink_panel_replay_su_support)
> +			goto unsupported;
> +
> +		if (intel_dsc_enabled_on_link(crtc_state) &&
> +		    intel_dp->psr.sink_panel_replay_dsc_support !=
> +		    INTEL_DP_PANEL_REPLAY_DSC_SELECTIVE_UPDATE) {
> +			drm_dbg_kms(display->drm,
> +				    "Selective update with Panel
> Replay not enabled because it's not supported with DSC\n");
> +			goto unsupported;
> +		}
> +	}
>  
>  	if (crtc_state->crc_enabled) {
>  		drm_dbg_kms(display->drm,
> @@ -1616,6 +1671,14 @@ _panel_replay_compute_config(struct intel_dp
> *intel_dp,
>  		return false;
>  	}
>  
> +	if (intel_dsc_enabled_on_link(crtc_state) &&
> +	    intel_dp->psr.sink_panel_replay_dsc_support ==
> +	    INTEL_DP_PANEL_REPLAY_DSC_NOT_SUPPORTED) {
> +		drm_dbg_kms(display->drm,
> +			    "Panel Replay not enabled because it's
> not supported with DSC\n");
> +		return false;
> +	}
> +
>  	if (!intel_dp_is_edp(intel_dp))
>  		return true;
>  
> @@ -1696,6 +1759,8 @@ void intel_psr_compute_config(struct intel_dp
> *intel_dp,
>  		return;
>  	}
>  
> +	/* Only used for state verification. */
> +	crtc_state->panel_replay_dsc_support = intel_dp-
> >psr.sink_panel_replay_dsc_support;
>  	crtc_state->has_panel_replay =
> _panel_replay_compute_config(intel_dp,
>  								   
> crtc_state,
>  								   
> conn_state);
> @@ -2955,6 +3020,20 @@ void intel_psr_pre_plane_update(struct
> intel_atomic_state *state,
>  	}
>  }
>  
> +static void
> +verify_panel_replay_dsc_state(const struct intel_crtc_state
> *crtc_state)
> +{
> +	struct intel_display *display =
> to_intel_display(crtc_state);
> +
> +	if (!crtc_state->has_panel_replay)
> +		return;
> +
> +	drm_WARN_ON(display->drm,
> +		    intel_dsc_enabled_on_link(crtc_state) &&
> +		    crtc_state->panel_replay_dsc_support ==
> +		    INTEL_DP_PANEL_REPLAY_DSC_NOT_SUPPORTED);
> +}
> +
>  void intel_psr_post_plane_update(struct intel_atomic_state *state,
>  				 struct intel_crtc *crtc)
>  {
> @@ -2966,6 +3045,8 @@ void intel_psr_post_plane_update(struct
> intel_atomic_state *state,
>  	if (!crtc_state->has_psr)
>  		return;
>  
> +	verify_panel_replay_dsc_state(crtc_state);
> +
>  	for_each_intel_encoder_mask_with_psr(state->base.dev,
> encoder,
>  					     crtc_state-
> >uapi.encoder_mask) {
>  		struct intel_dp *intel_dp =
> enc_to_intel_dp(encoder);
> @@ -3995,6 +4076,8 @@ static void intel_psr_sink_capability(struct
> intel_dp *intel_dp,
>  	seq_printf(m, ", Panel Replay = %s", str_yes_no(psr-
> >sink_panel_replay_support));
>  	seq_printf(m, ", Panel Replay Selective Update = %s",
>  		   str_yes_no(psr->sink_panel_replay_su_support));
> +	seq_printf(m, ", Panel Replay DSC support = %s",
> +		   panel_replay_dsc_support_str(psr-
> >sink_panel_replay_dsc_support));
>  	if (intel_dp-
> >pr_dpcd[INTEL_PR_DPCD_INDEX(DP_PANEL_REPLAY_CAP_SUPPORT)] &
>  	    DP_PANEL_REPLAY_EARLY_TRANSPORT_SUPPORT)
>  		seq_printf(m, " (Early Transport)");

Re: [PATCH v2 1/7] drm/i915/dsc: Add helper to enable the DSC configuration for a CRTC

[Hogander, Jouni]

On Wed, 2025-10-15 at 19:19 +0300, Imre Deak wrote:
> Add a helper to enable the DSC compression configuration for a CRTC.
> Follow-up changes will introduce tracking for the same DSC state on
> the
> whole link, which will need to be set whenever DSC is enabled for the
> CRTC. Also, according to the above, when querying the DSC state on
> the
> link, both the CRTC's and the link's DSC state must be considered.
> 
> Setting the DSC configuration for a CRTC and querying the DSC
> configuration for the link (added by follow-up changes) is better
> done
> via helper functions based on the above, prepare for that here.
> 
> Signed-off-by: Imre Deak <imre.deak@intel.com>

Reviewed-by: Jouni Högander <jouni.hogander@intel.com>
> ---
>  drivers/gpu/drm/i915/display/icl_dsi.c    | 2 +-
>  drivers/gpu/drm/i915/display/intel_dp.c   | 3 ++-
>  drivers/gpu/drm/i915/display/intel_vdsc.c | 5 +++++
>  drivers/gpu/drm/i915/display/intel_vdsc.h | 1 +
>  4 files changed, 9 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/icl_dsi.c
> b/drivers/gpu/drm/i915/display/icl_dsi.c
> index 37faa8f19f6e4..297368ff42a5e 100644
> --- a/drivers/gpu/drm/i915/display/icl_dsi.c
> +++ b/drivers/gpu/drm/i915/display/icl_dsi.c
> @@ -1655,7 +1655,7 @@ static int gen11_dsi_dsc_compute_config(struct
> intel_encoder *encoder,
>  	if (ret)
>  		return ret;
>  
> -	crtc_state->dsc.compression_enable = true;
> +	intel_dsc_enable_on_crtc(crtc_state);
>  
>  	return 0;
>  }
> diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
> b/drivers/gpu/drm/i915/display/intel_dp.c
> index a723e846321fd..1d3ca1970f25f 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> @@ -2475,7 +2475,8 @@ int intel_dp_dsc_compute_config(struct intel_dp
> *intel_dp,
>  		return ret;
>  	}
>  
> -	pipe_config->dsc.compression_enable = true;
> +	intel_dsc_enable_on_crtc(pipe_config);
> +
>  	drm_dbg_kms(display->drm, "DP DSC computed with Input Bpp =
> %d "
>  		    "Compressed Bpp = " FXP_Q4_FMT " Slice Count =
> %d\n",
>  		    pipe_config->pipe_bpp,
> diff --git a/drivers/gpu/drm/i915/display/intel_vdsc.c
> b/drivers/gpu/drm/i915/display/intel_vdsc.c
> index 8e799e225af17..64a1e9f0a1893 100644
> --- a/drivers/gpu/drm/i915/display/intel_vdsc.c
> +++ b/drivers/gpu/drm/i915/display/intel_vdsc.c
> @@ -372,6 +372,11 @@ int intel_dsc_compute_params(struct
> intel_crtc_state *pipe_config)
>  	return 0;
>  }
>  
> +void intel_dsc_enable_on_crtc(struct intel_crtc_state *crtc_state)
> +{
> +	crtc_state->dsc.compression_enable = true;
> +}
> +
>  enum intel_display_power_domain
>  intel_dsc_power_domain(struct intel_crtc *crtc, enum transcoder
> cpu_transcoder)
>  {
> diff --git a/drivers/gpu/drm/i915/display/intel_vdsc.h
> b/drivers/gpu/drm/i915/display/intel_vdsc.h
> index 9e2812f99dd74..240bef82d3576 100644
> --- a/drivers/gpu/drm/i915/display/intel_vdsc.h
> +++ b/drivers/gpu/drm/i915/display/intel_vdsc.h
> @@ -20,6 +20,7 @@ void intel_uncompressed_joiner_enable(const struct
> intel_crtc_state *crtc_state)
>  void intel_dsc_enable(const struct intel_crtc_state *crtc_state);
>  void intel_dsc_disable(const struct intel_crtc_state *crtc_state);
>  int intel_dsc_compute_params(struct intel_crtc_state *pipe_config);
> +void intel_dsc_enable_on_crtc(struct intel_crtc_state *crtc_state);
>  void intel_dsc_get_config(struct intel_crtc_state *crtc_state);
>  enum intel_display_power_domain
>  intel_dsc_power_domain(struct intel_crtc *crtc, enum transcoder
> cpu_transcoder);

Re: [PATCH v2 2/7] drm/i915/dp: Ensure the FEC state stays disabled for UHBR links

[Hogander, Jouni]

On Wed, 2025-10-15 at 19:19 +0300, Imre Deak wrote:
> Atm, in the DP SST case the FEC state is computed before
> intel_crtc_state::port_clock is initialized, hence intel_dp_is_uhbr()
> will always return false and the FEC state will be always computed
> assuming a non-UHBR link.
> 
> This happens to work, since the FEC state is recomputed later in
> intel_dp_mtp_tu_compute_config(), where port_clock will be set
> already,
> so intel_crtc_state::fec_enable will be reset as expected for UHBR.
> This
> also depends on link rates being tried in an increasing order (i.e.
> from
> non-UHBR -> UHBR link rates) in dsc_compute_link_config(), thus
> intel_crtc_state::fec_enable being set for the non-UHBR rates and
> getting reset for the first UHBR rate as expected.
> 
> A follow-up change will reuse intel_dp_fec_compute_config() for the
> DP
> MST state computation, prepare for that here, making sure that the
> function determines the correct intel_crtc_state::fec_enable=false
> state
> for UHBR link rates based on the above.
> 
> The DP SST and MST state computation should be further unified to
> avoid
> computing/setting the intel_crtc_state::fec_enable state multiple
> times,
> but that's left for a follow-up change. For now add only code
> comments
> about this.
> 
> Signed-off-by: Imre Deak <imre.deak@intel.com>

Reviewed-by: Jouni Högander <jouni.hogander@intel.com>

> ---
>  drivers/gpu/drm/i915/display/intel_dp.c     | 10 +++++++---
>  drivers/gpu/drm/i915/display/intel_dp_mst.c |  5 +++++
>  2 files changed, 12 insertions(+), 3 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
> b/drivers/gpu/drm/i915/display/intel_dp.c
> index 1d3ca1970f25f..b523c4e661412 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> @@ -2368,6 +2368,9 @@ static int
> intel_edp_dsc_compute_pipe_bpp(struct intel_dp *intel_dp,
>  static void intel_dp_fec_compute_config(struct intel_dp *intel_dp,
>  					struct intel_crtc_state
> *crtc_state)
>  {
> +	if (intel_dp_is_uhbr(crtc_state))
> +		return;
> +
>  	if (crtc_state->fec_enable)
>  		return;
>  
> @@ -2379,9 +2382,6 @@ static void intel_dp_fec_compute_config(struct
> intel_dp *intel_dp,
>  	if (intel_dp_is_edp(intel_dp))
>  		return;
>  
> -	if (intel_dp_is_uhbr(crtc_state))
> -		return;
> -
>  	crtc_state->fec_enable = true;
>  }
>  
> @@ -2400,6 +2400,10 @@ int intel_dp_dsc_compute_config(struct
> intel_dp *intel_dp,
>  	bool is_mst = intel_crtc_has_type(pipe_config,
> INTEL_OUTPUT_DP_MST);
>  	int ret;
>  
> +	/*
> +	 * FIXME: set the FEC enabled state once pipe_config-
> >port_clock is
> +	 * already known, so the UHBR/non-UHBR mode can be
> determined.
> +	 */
>  	intel_dp_fec_compute_config(intel_dp, pipe_config);
>  
>  	if (!intel_dp_dsc_supports_format(connector, pipe_config-
> >output_format))
> diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c
> b/drivers/gpu/drm/i915/display/intel_dp_mst.c
> index f2266b2653046..27e952a67c343 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp_mst.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c
> @@ -293,6 +293,11 @@ int intel_dp_mtp_tu_compute_config(struct
> intel_dp *intel_dp,
>  		mst_stream_update_slots(crtc_state, mst_state);
>  	}
>  
> +	/*
> +	 * NOTE: The following must reset crtc_state->fec_enable for
> UHBR/DSC
> +	 * after it was set by intel_dp_dsc_compute_config() ->
> +	 * intel_dp_fec_compute_config().
> +	 */
>  	if (dsc) {
>  		if (!intel_dp_supports_fec(intel_dp, connector,
> crtc_state))
>  			return -EINVAL;

Re: [PATCH v2 3/7] drm/i915/dp: Export helper to determine if FEC on non-UHBR links is required

[Hogander, Jouni]

On Wed, 2025-10-15 at 19:19 +0300, Imre Deak wrote:
> Export the helper function to determine if FEC is required on a non-
> UHBR
> (8b10b) SST or MST link. A follow up change will take this into use
> for
> MST as well.
> 
> While at it determine the output type from the CRTC state, which
> allows
> dropping the intel_dp argument. Also make the function return the
> required FEC state, instead of setting this in the CRTC state, which
> allows only querying this requirement, without changing the state.
> 
> Also rename the function to intel_dp_needs_8b10b_fec(), to clarify
> that
> the function determines if FEC is required on an 8b10b link (on
> 128b132b
> links FEC is always enabled by the HW implicitly, so the function
> will
> return false for that case).
> 
> Signed-off-by: Imre Deak <imre.deak@intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_dp.c     | 21 +++++++++++++------
> --
>  drivers/gpu/drm/i915/display/intel_dp.h     |  2 ++
>  drivers/gpu/drm/i915/display/intel_dp_mst.c |  2 +-
>  3 files changed, 16 insertions(+), 9 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
> b/drivers/gpu/drm/i915/display/intel_dp.c
> index b523c4e661412..3ffb015004c54 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> @@ -2365,24 +2365,29 @@ static int
> intel_edp_dsc_compute_pipe_bpp(struct intel_dp *intel_dp,
>  	return 0;
>  }
>  
> -static void intel_dp_fec_compute_config(struct intel_dp *intel_dp,
> -					struct intel_crtc_state
> *crtc_state)
> +/*
> + * Return whether FEC must be enabled for 8b10b SST or MST links. On
> 128b132b
> + * links FEC is always enabled implicitly by the HW, so this
> function returns
> + * false for that case.
> + */
> +bool intel_dp_needs_8b10b_fec(const struct intel_crtc_state
> *crtc_state,
> +			      bool dsc_enabled_on_crtc)
>  {
>  	if (intel_dp_is_uhbr(crtc_state))
> -		return;
> +		return false;
>  
>  	if (crtc_state->fec_enable)
> -		return;
> +		return true;

Not really changed in this patch: Do you know in what kind of case
"crtc_state->fec_enable == true" before intel_dp_needs_8b10b_fec is
called?

BR,

Jouni Högander
>  
>  	/*
>  	 * Though eDP v1.5 supports FEC with DSC, unlike DP, it is
> optional.
>  	 * Since, FEC is a bandwidth overhead, continue to not
> enable it for
>  	 * eDP. Until, there is a good reason to do so.
>  	 */
> -	if (intel_dp_is_edp(intel_dp))
> -		return;
> +	if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP))
> +		return false;
>  
> -	crtc_state->fec_enable = true;
> +	return dsc_enabled_on_crtc;
>  }
>  
>  int intel_dp_dsc_compute_config(struct intel_dp *intel_dp,
> @@ -2404,7 +2409,7 @@ int intel_dp_dsc_compute_config(struct intel_dp
> *intel_dp,
>  	 * FIXME: set the FEC enabled state once pipe_config-
> >port_clock is
>  	 * already known, so the UHBR/non-UHBR mode can be
> determined.
>  	 */
> -	intel_dp_fec_compute_config(intel_dp, pipe_config);
> +	pipe_config->fec_enable =
> intel_dp_needs_8b10b_fec(pipe_config, true);
>  
>  	if (!intel_dp_dsc_supports_format(connector, pipe_config-
> >output_format))
>  		return -EINVAL;
> diff --git a/drivers/gpu/drm/i915/display/intel_dp.h
> b/drivers/gpu/drm/i915/display/intel_dp.h
> index b379443e0211e..55059bd5c7efb 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp.h
> +++ b/drivers/gpu/drm/i915/display/intel_dp.h
> @@ -73,6 +73,8 @@ void intel_dp_encoder_flush_work(struct drm_encoder
> *encoder);
>  int intel_dp_compute_config(struct intel_encoder *encoder,
>  			    struct intel_crtc_state *pipe_config,
>  			    struct drm_connector_state *conn_state);
> +bool intel_dp_needs_8b10b_fec(const struct intel_crtc_state
> *crtc_state,
> +			      bool dsc_enabled_on_crtc);
>  int intel_dp_dsc_compute_config(struct intel_dp *intel_dp,
>  				struct intel_crtc_state
> *pipe_config,
>  				struct drm_connector_state
> *conn_state,
> diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c
> b/drivers/gpu/drm/i915/display/intel_dp_mst.c
> index 27e952a67c343..d0590b5ffffd7 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp_mst.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c
> @@ -296,7 +296,7 @@ int intel_dp_mtp_tu_compute_config(struct
> intel_dp *intel_dp,
>  	/*
>  	 * NOTE: The following must reset crtc_state->fec_enable for
> UHBR/DSC
>  	 * after it was set by intel_dp_dsc_compute_config() ->
> -	 * intel_dp_fec_compute_config().
> +	 * intel_dp_needs_8b10b_fec().
>  	 */
>  	if (dsc) {
>  		if (!intel_dp_supports_fec(intel_dp, connector,
> crtc_state))

Re: [PATCH v2 4/7] drm/i915/dp_mst: Reuse the DP-SST helper function to compute FEC config

[Hogander, Jouni]

On Wed, 2025-10-15 at 19:19 +0300, Imre Deak wrote:
> Reuse the DP-SST helper to compute the state for the FEC enabled
> state
> for DP-MST as well.
> 
> Signed-off-by: Imre Deak <imre.deak@intel.com>

Reviewed-by: Jouni Högander <jouni.hogander@intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_dp_mst.c | 10 ++++------
>  1 file changed, 4 insertions(+), 6 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c
> b/drivers/gpu/drm/i915/display/intel_dp_mst.c
> index d0590b5ffffd7..0cbb4c3a8e22f 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp_mst.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c
> @@ -298,12 +298,10 @@ int intel_dp_mtp_tu_compute_config(struct
> intel_dp *intel_dp,
>  	 * after it was set by intel_dp_dsc_compute_config() ->
>  	 * intel_dp_needs_8b10b_fec().
>  	 */
> -	if (dsc) {
> -		if (!intel_dp_supports_fec(intel_dp, connector,
> crtc_state))
> -			return -EINVAL;
> -
> -		crtc_state->fec_enable =
> !intel_dp_is_uhbr(crtc_state);
> -	}
> +	crtc_state->fec_enable =
> intel_dp_needs_8b10b_fec(crtc_state, dsc);
> +	if (crtc_state->fec_enable &&
> +	    !intel_dp_supports_fec(intel_dp, connector, crtc_state))
> +		return -EINVAL;
>  
>  	max_dpt_bpp_x16 =
> fxp_q4_from_int(intel_dp_mst_max_dpt_bpp(crtc_state, dsc));
>  	if (max_dpt_bpp_x16 && max_bpp_x16 > max_dpt_bpp_x16) {

Re: [PATCH v2 5/7] drm/i915/dp_mst: Track DSC enabled status on the MST link

[Hogander, Jouni]

On Wed, 2025-10-15 at 19:19 +0300, Imre Deak wrote:
> Track whether DSC is enabled on any CRTC on a link. On DP-SST (and
> DSI)
> this will always match the CRTC's DSC state, those links having only
> a
> single stream (aka CRTC). For instance, on DP-MST if DSC is enabled
> for
> CRTC#0, but disabled for CRTC#1, the DSC/FEC state for these CRTCs
> will
> be as follows:
> 
> CRTC#0:
>  - compression_enable = true
>  - compression_enabled_on_link = true
>  - fec_enable = true for 8b10b, false for 128b132b
> 
> CRTC#1:
>  - compression_enable = false
>  - compression_enabled_on_link = true
>  - fec_enable = true for 8b10b, false for 128b132b
> 
> This patch only sets compression_enabled_on_link for CRTC#0 above and
> enables FEC on CRTC#0 if DSC was enabled on any other CRTC on the
> 8b10b
> MST link. A follow-up change will make sure that the state of all the
> CRTCs (CRTC#1 above) on an MST link is recomputed if DSC gets enabled
> on
> any CRTC, setting compression_enabled_on_link and fec_enable for
> these.
> 
> Signed-off-by: Imre Deak <imre.deak@intel.com>

Reviewed-by: Jouni Högander <jouni.hogander@intel.com>

> ---
>  drivers/gpu/drm/i915/display/intel_display_types.h |  2 ++
>  drivers/gpu/drm/i915/display/intel_dp.c            |  2 +-
>  drivers/gpu/drm/i915/display/intel_vdsc.c          | 11 +++++++++++
>  drivers/gpu/drm/i915/display/intel_vdsc.h          |  1 +
>  4 files changed, 15 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h
> b/drivers/gpu/drm/i915/display/intel_display_types.h
> index 87b7cec35320f..58308146697ff 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_types.h
> +++ b/drivers/gpu/drm/i915/display/intel_display_types.h
> @@ -1277,6 +1277,8 @@ struct intel_crtc_state {
>  
>  	/* Display Stream compression state */
>  	struct {
> +		/* Only used for state computation, not read out
> from the HW. */
> +		bool compression_enabled_on_link;
>  		bool compression_enable;
>  		int num_streams;
>  		/* Compressed Bpp in U6.4 format (first 4 bits for
> fractional part) */
> diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
> b/drivers/gpu/drm/i915/display/intel_dp.c
> index 3ffb015004c54..8ba931204cb52 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> @@ -2387,7 +2387,7 @@ bool intel_dp_needs_8b10b_fec(const struct
> intel_crtc_state *crtc_state,
>  	if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP))
>  		return false;
>  
> -	return dsc_enabled_on_crtc;
> +	return dsc_enabled_on_crtc ||
> intel_dsc_enabled_on_link(crtc_state);
>  }
>  
>  int intel_dp_dsc_compute_config(struct intel_dp *intel_dp,
> diff --git a/drivers/gpu/drm/i915/display/intel_vdsc.c
> b/drivers/gpu/drm/i915/display/intel_vdsc.c
> index 64a1e9f0a1893..316753205ac45 100644
> --- a/drivers/gpu/drm/i915/display/intel_vdsc.c
> +++ b/drivers/gpu/drm/i915/display/intel_vdsc.c
> @@ -374,9 +374,20 @@ int intel_dsc_compute_params(struct
> intel_crtc_state *pipe_config)
>  
>  void intel_dsc_enable_on_crtc(struct intel_crtc_state *crtc_state)
>  {
> +	crtc_state->dsc.compression_enabled_on_link = true;
>  	crtc_state->dsc.compression_enable = true;
>  }
>  
> +bool intel_dsc_enabled_on_link(const struct intel_crtc_state
> *crtc_state)
> +{
> +	struct intel_display *display =
> to_intel_display(crtc_state);
> +
> +	drm_WARN_ON(display->drm, crtc_state->dsc.compression_enable
> &&
> +		    !crtc_state->dsc.compression_enabled_on_link);
> +
> +	return crtc_state->dsc.compression_enabled_on_link;
> +}
> +
>  enum intel_display_power_domain
>  intel_dsc_power_domain(struct intel_crtc *crtc, enum transcoder
> cpu_transcoder)
>  {
> diff --git a/drivers/gpu/drm/i915/display/intel_vdsc.h
> b/drivers/gpu/drm/i915/display/intel_vdsc.h
> index 240bef82d3576..9c52ece0027c3 100644
> --- a/drivers/gpu/drm/i915/display/intel_vdsc.h
> +++ b/drivers/gpu/drm/i915/display/intel_vdsc.h
> @@ -21,6 +21,7 @@ void intel_dsc_enable(const struct intel_crtc_state
> *crtc_state);
>  void intel_dsc_disable(const struct intel_crtc_state *crtc_state);
>  int intel_dsc_compute_params(struct intel_crtc_state *pipe_config);
>  void intel_dsc_enable_on_crtc(struct intel_crtc_state *crtc_state);
> +bool intel_dsc_enabled_on_link(const struct intel_crtc_state
> *crtc_state);
>  void intel_dsc_get_config(struct intel_crtc_state *crtc_state);
>  enum intel_display_power_domain
>  intel_dsc_power_domain(struct intel_crtc *crtc, enum transcoder
> cpu_transcoder);

Re: [PATCH v2 6/7] drm/i915/dp_mst: Recompute all MST link CRTCs if DSC gets enabled on the link

[Hogander, Jouni]

On Wed, 2025-10-15 at 19:19 +0300, Imre Deak wrote:
> The state of all the CRTCs on an MST link must be recomputed, if DSC
> gets enabled on any of the CRTCs on the link. For instance an MST
> docking station's Panel Replay capability may depend on whether DSC
> is
> enabled on any of the dock's streams (aka CRTCs). To assist the Panel
> Replay state computation for a CRTC based on the above, track in the
> CRTC state if DSC is enabled on any CRTC on an MST link.
> 
> The intel_link_bw_limits::force_fec_pipes mask is used for a reason
> similar to the above: enable FEC on all CRTCs of a non-UHBR (8b10b)
> MST
> link if DSC is enabled on any of the link's CRTCs. The FEC enabled
> state
> for a CRTC doesn't indicate if DSC is enabled on a UHBR MST link (FEC
> is
> always enabled by the HW for UHBR, hence it's not tracked by the
> intel_crtc_state::fec_enable flag for such links, where this flag is
> always false).
> 
> Based on the above, to be able to determine the DSC state on both
> non-UHBR and UHBR MST links, track the more generic DSC-enabled-on-
> link
> state (instead of the FEC-enabled-on-link state) for each CRTC in
> intel_link_bw_limits.
> 
> Signed-off-by: Imre Deak <imre.deak@intel.com>

Reviewed-by: Jouni Högander <jouni.hogander@intel.com>

> ---
>  drivers/gpu/drm/i915/display/intel_display.c |  2 +-
>  drivers/gpu/drm/i915/display/intel_dp_mst.c  | 16 ++++++++--------
>  drivers/gpu/drm/i915/display/intel_link_bw.c | 17 +++++++++--------
>  drivers/gpu/drm/i915/display/intel_link_bw.h |  2 +-
>  4 files changed, 19 insertions(+), 18 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c
> b/drivers/gpu/drm/i915/display/intel_display.c
> index d5b2612d4ec25..64c0cf34b7af3 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -4601,7 +4601,7 @@ intel_modeset_pipe_config(struct
> intel_atomic_state *state,
>  	if (ret)
>  		return ret;
>  
> -	crtc_state->fec_enable = limits->force_fec_pipes & BIT(crtc-
> >pipe);
> +	crtc_state->dsc.compression_enabled_on_link = limits-
> >link_dsc_pipes & BIT(crtc->pipe);
>  	crtc_state->max_link_bpp_x16 = limits->max_bpp_x16[crtc-
> >pipe];
>  
>  	if (crtc_state->pipe_bpp > fxp_q4_to_int(crtc_state-
> >max_link_bpp_x16)) {
> diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c
> b/drivers/gpu/drm/i915/display/intel_dp_mst.c
> index 0cbb4c3a8e22f..a845b2612a3fa 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp_mst.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c
> @@ -814,14 +814,14 @@ static u8
> get_pipes_downstream_of_mst_port(struct intel_atomic_state *state,
>  	return mask;
>  }
>  
> -static int intel_dp_mst_check_fec_change(struct intel_atomic_state
> *state,
> +static int intel_dp_mst_check_dsc_change(struct intel_atomic_state
> *state,
>  					 struct
> drm_dp_mst_topology_mgr *mst_mgr,
>  					 struct intel_link_bw_limits
> *limits)
>  {
>  	struct intel_display *display = to_intel_display(state);
>  	struct intel_crtc *crtc;
>  	u8 mst_pipe_mask;
> -	u8 fec_pipe_mask = 0;
> +	u8 dsc_pipe_mask = 0;
>  	int ret;
>  
>  	mst_pipe_mask = get_pipes_downstream_of_mst_port(state,
> mst_mgr, NULL);
> @@ -834,16 +834,16 @@ static int intel_dp_mst_check_fec_change(struct
> intel_atomic_state *state,
>  		if (drm_WARN_ON(display->drm, !crtc_state))
>  			return -EINVAL;
>  
> -		if (crtc_state->fec_enable)
> -			fec_pipe_mask |= BIT(crtc->pipe);
> +		if (intel_dsc_enabled_on_link(crtc_state))
> +			dsc_pipe_mask |= BIT(crtc->pipe);
>  	}
>  
> -	if (!fec_pipe_mask || mst_pipe_mask == fec_pipe_mask)
> +	if (!dsc_pipe_mask || mst_pipe_mask == dsc_pipe_mask)
>  		return 0;
>  
> -	limits->force_fec_pipes |= mst_pipe_mask;
> +	limits->link_dsc_pipes |= mst_pipe_mask;
>  
> -	ret = intel_modeset_pipes_in_mask_early(state, "MST FEC",
> +	ret = intel_modeset_pipes_in_mask_early(state, "MST DSC",
>  						mst_pipe_mask);
>  
>  	return ret ? : -EAGAIN;
> @@ -897,7 +897,7 @@ int intel_dp_mst_atomic_check_link(struct
> intel_atomic_state *state,
>  	int i;
>  
>  	for_each_new_mst_mgr_in_state(&state->base, mgr, mst_state,
> i) {
> -		ret = intel_dp_mst_check_fec_change(state, mgr,
> limits);
> +		ret = intel_dp_mst_check_dsc_change(state, mgr,
> limits);
>  		if (ret)
>  			return ret;
>  
> diff --git a/drivers/gpu/drm/i915/display/intel_link_bw.c
> b/drivers/gpu/drm/i915/display/intel_link_bw.c
> index f52dee0ea412f..d2862de894fa7 100644
> --- a/drivers/gpu/drm/i915/display/intel_link_bw.c
> +++ b/drivers/gpu/drm/i915/display/intel_link_bw.c
> @@ -20,6 +20,7 @@
>  #include "intel_dp_tunnel.h"
>  #include "intel_fdi.h"
>  #include "intel_link_bw.h"
> +#include "intel_vdsc.h"
>  
>  static int get_forced_link_bpp_x16(struct intel_atomic_state *state,
>  				   const struct intel_crtc *crtc)
> @@ -55,7 +56,7 @@ void intel_link_bw_init_limits(struct
> intel_atomic_state *state,
>  	struct intel_display *display = to_intel_display(state);
>  	enum pipe pipe;
>  
> -	limits->force_fec_pipes = 0;
> +	limits->link_dsc_pipes = 0;
>  	limits->bpp_limit_reached_pipes = 0;
>  	for_each_pipe(display, pipe) {
>  		struct intel_crtc *crtc =
> intel_crtc_for_pipe(display, pipe);
> @@ -65,8 +66,8 @@ void intel_link_bw_init_limits(struct
> intel_atomic_state *state,
>  
>  		if (state->base.duplicated && crtc_state) {
>  			limits->max_bpp_x16[pipe] = crtc_state-
> >max_link_bpp_x16;
> -			if (crtc_state->fec_enable)
> -				limits->force_fec_pipes |=
> BIT(pipe);
> +			if (intel_dsc_enabled_on_link(crtc_state))
> +				limits->link_dsc_pipes |= BIT(pipe);
>  		} else {
>  			limits->max_bpp_x16[pipe] = INT_MAX;
>  		}
> @@ -265,10 +266,10 @@ assert_link_limit_change_valid(struct
> intel_display *display,
>  	bool bpps_changed = false;
>  	enum pipe pipe;
>  
> -	/* FEC can't be forced off after it was forced on. */
> +	/* DSC can't be disabled after it was enabled. */
>  	if (drm_WARN_ON(display->drm,
> -			(old_limits->force_fec_pipes & new_limits-
> >force_fec_pipes) !=
> -			old_limits->force_fec_pipes))
> +			(old_limits->link_dsc_pipes & new_limits-
> >link_dsc_pipes) !=
> +			old_limits->link_dsc_pipes))
>  		return false;
>  
>  	for_each_pipe(display, pipe) {
> @@ -286,8 +287,8 @@ assert_link_limit_change_valid(struct
> intel_display *display,
>  	/* At least one limit must change. */
>  	if (drm_WARN_ON(display->drm,
>  			!bpps_changed &&
> -			new_limits->force_fec_pipes ==
> -			old_limits->force_fec_pipes))
> +			new_limits->link_dsc_pipes ==
> +			old_limits->link_dsc_pipes))
>  		return false;
>  
>  	return true;
> diff --git a/drivers/gpu/drm/i915/display/intel_link_bw.h
> b/drivers/gpu/drm/i915/display/intel_link_bw.h
> index 95ab7c50c61d0..cb18e171037cf 100644
> --- a/drivers/gpu/drm/i915/display/intel_link_bw.h
> +++ b/drivers/gpu/drm/i915/display/intel_link_bw.h
> @@ -15,7 +15,7 @@ struct intel_connector;
>  struct intel_crtc_state;
>  
>  struct intel_link_bw_limits {
> -	u8 force_fec_pipes;
> +	u8 link_dsc_pipes;
>  	u8 bpp_limit_reached_pipes;
>  	/* in 1/16 bpp units */
>  	int max_bpp_x16[I915_MAX_PIPES];

Re: [PATCH v2 3/7] drm/i915/dp: Export helper to determine if FEC on non-UHBR links is required

[Imre Deak]

On Thu, Oct 16, 2025 at 07:56:32PM +0300, Jouni Hogander wrote:
> On Wed, 2025-10-15 at 19:19 +0300, Imre Deak wrote:
> > Export the helper function to determine if FEC is required on a non-
> > UHBR
> > (8b10b) SST or MST link. A follow up change will take this into use
> > for
> > MST as well.
> > 
> > While at it determine the output type from the CRTC state, which
> > allows
> > dropping the intel_dp argument. Also make the function return the
> > required FEC state, instead of setting this in the CRTC state, which
> > allows only querying this requirement, without changing the state.
> > 
> > Also rename the function to intel_dp_needs_8b10b_fec(), to clarify
> > that
> > the function determines if FEC is required on an 8b10b link (on
> > 128b132b
> > links FEC is always enabled by the HW implicitly, so the function
> > will
> > return false for that case).
> > 
> > Signed-off-by: Imre Deak <imre.deak@intel.com>
> > ---
> >  drivers/gpu/drm/i915/display/intel_dp.c     | 21 +++++++++++++------
> > --
> >  drivers/gpu/drm/i915/display/intel_dp.h     |  2 ++
> >  drivers/gpu/drm/i915/display/intel_dp_mst.c |  2 +-
> >  3 files changed, 16 insertions(+), 9 deletions(-)
> > 
> > diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
> > b/drivers/gpu/drm/i915/display/intel_dp.c
> > index b523c4e661412..3ffb015004c54 100644
> > --- a/drivers/gpu/drm/i915/display/intel_dp.c
> > +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> > @@ -2365,24 +2365,29 @@ static int
> > intel_edp_dsc_compute_pipe_bpp(struct intel_dp *intel_dp,
> >  	return 0;
> >  }
> >  
> > -static void intel_dp_fec_compute_config(struct intel_dp *intel_dp,
> > -					struct intel_crtc_state
> > *crtc_state)
> > +/*
> > + * Return whether FEC must be enabled for 8b10b SST or MST links. On
> > 128b132b
> > + * links FEC is always enabled implicitly by the HW, so this
> > function returns
> > + * false for that case.
> > + */
> > +bool intel_dp_needs_8b10b_fec(const struct intel_crtc_state
> > *crtc_state,
> > +			      bool dsc_enabled_on_crtc)
> >  {
> >  	if (intel_dp_is_uhbr(crtc_state))
> > -		return;
> > +		return false;
> >  
> >  	if (crtc_state->fec_enable)
> > -		return;
> > +		return true;
> 
> Not really changed in this patch: Do you know in what kind of case
> "crtc_state->fec_enable == true" before intel_dp_needs_8b10b_fec is
> called?

Yes, that's another corner which should've been documented at least:
that's the case when there are two or more CRTCs on a 8b10b MST link,
only one/some of them enabling DSC (but not all). For instance, CRTC#1
enables DSC, but CRTC#0 does not enable DSC. First CRTC#0's state is
computed (due to the regular order of CRTC#0/1 etc. state computation)
and since DSC is not enabled on it, it will compute
intel_crtc_state::fec_enable=false. Then CRTC#1 will compute
fec_enable=true, due to it enabling DSC.

After all CRTCs computed their state, through
intel_atomic_check_config_and_link() -> intel_atomic_check_config(), the
following path will detect that the FEC enabled state is different for
the CRTCs on the same MST link (whereas the FEC enabled state should be
the same for all the CRTCs on the link, since FEC is the property of the
link encoding). After detecting this, the state of all the CRTCs on the
link will be recomputed with FEC forced on now for all (forced, even if
DSC is not enabled for a CRTC):

intel_atomic_check_config_and_link() -> intel_link_bw_atomic_check() -> 
check_all_link_config() -> intel_dp_mst_atomic_check_link() ->
intel_dp_mst_check_fec_change().

The above will set the intel_link_bw_limits::force_fec_pipes mask for
both CRTC#0 and CRTC#1, then both CRTCs' state gets recomputed, during
which intel_crtc_state::fec_enable will be set upfront in
intel_modeset_pipe_config(). The above intel_dp_dsc_compute_config() ->
intel_dp_needs_8b10b_fec() will be called after all the above (during
the second round of state computation) and so with
intel_crtc_state::fec_enable already set. This set state must be
preserved for CRTC#0 as well, even though it doesn't enable DSC.

> BR,
> 
> Jouni Högander
> >  
> >  	/*
> >  	 * Though eDP v1.5 supports FEC with DSC, unlike DP, it is
> > optional.
> >  	 * Since, FEC is a bandwidth overhead, continue to not
> > enable it for
> >  	 * eDP. Until, there is a good reason to do so.
> >  	 */
> > -	if (intel_dp_is_edp(intel_dp))
> > -		return;
> > +	if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP))
> > +		return false;
> >  
> > -	crtc_state->fec_enable = true;
> > +	return dsc_enabled_on_crtc;
> >  }
> >  
> >  int intel_dp_dsc_compute_config(struct intel_dp *intel_dp,
> > @@ -2404,7 +2409,7 @@ int intel_dp_dsc_compute_config(struct intel_dp
> > *intel_dp,
> >  	 * FIXME: set the FEC enabled state once pipe_config-
> > >port_clock is
> >  	 * already known, so the UHBR/non-UHBR mode can be
> > determined.
> >  	 */
> > -	intel_dp_fec_compute_config(intel_dp, pipe_config);
> > +	pipe_config->fec_enable =
> > intel_dp_needs_8b10b_fec(pipe_config, true);
> >  
> >  	if (!intel_dp_dsc_supports_format(connector, pipe_config-
> > >output_format))
> >  		return -EINVAL;
> > diff --git a/drivers/gpu/drm/i915/display/intel_dp.h
> > b/drivers/gpu/drm/i915/display/intel_dp.h
> > index b379443e0211e..55059bd5c7efb 100644
> > --- a/drivers/gpu/drm/i915/display/intel_dp.h
> > +++ b/drivers/gpu/drm/i915/display/intel_dp.h
> > @@ -73,6 +73,8 @@ void intel_dp_encoder_flush_work(struct drm_encoder
> > *encoder);
> >  int intel_dp_compute_config(struct intel_encoder *encoder,
> >  			    struct intel_crtc_state *pipe_config,
> >  			    struct drm_connector_state *conn_state);
> > +bool intel_dp_needs_8b10b_fec(const struct intel_crtc_state
> > *crtc_state,
> > +			      bool dsc_enabled_on_crtc);
> >  int intel_dp_dsc_compute_config(struct intel_dp *intel_dp,
> >  				struct intel_crtc_state
> > *pipe_config,
> >  				struct drm_connector_state
> > *conn_state,
> > diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c
> > b/drivers/gpu/drm/i915/display/intel_dp_mst.c
> > index 27e952a67c343..d0590b5ffffd7 100644
> > --- a/drivers/gpu/drm/i915/display/intel_dp_mst.c
> > +++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c
> > @@ -296,7 +296,7 @@ int intel_dp_mtp_tu_compute_config(struct
> > intel_dp *intel_dp,
> >  	/*
> >  	 * NOTE: The following must reset crtc_state->fec_enable for
> > UHBR/DSC
> >  	 * after it was set by intel_dp_dsc_compute_config() ->
> > -	 * intel_dp_fec_compute_config().
> > +	 * intel_dp_needs_8b10b_fec().
> >  	 */
> >  	if (dsc) {
> >  		if (!intel_dp_supports_fec(intel_dp, connector,
> > crtc_state))
> 

Re: [PATCH v2 3/7] drm/i915/dp: Export helper to determine if FEC on non-UHBR links is required

[Hogander, Jouni]

On Thu, 2025-10-16 at 20:18 +0300, Imre Deak wrote:
> On Thu, Oct 16, 2025 at 07:56:32PM +0300, Jouni Hogander wrote:
> > On Wed, 2025-10-15 at 19:19 +0300, Imre Deak wrote:
> > > Export the helper function to determine if FEC is required on a
> > > non-
> > > UHBR
> > > (8b10b) SST or MST link. A follow up change will take this into
> > > use
> > > for
> > > MST as well.
> > > 
> > > While at it determine the output type from the CRTC state, which
> > > allows
> > > dropping the intel_dp argument. Also make the function return the
> > > required FEC state, instead of setting this in the CRTC state,
> > > which
> > > allows only querying this requirement, without changing the
> > > state.
> > > 
> > > Also rename the function to intel_dp_needs_8b10b_fec(), to
> > > clarify
> > > that
> > > the function determines if FEC is required on an 8b10b link (on
> > > 128b132b
> > > links FEC is always enabled by the HW implicitly, so the function
> > > will
> > > return false for that case).
> > > 
> > > Signed-off-by: Imre Deak <imre.deak@intel.com>
> > > ---
> > >  drivers/gpu/drm/i915/display/intel_dp.c     | 21 +++++++++++++--
> > > ----
> > > --
> > >  drivers/gpu/drm/i915/display/intel_dp.h     |  2 ++
> > >  drivers/gpu/drm/i915/display/intel_dp_mst.c |  2 +-
> > >  3 files changed, 16 insertions(+), 9 deletions(-)
> > > 
> > > diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
> > > b/drivers/gpu/drm/i915/display/intel_dp.c
> > > index b523c4e661412..3ffb015004c54 100644
> > > --- a/drivers/gpu/drm/i915/display/intel_dp.c
> > > +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> > > @@ -2365,24 +2365,29 @@ static int
> > > intel_edp_dsc_compute_pipe_bpp(struct intel_dp *intel_dp,
> > >  	return 0;
> > >  }
> > >  
> > > -static void intel_dp_fec_compute_config(struct intel_dp
> > > *intel_dp,
> > > -					struct intel_crtc_state
> > > *crtc_state)
> > > +/*
> > > + * Return whether FEC must be enabled for 8b10b SST or MST
> > > links. On
> > > 128b132b
> > > + * links FEC is always enabled implicitly by the HW, so this
> > > function returns
> > > + * false for that case.
> > > + */
> > > +bool intel_dp_needs_8b10b_fec(const struct intel_crtc_state
> > > *crtc_state,
> > > +			      bool dsc_enabled_on_crtc)
> > >  {
> > >  	if (intel_dp_is_uhbr(crtc_state))
> > > -		return;
> > > +		return false;
> > >  
> > >  	if (crtc_state->fec_enable)
> > > -		return;
> > > +		return true;
> > 
> > Not really changed in this patch: Do you know in what kind of case
> > "crtc_state->fec_enable == true" before intel_dp_needs_8b10b_fec is
> > called?
> 
> Yes, that's another corner which should've been documented at least:
> that's the case when there are two or more CRTCs on a 8b10b MST link,
> only one/some of them enabling DSC (but not all). For instance,
> CRTC#1
> enables DSC, but CRTC#0 does not enable DSC. First CRTC#0's state is
> computed (due to the regular order of CRTC#0/1 etc. state
> computation)
> and since DSC is not enabled on it, it will compute
> intel_crtc_state::fec_enable=false. Then CRTC#1 will compute
> fec_enable=true, due to it enabling DSC.
> 
> After all CRTCs computed their state, through
> intel_atomic_check_config_and_link() -> intel_atomic_check_config(),
> the
> following path will detect that the FEC enabled state is different
> for
> the CRTCs on the same MST link (whereas the FEC enabled state should
> be
> the same for all the CRTCs on the link, since FEC is the property of
> the
> link encoding). After detecting this, the state of all the CRTCs on
> the
> link will be recomputed with FEC forced on now for all (forced, even
> if
> DSC is not enabled for a CRTC):
> 
> intel_atomic_check_config_and_link() -> intel_link_bw_atomic_check()
> -> 
> check_all_link_config() -> intel_dp_mst_atomic_check_link() ->
> intel_dp_mst_check_fec_change().
> 
> The above will set the intel_link_bw_limits::force_fec_pipes mask for
> both CRTC#0 and CRTC#1, then both CRTCs' state gets recomputed,
> during
> which intel_crtc_state::fec_enable will be set upfront in
> intel_modeset_pipe_config(). The above intel_dp_dsc_compute_config()
> ->
> intel_dp_needs_8b10b_fec() will be called after all the above (during
> the second round of state computation) and so with
> intel_crtc_state::fec_enable already set. This set state must be
> preserved for CRTC#0 as well, even though it doesn't enable DSC.

Thank you for the clarification. Patch 6 converts
intel_dp_mst_check_fec_change -> intel_dp_mst_check_dsc_change. I.e.
force_fec_pipes mask is not set and it doesn't exist. Instead there is
force_dsc_pipes mask. Maybe this could be dropped in patch 6 as
intel_modeset_pipe_config is setting compression_enabled_on_link
instead and this is also checked in intel_dp_needs_8b10b_fec? 

BR,

Jouni Högander

> 
> > BR,
> > 
> > Jouni Högander
> > >  
> > >  	/*
> > >  	 * Though eDP v1.5 supports FEC with DSC, unlike DP, it
> > > is
> > > optional.
> > >  	 * Since, FEC is a bandwidth overhead, continue to not
> > > enable it for
> > >  	 * eDP. Until, there is a good reason to do so.
> > >  	 */
> > > -	if (intel_dp_is_edp(intel_dp))
> > > -		return;
> > > +	if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP))
> > > +		return false;
> > >  
> > > -	crtc_state->fec_enable = true;
> > > +	return dsc_enabled_on_crtc;
> > >  }
> > >  
> > >  int intel_dp_dsc_compute_config(struct intel_dp *intel_dp,
> > > @@ -2404,7 +2409,7 @@ int intel_dp_dsc_compute_config(struct
> > > intel_dp
> > > *intel_dp,
> > >  	 * FIXME: set the FEC enabled state once pipe_config-
> > > > port_clock is
> > >  	 * already known, so the UHBR/non-UHBR mode can be
> > > determined.
> > >  	 */
> > > -	intel_dp_fec_compute_config(intel_dp, pipe_config);
> > > +	pipe_config->fec_enable =
> > > intel_dp_needs_8b10b_fec(pipe_config, true);
> > >  
> > >  	if (!intel_dp_dsc_supports_format(connector,
> > > pipe_config-
> > > > output_format))
> > >  		return -EINVAL;
> > > diff --git a/drivers/gpu/drm/i915/display/intel_dp.h
> > > b/drivers/gpu/drm/i915/display/intel_dp.h
> > > index b379443e0211e..55059bd5c7efb 100644
> > > --- a/drivers/gpu/drm/i915/display/intel_dp.h
> > > +++ b/drivers/gpu/drm/i915/display/intel_dp.h
> > > @@ -73,6 +73,8 @@ void intel_dp_encoder_flush_work(struct
> > > drm_encoder
> > > *encoder);
> > >  int intel_dp_compute_config(struct intel_encoder *encoder,
> > >  			    struct intel_crtc_state
> > > *pipe_config,
> > >  			    struct drm_connector_state
> > > *conn_state);
> > > +bool intel_dp_needs_8b10b_fec(const struct intel_crtc_state
> > > *crtc_state,
> > > +			      bool dsc_enabled_on_crtc);
> > >  int intel_dp_dsc_compute_config(struct intel_dp *intel_dp,
> > >  				struct intel_crtc_state
> > > *pipe_config,
> > >  				struct drm_connector_state
> > > *conn_state,
> > > diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c
> > > b/drivers/gpu/drm/i915/display/intel_dp_mst.c
> > > index 27e952a67c343..d0590b5ffffd7 100644
> > > --- a/drivers/gpu/drm/i915/display/intel_dp_mst.c
> > > +++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c
> > > @@ -296,7 +296,7 @@ int intel_dp_mtp_tu_compute_config(struct
> > > intel_dp *intel_dp,
> > >  	/*
> > >  	 * NOTE: The following must reset crtc_state->fec_enable
> > > for
> > > UHBR/DSC
> > >  	 * after it was set by intel_dp_dsc_compute_config() ->
> > > -	 * intel_dp_fec_compute_config().
> > > +	 * intel_dp_needs_8b10b_fec().
> > >  	 */
> > >  	if (dsc) {
> > >  		if (!intel_dp_supports_fec(intel_dp, connector,
> > > crtc_state))
> > 

✓ Xe.CI.Full: success for drm/i915/dp: Fix panel replay in DSC mode (rev2)

[Patchwork]

[-- Attachment #1: Type: text/plain, Size: 72794 bytes --]

== Series Details ==

Series: drm/i915/dp: Fix panel replay in DSC mode (rev2)
URL   : https://patchwork.freedesktop.org/series/155586/
State : success

== Summary ==

CI Bug Log - changes from xe-3928-f019aaad58112f89234f7b68557c831846437008_FULL -> xe-pw-155586v2_FULL
====================================================

Summary
-------

  **SUCCESS**

  No regressions found.

  

Participating hosts (4 -> 4)
------------------------------

  No changes in participating hosts

Known issues
------------

  Here are the changes found in xe-pw-155586v2_FULL that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@kms_async_flips@alternate-sync-async-flip-atomic@pipe-a-dp-2:
    - shard-bmg:          [PASS][1] -> [FAIL][2] ([Intel XE#3718] / [Intel XE#6078]) +1 other test fail
   [1]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3928-f019aaad58112f89234f7b68557c831846437008/shard-bmg-3/igt@kms_async_flips@alternate-sync-async-flip-atomic@pipe-a-dp-2.html
   [2]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155586v2/shard-bmg-1/igt@kms_async_flips@alternate-sync-async-flip-atomic@pipe-a-dp-2.html

  * igt@kms_big_fb@4-tiled-8bpp-rotate-90:
    - shard-dg2-set2:     NOTRUN -> [SKIP][3] ([Intel XE#316]) +1 other test skip
   [3]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155586v2/shard-dg2-433/igt@kms_big_fb@4-tiled-8bpp-rotate-90.html

  * igt@kms_big_fb@4-tiled-addfb:
    - shard-adlp:         NOTRUN -> [SKIP][4] ([Intel XE#619])
   [4]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155586v2/shard-adlp-6/igt@kms_big_fb@4-tiled-addfb.html

  * igt@kms_big_fb@linear-32bpp-rotate-270:
    - shard-bmg:          NOTRUN -> [SKIP][5] ([Intel XE#2327]) +2 other tests skip
   [5]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155586v2/shard-bmg-2/igt@kms_big_fb@linear-32bpp-rotate-270.html

  * igt@kms_big_fb@x-tiled-64bpp-rotate-180:
    - shard-adlp:         NOTRUN -> [DMESG-FAIL][6] ([Intel XE#4543]) +8 other tests dmesg-fail
   [6]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155586v2/shard-adlp-2/igt@kms_big_fb@x-tiled-64bpp-rotate-180.html

  * igt@kms_big_fb@x-tiled-8bpp-rotate-90:
    - shard-adlp:         NOTRUN -> [SKIP][7] ([Intel XE#316]) +6 other tests skip
   [7]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155586v2/shard-adlp-9/igt@kms_big_fb@x-tiled-8bpp-rotate-90.html

  * igt@kms_big_fb@x-tiled-max-hw-stride-64bpp-rotate-0:
    - shard-adlp:         NOTRUN -> [FAIL][8] ([Intel XE#1874])
   [8]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155586v2/shard-adlp-2/igt@kms_big_fb@x-tiled-max-hw-stride-64bpp-rotate-0.html

  * igt@kms_big_fb@y-tiled-max-hw-stride-32bpp-rotate-0:
    - shard-dg2-set2:     NOTRUN -> [SKIP][9] ([Intel XE#1124]) +2 other tests skip
   [9]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155586v2/shard-dg2-433/igt@kms_big_fb@y-tiled-max-hw-stride-32bpp-rotate-0.html

  * igt@kms_big_fb@y-tiled-max-hw-stride-64bpp-rotate-0-hflip:
    - shard-bmg:          NOTRUN -> [SKIP][10] ([Intel XE#1124]) +4 other tests skip
   [10]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155586v2/shard-bmg-7/igt@kms_big_fb@y-tiled-max-hw-stride-64bpp-rotate-0-hflip.html

  * igt@kms_big_fb@yf-tiled-addfb-size-offset-overflow:
    - shard-adlp:         NOTRUN -> [SKIP][11] ([Intel XE#607])
   [11]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155586v2/shard-adlp-9/igt@kms_big_fb@yf-tiled-addfb-size-offset-overflow.html

  * igt@kms_big_fb@yf-tiled-max-hw-stride-32bpp-rotate-0:
    - shard-adlp:         NOTRUN -> [SKIP][12] ([Intel XE#1124]) +17 other tests skip
   [12]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155586v2/shard-adlp-2/igt@kms_big_fb@yf-tiled-max-hw-stride-32bpp-rotate-0.html

  * igt@kms_bw@connected-linear-tiling-1-displays-3840x2160p:
    - shard-adlp:         NOTRUN -> [SKIP][13] ([Intel XE#367]) +5 other tests skip
   [13]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155586v2/shard-adlp-8/igt@kms_bw@connected-linear-tiling-1-displays-3840x2160p.html

  * igt@kms_bw@connected-linear-tiling-4-displays-2560x1440p:
    - shard-adlp:         NOTRUN -> [SKIP][14] ([Intel XE#2191]) +4 other tests skip
   [14]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155586v2/shard-adlp-1/igt@kms_bw@connected-linear-tiling-4-displays-2560x1440p.html

  * igt@kms_bw@linear-tiling-2-displays-2160x1440p:
    - shard-bmg:          NOTRUN -> [SKIP][15] ([Intel XE#367]) +1 other test skip
   [15]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155586v2/shard-bmg-2/igt@kms_bw@linear-tiling-2-displays-2160x1440p.html

  * igt@kms_bw@linear-tiling-3-displays-2560x1440p:
    - shard-dg2-set2:     NOTRUN -> [SKIP][16] ([Intel XE#367])
   [16]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155586v2/shard-dg2-433/igt@kms_bw@linear-tiling-3-displays-2560x1440p.html

  * igt@kms_ccs@bad-pixel-format-4-tiled-dg2-mc-ccs:
    - shard-adlp:         NOTRUN -> [SKIP][17] ([Intel XE#455] / [Intel XE#787]) +53 other tests skip
   [17]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155586v2/shard-adlp-9/igt@kms_ccs@bad-pixel-format-4-tiled-dg2-mc-ccs.html

  * igt@kms_ccs@bad-pixel-format-yf-tiled-ccs:
    - shard-dg2-set2:     NOTRUN -> [SKIP][18] ([Intel XE#455] / [Intel XE#787]) +13 other tests skip
   [18]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155586v2/shard-dg2-433/igt@kms_ccs@bad-pixel-format-yf-tiled-ccs.html

  * igt@kms_ccs@crc-primary-basic-4-tiled-bmg-ccs:
    - shard-dg2-set2:     NOTRUN -> [SKIP][19] ([Intel XE#2907])
   [19]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155586v2/shard-dg2-464/igt@kms_ccs@crc-primary-basic-4-tiled-bmg-ccs.html

  * igt@kms_ccs@crc-primary-rotation-180-y-tiled-gen12-rc-ccs:
    - shard-bmg:          NOTRUN -> [SKIP][20] ([Intel XE#2887]) +4 other tests skip
   [20]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155586v2/shard-bmg-7/igt@kms_ccs@crc-primary-rotation-180-y-tiled-gen12-rc-ccs.html

  * igt@kms_ccs@crc-primary-suspend-4-tiled-bmg-ccs:
    - shard-adlp:         NOTRUN -> [SKIP][21] ([Intel XE#3442])
   [21]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155586v2/shard-adlp-9/igt@kms_ccs@crc-primary-suspend-4-tiled-bmg-ccs.html
    - shard-bmg:          [PASS][22] -> [INCOMPLETE][23] ([Intel XE#3862]) +1 other test incomplete
   [22]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3928-f019aaad58112f89234f7b68557c831846437008/shard-bmg-6/igt@kms_ccs@crc-primary-suspend-4-tiled-bmg-ccs.html
   [23]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155586v2/shard-bmg-8/igt@kms_ccs@crc-primary-suspend-4-tiled-bmg-ccs.html

  * igt@kms_ccs@crc-primary-suspend-4-tiled-lnl-ccs:
    - shard-dg2-set2:     NOTRUN -> [SKIP][24] ([Intel XE#3442])
   [24]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155586v2/shard-dg2-433/igt@kms_ccs@crc-primary-suspend-4-tiled-lnl-ccs.html

  * igt@kms_ccs@crc-primary-suspend-y-tiled-gen12-rc-ccs-cc@pipe-b-hdmi-a-1:
    - shard-adlp:         NOTRUN -> [SKIP][25] ([Intel XE#787]) +80 other tests skip
   [25]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155586v2/shard-adlp-9/igt@kms_ccs@crc-primary-suspend-y-tiled-gen12-rc-ccs-cc@pipe-b-hdmi-a-1.html

  * igt@kms_ccs@crc-sprite-planes-basic-4-tiled-bmg-ccs:
    - shard-adlp:         NOTRUN -> [SKIP][26] ([Intel XE#2907]) +5 other tests skip
   [26]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155586v2/shard-adlp-6/igt@kms_ccs@crc-sprite-planes-basic-4-tiled-bmg-ccs.html

  * igt@kms_ccs@missing-ccs-buffer-yf-tiled-ccs@pipe-b-dp-4:
    - shard-dg2-set2:     NOTRUN -> [SKIP][27] ([Intel XE#787]) +48 other tests skip
   [27]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155586v2/shard-dg2-433/igt@kms_ccs@missing-ccs-buffer-yf-tiled-ccs@pipe-b-dp-4.html

  * igt@kms_ccs@random-ccs-data-4-tiled-dg2-mc-ccs:
    - shard-dg2-set2:     [PASS][28] -> [INCOMPLETE][29] ([Intel XE#1727] / [Intel XE#2705] / [Intel XE#3113] / [Intel XE#4212] / [Intel XE#4345] / [Intel XE#4522])
   [28]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3928-f019aaad58112f89234f7b68557c831846437008/shard-dg2-433/igt@kms_ccs@random-ccs-data-4-tiled-dg2-mc-ccs.html
   [29]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155586v2/shard-dg2-463/igt@kms_ccs@random-ccs-data-4-tiled-dg2-mc-ccs.html

  * igt@kms_ccs@random-ccs-data-4-tiled-dg2-mc-ccs@pipe-a-dp-4:
    - shard-dg2-set2:     [PASS][30] -> [INCOMPLETE][31] ([Intel XE#1727] / [Intel XE#2705] / [Intel XE#3113] / [Intel XE#4212] / [Intel XE#4522])
   [30]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3928-f019aaad58112f89234f7b68557c831846437008/shard-dg2-433/igt@kms_ccs@random-ccs-data-4-tiled-dg2-mc-ccs@pipe-a-dp-4.html
   [31]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155586v2/shard-dg2-463/igt@kms_ccs@random-ccs-data-4-tiled-dg2-mc-ccs@pipe-a-dp-4.html

  * igt@kms_ccs@random-ccs-data-4-tiled-dg2-rc-ccs-cc:
    - shard-dg2-set2:     [PASS][32] -> [INCOMPLETE][33] ([Intel XE#1727] / [Intel XE#3113] / [Intel XE#4212] / [Intel XE#4345] / [Intel XE#4522] / [Intel XE#4842])
   [32]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3928-f019aaad58112f89234f7b68557c831846437008/shard-dg2-432/igt@kms_ccs@random-ccs-data-4-tiled-dg2-rc-ccs-cc.html
   [33]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155586v2/shard-dg2-436/igt@kms_ccs@random-ccs-data-4-tiled-dg2-rc-ccs-cc.html

  * igt@kms_ccs@random-ccs-data-4-tiled-dg2-rc-ccs-cc@pipe-b-dp-4:
    - shard-dg2-set2:     [PASS][34] -> [INCOMPLETE][35] ([Intel XE#1727] / [Intel XE#3113] / [Intel XE#4212] / [Intel XE#4522] / [Intel XE#4842])
   [34]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3928-f019aaad58112f89234f7b68557c831846437008/shard-dg2-432/igt@kms_ccs@random-ccs-data-4-tiled-dg2-rc-ccs-cc@pipe-b-dp-4.html
   [35]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155586v2/shard-dg2-436/igt@kms_ccs@random-ccs-data-4-tiled-dg2-rc-ccs-cc@pipe-b-dp-4.html

  * igt@kms_cdclk@plane-scaling:
    - shard-adlp:         NOTRUN -> [SKIP][36] ([Intel XE#4416] / [Intel XE#455])
   [36]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155586v2/shard-adlp-9/igt@kms_cdclk@plane-scaling.html

  * igt@kms_cdclk@plane-scaling@pipe-a-hdmi-a-1:
    - shard-adlp:         NOTRUN -> [SKIP][37] ([Intel XE#4416]) +2 other tests skip
   [37]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155586v2/shard-adlp-9/igt@kms_cdclk@plane-scaling@pipe-a-hdmi-a-1.html

  * igt@kms_chamelium_audio@hdmi-audio-edid:
    - shard-adlp:         NOTRUN -> [SKIP][38] ([Intel XE#373]) +21 other tests skip
   [38]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155586v2/shard-adlp-2/igt@kms_chamelium_audio@hdmi-audio-edid.html

  * igt@kms_chamelium_color@ctm-0-50:
    - shard-adlp:         NOTRUN -> [SKIP][39] ([Intel XE#306]) +2 other tests skip
   [39]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155586v2/shard-adlp-8/igt@kms_chamelium_color@ctm-0-50.html

  * igt@kms_chamelium_color@ctm-0-75:
    - shard-bmg:          NOTRUN -> [SKIP][40] ([Intel XE#2325])
   [40]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155586v2/shard-bmg-7/igt@kms_chamelium_color@ctm-0-75.html

  * igt@kms_chamelium_edid@vga-edid-read:
    - shard-dg2-set2:     NOTRUN -> [SKIP][41] ([Intel XE#373]) +3 other tests skip
   [41]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155586v2/shard-dg2-433/igt@kms_chamelium_edid@vga-edid-read.html

  * igt@kms_chamelium_frames@dp-crc-single:
    - shard-bmg:          NOTRUN -> [SKIP][42] ([Intel XE#2252]) +4 other tests skip
   [42]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155586v2/shard-bmg-2/igt@kms_chamelium_frames@dp-crc-single.html

  * igt@kms_content_protection@dp-mst-type-1:
    - shard-adlp:         NOTRUN -> [SKIP][43] ([Intel XE#307]) +2 other tests skip
   [43]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155586v2/shard-adlp-9/igt@kms_content_protection@dp-mst-type-1.html

  * igt@kms_cursor_crc@cursor-random-128x42@pipe-a-hdmi-a-6:
    - shard-dg2-set2:     NOTRUN -> [INCOMPLETE][44] ([Intel XE#4842]) +1 other test incomplete
   [44]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155586v2/shard-dg2-466/igt@kms_cursor_crc@cursor-random-128x42@pipe-a-hdmi-a-6.html

  * igt@kms_cursor_crc@cursor-random-32x32:
    - shard-bmg:          NOTRUN -> [SKIP][45] ([Intel XE#2320]) +2 other tests skip
   [45]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155586v2/shard-bmg-2/igt@kms_cursor_crc@cursor-random-32x32.html

  * igt@kms_cursor_crc@cursor-rapid-movement-512x170:
    - shard-dg2-set2:     NOTRUN -> [SKIP][46] ([Intel XE#308])
   [46]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155586v2/shard-dg2-433/igt@kms_cursor_crc@cursor-rapid-movement-512x170.html

  * igt@kms_cursor_crc@cursor-sliding-512x170:
    - shard-adlp:         NOTRUN -> [SKIP][47] ([Intel XE#308]) +2 other tests skip
   [47]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155586v2/shard-adlp-8/igt@kms_cursor_crc@cursor-sliding-512x170.html

  * igt@kms_cursor_legacy@cursorb-vs-flipa-atomic-transitions-varying-size:
    - shard-adlp:         NOTRUN -> [SKIP][48] ([Intel XE#309]) +8 other tests skip
   [48]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155586v2/shard-adlp-9/igt@kms_cursor_legacy@cursorb-vs-flipa-atomic-transitions-varying-size.html
    - shard-bmg:          [PASS][49] -> [SKIP][50] ([Intel XE#2291]) +4 other tests skip
   [49]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3928-f019aaad58112f89234f7b68557c831846437008/shard-bmg-4/igt@kms_cursor_legacy@cursorb-vs-flipa-atomic-transitions-varying-size.html
   [50]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155586v2/shard-bmg-6/igt@kms_cursor_legacy@cursorb-vs-flipa-atomic-transitions-varying-size.html

  * igt@kms_cursor_legacy@flip-vs-cursor-atomic:
    - shard-bmg:          [PASS][51] -> [FAIL][52] ([Intel XE#1475])
   [51]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3928-f019aaad58112f89234f7b68557c831846437008/shard-bmg-7/igt@kms_cursor_legacy@flip-vs-cursor-atomic.html
   [52]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155586v2/shard-bmg-8/igt@kms_cursor_legacy@flip-vs-cursor-atomic.html

  * igt@kms_cursor_legacy@short-busy-flip-before-cursor-atomic-transitions-varying-size:
    - shard-adlp:         NOTRUN -> [SKIP][53] ([Intel XE#323])
   [53]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155586v2/shard-adlp-2/igt@kms_cursor_legacy@short-busy-flip-before-cursor-atomic-transitions-varying-size.html

  * igt@kms_dirtyfb@fbc-dirtyfb-ioctl:
    - shard-bmg:          NOTRUN -> [SKIP][54] ([Intel XE#5428])
   [54]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155586v2/shard-bmg-7/igt@kms_dirtyfb@fbc-dirtyfb-ioctl.html

  * igt@kms_dither@fb-8bpc-vs-panel-6bpc@pipe-a-hdmi-a-3:
    - shard-bmg:          NOTRUN -> [SKIP][55] ([Intel XE#1340])
   [55]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155586v2/shard-bmg-2/igt@kms_dither@fb-8bpc-vs-panel-6bpc@pipe-a-hdmi-a-3.html

  * igt@kms_dp_link_training@non-uhbr-mst:
    - shard-dg2-set2:     NOTRUN -> [SKIP][56] ([Intel XE#4354])
   [56]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155586v2/shard-dg2-433/igt@kms_dp_link_training@non-uhbr-mst.html

  * igt@kms_dp_link_training@non-uhbr-sst:
    - shard-adlp:         NOTRUN -> [SKIP][57] ([Intel XE#4354])
   [57]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155586v2/shard-adlp-6/igt@kms_dp_link_training@non-uhbr-sst.html

  * igt@kms_dp_link_training@uhbr-sst:
    - shard-adlp:         NOTRUN -> [SKIP][58] ([Intel XE#4356])
   [58]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155586v2/shard-adlp-9/igt@kms_dp_link_training@uhbr-sst.html

  * igt@kms_dp_linktrain_fallback@dp-fallback:
    - shard-adlp:         NOTRUN -> [SKIP][59] ([Intel XE#4331])
   [59]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155586v2/shard-adlp-2/igt@kms_dp_linktrain_fallback@dp-fallback.html

  * igt@kms_fbc_dirty_rect@fbc-dirty-rectangle-dirtyfb-tests:
    - shard-adlp:         NOTRUN -> [SKIP][60] ([Intel XE#4422]) +1 other test skip
   [60]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155586v2/shard-adlp-8/igt@kms_fbc_dirty_rect@fbc-dirty-rectangle-dirtyfb-tests.html

  * igt@kms_feature_discovery@chamelium:
    - shard-adlp:         NOTRUN -> [SKIP][61] ([Intel XE#701])
   [61]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155586v2/shard-adlp-6/igt@kms_feature_discovery@chamelium.html

  * igt@kms_feature_discovery@display-3x:
    - shard-dg2-set2:     NOTRUN -> [SKIP][62] ([Intel XE#703])
   [62]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155586v2/shard-dg2-433/igt@kms_feature_discovery@display-3x.html

  * igt@kms_feature_discovery@display-4x:
    - shard-adlp:         NOTRUN -> [SKIP][63] ([Intel XE#1138])
   [63]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155586v2/shard-adlp-9/igt@kms_feature_discovery@display-4x.html

  * igt@kms_feature_discovery@dp-mst:
    - shard-bmg:          NOTRUN -> [SKIP][64] ([Intel XE#2375])
   [64]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155586v2/shard-bmg-2/igt@kms_feature_discovery@dp-mst.html

  * igt@kms_flip@2x-flip-vs-dpms-on-nop-interruptible:
    - shard-adlp:         NOTRUN -> [SKIP][65] ([Intel XE#310]) +12 other tests skip
   [65]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155586v2/shard-adlp-1/igt@kms_flip@2x-flip-vs-dpms-on-nop-interruptible.html

  * igt@kms_flip@2x-plain-flip-fb-recreate-interruptible:
    - shard-bmg:          [PASS][66] -> [SKIP][67] ([Intel XE#2316]) +5 other tests skip
   [66]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3928-f019aaad58112f89234f7b68557c831846437008/shard-bmg-4/igt@kms_flip@2x-plain-flip-fb-recreate-interruptible.html
   [67]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155586v2/shard-bmg-6/igt@kms_flip@2x-plain-flip-fb-recreate-interruptible.html

  * igt@kms_flip@flip-vs-expired-vblank-interruptible@b-edp1:
    - shard-lnl:          [PASS][68] -> [FAIL][69] ([Intel XE#301]) +4 other tests fail
   [68]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3928-f019aaad58112f89234f7b68557c831846437008/shard-lnl-1/igt@kms_flip@flip-vs-expired-vblank-interruptible@b-edp1.html
   [69]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155586v2/shard-lnl-1/igt@kms_flip@flip-vs-expired-vblank-interruptible@b-edp1.html

  * igt@kms_flip@flip-vs-panning-interruptible:
    - shard-adlp:         NOTRUN -> [DMESG-WARN][70] ([Intel XE#4543] / [Intel XE#5208])
   [70]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155586v2/shard-adlp-2/igt@kms_flip@flip-vs-panning-interruptible.html

  * igt@kms_flip@flip-vs-suspend-interruptible:
    - shard-adlp:         NOTRUN -> [DMESG-WARN][71] ([Intel XE#4543]) +16 other tests dmesg-warn
   [71]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155586v2/shard-adlp-1/igt@kms_flip@flip-vs-suspend-interruptible.html

  * igt@kms_flip@flip-vs-suspend@b-hdmi-a1:
    - shard-adlp:         [PASS][72] -> [DMESG-WARN][73] ([Intel XE#4543]) +7 other tests dmesg-warn
   [72]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3928-f019aaad58112f89234f7b68557c831846437008/shard-adlp-6/igt@kms_flip@flip-vs-suspend@b-hdmi-a1.html
   [73]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155586v2/shard-adlp-6/igt@kms_flip@flip-vs-suspend@b-hdmi-a1.html

  * igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-32bpp-ytileccs-upscaling:
    - shard-bmg:          NOTRUN -> [SKIP][74] ([Intel XE#2293] / [Intel XE#2380])
   [74]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155586v2/shard-bmg-2/igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-32bpp-ytileccs-upscaling.html

  * igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-32bpp-ytileccs-upscaling@pipe-a-valid-mode:
    - shard-bmg:          NOTRUN -> [SKIP][75] ([Intel XE#2293])
   [75]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155586v2/shard-bmg-2/igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-32bpp-ytileccs-upscaling@pipe-a-valid-mode.html

  * igt@kms_flip_scaled_crc@flip-32bpp-ytileccs-to-64bpp-ytile-downscaling:
    - shard-dg2-set2:     NOTRUN -> [SKIP][76] ([Intel XE#455]) +1 other test skip
   [76]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155586v2/shard-dg2-464/igt@kms_flip_scaled_crc@flip-32bpp-ytileccs-to-64bpp-ytile-downscaling.html

  * igt@kms_frontbuffer_tracking@fbc-1p-primscrn-pri-indfb-draw-mmap-wc:
    - shard-bmg:          NOTRUN -> [SKIP][77] ([Intel XE#5390]) +2 other tests skip
   [77]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155586v2/shard-bmg-7/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-pri-indfb-draw-mmap-wc.html

  * igt@kms_frontbuffer_tracking@fbcdrrs-1p-pri-indfb-multidraw:
    - shard-bmg:          NOTRUN -> [SKIP][78] ([Intel XE#2311]) +9 other tests skip
   [78]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155586v2/shard-bmg-2/igt@kms_frontbuffer_tracking@fbcdrrs-1p-pri-indfb-multidraw.html

  * igt@kms_frontbuffer_tracking@fbcdrrs-1p-primscrn-cur-indfb-onoff:
    - shard-adlp:         NOTRUN -> [SKIP][79] ([Intel XE#651]) +21 other tests skip
   [79]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155586v2/shard-adlp-9/igt@kms_frontbuffer_tracking@fbcdrrs-1p-primscrn-cur-indfb-onoff.html

  * igt@kms_frontbuffer_tracking@fbcdrrs-tiling-4:
    - shard-dg2-set2:     NOTRUN -> [SKIP][80] ([Intel XE#651]) +12 other tests skip
   [80]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155586v2/shard-dg2-433/igt@kms_frontbuffer_tracking@fbcdrrs-tiling-4.html

  * igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-pri-shrfb-draw-blt:
    - shard-bmg:          NOTRUN -> [SKIP][81] ([Intel XE#2313]) +9 other tests skip
   [81]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155586v2/shard-bmg-2/igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-pri-shrfb-draw-blt.html

  * igt@kms_frontbuffer_tracking@psr-1p-primscrn-cur-indfb-draw-blt:
    - shard-adlp:         NOTRUN -> [SKIP][82] ([Intel XE#653]) +22 other tests skip
   [82]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155586v2/shard-adlp-9/igt@kms_frontbuffer_tracking@psr-1p-primscrn-cur-indfb-draw-blt.html

  * igt@kms_frontbuffer_tracking@psr-2p-scndscrn-pri-shrfb-draw-blt:
    - shard-adlp:         NOTRUN -> [SKIP][83] ([Intel XE#656]) +78 other tests skip
   [83]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155586v2/shard-adlp-2/igt@kms_frontbuffer_tracking@psr-2p-scndscrn-pri-shrfb-draw-blt.html

  * igt@kms_frontbuffer_tracking@psr-2p-scndscrn-spr-indfb-draw-render:
    - shard-dg2-set2:     NOTRUN -> [SKIP][84] ([Intel XE#653]) +9 other tests skip
   [84]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155586v2/shard-dg2-433/igt@kms_frontbuffer_tracking@psr-2p-scndscrn-spr-indfb-draw-render.html

  * igt@kms_hdr@invalid-hdr:
    - shard-bmg:          [PASS][85] -> [SKIP][86] ([Intel XE#1503])
   [85]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3928-f019aaad58112f89234f7b68557c831846437008/shard-bmg-2/igt@kms_hdr@invalid-hdr.html
   [86]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155586v2/shard-bmg-1/igt@kms_hdr@invalid-hdr.html

  * igt@kms_joiner@basic-big-joiner:
    - shard-adlp:         NOTRUN -> [SKIP][87] ([Intel XE#346])
   [87]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155586v2/shard-adlp-9/igt@kms_joiner@basic-big-joiner.html

  * igt@kms_joiner@basic-ultra-joiner:
    - shard-adlp:         NOTRUN -> [SKIP][88] ([Intel XE#2927])
   [88]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155586v2/shard-adlp-8/igt@kms_joiner@basic-ultra-joiner.html

  * igt@kms_joiner@invalid-modeset-force-big-joiner:
    - shard-adlp:         NOTRUN -> [SKIP][89] ([Intel XE#3012])
   [89]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155586v2/shard-adlp-9/igt@kms_joiner@invalid-modeset-force-big-joiner.html

  * igt@kms_plane@pixel-format-source-clamping@pipe-b-plane-0:
    - shard-adlp:         NOTRUN -> [FAIL][90] ([Intel XE#5195]) +4 other tests fail
   [90]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155586v2/shard-adlp-8/igt@kms_plane@pixel-format-source-clamping@pipe-b-plane-0.html

  * igt@kms_plane_multiple@2x-tiling-4:
    - shard-adlp:         NOTRUN -> [SKIP][91] ([Intel XE#4596])
   [91]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155586v2/shard-adlp-6/igt@kms_plane_multiple@2x-tiling-4.html

  * igt@kms_plane_scaling@intel-max-src-size:
    - shard-adlp:         NOTRUN -> [SKIP][92] ([Intel XE#455]) +40 other tests skip
   [92]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155586v2/shard-adlp-1/igt@kms_plane_scaling@intel-max-src-size.html

  * igt@kms_plane_scaling@planes-upscale-factor-0-25-downscale-factor-0-5:
    - shard-bmg:          NOTRUN -> [SKIP][93] ([Intel XE#2763]) +4 other tests skip
   [93]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155586v2/shard-bmg-2/igt@kms_plane_scaling@planes-upscale-factor-0-25-downscale-factor-0-5.html

  * igt@kms_pm_backlight@brightness-with-dpms:
    - shard-adlp:         NOTRUN -> [SKIP][94] ([Intel XE#2938])
   [94]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155586v2/shard-adlp-6/igt@kms_pm_backlight@brightness-with-dpms.html

  * igt@kms_pm_backlight@fade-with-dpms:
    - shard-adlp:         NOTRUN -> [SKIP][95] ([Intel XE#870]) +1 other test skip
   [95]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155586v2/shard-adlp-1/igt@kms_pm_backlight@fade-with-dpms.html

  * igt@kms_pm_dc@dc6-dpms:
    - shard-adlp:         NOTRUN -> [FAIL][96] ([Intel XE#718])
   [96]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155586v2/shard-adlp-9/igt@kms_pm_dc@dc6-dpms.html

  * igt@kms_pm_dc@dc9-dpms:
    - shard-adlp:         NOTRUN -> [SKIP][97] ([Intel XE#734])
   [97]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155586v2/shard-adlp-8/igt@kms_pm_dc@dc9-dpms.html

  * igt@kms_pm_dc@deep-pkgc:
    - shard-adlp:         NOTRUN -> [SKIP][98] ([Intel XE#2007])
   [98]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155586v2/shard-adlp-9/igt@kms_pm_dc@deep-pkgc.html

  * igt@kms_pm_rpm@dpms-non-lpsp:
    - shard-adlp:         NOTRUN -> [SKIP][99] ([Intel XE#836]) +1 other test skip
   [99]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155586v2/shard-adlp-9/igt@kms_pm_rpm@dpms-non-lpsp.html

  * igt@kms_psr2_sf@fbc-psr2-cursor-plane-move-continuous-sf:
    - shard-adlp:         NOTRUN -> [SKIP][100] ([Intel XE#1406] / [Intel XE#1489]) +17 other tests skip
   [100]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155586v2/shard-adlp-2/igt@kms_psr2_sf@fbc-psr2-cursor-plane-move-continuous-sf.html

  * igt@kms_psr2_sf@pr-cursor-plane-move-continuous-sf:
    - shard-dg2-set2:     NOTRUN -> [SKIP][101] ([Intel XE#1406] / [Intel XE#1489]) +4 other tests skip
   [101]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155586v2/shard-dg2-433/igt@kms_psr2_sf@pr-cursor-plane-move-continuous-sf.html

  * igt@kms_psr2_sf@pr-overlay-plane-move-continuous-exceed-fully-sf:
    - shard-bmg:          NOTRUN -> [SKIP][102] ([Intel XE#1406] / [Intel XE#1489])
   [102]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155586v2/shard-bmg-2/igt@kms_psr2_sf@pr-overlay-plane-move-continuous-exceed-fully-sf.html

  * igt@kms_psr2_su@page_flip-xrgb8888:
    - shard-adlp:         NOTRUN -> [SKIP][103] ([Intel XE#1122] / [Intel XE#1406] / [Intel XE#5580])
   [103]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155586v2/shard-adlp-6/igt@kms_psr2_su@page_flip-xrgb8888.html

  * igt@kms_psr@fbc-psr2-cursor-plane-move:
    - shard-adlp:         NOTRUN -> [SKIP][104] ([Intel XE#1406] / [Intel XE#2850] / [Intel XE#929]) +21 other tests skip
   [104]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155586v2/shard-adlp-9/igt@kms_psr@fbc-psr2-cursor-plane-move.html

  * igt@kms_psr@fbc-psr2-sprite-plane-onoff:
    - shard-dg2-set2:     NOTRUN -> [SKIP][105] ([Intel XE#1406] / [Intel XE#2850] / [Intel XE#929]) +5 other tests skip
   [105]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155586v2/shard-dg2-433/igt@kms_psr@fbc-psr2-sprite-plane-onoff.html

  * igt@kms_psr@psr2-sprite-blt:
    - shard-bmg:          NOTRUN -> [SKIP][106] ([Intel XE#1406] / [Intel XE#2234] / [Intel XE#2850]) +5 other tests skip
   [106]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155586v2/shard-bmg-2/igt@kms_psr@psr2-sprite-blt.html

  * igt@kms_psr_stress_test@invalidate-primary-flip-overlay:
    - shard-adlp:         NOTRUN -> [SKIP][107] ([Intel XE#1406] / [Intel XE#2939] / [Intel XE#5585]) +1 other test skip
   [107]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155586v2/shard-adlp-9/igt@kms_psr_stress_test@invalidate-primary-flip-overlay.html

  * igt@kms_rotation_crc@primary-rotation-270:
    - shard-bmg:          NOTRUN -> [SKIP][108] ([Intel XE#3414] / [Intel XE#3904]) +1 other test skip
   [108]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155586v2/shard-bmg-2/igt@kms_rotation_crc@primary-rotation-270.html

  * igt@kms_rotation_crc@primary-rotation-90:
    - shard-adlp:         NOTRUN -> [SKIP][109] ([Intel XE#3414]) +4 other tests skip
   [109]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155586v2/shard-adlp-6/igt@kms_rotation_crc@primary-rotation-90.html

  * igt@kms_tiled_display@basic-test-pattern:
    - shard-adlp:         NOTRUN -> [SKIP][110] ([Intel XE#362]) +1 other test skip
   [110]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155586v2/shard-adlp-9/igt@kms_tiled_display@basic-test-pattern.html

  * igt@kms_vrr@cmrr:
    - shard-bmg:          NOTRUN -> [SKIP][111] ([Intel XE#2168])
   [111]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155586v2/shard-bmg-2/igt@kms_vrr@cmrr.html

  * igt@kms_vrr@lobf:
    - shard-adlp:         NOTRUN -> [SKIP][112] ([Intel XE#2168])
   [112]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155586v2/shard-adlp-6/igt@kms_vrr@lobf.html

  * igt@xe_ccs@large-ctrl-surf-copy:
    - shard-adlp:         NOTRUN -> [SKIP][113] ([Intel XE#3576] / [Intel XE#5610])
   [113]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155586v2/shard-adlp-9/igt@xe_ccs@large-ctrl-surf-copy.html

  * igt@xe_ccs@suspend-resume:
    - shard-adlp:         NOTRUN -> [SKIP][114] ([Intel XE#455] / [Intel XE#488] / [Intel XE#5607]) +2 other tests skip
   [114]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155586v2/shard-adlp-1/igt@xe_ccs@suspend-resume.html

  * igt@xe_compute@ccs-mode-basic:
    - shard-adlp:         NOTRUN -> [SKIP][115] ([Intel XE#1447] / [Intel XE#5617])
   [115]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155586v2/shard-adlp-9/igt@xe_compute@ccs-mode-basic.html

  * igt@xe_compute@ccs-mode-compute-kernel:
    - shard-bmg:          NOTRUN -> [FAIL][116] ([Intel XE#5963])
   [116]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155586v2/shard-bmg-2/igt@xe_compute@ccs-mode-compute-kernel.html

  * igt@xe_compute_preempt@compute-preempt-many-all-ram:
    - shard-dg2-set2:     NOTRUN -> [SKIP][117] ([Intel XE#6360])
   [117]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155586v2/shard-dg2-433/igt@xe_compute_preempt@compute-preempt-many-all-ram.html

  * igt@xe_configfs@survivability-mode:
    - shard-adlp:         NOTRUN -> [SKIP][118] ([Intel XE#6010])
   [118]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155586v2/shard-adlp-2/igt@xe_configfs@survivability-mode.html

  * igt@xe_copy_basic@mem-copy-linear-0x369:
    - shard-adlp:         NOTRUN -> [SKIP][119] ([Intel XE#1123]) +1 other test skip
   [119]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155586v2/shard-adlp-6/igt@xe_copy_basic@mem-copy-linear-0x369.html

  * igt@xe_copy_basic@mem-set-linear-0xfffe:
    - shard-adlp:         NOTRUN -> [SKIP][120] ([Intel XE#1126])
   [120]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155586v2/shard-adlp-6/igt@xe_copy_basic@mem-set-linear-0xfffe.html

  * igt@xe_create@create-big-vram:
    - shard-adlp:         NOTRUN -> [SKIP][121] ([Intel XE#1062])
   [121]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155586v2/shard-adlp-9/igt@xe_create@create-big-vram.html

  * igt@xe_create@multigpu-create-massive-size:
    - shard-adlp:         NOTRUN -> [SKIP][122] ([Intel XE#944]) +5 other tests skip
   [122]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155586v2/shard-adlp-9/igt@xe_create@multigpu-create-massive-size.html

  * igt@xe_eu_stall@blocking-re-enable:
    - shard-adlp:         NOTRUN -> [SKIP][123] ([Intel XE#5626]) +2 other tests skip
   [123]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155586v2/shard-adlp-9/igt@xe_eu_stall@blocking-re-enable.html

  * igt@xe_eu_stall@invalid-gt-id:
    - shard-dg2-set2:     NOTRUN -> [SKIP][124] ([Intel XE#5626])
   [124]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155586v2/shard-dg2-464/igt@xe_eu_stall@invalid-gt-id.html

  * igt@xe_eudebug_online@reset-with-attention:
    - shard-adlp:         NOTRUN -> [SKIP][125] ([Intel XE#4837] / [Intel XE#5565]) +21 other tests skip
   [125]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155586v2/shard-adlp-9/igt@xe_eudebug_online@reset-with-attention.html

  * igt@xe_eudebug_online@writes-caching-sram-bb-vram-target-sram:
    - shard-dg2-set2:     NOTRUN -> [SKIP][126] ([Intel XE#4837]) +5 other tests skip
   [126]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155586v2/shard-dg2-433/igt@xe_eudebug_online@writes-caching-sram-bb-vram-target-sram.html

  * igt@xe_eudebug_online@writes-caching-vram-bb-vram-target-vram:
    - shard-bmg:          NOTRUN -> [SKIP][127] ([Intel XE#4837]) +6 other tests skip
   [127]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155586v2/shard-bmg-7/igt@xe_eudebug_online@writes-caching-vram-bb-vram-target-vram.html

  * igt@xe_evict@evict-beng-large:
    - shard-adlp:         NOTRUN -> [SKIP][128] ([Intel XE#261] / [Intel XE#5564]) +1 other test skip
   [128]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155586v2/shard-adlp-9/igt@xe_evict@evict-beng-large.html

  * igt@xe_evict@evict-cm-threads-small:
    - shard-adlp:         NOTRUN -> [SKIP][129] ([Intel XE#261] / [Intel XE#688]) +1 other test skip
   [129]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155586v2/shard-adlp-9/igt@xe_evict@evict-cm-threads-small.html

  * igt@xe_evict@evict-small-multi-vm:
    - shard-adlp:         NOTRUN -> [SKIP][130] ([Intel XE#261] / [Intel XE#5564] / [Intel XE#688]) +2 other tests skip
   [130]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155586v2/shard-adlp-9/igt@xe_evict@evict-small-multi-vm.html

  * igt@xe_evict@evict-threads-large:
    - shard-adlp:         NOTRUN -> [SKIP][131] ([Intel XE#261]) +8 other tests skip
   [131]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155586v2/shard-adlp-1/igt@xe_evict@evict-threads-large.html

  * igt@xe_evict_ccs@evict-overcommit-parallel-instantfree-reopen:
    - shard-adlp:         NOTRUN -> [SKIP][132] ([Intel XE#688]) +3 other tests skip
   [132]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155586v2/shard-adlp-6/igt@xe_evict_ccs@evict-overcommit-parallel-instantfree-reopen.html

  * igt@xe_exec_basic@multigpu-no-exec-bindexecqueue:
    - shard-bmg:          NOTRUN -> [SKIP][133] ([Intel XE#2322]) +4 other tests skip
   [133]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155586v2/shard-bmg-7/igt@xe_exec_basic@multigpu-no-exec-bindexecqueue.html

  * igt@xe_exec_basic@multigpu-once-bindexecqueue-userptr-rebind:
    - shard-adlp:         NOTRUN -> [SKIP][134] ([Intel XE#1392] / [Intel XE#5575]) +16 other tests skip
   [134]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155586v2/shard-adlp-2/igt@xe_exec_basic@multigpu-once-bindexecqueue-userptr-rebind.html

  * igt@xe_exec_fault_mode@many-bindexecqueue-userptr-imm:
    - shard-adlp:         NOTRUN -> [SKIP][135] ([Intel XE#288] / [Intel XE#5561]) +46 other tests skip
   [135]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155586v2/shard-adlp-6/igt@xe_exec_fault_mode@many-bindexecqueue-userptr-imm.html

  * igt@xe_exec_fault_mode@many-execqueues-userptr-invalidate-imm:
    - shard-dg2-set2:     NOTRUN -> [SKIP][136] ([Intel XE#288]) +11 other tests skip
   [136]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155586v2/shard-dg2-433/igt@xe_exec_fault_mode@many-execqueues-userptr-invalidate-imm.html

  * igt@xe_exec_mix_modes@exec-simple-batch-store-dma-fence:
    - shard-adlp:         NOTRUN -> [SKIP][137] ([Intel XE#2360])
   [137]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155586v2/shard-adlp-6/igt@xe_exec_mix_modes@exec-simple-batch-store-dma-fence.html

  * igt@xe_exec_mix_modes@exec-spinner-interrupted-dma-fence:
    - shard-dg2-set2:     NOTRUN -> [SKIP][138] ([Intel XE#2360])
   [138]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155586v2/shard-dg2-433/igt@xe_exec_mix_modes@exec-spinner-interrupted-dma-fence.html

  * igt@xe_exec_reset@cat-error:
    - shard-adlp:         NOTRUN -> [DMESG-WARN][139] ([Intel XE#3868])
   [139]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155586v2/shard-adlp-8/igt@xe_exec_reset@cat-error.html

  * igt@xe_exec_system_allocator@many-execqueues-mmap-huge-nomemset:
    - shard-bmg:          NOTRUN -> [SKIP][140] ([Intel XE#4943]) +11 other tests skip
   [140]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155586v2/shard-bmg-7/igt@xe_exec_system_allocator@many-execqueues-mmap-huge-nomemset.html

  * igt@xe_exec_system_allocator@process-many-execqueues-mmap-nomemset:
    - shard-adlp:         NOTRUN -> [SKIP][141] ([Intel XE#4915]) +467 other tests skip
   [141]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155586v2/shard-adlp-9/igt@xe_exec_system_allocator@process-many-execqueues-mmap-nomemset.html

  * igt@xe_exec_system_allocator@processes-evict-malloc-mix-bo:
    - shard-bmg:          [PASS][142] -> [ABORT][143] ([Intel XE#3970])
   [142]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3928-f019aaad58112f89234f7b68557c831846437008/shard-bmg-5/igt@xe_exec_system_allocator@processes-evict-malloc-mix-bo.html
   [143]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155586v2/shard-bmg-6/igt@xe_exec_system_allocator@processes-evict-malloc-mix-bo.html

  * igt@xe_exec_system_allocator@twice-mmap-new-huge:
    - shard-dg2-set2:     NOTRUN -> [SKIP][144] ([Intel XE#4915]) +114 other tests skip
   [144]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155586v2/shard-dg2-433/igt@xe_exec_system_allocator@twice-mmap-new-huge.html

  * igt@xe_fault_injection@probe-fail-guc-xe_guc_ct_send_recv:
    - shard-adlp:         NOTRUN -> [ABORT][145] ([Intel XE#4917] / [Intel XE#5530])
   [145]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155586v2/shard-adlp-8/igt@xe_fault_injection@probe-fail-guc-xe_guc_ct_send_recv.html

  * igt@xe_live_ktest@xe_dma_buf:
    - shard-dg2-set2:     NOTRUN -> [FAIL][146] ([Intel XE#3099]) +1 other test fail
   [146]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155586v2/shard-dg2-433/igt@xe_live_ktest@xe_dma_buf.html

  * igt@xe_mmap@pci-membarrier:
    - shard-adlp:         NOTRUN -> [SKIP][147] ([Intel XE#5100])
   [147]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155586v2/shard-adlp-6/igt@xe_mmap@pci-membarrier.html

  * igt@xe_module_load@force-load:
    - shard-adlp:         NOTRUN -> [SKIP][148] ([Intel XE#378] / [Intel XE#5612])
   [148]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155586v2/shard-adlp-9/igt@xe_module_load@force-load.html

  * igt@xe_oa@buffer-fill:
    - shard-adlp:         NOTRUN -> [SKIP][149] ([Intel XE#3573]) +11 other tests skip
   [149]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155586v2/shard-adlp-9/igt@xe_oa@buffer-fill.html

  * igt@xe_oa@mmio-triggered-reports:
    - shard-dg2-set2:     NOTRUN -> [SKIP][150] ([Intel XE#3573]) +3 other tests skip
   [150]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155586v2/shard-dg2-433/igt@xe_oa@mmio-triggered-reports.html

  * igt@xe_oa@mmio-triggered-reports-read:
    - shard-adlp:         NOTRUN -> [SKIP][151] ([Intel XE#6032]) +1 other test skip
   [151]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155586v2/shard-adlp-9/igt@xe_oa@mmio-triggered-reports-read.html

  * igt@xe_oa@oa-tlb-invalidate:
    - shard-bmg:          NOTRUN -> [SKIP][152] ([Intel XE#2248])
   [152]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155586v2/shard-bmg-2/igt@xe_oa@oa-tlb-invalidate.html

  * igt@xe_pat@pat-index-xe2:
    - shard-adlp:         NOTRUN -> [SKIP][153] ([Intel XE#977])
   [153]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155586v2/shard-adlp-6/igt@xe_pat@pat-index-xe2.html

  * igt@xe_pat@pat-index-xehpc:
    - shard-adlp:         NOTRUN -> [SKIP][154] ([Intel XE#2838] / [Intel XE#979])
   [154]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155586v2/shard-adlp-2/igt@xe_pat@pat-index-xehpc.html

  * igt@xe_pat@pat-index-xelpg:
    - shard-adlp:         NOTRUN -> [SKIP][155] ([Intel XE#979])
   [155]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155586v2/shard-adlp-9/igt@xe_pat@pat-index-xelpg.html

  * igt@xe_peer2peer@read:
    - shard-adlp:         NOTRUN -> [SKIP][156] ([Intel XE#1061] / [Intel XE#5568])
   [156]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155586v2/shard-adlp-9/igt@xe_peer2peer@read.html

  * igt@xe_pm@d3cold-basic:
    - shard-bmg:          NOTRUN -> [SKIP][157] ([Intel XE#2284])
   [157]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155586v2/shard-bmg-7/igt@xe_pm@d3cold-basic.html

  * igt@xe_pm@d3cold-multiple-execs:
    - shard-adlp:         NOTRUN -> [SKIP][158] ([Intel XE#2284] / [Intel XE#366]) +3 other tests skip
   [158]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155586v2/shard-adlp-9/igt@xe_pm@d3cold-multiple-execs.html

  * igt@xe_pm@s2idle-d3cold-basic-exec:
    - shard-dg2-set2:     NOTRUN -> [SKIP][159] ([Intel XE#2284] / [Intel XE#366])
   [159]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155586v2/shard-dg2-464/igt@xe_pm@s2idle-d3cold-basic-exec.html

  * igt@xe_pm@s4-d3hot-basic-exec:
    - shard-dg2-set2:     NOTRUN -> [FAIL][160] ([Intel XE#6339])
   [160]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155586v2/shard-dg2-433/igt@xe_pm@s4-d3hot-basic-exec.html

  * igt@xe_pm@vram-d3cold-threshold:
    - shard-adlp:         NOTRUN -> [SKIP][161] ([Intel XE#5611] / [Intel XE#579])
   [161]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155586v2/shard-adlp-9/igt@xe_pm@vram-d3cold-threshold.html

  * igt@xe_pmu@all-fn-engine-activity-load@engine-drm_xe_engine_class_render0:
    - shard-adlp:         NOTRUN -> [TIMEOUT][162] ([Intel XE#5213]) +1 other test timeout
   [162]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155586v2/shard-adlp-2/igt@xe_pmu@all-fn-engine-activity-load@engine-drm_xe_engine_class_render0.html

  * igt@xe_pxp@pxp-stale-bo-bind-post-termination-irq:
    - shard-adlp:         NOTRUN -> [SKIP][163] ([Intel XE#4733] / [Intel XE#5594]) +4 other tests skip
   [163]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155586v2/shard-adlp-2/igt@xe_pxp@pxp-stale-bo-bind-post-termination-irq.html

  * igt@xe_pxp@pxp-termination-key-update-post-rpm:
    - shard-dg2-set2:     NOTRUN -> [SKIP][164] ([Intel XE#4733]) +2 other tests skip
   [164]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155586v2/shard-dg2-433/igt@xe_pxp@pxp-termination-key-update-post-rpm.html

  * igt@xe_query@multigpu-query-invalid-extension:
    - shard-bmg:          NOTRUN -> [SKIP][165] ([Intel XE#944])
   [165]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155586v2/shard-bmg-2/igt@xe_query@multigpu-query-invalid-extension.html

  * igt@xe_render_copy@render-stress-4-copies:
    - shard-adlp:         NOTRUN -> [SKIP][166] ([Intel XE#4814] / [Intel XE#5614])
   [166]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155586v2/shard-adlp-1/igt@xe_render_copy@render-stress-4-copies.html

  * igt@xe_spin_batch@spin-mem-copy:
    - shard-adlp:         NOTRUN -> [SKIP][167] ([Intel XE#4821])
   [167]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155586v2/shard-adlp-2/igt@xe_spin_batch@spin-mem-copy.html

  * igt@xe_sriov_flr@flr-each-isolation:
    - shard-dg2-set2:     NOTRUN -> [SKIP][168] ([Intel XE#3342])
   [168]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155586v2/shard-dg2-433/igt@xe_sriov_flr@flr-each-isolation.html

  * igt@xe_sriov_scheduling@equal-throughput:
    - shard-adlp:         NOTRUN -> [DMESG-FAIL][169] ([Intel XE#3868] / [Intel XE#5213]) +1 other test dmesg-fail
   [169]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155586v2/shard-adlp-8/igt@xe_sriov_scheduling@equal-throughput.html

  
#### Possible fixes ####

  * igt@kms_ccs@crc-primary-suspend-4-tiled-dg2-mc-ccs@pipe-d-dp-4:
    - shard-dg2-set2:     [INCOMPLETE][170] ([Intel XE#3862]) -> [PASS][171] +1 other test pass
   [170]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3928-f019aaad58112f89234f7b68557c831846437008/shard-dg2-466/igt@kms_ccs@crc-primary-suspend-4-tiled-dg2-mc-ccs@pipe-d-dp-4.html
   [171]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155586v2/shard-dg2-464/igt@kms_ccs@crc-primary-suspend-4-tiled-dg2-mc-ccs@pipe-d-dp-4.html

  * igt@kms_color@ctm-0-50@pipe-a-dp-2:
    - shard-bmg:          [SKIP][172] -> [PASS][173]
   [172]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3928-f019aaad58112f89234f7b68557c831846437008/shard-bmg-6/igt@kms_color@ctm-0-50@pipe-a-dp-2.html
   [173]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155586v2/shard-bmg-7/igt@kms_color@ctm-0-50@pipe-a-dp-2.html

  * igt@kms_cursor_legacy@cursora-vs-flipb-legacy:
    - shard-bmg:          [DMESG-WARN][174] ([Intel XE#3428]) -> [PASS][175]
   [174]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3928-f019aaad58112f89234f7b68557c831846437008/shard-bmg-6/igt@kms_cursor_legacy@cursora-vs-flipb-legacy.html
   [175]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155586v2/shard-bmg-8/igt@kms_cursor_legacy@cursora-vs-flipb-legacy.html

  * igt@kms_cursor_legacy@flip-vs-cursor-legacy:
    - shard-bmg:          [FAIL][176] ([Intel XE#5299]) -> [PASS][177]
   [176]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3928-f019aaad58112f89234f7b68557c831846437008/shard-bmg-8/igt@kms_cursor_legacy@flip-vs-cursor-legacy.html
   [177]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155586v2/shard-bmg-2/igt@kms_cursor_legacy@flip-vs-cursor-legacy.html

  * igt@kms_flip@2x-absolute-wf_vblank-interruptible@cd-dp2-hdmi-a3:
    - shard-bmg:          [FAIL][178] ([Intel XE#5352]) -> [PASS][179] +4 other tests pass
   [178]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3928-f019aaad58112f89234f7b68557c831846437008/shard-bmg-6/igt@kms_flip@2x-absolute-wf_vblank-interruptible@cd-dp2-hdmi-a3.html
   [179]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155586v2/shard-bmg-7/igt@kms_flip@2x-absolute-wf_vblank-interruptible@cd-dp2-hdmi-a3.html

  * igt@kms_flip@basic-plain-flip@b-hdmi-a1:
    - shard-adlp:         [DMESG-WARN][180] ([Intel XE#4543]) -> [PASS][181] +5 other tests pass
   [180]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3928-f019aaad58112f89234f7b68557c831846437008/shard-adlp-6/igt@kms_flip@basic-plain-flip@b-hdmi-a1.html
   [181]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155586v2/shard-adlp-6/igt@kms_flip@basic-plain-flip@b-hdmi-a1.html

  * igt@kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-move:
    - shard-dg2-set2:     [INCOMPLETE][182] ([Intel XE#4842]) -> [PASS][183]
   [182]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3928-f019aaad58112f89234f7b68557c831846437008/shard-dg2-436/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-move.html
   [183]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155586v2/shard-dg2-466/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-move.html

  * igt@kms_plane_alpha_blend@constant-alpha-mid:
    - shard-bmg:          [SKIP][184] ([Intel XE#4848]) -> [PASS][185]
   [184]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3928-f019aaad58112f89234f7b68557c831846437008/shard-bmg-6/igt@kms_plane_alpha_blend@constant-alpha-mid.html
   [185]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155586v2/shard-bmg-7/igt@kms_plane_alpha_blend@constant-alpha-mid.html

  * igt@kms_vblank@ts-continuation-dpms-suspend:
    - shard-adlp:         [DMESG-WARN][186] ([Intel XE#2953] / [Intel XE#4173]) -> [PASS][187] +1 other test pass
   [186]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3928-f019aaad58112f89234f7b68557c831846437008/shard-adlp-9/igt@kms_vblank@ts-continuation-dpms-suspend.html
   [187]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155586v2/shard-adlp-2/igt@kms_vblank@ts-continuation-dpms-suspend.html

  * igt@kms_vrr@negative-basic:
    - shard-bmg:          [SKIP][188] ([Intel XE#1499]) -> [PASS][189]
   [188]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3928-f019aaad58112f89234f7b68557c831846437008/shard-bmg-6/igt@kms_vrr@negative-basic.html
   [189]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155586v2/shard-bmg-7/igt@kms_vrr@negative-basic.html

  * igt@xe_evict@evict-mixed-many-threads-small:
    - shard-bmg:          [INCOMPLETE][190] ([Intel XE#6321]) -> [PASS][191]
   [190]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3928-f019aaad58112f89234f7b68557c831846437008/shard-bmg-7/igt@xe_evict@evict-mixed-many-threads-small.html
   [191]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155586v2/shard-bmg-4/igt@xe_evict@evict-mixed-many-threads-small.html

  * igt@xe_exec_system_allocator@many-stride-mmap-mlock:
    - shard-bmg:          [DMESG-WARN][192] -> [PASS][193]
   [192]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3928-f019aaad58112f89234f7b68557c831846437008/shard-bmg-1/igt@xe_exec_system_allocator@many-stride-mmap-mlock.html
   [193]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155586v2/shard-bmg-7/igt@xe_exec_system_allocator@many-stride-mmap-mlock.html

  
#### Warnings ####

  * igt@kms_flip@flip-vs-rmfb:
    - shard-adlp:         [DMESG-WARN][194] ([Intel XE#4543] / [Intel XE#5208]) -> [DMESG-WARN][195] ([Intel XE#5208])
   [194]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3928-f019aaad58112f89234f7b68557c831846437008/shard-adlp-9/igt@kms_flip@flip-vs-rmfb.html
   [195]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155586v2/shard-adlp-2/igt@kms_flip@flip-vs-rmfb.html

  * igt@kms_frontbuffer_tracking@drrs-2p-primscrn-cur-indfb-draw-blt:
    - shard-bmg:          [SKIP][196] ([Intel XE#2312]) -> [SKIP][197] ([Intel XE#2311]) +1 other test skip
   [196]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3928-f019aaad58112f89234f7b68557c831846437008/shard-bmg-6/igt@kms_frontbuffer_tracking@drrs-2p-primscrn-cur-indfb-draw-blt.html
   [197]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155586v2/shard-bmg-7/igt@kms_frontbuffer_tracking@drrs-2p-primscrn-cur-indfb-draw-blt.html

  * igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-cur-indfb-draw-render:
    - shard-bmg:          [SKIP][198] ([Intel XE#5390]) -> [SKIP][199] ([Intel XE#2312]) +3 other tests skip
   [198]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3928-f019aaad58112f89234f7b68557c831846437008/shard-bmg-5/igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-cur-indfb-draw-render.html
   [199]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155586v2/shard-bmg-6/igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-cur-indfb-draw-render.html

  * igt@kms_frontbuffer_tracking@fbcdrrs-2p-primscrn-cur-indfb-draw-blt:
    - shard-bmg:          [SKIP][200] ([Intel XE#2311]) -> [SKIP][201] ([Intel XE#2312]) +9 other tests skip
   [200]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3928-f019aaad58112f89234f7b68557c831846437008/shard-bmg-8/igt@kms_frontbuffer_tracking@fbcdrrs-2p-primscrn-cur-indfb-draw-blt.html
   [201]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155586v2/shard-bmg-6/igt@kms_frontbuffer_tracking@fbcdrrs-2p-primscrn-cur-indfb-draw-blt.html

  * igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-pri-shrfb-draw-render:
    - shard-bmg:          [SKIP][202] ([Intel XE#2312]) -> [SKIP][203] ([Intel XE#2313]) +1 other test skip
   [202]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3928-f019aaad58112f89234f7b68557c831846437008/shard-bmg-6/igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-pri-shrfb-draw-render.html
   [203]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155586v2/shard-bmg-7/igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-pri-shrfb-draw-render.html

  * igt@kms_frontbuffer_tracking@psr-2p-scndscrn-pri-indfb-draw-mmap-wc:
    - shard-bmg:          [SKIP][204] ([Intel XE#2313]) -> [SKIP][205] ([Intel XE#2312]) +11 other tests skip
   [204]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3928-f019aaad58112f89234f7b68557c831846437008/shard-bmg-5/igt@kms_frontbuffer_tracking@psr-2p-scndscrn-pri-indfb-draw-mmap-wc.html
   [205]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155586v2/shard-bmg-6/igt@kms_frontbuffer_tracking@psr-2p-scndscrn-pri-indfb-draw-mmap-wc.html

  * igt@kms_tiled_display@basic-test-pattern:
    - shard-bmg:          [SKIP][206] ([Intel XE#2426]) -> [FAIL][207] ([Intel XE#1729])
   [206]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3928-f019aaad58112f89234f7b68557c831846437008/shard-bmg-2/igt@kms_tiled_display@basic-test-pattern.html
   [207]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155586v2/shard-bmg-1/igt@kms_tiled_display@basic-test-pattern.html

  * igt@xe_fault_injection@probe-fail-guc-xe_guc_ct_send_recv:
    - shard-bmg:          [ABORT][208] ([Intel XE#4917] / [Intel XE#5466] / [Intel XE#5530]) -> [ABORT][209] ([Intel XE#5466] / [Intel XE#5530])
   [208]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3928-f019aaad58112f89234f7b68557c831846437008/shard-bmg-8/igt@xe_fault_injection@probe-fail-guc-xe_guc_ct_send_recv.html
   [209]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155586v2/shard-bmg-6/igt@xe_fault_injection@probe-fail-guc-xe_guc_ct_send_recv.html

  * igt@xe_module_load@load:
    - shard-bmg:          ([PASS][210], [PASS][211], [PASS][212], [PASS][213], [PASS][214], [PASS][215], [PASS][216], [PASS][217], [PASS][218], [PASS][219], [PASS][220], [PASS][221], [SKIP][222], [PASS][223], [PASS][224], [PASS][225], [PASS][226], [PASS][227], [PASS][228], [PASS][229], [PASS][230], [PASS][231], [PASS][232], [PASS][233], [DMESG-WARN][234], [PASS][235]) ([Intel XE#2457] / [Intel XE#3428]) -> ([PASS][236], [PASS][237], [PASS][238], [PASS][239], [PASS][240], [PASS][241], [PASS][242], [PASS][243], [PASS][244], [PASS][245], [PASS][246], [PASS][247], [PASS][248], [PASS][249], [SKIP][250], [PASS][251], [PASS][252], [PASS][253], [PASS][254], [PASS][255], [PASS][256], [PASS][257], [PASS][258], [PASS][259], [PASS][260], [PASS][261]) ([Intel XE#2457])
   [210]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3928-f019aaad58112f89234f7b68557c831846437008/shard-bmg-5/igt@xe_module_load@load.html
   [211]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3928-f019aaad58112f89234f7b68557c831846437008/shard-bmg-6/igt@xe_module_load@load.html
   [212]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3928-f019aaad58112f89234f7b68557c831846437008/shard-bmg-7/igt@xe_module_load@load.html
   [213]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3928-f019aaad58112f89234f7b68557c831846437008/shard-bmg-7/igt@xe_module_load@load.html
   [214]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3928-f019aaad58112f89234f7b68557c831846437008/shard-bmg-1/igt@xe_module_load@load.html
   [215]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3928-f019aaad58112f89234f7b68557c831846437008/shard-bmg-2/igt@xe_module_load@load.html
   [216]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3928-f019aaad58112f89234f7b68557c831846437008/shard-bmg-4/igt@xe_module_load@load.html
   [217]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3928-f019aaad58112f89234f7b68557c831846437008/shard-bmg-4/igt@xe_module_load@load.html
   [218]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3928-f019aaad58112f89234f7b68557c831846437008/shard-bmg-8/igt@xe_module_load@load.html
   [219]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3928-f019aaad58112f89234f7b68557c831846437008/shard-bmg-2/igt@xe_module_load@load.html
   [220]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3928-f019aaad58112f89234f7b68557c831846437008/shard-bmg-5/igt@xe_module_load@load.html
   [221]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3928-f019aaad58112f89234f7b68557c831846437008/shard-bmg-5/igt@xe_module_load@load.html
   [222]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3928-f019aaad58112f89234f7b68557c831846437008/shard-bmg-5/igt@xe_module_load@load.html
   [223]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3928-f019aaad58112f89234f7b68557c831846437008/shard-bmg-4/igt@xe_module_load@load.html
   [224]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3928-f019aaad58112f89234f7b68557c831846437008/shard-bmg-2/igt@xe_module_load@load.html
   [225]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3928-f019aaad58112f89234f7b68557c831846437008/shard-bmg-1/igt@xe_module_load@load.html
   [226]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3928-f019aaad58112f89234f7b68557c831846437008/shard-bmg-1/igt@xe_module_load@load.html
   [227]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3928-f019aaad58112f89234f7b68557c831846437008/shard-bmg-8/igt@xe_module_load@load.html
   [228]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3928-f019aaad58112f89234f7b68557c831846437008/shard-bmg-8/igt@xe_module_load@load.html
   [229]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3928-f019aaad58112f89234f7b68557c831846437008/shard-bmg-8/igt@xe_module_load@load.html
   [230]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3928-f019aaad58112f89234f7b68557c831846437008/shard-bmg-7/igt@xe_module_load@load.html
   [231]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3928-f019aaad58112f89234f7b68557c831846437008/shard-bmg-3/igt@xe_module_load@load.html
   [232]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3928-f019aaad58112f89234f7b68557c831846437008/shard-bmg-3/igt@xe_module_load@load.html
   [233]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3928-f019aaad58112f89234f7b68557c831846437008/shard-bmg-3/igt@xe_module_load@load.html
   [234]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3928-f019aaad58112f89234f7b68557c831846437008/shard-bmg-6/igt@xe_module_load@load.html
   [235]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3928-f019aaad58112f89234f7b68557c831846437008/shard-bmg-6/igt@xe_module_load@load.html
   [236]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155586v2/shard-bmg-6/igt@xe_module_load@load.html
   [237]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155586v2/shard-bmg-1/igt@xe_module_load@load.html
   [238]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155586v2/shard-bmg-1/igt@xe_module_load@load.html
   [239]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155586v2/shard-bmg-6/igt@xe_module_load@load.html
   [240]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155586v2/shard-bmg-1/igt@xe_module_load@load.html
   [241]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155586v2/shard-bmg-1/igt@xe_module_load@load.html
   [242]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155586v2/shard-bmg-8/igt@xe_module_load@load.html
   [243]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155586v2/shard-bmg-8/igt@xe_module_load@load.html
   [244]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155586v2/shard-bmg-2/igt@xe_module_load@load.html
   [245]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155586v2/shard-bmg-2/igt@xe_module_load@load.html
   [246]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155586v2/shard-bmg-6/igt@xe_module_load@load.html
   [247]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155586v2/shard-bmg-7/igt@xe_module_load@load.html
   [248]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155586v2/shard-bmg-3/igt@xe_module_load@load.html
   [249]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155586v2/shard-bmg-3/igt@xe_module_load@load.html
   [250]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155586v2/shard-bmg-4/igt@xe_module_load@load.html
   [251]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155586v2/shard-bmg-2/igt@xe_module_load@load.html
   [252]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155586v2/shard-bmg-7/igt@xe_module_load@load.html
   [253]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155586v2/shard-bmg-7/igt@xe_module_load@load.html
   [254]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155586v2/shard-bmg-4/igt@xe_module_load@load.html
   [255]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155586v2/shard-bmg-4/igt@xe_module_load@load.html
   [256]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155586v2/shard-bmg-3/igt@xe_module_load@load.html
   [257]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155586v2/shard-bmg-8/igt@xe_module_load@load.html
   [258]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155586v2/shard-bmg-4/igt@xe_module_load@load.html
   [259]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155586v2/shard-bmg-5/igt@xe_module_load@load.html
   [260]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155586v2/shard-bmg-5/igt@xe_module_load@load.html
   [261]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155586v2/shard-bmg-2/igt@xe_module_load@load.html

  
  {name}: This element is suppressed. This means it is ignored when computing
          the status of the difference (SUCCESS, WARNING, or FAILURE).

  [Intel XE#1061]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1061
  [Intel XE#1062]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1062
  [Intel XE#1122]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1122
  [Intel XE#1123]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1123
  [Intel XE#1124]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1124
  [Intel XE#1126]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1126
  [Intel XE#1138]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1138
  [Intel XE#1340]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1340
  [Intel XE#1392]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1392
  [Intel XE#1406]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1406
  [Intel XE#1447]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1447
  [Intel XE#1475]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1475
  [Intel XE#1489]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1489
  [Intel XE#1499]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1499
  [Intel XE#1503]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1503
  [Intel XE#1727]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1727
  [Intel XE#1729]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1729
  [Intel XE#1874]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1874
  [Intel XE#2007]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2007
  [Intel XE#2168]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2168
  [Intel XE#2191]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2191
  [Intel XE#2234]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2234
  [Intel XE#2248]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2248
  [Intel XE#2252]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2252
  [Intel XE#2284]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2284
  [Intel XE#2291]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2291
  [Intel XE#2293]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2293
  [Intel XE#2311]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2311
  [Intel XE#2312]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2312
  [Intel XE#2313]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2313
  [Intel XE#2316]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2316
  [Intel XE#2320]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2320
  [Intel XE#2322]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2322
  [Intel XE#2325]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2325
  [Intel XE#2327]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2327
  [Intel XE#2360]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2360
  [Intel XE#2375]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2375
  [Intel XE#2380]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2380
  [Intel XE#2426]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2426
  [Intel XE#2457]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2457
  [Intel XE#261]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/261
  [Intel XE#2705]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2705
  [Intel XE#2763]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2763
  [Intel XE#2838]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2838
  [Intel XE#2850]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2850
  [Intel XE#288]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/288
  [Intel XE#2887]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2887
  [Intel XE#2907]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2907
  [Intel XE#2927]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2927
  [Intel XE#2938]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2938
  [Intel XE#2939]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2939
  [Intel XE#2953]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2953
  [Intel XE#301]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/301
  [Intel XE#3012]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3012
  [Intel XE#306]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/306
  [Intel XE#307]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/307
  [Intel XE#308]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/308
  [Intel XE#309]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/309
  [Intel XE#3099]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3099
  [Intel XE#310]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/310
  [Intel XE#3113]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3113
  [Intel XE#316]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/316
  [Intel XE#323]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/323
  [Intel XE#3342]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3342
  [Intel XE#3414]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3414
  [Intel XE#3428]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3428
  [Intel XE#3442]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3442
  [Intel XE#346]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/346
  [Intel XE#3573]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3573
  [Intel XE#3576]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3576
  [Intel XE#362]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/362
  [Intel XE#366]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/366
  [Intel XE#367]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/367
  [Intel XE#3718]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3718
  [Intel XE#373]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/373
  [Intel XE#378]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/378
  [Intel XE#3862]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3862
  [Intel XE#3868]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3868
  [Intel XE#3904]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3904
  [Intel XE#3970]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3970
  [Intel XE#4173]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4173
  [Intel XE#4212]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4212
  [Intel XE#4331]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4331
  [Intel XE#4345]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4345
  [Intel XE#4354]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4354
  [Intel XE#4356]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4356
  [Intel XE#4416]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4416
  [Intel XE#4422]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4422
  [Intel XE#4522]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4522
  [Intel XE#4543]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4543
  [Intel XE#455]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/455
  [Intel XE#4596]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4596
  [Intel XE#4733]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4733
  [Intel XE#4814]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4814
  [Intel XE#4821]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4821
  [Intel XE#4837]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4837
  [Intel XE#4842]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4842
  [Intel XE#4848]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4848
  [Intel XE#488]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/488
  [Intel XE#4915]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4915
  [Intel XE#4917]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4917
  [Intel XE#4943]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4943
  [Intel XE#5100]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5100
  [Intel XE#5191]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5191
  [Intel XE#5195]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5195
  [Intel XE#5208]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5208
  [Intel XE#5213]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5213
  [Intel XE#5299]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5299
  [Intel XE#5300]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5300
  [Intel XE#5352]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5352
  [Intel XE#5390]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5390
  [Intel XE#5428]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5428
  [Intel XE#5466]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5466
  [Intel XE#5530]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5530
  [Intel XE#5561]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5561
  [Intel XE#5564]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5564
  [Intel XE#5565]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5565
  [Intel XE#5568]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5568
  [Intel XE#5575]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5575
  [Intel XE#5580]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5580
  [Intel XE#5585]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5585
  [Intel XE#5594]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5594
  [Intel XE#5607]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5607
  [Intel XE#5610]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5610
  [Intel XE#5611]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5611
  [Intel XE#5612]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5612
  [Intel XE#5614]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5614
  [Intel XE#5617]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5617
  [Intel XE#5624]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5624
  [Intel XE#5626]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5626
  [Intel XE#579]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/579
  [Intel XE#5963]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5963
  [Intel XE#6010]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6010
  [Intel XE#6032]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6032
  [Intel XE#607]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/607
  [Intel XE#6078]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6078
  [Intel XE#619]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/619
  [Intel XE#6281]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6281
  [Intel XE#6312]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6312
  [Intel XE#6318]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6318
  [Intel XE#6321]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6321
  [Intel XE#6339]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6339
  [Intel XE#6360]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6360
  [Intel XE#651]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/651
  [Intel XE#653]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/653
  [Intel XE#656]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/656
  [Intel XE#688]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/688
  [Intel XE#701]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/701
  [Intel XE#703]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/703
  [Intel XE#718]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/718
  [Intel XE#734]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/734
  [Intel XE#787]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/787
  [Intel XE#836]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/836
  [Intel XE#870]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/870
  [Intel XE#929]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/929
  [Intel XE#944]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/944
  [Intel XE#977]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/977
  [Intel XE#979]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/979


Build changes
-------------

  * Linux: xe-3928-f019aaad58112f89234f7b68557c831846437008 -> xe-pw-155586v2

  IGT_8587: 8587
  xe-3928-f019aaad58112f89234f7b68557c831846437008: f019aaad58112f89234f7b68557c831846437008
  xe-pw-155586v2: 155586v2

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155586v2/index.html

[-- Attachment #2: Type: text/html, Size: 84350 bytes --]

Re: [PATCH v2 3/7] drm/i915/dp: Export helper to determine if FEC on non-UHBR links is required

[Imre Deak]

On Thu, Oct 16, 2025 at 09:23:26PM +0300, Jouni Hogander wrote:
> On Thu, 2025-10-16 at 20:18 +0300, Imre Deak wrote:
> > On Thu, Oct 16, 2025 at 07:56:32PM +0300, Jouni Hogander wrote:
> > > On Wed, 2025-10-15 at 19:19 +0300, Imre Deak wrote:
> > > > Export the helper function to determine if FEC is required on a
> > > > non- UHBR (8b10b) SST or MST link. A follow up change will take
> > > > this into use for MST as well.
> > > > 
> > > > While at it determine the output type from the CRTC state, which
> > > > allows dropping the intel_dp argument. Also make the function
> > > > return the required FEC state, instead of setting this in the
> > > > CRTC state, which allows only querying this requirement, without
> > > > changing the state.
> > > > 
> > > > Also rename the function to intel_dp_needs_8b10b_fec(), to
> > > > clarify that the function determines if FEC is required on an
> > > > 8b10b link (on 128b132b links FEC is always enabled by the HW
> > > > implicitly, so the function will return false for that case).
> > > > 
> > > > Signed-off-by: Imre Deak <imre.deak@intel.com>
> > > > ---
> > > >  drivers/gpu/drm/i915/display/intel_dp.c     | 21 +++++++++++++--
> > > > ----
> > > > --
> > > >  drivers/gpu/drm/i915/display/intel_dp.h     |  2 ++
> > > >  drivers/gpu/drm/i915/display/intel_dp_mst.c |  2 +-
> > > >  3 files changed, 16 insertions(+), 9 deletions(-)
> > > > 
> > > > diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
> > > > b/drivers/gpu/drm/i915/display/intel_dp.c
> > > > index b523c4e661412..3ffb015004c54 100644
> > > > --- a/drivers/gpu/drm/i915/display/intel_dp.c
> > > > +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> > > > @@ -2365,24 +2365,29 @@ static int
> > > > intel_edp_dsc_compute_pipe_bpp(struct intel_dp *intel_dp,
> > > >  	return 0;
> > > >  }
> > > >  
> > > > -static void intel_dp_fec_compute_config(struct intel_dp *intel_dp,
> > > > -					struct intel_crtc_state *crtc_state)
> > > > +/*
> > > > + * Return whether FEC must be enabled for 8b10b SST or MST links. On 128b132b
> > > > + * links FEC is always enabled implicitly by the HW, so this function returns
> > > > + * false for that case.
> > > > + */
> > > > +bool intel_dp_needs_8b10b_fec(const struct intel_crtc_state *crtc_state,
> > > > +			      bool dsc_enabled_on_crtc)
> > > >  {
> > > >  	if (intel_dp_is_uhbr(crtc_state))
> > > > -		return;
> > > > +		return false;
> > > >  
> > > >  	if (crtc_state->fec_enable)
> > > > -		return;
> > > > +		return true;
> > > 
> > > Not really changed in this patch: Do you know in what kind of case
> > > "crtc_state->fec_enable == true" before intel_dp_needs_8b10b_fec is
> > > called?
> > 
> > Yes, that's another corner which should've been documented at least:
> > that's the case when there are two or more CRTCs on a 8b10b MST
> > link, only one/some of them enabling DSC (but not all). For
> > instance, CRTC#1 enables DSC, but CRTC#0 does not enable DSC. First
> > CRTC#0's state is computed (due to the regular order of CRTC#0/1
> > etc. state computation) and since DSC is not enabled on it, it will
> > compute intel_crtc_state::fec_enable=false. Then CRTC#1 will compute
> > fec_enable=true, due to it enabling DSC.
> > 
> > After all CRTCs computed their state, through
> > intel_atomic_check_config_and_link() -> intel_atomic_check_config(),
> > the following path will detect that the FEC enabled state is
> > different for the CRTCs on the same MST link (whereas the FEC
> > enabled state should be the same for all the CRTCs on the link,
> > since FEC is the property of the link encoding). After detecting
> > this, the state of all the CRTCs on the link will be recomputed with
> > FEC forced on now for all (forced, even if DSC is not enabled for a
> > CRTC):
> > 
> > intel_atomic_check_config_and_link() -> intel_link_bw_atomic_check() -> 
> > check_all_link_config() -> intel_dp_mst_atomic_check_link() ->
> > intel_dp_mst_check_fec_change().
> > 
> > The above will set the intel_link_bw_limits::force_fec_pipes mask for
> > both CRTC#0 and CRTC#1, then both CRTCs' state gets recomputed,
> > during which intel_crtc_state::fec_enable will be set upfront in
> > intel_modeset_pipe_config(). The above intel_dp_dsc_compute_config() ->
> > intel_dp_needs_8b10b_fec() will be called after all the above (during
> > the second round of state computation) and so with
> > intel_crtc_state::fec_enable already set. This set state must be
> > preserved for CRTC#0 as well, even though it doesn't enable DSC.
> 
> Thank you for the clarification. Patch 6 converts
> intel_dp_mst_check_fec_change -> intel_dp_mst_check_dsc_change. I.e.
> force_fec_pipes mask is not set and it doesn't exist. Instead there is
> force_dsc_pipes mask. Maybe this could be dropped in patch 6 as
> intel_modeset_pipe_config is setting compression_enabled_on_link
> instead and this is also checked in intel_dp_needs_8b10b_fec?

Yes, I missed this, thanks for noticing it. Yes, it can be removed after
patch 6. There is a subtle interaction between
(a) intel_dp_dsc_compute_config() -> intel_dp_needs_8b10b_fec() and
(b) intel_dp_mtp_tu_compute_config() -> intel_dp_needs_8b10b_fec(),
whereby (b) can see intel_crtc_state::fec_enable being set, because (a)
has set it. Then (b) has to reset it for UHBR, as patch 2 and 3
explains. Removing the if (fec_enable) return true; case above reduces
that subtlety actually, which is good.

However, the check above shouldn't cause an issue (after patch 2) and
intel_crtc_state::fec_enable will still be computed twice in the end.
That's still a bit subtle and so I'd remove the check in a separate
patch, as a follow-up, to keep things isolated. Would you be ok with
that?

> BR,
> 
> Jouni Högander

Re: [PATCH v2 3/7] drm/i915/dp: Export helper to determine if FEC on non-UHBR links is required

[Hogander, Jouni]

On Thu, 2025-10-16 at 23:00 +0300, Imre Deak wrote:
> On Thu, Oct 16, 2025 at 09:23:26PM +0300, Jouni Hogander wrote:
> > On Thu, 2025-10-16 at 20:18 +0300, Imre Deak wrote:
> > > On Thu, Oct 16, 2025 at 07:56:32PM +0300, Jouni Hogander wrote:
> > > > On Wed, 2025-10-15 at 19:19 +0300, Imre Deak wrote:
> > > > > Export the helper function to determine if FEC is required on
> > > > > a
> > > > > non- UHBR (8b10b) SST or MST link. A follow up change will
> > > > > take
> > > > > this into use for MST as well.
> > > > > 
> > > > > While at it determine the output type from the CRTC state,
> > > > > which
> > > > > allows dropping the intel_dp argument. Also make the function
> > > > > return the required FEC state, instead of setting this in the
> > > > > CRTC state, which allows only querying this requirement,
> > > > > without
> > > > > changing the state.
> > > > > 
> > > > > Also rename the function to intel_dp_needs_8b10b_fec(), to
> > > > > clarify that the function determines if FEC is required on an
> > > > > 8b10b link (on 128b132b links FEC is always enabled by the HW
> > > > > implicitly, so the function will return false for that case).
> > > > > 
> > > > > Signed-off-by: Imre Deak <imre.deak@intel.com>

Reviewed-by: Jouni Högander <jouni.hogander@intel.com>

> > > > > ---
> > > > >  drivers/gpu/drm/i915/display/intel_dp.c     | 21
> > > > > +++++++++++++--
> > > > > ----
> > > > > --
> > > > >  drivers/gpu/drm/i915/display/intel_dp.h     |  2 ++
> > > > >  drivers/gpu/drm/i915/display/intel_dp_mst.c |  2 +-
> > > > >  3 files changed, 16 insertions(+), 9 deletions(-)
> > > > > 
> > > > > diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
> > > > > b/drivers/gpu/drm/i915/display/intel_dp.c
> > > > > index b523c4e661412..3ffb015004c54 100644
> > > > > --- a/drivers/gpu/drm/i915/display/intel_dp.c
> > > > > +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> > > > > @@ -2365,24 +2365,29 @@ static int
> > > > > intel_edp_dsc_compute_pipe_bpp(struct intel_dp *intel_dp,
> > > > >  	return 0;
> > > > >  }
> > > > >  
> > > > > -static void intel_dp_fec_compute_config(struct intel_dp
> > > > > *intel_dp,
> > > > > -					struct
> > > > > intel_crtc_state *crtc_state)
> > > > > +/*
> > > > > + * Return whether FEC must be enabled for 8b10b SST or MST
> > > > > links. On 128b132b
> > > > > + * links FEC is always enabled implicitly by the HW, so this
> > > > > function returns
> > > > > + * false for that case.
> > > > > + */
> > > > > +bool intel_dp_needs_8b10b_fec(const struct intel_crtc_state
> > > > > *crtc_state,
> > > > > +			      bool dsc_enabled_on_crtc)
> > > > >  {
> > > > >  	if (intel_dp_is_uhbr(crtc_state))
> > > > > -		return;
> > > > > +		return false;
> > > > >  
> > > > >  	if (crtc_state->fec_enable)
> > > > > -		return;
> > > > > +		return true;
> > > > 
> > > > Not really changed in this patch: Do you know in what kind of
> > > > case
> > > > "crtc_state->fec_enable == true" before
> > > > intel_dp_needs_8b10b_fec is
> > > > called?
> > > 
> > > Yes, that's another corner which should've been documented at
> > > least:
> > > that's the case when there are two or more CRTCs on a 8b10b MST
> > > link, only one/some of them enabling DSC (but not all). For
> > > instance, CRTC#1 enables DSC, but CRTC#0 does not enable DSC.
> > > First
> > > CRTC#0's state is computed (due to the regular order of CRTC#0/1
> > > etc. state computation) and since DSC is not enabled on it, it
> > > will
> > > compute intel_crtc_state::fec_enable=false. Then CRTC#1 will
> > > compute
> > > fec_enable=true, due to it enabling DSC.
> > > 
> > > After all CRTCs computed their state, through
> > > intel_atomic_check_config_and_link() ->
> > > intel_atomic_check_config(),
> > > the following path will detect that the FEC enabled state is
> > > different for the CRTCs on the same MST link (whereas the FEC
> > > enabled state should be the same for all the CRTCs on the link,
> > > since FEC is the property of the link encoding). After detecting
> > > this, the state of all the CRTCs on the link will be recomputed
> > > with
> > > FEC forced on now for all (forced, even if DSC is not enabled for
> > > a
> > > CRTC):
> > > 
> > > intel_atomic_check_config_and_link() ->
> > > intel_link_bw_atomic_check() -> 
> > > check_all_link_config() -> intel_dp_mst_atomic_check_link() ->
> > > intel_dp_mst_check_fec_change().
> > > 
> > > The above will set the intel_link_bw_limits::force_fec_pipes mask
> > > for
> > > both CRTC#0 and CRTC#1, then both CRTCs' state gets recomputed,
> > > during which intel_crtc_state::fec_enable will be set upfront in
> > > intel_modeset_pipe_config(). The above
> > > intel_dp_dsc_compute_config() ->
> > > intel_dp_needs_8b10b_fec() will be called after all the above
> > > (during
> > > the second round of state computation) and so with
> > > intel_crtc_state::fec_enable already set. This set state must be
> > > preserved for CRTC#0 as well, even though it doesn't enable DSC.
> > 
> > Thank you for the clarification. Patch 6 converts
> > intel_dp_mst_check_fec_change -> intel_dp_mst_check_dsc_change.
> > I.e.
> > force_fec_pipes mask is not set and it doesn't exist. Instead there
> > is
> > force_dsc_pipes mask. Maybe this could be dropped in patch 6 as
> > intel_modeset_pipe_config is setting compression_enabled_on_link
> > instead and this is also checked in intel_dp_needs_8b10b_fec?
> 
> Yes, I missed this, thanks for noticing it. Yes, it can be removed
> after
> patch 6. There is a subtle interaction between
> (a) intel_dp_dsc_compute_config() -> intel_dp_needs_8b10b_fec() and
> (b) intel_dp_mtp_tu_compute_config() -> intel_dp_needs_8b10b_fec(),
> whereby (b) can see intel_crtc_state::fec_enable being set, because
> (a)
> has set it. Then (b) has to reset it for UHBR, as patch 2 and 3
> explains. Removing the if (fec_enable) return true; case above
> reduces
> that subtlety actually, which is good.
> 
> However, the check above shouldn't cause an issue (after patch 2) and
> intel_crtc_state::fec_enable will still be computed twice in the end.
> That's still a bit subtle and so I'd remove the check in a separate
> patch, as a follow-up, to keep things isolated. Would you be ok with
> that?

Yes, it shouldn't cause any issue. This is ok to me. Provided rb above.

BR,

Jouni Högander
> 
> > BR,
> > 
> > Jouni Högander