[PATCH 0/6] Optimize vrr.guardband

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* [PATCH 0/6] Optimize vrr.guardband
@ 2025-10-16  9:30 Ankit Nautiyal
  2025-10-16  9:30 ` [PATCH 1/6] [NOT FOR REVIEW] drm/i915/vrr: prep patches for guardband optimization squashed Ankit Nautiyal
                   ` (10 more replies)
  0 siblings, 11 replies; 14+ messages in thread
From: Ankit Nautiyal @ 2025-10-16  9:30 UTC (permalink / raw)
  To: intel-gfx, intel-xe; +Cc: ville.syrjala, Ankit Nautiyal

Instead of setting vrr.guardband to vblank, use optimal guardband that
works for most of the cases. This will help in avoiding need of change
in guardband and fix the LRR feature that needs seamless switching to
a lower refresh rate.

-Patch [1-2] are squashed from series [1] and [2] and are not meant for
 review.
-Patch [3-6] are patches to check the guardband for prefill+PSR+SDP
 latencies and to use a static optimized guardband.

[1] "Preparatory patches for guardband optimization"
https://patchwork.freedesktop.org/series/155661/#rev8

[2] "Introduce helpers for prefill latency calculations"
https://patchwork.freedesktop.org/series/155629/#rev3

Rev2:
- Drop patch to check guardband in crtc_check phase, instead check
  guardband for SDP in compute_config_late.
- Modify the helper to get the min sdp guardband if all SDPs are assumed
  to be enabled.
- Rename the helpers to get min guardband for sdp and psr.

Ankit Nautiyal (5):
  [NOT FOR REVIEW] drm/i915/vrr: prep patches for guardband optimization
    squashed
  drm/i915/psr: Add helper to get min psr guardband
  drm/i915/dp: Add helper to get min sdp guardband
  drm/i915/dp: Check if guardband can accommodate sdp latencies
  drm/i915/vrr: Use the min static optimized guardband

Ville Syrjälä (1):
  [NOT FOR REVIEW] drm/i915/prefill: Prefill latency calculations series
    squashed

 drivers/gpu/drm/i915/Makefile                |   1 +
 drivers/gpu/drm/i915/display/intel_cdclk.c   |  80 +++++-
 drivers/gpu/drm/i915/display/intel_cdclk.h   |   6 +
 drivers/gpu/drm/i915/display/intel_ddi.c     |   7 +
 drivers/gpu/drm/i915/display/intel_display.c |  26 +-
 drivers/gpu/drm/i915/display/intel_dp.c      |  69 +++++
 drivers/gpu/drm/i915/display/intel_dp.h      |   5 +
 drivers/gpu/drm/i915/display/intel_psr.c     | 256 +++++++++++++------
 drivers/gpu/drm/i915/display/intel_psr.h     |   3 +
 drivers/gpu/drm/i915/display/intel_vblank.c  |  10 +
 drivers/gpu/drm/i915/display/intel_vblank.h  |   2 +
 drivers/gpu/drm/i915/display/intel_vdsc.c    |   8 +
 drivers/gpu/drm/i915/display/intel_vdsc.h    |   1 +
 drivers/gpu/drm/i915/display/intel_vrr.c     |  83 +++++-
 drivers/gpu/drm/i915/display/intel_vrr.h     |   2 +-
 drivers/gpu/drm/i915/display/skl_prefill.c   | 157 ++++++++++++
 drivers/gpu/drm/i915/display/skl_prefill.h   |  46 ++++
 drivers/gpu/drm/i915/display/skl_scaler.c    | 141 ++++++++++
 drivers/gpu/drm/i915/display/skl_scaler.h    |  15 ++
 drivers/gpu/drm/i915/display/skl_watermark.c | 156 +++++------
 drivers/gpu/drm/i915/display/skl_watermark.h |   3 +
 drivers/gpu/drm/xe/Makefile                  |   1 +
 22 files changed, 894 insertions(+), 184 deletions(-)
 create mode 100644 drivers/gpu/drm/i915/display/skl_prefill.c
 create mode 100644 drivers/gpu/drm/i915/display/skl_prefill.h

-- 
2.45.2


^ permalink raw reply	[flat|nested] 14+ messages in thread

* [PATCH 1/6] [NOT FOR REVIEW] drm/i915/vrr: prep patches for guardband optimization squashed
  2025-10-16  9:30 [PATCH 0/6] Optimize vrr.guardband Ankit Nautiyal
@ 2025-10-16  9:30 ` Ankit Nautiyal
  2025-10-16  9:30 ` [PATCH 2/6] [NOT FOR REVIEW] drm/i915/prefill: Prefill latency calculations series squashed Ankit Nautiyal
                   ` (9 subsequent siblings)
  10 siblings, 0 replies; 14+ messages in thread
From: Ankit Nautiyal @ 2025-10-16  9:30 UTC (permalink / raw)
  To: intel-gfx, intel-xe; +Cc: ville.syrjala, Ankit Nautiyal

This is a squashed patch based on the preparatory series for guardband
optimization. It contains all the changes in the v8 of the series:
'Preparatory patches for guardband optimization' [1]

This handles few cases which will need changes when guardband will no
longer be matched to vblank length.
- Fix the vblank_start evaluation.
- Fix PSR wake latency checks wrt to guradband.

NOTE: This patch is not meant for review. Any review related to this
patch should be done on the original series. In order not to diverge
the discussion from the main series.

[1] https://patchwork.freedesktop.org/series/155661/#rev8

Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
---
 drivers/gpu/drm/i915/display/intel_ddi.c     |   7 +
 drivers/gpu/drm/i915/display/intel_display.c |  18 +-
 drivers/gpu/drm/i915/display/intel_dp.c      |  11 +
 drivers/gpu/drm/i915/display/intel_dp.h      |   3 +
 drivers/gpu/drm/i915/display/intel_psr.c     | 244 +++++++++++++------
 drivers/gpu/drm/i915/display/intel_psr.h     |   2 +
 drivers/gpu/drm/i915/display/intel_vblank.c  |  10 +
 drivers/gpu/drm/i915/display/intel_vblank.h  |   2 +
 drivers/gpu/drm/i915/display/intel_vrr.c     |  33 ++-
 drivers/gpu/drm/i915/display/intel_vrr.h     |   2 +-
 drivers/gpu/drm/i915/display/skl_watermark.c |   3 +-
 11 files changed, 246 insertions(+), 89 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
index c09aa759f4d4..870140340342 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -4559,6 +4559,13 @@ static int intel_ddi_compute_config_late(struct intel_encoder *encoder,
 	struct intel_display *display = to_intel_display(encoder);
 	struct drm_connector *connector = conn_state->connector;
 	u8 port_sync_transcoders = 0;
+	int ret = 0;
+
+	if (intel_crtc_has_dp_encoder(crtc_state))
+		ret = intel_dp_compute_config_late(encoder, crtc_state, conn_state);
+
+	if (ret)
+		return ret;
 
 	drm_dbg_kms(display->drm, "[ENCODER:%d:%s] [CRTC:%d:%s]\n",
 		    encoder->base.base.id, encoder->base.name,
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index d5b2612d4ec2..65a7da694ef6 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -2410,11 +2410,11 @@ static int intel_crtc_compute_config(struct intel_atomic_state *state,
 		intel_atomic_get_new_crtc_state(state, crtc);
 	int ret;
 
-	ret = intel_crtc_compute_set_context_latency(state, crtc);
+	ret = intel_dpll_crtc_compute_clock(state, crtc);
 	if (ret)
 		return ret;
 
-	ret = intel_dpll_crtc_compute_clock(state, crtc);
+	ret = intel_crtc_compute_set_context_latency(state, crtc);
 	if (ret)
 		return ret;
 
@@ -2431,6 +2431,8 @@ static int intel_crtc_compute_config(struct intel_atomic_state *state,
 	if (crtc_state->has_pch_encoder)
 		return ilk_fdi_compute_config(crtc, crtc_state);
 
+	intel_vrr_compute_guardband(crtc_state);
+
 	return 0;
 }
 
@@ -4722,8 +4724,6 @@ intel_modeset_pipe_config_late(struct intel_atomic_state *state,
 	struct drm_connector *connector;
 	int i;
 
-	intel_vrr_compute_config_late(crtc_state);
-
 	for_each_new_connector_in_state(&state->base, connector,
 					conn_state, i) {
 		struct intel_encoder *encoder =
@@ -4958,9 +4958,15 @@ static bool allow_vblank_delay_fastset(const struct intel_crtc_state *old_crtc_s
 	 * Allow fastboot to fix up vblank delay (handled via LRR
 	 * codepaths), a bit dodgy as the registers aren't
 	 * double buffered but seems to be working more or less...
+	 *
+	 * Also allow this when the VRR timing generator is always on,
+	 * and optimized guardband is used. In such cases,
+	 * vblank delay may vary even without inherited state, but it's
+	 * still safe as VRR guardband is still same.
 	 */
-	return HAS_LRR(display) && old_crtc_state->inherited &&
-		!intel_crtc_has_type(old_crtc_state, INTEL_OUTPUT_DSI);
+	return HAS_LRR(display) &&
+	       (old_crtc_state->inherited || intel_vrr_always_use_vrr_tg(display)) &&
+	       !intel_crtc_has_type(old_crtc_state, INTEL_OUTPUT_DSI);
 }
 
 bool
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index a723e846321f..7059d55687cf 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -6979,3 +6979,14 @@ void intel_dp_mst_resume(struct intel_display *display)
 		}
 	}
 }
+
+int intel_dp_compute_config_late(struct intel_encoder *encoder,
+				 struct intel_crtc_state *crtc_state,
+				 struct drm_connector_state *conn_state)
+{
+	struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
+
+	intel_psr_compute_config_late(intel_dp, crtc_state);
+
+	return 0;
+}
diff --git a/drivers/gpu/drm/i915/display/intel_dp.h b/drivers/gpu/drm/i915/display/intel_dp.h
index b379443e0211..281ced3a3b39 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.h
+++ b/drivers/gpu/drm/i915/display/intel_dp.h
@@ -218,5 +218,8 @@ int intel_dp_compute_min_hblank(struct intel_crtc_state *crtc_state,
 int intel_dp_dsc_bpp_step_x16(const struct intel_connector *connector);
 void intel_dp_dpcd_set_probe(struct intel_dp *intel_dp, bool force_on_external);
 bool intel_dp_in_hdr_mode(const struct drm_connector_state *conn_state);
+int intel_dp_compute_config_late(struct intel_encoder *encoder,
+				 struct intel_crtc_state *crtc_state,
+				 struct drm_connector_state *conn_state);
 
 #endif /* __INTEL_DP_H__ */
diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c
index 2131473cead6..703e5f6af04c 100644
--- a/drivers/gpu/drm/i915/display/intel_psr.c
+++ b/drivers/gpu/drm/i915/display/intel_psr.c
@@ -1361,14 +1361,78 @@ static int intel_psr_entry_setup_frames(struct intel_dp *intel_dp,
 	return entry_setup_frames;
 }
 
+static
+int _intel_psr_min_set_context_latency(const struct intel_crtc_state *crtc_state,
+				       bool needs_panel_replay,
+				       bool needs_sel_update)
+{
+	struct intel_display *display = to_intel_display(crtc_state);
+
+	if (!crtc_state->has_psr)
+		return 0;
+
+	/* Wa_14015401596 */
+	if (intel_vrr_possible(crtc_state) && IS_DISPLAY_VER(display, 13, 14))
+		return 1;
+
+	/* Rest is for SRD_STATUS needed on LunarLake and onwards */
+	if (DISPLAY_VER(display) < 20)
+		return 0;
+
+	/*
+	 * Comment on SRD_STATUS register in Bspec for LunarLake and onwards:
+	 *
+	 * To deterministically capture the transition of the state machine
+	 * going from SRDOFFACK to IDLE, the delayed V. Blank should be at least
+	 * one line after the non-delayed V. Blank.
+	 *
+	 * Legacy TG: TRANS_SET_CONTEXT_LATENCY > 0
+	 * VRR TG: TRANS_VRR_CTL[ VRR Guardband ] < (TRANS_VRR_VMAX[ VRR Vmax ]
+	 * - TRANS_VTOTAL[ Vertical Active ])
+	 *
+	 * SRD_STATUS is used only by PSR1 on PantherLake.
+	 * SRD_STATUS is used by PSR1 and Panel Replay DP on LunarLake.
+	 */
+
+	if (DISPLAY_VER(display) >= 30 && (needs_panel_replay ||
+					   needs_sel_update))
+		return 0;
+	else if (DISPLAY_VER(display) < 30 && (needs_sel_update ||
+					       intel_crtc_has_type(crtc_state,
+								   INTEL_OUTPUT_EDP)))
+		return 0;
+	else
+		return 1;
+}
+
+static bool _wake_lines_fit_into_vblank(const struct intel_crtc_state *crtc_state,
+					int vblank,
+					int wake_lines)
+{
+	if (crtc_state->req_psr2_sdp_prior_scanline)
+		vblank -= 1;
+
+	/* Vblank >= PSR2_CTL Block Count Number maximum line count */
+	if (vblank < wake_lines)
+		return false;
+
+	return true;
+}
+
 static bool wake_lines_fit_into_vblank(struct intel_dp *intel_dp,
 				       const struct intel_crtc_state *crtc_state,
-				       bool aux_less)
+				       bool aux_less,
+				       bool needs_panel_replay,
+				       bool needs_sel_update)
 {
 	struct intel_display *display = to_intel_display(intel_dp);
 	int vblank = crtc_state->hw.adjusted_mode.crtc_vblank_end -
 		crtc_state->hw.adjusted_mode.crtc_vblank_start;
 	int wake_lines;
+	int scl = _intel_psr_min_set_context_latency(crtc_state,
+						     needs_panel_replay,
+						     needs_sel_update);
+	vblank -= scl;
 
 	if (aux_less)
 		wake_lines = crtc_state->alpm_state.aux_less_wake_lines;
@@ -1378,19 +1442,23 @@ static bool wake_lines_fit_into_vblank(struct intel_dp *intel_dp,
 					       crtc_state->alpm_state.fast_wake_lines) :
 			crtc_state->alpm_state.io_wake_lines;
 
-	if (crtc_state->req_psr2_sdp_prior_scanline)
-		vblank -= 1;
-
-	/* Vblank >= PSR2_CTL Block Count Number maximum line count */
-	if (vblank < wake_lines)
-		return false;
-
-	return true;
+	/*
+	 * Guardband has not been computed yet, so we conservatively check if the
+	 * full vblank duration is sufficient to accommodate wake line requirements
+	 * for PSR features like Panel Replay and Selective Update.
+	 *
+	 * Once the actual guardband is available, a more accurate validation is
+	 * performed in intel_psr_compute_config_late(), and PSR features are
+	 * disabled if wake lines exceed the available guardband.
+	 */
+	return _wake_lines_fit_into_vblank(crtc_state, vblank, wake_lines);
 }
 
 static bool alpm_config_valid(struct intel_dp *intel_dp,
 			      struct intel_crtc_state *crtc_state,
-			      bool aux_less)
+			      bool aux_less,
+			      bool needs_panel_replay,
+			      bool needs_sel_update)
 {
 	struct intel_display *display = to_intel_display(intel_dp);
 
@@ -1400,7 +1468,8 @@ static bool alpm_config_valid(struct intel_dp *intel_dp,
 		return false;
 	}
 
-	if (!wake_lines_fit_into_vblank(intel_dp, crtc_state, aux_less)) {
+	if (!wake_lines_fit_into_vblank(intel_dp, crtc_state, aux_less,
+					needs_panel_replay, needs_sel_update)) {
 		drm_dbg_kms(display->drm,
 			    "PSR2/Panel Replay not enabled, too short vblank time\n");
 		return false;
@@ -1492,7 +1561,7 @@ static bool intel_psr2_config_valid(struct intel_dp *intel_dp,
 		return false;
 	}
 
-	if (!alpm_config_valid(intel_dp, crtc_state, false))
+	if (!alpm_config_valid(intel_dp, crtc_state, false, false, true))
 		return false;
 
 	if (!crtc_state->enable_psr2_sel_fetch &&
@@ -1643,7 +1712,7 @@ _panel_replay_compute_config(struct intel_dp *intel_dp,
 		return false;
 	}
 
-	if (!alpm_config_valid(intel_dp, crtc_state, true))
+	if (!alpm_config_valid(intel_dp, crtc_state, true, true, false))
 		return false;
 
 	return true;
@@ -1658,15 +1727,40 @@ static bool intel_psr_needs_wa_18037818876(struct intel_dp *intel_dp,
 		!crtc_state->has_sel_update);
 }
 
+static
+void intel_psr_set_non_psr_pipes(struct intel_dp *intel_dp,
+				 struct intel_crtc_state *crtc_state)
+{
+	struct intel_display *display = to_intel_display(intel_dp);
+	struct intel_atomic_state *state = to_intel_atomic_state(crtc_state->uapi.state);
+	struct intel_crtc *crtc;
+	u8 active_pipes = 0;
+
+	/* Wa_16025596647 */
+	if (DISPLAY_VER(display) != 20 &&
+	    !IS_DISPLAY_VERx100_STEP(display, 3000, STEP_A0, STEP_B0))
+		return;
+
+	/* Not needed by Panel Replay  */
+	if (crtc_state->has_panel_replay)
+		return;
+
+	/* We ignore possible secondary PSR/Panel Replay capable eDP */
+	for_each_intel_crtc(display->drm, crtc)
+		active_pipes |= crtc->active ? BIT(crtc->pipe) : 0;
+
+	active_pipes = intel_calc_active_pipes(state, active_pipes);
+
+	crtc_state->active_non_psr_pipes = active_pipes &
+		~BIT(to_intel_crtc(crtc_state->uapi.crtc)->pipe);
+}
+
 void intel_psr_compute_config(struct intel_dp *intel_dp,
 			      struct intel_crtc_state *crtc_state,
 			      struct drm_connector_state *conn_state)
 {
 	struct intel_display *display = to_intel_display(intel_dp);
 	const struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode;
-	struct intel_atomic_state *state = to_intel_atomic_state(crtc_state->uapi.state);
-	struct intel_crtc *crtc;
-	u8 active_pipes = 0;
 
 	if (!psr_global_enabled(intel_dp)) {
 		drm_dbg_kms(display->drm, "PSR disabled by flag\n");
@@ -1707,31 +1801,6 @@ void intel_psr_compute_config(struct intel_dp *intel_dp,
 		return;
 
 	crtc_state->has_sel_update = intel_sel_update_config_valid(intel_dp, crtc_state);
-
-	/* Wa_18037818876 */
-	if (intel_psr_needs_wa_18037818876(intel_dp, crtc_state)) {
-		crtc_state->has_psr = false;
-		drm_dbg_kms(display->drm,
-			    "PSR disabled to workaround PSR FSM hang issue\n");
-	}
-
-	/* Rest is for Wa_16025596647 */
-	if (DISPLAY_VER(display) != 20 &&
-	    !IS_DISPLAY_VERx100_STEP(display, 3000, STEP_A0, STEP_B0))
-		return;
-
-	/* Not needed by Panel Replay  */
-	if (crtc_state->has_panel_replay)
-		return;
-
-	/* We ignore possible secondary PSR/Panel Replay capable eDP */
-	for_each_intel_crtc(display->drm, crtc)
-		active_pipes |= crtc->active ? BIT(crtc->pipe) : 0;
-
-	active_pipes = intel_calc_active_pipes(state, active_pipes);
-
-	crtc_state->active_non_psr_pipes = active_pipes &
-		~BIT(to_intel_crtc(crtc_state->uapi.crtc)->pipe);
 }
 
 void intel_psr_get_config(struct intel_encoder *encoder,
@@ -2371,43 +2440,10 @@ void intel_psr_trigger_frame_change_event(struct intel_dsb *dsb,
  */
 int intel_psr_min_set_context_latency(const struct intel_crtc_state *crtc_state)
 {
-	struct intel_display *display = to_intel_display(crtc_state);
-
-	if (!crtc_state->has_psr)
-		return 0;
-
-	/* Wa_14015401596 */
-	if (intel_vrr_possible(crtc_state) && IS_DISPLAY_VER(display, 13, 14))
-		return 1;
-
-	/* Rest is for SRD_STATUS needed on LunarLake and onwards */
-	if (DISPLAY_VER(display) < 20)
-		return 0;
-
-	/*
-	 * Comment on SRD_STATUS register in Bspec for LunarLake and onwards:
-	 *
-	 * To deterministically capture the transition of the state machine
-	 * going from SRDOFFACK to IDLE, the delayed V. Blank should be at least
-	 * one line after the non-delayed V. Blank.
-	 *
-	 * Legacy TG: TRANS_SET_CONTEXT_LATENCY > 0
-	 * VRR TG: TRANS_VRR_CTL[ VRR Guardband ] < (TRANS_VRR_VMAX[ VRR Vmax ]
-	 * - TRANS_VTOTAL[ Vertical Active ])
-	 *
-	 * SRD_STATUS is used only by PSR1 on PantherLake.
-	 * SRD_STATUS is used by PSR1 and Panel Replay DP on LunarLake.
-	 */
 
-	if (DISPLAY_VER(display) >= 30 && (crtc_state->has_panel_replay ||
-					   crtc_state->has_sel_update))
-		return 0;
-	else if (DISPLAY_VER(display) < 30 && (crtc_state->has_sel_update ||
-					       intel_crtc_has_type(crtc_state,
-								   INTEL_OUTPUT_EDP)))
-		return 0;
-	else
-		return 1;
+	return _intel_psr_min_set_context_latency(crtc_state,
+						  crtc_state->has_panel_replay,
+						  crtc_state->has_sel_update);
 }
 
 static u32 man_trk_ctl_enable_bit_get(struct intel_display *display)
@@ -4326,3 +4362,57 @@ bool intel_psr_needs_alpm_aux_less(struct intel_dp *intel_dp,
 {
 	return intel_dp_is_edp(intel_dp) && crtc_state->has_panel_replay;
 }
+
+void intel_psr_compute_config_late(struct intel_dp *intel_dp,
+				   struct intel_crtc_state *crtc_state)
+{
+	struct intel_display *display = to_intel_display(intel_dp);
+	int vblank = intel_crtc_vblank_length(crtc_state);
+	int wake_lines;
+
+	if (intel_psr_needs_alpm_aux_less(intel_dp, crtc_state))
+		wake_lines = crtc_state->alpm_state.aux_less_wake_lines;
+	else if (intel_psr_needs_alpm(intel_dp, crtc_state))
+		wake_lines = DISPLAY_VER(display) < 20 ?
+			     psr2_block_count_lines(crtc_state->alpm_state.io_wake_lines,
+						    crtc_state->alpm_state.fast_wake_lines) :
+			     crtc_state->alpm_state.io_wake_lines;
+	else
+		wake_lines = 0;
+
+	/*
+	 * Disable the PSR features if wake lines exceed the available vblank.
+	 * Though SCL is computed based on these PSR features, it is not reset
+	 * even if the PSR features are disabled to avoid changing vblank start
+	 * at this stage.
+	 */
+	if (wake_lines && !_wake_lines_fit_into_vblank(crtc_state, vblank, wake_lines)) {
+		drm_dbg_kms(display->drm,
+			    "Adjusting PSR/PR mode: vblank too short for wake lines = %d\n",
+			    wake_lines);
+
+		if (crtc_state->has_panel_replay) {
+			crtc_state->has_panel_replay = false;
+			/*
+			 * #TODO : Add fall back to PSR/PSR2
+			 * Since panel replay cannot be supported, we can fall back to PSR/PSR2.
+			 * This will require calling compute_config for psr and psr2 with check for
+			 * actual guardband instead of vblank_length.
+			 */
+			crtc_state->has_psr = false;
+		}
+
+		crtc_state->has_sel_update = false;
+		crtc_state->enable_psr2_su_region_et = false;
+		crtc_state->enable_psr2_sel_fetch = false;
+	}
+
+	/* Wa_18037818876 */
+	if (intel_psr_needs_wa_18037818876(intel_dp, crtc_state)) {
+		crtc_state->has_psr = false;
+		drm_dbg_kms(display->drm,
+			    "PSR disabled to workaround PSR FSM hang issue\n");
+	}
+
+	intel_psr_set_non_psr_pipes(intel_dp, crtc_state);
+}
diff --git a/drivers/gpu/drm/i915/display/intel_psr.h b/drivers/gpu/drm/i915/display/intel_psr.h
index 9147996d6c9e..b17ce312dc37 100644
--- a/drivers/gpu/drm/i915/display/intel_psr.h
+++ b/drivers/gpu/drm/i915/display/intel_psr.h
@@ -83,5 +83,7 @@ void intel_psr_debugfs_register(struct intel_display *display);
 bool intel_psr_needs_alpm(struct intel_dp *intel_dp, const struct intel_crtc_state *crtc_state);
 bool intel_psr_needs_alpm_aux_less(struct intel_dp *intel_dp,
 				   const struct intel_crtc_state *crtc_state);
+void intel_psr_compute_config_late(struct intel_dp *intel_dp,
+				   struct intel_crtc_state *crtc_state);
 
 #endif /* __INTEL_PSR_H__ */
diff --git a/drivers/gpu/drm/i915/display/intel_vblank.c b/drivers/gpu/drm/i915/display/intel_vblank.c
index 0b7fcc05e64c..2fc0c1c0bb87 100644
--- a/drivers/gpu/drm/i915/display/intel_vblank.c
+++ b/drivers/gpu/drm/i915/display/intel_vblank.c
@@ -767,3 +767,13 @@ int intel_vblank_evade(struct intel_vblank_evade_ctx *evade)
 
 	return scanline;
 }
+
+int intel_crtc_vblank_length(const struct intel_crtc_state *crtc_state)
+{
+	const struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode;
+
+	if (crtc_state->vrr.enable)
+		return crtc_state->vrr.guardband;
+	else
+		return adjusted_mode->crtc_vtotal - adjusted_mode->crtc_vblank_start;
+}
diff --git a/drivers/gpu/drm/i915/display/intel_vblank.h b/drivers/gpu/drm/i915/display/intel_vblank.h
index 21fbb08d61d5..98d04cacd65f 100644
--- a/drivers/gpu/drm/i915/display/intel_vblank.h
+++ b/drivers/gpu/drm/i915/display/intel_vblank.h
@@ -48,4 +48,6 @@ const struct intel_crtc_state *
 intel_pre_commit_crtc_state(struct intel_atomic_state *state,
 			    struct intel_crtc *crtc);
 
+int intel_crtc_vblank_length(const struct intel_crtc_state *crtc_state);
+
 #endif /* __INTEL_VBLANK_H__ */
diff --git a/drivers/gpu/drm/i915/display/intel_vrr.c b/drivers/gpu/drm/i915/display/intel_vrr.c
index 190c51be5cbc..597008a6c744 100644
--- a/drivers/gpu/drm/i915/display/intel_vrr.c
+++ b/drivers/gpu/drm/i915/display/intel_vrr.c
@@ -394,10 +394,10 @@ intel_vrr_compute_config(struct intel_crtc_state *crtc_state,
 	if (HAS_AS_SDP(display)) {
 		crtc_state->vrr.vsync_start =
 			(crtc_state->hw.adjusted_mode.crtc_vtotal -
-			 crtc_state->hw.adjusted_mode.vsync_start);
+			 crtc_state->hw.adjusted_mode.crtc_vsync_start);
 		crtc_state->vrr.vsync_end =
 			(crtc_state->hw.adjusted_mode.crtc_vtotal -
-			 crtc_state->hw.adjusted_mode.vsync_end);
+			 crtc_state->hw.adjusted_mode.crtc_vsync_end);
 	}
 }
 
@@ -433,10 +433,11 @@ intel_vrr_max_guardband(struct intel_crtc_state *crtc_state)
 		   intel_vrr_max_vblank_guardband(crtc_state));
 }
 
-void intel_vrr_compute_config_late(struct intel_crtc_state *crtc_state)
+void intel_vrr_compute_guardband(struct intel_crtc_state *crtc_state)
 {
 	struct intel_display *display = to_intel_display(crtc_state);
-	const struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode;
+	struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode;
+	struct drm_display_mode *pipe_mode = &crtc_state->hw.pipe_mode;
 
 	if (!intel_vrr_possible(crtc_state))
 		return;
@@ -444,6 +445,17 @@ void intel_vrr_compute_config_late(struct intel_crtc_state *crtc_state)
 	crtc_state->vrr.guardband = min(crtc_state->vrr.vmin - adjusted_mode->crtc_vdisplay,
 					intel_vrr_max_guardband(crtc_state));
 
+	if (intel_vrr_always_use_vrr_tg(display)) {
+		adjusted_mode->crtc_vblank_start  =
+			adjusted_mode->crtc_vtotal - crtc_state->vrr.guardband;
+		/*
+		 * pipe_mode has already been derived from the
+		 * original adjusted_mode, keep the two in sync.
+		 */
+		pipe_mode->crtc_vblank_start =
+			adjusted_mode->crtc_vblank_start;
+	}
+
 	if (DISPLAY_VER(display) < 13)
 		crtc_state->vrr.pipeline_full =
 			intel_vrr_guardband_to_pipeline_full(crtc_state,
@@ -821,6 +833,19 @@ void intel_vrr_get_config(struct intel_crtc_state *crtc_state)
 	 */
 	if (crtc_state->vrr.enable)
 		crtc_state->mode_flags |= I915_MODE_FLAG_VRR;
+
+	/*
+	 * For platforms that always use the VRR timing generator, we overwrite
+	 * crtc_vblank_start with vtotal - guardband to reflect the delayed
+	 * vblank start. This works for both default and optimized guardband values.
+	 * On other platforms, we keep the original value from
+	 * intel_get_transcoder_timings() and apply adjustments only in VRR-specific
+	 * paths as needed.
+	 */
+	if (intel_vrr_always_use_vrr_tg(display))
+		crtc_state->hw.adjusted_mode.crtc_vblank_start =
+			crtc_state->hw.adjusted_mode.crtc_vtotal -
+			crtc_state->vrr.guardband;
 }
 
 int intel_vrr_safe_window_start(const struct intel_crtc_state *crtc_state)
diff --git a/drivers/gpu/drm/i915/display/intel_vrr.h b/drivers/gpu/drm/i915/display/intel_vrr.h
index 7317f8730089..bc9044621635 100644
--- a/drivers/gpu/drm/i915/display/intel_vrr.h
+++ b/drivers/gpu/drm/i915/display/intel_vrr.h
@@ -21,7 +21,7 @@ bool intel_vrr_possible(const struct intel_crtc_state *crtc_state);
 void intel_vrr_check_modeset(struct intel_atomic_state *state);
 void intel_vrr_compute_config(struct intel_crtc_state *crtc_state,
 			      struct drm_connector_state *conn_state);
-void intel_vrr_compute_config_late(struct intel_crtc_state *crtc_state);
+void intel_vrr_compute_guardband(struct intel_crtc_state *crtc_state);
 void intel_vrr_set_transcoder_timings(const struct intel_crtc_state *crtc_state);
 void intel_vrr_enable(const struct intel_crtc_state *crtc_state);
 void intel_vrr_send_push(struct intel_dsb *dsb,
diff --git a/drivers/gpu/drm/i915/display/skl_watermark.c b/drivers/gpu/drm/i915/display/skl_watermark.c
index 9df9ee137bf9..06e5e6c77d2e 100644
--- a/drivers/gpu/drm/i915/display/skl_watermark.c
+++ b/drivers/gpu/drm/i915/display/skl_watermark.c
@@ -28,6 +28,7 @@
 #include "intel_flipq.h"
 #include "intel_pcode.h"
 #include "intel_plane.h"
+#include "intel_vblank.h"
 #include "intel_wm.h"
 #include "skl_universal_plane_regs.h"
 #include "skl_watermark.h"
@@ -2241,7 +2242,7 @@ skl_is_vblank_too_short(const struct intel_crtc_state *crtc_state,
 		scaler_prefill_latency(crtc_state) +
 		dsc_prefill_latency(crtc_state) +
 		wm0_lines >
-		adjusted_mode->crtc_vtotal - adjusted_mode->crtc_vblank_start;
+		intel_crtc_vblank_length(crtc_state);
 }
 
 static int skl_max_wm0_lines(const struct intel_crtc_state *crtc_state)
-- 
2.45.2


^ permalink raw reply related	[flat|nested] 14+ messages in thread

* [PATCH 2/6] [NOT FOR REVIEW] drm/i915/prefill: Prefill latency calculations series squashed
  2025-10-16  9:30 [PATCH 0/6] Optimize vrr.guardband Ankit Nautiyal
  2025-10-16  9:30 ` [PATCH 1/6] [NOT FOR REVIEW] drm/i915/vrr: prep patches for guardband optimization squashed Ankit Nautiyal
@ 2025-10-16  9:30 ` Ankit Nautiyal
  2025-10-16  9:30 ` [PATCH 3/6] drm/i915/psr: Add helper to get min psr guardband Ankit Nautiyal
                   ` (8 subsequent siblings)
  10 siblings, 0 replies; 14+ messages in thread
From: Ankit Nautiyal @ 2025-10-16  9:30 UTC (permalink / raw)
  To: intel-gfx, intel-xe; +Cc: ville.syrjala, Ankit Nautiyal

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

This is a squashed patch based on the series from Ville Syrjälä
to introduce helpers for prefill latency calculations
'drm/i915/prefill: Introduce helpers for prefill latency calculations' [1]

Introduce skl_prefill and various accompanying helpers to do
pipe prefill latency related stuff (vblank/guardband length
checks, and in the future reduced guardband length).

NOTE: This patch is not meant for review. Any review related to this
patch should be done on the original series. In order not to diverge
the discussion from the main series.

[1] http://patchwork.freedesktop.org/series/155629/#rev3

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
---
 drivers/gpu/drm/i915/Makefile                |   1 +
 drivers/gpu/drm/i915/display/intel_cdclk.c   |  80 +++++++++-
 drivers/gpu/drm/i915/display/intel_cdclk.h   |   6 +
 drivers/gpu/drm/i915/display/intel_display.c |   8 +
 drivers/gpu/drm/i915/display/intel_vdsc.c    |   8 +
 drivers/gpu/drm/i915/display/intel_vdsc.h    |   1 +
 drivers/gpu/drm/i915/display/skl_prefill.c   | 157 +++++++++++++++++++
 drivers/gpu/drm/i915/display/skl_prefill.h   |  46 ++++++
 drivers/gpu/drm/i915/display/skl_scaler.c    | 141 +++++++++++++++++
 drivers/gpu/drm/i915/display/skl_scaler.h    |  15 ++
 drivers/gpu/drm/i915/display/skl_watermark.c | 155 ++++++++----------
 drivers/gpu/drm/i915/display/skl_watermark.h |   3 +
 drivers/gpu/drm/xe/Makefile                  |   1 +
 13 files changed, 528 insertions(+), 94 deletions(-)
 create mode 100644 drivers/gpu/drm/i915/display/skl_prefill.c
 create mode 100644 drivers/gpu/drm/i915/display/skl_prefill.h

diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
index 6d7800e25e55..aa2f0fd95117 100644
--- a/drivers/gpu/drm/i915/Makefile
+++ b/drivers/gpu/drm/i915/Makefile
@@ -302,6 +302,7 @@ i915-y += \
 	display/intel_vblank.o \
 	display/intel_vga.o \
 	display/intel_wm.o \
+	display/skl_prefill.o \
 	display/skl_scaler.o \
 	display/skl_universal_plane.o \
 	display/skl_watermark.o \
diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c b/drivers/gpu/drm/i915/display/intel_cdclk.c
index f2e092f89ddd..bd45b719d4f8 100644
--- a/drivers/gpu/drm/i915/display/intel_cdclk.c
+++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
@@ -2806,16 +2806,20 @@ static int intel_cdclk_guardband(struct intel_display *display)
 		return 90;
 }
 
-static int intel_pixel_rate_to_cdclk(const struct intel_crtc_state *crtc_state)
+static int _intel_pixel_rate_to_cdclk(const struct intel_crtc_state *crtc_state, int pixel_rate)
 {
 	struct intel_display *display = to_intel_display(crtc_state);
 	int ppc = intel_cdclk_ppc(display, crtc_state->double_wide);
 	int guardband = intel_cdclk_guardband(display);
-	int pixel_rate = crtc_state->pixel_rate;
 
 	return DIV_ROUND_UP(pixel_rate * 100, guardband * ppc);
 }
 
+static int intel_pixel_rate_to_cdclk(const struct intel_crtc_state *crtc_state)
+{
+	return _intel_pixel_rate_to_cdclk(crtc_state, crtc_state->pixel_rate);
+}
+
 static int intel_planes_min_cdclk(const struct intel_crtc_state *crtc_state)
 {
 	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
@@ -4056,3 +4060,75 @@ void intel_cdclk_read_hw(struct intel_display *display)
 	cdclk_state->actual = display->cdclk.hw;
 	cdclk_state->logical = display->cdclk.hw;
 }
+
+static int calc_cdclk(const struct intel_crtc_state *crtc_state, int min_cdclk)
+{
+	struct intel_display *display = to_intel_display(crtc_state);
+
+	if (DISPLAY_VER(display) >= 10 || display->platform.broxton) {
+		return bxt_calc_cdclk(display, min_cdclk);
+	} else if (DISPLAY_VER(display) == 9) {
+		int vco;
+
+		vco = display->cdclk.skl_preferred_vco_freq;
+		if (vco == 0)
+			vco = 8100000;
+
+		return skl_calc_cdclk(min_cdclk, vco);
+	} else if (display->platform.broadwell) {
+		return bdw_calc_cdclk(min_cdclk);
+	} else if (display->platform.cherryview || display->platform.valleyview) {
+		return vlv_calc_cdclk(display, min_cdclk);
+	} else {
+		return display->cdclk.max_cdclk_freq;
+	}
+}
+
+static unsigned int _intel_cdclk_prefill_adj(const struct intel_crtc_state *crtc_state,
+					     int clock, int min_cdclk)
+{
+	struct intel_display *display = to_intel_display(crtc_state);
+	int ppc = intel_cdclk_ppc(display, crtc_state->double_wide);
+	int cdclk = calc_cdclk(crtc_state, min_cdclk);
+
+	return min(0x10000, DIV_ROUND_UP_ULL((u64)clock << 16, ppc * cdclk));
+}
+
+unsigned int intel_cdclk_prefill_adjustment(const struct intel_crtc_state *crtc_state)
+{
+	/* FIXME use the actual min_cdclk for the pipe here */
+	return intel_cdclk_prefill_adjustment_worst(crtc_state);
+}
+
+unsigned int intel_cdclk_prefill_adjustment_worst(const struct intel_crtc_state *crtc_state)
+{
+	int clock = crtc_state->hw.pipe_mode.crtc_clock;
+	int min_cdclk;
+
+	/*
+	 * FIXME could perhaps consider a few more of the factors
+	 * that go the per-crtc min_cdclk. Namely anything that
+	 * only changes during full modesets.
+	 *
+	 * FIXME this assumes 1:1 scaling, but the other _worst() stuff
+	 * assumes max downscaling, so the final result will be
+	 * unrealistically bad. Figure out where the actual maximum value
+	 * lies and use that to compute a more realistic worst case
+	 * estimate...
+	 */
+	min_cdclk = _intel_pixel_rate_to_cdclk(crtc_state, clock);
+
+	return _intel_cdclk_prefill_adj(crtc_state, clock, min_cdclk);
+}
+
+int intel_cdclk_min_cdclk_for_prefill(const struct intel_crtc_state *crtc_state,
+				      unsigned int prefill_lines_unadjusted,
+				      unsigned int prefill_lines_available)
+{
+	struct intel_display *display = to_intel_display(crtc_state);
+	const struct drm_display_mode *pipe_mode = &crtc_state->hw.pipe_mode;
+	int ppc = intel_cdclk_ppc(display, crtc_state->double_wide);
+
+	return DIV_ROUND_UP_ULL(mul_u32_u32(pipe_mode->crtc_clock, prefill_lines_unadjusted),
+				ppc * prefill_lines_available);
+}
diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.h b/drivers/gpu/drm/i915/display/intel_cdclk.h
index 72963f6f399a..1c1140b53b17 100644
--- a/drivers/gpu/drm/i915/display/intel_cdclk.h
+++ b/drivers/gpu/drm/i915/display/intel_cdclk.h
@@ -70,4 +70,10 @@ bool intel_cdclk_pmdemand_needs_update(struct intel_atomic_state *state);
 void intel_cdclk_force_min_cdclk(struct intel_cdclk_state *cdclk_state, int force_min_cdclk);
 void intel_cdclk_read_hw(struct intel_display *display);
 
+unsigned int intel_cdclk_prefill_adjustment(const struct intel_crtc_state *crtc_state);
+unsigned int intel_cdclk_prefill_adjustment_worst(const struct intel_crtc_state *crtc_state);
+int intel_cdclk_min_cdclk_for_prefill(const struct intel_crtc_state *crtc_state,
+				      unsigned int prefill_lines_unadjusted,
+				      unsigned int prefill_lines_available);
+
 #endif /* __INTEL_CDCLK_H__ */
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 65a7da694ef6..4367ecfab2b3 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -7978,6 +7978,14 @@ enum drm_mode_status intel_mode_valid(struct drm_device *dev,
 	    mode->vtotal > vtotal_max)
 		return MODE_V_ILLEGAL;
 
+	/*
+	 * WM_LINETIME only goes up to (almost) 64 usec, and also
+	 * knowing that the linetime is always bounded will ease the
+	 * mind during various calculations.
+	 */
+	if (DIV_ROUND_UP(mode->htotal * 1000, mode->clock) > 64)
+		return MODE_H_ILLEGAL;
+
 	return MODE_OK;
 }
 
diff --git a/drivers/gpu/drm/i915/display/intel_vdsc.c b/drivers/gpu/drm/i915/display/intel_vdsc.c
index 8e799e225af1..bca747e24a7f 100644
--- a/drivers/gpu/drm/i915/display/intel_vdsc.c
+++ b/drivers/gpu/drm/i915/display/intel_vdsc.c
@@ -1077,3 +1077,11 @@ int intel_vdsc_min_cdclk(const struct intel_crtc_state *crtc_state)
 
 	return min_cdclk;
 }
+
+unsigned int intel_vdsc_prefill_lines(const struct intel_crtc_state *crtc_state)
+{
+	if (!crtc_state->dsc.compression_enable)
+		return 0;
+
+	return 0x18000; /* 1.5 */
+}
diff --git a/drivers/gpu/drm/i915/display/intel_vdsc.h b/drivers/gpu/drm/i915/display/intel_vdsc.h
index 9e2812f99dd7..2139391ff881 100644
--- a/drivers/gpu/drm/i915/display/intel_vdsc.h
+++ b/drivers/gpu/drm/i915/display/intel_vdsc.h
@@ -32,5 +32,6 @@ void intel_dsc_dp_pps_write(struct intel_encoder *encoder,
 void intel_vdsc_state_dump(struct drm_printer *p, int indent,
 			   const struct intel_crtc_state *crtc_state);
 int intel_vdsc_min_cdclk(const struct intel_crtc_state *crtc_state);
+unsigned int intel_vdsc_prefill_lines(const struct intel_crtc_state *crtc_state);
 
 #endif /* __INTEL_VDSC_H__ */
diff --git a/drivers/gpu/drm/i915/display/skl_prefill.c b/drivers/gpu/drm/i915/display/skl_prefill.c
new file mode 100644
index 000000000000..4707c2e7127a
--- /dev/null
+++ b/drivers/gpu/drm/i915/display/skl_prefill.c
@@ -0,0 +1,157 @@
+// SPDX-License-Identifier: MIT
+/*
+ * Copyright © 2025 Intel Corporation
+ */
+
+#include <linux/debugfs.h>
+
+#include <drm/drm_print.h>
+
+#include "intel_cdclk.h"
+#include "intel_display_core.h"
+#include "intel_display_types.h"
+#include "intel_vblank.h"
+#include "intel_vdsc.h"
+#include "skl_prefill.h"
+#include "skl_scaler.h"
+#include "skl_watermark.h"
+
+static unsigned int prefill_usecs_to_lines(const struct intel_crtc_state *crtc_state,
+					   unsigned int usecs)
+{
+	const struct drm_display_mode *pipe_mode = &crtc_state->hw.pipe_mode;
+
+	return DIV_ROUND_UP_ULL(mul_u32_u32(pipe_mode->crtc_clock, usecs << 16),
+				pipe_mode->crtc_htotal * 1000);
+}
+
+static void prefill_init(struct skl_prefill_ctx *ctx,
+			 const struct intel_crtc_state *crtc_state)
+{
+	memset(ctx, 0, sizeof(*ctx));
+
+	ctx->prefill.fixed = crtc_state->framestart_delay << 16;
+
+	/* 20 usec for translation walks/etc. */
+	ctx->prefill.fixed += prefill_usecs_to_lines(crtc_state, 20);
+
+	ctx->prefill.dsc = intel_vdsc_prefill_lines(crtc_state);
+}
+
+static void prefill_init_nocdclk_worst(struct skl_prefill_ctx *ctx,
+				       const struct intel_crtc_state *crtc_state)
+{
+	prefill_init(ctx, crtc_state);
+
+	ctx->prefill.wm0 = skl_wm0_prefill_lines_worst(crtc_state);
+	ctx->prefill.scaler_1st = skl_scaler_1st_prefill_lines_worst(crtc_state);
+	ctx->prefill.scaler_2nd = skl_scaler_2nd_prefill_lines_worst(crtc_state);
+
+	ctx->adj.scaler_1st = skl_scaler_1st_prefill_adjustment_worst(crtc_state);
+	ctx->adj.scaler_2nd = skl_scaler_2nd_prefill_adjustment_worst(crtc_state);
+}
+
+static void prefill_init_nocdclk(struct skl_prefill_ctx *ctx,
+				 const struct intel_crtc_state *crtc_state)
+{
+	prefill_init(ctx, crtc_state);
+
+	ctx->prefill.wm0 = skl_wm0_prefill_lines(crtc_state);
+	ctx->prefill.scaler_1st = skl_scaler_1st_prefill_lines(crtc_state);
+	ctx->prefill.scaler_2nd = skl_scaler_2nd_prefill_lines(crtc_state);
+
+	ctx->adj.scaler_1st = skl_scaler_1st_prefill_adjustment(crtc_state);
+	ctx->adj.scaler_2nd = skl_scaler_2nd_prefill_adjustment(crtc_state);
+}
+
+static unsigned int prefill_adjust(unsigned int value, unsigned int factor)
+{
+	return DIV_ROUND_UP_ULL(mul_u32_u32(value, factor), 0x10000);
+}
+
+static unsigned int prefill_lines_nocdclk(const struct skl_prefill_ctx *ctx)
+{
+	unsigned int prefill = 0;
+
+	prefill += ctx->prefill.dsc;
+	prefill = prefill_adjust(prefill, ctx->adj.scaler_2nd);
+
+	prefill += ctx->prefill.scaler_2nd;
+	prefill = prefill_adjust(prefill, ctx->adj.scaler_1st);
+
+	prefill += ctx->prefill.scaler_1st;
+	prefill += ctx->prefill.wm0;
+
+	return prefill;
+}
+
+static unsigned int prefill_lines_cdclk(const struct skl_prefill_ctx *ctx)
+{
+	return prefill_adjust(prefill_lines_nocdclk(ctx), ctx->adj.cdclk);
+}
+
+static unsigned int prefill_lines_full(const struct skl_prefill_ctx *ctx)
+{
+	return ctx->prefill.fixed + prefill_lines_cdclk(ctx);
+}
+
+void skl_prefill_init_worst(struct skl_prefill_ctx *ctx,
+			    const struct intel_crtc_state *crtc_state)
+{
+	prefill_init_nocdclk_worst(ctx, crtc_state);
+
+	ctx->adj.cdclk = intel_cdclk_prefill_adjustment_worst(crtc_state);
+
+	ctx->prefill.full = prefill_lines_full(ctx);
+}
+
+void skl_prefill_init(struct skl_prefill_ctx *ctx,
+		      const struct intel_crtc_state *crtc_state)
+{
+	prefill_init_nocdclk(ctx, crtc_state);
+
+	ctx->adj.cdclk = intel_cdclk_prefill_adjustment(crtc_state);
+
+	ctx->prefill.full = prefill_lines_full(ctx);
+}
+
+static unsigned int prefill_lines_with_latency(const struct skl_prefill_ctx *ctx,
+					       const struct intel_crtc_state *crtc_state,
+					       unsigned int latency_us)
+{
+	return ctx->prefill.full + prefill_usecs_to_lines(crtc_state, latency_us);
+}
+
+int skl_prefill_min_guardband(const struct skl_prefill_ctx *ctx,
+			      const struct intel_crtc_state *crtc_state,
+			      unsigned int latency_us)
+{
+	unsigned int prefill = prefill_lines_with_latency(ctx, crtc_state, latency_us);
+
+	return DIV_ROUND_UP(prefill, 0x10000);
+}
+
+static unsigned int prefill_guardband(const struct intel_crtc_state *crtc_state)
+{
+	return intel_crtc_vblank_length(crtc_state) << 16;
+}
+
+bool skl_prefill_vblank_too_short(const struct skl_prefill_ctx *ctx,
+				  const struct intel_crtc_state *crtc_state,
+				  unsigned int latency_us)
+{
+	unsigned int guardband = prefill_guardband(crtc_state);
+	unsigned int prefill = prefill_lines_with_latency(ctx, crtc_state, latency_us);
+
+	return guardband < prefill;
+}
+
+int skl_prefill_min_cdclk(const struct skl_prefill_ctx *ctx,
+			  const struct intel_crtc_state *crtc_state)
+{
+	unsigned int prefill_unadjusted = prefill_lines_nocdclk(ctx);
+	unsigned int prefill_available = prefill_guardband(crtc_state) - ctx->prefill.fixed;
+
+	return intel_cdclk_min_cdclk_for_prefill(crtc_state, prefill_unadjusted,
+						 prefill_available);
+}
diff --git a/drivers/gpu/drm/i915/display/skl_prefill.h b/drivers/gpu/drm/i915/display/skl_prefill.h
new file mode 100644
index 000000000000..028ee19b64ce
--- /dev/null
+++ b/drivers/gpu/drm/i915/display/skl_prefill.h
@@ -0,0 +1,46 @@
+/* SPDX-License-Identifier: MIT */
+/*
+ * Copyright © 2025 Intel Corporation
+ */
+
+#ifndef __SKL_PREFILL_H__
+#define __SKL_PREFILL_H__
+
+#include <linux/types.h>
+
+struct intel_crtc_state;
+
+struct skl_prefill_ctx {
+	/* .16 scanlines */
+	struct {
+		unsigned int fixed;
+		unsigned int wm0;
+		unsigned int scaler_1st;
+		unsigned int scaler_2nd;
+		unsigned int dsc;
+		unsigned int full;
+	} prefill;
+
+	/* .16 adjustment factors */
+	struct {
+		unsigned int cdclk;
+		unsigned int scaler_1st;
+		unsigned int scaler_2nd;
+	} adj;
+};
+
+void skl_prefill_init_worst(struct skl_prefill_ctx *ctx,
+			    const struct intel_crtc_state *crtc_state);
+void skl_prefill_init(struct skl_prefill_ctx *ctx,
+		      const struct intel_crtc_state *crtc_state);
+
+bool skl_prefill_vblank_too_short(const struct skl_prefill_ctx *ctx,
+				  const struct intel_crtc_state *crtc_state,
+				  unsigned int latency_us);
+int skl_prefill_min_guardband(const struct skl_prefill_ctx *ctx,
+			      const struct intel_crtc_state *crtc_state,
+			      unsigned int latency_us);
+int skl_prefill_min_cdclk(const struct skl_prefill_ctx *ctx,
+			  const struct intel_crtc_state *crtc_state);
+
+#endif /* __SKL_PREFILL_H__ */
diff --git a/drivers/gpu/drm/i915/display/skl_scaler.c b/drivers/gpu/drm/i915/display/skl_scaler.c
index c6cccf170ff1..d29efcbf2319 100644
--- a/drivers/gpu/drm/i915/display/skl_scaler.c
+++ b/drivers/gpu/drm/i915/display/skl_scaler.c
@@ -968,3 +968,144 @@ void adl_scaler_ecc_unmask(const struct intel_crtc_state *crtc_state)
 			  1);
 	intel_de_write(display, XELPD_DISPLAY_ERR_FATAL_MASK, 0);
 }
+
+unsigned int skl_scaler_1st_prefill_adjustment(const struct intel_crtc_state *crtc_state)
+{
+	/*
+	 * FIXME don't have scalers assigned yet
+	 * so can't look up the scale factors
+	 */
+	return 0x10000;
+}
+
+unsigned int skl_scaler_2nd_prefill_adjustment(const struct intel_crtc_state *crtc_state)
+{
+	/*
+	 * FIXME don't have scalers assigned yet
+	 * so can't look up the scale factors
+	 */
+	return 0x10000;
+}
+
+unsigned int skl_scaler_1st_prefill_lines(const struct intel_crtc_state *crtc_state)
+{
+	const struct intel_crtc_scaler_state *scaler_state =
+		&crtc_state->scaler_state;
+	int num_scalers = hweight32(scaler_state->scaler_users);
+
+	if (num_scalers > 0)
+		return 4 << 16;
+
+	return 0;
+}
+
+unsigned int skl_scaler_2nd_prefill_lines(const struct intel_crtc_state *crtc_state)
+{
+	const struct intel_crtc_scaler_state *scaler_state =
+		&crtc_state->scaler_state;
+	int num_scalers = hweight32(scaler_state->scaler_users);
+
+	if (num_scalers > 1 && crtc_state->pch_pfit.enabled)
+		return 4 << 16;
+
+	return 0;
+}
+
+static unsigned int _skl_scaler_max_scale(const struct intel_crtc_state *crtc_state,
+					  unsigned int max_scale)
+{
+	struct intel_display *display = to_intel_display(crtc_state);
+
+	/*
+	 * Downscaling requires increasing cdclk, so max scale
+	 * factor is limited to the max_dotclock/dotclock ratio.
+	 *
+	 * FIXME find out the max downscale factors properly
+	 */
+	return min(max_scale, DIV_ROUND_UP_ULL((u64)display->cdclk.max_dotclk_freq << 16,
+					       crtc_state->hw.pipe_mode.crtc_clock));
+}
+
+unsigned int skl_scaler_max_total_scale(const struct intel_crtc_state *crtc_state)
+{
+	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
+	unsigned int max_scale;
+
+	if (crtc->num_scalers < 1)
+		return 0x10000;
+
+	/* FIXME find out the max downscale factors properly */
+	max_scale = 9 << 16;
+	if (crtc->num_scalers > 1)
+		max_scale *= 9;
+
+	return _skl_scaler_max_scale(crtc_state, max_scale);
+}
+
+unsigned int skl_scaler_max_hscale(const struct intel_crtc_state *crtc_state)
+{
+	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
+	unsigned int max_scale;
+
+	if (crtc->num_scalers < 1)
+		return 0x10000;
+
+	/* FIXME find out the max downscale factors properly */
+	max_scale = 3 << 16;
+
+	return _skl_scaler_max_scale(crtc_state, max_scale);
+}
+
+unsigned int skl_scaler_max_scale(const struct intel_crtc_state *crtc_state)
+{
+	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
+	unsigned int max_scale;
+
+	if (crtc->num_scalers < 1)
+		return 0x10000;
+
+	/* FIXME find out the max downscale factors properly */
+	max_scale = 9 << 16;
+
+	return _skl_scaler_max_scale(crtc_state, max_scale);
+}
+
+unsigned int skl_scaler_1st_prefill_adjustment_worst(const struct intel_crtc_state *crtc_state)
+{
+	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
+
+	if (crtc->num_scalers > 0)
+		return skl_scaler_max_scale(crtc_state);
+	else
+		return 0x10000;
+}
+
+unsigned int skl_scaler_2nd_prefill_adjustment_worst(const struct intel_crtc_state *crtc_state)
+{
+	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
+
+	if (crtc->num_scalers > 1)
+		return skl_scaler_max_scale(crtc_state);
+	else
+		return 0x10000;
+}
+
+unsigned int skl_scaler_1st_prefill_lines_worst(const struct intel_crtc_state *crtc_state)
+{
+	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
+
+	if (crtc->num_scalers > 0)
+		return 4 << 16;
+	else
+		return 0;
+}
+
+unsigned int skl_scaler_2nd_prefill_lines_worst(const struct intel_crtc_state *crtc_state)
+{
+	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
+
+	if (crtc->num_scalers > 1)
+		return 4 << 16;
+	else
+		return 0;
+}
diff --git a/drivers/gpu/drm/i915/display/skl_scaler.h b/drivers/gpu/drm/i915/display/skl_scaler.h
index 12a19016c5f6..5deabca909e6 100644
--- a/drivers/gpu/drm/i915/display/skl_scaler.h
+++ b/drivers/gpu/drm/i915/display/skl_scaler.h
@@ -45,4 +45,19 @@ skl_scaler_mode_valid(struct intel_display *display,
 void adl_scaler_ecc_mask(const struct intel_crtc_state *crtc_state);
 
 void adl_scaler_ecc_unmask(const struct intel_crtc_state *crtc_state);
+
+unsigned int skl_scaler_max_total_scale(const struct intel_crtc_state *crtc_state);
+unsigned int skl_scaler_max_scale(const struct intel_crtc_state *crtc_state);
+unsigned int skl_scaler_max_hscale(const struct intel_crtc_state *crtc_state);
+
+unsigned int skl_scaler_1st_prefill_adjustment_worst(const struct intel_crtc_state *crtc_state);
+unsigned int skl_scaler_2nd_prefill_adjustment_worst(const struct intel_crtc_state *crtc_state);
+unsigned int skl_scaler_1st_prefill_lines_worst(const struct intel_crtc_state *crtc_state);
+unsigned int skl_scaler_2nd_prefill_lines_worst(const struct intel_crtc_state *crtc_state);
+
+unsigned int skl_scaler_1st_prefill_adjustment(const struct intel_crtc_state *crtc_state);
+unsigned int skl_scaler_2nd_prefill_adjustment(const struct intel_crtc_state *crtc_state);
+unsigned int skl_scaler_1st_prefill_lines(const struct intel_crtc_state *crtc_state);
+unsigned int skl_scaler_2nd_prefill_lines(const struct intel_crtc_state *crtc_state);
+
 #endif
diff --git a/drivers/gpu/drm/i915/display/skl_watermark.c b/drivers/gpu/drm/i915/display/skl_watermark.c
index 06e5e6c77d2e..256162da9afc 100644
--- a/drivers/gpu/drm/i915/display/skl_watermark.c
+++ b/drivers/gpu/drm/i915/display/skl_watermark.c
@@ -30,6 +30,8 @@
 #include "intel_plane.h"
 #include "intel_vblank.h"
 #include "intel_wm.h"
+#include "skl_prefill.h"
+#include "skl_scaler.h"
 #include "skl_universal_plane_regs.h"
 #include "skl_watermark.h"
 #include "skl_watermark_regs.h"
@@ -2146,103 +2148,55 @@ static int icl_build_plane_wm(struct intel_crtc_state *crtc_state,
 	return 0;
 }
 
-static int
-cdclk_prefill_adjustment(const struct intel_crtc_state *crtc_state)
+unsigned int skl_wm0_prefill_lines_worst(const struct intel_crtc_state *crtc_state)
 {
 	struct intel_display *display = to_intel_display(crtc_state);
-	struct intel_atomic_state *state =
-		to_intel_atomic_state(crtc_state->uapi.state);
-	const struct intel_cdclk_state *cdclk_state;
-
-	cdclk_state = intel_atomic_get_cdclk_state(state);
-	if (IS_ERR(cdclk_state)) {
-		drm_WARN_ON(display->drm, PTR_ERR(cdclk_state));
-		return 1;
-	}
-
-	return min(1, DIV_ROUND_UP(crtc_state->pixel_rate,
-				   2 * intel_cdclk_logical(cdclk_state)));
-}
-
-static int
-dsc_prefill_latency(const struct intel_crtc_state *crtc_state)
-{
-	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
-	const struct intel_crtc_scaler_state *scaler_state =
-					&crtc_state->scaler_state;
-	int linetime = DIV_ROUND_UP(1000 * crtc_state->hw.adjusted_mode.htotal,
-				    crtc_state->hw.adjusted_mode.clock);
-	int num_scaler_users = hweight32(scaler_state->scaler_users);
-	int chroma_downscaling_factor =
-		crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420 ? 2 : 1;
-	u32 dsc_prefill_latency = 0;
-
-	if (!crtc_state->dsc.compression_enable ||
-	    !num_scaler_users ||
-	    num_scaler_users > crtc->num_scalers)
-		return dsc_prefill_latency;
-
-	dsc_prefill_latency = DIV_ROUND_UP(15 * linetime * chroma_downscaling_factor, 10);
-
-	for (int i = 0; i < num_scaler_users; i++) {
-		u64 hscale_k, vscale_k;
-
-		hscale_k = max(1000, mul_u32_u32(scaler_state->scalers[i].hscale, 1000) >> 16);
-		vscale_k = max(1000, mul_u32_u32(scaler_state->scalers[i].vscale, 1000) >> 16);
-		dsc_prefill_latency = DIV_ROUND_UP_ULL(dsc_prefill_latency * hscale_k * vscale_k,
-						       1000000);
-	}
-
-	dsc_prefill_latency *= cdclk_prefill_adjustment(crtc_state);
+	struct intel_plane *plane = to_intel_plane(crtc_state->uapi.crtc->primary);
+	const struct drm_display_mode *pipe_mode = &crtc_state->hw.pipe_mode;
+	int ret, pixel_rate, width, level = 0;
+	const struct drm_format_info *info;
+	struct skl_wm_level wm = {};
+	struct skl_wm_params wp;
+	unsigned int latency;
+	u64 modifier;
+	u32 format;
 
-	return intel_usecs_to_scanlines(&crtc_state->hw.adjusted_mode, dsc_prefill_latency);
-}
+	/* only expected to be used for VRR guardband calculation */
+	drm_WARN_ON(display->drm, !HAS_VRR(display));
 
-static int
-scaler_prefill_latency(const struct intel_crtc_state *crtc_state)
-{
-	const struct intel_crtc_scaler_state *scaler_state =
-					&crtc_state->scaler_state;
-	int num_scaler_users = hweight32(scaler_state->scaler_users);
-	int scaler_prefill_latency = 0;
-	int linetime = DIV_ROUND_UP(1000 * crtc_state->hw.adjusted_mode.htotal,
-				    crtc_state->hw.adjusted_mode.clock);
+	/* FIXME rather ugly to pick this by hand but maybe no better way? */
+	format = DRM_FORMAT_XBGR16161616F;
+	if (HAS_4TILE(display))
+		modifier = I915_FORMAT_MOD_4_TILED;
+	else
+		modifier = I915_FORMAT_MOD_Y_TILED;
 
-	if (!num_scaler_users)
-		return scaler_prefill_latency;
+	info = drm_get_format_info(display->drm, format, modifier);
 
-	scaler_prefill_latency = 4 * linetime;
+	pixel_rate = DIV_ROUND_UP_ULL(mul_u32_u32(skl_scaler_max_total_scale(crtc_state),
+						  pipe_mode->crtc_clock),
+				      0x10000);
 
-	if (num_scaler_users > 1) {
-		u64 hscale_k = max(1000, mul_u32_u32(scaler_state->scalers[0].hscale, 1000) >> 16);
-		u64 vscale_k = max(1000, mul_u32_u32(scaler_state->scalers[0].vscale, 1000) >> 16);
-		int chroma_downscaling_factor =
-			crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420 ? 2 : 1;
-		int latency;
+	/* FIXME limit to max plane width? */
+	width = DIV_ROUND_UP_ULL(mul_u32_u32(skl_scaler_max_hscale(crtc_state),
+					     pipe_mode->crtc_hdisplay),
+				 0x10000);
 
-		latency = DIV_ROUND_UP_ULL((4 * linetime * hscale_k * vscale_k *
-					    chroma_downscaling_factor), 1000000);
-		scaler_prefill_latency += latency;
-	}
+	/* FIXME is 90/270 rotation worse than 0/180? */
+	ret = skl_compute_wm_params(crtc_state, width, info,
+				    modifier, DRM_MODE_ROTATE_0,
+				    pixel_rate, &wp, 0, 1);
+	drm_WARN_ON(display->drm, ret);
 
-	scaler_prefill_latency *= cdclk_prefill_adjustment(crtc_state);
+	latency = skl_wm_latency(display, level, &wp);
 
-	return intel_usecs_to_scanlines(&crtc_state->hw.adjusted_mode, scaler_prefill_latency);
-}
+	skl_compute_plane_wm(crtc_state, plane, level, latency, &wp, &wm, &wm);
 
-static bool
-skl_is_vblank_too_short(const struct intel_crtc_state *crtc_state,
-			int wm0_lines, int latency)
-{
-	const struct drm_display_mode *adjusted_mode =
-		&crtc_state->hw.adjusted_mode;
+	/* FIXME is this sane? */
+	if (wm.min_ddb_alloc == U16_MAX)
+		wm.lines = skl_wm_max_lines(display);
 
-	return crtc_state->framestart_delay +
-		intel_usecs_to_scanlines(adjusted_mode, latency) +
-		scaler_prefill_latency(crtc_state) +
-		dsc_prefill_latency(crtc_state) +
-		wm0_lines >
-		intel_crtc_vblank_length(crtc_state);
+	return wm.lines << 16;
 }
 
 static int skl_max_wm0_lines(const struct intel_crtc_state *crtc_state)
@@ -2261,15 +2215,21 @@ static int skl_max_wm0_lines(const struct intel_crtc_state *crtc_state)
 	return wm0_lines;
 }
 
+unsigned int skl_wm0_prefill_lines(const struct intel_crtc_state *crtc_state)
+{
+	return skl_max_wm0_lines(crtc_state) << 16;
+}
+
 /*
  * TODO: In case we use PKG_C_LATENCY to allow C-states when the delayed vblank
  * size is too small for the package C exit latency we need to notify PSR about
  * the scenario to apply Wa_16025596647.
  */
 static int skl_max_wm_level_for_vblank(struct intel_crtc_state *crtc_state,
-				       int wm0_lines)
+				       const struct skl_prefill_ctx *ctx)
 {
 	struct intel_display *display = to_intel_display(crtc_state);
+	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
 	int level;
 
 	for (level = display->wm.num_levels - 1; level >= 0; level--) {
@@ -2284,10 +2244,13 @@ static int skl_max_wm_level_for_vblank(struct intel_crtc_state *crtc_state,
 		if (level == 0)
 			latency = 0;
 
-		if (!skl_is_vblank_too_short(crtc_state, wm0_lines, latency))
+		if (!skl_prefill_vblank_too_short(ctx, crtc_state, latency))
 			return level;
 	}
 
+	drm_dbg_kms(display->drm, "[CRTC:%d:%s] Not enough time in vblank for prefill\n",
+		    crtc->base.base.id, crtc->base.name);
+
 	return -EINVAL;
 }
 
@@ -2295,14 +2258,15 @@ static int skl_wm_check_vblank(struct intel_crtc_state *crtc_state)
 {
 	struct intel_display *display = to_intel_display(crtc_state);
 	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
-	int wm0_lines, level;
+	struct skl_prefill_ctx ctx;
+	int level;
 
 	if (!crtc_state->hw.active)
 		return 0;
 
-	wm0_lines = skl_max_wm0_lines(crtc_state);
+	skl_prefill_init(&ctx, crtc_state);
 
-	level = skl_max_wm_level_for_vblank(crtc_state, wm0_lines);
+	level = skl_max_wm_level_for_vblank(crtc_state, &ctx);
 	if (level < 0)
 		return level;
 
@@ -2312,6 +2276,13 @@ static int skl_wm_check_vblank(struct intel_crtc_state *crtc_state)
 	 */
 	crtc_state->wm_level_disabled = level < display->wm.num_levels - 1;
 
+	/*
+	 * TODO: assert that we are in fact using the maximum guardband
+	 * if we end up disabling any WM levels here. Otherwise we clearly
+	 * failed in using a realistic worst case prefill estimate when
+	 * determining the guardband size.
+	 */
+
 	for (level++; level < display->wm.num_levels; level++) {
 		enum plane_id plane_id;
 
@@ -2330,8 +2301,8 @@ static int skl_wm_check_vblank(struct intel_crtc_state *crtc_state)
 
 	if (DISPLAY_VER(display) >= 12 &&
 	    display->sagv.block_time_us &&
-	    skl_is_vblank_too_short(crtc_state, wm0_lines,
-				    display->sagv.block_time_us)) {
+	    skl_prefill_vblank_too_short(&ctx, crtc_state,
+					 display->sagv.block_time_us)) {
 		enum plane_id plane_id;
 
 		for_each_plane_id_on_crtc(crtc, plane_id) {
diff --git a/drivers/gpu/drm/i915/display/skl_watermark.h b/drivers/gpu/drm/i915/display/skl_watermark.h
index 62790816f030..6bc2ec9164bf 100644
--- a/drivers/gpu/drm/i915/display/skl_watermark.h
+++ b/drivers/gpu/drm/i915/display/skl_watermark.h
@@ -79,5 +79,8 @@ void intel_program_dpkgc_latency(struct intel_atomic_state *state);
 
 bool intel_dbuf_pmdemand_needs_update(struct intel_atomic_state *state);
 
+unsigned int skl_wm0_prefill_lines_worst(const struct intel_crtc_state *crtc_state);
+unsigned int skl_wm0_prefill_lines(const struct intel_crtc_state *crtc_state);
+
 #endif /* __SKL_WATERMARK_H__ */
 
diff --git a/drivers/gpu/drm/xe/Makefile b/drivers/gpu/drm/xe/Makefile
index 84321fad3265..6f5964f1a04d 100644
--- a/drivers/gpu/drm/xe/Makefile
+++ b/drivers/gpu/drm/xe/Makefile
@@ -311,6 +311,7 @@ xe-$(CONFIG_DRM_XE_DISPLAY) += \
 	i915-display/intel_vga.o \
 	i915-display/intel_vrr.o \
 	i915-display/intel_wm.o \
+	i915-display/skl_prefill.o \
 	i915-display/skl_scaler.o \
 	i915-display/skl_universal_plane.o \
 	i915-display/skl_watermark.o
-- 
2.45.2


^ permalink raw reply related	[flat|nested] 14+ messages in thread

* [PATCH 3/6] drm/i915/psr: Add helper to get min psr guardband
  2025-10-16  9:30 [PATCH 0/6] Optimize vrr.guardband Ankit Nautiyal
  2025-10-16  9:30 ` [PATCH 1/6] [NOT FOR REVIEW] drm/i915/vrr: prep patches for guardband optimization squashed Ankit Nautiyal
  2025-10-16  9:30 ` [PATCH 2/6] [NOT FOR REVIEW] drm/i915/prefill: Prefill latency calculations series squashed Ankit Nautiyal
@ 2025-10-16  9:30 ` Ankit Nautiyal
  2025-10-16  9:30 ` [PATCH 4/6] drm/i915/dp: Add helper to get min sdp guardband Ankit Nautiyal
                   ` (7 subsequent siblings)
  10 siblings, 0 replies; 14+ messages in thread
From: Ankit Nautiyal @ 2025-10-16  9:30 UTC (permalink / raw)
  To: intel-gfx, intel-xe; +Cc: ville.syrjala, Ankit Nautiyal

Introduce a helper to compute the max link wake latency when using
Auxless/Aux wake mechanism for PSR/Panel Replay/LOBF features.

This will be used to compute the minimum guardband so that the link wake
latencies are accounted and these features work smoothly for higher
refresh rate panels.

Bspec: 70151, 71477
Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
---
 drivers/gpu/drm/i915/display/intel_psr.c | 12 ++++++++++++
 drivers/gpu/drm/i915/display/intel_psr.h |  1 +
 2 files changed, 13 insertions(+)

diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c
index 703e5f6af04c..a8303b669853 100644
--- a/drivers/gpu/drm/i915/display/intel_psr.c
+++ b/drivers/gpu/drm/i915/display/intel_psr.c
@@ -4416,3 +4416,15 @@ void intel_psr_compute_config_late(struct intel_dp *intel_dp,
 
 	intel_psr_set_non_psr_pipes(intel_dp, crtc_state);
 }
+
+int intel_psr_min_guardband(struct intel_crtc_state *crtc_state)
+{
+	struct intel_display *display = to_intel_display(crtc_state);
+	int auxless_wake_lines = crtc_state->alpm_state.aux_less_wake_lines;
+	int wake_lines = DISPLAY_VER(display) < 20 ?
+			 psr2_block_count_lines(crtc_state->alpm_state.io_wake_lines,
+						crtc_state->alpm_state.fast_wake_lines) :
+			 crtc_state->alpm_state.io_wake_lines;
+
+	return max(auxless_wake_lines, wake_lines);
+}
diff --git a/drivers/gpu/drm/i915/display/intel_psr.h b/drivers/gpu/drm/i915/display/intel_psr.h
index b17ce312dc37..620b35928832 100644
--- a/drivers/gpu/drm/i915/display/intel_psr.h
+++ b/drivers/gpu/drm/i915/display/intel_psr.h
@@ -85,5 +85,6 @@ bool intel_psr_needs_alpm_aux_less(struct intel_dp *intel_dp,
 				   const struct intel_crtc_state *crtc_state);
 void intel_psr_compute_config_late(struct intel_dp *intel_dp,
 				   struct intel_crtc_state *crtc_state);
+int intel_psr_min_guardband(struct intel_crtc_state *crtc_state);
 
 #endif /* __INTEL_PSR_H__ */
-- 
2.45.2


^ permalink raw reply related	[flat|nested] 14+ messages in thread

* [PATCH 4/6] drm/i915/dp: Add helper to get min sdp guardband
  2025-10-16  9:30 [PATCH 0/6] Optimize vrr.guardband Ankit Nautiyal
                   ` (2 preceding siblings ...)
  2025-10-16  9:30 ` [PATCH 3/6] drm/i915/psr: Add helper to get min psr guardband Ankit Nautiyal
@ 2025-10-16  9:30 ` Ankit Nautiyal
  2025-10-16  9:30 ` [PATCH 5/6] drm/i915/dp: Check if guardband can accommodate sdp latencies Ankit Nautiyal
                   ` (6 subsequent siblings)
  10 siblings, 0 replies; 14+ messages in thread
From: Ankit Nautiyal @ 2025-10-16  9:30 UTC (permalink / raw)
  To: intel-gfx, intel-xe; +Cc: ville.syrjala, Ankit Nautiyal

Add a helper to compute vblank time needed for transmitting specific
DisplayPort SDPs like PPS, GAMUT_METADATA, and VSC_EXT. Latency is
based on line count per packet type.

This will be used to ensure adequate guardband when features like DSC/HDR
are enabled.

Bspec: 70151
Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
---
 drivers/gpu/drm/i915/display/intel_dp.c | 36 +++++++++++++++++++++++++
 drivers/gpu/drm/i915/display/intel_dp.h |  2 ++
 2 files changed, 38 insertions(+)

diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index 7059d55687cf..3f2c319e3d6f 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -6990,3 +6990,39 @@ int intel_dp_compute_config_late(struct intel_encoder *encoder,
 
 	return 0;
 }
+
+static
+int intel_dp_get_lines_for_sdp(u32 type)
+{
+	switch (type) {
+	case DP_SDP_VSC_EXT_VESA:
+	case DP_SDP_VSC_EXT_CEA:
+		return 10;
+	case HDMI_PACKET_TYPE_GAMUT_METADATA:
+		return 8;
+	case DP_SDP_PPS:
+		return 6;
+	default:
+		break;
+	}
+
+	return 0;
+}
+
+int intel_dp_sdp_min_guardband(const struct intel_crtc_state *crtc_state,
+			       bool assume_all_enabled)
+{
+	int sdp_guardband = 0;
+
+	if (assume_all_enabled ||
+	    crtc_state->infoframes.enable &
+	    intel_hdmi_infoframe_enable(HDMI_PACKET_TYPE_GAMUT_METADATA))
+		sdp_guardband = max(sdp_guardband,
+				    intel_dp_get_lines_for_sdp(HDMI_PACKET_TYPE_GAMUT_METADATA));
+
+	if (assume_all_enabled ||
+	    crtc_state->dsc.compression_enable)
+		sdp_guardband = max(sdp_guardband, intel_dp_get_lines_for_sdp(DP_SDP_PPS));
+
+	return sdp_guardband;
+}
diff --git a/drivers/gpu/drm/i915/display/intel_dp.h b/drivers/gpu/drm/i915/display/intel_dp.h
index 281ced3a3b39..7ee5aeb28fe2 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.h
+++ b/drivers/gpu/drm/i915/display/intel_dp.h
@@ -221,5 +221,7 @@ bool intel_dp_in_hdr_mode(const struct drm_connector_state *conn_state);
 int intel_dp_compute_config_late(struct intel_encoder *encoder,
 				 struct intel_crtc_state *crtc_state,
 				 struct drm_connector_state *conn_state);
+int intel_dp_sdp_min_guardband(const struct intel_crtc_state *crtc_state,
+			       bool assume_all_enabled);
 
 #endif /* __INTEL_DP_H__ */
-- 
2.45.2


^ permalink raw reply related	[flat|nested] 14+ messages in thread

* [PATCH 5/6] drm/i915/dp: Check if guardband can accommodate sdp latencies
  2025-10-16  9:30 [PATCH 0/6] Optimize vrr.guardband Ankit Nautiyal
                   ` (3 preceding siblings ...)
  2025-10-16  9:30 ` [PATCH 4/6] drm/i915/dp: Add helper to get min sdp guardband Ankit Nautiyal
@ 2025-10-16  9:30 ` Ankit Nautiyal
  2025-10-16  9:30 ` [PATCH 6/6] drm/i915/vrr: Use the min static optimized guardband Ankit Nautiyal
                   ` (5 subsequent siblings)
  10 siblings, 0 replies; 14+ messages in thread
From: Ankit Nautiyal @ 2025-10-16  9:30 UTC (permalink / raw)
  To: intel-gfx, intel-xe; +Cc: ville.syrjala, Ankit Nautiyal

Check if guardband is sufficient for all DP SDP latencies.
If its not, fail .compute_config_late().

Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
---
 drivers/gpu/drm/i915/display/intel_dp.c | 22 ++++++++++++++++++++++
 1 file changed, 22 insertions(+)

diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index 3f2c319e3d6f..8ae99cee79d4 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -93,6 +93,7 @@
 #include "intel_psr.h"
 #include "intel_quirks.h"
 #include "intel_tc.h"
+#include "intel_vblank.h"
 #include "intel_vdsc.h"
 #include "intel_vrr.h"
 
@@ -6980,14 +6981,35 @@ void intel_dp_mst_resume(struct intel_display *display)
 	}
 }
 
+static
+int intel_dp_sdp_compute_config_late(struct intel_crtc_state *crtc_state)
+{
+	struct intel_display *display = to_intel_display(crtc_state);
+	int guardband = intel_crtc_vblank_length(crtc_state);
+	int min_sdp_guardband = intel_dp_sdp_min_guardband(crtc_state, false);
+
+	if (guardband < min_sdp_guardband) {
+		drm_dbg_kms(display->drm, "guardband %d < min sdp guardband %d\n",
+			    guardband, min_sdp_guardband);
+		return -EINVAL;
+	}
+
+	return 0;
+}
+
 int intel_dp_compute_config_late(struct intel_encoder *encoder,
 				 struct intel_crtc_state *crtc_state,
 				 struct drm_connector_state *conn_state)
 {
 	struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
+	int ret;
 
 	intel_psr_compute_config_late(intel_dp, crtc_state);
 
+	ret = intel_dp_sdp_compute_config_late(crtc_state);
+	if (ret)
+		return ret;
+
 	return 0;
 }
 
-- 
2.45.2


^ permalink raw reply related	[flat|nested] 14+ messages in thread

* [PATCH 6/6] drm/i915/vrr: Use the min static optimized guardband
  2025-10-16  9:30 [PATCH 0/6] Optimize vrr.guardband Ankit Nautiyal
                   ` (4 preceding siblings ...)
  2025-10-16  9:30 ` [PATCH 5/6] drm/i915/dp: Check if guardband can accommodate sdp latencies Ankit Nautiyal
@ 2025-10-16  9:30 ` Ankit Nautiyal
  2025-10-16 17:29   ` Ville Syrjälä
  2025-10-16 10:31 ` ✗ CI.checkpatch: warning for Optimize vrr.guardband (rev2) Patchwork
                   ` (4 subsequent siblings)
  10 siblings, 1 reply; 14+ messages in thread
From: Ankit Nautiyal @ 2025-10-16  9:30 UTC (permalink / raw)
  To: intel-gfx, intel-xe; +Cc: ville.syrjala, Ankit Nautiyal

In the current VRR implementation, vrr.vmin and vrr.guardband are set such
that they do not need to change when switching from fixed refresh rate to
variable refresh rate. Specifically, vrr.guardband is always set to match
the vblank length. This approach works for most cases, but not for LRR,
where the guardband would need to change while the VRR timing generator is
still active.

With the VRR TG always active, live updates to guardband are unsafe and not
recommended. To ensure hardware safety, guardband was moved out of the
!fastset block, meaning any change now requires a full modeset.
This breaks seamless LRR switching, which was previously supported.

Since the problem arises from guardband being matched to the vblank length,
solution is to use a minimal, sufficient static value, instead. So we use a
static guardband defined during mode-set that fits within the smallest
expected vblank and remains unchanged in case of features like LRR where
vtotal changes. To compute this minimum guardband we take into account
latencies/delays due to different features as mentioned in the Bspec.

Introduce a helper to compute the minimal sufficient guardband.
On platforms where the VRR timing generator is always ON, we optimize the
guardband regardless of whether the display is operating in fixed or
variable refresh rate mode.
On platforms where the VRR timing generator is not always ON, we optimize
the guardband only when VRR is enabled.

Bspec: 70151
Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
---
 drivers/gpu/drm/i915/display/intel_vrr.c | 50 +++++++++++++++++++++++-
 1 file changed, 48 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_vrr.c b/drivers/gpu/drm/i915/display/intel_vrr.c
index 597008a6c744..732e356e6fac 100644
--- a/drivers/gpu/drm/i915/display/intel_vrr.c
+++ b/drivers/gpu/drm/i915/display/intel_vrr.c
@@ -6,12 +6,16 @@
 
 #include <drm/drm_print.h>
 
+#include "intel_crtc.h"
 #include "intel_de.h"
 #include "intel_display_regs.h"
 #include "intel_display_types.h"
 #include "intel_dp.h"
+#include "intel_psr.h"
 #include "intel_vrr.h"
 #include "intel_vrr_regs.h"
+#include "skl_prefill.h"
+#include "skl_watermark.h"
 
 #define FIXED_POINT_PRECISION		100
 #define CMRR_PRECISION_TOLERANCE	10
@@ -433,17 +437,59 @@ intel_vrr_max_guardband(struct intel_crtc_state *crtc_state)
 		   intel_vrr_max_vblank_guardband(crtc_state));
 }
 
+static
+int intel_vrr_compute_optimized_guardband(struct intel_crtc_state *crtc_state)
+{
+	struct intel_display *display = to_intel_display(crtc_state);
+	struct skl_prefill_ctx prefill_ctx;
+	int psr_min_guardband = 0;
+	int sdp_min_guardband = 0;
+	int prefill_min_guardband;
+	int prefill_sagv_us;
+	int guardband;
+
+	skl_prefill_init_worst(&prefill_ctx, crtc_state);
+	prefill_sagv_us = display->sagv.block_time_us;
+	prefill_min_guardband =
+		skl_prefill_min_guardband(&prefill_ctx,
+					  crtc_state,
+					  prefill_sagv_us);
+
+	if (intel_crtc_has_dp_encoder(crtc_state)) {
+		psr_min_guardband = intel_psr_min_guardband(crtc_state);
+		sdp_min_guardband = intel_dp_sdp_min_guardband(crtc_state, true);
+	}
+
+	guardband = max(sdp_min_guardband, psr_min_guardband);
+
+	guardband = max(guardband, prefill_min_guardband);
+
+	return guardband;
+}
+
+static bool intel_vrr_use_optimized_guardband(const struct intel_crtc_state *crtc_state)
+{
+	struct intel_display *display = to_intel_display(crtc_state);
+
+	return intel_vrr_always_use_vrr_tg(display) || crtc_state->vrr.enable;
+}
+
 void intel_vrr_compute_guardband(struct intel_crtc_state *crtc_state)
 {
 	struct intel_display *display = to_intel_display(crtc_state);
 	struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode;
 	struct drm_display_mode *pipe_mode = &crtc_state->hw.pipe_mode;
+	int guardband;
 
 	if (!intel_vrr_possible(crtc_state))
 		return;
 
-	crtc_state->vrr.guardband = min(crtc_state->vrr.vmin - adjusted_mode->crtc_vdisplay,
-					intel_vrr_max_guardband(crtc_state));
+	if (intel_vrr_use_optimized_guardband(crtc_state))
+		guardband = intel_vrr_compute_optimized_guardband(crtc_state);
+	else
+		guardband = crtc_state->vrr.vmin - adjusted_mode->crtc_vdisplay;
+
+	crtc_state->vrr.guardband = min(guardband, intel_vrr_max_guardband(crtc_state));
 
 	if (intel_vrr_always_use_vrr_tg(display)) {
 		adjusted_mode->crtc_vblank_start  =
-- 
2.45.2


^ permalink raw reply related	[flat|nested] 14+ messages in thread

* Re: [PATCH 6/6] drm/i915/vrr: Use the min static optimized guardband
  2025-10-16  9:30 ` [PATCH 6/6] drm/i915/vrr: Use the min static optimized guardband Ankit Nautiyal
@ 2025-10-16 17:29   ` Ville Syrjälä
  0 siblings, 0 replies; 14+ messages in thread
From: Ville Syrjälä @ 2025-10-16 17:29 UTC (permalink / raw)
  To: Ankit Nautiyal; +Cc: intel-gfx, intel-xe

On Thu, Oct 16, 2025 at 03:00:09PM +0530, Ankit Nautiyal wrote:
> In the current VRR implementation, vrr.vmin and vrr.guardband are set such
> that they do not need to change when switching from fixed refresh rate to
> variable refresh rate. Specifically, vrr.guardband is always set to match
> the vblank length. This approach works for most cases, but not for LRR,
> where the guardband would need to change while the VRR timing generator is
> still active.
> 
> With the VRR TG always active, live updates to guardband are unsafe and not
> recommended. To ensure hardware safety, guardband was moved out of the
> !fastset block, meaning any change now requires a full modeset.
> This breaks seamless LRR switching, which was previously supported.
> 
> Since the problem arises from guardband being matched to the vblank length,
> solution is to use a minimal, sufficient static value, instead. So we use a
> static guardband defined during mode-set that fits within the smallest
> expected vblank and remains unchanged in case of features like LRR where
> vtotal changes. To compute this minimum guardband we take into account
> latencies/delays due to different features as mentioned in the Bspec.
> 
> Introduce a helper to compute the minimal sufficient guardband.
> On platforms where the VRR timing generator is always ON, we optimize the
> guardband regardless of whether the display is operating in fixed or
> variable refresh rate mode.
> On platforms where the VRR timing generator is not always ON, we optimize
> the guardband only when VRR is enabled.
> 
> Bspec: 70151
> Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_vrr.c | 50 +++++++++++++++++++++++-
>  1 file changed, 48 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_vrr.c b/drivers/gpu/drm/i915/display/intel_vrr.c
> index 597008a6c744..732e356e6fac 100644
> --- a/drivers/gpu/drm/i915/display/intel_vrr.c
> +++ b/drivers/gpu/drm/i915/display/intel_vrr.c
> @@ -6,12 +6,16 @@
>  
>  #include <drm/drm_print.h>
>  
> +#include "intel_crtc.h"
>  #include "intel_de.h"
>  #include "intel_display_regs.h"
>  #include "intel_display_types.h"
>  #include "intel_dp.h"
> +#include "intel_psr.h"
>  #include "intel_vrr.h"
>  #include "intel_vrr_regs.h"
> +#include "skl_prefill.h"
> +#include "skl_watermark.h"
>  
>  #define FIXED_POINT_PRECISION		100
>  #define CMRR_PRECISION_TOLERANCE	10
> @@ -433,17 +437,59 @@ intel_vrr_max_guardband(struct intel_crtc_state *crtc_state)
>  		   intel_vrr_max_vblank_guardband(crtc_state));
>  }
>  
> +static
> +int intel_vrr_compute_optimized_guardband(struct intel_crtc_state *crtc_state)
> +{
> +	struct intel_display *display = to_intel_display(crtc_state);
> +	struct skl_prefill_ctx prefill_ctx;
> +	int psr_min_guardband = 0;
> +	int sdp_min_guardband = 0;
> +	int prefill_min_guardband;
> +	int prefill_sagv_us;
> +	int guardband;
> +
> +	skl_prefill_init_worst(&prefill_ctx, crtc_state);
> +	prefill_sagv_us = display->sagv.block_time_us;

We want max(sagv, skl_wm_latency(1)) here or else we risk destroying
power savings.

> +	prefill_min_guardband =
> +		skl_prefill_min_guardband(&prefill_ctx,
> +					  crtc_state,
> +					  prefill_sagv_us);
> +
> +	if (intel_crtc_has_dp_encoder(crtc_state)) {
> +		psr_min_guardband = intel_psr_min_guardband(crtc_state);
> +		sdp_min_guardband = intel_dp_sdp_min_guardband(crtc_state, true);
> +	}
> +
> +	guardband = max(sdp_min_guardband, psr_min_guardband);
> +
> +	guardband = max(guardband, prefill_min_guardband);

All these temp variables seem rather pointless. Could just do

guardband = prefill_min_guardband(...);
if (dp)
 guardband = max(guardband, intel_psr_min_guardband(...));
 guardband = max(guardband, intel_dp_sdp_min_guardband(...));
}

I'm also pondering what to do about HDMI. A quick glance at the spec
says a lot of the inforframes are transmitted a line of two after
vsync, but the double buffering point is at delayed vblank. That to
me suggests that for HDMI we'd want to makes sure the start of
vsync happens after delayed vblank. For now it's probably safest to
simply not use the optimized guardband on HDMI. We can take another
stab at it on some later date.

> +
> +	return guardband;
> +}
> +
> +static bool intel_vrr_use_optimized_guardband(const struct intel_crtc_state *crtc_state)
> +{
> +	struct intel_display *display = to_intel_display(crtc_state);
> +
> +	return intel_vrr_always_use_vrr_tg(display) || crtc_state->vrr.enable;

I think we should do this in two separate patches:
 1. use optimzied guardband for intel_vrr_always_use_vrr_tg
 2. use if for vrr.enable as well

Easier to revert just 2. on its own if we have to.

> +}
> +
>  void intel_vrr_compute_guardband(struct intel_crtc_state *crtc_state)
>  {
>  	struct intel_display *display = to_intel_display(crtc_state);
>  	struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode;
>  	struct drm_display_mode *pipe_mode = &crtc_state->hw.pipe_mode;
> +	int guardband;
>  
>  	if (!intel_vrr_possible(crtc_state))
>  		return;
>  
> -	crtc_state->vrr.guardband = min(crtc_state->vrr.vmin - adjusted_mode->crtc_vdisplay,
> -					intel_vrr_max_guardband(crtc_state));
> +	if (intel_vrr_use_optimized_guardband(crtc_state))
> +		guardband = intel_vrr_compute_optimized_guardband(crtc_state);
> +	else
> +		guardband = crtc_state->vrr.vmin - adjusted_mode->crtc_vdisplay;
> +
> +	crtc_state->vrr.guardband = min(guardband, intel_vrr_max_guardband(crtc_state));
>  
>  	if (intel_vrr_always_use_vrr_tg(display)) {
>  		adjusted_mode->crtc_vblank_start  =
> -- 
> 2.45.2

-- 
Ville Syrjälä
Intel

^ permalink raw reply	[flat|nested] 14+ messages in thread

* ✗ CI.checkpatch: warning for Optimize vrr.guardband (rev2)
  2025-10-16  9:30 [PATCH 0/6] Optimize vrr.guardband Ankit Nautiyal
                   ` (5 preceding siblings ...)
  2025-10-16  9:30 ` [PATCH 6/6] drm/i915/vrr: Use the min static optimized guardband Ankit Nautiyal
@ 2025-10-16 10:31 ` Patchwork
  2025-10-16 10:32 ` ✓ CI.KUnit: success " Patchwork
                   ` (3 subsequent siblings)
  10 siblings, 0 replies; 14+ messages in thread
From: Patchwork @ 2025-10-16 10:31 UTC (permalink / raw)
  To: Ankit Nautiyal; +Cc: intel-xe

== Series Details ==

Series: Optimize vrr.guardband (rev2)
URL   : https://patchwork.freedesktop.org/series/155979/
State : warning

== Summary ==

+ KERNEL=/kernel
+ git clone https://gitlab.freedesktop.org/drm/maintainer-tools mt
Cloning into 'mt'...
warning: redirecting to https://gitlab.freedesktop.org/drm/maintainer-tools.git/
+ git -C mt rev-list -n1 origin/master
fbd08a78c3a3bb17964db2a326514c69c1dca660
+ cd /kernel
+ git config --global --add safe.directory /kernel
+ git log -n1
commit 4cfa51c7d17e794eef306a042123a1aa6aedf282
Author: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
Date:   Thu Oct 16 15:00:09 2025 +0530

    drm/i915/vrr: Use the min static optimized guardband
    
    In the current VRR implementation, vrr.vmin and vrr.guardband are set such
    that they do not need to change when switching from fixed refresh rate to
    variable refresh rate. Specifically, vrr.guardband is always set to match
    the vblank length. This approach works for most cases, but not for LRR,
    where the guardband would need to change while the VRR timing generator is
    still active.
    
    With the VRR TG always active, live updates to guardband are unsafe and not
    recommended. To ensure hardware safety, guardband was moved out of the
    !fastset block, meaning any change now requires a full modeset.
    This breaks seamless LRR switching, which was previously supported.
    
    Since the problem arises from guardband being matched to the vblank length,
    solution is to use a minimal, sufficient static value, instead. So we use a
    static guardband defined during mode-set that fits within the smallest
    expected vblank and remains unchanged in case of features like LRR where
    vtotal changes. To compute this minimum guardband we take into account
    latencies/delays due to different features as mentioned in the Bspec.
    
    Introduce a helper to compute the minimal sufficient guardband.
    On platforms where the VRR timing generator is always ON, we optimize the
    guardband regardless of whether the display is operating in fixed or
    variable refresh rate mode.
    On platforms where the VRR timing generator is not always ON, we optimize
    the guardband only when VRR is enabled.
    
    Bspec: 70151
    Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
+ /mt/dim checkpatch aaaff197c9186f4959c2bcb18035725188b950ed drm-intel
2c63e4cb372e drm/i915/vrr: prep patches for guardband optimization squashed
ac9598929244 drm/i915/prefill: Prefill latency calculations series squashed
-:204: WARNING:FILE_PATH_CHANGES: added, moved or deleted file(s), does MAINTAINERS need updating?
#204: 
new file mode 100644

total: 0 errors, 1 warnings, 0 checks, 751 lines checked
9de0678192e2 drm/i915/psr: Add helper to get min psr guardband
f535b2814c5c drm/i915/dp: Add helper to get min sdp guardband
5c92243f39b0 drm/i915/dp: Check if guardband can accommodate sdp latencies
4cfa51c7d17e drm/i915/vrr: Use the min static optimized guardband



^ permalink raw reply	[flat|nested] 14+ messages in thread

* ✓ CI.KUnit: success for Optimize vrr.guardband (rev2)
  2025-10-16  9:30 [PATCH 0/6] Optimize vrr.guardband Ankit Nautiyal
                   ` (6 preceding siblings ...)
  2025-10-16 10:31 ` ✗ CI.checkpatch: warning for Optimize vrr.guardband (rev2) Patchwork
@ 2025-10-16 10:32 ` Patchwork
  2025-10-16 10:50 ` ✗ CI.checksparse: warning " Patchwork
                   ` (2 subsequent siblings)
  10 siblings, 0 replies; 14+ messages in thread
From: Patchwork @ 2025-10-16 10:32 UTC (permalink / raw)
  To: Ankit Nautiyal; +Cc: intel-xe

== Series Details ==

Series: Optimize vrr.guardband (rev2)
URL   : https://patchwork.freedesktop.org/series/155979/
State : success

== Summary ==

+ trap cleanup EXIT
+ /kernel/tools/testing/kunit/kunit.py run --kunitconfig /kernel/drivers/gpu/drm/xe/.kunitconfig
[10:31:25] Configuring KUnit Kernel ...
Generating .config ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
[10:31:29] Building KUnit Kernel ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
Building with:
$ make all compile_commands.json scripts_gdb ARCH=um O=.kunit --jobs=25
[10:32:06] Starting KUnit Kernel (1/1)...
[10:32:06] ============================================================
Running tests with:
$ .kunit/linux kunit.enable=1 mem=1G console=tty kunit_shutdown=halt
[10:32:06] ================== guc_buf (11 subtests) ===================
[10:32:06] [PASSED] test_smallest
[10:32:06] [PASSED] test_largest
[10:32:06] [PASSED] test_granular
[10:32:06] [PASSED] test_unique
[10:32:06] [PASSED] test_overlap
[10:32:06] [PASSED] test_reusable
[10:32:06] [PASSED] test_too_big
[10:32:06] [PASSED] test_flush
[10:32:06] [PASSED] test_lookup
[10:32:06] [PASSED] test_data
[10:32:06] [PASSED] test_class
[10:32:06] ===================== [PASSED] guc_buf =====================
[10:32:06] =================== guc_dbm (7 subtests) ===================
[10:32:06] [PASSED] test_empty
[10:32:06] [PASSED] test_default
[10:32:06] ======================== test_size  ========================
[10:32:06] [PASSED] 4
[10:32:06] [PASSED] 8
[10:32:06] [PASSED] 32
[10:32:06] [PASSED] 256
[10:32:06] ==================== [PASSED] test_size ====================
[10:32:06] ======================= test_reuse  ========================
[10:32:06] [PASSED] 4
[10:32:06] [PASSED] 8
[10:32:06] [PASSED] 32
[10:32:06] [PASSED] 256
[10:32:06] =================== [PASSED] test_reuse ====================
[10:32:06] =================== test_range_overlap  ====================
[10:32:06] [PASSED] 4
[10:32:06] [PASSED] 8
[10:32:06] [PASSED] 32
[10:32:06] [PASSED] 256
[10:32:06] =============== [PASSED] test_range_overlap ================
[10:32:06] =================== test_range_compact  ====================
[10:32:06] [PASSED] 4
[10:32:06] [PASSED] 8
[10:32:06] [PASSED] 32
[10:32:06] [PASSED] 256
[10:32:06] =============== [PASSED] test_range_compact ================
[10:32:06] ==================== test_range_spare  =====================
[10:32:06] [PASSED] 4
[10:32:06] [PASSED] 8
[10:32:06] [PASSED] 32
[10:32:06] [PASSED] 256
[10:32:06] ================ [PASSED] test_range_spare =================
[10:32:06] ===================== [PASSED] guc_dbm =====================
[10:32:06] =================== guc_idm (6 subtests) ===================
[10:32:06] [PASSED] bad_init
[10:32:06] [PASSED] no_init
[10:32:06] [PASSED] init_fini
[10:32:06] [PASSED] check_used
[10:32:06] [PASSED] check_quota
[10:32:06] [PASSED] check_all
[10:32:06] ===================== [PASSED] guc_idm =====================
[10:32:06] ================== no_relay (3 subtests) ===================
[10:32:06] [PASSED] xe_drops_guc2pf_if_not_ready
[10:32:06] [PASSED] xe_drops_guc2vf_if_not_ready
[10:32:06] [PASSED] xe_rejects_send_if_not_ready
[10:32:06] ==================== [PASSED] no_relay =====================
[10:32:06] ================== pf_relay (14 subtests) ==================
[10:32:06] [PASSED] pf_rejects_guc2pf_too_short
[10:32:06] [PASSED] pf_rejects_guc2pf_too_long
[10:32:06] [PASSED] pf_rejects_guc2pf_no_payload
[10:32:06] [PASSED] pf_fails_no_payload
[10:32:06] [PASSED] pf_fails_bad_origin
[10:32:06] [PASSED] pf_fails_bad_type
[10:32:06] [PASSED] pf_txn_reports_error
[10:32:06] [PASSED] pf_txn_sends_pf2guc
[10:32:06] [PASSED] pf_sends_pf2guc
[10:32:06] [SKIPPED] pf_loopback_nop
[10:32:06] [SKIPPED] pf_loopback_echo
[10:32:06] [SKIPPED] pf_loopback_fail
[10:32:06] [SKIPPED] pf_loopback_busy
[10:32:06] [SKIPPED] pf_loopback_retry
[10:32:06] ==================== [PASSED] pf_relay =====================
[10:32:06] ================== vf_relay (3 subtests) ===================
[10:32:06] [PASSED] vf_rejects_guc2vf_too_short
[10:32:06] [PASSED] vf_rejects_guc2vf_too_long
[10:32:06] [PASSED] vf_rejects_guc2vf_no_payload
[10:32:06] ==================== [PASSED] vf_relay =====================
[10:32:06] ===================== lmtt (1 subtest) =====================
[10:32:06] ======================== test_ops  =========================
[10:32:06] [PASSED] 2-level
[10:32:06] [PASSED] multi-level
[10:32:06] ==================== [PASSED] test_ops =====================
[10:32:06] ====================== [PASSED] lmtt =======================
[10:32:06] ================= pf_service (11 subtests) =================
[10:32:06] [PASSED] pf_negotiate_any
[10:32:06] [PASSED] pf_negotiate_base_match
[10:32:06] [PASSED] pf_negotiate_base_newer
[10:32:06] [PASSED] pf_negotiate_base_next
[10:32:06] [SKIPPED] pf_negotiate_base_older
[10:32:06] [PASSED] pf_negotiate_base_prev
[10:32:06] [PASSED] pf_negotiate_latest_match
[10:32:06] [PASSED] pf_negotiate_latest_newer
[10:32:06] [PASSED] pf_negotiate_latest_next
[10:32:06] [SKIPPED] pf_negotiate_latest_older
[10:32:06] [SKIPPED] pf_negotiate_latest_prev
[10:32:06] =================== [PASSED] pf_service ====================
[10:32:06] ================= xe_guc_g2g (2 subtests) ==================
[10:32:06] ============== xe_live_guc_g2g_kunit_default  ==============
[10:32:06] ========= [SKIPPED] xe_live_guc_g2g_kunit_default ==========
[10:32:06] ============== xe_live_guc_g2g_kunit_allmem  ===============
[10:32:06] ========== [SKIPPED] xe_live_guc_g2g_kunit_allmem ==========
[10:32:06] =================== [SKIPPED] xe_guc_g2g ===================
[10:32:06] =================== xe_mocs (2 subtests) ===================
[10:32:06] ================ xe_live_mocs_kernel_kunit  ================
[10:32:06] =========== [SKIPPED] xe_live_mocs_kernel_kunit ============
[10:32:06] ================ xe_live_mocs_reset_kunit  =================
[10:32:06] ============ [SKIPPED] xe_live_mocs_reset_kunit ============
[10:32:06] ==================== [SKIPPED] xe_mocs =====================
[10:32:06] ================= xe_migrate (2 subtests) ==================
[10:32:06] ================= xe_migrate_sanity_kunit  =================
[10:32:06] ============ [SKIPPED] xe_migrate_sanity_kunit =============
[10:32:06] ================== xe_validate_ccs_kunit  ==================
[10:32:06] ============= [SKIPPED] xe_validate_ccs_kunit ==============
[10:32:06] =================== [SKIPPED] xe_migrate ===================
[10:32:06] ================== xe_dma_buf (1 subtest) ==================
[10:32:06] ==================== xe_dma_buf_kunit  =====================
[10:32:06] ================ [SKIPPED] xe_dma_buf_kunit ================
[10:32:06] =================== [SKIPPED] xe_dma_buf ===================
[10:32:06] ================= xe_bo_shrink (1 subtest) =================
[10:32:06] =================== xe_bo_shrink_kunit  ====================
[10:32:06] =============== [SKIPPED] xe_bo_shrink_kunit ===============
[10:32:06] ================== [SKIPPED] xe_bo_shrink ==================
[10:32:06] ==================== xe_bo (2 subtests) ====================
[10:32:06] ================== xe_ccs_migrate_kunit  ===================
[10:32:06] ============== [SKIPPED] xe_ccs_migrate_kunit ==============
[10:32:06] ==================== xe_bo_evict_kunit  ====================
[10:32:06] =============== [SKIPPED] xe_bo_evict_kunit ================
[10:32:06] ===================== [SKIPPED] xe_bo ======================
[10:32:06] ==================== args (11 subtests) ====================
[10:32:06] [PASSED] count_args_test
[10:32:06] [PASSED] call_args_example
[10:32:06] [PASSED] call_args_test
[10:32:06] [PASSED] drop_first_arg_example
[10:32:06] [PASSED] drop_first_arg_test
[10:32:06] [PASSED] first_arg_example
[10:32:06] [PASSED] first_arg_test
[10:32:06] [PASSED] last_arg_example
[10:32:06] [PASSED] last_arg_test
[10:32:06] [PASSED] pick_arg_example
[10:32:06] [PASSED] sep_comma_example
[10:32:06] ====================== [PASSED] args =======================
[10:32:06] =================== xe_pci (3 subtests) ====================
[10:32:06] ==================== check_graphics_ip  ====================
[10:32:06] [PASSED] 12.00 Xe_LP
[10:32:06] [PASSED] 12.10 Xe_LP+
[10:32:06] [PASSED] 12.55 Xe_HPG
[10:32:06] [PASSED] 12.60 Xe_HPC
[10:32:06] [PASSED] 12.70 Xe_LPG
[10:32:06] [PASSED] 12.71 Xe_LPG
[10:32:06] [PASSED] 12.74 Xe_LPG+
[10:32:06] [PASSED] 20.01 Xe2_HPG
[10:32:06] [PASSED] 20.02 Xe2_HPG
[10:32:06] [PASSED] 20.04 Xe2_LPG
[10:32:06] [PASSED] 30.00 Xe3_LPG
[10:32:06] [PASSED] 30.01 Xe3_LPG
[10:32:06] [PASSED] 30.03 Xe3_LPG
[10:32:06] ================ [PASSED] check_graphics_ip ================
[10:32:06] ===================== check_media_ip  ======================
[10:32:06] [PASSED] 12.00 Xe_M
[10:32:06] [PASSED] 12.55 Xe_HPM
[10:32:06] [PASSED] 13.00 Xe_LPM+
[10:32:06] [PASSED] 13.01 Xe2_HPM
[10:32:06] [PASSED] 20.00 Xe2_LPM
[10:32:06] [PASSED] 30.00 Xe3_LPM
[10:32:06] [PASSED] 30.02 Xe3_LPM
[10:32:06] ================= [PASSED] check_media_ip ==================
[10:32:06] ================= check_platform_gt_count  =================
[10:32:06] [PASSED] 0x9A60 (TIGERLAKE)
[10:32:06] [PASSED] 0x9A68 (TIGERLAKE)
[10:32:06] [PASSED] 0x9A70 (TIGERLAKE)
[10:32:06] [PASSED] 0x9A40 (TIGERLAKE)
[10:32:06] [PASSED] 0x9A49 (TIGERLAKE)
[10:32:06] [PASSED] 0x9A59 (TIGERLAKE)
[10:32:06] [PASSED] 0x9A78 (TIGERLAKE)
[10:32:06] [PASSED] 0x9AC0 (TIGERLAKE)
[10:32:06] [PASSED] 0x9AC9 (TIGERLAKE)
[10:32:06] [PASSED] 0x9AD9 (TIGERLAKE)
[10:32:06] [PASSED] 0x9AF8 (TIGERLAKE)
[10:32:06] [PASSED] 0x4C80 (ROCKETLAKE)
[10:32:06] [PASSED] 0x4C8A (ROCKETLAKE)
[10:32:06] [PASSED] 0x4C8B (ROCKETLAKE)
[10:32:06] [PASSED] 0x4C8C (ROCKETLAKE)
[10:32:06] [PASSED] 0x4C90 (ROCKETLAKE)
[10:32:06] [PASSED] 0x4C9A (ROCKETLAKE)
[10:32:06] [PASSED] 0x4680 (ALDERLAKE_S)
[10:32:06] [PASSED] 0x4682 (ALDERLAKE_S)
[10:32:06] [PASSED] 0x4688 (ALDERLAKE_S)
[10:32:06] [PASSED] 0x468A (ALDERLAKE_S)
[10:32:06] [PASSED] 0x468B (ALDERLAKE_S)
[10:32:06] [PASSED] 0x4690 (ALDERLAKE_S)
[10:32:06] [PASSED] 0x4692 (ALDERLAKE_S)
[10:32:06] [PASSED] 0x4693 (ALDERLAKE_S)
[10:32:06] [PASSED] 0x46A0 (ALDERLAKE_P)
[10:32:06] [PASSED] 0x46A1 (ALDERLAKE_P)
[10:32:06] [PASSED] 0x46A2 (ALDERLAKE_P)
[10:32:06] [PASSED] 0x46A3 (ALDERLAKE_P)
[10:32:06] [PASSED] 0x46A6 (ALDERLAKE_P)
[10:32:06] [PASSED] 0x46A8 (ALDERLAKE_P)
[10:32:06] [PASSED] 0x46AA (ALDERLAKE_P)
[10:32:06] [PASSED] 0x462A (ALDERLAKE_P)
[10:32:06] [PASSED] 0x4626 (ALDERLAKE_P)
[10:32:06] [PASSED] 0x4628 (ALDERLAKE_P)
[10:32:06] [PASSED] 0x46B0 (ALDERLAKE_P)
[10:32:06] [PASSED] 0x46B1 (ALDERLAKE_P)
[10:32:06] [PASSED] 0x46B2 (ALDERLAKE_P)
[10:32:06] [PASSED] 0x46B3 (ALDERLAKE_P)
[10:32:06] [PASSED] 0x46C0 (ALDERLAKE_P)
[10:32:06] [PASSED] 0x46C1 (ALDERLAKE_P)
[10:32:06] [PASSED] 0x46C2 (ALDERLAKE_P)
[10:32:06] [PASSED] 0x46C3 (ALDERLAKE_P)
[10:32:06] [PASSED] 0x46D0 (ALDERLAKE_N)
[10:32:06] [PASSED] 0x46D1 (ALDERLAKE_N)
[10:32:06] [PASSED] 0x46D2 (ALDERLAKE_N)
[10:32:06] [PASSED] 0x46D3 (ALDERLAKE_N)
[10:32:06] [PASSED] 0x46D4 (ALDERLAKE_N)
[10:32:06] [PASSED] 0xA721 (ALDERLAKE_P)
[10:32:06] [PASSED] 0xA7A1 (ALDERLAKE_P)
[10:32:06] [PASSED] 0xA7A9 (ALDERLAKE_P)
[10:32:06] [PASSED] 0xA7AC (ALDERLAKE_P)
[10:32:06] [PASSED] 0xA7AD (ALDERLAKE_P)
[10:32:06] [PASSED] 0xA720 (ALDERLAKE_P)
[10:32:06] [PASSED] 0xA7A0 (ALDERLAKE_P)
[10:32:06] [PASSED] 0xA7A8 (ALDERLAKE_P)
[10:32:06] [PASSED] 0xA7AA (ALDERLAKE_P)
[10:32:06] [PASSED] 0xA7AB (ALDERLAKE_P)
[10:32:06] [PASSED] 0xA780 (ALDERLAKE_S)
[10:32:06] [PASSED] 0xA781 (ALDERLAKE_S)
[10:32:06] [PASSED] 0xA782 (ALDERLAKE_S)
[10:32:06] [PASSED] 0xA783 (ALDERLAKE_S)
[10:32:06] [PASSED] 0xA788 (ALDERLAKE_S)
[10:32:06] [PASSED] 0xA789 (ALDERLAKE_S)
[10:32:06] [PASSED] 0xA78A (ALDERLAKE_S)
[10:32:06] [PASSED] 0xA78B (ALDERLAKE_S)
[10:32:06] [PASSED] 0x4905 (DG1)
[10:32:06] [PASSED] 0x4906 (DG1)
[10:32:06] [PASSED] 0x4907 (DG1)
[10:32:06] [PASSED] 0x4908 (DG1)
[10:32:06] [PASSED] 0x4909 (DG1)
[10:32:06] [PASSED] 0x56C0 (DG2)
[10:32:06] [PASSED] 0x56C2 (DG2)
[10:32:06] [PASSED] 0x56C1 (DG2)
[10:32:06] [PASSED] 0x7D51 (METEORLAKE)
[10:32:06] [PASSED] 0x7DD1 (METEORLAKE)
[10:32:06] [PASSED] 0x7D41 (METEORLAKE)
[10:32:06] [PASSED] 0x7D67 (METEORLAKE)
[10:32:06] [PASSED] 0xB640 (METEORLAKE)
[10:32:06] [PASSED] 0x56A0 (DG2)
[10:32:06] [PASSED] 0x56A1 (DG2)
[10:32:06] [PASSED] 0x56A2 (DG2)
[10:32:06] [PASSED] 0x56BE (DG2)
[10:32:06] [PASSED] 0x56BF (DG2)
[10:32:06] [PASSED] 0x5690 (DG2)
[10:32:06] [PASSED] 0x5691 (DG2)
[10:32:06] [PASSED] 0x5692 (DG2)
[10:32:06] [PASSED] 0x56A5 (DG2)
[10:32:06] [PASSED] 0x56A6 (DG2)
[10:32:06] [PASSED] 0x56B0 (DG2)
[10:32:06] [PASSED] 0x56B1 (DG2)
[10:32:06] [PASSED] 0x56BA (DG2)
[10:32:06] [PASSED] 0x56BB (DG2)
[10:32:06] [PASSED] 0x56BC (DG2)
[10:32:06] [PASSED] 0x56BD (DG2)
[10:32:06] [PASSED] 0x5693 (DG2)
[10:32:06] [PASSED] 0x5694 (DG2)
[10:32:06] [PASSED] 0x5695 (DG2)
[10:32:06] [PASSED] 0x56A3 (DG2)
[10:32:06] [PASSED] 0x56A4 (DG2)
[10:32:06] [PASSED] 0x56B2 (DG2)
[10:32:06] [PASSED] 0x56B3 (DG2)
[10:32:06] [PASSED] 0x5696 (DG2)
[10:32:06] [PASSED] 0x5697 (DG2)
[10:32:06] [PASSED] 0xB69 (PVC)
[10:32:06] [PASSED] 0xB6E (PVC)
[10:32:06] [PASSED] 0xBD4 (PVC)
[10:32:06] [PASSED] 0xBD5 (PVC)
[10:32:06] [PASSED] 0xBD6 (PVC)
[10:32:06] [PASSED] 0xBD7 (PVC)
[10:32:06] [PASSED] 0xBD8 (PVC)
[10:32:06] [PASSED] 0xBD9 (PVC)
[10:32:06] [PASSED] 0xBDA (PVC)
[10:32:06] [PASSED] 0xBDB (PVC)
[10:32:06] [PASSED] 0xBE0 (PVC)
[10:32:06] [PASSED] 0xBE1 (PVC)
[10:32:06] [PASSED] 0xBE5 (PVC)
[10:32:06] [PASSED] 0x7D40 (METEORLAKE)
[10:32:06] [PASSED] 0x7D45 (METEORLAKE)
[10:32:06] [PASSED] 0x7D55 (METEORLAKE)
[10:32:06] [PASSED] 0x7D60 (METEORLAKE)
[10:32:06] [PASSED] 0x7DD5 (METEORLAKE)
[10:32:06] [PASSED] 0x6420 (LUNARLAKE)
[10:32:06] [PASSED] 0x64A0 (LUNARLAKE)
[10:32:06] [PASSED] 0x64B0 (LUNARLAKE)
[10:32:06] [PASSED] 0xE202 (BATTLEMAGE)
[10:32:06] [PASSED] 0xE209 (BATTLEMAGE)
[10:32:06] [PASSED] 0xE20B (BATTLEMAGE)
[10:32:06] [PASSED] 0xE20C (BATTLEMAGE)
[10:32:06] [PASSED] 0xE20D (BATTLEMAGE)
[10:32:06] [PASSED] 0xE210 (BATTLEMAGE)
[10:32:06] [PASSED] 0xE211 (BATTLEMAGE)
[10:32:06] [PASSED] 0xE212 (BATTLEMAGE)
[10:32:06] [PASSED] 0xE216 (BATTLEMAGE)
[10:32:06] [PASSED] 0xE220 (BATTLEMAGE)
[10:32:06] [PASSED] 0xE221 (BATTLEMAGE)
[10:32:06] [PASSED] 0xE222 (BATTLEMAGE)
[10:32:06] [PASSED] 0xE223 (BATTLEMAGE)
[10:32:06] [PASSED] 0xB080 (PANTHERLAKE)
[10:32:06] [PASSED] 0xB081 (PANTHERLAKE)
[10:32:06] [PASSED] 0xB082 (PANTHERLAKE)
[10:32:06] [PASSED] 0xB083 (PANTHERLAKE)
[10:32:06] [PASSED] 0xB084 (PANTHERLAKE)
[10:32:06] [PASSED] 0xB085 (PANTHERLAKE)
[10:32:06] [PASSED] 0xB086 (PANTHERLAKE)
[10:32:06] [PASSED] 0xB087 (PANTHERLAKE)
[10:32:06] [PASSED] 0xB08F (PANTHERLAKE)
[10:32:06] [PASSED] 0xB090 (PANTHERLAKE)
[10:32:06] [PASSED] 0xB0A0 (PANTHERLAKE)
[10:32:06] [PASSED] 0xB0B0 (PANTHERLAKE)
[10:32:06] [PASSED] 0xFD80 (PANTHERLAKE)
[10:32:06] [PASSED] 0xFD81 (PANTHERLAKE)
[10:32:06] ============= [PASSED] check_platform_gt_count =============
[10:32:06] ===================== [PASSED] xe_pci ======================
[10:32:06] =================== xe_rtp (2 subtests) ====================
[10:32:06] =============== xe_rtp_process_to_sr_tests  ================
[10:32:06] [PASSED] coalesce-same-reg
[10:32:06] [PASSED] no-match-no-add
[10:32:06] [PASSED] match-or
[10:32:06] [PASSED] match-or-xfail
[10:32:06] [PASSED] no-match-no-add-multiple-rules
[10:32:06] [PASSED] two-regs-two-entries
[10:32:06] [PASSED] clr-one-set-other
[10:32:06] [PASSED] set-field
[10:32:06] [PASSED] conflict-duplicate
[10:32:06] [PASSED] conflict-not-disjoint
[10:32:06] [PASSED] conflict-reg-type
[10:32:06] =========== [PASSED] xe_rtp_process_to_sr_tests ============
[10:32:06] ================== xe_rtp_process_tests  ===================
[10:32:06] [PASSED] active1
[10:32:06] [PASSED] active2
[10:32:06] [PASSED] active-inactive
[10:32:06] [PASSED] inactive-active
[10:32:06] [PASSED] inactive-1st_or_active-inactive
[10:32:06] [PASSED] inactive-2nd_or_active-inactive
[10:32:06] [PASSED] inactive-last_or_active-inactive
[10:32:06] [PASSED] inactive-no_or_active-inactive
[10:32:06] ============== [PASSED] xe_rtp_process_tests ===============
[10:32:06] ===================== [PASSED] xe_rtp ======================
[10:32:06] ==================== xe_wa (1 subtest) =====================
[10:32:06] ======================== xe_wa_gt  =========================
[10:32:06] [PASSED] TIGERLAKE B0
[10:32:06] [PASSED] DG1 A0
[10:32:06] [PASSED] DG1 B0
[10:32:06] [PASSED] ALDERLAKE_S A0
[10:32:06] [PASSED] ALDERLAKE_S B0
stty: 'standard input': Inappropriate ioctl for device
[10:32:06] [PASSED] ALDERLAKE_S C0
[10:32:06] [PASSED] ALDERLAKE_S D0
[10:32:06] [PASSED] ALDERLAKE_P A0
[10:32:06] [PASSED] ALDERLAKE_P B0
[10:32:06] [PASSED] ALDERLAKE_P C0
[10:32:06] [PASSED] ALDERLAKE_S RPLS D0
[10:32:06] [PASSED] ALDERLAKE_P RPLU E0
[10:32:06] [PASSED] DG2 G10 C0
[10:32:06] [PASSED] DG2 G11 B1
[10:32:06] [PASSED] DG2 G12 A1
[10:32:06] [PASSED] METEORLAKE 12.70(Xe_LPG) A0 13.00(Xe_LPM+) A0
[10:32:06] [PASSED] METEORLAKE 12.71(Xe_LPG) A0 13.00(Xe_LPM+) A0
[10:32:06] [PASSED] METEORLAKE 12.74(Xe_LPG+) A0 13.00(Xe_LPM+) A0
[10:32:06] [PASSED] LUNARLAKE 20.04(Xe2_LPG) A0 20.00(Xe2_LPM) A0
[10:32:06] [PASSED] LUNARLAKE 20.04(Xe2_LPG) B0 20.00(Xe2_LPM) A0
[10:32:06] [PASSED] BATTLEMAGE 20.01(Xe2_HPG) A0 13.01(Xe2_HPM) A1
[10:32:06] [PASSED] PANTHERLAKE 30.00(Xe3_LPG) A0 30.00(Xe3_LPM) A0
[10:32:06] ==================== [PASSED] xe_wa_gt =====================
[10:32:06] ====================== [PASSED] xe_wa ======================
[10:32:06] ============================================================
[10:32:06] Testing complete. Ran 306 tests: passed: 288, skipped: 18
[10:32:07] Elapsed time: 41.813s total, 4.321s configuring, 37.124s building, 0.333s running

+ /kernel/tools/testing/kunit/kunit.py run --kunitconfig /kernel/drivers/gpu/drm/tests/.kunitconfig
[10:32:07] Configuring KUnit Kernel ...
Regenerating .config ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
[10:32:08] Building KUnit Kernel ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
Building with:
$ make all compile_commands.json scripts_gdb ARCH=um O=.kunit --jobs=25
[10:32:38] Starting KUnit Kernel (1/1)...
[10:32:38] ============================================================
Running tests with:
$ .kunit/linux kunit.enable=1 mem=1G console=tty kunit_shutdown=halt
[10:32:38] ============ drm_test_pick_cmdline (2 subtests) ============
[10:32:38] [PASSED] drm_test_pick_cmdline_res_1920_1080_60
[10:32:38] =============== drm_test_pick_cmdline_named  ===============
[10:32:38] [PASSED] NTSC
[10:32:38] [PASSED] NTSC-J
[10:32:38] [PASSED] PAL
[10:32:38] [PASSED] PAL-M
[10:32:38] =========== [PASSED] drm_test_pick_cmdline_named ===========
[10:32:38] ============== [PASSED] drm_test_pick_cmdline ==============
[10:32:38] == drm_test_atomic_get_connector_for_encoder (1 subtest) ===
[10:32:38] [PASSED] drm_test_drm_atomic_get_connector_for_encoder
[10:32:38] ==== [PASSED] drm_test_atomic_get_connector_for_encoder ====
[10:32:38] =========== drm_validate_clone_mode (2 subtests) ===========
[10:32:38] ============== drm_test_check_in_clone_mode  ===============
[10:32:38] [PASSED] in_clone_mode
[10:32:38] [PASSED] not_in_clone_mode
[10:32:38] ========== [PASSED] drm_test_check_in_clone_mode ===========
[10:32:38] =============== drm_test_check_valid_clones  ===============
[10:32:38] [PASSED] not_in_clone_mode
[10:32:38] [PASSED] valid_clone
[10:32:38] [PASSED] invalid_clone
[10:32:38] =========== [PASSED] drm_test_check_valid_clones ===========
[10:32:38] ============= [PASSED] drm_validate_clone_mode =============
[10:32:38] ============= drm_validate_modeset (1 subtest) =============
[10:32:38] [PASSED] drm_test_check_connector_changed_modeset
[10:32:38] ============== [PASSED] drm_validate_modeset ===============
[10:32:38] ====== drm_test_bridge_get_current_state (2 subtests) ======
[10:32:38] [PASSED] drm_test_drm_bridge_get_current_state_atomic
[10:32:38] [PASSED] drm_test_drm_bridge_get_current_state_legacy
[10:32:38] ======== [PASSED] drm_test_bridge_get_current_state ========
[10:32:38] ====== drm_test_bridge_helper_reset_crtc (3 subtests) ======
[10:32:38] [PASSED] drm_test_drm_bridge_helper_reset_crtc_atomic
[10:32:38] [PASSED] drm_test_drm_bridge_helper_reset_crtc_atomic_disabled
[10:32:38] [PASSED] drm_test_drm_bridge_helper_reset_crtc_legacy
[10:32:38] ======== [PASSED] drm_test_bridge_helper_reset_crtc ========
[10:32:38] ============== drm_bridge_alloc (2 subtests) ===============
[10:32:38] [PASSED] drm_test_drm_bridge_alloc_basic
[10:32:38] [PASSED] drm_test_drm_bridge_alloc_get_put
[10:32:38] ================ [PASSED] drm_bridge_alloc =================
[10:32:38] ================== drm_buddy (8 subtests) ==================
[10:32:38] [PASSED] drm_test_buddy_alloc_limit
[10:32:38] [PASSED] drm_test_buddy_alloc_optimistic
[10:32:38] [PASSED] drm_test_buddy_alloc_pessimistic
[10:32:38] [PASSED] drm_test_buddy_alloc_pathological
[10:32:38] [PASSED] drm_test_buddy_alloc_contiguous
[10:32:38] [PASSED] drm_test_buddy_alloc_clear
[10:32:38] [PASSED] drm_test_buddy_alloc_range_bias
[10:32:38] [PASSED] drm_test_buddy_fragmentation_performance
[10:32:38] ==================== [PASSED] drm_buddy ====================
[10:32:38] ============= drm_cmdline_parser (40 subtests) =============
[10:32:38] [PASSED] drm_test_cmdline_force_d_only
[10:32:38] [PASSED] drm_test_cmdline_force_D_only_dvi
[10:32:38] [PASSED] drm_test_cmdline_force_D_only_hdmi
[10:32:38] [PASSED] drm_test_cmdline_force_D_only_not_digital
[10:32:38] [PASSED] drm_test_cmdline_force_e_only
[10:32:38] [PASSED] drm_test_cmdline_res
[10:32:38] [PASSED] drm_test_cmdline_res_vesa
[10:32:38] [PASSED] drm_test_cmdline_res_vesa_rblank
[10:32:38] [PASSED] drm_test_cmdline_res_rblank
[10:32:38] [PASSED] drm_test_cmdline_res_bpp
[10:32:38] [PASSED] drm_test_cmdline_res_refresh
[10:32:38] [PASSED] drm_test_cmdline_res_bpp_refresh
[10:32:38] [PASSED] drm_test_cmdline_res_bpp_refresh_interlaced
[10:32:38] [PASSED] drm_test_cmdline_res_bpp_refresh_margins
[10:32:38] [PASSED] drm_test_cmdline_res_bpp_refresh_force_off
[10:32:38] [PASSED] drm_test_cmdline_res_bpp_refresh_force_on
[10:32:38] [PASSED] drm_test_cmdline_res_bpp_refresh_force_on_analog
[10:32:38] [PASSED] drm_test_cmdline_res_bpp_refresh_force_on_digital
[10:32:38] [PASSED] drm_test_cmdline_res_bpp_refresh_interlaced_margins_force_on
[10:32:38] [PASSED] drm_test_cmdline_res_margins_force_on
[10:32:38] [PASSED] drm_test_cmdline_res_vesa_margins
[10:32:38] [PASSED] drm_test_cmdline_name
[10:32:38] [PASSED] drm_test_cmdline_name_bpp
[10:32:38] [PASSED] drm_test_cmdline_name_option
[10:32:38] [PASSED] drm_test_cmdline_name_bpp_option
[10:32:38] [PASSED] drm_test_cmdline_rotate_0
[10:32:38] [PASSED] drm_test_cmdline_rotate_90
[10:32:38] [PASSED] drm_test_cmdline_rotate_180
[10:32:38] [PASSED] drm_test_cmdline_rotate_270
[10:32:38] [PASSED] drm_test_cmdline_hmirror
[10:32:38] [PASSED] drm_test_cmdline_vmirror
[10:32:38] [PASSED] drm_test_cmdline_margin_options
[10:32:38] [PASSED] drm_test_cmdline_multiple_options
[10:32:38] [PASSED] drm_test_cmdline_bpp_extra_and_option
[10:32:38] [PASSED] drm_test_cmdline_extra_and_option
[10:32:38] [PASSED] drm_test_cmdline_freestanding_options
[10:32:38] [PASSED] drm_test_cmdline_freestanding_force_e_and_options
[10:32:38] [PASSED] drm_test_cmdline_panel_orientation
[10:32:38] ================ drm_test_cmdline_invalid  =================
[10:32:38] [PASSED] margin_only
[10:32:38] [PASSED] interlace_only
[10:32:38] [PASSED] res_missing_x
[10:32:38] [PASSED] res_missing_y
[10:32:38] [PASSED] res_bad_y
[10:32:38] [PASSED] res_missing_y_bpp
[10:32:38] [PASSED] res_bad_bpp
[10:32:38] [PASSED] res_bad_refresh
[10:32:38] [PASSED] res_bpp_refresh_force_on_off
[10:32:38] [PASSED] res_invalid_mode
[10:32:38] [PASSED] res_bpp_wrong_place_mode
[10:32:38] [PASSED] name_bpp_refresh
[10:32:38] [PASSED] name_refresh
[10:32:38] [PASSED] name_refresh_wrong_mode
[10:32:38] [PASSED] name_refresh_invalid_mode
[10:32:38] [PASSED] rotate_multiple
[10:32:38] [PASSED] rotate_invalid_val
[10:32:38] [PASSED] rotate_truncated
[10:32:38] [PASSED] invalid_option
[10:32:38] [PASSED] invalid_tv_option
[10:32:38] [PASSED] truncated_tv_option
[10:32:38] ============ [PASSED] drm_test_cmdline_invalid =============
[10:32:38] =============== drm_test_cmdline_tv_options  ===============
[10:32:38] [PASSED] NTSC
[10:32:38] [PASSED] NTSC_443
[10:32:38] [PASSED] NTSC_J
[10:32:38] [PASSED] PAL
[10:32:38] [PASSED] PAL_M
[10:32:38] [PASSED] PAL_N
[10:32:38] [PASSED] SECAM
[10:32:38] [PASSED] MONO_525
[10:32:38] [PASSED] MONO_625
[10:32:38] =========== [PASSED] drm_test_cmdline_tv_options ===========
[10:32:38] =============== [PASSED] drm_cmdline_parser ================
[10:32:38] ========== drmm_connector_hdmi_init (20 subtests) ==========
[10:32:38] [PASSED] drm_test_connector_hdmi_init_valid
[10:32:38] [PASSED] drm_test_connector_hdmi_init_bpc_8
[10:32:38] [PASSED] drm_test_connector_hdmi_init_bpc_10
[10:32:38] [PASSED] drm_test_connector_hdmi_init_bpc_12
[10:32:38] [PASSED] drm_test_connector_hdmi_init_bpc_invalid
[10:32:38] [PASSED] drm_test_connector_hdmi_init_bpc_null
[10:32:38] [PASSED] drm_test_connector_hdmi_init_formats_empty
[10:32:38] [PASSED] drm_test_connector_hdmi_init_formats_no_rgb
[10:32:38] === drm_test_connector_hdmi_init_formats_yuv420_allowed  ===
[10:32:38] [PASSED] supported_formats=0x9 yuv420_allowed=1
[10:32:38] [PASSED] supported_formats=0x9 yuv420_allowed=0
[10:32:38] [PASSED] supported_formats=0x3 yuv420_allowed=1
[10:32:38] [PASSED] supported_formats=0x3 yuv420_allowed=0
[10:32:38] === [PASSED] drm_test_connector_hdmi_init_formats_yuv420_allowed ===
[10:32:38] [PASSED] drm_test_connector_hdmi_init_null_ddc
[10:32:38] [PASSED] drm_test_connector_hdmi_init_null_product
[10:32:38] [PASSED] drm_test_connector_hdmi_init_null_vendor
[10:32:38] [PASSED] drm_test_connector_hdmi_init_product_length_exact
[10:32:38] [PASSED] drm_test_connector_hdmi_init_product_length_too_long
[10:32:38] [PASSED] drm_test_connector_hdmi_init_product_valid
[10:32:38] [PASSED] drm_test_connector_hdmi_init_vendor_length_exact
[10:32:38] [PASSED] drm_test_connector_hdmi_init_vendor_length_too_long
[10:32:38] [PASSED] drm_test_connector_hdmi_init_vendor_valid
[10:32:38] ========= drm_test_connector_hdmi_init_type_valid  =========
[10:32:38] [PASSED] HDMI-A
[10:32:38] [PASSED] HDMI-B
[10:32:38] ===== [PASSED] drm_test_connector_hdmi_init_type_valid =====
[10:32:38] ======== drm_test_connector_hdmi_init_type_invalid  ========
[10:32:38] [PASSED] Unknown
[10:32:38] [PASSED] VGA
[10:32:38] [PASSED] DVI-I
[10:32:38] [PASSED] DVI-D
[10:32:38] [PASSED] DVI-A
[10:32:38] [PASSED] Composite
[10:32:38] [PASSED] SVIDEO
[10:32:38] [PASSED] LVDS
[10:32:38] [PASSED] Component
[10:32:38] [PASSED] DIN
[10:32:38] [PASSED] DP
[10:32:38] [PASSED] TV
[10:32:38] [PASSED] eDP
[10:32:38] [PASSED] Virtual
[10:32:38] [PASSED] DSI
[10:32:38] [PASSED] DPI
[10:32:38] [PASSED] Writeback
[10:32:38] [PASSED] SPI
[10:32:38] [PASSED] USB
[10:32:38] ==== [PASSED] drm_test_connector_hdmi_init_type_invalid ====
[10:32:38] ============ [PASSED] drmm_connector_hdmi_init =============
[10:32:38] ============= drmm_connector_init (3 subtests) =============
[10:32:38] [PASSED] drm_test_drmm_connector_init
[10:32:38] [PASSED] drm_test_drmm_connector_init_null_ddc
[10:32:38] ========= drm_test_drmm_connector_init_type_valid  =========
[10:32:38] [PASSED] Unknown
[10:32:38] [PASSED] VGA
[10:32:38] [PASSED] DVI-I
[10:32:38] [PASSED] DVI-D
[10:32:38] [PASSED] DVI-A
[10:32:38] [PASSED] Composite
[10:32:38] [PASSED] SVIDEO
[10:32:38] [PASSED] LVDS
[10:32:38] [PASSED] Component
[10:32:38] [PASSED] DIN
[10:32:38] [PASSED] DP
[10:32:38] [PASSED] HDMI-A
[10:32:38] [PASSED] HDMI-B
[10:32:38] [PASSED] TV
[10:32:38] [PASSED] eDP
[10:32:38] [PASSED] Virtual
[10:32:38] [PASSED] DSI
[10:32:38] [PASSED] DPI
[10:32:38] [PASSED] Writeback
[10:32:38] [PASSED] SPI
[10:32:38] [PASSED] USB
[10:32:38] ===== [PASSED] drm_test_drmm_connector_init_type_valid =====
[10:32:38] =============== [PASSED] drmm_connector_init ===============
[10:32:38] ========= drm_connector_dynamic_init (6 subtests) ==========
[10:32:38] [PASSED] drm_test_drm_connector_dynamic_init
[10:32:38] [PASSED] drm_test_drm_connector_dynamic_init_null_ddc
[10:32:38] [PASSED] drm_test_drm_connector_dynamic_init_not_added
[10:32:38] [PASSED] drm_test_drm_connector_dynamic_init_properties
[10:32:38] ===== drm_test_drm_connector_dynamic_init_type_valid  ======
[10:32:38] [PASSED] Unknown
[10:32:38] [PASSED] VGA
[10:32:38] [PASSED] DVI-I
[10:32:38] [PASSED] DVI-D
[10:32:38] [PASSED] DVI-A
[10:32:38] [PASSED] Composite
[10:32:38] [PASSED] SVIDEO
[10:32:38] [PASSED] LVDS
[10:32:38] [PASSED] Component
[10:32:38] [PASSED] DIN
[10:32:38] [PASSED] DP
[10:32:38] [PASSED] HDMI-A
[10:32:38] [PASSED] HDMI-B
[10:32:38] [PASSED] TV
[10:32:38] [PASSED] eDP
[10:32:38] [PASSED] Virtual
[10:32:38] [PASSED] DSI
[10:32:38] [PASSED] DPI
[10:32:38] [PASSED] Writeback
[10:32:38] [PASSED] SPI
[10:32:38] [PASSED] USB
[10:32:38] = [PASSED] drm_test_drm_connector_dynamic_init_type_valid ==
[10:32:38] ======== drm_test_drm_connector_dynamic_init_name  =========
[10:32:38] [PASSED] Unknown
[10:32:38] [PASSED] VGA
[10:32:38] [PASSED] DVI-I
[10:32:38] [PASSED] DVI-D
[10:32:38] [PASSED] DVI-A
[10:32:38] [PASSED] Composite
[10:32:38] [PASSED] SVIDEO
[10:32:38] [PASSED] LVDS
[10:32:38] [PASSED] Component
[10:32:38] [PASSED] DIN
[10:32:38] [PASSED] DP
[10:32:38] [PASSED] HDMI-A
[10:32:38] [PASSED] HDMI-B
[10:32:38] [PASSED] TV
[10:32:38] [PASSED] eDP
[10:32:38] [PASSED] Virtual
[10:32:38] [PASSED] DSI
[10:32:38] [PASSED] DPI
[10:32:38] [PASSED] Writeback
[10:32:38] [PASSED] SPI
[10:32:38] [PASSED] USB
[10:32:38] ==== [PASSED] drm_test_drm_connector_dynamic_init_name =====
[10:32:38] =========== [PASSED] drm_connector_dynamic_init ============
[10:32:38] ==== drm_connector_dynamic_register_early (4 subtests) =====
[10:32:38] [PASSED] drm_test_drm_connector_dynamic_register_early_on_list
[10:32:38] [PASSED] drm_test_drm_connector_dynamic_register_early_defer
[10:32:38] [PASSED] drm_test_drm_connector_dynamic_register_early_no_init
[10:32:38] [PASSED] drm_test_drm_connector_dynamic_register_early_no_mode_object
[10:32:38] ====== [PASSED] drm_connector_dynamic_register_early =======
[10:32:38] ======= drm_connector_dynamic_register (7 subtests) ========
[10:32:38] [PASSED] drm_test_drm_connector_dynamic_register_on_list
[10:32:38] [PASSED] drm_test_drm_connector_dynamic_register_no_defer
[10:32:38] [PASSED] drm_test_drm_connector_dynamic_register_no_init
[10:32:38] [PASSED] drm_test_drm_connector_dynamic_register_mode_object
[10:32:38] [PASSED] drm_test_drm_connector_dynamic_register_sysfs
[10:32:38] [PASSED] drm_test_drm_connector_dynamic_register_sysfs_name
[10:32:38] [PASSED] drm_test_drm_connector_dynamic_register_debugfs
[10:32:38] ========= [PASSED] drm_connector_dynamic_register ==========
[10:32:38] = drm_connector_attach_broadcast_rgb_property (2 subtests) =
[10:32:38] [PASSED] drm_test_drm_connector_attach_broadcast_rgb_property
[10:32:38] [PASSED] drm_test_drm_connector_attach_broadcast_rgb_property_hdmi_connector
[10:32:38] === [PASSED] drm_connector_attach_broadcast_rgb_property ===
[10:32:38] ========== drm_get_tv_mode_from_name (2 subtests) ==========
[10:32:38] ========== drm_test_get_tv_mode_from_name_valid  ===========
[10:32:38] [PASSED] NTSC
[10:32:38] [PASSED] NTSC-443
[10:32:38] [PASSED] NTSC-J
[10:32:38] [PASSED] PAL
[10:32:38] [PASSED] PAL-M
[10:32:38] [PASSED] PAL-N
[10:32:38] [PASSED] SECAM
[10:32:38] [PASSED] Mono
[10:32:38] ====== [PASSED] drm_test_get_tv_mode_from_name_valid =======
[10:32:38] [PASSED] drm_test_get_tv_mode_from_name_truncated
[10:32:38] ============ [PASSED] drm_get_tv_mode_from_name ============
[10:32:38] = drm_test_connector_hdmi_compute_mode_clock (12 subtests) =
[10:32:38] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb
[10:32:38] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_10bpc
[10:32:38] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_10bpc_vic_1
[10:32:38] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_12bpc
[10:32:38] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_12bpc_vic_1
[10:32:38] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_double
[10:32:38] = drm_test_connector_hdmi_compute_mode_clock_yuv420_valid  =
[10:32:38] [PASSED] VIC 96
[10:32:38] [PASSED] VIC 97
[10:32:38] [PASSED] VIC 101
[10:32:38] [PASSED] VIC 102
[10:32:38] [PASSED] VIC 106
[10:32:38] [PASSED] VIC 107
[10:32:38] === [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv420_valid ===
[10:32:38] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv420_10_bpc
[10:32:38] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv420_12_bpc
[10:32:38] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv422_8_bpc
[10:32:38] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv422_10_bpc
[10:32:38] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv422_12_bpc
[10:32:38] === [PASSED] drm_test_connector_hdmi_compute_mode_clock ====
[10:32:38] == drm_hdmi_connector_get_broadcast_rgb_name (2 subtests) ==
[10:32:38] === drm_test_drm_hdmi_connector_get_broadcast_rgb_name  ====
[10:32:38] [PASSED] Automatic
[10:32:38] [PASSED] Full
[10:32:38] [PASSED] Limited 16:235
[10:32:38] === [PASSED] drm_test_drm_hdmi_connector_get_broadcast_rgb_name ===
[10:32:38] [PASSED] drm_test_drm_hdmi_connector_get_broadcast_rgb_name_invalid
[10:32:38] ==== [PASSED] drm_hdmi_connector_get_broadcast_rgb_name ====
[10:32:38] == drm_hdmi_connector_get_output_format_name (2 subtests) ==
[10:32:38] === drm_test_drm_hdmi_connector_get_output_format_name  ====
[10:32:38] [PASSED] RGB
[10:32:38] [PASSED] YUV 4:2:0
[10:32:38] [PASSED] YUV 4:2:2
[10:32:38] [PASSED] YUV 4:4:4
[10:32:38] === [PASSED] drm_test_drm_hdmi_connector_get_output_format_name ===
[10:32:38] [PASSED] drm_test_drm_hdmi_connector_get_output_format_name_invalid
[10:32:38] ==== [PASSED] drm_hdmi_connector_get_output_format_name ====
[10:32:38] ============= drm_damage_helper (21 subtests) ==============
[10:32:38] [PASSED] drm_test_damage_iter_no_damage
[10:32:38] [PASSED] drm_test_damage_iter_no_damage_fractional_src
[10:32:38] [PASSED] drm_test_damage_iter_no_damage_src_moved
[10:32:38] [PASSED] drm_test_damage_iter_no_damage_fractional_src_moved
[10:32:38] [PASSED] drm_test_damage_iter_no_damage_not_visible
[10:32:38] [PASSED] drm_test_damage_iter_no_damage_no_crtc
[10:32:38] [PASSED] drm_test_damage_iter_no_damage_no_fb
[10:32:38] [PASSED] drm_test_damage_iter_simple_damage
[10:32:38] [PASSED] drm_test_damage_iter_single_damage
[10:32:38] [PASSED] drm_test_damage_iter_single_damage_intersect_src
[10:32:38] [PASSED] drm_test_damage_iter_single_damage_outside_src
[10:32:38] [PASSED] drm_test_damage_iter_single_damage_fractional_src
[10:32:38] [PASSED] drm_test_damage_iter_single_damage_intersect_fractional_src
[10:32:38] [PASSED] drm_test_damage_iter_single_damage_outside_fractional_src
[10:32:38] [PASSED] drm_test_damage_iter_single_damage_src_moved
[10:32:38] [PASSED] drm_test_damage_iter_single_damage_fractional_src_moved
[10:32:38] [PASSED] drm_test_damage_iter_damage
[10:32:38] [PASSED] drm_test_damage_iter_damage_one_intersect
[10:32:38] [PASSED] drm_test_damage_iter_damage_one_outside
[10:32:38] [PASSED] drm_test_damage_iter_damage_src_moved
[10:32:38] [PASSED] drm_test_damage_iter_damage_not_visible
[10:32:38] ================ [PASSED] drm_damage_helper ================
[10:32:38] ============== drm_dp_mst_helper (3 subtests) ==============
[10:32:38] ============== drm_test_dp_mst_calc_pbn_mode  ==============
[10:32:38] [PASSED] Clock 154000 BPP 30 DSC disabled
[10:32:38] [PASSED] Clock 234000 BPP 30 DSC disabled
[10:32:38] [PASSED] Clock 297000 BPP 24 DSC disabled
[10:32:38] [PASSED] Clock 332880 BPP 24 DSC enabled
[10:32:38] [PASSED] Clock 324540 BPP 24 DSC enabled
[10:32:38] ========== [PASSED] drm_test_dp_mst_calc_pbn_mode ==========
[10:32:38] ============== drm_test_dp_mst_calc_pbn_div  ===============
[10:32:38] [PASSED] Link rate 2000000 lane count 4
[10:32:38] [PASSED] Link rate 2000000 lane count 2
[10:32:38] [PASSED] Link rate 2000000 lane count 1
[10:32:38] [PASSED] Link rate 1350000 lane count 4
[10:32:38] [PASSED] Link rate 1350000 lane count 2
[10:32:38] [PASSED] Link rate 1350000 lane count 1
[10:32:38] [PASSED] Link rate 1000000 lane count 4
[10:32:38] [PASSED] Link rate 1000000 lane count 2
[10:32:38] [PASSED] Link rate 1000000 lane count 1
[10:32:38] [PASSED] Link rate 810000 lane count 4
[10:32:38] [PASSED] Link rate 810000 lane count 2
[10:32:38] [PASSED] Link rate 810000 lane count 1
[10:32:38] [PASSED] Link rate 540000 lane count 4
[10:32:38] [PASSED] Link rate 540000 lane count 2
[10:32:38] [PASSED] Link rate 540000 lane count 1
[10:32:38] [PASSED] Link rate 270000 lane count 4
[10:32:38] [PASSED] Link rate 270000 lane count 2
[10:32:38] [PASSED] Link rate 270000 lane count 1
[10:32:38] [PASSED] Link rate 162000 lane count 4
[10:32:38] [PASSED] Link rate 162000 lane count 2
[10:32:38] [PASSED] Link rate 162000 lane count 1
[10:32:38] ========== [PASSED] drm_test_dp_mst_calc_pbn_div ===========
[10:32:38] ========= drm_test_dp_mst_sideband_msg_req_decode  =========
[10:32:38] [PASSED] DP_ENUM_PATH_RESOURCES with port number
[10:32:38] [PASSED] DP_POWER_UP_PHY with port number
[10:32:38] [PASSED] DP_POWER_DOWN_PHY with port number
[10:32:38] [PASSED] DP_ALLOCATE_PAYLOAD with SDP stream sinks
[10:32:38] [PASSED] DP_ALLOCATE_PAYLOAD with port number
[10:32:38] [PASSED] DP_ALLOCATE_PAYLOAD with VCPI
[10:32:38] [PASSED] DP_ALLOCATE_PAYLOAD with PBN
[10:32:38] [PASSED] DP_QUERY_PAYLOAD with port number
[10:32:38] [PASSED] DP_QUERY_PAYLOAD with VCPI
[10:32:38] [PASSED] DP_REMOTE_DPCD_READ with port number
[10:32:38] [PASSED] DP_REMOTE_DPCD_READ with DPCD address
[10:32:38] [PASSED] DP_REMOTE_DPCD_READ with max number of bytes
[10:32:38] [PASSED] DP_REMOTE_DPCD_WRITE with port number
[10:32:38] [PASSED] DP_REMOTE_DPCD_WRITE with DPCD address
[10:32:38] [PASSED] DP_REMOTE_DPCD_WRITE with data array
[10:32:38] [PASSED] DP_REMOTE_I2C_READ with port number
[10:32:38] [PASSED] DP_REMOTE_I2C_READ with I2C device ID
[10:32:38] [PASSED] DP_REMOTE_I2C_READ with transactions array
[10:32:38] [PASSED] DP_REMOTE_I2C_WRITE with port number
[10:32:38] [PASSED] DP_REMOTE_I2C_WRITE with I2C device ID
[10:32:38] [PASSED] DP_REMOTE_I2C_WRITE with data array
[10:32:38] [PASSED] DP_QUERY_STREAM_ENC_STATUS with stream ID
[10:32:38] [PASSED] DP_QUERY_STREAM_ENC_STATUS with client ID
[10:32:38] [PASSED] DP_QUERY_STREAM_ENC_STATUS with stream event
[10:32:38] [PASSED] DP_QUERY_STREAM_ENC_STATUS with valid stream event
[10:32:38] [PASSED] DP_QUERY_STREAM_ENC_STATUS with stream behavior
[10:32:38] [PASSED] DP_QUERY_STREAM_ENC_STATUS with a valid stream behavior
[10:32:38] ===== [PASSED] drm_test_dp_mst_sideband_msg_req_decode =====
[10:32:38] ================ [PASSED] drm_dp_mst_helper ================
[10:32:38] ================== drm_exec (7 subtests) ===================
[10:32:38] [PASSED] sanitycheck
[10:32:38] [PASSED] test_lock
[10:32:38] [PASSED] test_lock_unlock
[10:32:38] [PASSED] test_duplicates
[10:32:38] [PASSED] test_prepare
[10:32:38] [PASSED] test_prepare_array
[10:32:38] [PASSED] test_multiple_loops
[10:32:38] ==================== [PASSED] drm_exec =====================
[10:32:38] =========== drm_format_helper_test (17 subtests) ===========
[10:32:38] ============== drm_test_fb_xrgb8888_to_gray8  ==============
[10:32:38] [PASSED] single_pixel_source_buffer
[10:32:38] [PASSED] single_pixel_clip_rectangle
[10:32:38] [PASSED] well_known_colors
[10:32:38] [PASSED] destination_pitch
[10:32:38] ========== [PASSED] drm_test_fb_xrgb8888_to_gray8 ==========
[10:32:38] ============= drm_test_fb_xrgb8888_to_rgb332  ==============
[10:32:38] [PASSED] single_pixel_source_buffer
[10:32:38] [PASSED] single_pixel_clip_rectangle
[10:32:38] [PASSED] well_known_colors
[10:32:38] [PASSED] destination_pitch
[10:32:38] ========= [PASSED] drm_test_fb_xrgb8888_to_rgb332 ==========
[10:32:38] ============= drm_test_fb_xrgb8888_to_rgb565  ==============
[10:32:38] [PASSED] single_pixel_source_buffer
[10:32:38] [PASSED] single_pixel_clip_rectangle
[10:32:38] [PASSED] well_known_colors
[10:32:38] [PASSED] destination_pitch
[10:32:38] ========= [PASSED] drm_test_fb_xrgb8888_to_rgb565 ==========
[10:32:38] ============ drm_test_fb_xrgb8888_to_xrgb1555  =============
[10:32:38] [PASSED] single_pixel_source_buffer
[10:32:38] [PASSED] single_pixel_clip_rectangle
[10:32:38] [PASSED] well_known_colors
[10:32:38] [PASSED] destination_pitch
[10:32:38] ======== [PASSED] drm_test_fb_xrgb8888_to_xrgb1555 =========
[10:32:38] ============ drm_test_fb_xrgb8888_to_argb1555  =============
[10:32:38] [PASSED] single_pixel_source_buffer
[10:32:38] [PASSED] single_pixel_clip_rectangle
[10:32:38] [PASSED] well_known_colors
[10:32:38] [PASSED] destination_pitch
[10:32:38] ======== [PASSED] drm_test_fb_xrgb8888_to_argb1555 =========
[10:32:38] ============ drm_test_fb_xrgb8888_to_rgba5551  =============
[10:32:38] [PASSED] single_pixel_source_buffer
[10:32:38] [PASSED] single_pixel_clip_rectangle
[10:32:38] [PASSED] well_known_colors
[10:32:38] [PASSED] destination_pitch
[10:32:38] ======== [PASSED] drm_test_fb_xrgb8888_to_rgba5551 =========
[10:32:38] ============= drm_test_fb_xrgb8888_to_rgb888  ==============
[10:32:38] [PASSED] single_pixel_source_buffer
[10:32:38] [PASSED] single_pixel_clip_rectangle
[10:32:38] [PASSED] well_known_colors
[10:32:38] [PASSED] destination_pitch
[10:32:38] ========= [PASSED] drm_test_fb_xrgb8888_to_rgb888 ==========
[10:32:38] ============= drm_test_fb_xrgb8888_to_bgr888  ==============
[10:32:38] [PASSED] single_pixel_source_buffer
[10:32:38] [PASSED] single_pixel_clip_rectangle
[10:32:38] [PASSED] well_known_colors
[10:32:38] [PASSED] destination_pitch
[10:32:38] ========= [PASSED] drm_test_fb_xrgb8888_to_bgr888 ==========
[10:32:38] ============ drm_test_fb_xrgb8888_to_argb8888  =============
[10:32:38] [PASSED] single_pixel_source_buffer
[10:32:38] [PASSED] single_pixel_clip_rectangle
[10:32:38] [PASSED] well_known_colors
[10:32:38] [PASSED] destination_pitch
[10:32:38] ======== [PASSED] drm_test_fb_xrgb8888_to_argb8888 =========
[10:32:38] =========== drm_test_fb_xrgb8888_to_xrgb2101010  ===========
[10:32:38] [PASSED] single_pixel_source_buffer
[10:32:38] [PASSED] single_pixel_clip_rectangle
[10:32:38] [PASSED] well_known_colors
[10:32:38] [PASSED] destination_pitch
[10:32:38] ======= [PASSED] drm_test_fb_xrgb8888_to_xrgb2101010 =======
[10:32:38] =========== drm_test_fb_xrgb8888_to_argb2101010  ===========
[10:32:38] [PASSED] single_pixel_source_buffer
[10:32:38] [PASSED] single_pixel_clip_rectangle
[10:32:38] [PASSED] well_known_colors
[10:32:38] [PASSED] destination_pitch
[10:32:38] ======= [PASSED] drm_test_fb_xrgb8888_to_argb2101010 =======
[10:32:38] ============== drm_test_fb_xrgb8888_to_mono  ===============
[10:32:38] [PASSED] single_pixel_source_buffer
[10:32:38] [PASSED] single_pixel_clip_rectangle
[10:32:38] [PASSED] well_known_colors
[10:32:38] [PASSED] destination_pitch
[10:32:38] ========== [PASSED] drm_test_fb_xrgb8888_to_mono ===========
[10:32:38] ==================== drm_test_fb_swab  =====================
[10:32:38] [PASSED] single_pixel_source_buffer
[10:32:38] [PASSED] single_pixel_clip_rectangle
[10:32:38] [PASSED] well_known_colors
[10:32:38] [PASSED] destination_pitch
[10:32:38] ================ [PASSED] drm_test_fb_swab =================
[10:32:38] ============ drm_test_fb_xrgb8888_to_xbgr8888  =============
[10:32:38] [PASSED] single_pixel_source_buffer
[10:32:38] [PASSED] single_pixel_clip_rectangle
[10:32:38] [PASSED] well_known_colors
[10:32:38] [PASSED] destination_pitch
[10:32:38] ======== [PASSED] drm_test_fb_xrgb8888_to_xbgr8888 =========
[10:32:38] ============ drm_test_fb_xrgb8888_to_abgr8888  =============
[10:32:38] [PASSED] single_pixel_source_buffer
[10:32:38] [PASSED] single_pixel_clip_rectangle
[10:32:38] [PASSED] well_known_colors
[10:32:38] [PASSED] destination_pitch
[10:32:38] ======== [PASSED] drm_test_fb_xrgb8888_to_abgr8888 =========
[10:32:38] ================= drm_test_fb_clip_offset  =================
[10:32:38] [PASSED] pass through
[10:32:38] [PASSED] horizontal offset
[10:32:38] [PASSED] vertical offset
[10:32:38] [PASSED] horizontal and vertical offset
[10:32:38] [PASSED] horizontal offset (custom pitch)
[10:32:38] [PASSED] vertical offset (custom pitch)
[10:32:38] [PASSED] horizontal and vertical offset (custom pitch)
[10:32:38] ============= [PASSED] drm_test_fb_clip_offset =============
[10:32:38] =================== drm_test_fb_memcpy  ====================
[10:32:38] [PASSED] single_pixel_source_buffer: XR24 little-endian (0x34325258)
[10:32:38] [PASSED] single_pixel_source_buffer: XRA8 little-endian (0x38415258)
[10:32:38] [PASSED] single_pixel_source_buffer: YU24 little-endian (0x34325559)
[10:32:38] [PASSED] single_pixel_clip_rectangle: XB24 little-endian (0x34324258)
[10:32:38] [PASSED] single_pixel_clip_rectangle: XRA8 little-endian (0x38415258)
[10:32:38] [PASSED] single_pixel_clip_rectangle: YU24 little-endian (0x34325559)
[10:32:38] [PASSED] well_known_colors: XB24 little-endian (0x34324258)
[10:32:38] [PASSED] well_known_colors: XRA8 little-endian (0x38415258)
[10:32:38] [PASSED] well_known_colors: YU24 little-endian (0x34325559)
[10:32:38] [PASSED] destination_pitch: XB24 little-endian (0x34324258)
[10:32:38] [PASSED] destination_pitch: XRA8 little-endian (0x38415258)
[10:32:38] [PASSED] destination_pitch: YU24 little-endian (0x34325559)
[10:32:38] =============== [PASSED] drm_test_fb_memcpy ================
[10:32:38] ============= [PASSED] drm_format_helper_test ==============
[10:32:38] ================= drm_format (18 subtests) =================
[10:32:38] [PASSED] drm_test_format_block_width_invalid
[10:32:38] [PASSED] drm_test_format_block_width_one_plane
[10:32:38] [PASSED] drm_test_format_block_width_two_plane
[10:32:38] [PASSED] drm_test_format_block_width_three_plane
[10:32:38] [PASSED] drm_test_format_block_width_tiled
[10:32:38] [PASSED] drm_test_format_block_height_invalid
[10:32:38] [PASSED] drm_test_format_block_height_one_plane
[10:32:38] [PASSED] drm_test_format_block_height_two_plane
[10:32:38] [PASSED] drm_test_format_block_height_three_plane
[10:32:38] [PASSED] drm_test_format_block_height_tiled
[10:32:38] [PASSED] drm_test_format_min_pitch_invalid
[10:32:38] [PASSED] drm_test_format_min_pitch_one_plane_8bpp
[10:32:38] [PASSED] drm_test_format_min_pitch_one_plane_16bpp
[10:32:38] [PASSED] drm_test_format_min_pitch_one_plane_24bpp
[10:32:38] [PASSED] drm_test_format_min_pitch_one_plane_32bpp
[10:32:38] [PASSED] drm_test_format_min_pitch_two_plane
[10:32:38] [PASSED] drm_test_format_min_pitch_three_plane_8bpp
[10:32:38] [PASSED] drm_test_format_min_pitch_tiled
[10:32:38] =================== [PASSED] drm_format ====================
[10:32:38] ============== drm_framebuffer (10 subtests) ===============
[10:32:38] ========== drm_test_framebuffer_check_src_coords  ==========
[10:32:38] [PASSED] Success: source fits into fb
[10:32:38] [PASSED] Fail: overflowing fb with x-axis coordinate
[10:32:38] [PASSED] Fail: overflowing fb with y-axis coordinate
[10:32:38] [PASSED] Fail: overflowing fb with source width
[10:32:38] [PASSED] Fail: overflowing fb with source height
[10:32:38] ====== [PASSED] drm_test_framebuffer_check_src_coords ======
[10:32:38] [PASSED] drm_test_framebuffer_cleanup
[10:32:38] =============== drm_test_framebuffer_create  ===============
[10:32:38] [PASSED] ABGR8888 normal sizes
[10:32:38] [PASSED] ABGR8888 max sizes
[10:32:38] [PASSED] ABGR8888 pitch greater than min required
[10:32:38] [PASSED] ABGR8888 pitch less than min required
[10:32:38] [PASSED] ABGR8888 Invalid width
[10:32:38] [PASSED] ABGR8888 Invalid buffer handle
[10:32:38] [PASSED] No pixel format
[10:32:38] [PASSED] ABGR8888 Width 0
[10:32:38] [PASSED] ABGR8888 Height 0
[10:32:38] [PASSED] ABGR8888 Out of bound height * pitch combination
[10:32:38] [PASSED] ABGR8888 Large buffer offset
[10:32:38] [PASSED] ABGR8888 Buffer offset for inexistent plane
[10:32:38] [PASSED] ABGR8888 Invalid flag
[10:32:38] [PASSED] ABGR8888 Set DRM_MODE_FB_MODIFIERS without modifiers
[10:32:38] [PASSED] ABGR8888 Valid buffer modifier
[10:32:38] [PASSED] ABGR8888 Invalid buffer modifier(DRM_FORMAT_MOD_SAMSUNG_64_32_TILE)
[10:32:38] [PASSED] ABGR8888 Extra pitches without DRM_MODE_FB_MODIFIERS
[10:32:38] [PASSED] ABGR8888 Extra pitches with DRM_MODE_FB_MODIFIERS
[10:32:38] [PASSED] NV12 Normal sizes
[10:32:38] [PASSED] NV12 Max sizes
[10:32:38] [PASSED] NV12 Invalid pitch
[10:32:38] [PASSED] NV12 Invalid modifier/missing DRM_MODE_FB_MODIFIERS flag
[10:32:38] [PASSED] NV12 different  modifier per-plane
[10:32:38] [PASSED] NV12 with DRM_FORMAT_MOD_SAMSUNG_64_32_TILE
[10:32:38] [PASSED] NV12 Valid modifiers without DRM_MODE_FB_MODIFIERS
[10:32:38] [PASSED] NV12 Modifier for inexistent plane
[10:32:38] [PASSED] NV12 Handle for inexistent plane
[10:32:38] [PASSED] NV12 Handle for inexistent plane without DRM_MODE_FB_MODIFIERS
[10:32:38] [PASSED] YVU420 DRM_MODE_FB_MODIFIERS set without modifier
[10:32:38] [PASSED] YVU420 Normal sizes
[10:32:38] [PASSED] YVU420 Max sizes
[10:32:38] [PASSED] YVU420 Invalid pitch
[10:32:38] [PASSED] YVU420 Different pitches
[10:32:38] [PASSED] YVU420 Different buffer offsets/pitches
[10:32:38] [PASSED] YVU420 Modifier set just for plane 0, without DRM_MODE_FB_MODIFIERS
[10:32:38] [PASSED] YVU420 Modifier set just for planes 0, 1, without DRM_MODE_FB_MODIFIERS
[10:32:38] [PASSED] YVU420 Modifier set just for plane 0, 1, with DRM_MODE_FB_MODIFIERS
[10:32:38] [PASSED] YVU420 Valid modifier
[10:32:38] [PASSED] YVU420 Different modifiers per plane
[10:32:38] [PASSED] YVU420 Modifier for inexistent plane
[10:32:38] [PASSED] YUV420_10BIT Invalid modifier(DRM_FORMAT_MOD_LINEAR)
[10:32:38] [PASSED] X0L2 Normal sizes
[10:32:38] [PASSED] X0L2 Max sizes
[10:32:38] [PASSED] X0L2 Invalid pitch
[10:32:38] [PASSED] X0L2 Pitch greater than minimum required
[10:32:38] [PASSED] X0L2 Handle for inexistent plane
[10:32:38] [PASSED] X0L2 Offset for inexistent plane, without DRM_MODE_FB_MODIFIERS set
[10:32:38] [PASSED] X0L2 Modifier without DRM_MODE_FB_MODIFIERS set
[10:32:38] [PASSED] X0L2 Valid modifier
[10:32:38] [PASSED] X0L2 Modifier for inexistent plane
[10:32:38] =========== [PASSED] drm_test_framebuffer_create ===========
[10:32:38] [PASSED] drm_test_framebuffer_free
[10:32:38] [PASSED] drm_test_framebuffer_init
[10:32:38] [PASSED] drm_test_framebuffer_init_bad_format
[10:32:38] [PASSED] drm_test_framebuffer_init_dev_mismatch
[10:32:38] [PASSED] drm_test_framebuffer_lookup
[10:32:38] [PASSED] drm_test_framebuffer_lookup_inexistent
[10:32:38] [PASSED] drm_test_framebuffer_modifiers_not_supported
[10:32:38] ================= [PASSED] drm_framebuffer =================
[10:32:38] ================ drm_gem_shmem (8 subtests) ================
[10:32:38] [PASSED] drm_gem_shmem_test_obj_create
[10:32:38] [PASSED] drm_gem_shmem_test_obj_create_private
[10:32:38] [PASSED] drm_gem_shmem_test_pin_pages
[10:32:38] [PASSED] drm_gem_shmem_test_vmap
[10:32:38] [PASSED] drm_gem_shmem_test_get_pages_sgt
[10:32:38] [PASSED] drm_gem_shmem_test_get_sg_table
[10:32:38] [PASSED] drm_gem_shmem_test_madvise
[10:32:38] [PASSED] drm_gem_shmem_test_purge
[10:32:38] ================== [PASSED] drm_gem_shmem ==================
[10:32:38] === drm_atomic_helper_connector_hdmi_check (27 subtests) ===
[10:32:38] [PASSED] drm_test_check_broadcast_rgb_auto_cea_mode
[10:32:38] [PASSED] drm_test_check_broadcast_rgb_auto_cea_mode_vic_1
[10:32:38] [PASSED] drm_test_check_broadcast_rgb_full_cea_mode
[10:32:38] [PASSED] drm_test_check_broadcast_rgb_full_cea_mode_vic_1
[10:32:38] [PASSED] drm_test_check_broadcast_rgb_limited_cea_mode
[10:32:38] [PASSED] drm_test_check_broadcast_rgb_limited_cea_mode_vic_1
[10:32:38] ====== drm_test_check_broadcast_rgb_cea_mode_yuv420  =======
[10:32:38] [PASSED] Automatic
[10:32:38] [PASSED] Full
[10:32:38] [PASSED] Limited 16:235
[10:32:38] == [PASSED] drm_test_check_broadcast_rgb_cea_mode_yuv420 ===
[10:32:38] [PASSED] drm_test_check_broadcast_rgb_crtc_mode_changed
[10:32:38] [PASSED] drm_test_check_broadcast_rgb_crtc_mode_not_changed
[10:32:38] [PASSED] drm_test_check_disable_connector
[10:32:38] [PASSED] drm_test_check_hdmi_funcs_reject_rate
[10:32:38] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_rgb
[10:32:38] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_yuv420
[10:32:38] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_ignore_yuv422
[10:32:38] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_ignore_yuv420
[10:32:38] [PASSED] drm_test_check_driver_unsupported_fallback_yuv420
[10:32:38] [PASSED] drm_test_check_output_bpc_crtc_mode_changed
[10:32:38] [PASSED] drm_test_check_output_bpc_crtc_mode_not_changed
[10:32:38] [PASSED] drm_test_check_output_bpc_dvi
[10:32:38] [PASSED] drm_test_check_output_bpc_format_vic_1
[10:32:38] [PASSED] drm_test_check_output_bpc_format_display_8bpc_only
[10:32:38] [PASSED] drm_test_check_output_bpc_format_display_rgb_only
[10:32:38] [PASSED] drm_test_check_output_bpc_format_driver_8bpc_only
[10:32:38] [PASSED] drm_test_check_output_bpc_format_driver_rgb_only
[10:32:38] [PASSED] drm_test_check_tmds_char_rate_rgb_8bpc
[10:32:38] [PASSED] drm_test_check_tmds_char_rate_rgb_10bpc
[10:32:38] [PASSED] drm_test_check_tmds_char_rate_rgb_12bpc
[10:32:38] ===== [PASSED] drm_atomic_helper_connector_hdmi_check ======
[10:32:38] === drm_atomic_helper_connector_hdmi_reset (6 subtests) ====
[10:32:38] [PASSED] drm_test_check_broadcast_rgb_value
[10:32:38] [PASSED] drm_test_check_bpc_8_value
[10:32:38] [PASSED] drm_test_check_bpc_10_value
[10:32:38] [PASSED] drm_test_check_bpc_12_value
[10:32:38] [PASSED] drm_test_check_format_value
[10:32:38] [PASSED] drm_test_check_tmds_char_value
[10:32:38] ===== [PASSED] drm_atomic_helper_connector_hdmi_reset ======
[10:32:38] = drm_atomic_helper_connector_hdmi_mode_valid (4 subtests) =
[10:32:38] [PASSED] drm_test_check_mode_valid
[10:32:38] [PASSED] drm_test_check_mode_valid_reject
[10:32:38] [PASSED] drm_test_check_mode_valid_reject_rate
[10:32:38] [PASSED] drm_test_check_mode_valid_reject_max_clock
[10:32:38] === [PASSED] drm_atomic_helper_connector_hdmi_mode_valid ===
[10:32:38] ================= drm_managed (2 subtests) =================
[10:32:38] [PASSED] drm_test_managed_release_action
[10:32:38] [PASSED] drm_test_managed_run_action
[10:32:38] =================== [PASSED] drm_managed ===================
[10:32:38] =================== drm_mm (6 subtests) ====================
[10:32:38] [PASSED] drm_test_mm_init
[10:32:38] [PASSED] drm_test_mm_debug
[10:32:38] [PASSED] drm_test_mm_align32
[10:32:38] [PASSED] drm_test_mm_align64
[10:32:38] [PASSED] drm_test_mm_lowest
[10:32:38] [PASSED] drm_test_mm_highest
[10:32:38] ===================== [PASSED] drm_mm ======================
[10:32:38] ============= drm_modes_analog_tv (5 subtests) =============
[10:32:38] [PASSED] drm_test_modes_analog_tv_mono_576i
[10:32:38] [PASSED] drm_test_modes_analog_tv_ntsc_480i
[10:32:38] [PASSED] drm_test_modes_analog_tv_ntsc_480i_inlined
[10:32:38] [PASSED] drm_test_modes_analog_tv_pal_576i
[10:32:38] [PASSED] drm_test_modes_analog_tv_pal_576i_inlined
[10:32:38] =============== [PASSED] drm_modes_analog_tv ===============
[10:32:38] ============== drm_plane_helper (2 subtests) ===============
[10:32:38] =============== drm_test_check_plane_state  ================
[10:32:38] [PASSED] clipping_simple
[10:32:38] [PASSED] clipping_rotate_reflect
[10:32:38] [PASSED] positioning_simple
[10:32:38] [PASSED] upscaling
[10:32:38] [PASSED] downscaling
[10:32:38] [PASSED] rounding1
[10:32:38] [PASSED] rounding2
[10:32:38] [PASSED] rounding3
[10:32:38] [PASSED] rounding4
[10:32:38] =========== [PASSED] drm_test_check_plane_state ============
[10:32:38] =========== drm_test_check_invalid_plane_state  ============
[10:32:38] [PASSED] positioning_invalid
[10:32:38] [PASSED] upscaling_invalid
[10:32:38] [PASSED] downscaling_invalid
[10:32:38] ======= [PASSED] drm_test_check_invalid_plane_state ========
[10:32:38] ================ [PASSED] drm_plane_helper =================
[10:32:38] ====== drm_connector_helper_tv_get_modes (1 subtest) =======
[10:32:38] ====== drm_test_connector_helper_tv_get_modes_check  =======
[10:32:38] [PASSED] None
[10:32:38] [PASSED] PAL
[10:32:38] [PASSED] NTSC
[10:32:38] [PASSED] Both, NTSC Default
[10:32:38] [PASSED] Both, PAL Default
[10:32:38] [PASSED] Both, NTSC Default, with PAL on command-line
[10:32:38] [PASSED] Both, PAL Default, with NTSC on command-line
[10:32:38] == [PASSED] drm_test_connector_helper_tv_get_modes_check ===
[10:32:38] ======== [PASSED] drm_connector_helper_tv_get_modes ========
[10:32:38] ================== drm_rect (9 subtests) ===================
[10:32:38] [PASSED] drm_test_rect_clip_scaled_div_by_zero
[10:32:38] [PASSED] drm_test_rect_clip_scaled_not_clipped
[10:32:38] [PASSED] drm_test_rect_clip_scaled_clipped
[10:32:38] [PASSED] drm_test_rect_clip_scaled_signed_vs_unsigned
[10:32:38] ================= drm_test_rect_intersect  =================
[10:32:38] [PASSED] top-left x bottom-right: 2x2+1+1 x 2x2+0+0
[10:32:38] [PASSED] top-right x bottom-left: 2x2+0+0 x 2x2+1-1
[10:32:38] [PASSED] bottom-left x top-right: 2x2+1-1 x 2x2+0+0
[10:32:38] [PASSED] bottom-right x top-left: 2x2+0+0 x 2x2+1+1
[10:32:38] [PASSED] right x left: 2x1+0+0 x 3x1+1+0
[10:32:38] [PASSED] left x right: 3x1+1+0 x 2x1+0+0
[10:32:38] [PASSED] up x bottom: 1x2+0+0 x 1x3+0-1
[10:32:38] [PASSED] bottom x up: 1x3+0-1 x 1x2+0+0
[10:32:38] [PASSED] touching corner: 1x1+0+0 x 2x2+1+1
[10:32:38] [PASSED] touching side: 1x1+0+0 x 1x1+1+0
[10:32:38] [PASSED] equal rects: 2x2+0+0 x 2x2+0+0
[10:32:38] [PASSED] inside another: 2x2+0+0 x 1x1+1+1
[10:32:38] [PASSED] far away: 1x1+0+0 x 1x1+3+6
[10:32:38] [PASSED] points intersecting: 0x0+5+10 x 0x0+5+10
[10:32:38] [PASSED] points not intersecting: 0x0+0+0 x 0x0+5+10
[10:32:38] ============= [PASSED] drm_test_rect_intersect =============
[10:32:38] ================ drm_test_rect_calc_hscale  ================
[10:32:38] [PASSED] normal use
[10:32:38] [PASSED] out of max range
[10:32:38] [PASSED] out of min range
[10:32:38] [PASSED] zero dst
[10:32:38] [PASSED] negative src
[10:32:38] [PASSED] negative dst
[10:32:38] ============ [PASSED] drm_test_rect_calc_hscale ============
[10:32:38] ================ drm_test_rect_calc_vscale  ================
[10:32:38] [PASSED] normal use
stty: 'standard input': Inappropriate ioctl for device
[10:32:38] [PASSED] out of max range
[10:32:38] [PASSED] out of min range
[10:32:38] [PASSED] zero dst
[10:32:38] [PASSED] negative src
[10:32:38] [PASSED] negative dst
[10:32:38] ============ [PASSED] drm_test_rect_calc_vscale ============
[10:32:38] ================== drm_test_rect_rotate  ===================
[10:32:38] [PASSED] reflect-x
[10:32:38] [PASSED] reflect-y
[10:32:38] [PASSED] rotate-0
[10:32:38] [PASSED] rotate-90
[10:32:38] [PASSED] rotate-180
[10:32:38] [PASSED] rotate-270
[10:32:38] ============== [PASSED] drm_test_rect_rotate ===============
[10:32:38] ================ drm_test_rect_rotate_inv  =================
[10:32:38] [PASSED] reflect-x
[10:32:38] [PASSED] reflect-y
[10:32:38] [PASSED] rotate-0
[10:32:38] [PASSED] rotate-90
[10:32:38] [PASSED] rotate-180
[10:32:38] [PASSED] rotate-270
[10:32:38] ============ [PASSED] drm_test_rect_rotate_inv =============
[10:32:38] ==================== [PASSED] drm_rect =====================
[10:32:38] ============ drm_sysfb_modeset_test (1 subtest) ============
[10:32:38] ============ drm_test_sysfb_build_fourcc_list  =============
[10:32:38] [PASSED] no native formats
[10:32:38] [PASSED] XRGB8888 as native format
[10:32:38] [PASSED] remove duplicates
[10:32:38] [PASSED] convert alpha formats
[10:32:38] [PASSED] random formats
[10:32:38] ======== [PASSED] drm_test_sysfb_build_fourcc_list =========
[10:32:38] ============= [PASSED] drm_sysfb_modeset_test ==============
[10:32:38] ============================================================
[10:32:38] Testing complete. Ran 622 tests: passed: 622
[10:32:38] Elapsed time: 31.582s total, 1.652s configuring, 29.413s building, 0.472s running

+ /kernel/tools/testing/kunit/kunit.py run --kunitconfig /kernel/drivers/gpu/drm/ttm/tests/.kunitconfig
[10:32:38] Configuring KUnit Kernel ...
Regenerating .config ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
[10:32:40] Building KUnit Kernel ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
Building with:
$ make all compile_commands.json scripts_gdb ARCH=um O=.kunit --jobs=25
[10:32:49] Starting KUnit Kernel (1/1)...
[10:32:49] ============================================================
Running tests with:
$ .kunit/linux kunit.enable=1 mem=1G console=tty kunit_shutdown=halt
[10:32:49] ================= ttm_device (5 subtests) ==================
[10:32:49] [PASSED] ttm_device_init_basic
[10:32:49] [PASSED] ttm_device_init_multiple
[10:32:49] [PASSED] ttm_device_fini_basic
[10:32:49] [PASSED] ttm_device_init_no_vma_man
[10:32:49] ================== ttm_device_init_pools  ==================
[10:32:49] [PASSED] No DMA allocations, no DMA32 required
[10:32:49] [PASSED] DMA allocations, DMA32 required
[10:32:49] [PASSED] No DMA allocations, DMA32 required
[10:32:49] [PASSED] DMA allocations, no DMA32 required
[10:32:49] ============== [PASSED] ttm_device_init_pools ==============
[10:32:49] =================== [PASSED] ttm_device ====================
[10:32:49] ================== ttm_pool (8 subtests) ===================
[10:32:49] ================== ttm_pool_alloc_basic  ===================
[10:32:49] [PASSED] One page
[10:32:49] [PASSED] More than one page
[10:32:49] [PASSED] Above the allocation limit
[10:32:49] [PASSED] One page, with coherent DMA mappings enabled
[10:32:49] [PASSED] Above the allocation limit, with coherent DMA mappings enabled
[10:32:49] ============== [PASSED] ttm_pool_alloc_basic ===============
[10:32:49] ============== ttm_pool_alloc_basic_dma_addr  ==============
[10:32:49] [PASSED] One page
[10:32:49] [PASSED] More than one page
[10:32:49] [PASSED] Above the allocation limit
[10:32:49] [PASSED] One page, with coherent DMA mappings enabled
[10:32:49] [PASSED] Above the allocation limit, with coherent DMA mappings enabled
[10:32:49] ========== [PASSED] ttm_pool_alloc_basic_dma_addr ==========
[10:32:49] [PASSED] ttm_pool_alloc_order_caching_match
[10:32:49] [PASSED] ttm_pool_alloc_caching_mismatch
[10:32:49] [PASSED] ttm_pool_alloc_order_mismatch
[10:32:49] [PASSED] ttm_pool_free_dma_alloc
[10:32:49] [PASSED] ttm_pool_free_no_dma_alloc
[10:32:49] [PASSED] ttm_pool_fini_basic
[10:32:49] ==================== [PASSED] ttm_pool =====================
[10:32:49] ================ ttm_resource (8 subtests) =================
[10:32:49] ================= ttm_resource_init_basic  =================
[10:32:49] [PASSED] Init resource in TTM_PL_SYSTEM
[10:32:49] [PASSED] Init resource in TTM_PL_VRAM
[10:32:49] [PASSED] Init resource in a private placement
[10:32:49] [PASSED] Init resource in TTM_PL_SYSTEM, set placement flags
[10:32:49] ============= [PASSED] ttm_resource_init_basic =============
[10:32:49] [PASSED] ttm_resource_init_pinned
[10:32:49] [PASSED] ttm_resource_fini_basic
[10:32:49] [PASSED] ttm_resource_manager_init_basic
[10:32:49] [PASSED] ttm_resource_manager_usage_basic
[10:32:49] [PASSED] ttm_resource_manager_set_used_basic
[10:32:49] [PASSED] ttm_sys_man_alloc_basic
[10:32:49] [PASSED] ttm_sys_man_free_basic
[10:32:49] ================== [PASSED] ttm_resource ===================
[10:32:49] =================== ttm_tt (15 subtests) ===================
[10:32:49] ==================== ttm_tt_init_basic  ====================
[10:32:49] [PASSED] Page-aligned size
[10:32:49] [PASSED] Extra pages requested
[10:32:49] ================ [PASSED] ttm_tt_init_basic ================
[10:32:49] [PASSED] ttm_tt_init_misaligned
[10:32:49] [PASSED] ttm_tt_fini_basic
[10:32:49] [PASSED] ttm_tt_fini_sg
[10:32:49] [PASSED] ttm_tt_fini_shmem
[10:32:49] [PASSED] ttm_tt_create_basic
[10:32:49] [PASSED] ttm_tt_create_invalid_bo_type
[10:32:49] [PASSED] ttm_tt_create_ttm_exists
[10:32:49] [PASSED] ttm_tt_create_failed
[10:32:49] [PASSED] ttm_tt_destroy_basic
[10:32:49] [PASSED] ttm_tt_populate_null_ttm
[10:32:49] [PASSED] ttm_tt_populate_populated_ttm
[10:32:49] [PASSED] ttm_tt_unpopulate_basic
[10:32:49] [PASSED] ttm_tt_unpopulate_empty_ttm
[10:32:49] [PASSED] ttm_tt_swapin_basic
[10:32:49] ===================== [PASSED] ttm_tt ======================
[10:32:49] =================== ttm_bo (14 subtests) ===================
[10:32:49] =========== ttm_bo_reserve_optimistic_no_ticket  ===========
[10:32:49] [PASSED] Cannot be interrupted and sleeps
[10:32:49] [PASSED] Cannot be interrupted, locks straight away
[10:32:49] [PASSED] Can be interrupted, sleeps
[10:32:49] ======= [PASSED] ttm_bo_reserve_optimistic_no_ticket =======
[10:32:49] [PASSED] ttm_bo_reserve_locked_no_sleep
[10:32:49] [PASSED] ttm_bo_reserve_no_wait_ticket
[10:32:49] [PASSED] ttm_bo_reserve_double_resv
[10:32:49] [PASSED] ttm_bo_reserve_interrupted
[10:32:49] [PASSED] ttm_bo_reserve_deadlock
[10:32:49] [PASSED] ttm_bo_unreserve_basic
[10:32:49] [PASSED] ttm_bo_unreserve_pinned
[10:32:49] [PASSED] ttm_bo_unreserve_bulk
[10:32:49] [PASSED] ttm_bo_fini_basic
[10:32:49] [PASSED] ttm_bo_fini_shared_resv
[10:32:49] [PASSED] ttm_bo_pin_basic
[10:32:49] [PASSED] ttm_bo_pin_unpin_resource
[10:32:49] [PASSED] ttm_bo_multiple_pin_one_unpin
[10:32:49] ===================== [PASSED] ttm_bo ======================
[10:32:49] ============== ttm_bo_validate (21 subtests) ===============
[10:32:49] ============== ttm_bo_init_reserved_sys_man  ===============
[10:32:49] [PASSED] Buffer object for userspace
[10:32:49] [PASSED] Kernel buffer object
[10:32:49] [PASSED] Shared buffer object
[10:32:49] ========== [PASSED] ttm_bo_init_reserved_sys_man ===========
[10:32:49] ============== ttm_bo_init_reserved_mock_man  ==============
[10:32:49] [PASSED] Buffer object for userspace
[10:32:49] [PASSED] Kernel buffer object
[10:32:49] [PASSED] Shared buffer object
[10:32:49] ========== [PASSED] ttm_bo_init_reserved_mock_man ==========
[10:32:49] [PASSED] ttm_bo_init_reserved_resv
[10:32:49] ================== ttm_bo_validate_basic  ==================
[10:32:49] [PASSED] Buffer object for userspace
[10:32:49] [PASSED] Kernel buffer object
[10:32:49] [PASSED] Shared buffer object
[10:32:49] ============== [PASSED] ttm_bo_validate_basic ==============
[10:32:49] [PASSED] ttm_bo_validate_invalid_placement
[10:32:49] ============= ttm_bo_validate_same_placement  ==============
[10:32:49] [PASSED] System manager
[10:32:49] [PASSED] VRAM manager
[10:32:49] ========= [PASSED] ttm_bo_validate_same_placement ==========
[10:32:49] [PASSED] ttm_bo_validate_failed_alloc
[10:32:49] [PASSED] ttm_bo_validate_pinned
[10:32:49] [PASSED] ttm_bo_validate_busy_placement
[10:32:49] ================ ttm_bo_validate_multihop  =================
[10:32:49] [PASSED] Buffer object for userspace
[10:32:49] [PASSED] Kernel buffer object
[10:32:49] [PASSED] Shared buffer object
[10:32:49] ============ [PASSED] ttm_bo_validate_multihop =============
[10:32:49] ========== ttm_bo_validate_no_placement_signaled  ==========
[10:32:49] [PASSED] Buffer object in system domain, no page vector
[10:32:49] [PASSED] Buffer object in system domain with an existing page vector
[10:32:49] ====== [PASSED] ttm_bo_validate_no_placement_signaled ======
[10:32:49] ======== ttm_bo_validate_no_placement_not_signaled  ========
[10:32:49] [PASSED] Buffer object for userspace
[10:32:49] [PASSED] Kernel buffer object
[10:32:49] [PASSED] Shared buffer object
[10:32:49] ==== [PASSED] ttm_bo_validate_no_placement_not_signaled ====
[10:32:49] [PASSED] ttm_bo_validate_move_fence_signaled
[10:32:49] ========= ttm_bo_validate_move_fence_not_signaled  =========
[10:32:49] [PASSED] Waits for GPU
[10:32:49] [PASSED] Tries to lock straight away
[10:32:49] ===== [PASSED] ttm_bo_validate_move_fence_not_signaled =====
[10:32:49] [PASSED] ttm_bo_validate_happy_evict
[10:32:49] [PASSED] ttm_bo_validate_all_pinned_evict
[10:32:49] [PASSED] ttm_bo_validate_allowed_only_evict
[10:32:49] [PASSED] ttm_bo_validate_deleted_evict
[10:32:49] [PASSED] ttm_bo_validate_busy_domain_evict
[10:32:49] [PASSED] ttm_bo_validate_evict_gutting
[10:32:49] [PASSED] ttm_bo_validate_recrusive_evict
stty: 'standard input': Inappropriate ioctl for device
[10:32:49] ================= [PASSED] ttm_bo_validate =================
[10:32:49] ============================================================
[10:32:49] Testing complete. Ran 101 tests: passed: 101
[10:32:49] Elapsed time: 11.119s total, 1.641s configuring, 9.212s building, 0.231s running

+ cleanup
++ stat -c %u:%g /kernel
+ chown -R 1003:1003 /kernel



^ permalink raw reply	[flat|nested] 14+ messages in thread

* ✗ CI.checksparse: warning for Optimize vrr.guardband (rev2)
  2025-10-16  9:30 [PATCH 0/6] Optimize vrr.guardband Ankit Nautiyal
                   ` (7 preceding siblings ...)
  2025-10-16 10:32 ` ✓ CI.KUnit: success " Patchwork
@ 2025-10-16 10:50 ` Patchwork
  2025-10-16 11:25 ` ✓ Xe.CI.BAT: success " Patchwork
  2025-10-17  6:56 ` ✓ Xe.CI.Full: " Patchwork
  10 siblings, 0 replies; 14+ messages in thread
From: Patchwork @ 2025-10-16 10:50 UTC (permalink / raw)
  To: Ankit Nautiyal; +Cc: intel-xe

== Series Details ==

Series: Optimize vrr.guardband (rev2)
URL   : https://patchwork.freedesktop.org/series/155979/
State : warning

== Summary ==

+ trap cleanup EXIT
+ KERNEL=/kernel
+ MT=/root/linux/maintainer-tools
+ git clone https://gitlab.freedesktop.org/drm/maintainer-tools /root/linux/maintainer-tools
Cloning into '/root/linux/maintainer-tools'...
warning: redirecting to https://gitlab.freedesktop.org/drm/maintainer-tools.git/
+ make -C /root/linux/maintainer-tools
make: Entering directory '/root/linux/maintainer-tools'
cc -O2 -g -Wextra -o remap-log remap-log.c
make: Leaving directory '/root/linux/maintainer-tools'
+ cd /kernel
+ git config --global --add safe.directory /kernel
+ /root/linux/maintainer-tools/dim sparse --fast aaaff197c9186f4959c2bcb18035725188b950ed
Sparse version: 0.6.4 (Ubuntu: 0.6.4-4ubuntu3)
Fast mode used, each commit won't be checked separately.
-
+drivers/gpu/drm/i915/display/intel_alpm.c: note: in included file:
+drivers/gpu/drm/i915/display/intel_cdclk.c: note: in included file:
+drivers/gpu/drm/i915/display/intel_ddi.c: note: in included file:
+drivers/gpu/drm/i915/display/intel_display_types.h:2042:24: warning: unreplaced symbol '<noident>'
+drivers/gpu/drm/i915/display/intel_display_types.h:2042:24: warning: unreplaced symbol '<noident>'
+drivers/gpu/drm/i915/display/intel_display_types.h:2042:24: warning: unreplaced symbol '<noident>'
+drivers/gpu/drm/i915/display/intel_display_types.h:2042:24: warning: unreplaced symbol '<noident>'
+drivers/gpu/drm/i915/display/intel_display_types.h:2042:24: warning: unreplaced symbol '<noident>'
+drivers/gpu/drm/i915/display/intel_display_types.h:2042:24: warning: unreplaced symbol '<noident>'
+drivers/gpu/drm/i915/display/intel_display_types.h:2042:24: warning: unreplaced symbol '<noident>'
+drivers/gpu/drm/i915/display/intel_display_types.h:2042:24: warning: unreplaced symbol '<noident>'
+drivers/gpu/drm/i915/display/intel_display_types.h:2042:24: warning: unreplaced symbol '<noident>'
+drivers/gpu/drm/i915/display/intel_display_types.h:2042:24: warning: unreplaced symbol '<noident>'
+drivers/gpu/drm/i915/display/intel_display_types.h:2042:24: warning: unreplaced symbol '<noident>'
+drivers/gpu/drm/i915/display/intel_display_types.h:2042:24: warning: unreplaced symbol '<noident>'
+drivers/gpu/drm/i915/display/intel_display_types.h:2042:24: warning: unreplaced symbol '<noident>'
+drivers/gpu/drm/i915/display/intel_display_types.h:2042:24: warning: unreplaced symbol '<noident>'
+drivers/gpu/drm/i915/display/intel_display_types.h:2042:24: warning: unreplaced symbol '<noident>'
+drivers/gpu/drm/i915/display/intel_display_types.h:2042:24: warning: unreplaced symbol '<noident>'
+drivers/gpu/drm/i915/display/intel_display_types.h:2055:24: warning: unreplaced symbol '<noident>'
+drivers/gpu/drm/i915/display/intel_display_types.h:2055:24: warning: unreplaced symbol '<noident>'
+drivers/gpu/drm/i915/display/intel_display_types.h:2055:24: warning: unreplaced symbol '<noident>'
+drivers/gpu/drm/i915/display/intel_hdcp.c: note: in included file:
+drivers/gpu/drm/i915/display/intel_hotplug.c: note: in included file:
+drivers/gpu/drm/i915/display/intel_pps.c: note: in included file:
+drivers/gpu/drm/i915/display/intel_psr.c: note: in included file:
+drivers/gpu/drm/i915/intel_uncore.c:1928:1: warning: context imbalance in 'fwtable_read8' - unexpected unlock
+drivers/gpu/drm/i915/intel_uncore.c:1929:1: warning: context imbalance in 'fwtable_read16' - unexpected unlock
+drivers/gpu/drm/i915/intel_uncore.c:1930:1: warning: context imbalance in 'fwtable_read32' - unexpected unlock
+drivers/gpu/drm/i915/intel_uncore.c:1931:1: warning: context imbalance in 'fwtable_read64' - unexpected unlock
+drivers/gpu/drm/i915/intel_uncore.c:1996:1: warning: context imbalance in 'gen6_write8' - unexpected unlock
+drivers/gpu/drm/i915/intel_uncore.c:1997:1: warning: context imbalance in 'gen6_write16' - unexpected unlock
+drivers/gpu/drm/i915/intel_uncore.c:1998:1: warning: context imbalance in 'gen6_write32' - unexpected unlock
+drivers/gpu/drm/i915/intel_uncore.c:2018:1: warning: context imbalance in 'fwtable_write8' - unexpected unlock
+drivers/gpu/drm/i915/intel_uncore.c:2019:1: warning: context imbalance in 'fwtable_write16' - unexpected unlock
+drivers/gpu/drm/i915/intel_uncore.c:2020:1: warning: context imbalance in 'fwtable_write32' - unexpected unlock

+ cleanup
++ stat -c %u:%g /kernel
+ chown -R 1003:1003 /kernel



^ permalink raw reply	[flat|nested] 14+ messages in thread

* ✓ Xe.CI.BAT: success for Optimize vrr.guardband (rev2)
  2025-10-16  9:30 [PATCH 0/6] Optimize vrr.guardband Ankit Nautiyal
                   ` (8 preceding siblings ...)
  2025-10-16 10:50 ` ✗ CI.checksparse: warning " Patchwork
@ 2025-10-16 11:25 ` Patchwork
  2025-10-17  6:56 ` ✓ Xe.CI.Full: " Patchwork
  10 siblings, 0 replies; 14+ messages in thread
From: Patchwork @ 2025-10-16 11:25 UTC (permalink / raw)
  To: Ankit Nautiyal; +Cc: intel-xe

[-- Attachment #1: Type: text/plain, Size: 852 bytes --]

== Series Details ==

Series: Optimize vrr.guardband (rev2)
URL   : https://patchwork.freedesktop.org/series/155979/
State : success

== Summary ==

CI Bug Log - changes from xe-3930-aaaff197c9186f4959c2bcb18035725188b950ed_BAT -> xe-pw-155979v2_BAT
====================================================

Summary
-------

  **SUCCESS**

  No regressions found.

  

Participating hosts (11 -> 11)
------------------------------

  No changes in participating hosts


Changes
-------

  No changes found


Build changes
-------------

  * Linux: xe-3930-aaaff197c9186f4959c2bcb18035725188b950ed -> xe-pw-155979v2

  IGT_8587: 8587
  xe-3930-aaaff197c9186f4959c2bcb18035725188b950ed: aaaff197c9186f4959c2bcb18035725188b950ed
  xe-pw-155979v2: 155979v2

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155979v2/index.html

[-- Attachment #2: Type: text/html, Size: 1400 bytes --]

^ permalink raw reply	[flat|nested] 14+ messages in thread

* ✓ Xe.CI.Full: success for Optimize vrr.guardband (rev2)
  2025-10-16  9:30 [PATCH 0/6] Optimize vrr.guardband Ankit Nautiyal
                   ` (9 preceding siblings ...)
  2025-10-16 11:25 ` ✓ Xe.CI.BAT: success " Patchwork
@ 2025-10-17  6:56 ` Patchwork
  10 siblings, 0 replies; 14+ messages in thread
From: Patchwork @ 2025-10-17  6:56 UTC (permalink / raw)
  To: Ankit Nautiyal; +Cc: intel-xe

[-- Attachment #1: Type: text/plain, Size: 53715 bytes --]

== Series Details ==

Series: Optimize vrr.guardband (rev2)
URL   : https://patchwork.freedesktop.org/series/155979/
State : success

== Summary ==

CI Bug Log - changes from xe-3930-aaaff197c9186f4959c2bcb18035725188b950ed_FULL -> xe-pw-155979v2_FULL
====================================================

Summary
-------

  **SUCCESS**

  No regressions found.

  

Participating hosts (4 -> 4)
------------------------------

  No changes in participating hosts

Known issues
------------

  Here are the changes found in xe-pw-155979v2_FULL that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@intel_hwmon@hwmon-write:
    - shard-adlp:         NOTRUN -> [SKIP][1] ([Intel XE#1125] / [Intel XE#5574])
   [1]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155979v2/shard-adlp-6/igt@intel_hwmon@hwmon-write.html

  * igt@kms_addfb_basic@size-max:
    - shard-adlp:         NOTRUN -> [DMESG-WARN][2] ([Intel XE#2953] / [Intel XE#4173])
   [2]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155979v2/shard-adlp-1/igt@kms_addfb_basic@size-max.html

  * igt@kms_atomic_transition@plane-all-modeset-transition-internal-panels:
    - shard-bmg:          NOTRUN -> [SKIP][3] ([Intel XE#2370])
   [3]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155979v2/shard-bmg-5/igt@kms_atomic_transition@plane-all-modeset-transition-internal-panels.html

  * igt@kms_big_fb@4-tiled-addfb-size-offset-overflow:
    - shard-adlp:         NOTRUN -> [SKIP][4] ([Intel XE#607])
   [4]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155979v2/shard-adlp-6/igt@kms_big_fb@4-tiled-addfb-size-offset-overflow.html

  * igt@kms_big_fb@x-tiled-16bpp-rotate-270:
    - shard-dg2-set2:     NOTRUN -> [SKIP][5] ([Intel XE#316]) +1 other test skip
   [5]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155979v2/shard-dg2-436/igt@kms_big_fb@x-tiled-16bpp-rotate-270.html

  * igt@kms_big_fb@x-tiled-max-hw-stride-64bpp-rotate-0:
    - shard-adlp:         NOTRUN -> [FAIL][6] ([Intel XE#1874])
   [6]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155979v2/shard-adlp-1/igt@kms_big_fb@x-tiled-max-hw-stride-64bpp-rotate-0.html

  * igt@kms_big_fb@y-tiled-64bpp-rotate-270:
    - shard-adlp:         NOTRUN -> [SKIP][7] ([Intel XE#316]) +4 other tests skip
   [7]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155979v2/shard-adlp-6/igt@kms_big_fb@y-tiled-64bpp-rotate-270.html

  * igt@kms_big_fb@y-tiled-max-hw-stride-32bpp-rotate-180:
    - shard-bmg:          NOTRUN -> [SKIP][8] ([Intel XE#1124]) +2 other tests skip
   [8]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155979v2/shard-bmg-8/igt@kms_big_fb@y-tiled-max-hw-stride-32bpp-rotate-180.html

  * igt@kms_big_fb@y-tiled-max-hw-stride-64bpp-rotate-180-hflip:
    - shard-adlp:         NOTRUN -> [DMESG-FAIL][9] ([Intel XE#4543]) +5 other tests dmesg-fail
   [9]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155979v2/shard-adlp-6/igt@kms_big_fb@y-tiled-max-hw-stride-64bpp-rotate-180-hflip.html

  * igt@kms_big_fb@yf-tiled-addfb-size-offset-overflow:
    - shard-bmg:          NOTRUN -> [SKIP][10] ([Intel XE#607])
   [10]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155979v2/shard-bmg-5/igt@kms_big_fb@yf-tiled-addfb-size-offset-overflow.html

  * igt@kms_big_fb@yf-tiled-max-hw-stride-32bpp-rotate-0:
    - shard-adlp:         NOTRUN -> [SKIP][11] ([Intel XE#1124]) +9 other tests skip
   [11]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155979v2/shard-adlp-1/igt@kms_big_fb@yf-tiled-max-hw-stride-32bpp-rotate-0.html

  * igt@kms_bw@connected-linear-tiling-1-displays-3840x2160p:
    - shard-adlp:         NOTRUN -> [SKIP][12] ([Intel XE#367]) +2 other tests skip
   [12]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155979v2/shard-adlp-8/igt@kms_bw@connected-linear-tiling-1-displays-3840x2160p.html

  * igt@kms_bw@connected-linear-tiling-2-displays-2560x1440p:
    - shard-adlp:         NOTRUN -> [SKIP][13] ([Intel XE#2191]) +3 other tests skip
   [13]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155979v2/shard-adlp-6/igt@kms_bw@connected-linear-tiling-2-displays-2560x1440p.html

  * igt@kms_bw@linear-tiling-3-displays-1920x1080p:
    - shard-bmg:          NOTRUN -> [SKIP][14] ([Intel XE#367])
   [14]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155979v2/shard-bmg-5/igt@kms_bw@linear-tiling-3-displays-1920x1080p.html

  * igt@kms_ccs@bad-pixel-format-4-tiled-dg2-mc-ccs:
    - shard-bmg:          NOTRUN -> [SKIP][15] ([Intel XE#2887]) +1 other test skip
   [15]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155979v2/shard-bmg-5/igt@kms_ccs@bad-pixel-format-4-tiled-dg2-mc-ccs.html

  * igt@kms_ccs@bad-rotation-90-y-tiled-gen12-rc-ccs-cc@pipe-a-hdmi-a-1:
    - shard-adlp:         NOTRUN -> [SKIP][16] ([Intel XE#787]) +44 other tests skip
   [16]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155979v2/shard-adlp-6/igt@kms_ccs@bad-rotation-90-y-tiled-gen12-rc-ccs-cc@pipe-a-hdmi-a-1.html

  * igt@kms_ccs@ccs-on-another-bo-4-tiled-mtl-rc-ccs:
    - shard-adlp:         NOTRUN -> [SKIP][17] ([Intel XE#455] / [Intel XE#787]) +29 other tests skip
   [17]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155979v2/shard-adlp-6/igt@kms_ccs@ccs-on-another-bo-4-tiled-mtl-rc-ccs.html

  * igt@kms_ccs@crc-primary-basic-4-tiled-bmg-ccs:
    - shard-dg2-set2:     NOTRUN -> [SKIP][18] ([Intel XE#2907])
   [18]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155979v2/shard-dg2-436/igt@kms_ccs@crc-primary-basic-4-tiled-bmg-ccs.html

  * igt@kms_ccs@crc-sprite-planes-basic-4-tiled-lnl-ccs:
    - shard-adlp:         NOTRUN -> [SKIP][19] ([Intel XE#2907])
   [19]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155979v2/shard-adlp-8/igt@kms_ccs@crc-sprite-planes-basic-4-tiled-lnl-ccs.html

  * igt@kms_ccs@missing-ccs-buffer-4-tiled-mtl-rc-ccs@pipe-c-hdmi-a-6:
    - shard-dg2-set2:     NOTRUN -> [SKIP][20] ([Intel XE#787]) +20 other tests skip
   [20]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155979v2/shard-dg2-433/igt@kms_ccs@missing-ccs-buffer-4-tiled-mtl-rc-ccs@pipe-c-hdmi-a-6.html

  * igt@kms_ccs@missing-ccs-buffer-4-tiled-mtl-rc-ccs@pipe-d-dp-4:
    - shard-dg2-set2:     NOTRUN -> [SKIP][21] ([Intel XE#455] / [Intel XE#787]) +7 other tests skip
   [21]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155979v2/shard-dg2-433/igt@kms_ccs@missing-ccs-buffer-4-tiled-mtl-rc-ccs@pipe-d-dp-4.html

  * igt@kms_ccs@random-ccs-data-4-tiled-dg2-mc-ccs@pipe-c-hdmi-a-6:
    - shard-dg2-set2:     NOTRUN -> [INCOMPLETE][22] ([Intel XE#1727] / [Intel XE#3113] / [Intel XE#6168])
   [22]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155979v2/shard-dg2-463/igt@kms_ccs@random-ccs-data-4-tiled-dg2-mc-ccs@pipe-c-hdmi-a-6.html

  * igt@kms_chamelium_audio@hdmi-audio:
    - shard-bmg:          NOTRUN -> [SKIP][23] ([Intel XE#2252]) +4 other tests skip
   [23]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155979v2/shard-bmg-5/igt@kms_chamelium_audio@hdmi-audio.html

  * igt@kms_chamelium_audio@hdmi-audio-edid:
    - shard-adlp:         NOTRUN -> [SKIP][24] ([Intel XE#373]) +9 other tests skip
   [24]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155979v2/shard-adlp-1/igt@kms_chamelium_audio@hdmi-audio-edid.html

  * igt@kms_chamelium_color@ctm-0-50:
    - shard-adlp:         NOTRUN -> [SKIP][25] ([Intel XE#306]) +2 other tests skip
   [25]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155979v2/shard-adlp-8/igt@kms_chamelium_color@ctm-0-50.html

  * igt@kms_chamelium_edid@dp-edid-change-during-suspend:
    - shard-dg2-set2:     NOTRUN -> [SKIP][26] ([Intel XE#373]) +2 other tests skip
   [26]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155979v2/shard-dg2-434/igt@kms_chamelium_edid@dp-edid-change-during-suspend.html

  * igt@kms_content_protection@dp-mst-type-0:
    - shard-bmg:          NOTRUN -> [SKIP][27] ([Intel XE#2390])
   [27]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155979v2/shard-bmg-5/igt@kms_content_protection@dp-mst-type-0.html

  * igt@kms_content_protection@legacy:
    - shard-adlp:         NOTRUN -> [SKIP][28] ([Intel XE#455]) +20 other tests skip
   [28]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155979v2/shard-adlp-6/igt@kms_content_protection@legacy.html

  * igt@kms_cursor_crc@cursor-sliding-512x170:
    - shard-adlp:         NOTRUN -> [SKIP][29] ([Intel XE#308]) +1 other test skip
   [29]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155979v2/shard-adlp-8/igt@kms_cursor_crc@cursor-sliding-512x170.html

  * igt@kms_cursor_crc@cursor-sliding-max-size:
    - shard-bmg:          NOTRUN -> [SKIP][30] ([Intel XE#2320]) +2 other tests skip
   [30]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155979v2/shard-bmg-5/igt@kms_cursor_crc@cursor-sliding-max-size.html

  * igt@kms_cursor_legacy@cursora-vs-flipb-atomic-transitions-varying-size:
    - shard-adlp:         NOTRUN -> [SKIP][31] ([Intel XE#309]) +2 other tests skip
   [31]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155979v2/shard-adlp-6/igt@kms_cursor_legacy@cursora-vs-flipb-atomic-transitions-varying-size.html

  * igt@kms_cursor_legacy@cursorb-vs-flipa-atomic:
    - shard-bmg:          [PASS][32] -> [SKIP][33] ([Intel XE#2291])
   [32]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3930-aaaff197c9186f4959c2bcb18035725188b950ed/shard-bmg-5/igt@kms_cursor_legacy@cursorb-vs-flipa-atomic.html
   [33]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155979v2/shard-bmg-6/igt@kms_cursor_legacy@cursorb-vs-flipa-atomic.html

  * igt@kms_cursor_legacy@short-busy-flip-before-cursor-atomic-transitions-varying-size:
    - shard-adlp:         NOTRUN -> [SKIP][34] ([Intel XE#323])
   [34]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155979v2/shard-adlp-1/igt@kms_cursor_legacy@short-busy-flip-before-cursor-atomic-transitions-varying-size.html

  * igt@kms_dirtyfb@drrs-dirtyfb-ioctl:
    - shard-bmg:          NOTRUN -> [SKIP][35] ([Intel XE#1508])
   [35]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155979v2/shard-bmg-5/igt@kms_dirtyfb@drrs-dirtyfb-ioctl.html

  * igt@kms_dp_linktrain_fallback@dp-fallback:
    - shard-adlp:         NOTRUN -> [SKIP][36] ([Intel XE#4331])
   [36]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155979v2/shard-adlp-1/igt@kms_dp_linktrain_fallback@dp-fallback.html

  * igt@kms_dsc@dsc-with-output-formats:
    - shard-bmg:          NOTRUN -> [SKIP][37] ([Intel XE#2244])
   [37]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155979v2/shard-bmg-5/igt@kms_dsc@dsc-with-output-formats.html

  * igt@kms_fbc_dirty_rect@fbc-dirty-rectangle-dirtyfb-tests:
    - shard-adlp:         NOTRUN -> [SKIP][38] ([Intel XE#4422]) +1 other test skip
   [38]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155979v2/shard-adlp-8/igt@kms_fbc_dirty_rect@fbc-dirty-rectangle-dirtyfb-tests.html

  * igt@kms_flip@2x-flip-vs-dpms:
    - shard-bmg:          [PASS][39] -> [SKIP][40] ([Intel XE#2316]) +1 other test skip
   [39]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3930-aaaff197c9186f4959c2bcb18035725188b950ed/shard-bmg-7/igt@kms_flip@2x-flip-vs-dpms.html
   [40]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155979v2/shard-bmg-6/igt@kms_flip@2x-flip-vs-dpms.html

  * igt@kms_flip@2x-flip-vs-dpms-on-nop-interruptible:
    - shard-adlp:         NOTRUN -> [SKIP][41] ([Intel XE#310]) +5 other tests skip
   [41]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155979v2/shard-adlp-6/igt@kms_flip@2x-flip-vs-dpms-on-nop-interruptible.html

  * igt@kms_flip@dpms-off-confusion-interruptible@c-hdmi-a1:
    - shard-adlp:         [PASS][42] -> [DMESG-WARN][43] ([Intel XE#4543]) +2 other tests dmesg-warn
   [42]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3930-aaaff197c9186f4959c2bcb18035725188b950ed/shard-adlp-9/igt@kms_flip@dpms-off-confusion-interruptible@c-hdmi-a1.html
   [43]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155979v2/shard-adlp-1/igt@kms_flip@dpms-off-confusion-interruptible@c-hdmi-a1.html

  * igt@kms_flip@flip-vs-expired-vblank-interruptible@d-hdmi-a1:
    - shard-adlp:         NOTRUN -> [DMESG-WARN][44] ([Intel XE#4543]) +8 other tests dmesg-warn
   [44]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155979v2/shard-adlp-6/igt@kms_flip@flip-vs-expired-vblank-interruptible@d-hdmi-a1.html

  * igt@kms_flip@flip-vs-expired-vblank@a-edp1:
    - shard-lnl:          [PASS][45] -> [FAIL][46] ([Intel XE#301]) +2 other tests fail
   [45]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3930-aaaff197c9186f4959c2bcb18035725188b950ed/shard-lnl-4/igt@kms_flip@flip-vs-expired-vblank@a-edp1.html
   [46]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155979v2/shard-lnl-2/igt@kms_flip@flip-vs-expired-vblank@a-edp1.html

  * igt@kms_flip@flip-vs-panning-interruptible:
    - shard-adlp:         NOTRUN -> [DMESG-WARN][47] ([Intel XE#4543] / [Intel XE#5208])
   [47]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155979v2/shard-adlp-1/igt@kms_flip@flip-vs-panning-interruptible.html

  * igt@kms_flip_scaled_crc@flip-64bpp-4tile-to-32bpp-4tiledg2rcccs-downscaling:
    - shard-bmg:          NOTRUN -> [SKIP][48] ([Intel XE#2380]) +1 other test skip
   [48]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155979v2/shard-bmg-8/igt@kms_flip_scaled_crc@flip-64bpp-4tile-to-32bpp-4tiledg2rcccs-downscaling.html

  * igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-16bpp-ytile-upscaling:
    - shard-bmg:          NOTRUN -> [SKIP][49] ([Intel XE#2293] / [Intel XE#2380])
   [49]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155979v2/shard-bmg-5/igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-16bpp-ytile-upscaling.html

  * igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-16bpp-ytile-upscaling@pipe-a-valid-mode:
    - shard-bmg:          NOTRUN -> [SKIP][50] ([Intel XE#2293])
   [50]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155979v2/shard-bmg-5/igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-16bpp-ytile-upscaling@pipe-a-valid-mode.html

  * igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-32bpp-ytile-downscaling:
    - shard-dg2-set2:     NOTRUN -> [SKIP][51] ([Intel XE#455]) +8 other tests skip
   [51]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155979v2/shard-dg2-436/igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-32bpp-ytile-downscaling.html

  * igt@kms_frontbuffer_tracking@drrs-modesetfrombusy:
    - shard-adlp:         NOTRUN -> [SKIP][52] ([Intel XE#651]) +11 other tests skip
   [52]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155979v2/shard-adlp-8/igt@kms_frontbuffer_tracking@drrs-modesetfrombusy.html

  * igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-spr-indfb-draw-mmap-wc:
    - shard-lnl:          NOTRUN -> [SKIP][53] ([Intel XE#656])
   [53]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155979v2/shard-lnl-7/igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-spr-indfb-draw-mmap-wc.html

  * igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-spr-indfb-draw-render:
    - shard-bmg:          NOTRUN -> [SKIP][54] ([Intel XE#5390]) +4 other tests skip
   [54]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155979v2/shard-bmg-5/igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-spr-indfb-draw-render.html

  * igt@kms_frontbuffer_tracking@fbcdrrs-1p-primscrn-pri-indfb-draw-blt:
    - shard-dg2-set2:     NOTRUN -> [SKIP][55] ([Intel XE#651]) +5 other tests skip
   [55]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155979v2/shard-dg2-433/igt@kms_frontbuffer_tracking@fbcdrrs-1p-primscrn-pri-indfb-draw-blt.html

  * igt@kms_frontbuffer_tracking@fbcdrrs-1p-primscrn-shrfb-msflip-blt:
    - shard-bmg:          NOTRUN -> [SKIP][56] ([Intel XE#2311]) +6 other tests skip
   [56]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155979v2/shard-bmg-5/igt@kms_frontbuffer_tracking@fbcdrrs-1p-primscrn-shrfb-msflip-blt.html

  * igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-indfb-msflip-blt:
    - shard-dg2-set2:     NOTRUN -> [SKIP][57] ([Intel XE#653]) +11 other tests skip
   [57]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155979v2/shard-dg2-433/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-indfb-msflip-blt.html

  * igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-pri-indfb-draw-mmap-wc:
    - shard-adlp:         NOTRUN -> [SKIP][58] ([Intel XE#653]) +11 other tests skip
   [58]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155979v2/shard-adlp-6/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-pri-indfb-draw-mmap-wc.html

  * igt@kms_frontbuffer_tracking@fbcpsr-2p-pri-indfb-multidraw:
    - shard-bmg:          NOTRUN -> [SKIP][59] ([Intel XE#2313]) +6 other tests skip
   [59]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155979v2/shard-bmg-5/igt@kms_frontbuffer_tracking@fbcpsr-2p-pri-indfb-multidraw.html

  * igt@kms_frontbuffer_tracking@psr-2p-scndscrn-pri-shrfb-draw-blt:
    - shard-adlp:         NOTRUN -> [SKIP][60] ([Intel XE#656]) +35 other tests skip
   [60]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155979v2/shard-adlp-1/igt@kms_frontbuffer_tracking@psr-2p-scndscrn-pri-shrfb-draw-blt.html

  * igt@kms_hdr@invalid-hdr:
    - shard-bmg:          [PASS][61] -> [SKIP][62] ([Intel XE#1503])
   [61]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3930-aaaff197c9186f4959c2bcb18035725188b950ed/shard-bmg-6/igt@kms_hdr@invalid-hdr.html
   [62]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155979v2/shard-bmg-5/igt@kms_hdr@invalid-hdr.html

  * igt@kms_joiner@basic-ultra-joiner:
    - shard-adlp:         NOTRUN -> [SKIP][63] ([Intel XE#2927])
   [63]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155979v2/shard-adlp-8/igt@kms_joiner@basic-ultra-joiner.html

  * igt@kms_plane@pixel-format-source-clamping@pipe-b-plane-0:
    - shard-adlp:         NOTRUN -> [FAIL][64] ([Intel XE#5195]) +4 other tests fail
   [64]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155979v2/shard-adlp-8/igt@kms_plane@pixel-format-source-clamping@pipe-b-plane-0.html

  * igt@kms_plane_lowres@tiling-y:
    - shard-bmg:          NOTRUN -> [SKIP][65] ([Intel XE#2393])
   [65]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155979v2/shard-bmg-5/igt@kms_plane_lowres@tiling-y.html

  * igt@kms_pm_backlight@fade-with-dpms:
    - shard-adlp:         NOTRUN -> [SKIP][66] ([Intel XE#870])
   [66]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155979v2/shard-adlp-6/igt@kms_pm_backlight@fade-with-dpms.html

  * igt@kms_pm_dc@dc5-retention-flops:
    - shard-adlp:         NOTRUN -> [SKIP][67] ([Intel XE#3309])
   [67]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155979v2/shard-adlp-6/igt@kms_pm_dc@dc5-retention-flops.html

  * igt@kms_pm_dc@dc9-dpms:
    - shard-adlp:         NOTRUN -> [SKIP][68] ([Intel XE#734])
   [68]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155979v2/shard-adlp-8/igt@kms_pm_dc@dc9-dpms.html

  * igt@kms_psr2_sf@fbc-pr-overlay-plane-move-continuous-exceed-sf:
    - shard-dg2-set2:     NOTRUN -> [SKIP][69] ([Intel XE#1406] / [Intel XE#1489])
   [69]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155979v2/shard-dg2-436/igt@kms_psr2_sf@fbc-pr-overlay-plane-move-continuous-exceed-sf.html

  * igt@kms_psr2_sf@fbc-pr-overlay-primary-update-sf-dmg-area:
    - shard-bmg:          NOTRUN -> [SKIP][70] ([Intel XE#1406] / [Intel XE#1489]) +3 other tests skip
   [70]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155979v2/shard-bmg-5/igt@kms_psr2_sf@fbc-pr-overlay-primary-update-sf-dmg-area.html

  * igt@kms_psr2_sf@fbc-psr2-cursor-plane-move-continuous-sf:
    - shard-adlp:         NOTRUN -> [SKIP][71] ([Intel XE#1406] / [Intel XE#1489]) +8 other tests skip
   [71]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155979v2/shard-adlp-1/igt@kms_psr2_sf@fbc-psr2-cursor-plane-move-continuous-sf.html

  * igt@kms_psr@fbc-psr2-cursor-plane-move:
    - shard-dg2-set2:     NOTRUN -> [SKIP][72] ([Intel XE#1406] / [Intel XE#2850] / [Intel XE#929]) +2 other tests skip
   [72]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155979v2/shard-dg2-436/igt@kms_psr@fbc-psr2-cursor-plane-move.html

  * igt@kms_psr@psr-cursor-plane-onoff:
    - shard-adlp:         NOTRUN -> [SKIP][73] ([Intel XE#1406] / [Intel XE#2850] / [Intel XE#929]) +9 other tests skip
   [73]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155979v2/shard-adlp-1/igt@kms_psr@psr-cursor-plane-onoff.html

  * igt@kms_psr@psr-sprite-plane-onoff:
    - shard-bmg:          NOTRUN -> [SKIP][74] ([Intel XE#1406] / [Intel XE#2234] / [Intel XE#2850]) +4 other tests skip
   [74]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155979v2/shard-bmg-5/igt@kms_psr@psr-sprite-plane-onoff.html

  * igt@kms_rotation_crc@primary-y-tiled-reflect-x-270:
    - shard-bmg:          NOTRUN -> [SKIP][75] ([Intel XE#3414] / [Intel XE#3904])
   [75]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155979v2/shard-bmg-5/igt@kms_rotation_crc@primary-y-tiled-reflect-x-270.html

  * igt@kms_rotation_crc@primary-yf-tiled-reflect-x-90:
    - shard-adlp:         NOTRUN -> [SKIP][76] ([Intel XE#3414]) +1 other test skip
   [76]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155979v2/shard-adlp-6/igt@kms_rotation_crc@primary-yf-tiled-reflect-x-90.html

  * igt@kms_vrr@negative-basic:
    - shard-bmg:          [PASS][77] -> [SKIP][78] ([Intel XE#1499])
   [77]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3930-aaaff197c9186f4959c2bcb18035725188b950ed/shard-bmg-5/igt@kms_vrr@negative-basic.html
   [78]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155979v2/shard-bmg-6/igt@kms_vrr@negative-basic.html

  * igt@kms_vrr@seamless-rr-switch-drrs:
    - shard-bmg:          NOTRUN -> [SKIP][79] ([Intel XE#1499])
   [79]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155979v2/shard-bmg-5/igt@kms_vrr@seamless-rr-switch-drrs.html

  * igt@xe_ccs@suspend-resume:
    - shard-adlp:         NOTRUN -> [SKIP][80] ([Intel XE#455] / [Intel XE#488] / [Intel XE#5607]) +1 other test skip
   [80]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155979v2/shard-adlp-6/igt@xe_ccs@suspend-resume.html

  * igt@xe_configfs@survivability-mode:
    - shard-adlp:         NOTRUN -> [SKIP][81] ([Intel XE#6010])
   [81]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155979v2/shard-adlp-1/igt@xe_configfs@survivability-mode.html

  * igt@xe_copy_basic@mem-copy-linear-0xfffe:
    - shard-adlp:         NOTRUN -> [SKIP][82] ([Intel XE#1123])
   [82]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155979v2/shard-adlp-8/igt@xe_copy_basic@mem-copy-linear-0xfffe.html

  * igt@xe_copy_basic@mem-set-linear-0x369:
    - shard-dg2-set2:     NOTRUN -> [SKIP][83] ([Intel XE#1126])
   [83]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155979v2/shard-dg2-433/igt@xe_copy_basic@mem-set-linear-0x369.html

  * igt@xe_eu_stall@invalid-gt-id:
    - shard-dg2-set2:     NOTRUN -> [SKIP][84] ([Intel XE#5626])
   [84]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155979v2/shard-dg2-436/igt@xe_eu_stall@invalid-gt-id.html

  * igt@xe_eu_stall@non-blocking-re-enable:
    - shard-adlp:         NOTRUN -> [SKIP][85] ([Intel XE#5626])
   [85]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155979v2/shard-adlp-1/igt@xe_eu_stall@non-blocking-re-enable.html

  * igt@xe_eudebug@basic-vm-access-parameters-userptr-faultable:
    - shard-bmg:          NOTRUN -> [SKIP][86] ([Intel XE#4837]) +2 other tests skip
   [86]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155979v2/shard-bmg-5/igt@xe_eudebug@basic-vm-access-parameters-userptr-faultable.html

  * igt@xe_eudebug@basic-vm-bind-discovery:
    - shard-lnl:          NOTRUN -> [SKIP][87] ([Intel XE#4837])
   [87]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155979v2/shard-lnl-7/igt@xe_eudebug@basic-vm-bind-discovery.html

  * igt@xe_eudebug@discovery-empty:
    - shard-adlp:         NOTRUN -> [SKIP][88] ([Intel XE#4837] / [Intel XE#5565]) +12 other tests skip
   [88]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155979v2/shard-adlp-1/igt@xe_eudebug@discovery-empty.html

  * igt@xe_eudebug_online@writes-caching-sram-bb-vram-target-vram:
    - shard-dg2-set2:     NOTRUN -> [SKIP][89] ([Intel XE#4837])
   [89]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155979v2/shard-dg2-433/igt@xe_eudebug_online@writes-caching-sram-bb-vram-target-vram.html

  * igt@xe_evict@evict-beng-large-external-cm:
    - shard-adlp:         NOTRUN -> [SKIP][90] ([Intel XE#261] / [Intel XE#5564]) +1 other test skip
   [90]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155979v2/shard-adlp-6/igt@xe_evict@evict-beng-large-external-cm.html

  * igt@xe_evict@evict-mixed-many-threads-small:
    - shard-bmg:          [PASS][91] -> [INCOMPLETE][92] ([Intel XE#6321]) +1 other test incomplete
   [91]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3930-aaaff197c9186f4959c2bcb18035725188b950ed/shard-bmg-2/igt@xe_evict@evict-mixed-many-threads-small.html
   [92]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155979v2/shard-bmg-2/igt@xe_evict@evict-mixed-many-threads-small.html

  * igt@xe_evict@evict-threads-large:
    - shard-adlp:         NOTRUN -> [SKIP][93] ([Intel XE#261]) +3 other tests skip
   [93]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155979v2/shard-adlp-6/igt@xe_evict@evict-threads-large.html

  * igt@xe_evict_ccs@evict-overcommit-parallel-nofree-reopen:
    - shard-adlp:         NOTRUN -> [SKIP][94] ([Intel XE#688]) +1 other test skip
   [94]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155979v2/shard-adlp-1/igt@xe_evict_ccs@evict-overcommit-parallel-nofree-reopen.html

  * igt@xe_exec_balancer@once-virtual-rebind:
    - shard-adlp:         [PASS][95] -> [DMESG-FAIL][96] ([Intel XE#3876]) +1 other test dmesg-fail
   [95]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3930-aaaff197c9186f4959c2bcb18035725188b950ed/shard-adlp-2/igt@xe_exec_balancer@once-virtual-rebind.html
   [96]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155979v2/shard-adlp-9/igt@xe_exec_balancer@once-virtual-rebind.html

  * igt@xe_exec_basic@multigpu-once-bindexecqueue-userptr-rebind:
    - shard-adlp:         NOTRUN -> [SKIP][97] ([Intel XE#1392] / [Intel XE#5575]) +9 other tests skip
   [97]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155979v2/shard-adlp-1/igt@xe_exec_basic@multigpu-once-bindexecqueue-userptr-rebind.html

  * igt@xe_exec_basic@multigpu-once-null-defer-mmap:
    - shard-bmg:          NOTRUN -> [SKIP][98] ([Intel XE#2322]) +1 other test skip
   [98]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155979v2/shard-bmg-5/igt@xe_exec_basic@multigpu-once-null-defer-mmap.html

  * igt@xe_exec_fault_mode@once-bindexecqueue-rebind-prefetch:
    - shard-dg2-set2:     NOTRUN -> [SKIP][99] ([Intel XE#288]) +9 other tests skip
   [99]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155979v2/shard-dg2-436/igt@xe_exec_fault_mode@once-bindexecqueue-rebind-prefetch.html

  * igt@xe_exec_fault_mode@twice-bindexecqueue-userptr-prefetch:
    - shard-adlp:         NOTRUN -> [SKIP][100] ([Intel XE#288] / [Intel XE#5561]) +19 other tests skip
   [100]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155979v2/shard-adlp-1/igt@xe_exec_fault_mode@twice-bindexecqueue-userptr-prefetch.html

  * igt@xe_exec_reset@cat-error:
    - shard-adlp:         NOTRUN -> [DMESG-WARN][101] ([Intel XE#3868])
   [101]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155979v2/shard-adlp-8/igt@xe_exec_reset@cat-error.html

  * igt@xe_exec_system_allocator@once-mmap-huge-nomemset:
    - shard-bmg:          NOTRUN -> [SKIP][102] ([Intel XE#4943]) +2 other tests skip
   [102]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155979v2/shard-bmg-5/igt@xe_exec_system_allocator@once-mmap-huge-nomemset.html

  * igt@xe_exec_system_allocator@once-mmap-remap-ro-dontunmap:
    - shard-adlp:         NOTRUN -> [SKIP][103] ([Intel XE#4915]) +237 other tests skip
   [103]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155979v2/shard-adlp-1/igt@xe_exec_system_allocator@once-mmap-remap-ro-dontunmap.html

  * igt@xe_exec_system_allocator@process-many-large-execqueues-mmap-shared-remap-eocheck:
    - shard-dg2-set2:     NOTRUN -> [SKIP][104] ([Intel XE#4915]) +80 other tests skip
   [104]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155979v2/shard-dg2-434/igt@xe_exec_system_allocator@process-many-large-execqueues-mmap-shared-remap-eocheck.html

  * igt@xe_fault_injection@probe-fail-guc-xe_guc_ct_send_recv:
    - shard-adlp:         NOTRUN -> [ABORT][105] ([Intel XE#5530])
   [105]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155979v2/shard-adlp-8/igt@xe_fault_injection@probe-fail-guc-xe_guc_ct_send_recv.html

  * igt@xe_oa@invalid-oa-format-id:
    - shard-adlp:         NOTRUN -> [SKIP][106] ([Intel XE#3573]) +6 other tests skip
   [106]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155979v2/shard-adlp-1/igt@xe_oa@invalid-oa-format-id.html

  * igt@xe_oa@oa-exponents:
    - shard-dg2-set2:     NOTRUN -> [SKIP][107] ([Intel XE#3573])
   [107]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155979v2/shard-dg2-433/igt@xe_oa@oa-exponents.html

  * igt@xe_pat@display-vs-wb-transient:
    - shard-adlp:         NOTRUN -> [SKIP][108] ([Intel XE#1337] / [Intel XE#5572])
   [108]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155979v2/shard-adlp-6/igt@xe_pat@display-vs-wb-transient.html

  * igt@xe_pat@pat-index-xehpc:
    - shard-adlp:         NOTRUN -> [SKIP][109] ([Intel XE#2838] / [Intel XE#979])
   [109]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155979v2/shard-adlp-1/igt@xe_pat@pat-index-xehpc.html

  * igt@xe_pm@d3cold-mmap-vram:
    - shard-adlp:         NOTRUN -> [SKIP][110] ([Intel XE#2284] / [Intel XE#366])
   [110]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155979v2/shard-adlp-6/igt@xe_pm@d3cold-mmap-vram.html

  * igt@xe_pm@s2idle-d3cold-basic-exec:
    - shard-dg2-set2:     NOTRUN -> [SKIP][111] ([Intel XE#2284] / [Intel XE#366]) +1 other test skip
   [111]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155979v2/shard-dg2-436/igt@xe_pm@s2idle-d3cold-basic-exec.html

  * igt@xe_pmu@all-fn-engine-activity-load@engine-drm_xe_engine_class_render0:
    - shard-adlp:         NOTRUN -> [TIMEOUT][112] ([Intel XE#5213]) +1 other test timeout
   [112]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155979v2/shard-adlp-1/igt@xe_pmu@all-fn-engine-activity-load@engine-drm_xe_engine_class_render0.html

  * igt@xe_pxp@pxp-src-to-pxp-dest-rendercopy:
    - shard-bmg:          NOTRUN -> [SKIP][113] ([Intel XE#4733])
   [113]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155979v2/shard-bmg-5/igt@xe_pxp@pxp-src-to-pxp-dest-rendercopy.html

  * igt@xe_pxp@pxp-stale-bo-bind-post-termination-irq:
    - shard-adlp:         NOTRUN -> [SKIP][114] ([Intel XE#4733] / [Intel XE#5594]) +2 other tests skip
   [114]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155979v2/shard-adlp-1/igt@xe_pxp@pxp-stale-bo-bind-post-termination-irq.html

  * igt@xe_query@multigpu-query-engines:
    - shard-dg2-set2:     NOTRUN -> [SKIP][115] ([Intel XE#944])
   [115]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155979v2/shard-dg2-433/igt@xe_query@multigpu-query-engines.html

  * igt@xe_query@multigpu-query-topology:
    - shard-bmg:          NOTRUN -> [SKIP][116] ([Intel XE#944])
   [116]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155979v2/shard-bmg-5/igt@xe_query@multigpu-query-topology.html

  * igt@xe_query@multigpu-query-uc-fw-version-huc:
    - shard-adlp:         NOTRUN -> [SKIP][117] ([Intel XE#944]) +2 other tests skip
   [117]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155979v2/shard-adlp-6/igt@xe_query@multigpu-query-uc-fw-version-huc.html

  * igt@xe_render_copy@render-stress-4-copies:
    - shard-adlp:         NOTRUN -> [SKIP][118] ([Intel XE#4814] / [Intel XE#5614])
   [118]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155979v2/shard-adlp-6/igt@xe_render_copy@render-stress-4-copies.html

  * igt@xe_spin_batch@spin-mem-copy:
    - shard-adlp:         NOTRUN -> [SKIP][119] ([Intel XE#4821])
   [119]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155979v2/shard-adlp-1/igt@xe_spin_batch@spin-mem-copy.html

  * igt@xe_sriov_scheduling@equal-throughput:
    - shard-adlp:         NOTRUN -> [DMESG-FAIL][120] ([Intel XE#3868] / [Intel XE#5213]) +1 other test dmesg-fail
   [120]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155979v2/shard-adlp-8/igt@xe_sriov_scheduling@equal-throughput.html

  
#### Possible fixes ####

  * igt@kms_ccs@crc-primary-suspend-4-tiled-dg2-mc-ccs@pipe-d-dp-4:
    - shard-dg2-set2:     [INCOMPLETE][121] ([Intel XE#3862]) -> [PASS][122] +1 other test pass
   [121]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3930-aaaff197c9186f4959c2bcb18035725188b950ed/shard-dg2-466/igt@kms_ccs@crc-primary-suspend-4-tiled-dg2-mc-ccs@pipe-d-dp-4.html
   [122]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155979v2/shard-dg2-436/igt@kms_ccs@crc-primary-suspend-4-tiled-dg2-mc-ccs@pipe-d-dp-4.html

  * igt@kms_ccs@random-ccs-data-4-tiled-dg2-mc-ccs@pipe-b-hdmi-a-6:
    - shard-dg2-set2:     [INCOMPLETE][123] ([Intel XE#1727] / [Intel XE#3113] / [Intel XE#4345] / [Intel XE#6168]) -> [PASS][124]
   [123]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3930-aaaff197c9186f4959c2bcb18035725188b950ed/shard-dg2-436/igt@kms_ccs@random-ccs-data-4-tiled-dg2-mc-ccs@pipe-b-hdmi-a-6.html
   [124]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155979v2/shard-dg2-463/igt@kms_ccs@random-ccs-data-4-tiled-dg2-mc-ccs@pipe-b-hdmi-a-6.html

  * igt@kms_ccs@random-ccs-data-4-tiled-dg2-rc-ccs-cc:
    - shard-dg2-set2:     [INCOMPLETE][125] ([Intel XE#1727] / [Intel XE#2705] / [Intel XE#3113] / [Intel XE#4212] / [Intel XE#4345] / [Intel XE#4522]) -> [PASS][126]
   [125]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3930-aaaff197c9186f4959c2bcb18035725188b950ed/shard-dg2-464/igt@kms_ccs@random-ccs-data-4-tiled-dg2-rc-ccs-cc.html
   [126]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155979v2/shard-dg2-436/igt@kms_ccs@random-ccs-data-4-tiled-dg2-rc-ccs-cc.html

  * igt@kms_ccs@random-ccs-data-4-tiled-dg2-rc-ccs-cc@pipe-a-hdmi-a-6:
    - shard-dg2-set2:     [INCOMPLETE][127] ([Intel XE#1727] / [Intel XE#2705] / [Intel XE#3113] / [Intel XE#4212] / [Intel XE#4522]) -> [PASS][128]
   [127]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3930-aaaff197c9186f4959c2bcb18035725188b950ed/shard-dg2-464/igt@kms_ccs@random-ccs-data-4-tiled-dg2-rc-ccs-cc@pipe-a-hdmi-a-6.html
   [128]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155979v2/shard-dg2-436/igt@kms_ccs@random-ccs-data-4-tiled-dg2-rc-ccs-cc@pipe-a-hdmi-a-6.html

  * igt@kms_cursor_legacy@cursorb-vs-flipa-atomic-transitions-varying-size:
    - shard-bmg:          [SKIP][129] ([Intel XE#2291]) -> [PASS][130] +4 other tests pass
   [129]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3930-aaaff197c9186f4959c2bcb18035725188b950ed/shard-bmg-6/igt@kms_cursor_legacy@cursorb-vs-flipa-atomic-transitions-varying-size.html
   [130]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155979v2/shard-bmg-3/igt@kms_cursor_legacy@cursorb-vs-flipa-atomic-transitions-varying-size.html

  * igt@kms_cursor_legacy@flip-vs-cursor-atomic:
    - shard-bmg:          [FAIL][131] ([Intel XE#1475]) -> [PASS][132] +1 other test pass
   [131]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3930-aaaff197c9186f4959c2bcb18035725188b950ed/shard-bmg-1/igt@kms_cursor_legacy@flip-vs-cursor-atomic.html
   [132]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155979v2/shard-bmg-4/igt@kms_cursor_legacy@flip-vs-cursor-atomic.html

  * igt@kms_cursor_legacy@flip-vs-cursor-legacy:
    - shard-bmg:          [FAIL][133] ([Intel XE#5299]) -> [PASS][134]
   [133]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3930-aaaff197c9186f4959c2bcb18035725188b950ed/shard-bmg-7/igt@kms_cursor_legacy@flip-vs-cursor-legacy.html
   [134]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155979v2/shard-bmg-2/igt@kms_cursor_legacy@flip-vs-cursor-legacy.html

  * igt@kms_flip@2x-plain-flip-fb-recreate-interruptible:
    - shard-bmg:          [SKIP][135] ([Intel XE#2316]) -> [PASS][136] +5 other tests pass
   [135]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3930-aaaff197c9186f4959c2bcb18035725188b950ed/shard-bmg-6/igt@kms_flip@2x-plain-flip-fb-recreate-interruptible.html
   [136]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155979v2/shard-bmg-3/igt@kms_flip@2x-plain-flip-fb-recreate-interruptible.html

  * igt@kms_flip@flip-vs-expired-vblank-interruptible:
    - shard-lnl:          [FAIL][137] ([Intel XE#301] / [Intel XE#3149]) -> [PASS][138]
   [137]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3930-aaaff197c9186f4959c2bcb18035725188b950ed/shard-lnl-1/igt@kms_flip@flip-vs-expired-vblank-interruptible.html
   [138]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155979v2/shard-lnl-3/igt@kms_flip@flip-vs-expired-vblank-interruptible.html

  * igt@kms_flip@flip-vs-expired-vblank-interruptible@c-edp1:
    - shard-lnl:          [FAIL][139] ([Intel XE#301]) -> [PASS][140]
   [139]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3930-aaaff197c9186f4959c2bcb18035725188b950ed/shard-lnl-1/igt@kms_flip@flip-vs-expired-vblank-interruptible@c-edp1.html
   [140]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155979v2/shard-lnl-3/igt@kms_flip@flip-vs-expired-vblank-interruptible@c-edp1.html

  * igt@kms_flip@plain-flip-ts-check-interruptible@b-hdmi-a1:
    - shard-adlp:         [DMESG-WARN][141] ([Intel XE#4543]) -> [PASS][142] +2 other tests pass
   [141]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3930-aaaff197c9186f4959c2bcb18035725188b950ed/shard-adlp-8/igt@kms_flip@plain-flip-ts-check-interruptible@b-hdmi-a1.html
   [142]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155979v2/shard-adlp-9/igt@kms_flip@plain-flip-ts-check-interruptible@b-hdmi-a1.html

  * {igt@kms_frontbuffer_tracking@fbc-1p-offscreen-pri-indfb-draw-mmap-wc}:
    - shard-adlp:         [DMESG-WARN][143] ([Intel XE#2953] / [Intel XE#4173]) -> [PASS][144]
   [143]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3930-aaaff197c9186f4959c2bcb18035725188b950ed/shard-adlp-9/igt@kms_frontbuffer_tracking@fbc-1p-offscreen-pri-indfb-draw-mmap-wc.html
   [144]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155979v2/shard-adlp-1/igt@kms_frontbuffer_tracking@fbc-1p-offscreen-pri-indfb-draw-mmap-wc.html

  * igt@kms_joiner@invalid-modeset-force-big-joiner:
    - shard-bmg:          [SKIP][145] ([Intel XE#3012]) -> [PASS][146]
   [145]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3930-aaaff197c9186f4959c2bcb18035725188b950ed/shard-bmg-6/igt@kms_joiner@invalid-modeset-force-big-joiner.html
   [146]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155979v2/shard-bmg-5/igt@kms_joiner@invalid-modeset-force-big-joiner.html

  * igt@kms_vrr@cmrr@pipe-a-edp-1:
    - shard-lnl:          [FAIL][147] ([Intel XE#4459]) -> [PASS][148] +1 other test pass
   [147]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3930-aaaff197c9186f4959c2bcb18035725188b950ed/shard-lnl-3/igt@kms_vrr@cmrr@pipe-a-edp-1.html
   [148]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155979v2/shard-lnl-8/igt@kms_vrr@cmrr@pipe-a-edp-1.html

  * {igt@xe_exec_system_allocator@many-stride-malloc-prefetch}:
    - shard-bmg:          [WARN][149] ([Intel XE#5786]) -> [PASS][150]
   [149]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3930-aaaff197c9186f4959c2bcb18035725188b950ed/shard-bmg-7/igt@xe_exec_system_allocator@many-stride-malloc-prefetch.html
   [150]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155979v2/shard-bmg-2/igt@xe_exec_system_allocator@many-stride-malloc-prefetch.html

  
#### Warnings ####

  * igt@kms_async_flips@async-flip-suspend-resume:
    - shard-adlp:         [DMESG-WARN][151] ([Intel XE#2953] / [Intel XE#4173] / [Intel XE#4543]) -> [DMESG-WARN][152] ([Intel XE#4543]) +1 other test dmesg-warn
   [151]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3930-aaaff197c9186f4959c2bcb18035725188b950ed/shard-adlp-9/igt@kms_async_flips@async-flip-suspend-resume.html
   [152]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155979v2/shard-adlp-1/igt@kms_async_flips@async-flip-suspend-resume.html

  * igt@kms_content_protection@uevent:
    - shard-bmg:          [FAIL][153] ([Intel XE#1188]) -> [SKIP][154] ([Intel XE#2341])
   [153]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3930-aaaff197c9186f4959c2bcb18035725188b950ed/shard-bmg-5/igt@kms_content_protection@uevent.html
   [154]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155979v2/shard-bmg-6/igt@kms_content_protection@uevent.html

  * igt@kms_flip@flip-vs-expired-vblank@b-hdmi-a1:
    - shard-adlp:         [DMESG-FAIL][155] ([Intel XE#4543]) -> [DMESG-WARN][156] ([Intel XE#4543]) +1 other test dmesg-warn
   [155]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3930-aaaff197c9186f4959c2bcb18035725188b950ed/shard-adlp-9/igt@kms_flip@flip-vs-expired-vblank@b-hdmi-a1.html
   [156]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155979v2/shard-adlp-8/igt@kms_flip@flip-vs-expired-vblank@b-hdmi-a1.html

  * igt@kms_frontbuffer_tracking@drrs-2p-primscrn-cur-indfb-draw-blt:
    - shard-bmg:          [SKIP][157] ([Intel XE#2311]) -> [SKIP][158] ([Intel XE#2312]) +7 other tests skip
   [157]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3930-aaaff197c9186f4959c2bcb18035725188b950ed/shard-bmg-5/igt@kms_frontbuffer_tracking@drrs-2p-primscrn-cur-indfb-draw-blt.html
   [158]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155979v2/shard-bmg-6/igt@kms_frontbuffer_tracking@drrs-2p-primscrn-cur-indfb-draw-blt.html

  * igt@kms_frontbuffer_tracking@drrs-2p-primscrn-cur-indfb-draw-render:
    - shard-bmg:          [SKIP][159] ([Intel XE#2312]) -> [SKIP][160] ([Intel XE#2311]) +10 other tests skip
   [159]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3930-aaaff197c9186f4959c2bcb18035725188b950ed/shard-bmg-6/igt@kms_frontbuffer_tracking@drrs-2p-primscrn-cur-indfb-draw-render.html
   [160]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155979v2/shard-bmg-4/igt@kms_frontbuffer_tracking@drrs-2p-primscrn-cur-indfb-draw-render.html

  * igt@kms_frontbuffer_tracking@fbc-2p-primscrn-indfb-pgflip-blt:
    - shard-bmg:          [SKIP][161] ([Intel XE#5390]) -> [SKIP][162] ([Intel XE#2312]) +4 other tests skip
   [161]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3930-aaaff197c9186f4959c2bcb18035725188b950ed/shard-bmg-7/igt@kms_frontbuffer_tracking@fbc-2p-primscrn-indfb-pgflip-blt.html
   [162]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155979v2/shard-bmg-6/igt@kms_frontbuffer_tracking@fbc-2p-primscrn-indfb-pgflip-blt.html

  * igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-cur-indfb-draw-render:
    - shard-bmg:          [SKIP][163] ([Intel XE#2312]) -> [SKIP][164] ([Intel XE#5390]) +6 other tests skip
   [163]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3930-aaaff197c9186f4959c2bcb18035725188b950ed/shard-bmg-6/igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-cur-indfb-draw-render.html
   [164]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155979v2/shard-bmg-4/igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-cur-indfb-draw-render.html

  * igt@kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-cur-indfb-draw-blt:
    - shard-bmg:          [SKIP][165] ([Intel XE#2312]) -> [SKIP][166] ([Intel XE#2313]) +11 other tests skip
   [165]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3930-aaaff197c9186f4959c2bcb18035725188b950ed/shard-bmg-6/igt@kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-cur-indfb-draw-blt.html
   [166]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155979v2/shard-bmg-5/igt@kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-cur-indfb-draw-blt.html

  * igt@kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-cur-indfb-draw-mmap-wc:
    - shard-bmg:          [SKIP][167] ([Intel XE#2313]) -> [SKIP][168] ([Intel XE#2312]) +6 other tests skip
   [167]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3930-aaaff197c9186f4959c2bcb18035725188b950ed/shard-bmg-7/igt@kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-cur-indfb-draw-mmap-wc.html
   [168]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155979v2/shard-bmg-6/igt@kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-cur-indfb-draw-mmap-wc.html

  * igt@kms_tiled_display@basic-test-pattern:
    - shard-bmg:          [SKIP][169] ([Intel XE#2426]) -> [FAIL][170] ([Intel XE#1729])
   [169]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3930-aaaff197c9186f4959c2bcb18035725188b950ed/shard-bmg-6/igt@kms_tiled_display@basic-test-pattern.html
   [170]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155979v2/shard-bmg-5/igt@kms_tiled_display@basic-test-pattern.html

  * igt@xe_exec_reset@cm-cat-error:
    - shard-adlp:         [DMESG-WARN][171] ([Intel XE#3868]) -> [DMESG-FAIL][172] ([Intel XE#3868])
   [171]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3930-aaaff197c9186f4959c2bcb18035725188b950ed/shard-adlp-2/igt@xe_exec_reset@cm-cat-error.html
   [172]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155979v2/shard-adlp-9/igt@xe_exec_reset@cm-cat-error.html

  
  {name}: This element is suppressed. This means it is ignored when computing
          the status of the difference (SUCCESS, WARNING, or FAILURE).

  [Intel XE#1123]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1123
  [Intel XE#1124]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1124
  [Intel XE#1125]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1125
  [Intel XE#1126]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1126
  [Intel XE#1188]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1188
  [Intel XE#1337]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1337
  [Intel XE#1392]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1392
  [Intel XE#1406]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1406
  [Intel XE#1475]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1475
  [Intel XE#1489]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1489
  [Intel XE#1499]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1499
  [Intel XE#1503]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1503
  [Intel XE#1508]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1508
  [Intel XE#1727]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1727
  [Intel XE#1729]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1729
  [Intel XE#1874]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1874
  [Intel XE#2191]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2191
  [Intel XE#2234]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2234
  [Intel XE#2244]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2244
  [Intel XE#2252]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2252
  [Intel XE#2284]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2284
  [Intel XE#2291]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2291
  [Intel XE#2293]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2293
  [Intel XE#2311]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2311
  [Intel XE#2312]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2312
  [Intel XE#2313]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2313
  [Intel XE#2316]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2316
  [Intel XE#2320]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2320
  [Intel XE#2322]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2322
  [Intel XE#2341]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2341
  [Intel XE#2370]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2370
  [Intel XE#2380]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2380
  [Intel XE#2390]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2390
  [Intel XE#2393]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2393
  [Intel XE#2426]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2426
  [Intel XE#261]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/261
  [Intel XE#2705]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2705
  [Intel XE#2838]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2838
  [Intel XE#2850]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2850
  [Intel XE#288]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/288
  [Intel XE#2887]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2887
  [Intel XE#2907]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2907
  [Intel XE#2927]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2927
  [Intel XE#2953]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2953
  [Intel XE#301]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/301
  [Intel XE#3012]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3012
  [Intel XE#306]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/306
  [Intel XE#308]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/308
  [Intel XE#309]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/309
  [Intel XE#310]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/310
  [Intel XE#3113]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3113
  [Intel XE#3149]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3149
  [Intel XE#316]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/316
  [Intel XE#323]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/323
  [Intel XE#3309]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3309
  [Intel XE#3414]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3414
  [Intel XE#3573]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3573
  [Intel XE#366]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/366
  [Intel XE#367]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/367
  [Intel XE#373]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/373
  [Intel XE#3862]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3862
  [Intel XE#3868]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3868
  [Intel XE#3876]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3876
  [Intel XE#3904]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3904
  [Intel XE#4173]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4173
  [Intel XE#4212]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4212
  [Intel XE#4331]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4331
  [Intel XE#4345]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4345
  [Intel XE#4422]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4422
  [Intel XE#4459]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4459
  [Intel XE#4522]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4522
  [Intel XE#4543]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4543
  [Intel XE#455]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/455
  [Intel XE#4733]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4733
  [Intel XE#4814]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4814
  [Intel XE#4821]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4821
  [Intel XE#4837]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4837
  [Intel XE#488]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/488
  [Intel XE#4915]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4915
  [Intel XE#4943]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4943
  [Intel XE#5191]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5191
  [Intel XE#5195]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5195
  [Intel XE#5208]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5208
  [Intel XE#5213]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5213
  [Intel XE#5299]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5299
  [Intel XE#5300]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5300
  [Intel XE#5390]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5390
  [Intel XE#5530]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5530
  [Intel XE#5561]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5561
  [Intel XE#5564]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5564
  [Intel XE#5565]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5565
  [Intel XE#5572]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5572
  [Intel XE#5574]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5574
  [Intel XE#5575]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5575
  [Intel XE#5594]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5594
  [Intel XE#5607]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5607
  [Intel XE#5614]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5614
  [Intel XE#5624]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5624
  [Intel XE#5626]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5626
  [Intel XE#5786]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5786
  [Intel XE#6010]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6010
  [Intel XE#607]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/607
  [Intel XE#6168]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6168
  [Intel XE#6312]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6312
  [Intel XE#6313]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6313
  [Intel XE#6318]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6318
  [Intel XE#6321]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6321
  [Intel XE#651]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/651
  [Intel XE#653]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/653
  [Intel XE#656]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/656
  [Intel XE#688]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/688
  [Intel XE#734]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/734
  [Intel XE#787]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/787
  [Intel XE#870]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/870
  [Intel XE#929]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/929
  [Intel XE#944]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/944
  [Intel XE#979]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/979


Build changes
-------------

  * Linux: xe-3930-aaaff197c9186f4959c2bcb18035725188b950ed -> xe-pw-155979v2

  IGT_8587: 8587
  xe-3930-aaaff197c9186f4959c2bcb18035725188b950ed: aaaff197c9186f4959c2bcb18035725188b950ed
  xe-pw-155979v2: 155979v2

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155979v2/index.html

[-- Attachment #2: Type: text/html, Size: 62761 bytes --]

^ permalink raw reply	[flat|nested] 14+ messages in thread

* [PATCH 0/6] Optimize vrr.guardband
@ 2025-10-15 10:22 Ankit Nautiyal
  2025-10-15 10:22 ` [PATCH 6/6] drm/i915/vrr: Use the min static optimized guardband Ankit Nautiyal
  0 siblings, 1 reply; 14+ messages in thread
From: Ankit Nautiyal @ 2025-10-15 10:22 UTC (permalink / raw)
  To: intel-gfx, intel-xe; +Cc: ville.syrjala, uma.shankar, Ankit Nautiyal

Instead of setting vrr.guardband to vblank, use optimal guardband that
works for most of the cases. This will help in avoiding need of change
in guardband and fix the LRR feature that needs seamless switching to
a lower refresh rate.

-Patch [1-2] are squashed from series [1] and [2] and are not meant for
 review.
-Patch [3-6] are patches to check the guardband for prefill+PSR+SDP
 latencies and to use a static optimized guardband.

[1] "Preparatory patches for guardband optimization"
https://patchwork.freedesktop.org/series/155661/#rev7

[2] "Introduce helpers for prefill latency calculations"
https://patchwork.freedesktop.org/series/155629/#rev2

Ankit Nautiyal (5):
  [NOT FOR REVIEW] drm/i915/vrr: prep patches for guardband optimization
    squashed
  drm/i915/dp: Add SDP latency computation helper
  drm/i915/psr: Add function to compute max link-wake latency
  drm/i915/display: Add guardband check for feature latencies
  drm/i915/vrr: Use the min static optimized guardband

Ville Syrjälä (1):
  [NOT FOR REVIEW] drm/i915/prefill: Prefill latency calculations series
    squashed

 drivers/gpu/drm/i915/Makefile                |   1 +
 drivers/gpu/drm/i915/display/intel_cdclk.c   |  80 +++++-
 drivers/gpu/drm/i915/display/intel_cdclk.h   |   6 +
 drivers/gpu/drm/i915/display/intel_ddi.c     |   3 +
 drivers/gpu/drm/i915/display/intel_display.c |  82 +++++-
 drivers/gpu/drm/i915/display/intel_dp.c      |  42 +++
 drivers/gpu/drm/i915/display/intel_dp.h      |   4 +
 drivers/gpu/drm/i915/display/intel_psr.c     | 257 +++++++++++++------
 drivers/gpu/drm/i915/display/intel_psr.h     |   3 +
 drivers/gpu/drm/i915/display/intel_vblank.c  |  10 +
 drivers/gpu/drm/i915/display/intel_vblank.h  |   2 +
 drivers/gpu/drm/i915/display/intel_vdsc.c    |   8 +
 drivers/gpu/drm/i915/display/intel_vdsc.h    |   1 +
 drivers/gpu/drm/i915/display/intel_vrr.c     |  90 ++++++-
 drivers/gpu/drm/i915/display/intel_vrr.h     |   2 +-
 drivers/gpu/drm/i915/display/skl_prefill.c   | 157 +++++++++++
 drivers/gpu/drm/i915/display/skl_prefill.h   |  46 ++++
 drivers/gpu/drm/i915/display/skl_scaler.c    | 198 ++++++++++++++
 drivers/gpu/drm/i915/display/skl_scaler.h    |  15 ++
 drivers/gpu/drm/i915/display/skl_watermark.c | 156 +++++------
 drivers/gpu/drm/i915/display/skl_watermark.h |   3 +
 drivers/gpu/drm/xe/Makefile                  |   1 +
 22 files changed, 983 insertions(+), 184 deletions(-)
 create mode 100644 drivers/gpu/drm/i915/display/skl_prefill.c
 create mode 100644 drivers/gpu/drm/i915/display/skl_prefill.h

-- 
2.45.2


^ permalink raw reply	[flat|nested] 14+ messages in thread

* [PATCH 6/6] drm/i915/vrr: Use the min static optimized guardband
  2025-10-15 10:22 [PATCH 0/6] Optimize vrr.guardband Ankit Nautiyal
@ 2025-10-15 10:22 ` Ankit Nautiyal
  0 siblings, 0 replies; 14+ messages in thread
From: Ankit Nautiyal @ 2025-10-15 10:22 UTC (permalink / raw)
  To: intel-gfx, intel-xe; +Cc: ville.syrjala, uma.shankar, Ankit Nautiyal

In the current VRR implementation, vrr.vmin and vrr.guardband are set such
that they do not need to change when switching from fixed refresh rate to
variable refresh rate. Specifically, vrr.guardband is always set to match
the vblank length. This approach works for most cases, but not for LRR,
where the guardband would need to change while the VRR timing generator is
still active.

With the VRR TG always active, live updates to guardband are unsafe and not
recommended. To ensure hardware safety, guardband was moved out of the
!fastset block, meaning any change now requires a full modeset.
This breaks seamless LRR switching, which was previously supported.

Since the problem arises from guardband being matched to the vblank length,
solution is to use a minimal, sufficient static value, instead. So we use a
static guardband defined during mode-set that fits within the smallest
expected vblank and remains unchanged in case of features like LRR where
vtotal changes. To compute this minimum guardband we take into account
latencies/delays due to different features as mentioned in the Bspec.

Introduce a helper to compute the minimal sufficient guardband.
On platforms where the VRR timing generator is always ON, we optimize the
guardband regardless of whether the display is operating in fixed or
variable refresh rate mode.
On platforms where the VRR timing generator is not always ON, we optimize
the guardband only when VRR is enabled.

Bspec: 70151
Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
---
 drivers/gpu/drm/i915/display/intel_vrr.c | 61 +++++++++++++++++++++++-
 1 file changed, 59 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_vrr.c b/drivers/gpu/drm/i915/display/intel_vrr.c
index 1cfcc31bd899..4d96aad93dba 100644
--- a/drivers/gpu/drm/i915/display/intel_vrr.c
+++ b/drivers/gpu/drm/i915/display/intel_vrr.c
@@ -6,12 +6,16 @@
 
 #include <drm/drm_print.h>
 
+#include "intel_crtc.h"
 #include "intel_de.h"
 #include "intel_display_regs.h"
 #include "intel_display_types.h"
 #include "intel_dp.h"
+#include "intel_psr.h"
 #include "intel_vrr.h"
 #include "intel_vrr_regs.h"
+#include "skl_prefill.h"
+#include "skl_watermark.h"
 
 #define FIXED_POINT_PRECISION		100
 #define CMRR_PRECISION_TOLERANCE	10
@@ -433,17 +437,70 @@ intel_vrr_max_guardband(struct intel_crtc_state *crtc_state)
 		   intel_vrr_max_vblank_guardband(crtc_state));
 }
 
+static
+int intel_vrr_compute_optimized_guardband(struct intel_crtc_state *crtc_state)
+{
+	struct intel_display *display = to_intel_display(crtc_state);
+	const struct drm_display_mode *adjusted_mode =
+		&crtc_state->hw.adjusted_mode;
+	struct skl_prefill_ctx prefill_ctx;
+	int prefill_framestart_delay = 1;
+	int prefill_min_guardband;
+	int prefill_latency_us;
+	int prefill_wm0_lines;
+	int prefill_sagv_us;
+	int psr_latency = 0;
+	int sdp_latency = 0;
+	int guardband;
+
+	skl_prefill_init_worst(&prefill_ctx, crtc_state);
+	prefill_wm0_lines = skl_wm0_prefill_lines_worst(crtc_state);
+	prefill_sagv_us = display->sagv.block_time_us;
+
+	prefill_latency_us = prefill_sagv_us +
+			     intel_scanlines_to_usecs(adjusted_mode,
+						      prefill_framestart_delay +
+						      prefill_wm0_lines);
+	prefill_min_guardband =
+		skl_prefill_min_guardband(&prefill_ctx,
+					  crtc_state,
+					  prefill_latency_us);
+
+	if (intel_crtc_has_dp_encoder(crtc_state)) {
+		psr_latency = intel_psr_max_link_wake_latency(crtc_state);
+		sdp_latency = intel_dp_compute_sdp_latency(crtc_state);
+	}
+
+	guardband = max(sdp_latency, psr_latency);
+
+	guardband = max(guardband, prefill_min_guardband);
+
+	return guardband;
+}
+
+static bool intel_vrr_use_optimized_guardband(const struct intel_crtc_state *crtc_state)
+{
+	struct intel_display *display = to_intel_display(crtc_state);
+
+	return intel_vrr_always_use_vrr_tg(display) || crtc_state->vrr.enable;
+}
+
 void intel_vrr_compute_guardband(struct intel_crtc_state *crtc_state)
 {
 	struct intel_display *display = to_intel_display(crtc_state);
 	struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode;
 	struct drm_display_mode *pipe_mode = &crtc_state->hw.pipe_mode;
+	int guardband;
 
 	if (!intel_vrr_possible(crtc_state))
 		return;
 
-	crtc_state->vrr.guardband = min(crtc_state->vrr.vmin - adjusted_mode->crtc_vdisplay,
-					intel_vrr_max_guardband(crtc_state));
+	if (intel_vrr_use_optimized_guardband(crtc_state))
+		guardband = intel_vrr_compute_optimized_guardband(crtc_state);
+	else
+		guardband = crtc_state->vrr.vmin - adjusted_mode->crtc_vdisplay;
+
+	crtc_state->vrr.guardband = min(guardband, intel_vrr_max_guardband(crtc_state));
 
 	if (intel_vrr_always_use_vrr_tg(display)) {
 		adjusted_mode->crtc_vblank_start  =
-- 
2.45.2


^ permalink raw reply related	[flat|nested] 14+ messages in thread

end of thread, other threads:[~2025-10-17  6:56 UTC | newest]

Thread overview: 14+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2025-10-16  9:30 [PATCH 0/6] Optimize vrr.guardband Ankit Nautiyal
2025-10-16  9:30 ` [PATCH 1/6] [NOT FOR REVIEW] drm/i915/vrr: prep patches for guardband optimization squashed Ankit Nautiyal
2025-10-16  9:30 ` [PATCH 2/6] [NOT FOR REVIEW] drm/i915/prefill: Prefill latency calculations series squashed Ankit Nautiyal
2025-10-16  9:30 ` [PATCH 3/6] drm/i915/psr: Add helper to get min psr guardband Ankit Nautiyal
2025-10-16  9:30 ` [PATCH 4/6] drm/i915/dp: Add helper to get min sdp guardband Ankit Nautiyal
2025-10-16  9:30 ` [PATCH 5/6] drm/i915/dp: Check if guardband can accommodate sdp latencies Ankit Nautiyal
2025-10-16  9:30 ` [PATCH 6/6] drm/i915/vrr: Use the min static optimized guardband Ankit Nautiyal
2025-10-16 17:29   ` Ville Syrjälä
2025-10-16 10:31 ` ✗ CI.checkpatch: warning for Optimize vrr.guardband (rev2) Patchwork
2025-10-16 10:32 ` ✓ CI.KUnit: success " Patchwork
2025-10-16 10:50 ` ✗ CI.checksparse: warning " Patchwork
2025-10-16 11:25 ` ✓ Xe.CI.BAT: success " Patchwork
2025-10-17  6:56 ` ✓ Xe.CI.Full: " Patchwork
  -- strict thread matches above, loose matches on Subject: below --
2025-10-15 10:22 [PATCH 0/6] Optimize vrr.guardband Ankit Nautiyal
2025-10-15 10:22 ` [PATCH 6/6] drm/i915/vrr: Use the min static optimized guardband Ankit Nautiyal

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