From: Tvrtko Ursulin <tvrtko.ursulin@igalia.com>
To: intel-xe@lists.freedesktop.org
Subject: [CI 10/13] drm/xe: Handle DPT in system memory
Date: Wed, 22 Oct 2025 08:30:02 +0100 [thread overview]
Message-ID: <20251022073010.71285-11-tvrtko.ursulin@igalia.com> (raw)
In-Reply-To: <20251022073010.71285-1-tvrtko.ursulin@igalia.com>
If DPT is allocated from system memory it will be created in the default
write-back cached mode. This means we need to flush it after populating
otherwise nothing works.
Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@igalia.com>
---
drivers/gpu/drm/xe/display/xe_fb_pin.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/drivers/gpu/drm/xe/display/xe_fb_pin.c b/drivers/gpu/drm/xe/display/xe_fb_pin.c
index eb21eeae9d17..af691eee398a 100644
--- a/drivers/gpu/drm/xe/display/xe_fb_pin.c
+++ b/drivers/gpu/drm/xe/display/xe_fb_pin.c
@@ -3,6 +3,7 @@
* Copyright © 2021 Intel Corporation
*/
+#include <drm/drm_cache.h>
#include <drm/ttm/ttm_bo.h>
#include "i915_vma.h"
@@ -206,6 +207,8 @@ static int __xe_pin_fb_vma_dpt(const struct intel_framebuffer *fb,
if (dpt->vmap.is_iomem && !xe_bo_is_vram(dpt))
ggtt_flush_writes(tile0->mem.ggtt);
+ else if (!xe_bo_is_vram(dpt) && !xe_bo_is_stolen(dpt))
+ drm_clflush_virt_range(dpt->vmap.vaddr, dpt_size);
vma->dpt = dpt;
vma->node = dpt->ggtt_node[tile0->id];
--
2.48.0
next prev parent reply other threads:[~2025-10-22 7:30 UTC|newest]
Thread overview: 29+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-10-22 7:29 [CI 00/13] auxccs ci run no stolen Tvrtko Ursulin
2025-10-22 7:29 ` [CI 01/13] drm/xe: Fix ggtt fb alignment Tvrtko Ursulin
2025-10-22 7:29 ` [CI 02/13] drm/xe/xelpg: Flush CCS when flushing caches Tvrtko Ursulin
2025-10-22 7:29 ` [CI 03/13] drm/xe/xelp: Quiesce memory traffic before invalidating AuxCCS Tvrtko Ursulin
2025-10-22 7:29 ` [CI 04/13] drm/xe/xelp: Support auxccs invalidation on blitter Tvrtko Ursulin
2025-10-22 7:29 ` [CI 05/13] drm/xe/xelp: Use MI_FLUSH_DW_CCS on auxccs platforms Tvrtko Ursulin
2025-10-22 7:29 ` [CI 06/13] drm/xe/xelp: Wait for AuxCCS invalidation to complete Tvrtko Ursulin
2025-10-22 7:29 ` [CI 07/13] drm/xe: Export xe_emit_aux_table_inv Tvrtko Ursulin
2025-10-22 7:30 ` [CI 08/13] drm/xe/xelp: Add AuxCCS invalidation to the indirect context workarounds Tvrtko Ursulin
2025-10-22 7:30 ` [CI 09/13] drm/xe: Flush GGTT writes after populating DPT Tvrtko Ursulin
2025-10-22 7:30 ` Tvrtko Ursulin [this message]
2025-10-22 7:30 ` [CI 11/13] drm/xe: Do not use stolen memory for DPT on IGFX and AuxCCS Tvrtko Ursulin
2025-10-22 7:30 ` [CI 12/13] drm/xe/display: Add support for AuxCCS Tvrtko Ursulin
2025-10-22 7:30 ` [CI 13/13] drm/i915/display: Expose AuxCCS frame buffer modifiers for Xe Tvrtko Ursulin
2025-10-22 7:36 ` ✗ CI.checkpatch: warning for auxccs ci run no stolen Patchwork
2025-10-22 7:37 ` ✓ CI.KUnit: success " Patchwork
2025-10-22 8:47 ` ✓ Xe.CI.BAT: " Patchwork
2025-10-22 10:02 ` ✗ Xe.CI.Full: failure " Patchwork
2025-10-22 16:05 ` ✗ CI.checkpatch: warning for auxccs ci run no stolen (rev2) Patchwork
2025-10-22 16:07 ` ✓ CI.KUnit: success " Patchwork
2025-10-22 17:10 ` ✓ Xe.CI.BAT: " Patchwork
2025-10-22 20:00 ` ✗ Xe.CI.Full: failure " Patchwork
2025-10-23 8:37 ` ✗ CI.checkpatch: warning for auxccs ci run no stolen (rev3) Patchwork
2025-10-23 8:38 ` ✓ CI.KUnit: success " Patchwork
2025-10-23 9:26 ` ✓ Xe.CI.BAT: " Patchwork
2025-10-23 15:28 ` ✗ Xe.CI.Full: failure " Patchwork
-- strict thread matches above, loose matches on Subject: below --
2025-10-02 14:24 [CI 00/13] CCS uncached mocs 0 test run Tvrtko Ursulin
2025-10-02 14:24 ` [CI 10/13] drm/xe: Handle DPT in system memory Tvrtko Ursulin
2025-07-24 13:16 [CI 00/13] adl auxcss ci run Tvrtko Ursulin
2025-07-24 13:17 ` [CI 10/13] drm/xe: Handle DPT in system memory Tvrtko Ursulin
2025-07-24 12:03 [CI 00/13] adl auxcss ci run Tvrtko Ursulin
2025-07-24 12:03 ` [CI 10/13] drm/xe: Handle DPT in system memory Tvrtko Ursulin
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