From: Tvrtko Ursulin <tvrtko.ursulin@igalia.com>
To: intel-xe@lists.freedesktop.org
Subject: [CI 03/13] drm/xe/xelp: Quiesce memory traffic before invalidating AuxCCS
Date: Wed, 22 Oct 2025 08:29:55 +0100 [thread overview]
Message-ID: <20251022073010.71285-4-tvrtko.ursulin@igalia.com> (raw)
In-Reply-To: <20251022073010.71285-1-tvrtko.ursulin@igalia.com>
According to i915 commit
ad8ebf12217e ("drm/i915/gt: Ensure memory quiesced before invalidation")
quiescing of the memory traffic is required before invalidating the AuxCCS
tables.
Add an extra pipe control flush to achieve that.
Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@igalia.com>
Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
---
drivers/gpu/drm/xe/xe_ring_ops.c | 10 +++++++++-
drivers/gpu/drm/xe/xe_ring_ops_types.h | 2 +-
2 files changed, 10 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/xe/xe_ring_ops.c b/drivers/gpu/drm/xe/xe_ring_ops.c
index 15fc4010a710..f384c9968859 100644
--- a/drivers/gpu/drm/xe/xe_ring_ops.c
+++ b/drivers/gpu/drm/xe/xe_ring_ops.c
@@ -363,12 +363,20 @@ static void __emit_job_gen12_render_compute(struct xe_sched_job *job,
struct xe_gt *gt = job->q->gt;
struct xe_device *xe = gt_to_xe(gt);
bool lacks_render = !(gt->info.engine_mask & XE_HW_ENGINE_RCS_MASK);
+ const bool aux_ccs = has_aux_ccs(xe);
u32 mask_flags = 0;
*head = lrc->ring.tail;
i = emit_copy_timestamp(lrc, dw, i);
+ /*
+ * On AuxCCS platforms the invalidation of the Aux table requires
+ * quiescing the memory traffic beforehand.
+ */
+ if (aux_ccs)
+ i = emit_render_cache_flush(job, dw, i);
+
dw[i++] = preparser_disable(true);
if (lacks_render)
mask_flags = PIPE_CONTROL_3D_ARCH_FLAGS;
@@ -379,7 +387,7 @@ static void __emit_job_gen12_render_compute(struct xe_sched_job *job,
i = emit_pipe_invalidate(mask_flags, job->ring_ops_flush_tlb, dw, i);
/* hsdes: 1809175790 */
- if (has_aux_ccs(xe))
+ if (aux_ccs)
i = emit_aux_table_inv(gt, CCS_AUX_INV, dw, i);
dw[i++] = preparser_disable(false);
diff --git a/drivers/gpu/drm/xe/xe_ring_ops_types.h b/drivers/gpu/drm/xe/xe_ring_ops_types.h
index d7e3e150a9a5..477dc7defd72 100644
--- a/drivers/gpu/drm/xe/xe_ring_ops_types.h
+++ b/drivers/gpu/drm/xe/xe_ring_ops_types.h
@@ -8,7 +8,7 @@
struct xe_sched_job;
-#define MAX_JOB_SIZE_DW 58
+#define MAX_JOB_SIZE_DW 70
#define MAX_JOB_SIZE_BYTES (MAX_JOB_SIZE_DW * 4)
/**
--
2.48.0
next prev parent reply other threads:[~2025-10-22 7:30 UTC|newest]
Thread overview: 29+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-10-22 7:29 [CI 00/13] auxccs ci run no stolen Tvrtko Ursulin
2025-10-22 7:29 ` [CI 01/13] drm/xe: Fix ggtt fb alignment Tvrtko Ursulin
2025-10-22 7:29 ` [CI 02/13] drm/xe/xelpg: Flush CCS when flushing caches Tvrtko Ursulin
2025-10-22 7:29 ` Tvrtko Ursulin [this message]
2025-10-22 7:29 ` [CI 04/13] drm/xe/xelp: Support auxccs invalidation on blitter Tvrtko Ursulin
2025-10-22 7:29 ` [CI 05/13] drm/xe/xelp: Use MI_FLUSH_DW_CCS on auxccs platforms Tvrtko Ursulin
2025-10-22 7:29 ` [CI 06/13] drm/xe/xelp: Wait for AuxCCS invalidation to complete Tvrtko Ursulin
2025-10-22 7:29 ` [CI 07/13] drm/xe: Export xe_emit_aux_table_inv Tvrtko Ursulin
2025-10-22 7:30 ` [CI 08/13] drm/xe/xelp: Add AuxCCS invalidation to the indirect context workarounds Tvrtko Ursulin
2025-10-22 7:30 ` [CI 09/13] drm/xe: Flush GGTT writes after populating DPT Tvrtko Ursulin
2025-10-22 7:30 ` [CI 10/13] drm/xe: Handle DPT in system memory Tvrtko Ursulin
2025-10-22 7:30 ` [CI 11/13] drm/xe: Do not use stolen memory for DPT on IGFX and AuxCCS Tvrtko Ursulin
2025-10-22 7:30 ` [CI 12/13] drm/xe/display: Add support for AuxCCS Tvrtko Ursulin
2025-10-22 7:30 ` [CI 13/13] drm/i915/display: Expose AuxCCS frame buffer modifiers for Xe Tvrtko Ursulin
2025-10-22 7:36 ` ✗ CI.checkpatch: warning for auxccs ci run no stolen Patchwork
2025-10-22 7:37 ` ✓ CI.KUnit: success " Patchwork
2025-10-22 8:47 ` ✓ Xe.CI.BAT: " Patchwork
2025-10-22 10:02 ` ✗ Xe.CI.Full: failure " Patchwork
2025-10-22 16:05 ` ✗ CI.checkpatch: warning for auxccs ci run no stolen (rev2) Patchwork
2025-10-22 16:07 ` ✓ CI.KUnit: success " Patchwork
2025-10-22 17:10 ` ✓ Xe.CI.BAT: " Patchwork
2025-10-22 20:00 ` ✗ Xe.CI.Full: failure " Patchwork
2025-10-23 8:37 ` ✗ CI.checkpatch: warning for auxccs ci run no stolen (rev3) Patchwork
2025-10-23 8:38 ` ✓ CI.KUnit: success " Patchwork
2025-10-23 9:26 ` ✓ Xe.CI.BAT: " Patchwork
2025-10-23 15:28 ` ✗ Xe.CI.Full: failure " Patchwork
-- strict thread matches above, loose matches on Subject: below --
2025-10-02 14:24 [CI 00/13] CCS uncached mocs 0 test run Tvrtko Ursulin
2025-10-02 14:24 ` [CI 03/13] drm/xe/xelp: Quiesce memory traffic before invalidating AuxCCS Tvrtko Ursulin
2025-07-24 13:16 [CI 00/13] adl auxcss ci run Tvrtko Ursulin
2025-07-24 13:17 ` [CI 03/13] drm/xe/xelp: Quiesce memory traffic before invalidating auxccs Tvrtko Ursulin
2025-07-24 12:03 [CI 00/13] adl auxcss ci run Tvrtko Ursulin
2025-07-24 12:03 ` [CI 03/13] drm/xe/xelp: Quiesce memory traffic before invalidating auxccs Tvrtko Ursulin
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20251022073010.71285-4-tvrtko.ursulin@igalia.com \
--to=tvrtko.ursulin@igalia.com \
--cc=intel-xe@lists.freedesktop.org \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox