From: Tvrtko Ursulin <tvrtko.ursulin@igalia.com>
To: intel-xe@lists.freedesktop.org
Subject: [CI 04/13] drm/xe/xelp: Support auxccs invalidation on blitter
Date: Wed, 22 Oct 2025 08:29:56 +0100 [thread overview]
Message-ID: <20251022073010.71285-5-tvrtko.ursulin@igalia.com> (raw)
In-Reply-To: <20251022073010.71285-1-tvrtko.ursulin@igalia.com>
Auxccs platforms need to be able to invalidate auxccs on the blitter
engine.
Add the relevant mmio register and enable this by refactoring the ring
emission a bit to consolidate all non-render engines.
Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@igalia.com>
---
drivers/gpu/drm/xe/regs/xe_gt_regs.h | 1 +
drivers/gpu/drm/xe/xe_ring_ops.c | 118 ++++++++++-----------------
2 files changed, 46 insertions(+), 73 deletions(-)
diff --git a/drivers/gpu/drm/xe/regs/xe_gt_regs.h b/drivers/gpu/drm/xe/regs/xe_gt_regs.h
index 3545e0be06da..f3bc2abf678c 100644
--- a/drivers/gpu/drm/xe/regs/xe_gt_regs.h
+++ b/drivers/gpu/drm/xe/regs/xe_gt_regs.h
@@ -94,6 +94,7 @@
#define CCS_AUX_INV XE_REG(0x4208)
#define VD0_AUX_INV XE_REG(0x4218)
+#define BCS_AUX_INV XE_REG(0x4248)
#define VE0_AUX_INV XE_REG(0x4238)
#define VE1_AUX_INV XE_REG(0x42b8)
diff --git a/drivers/gpu/drm/xe/xe_ring_ops.c b/drivers/gpu/drm/xe/xe_ring_ops.c
index f384c9968859..87e467972070 100644
--- a/drivers/gpu/drm/xe/xe_ring_ops.c
+++ b/drivers/gpu/drm/xe/xe_ring_ops.c
@@ -248,46 +248,6 @@ static int emit_copy_timestamp(struct xe_lrc *lrc, u32 *dw, int i)
return i;
}
-/* for engines that don't require any special HW handling (no EUs, no aux inval, etc) */
-static void __emit_job_gen12_simple(struct xe_sched_job *job, struct xe_lrc *lrc,
- u64 batch_addr, u32 *head, u32 seqno)
-{
- u32 dw[MAX_JOB_SIZE_DW], i = 0;
- u32 ppgtt_flag = get_ppgtt_flag(job);
- struct xe_gt *gt = job->q->gt;
-
- *head = lrc->ring.tail;
-
- i = emit_copy_timestamp(lrc, dw, i);
-
- if (job->ring_ops_flush_tlb) {
- dw[i++] = preparser_disable(true);
- i = emit_flush_imm_ggtt(xe_lrc_start_seqno_ggtt_addr(lrc),
- seqno, MI_INVALIDATE_TLB, dw, i);
- dw[i++] = preparser_disable(false);
- } else {
- i = emit_store_imm_ggtt(xe_lrc_start_seqno_ggtt_addr(lrc),
- seqno, dw, i);
- }
-
- i = emit_bb_start(batch_addr, ppgtt_flag, dw, i);
-
- if (job->user_fence.used) {
- i = emit_flush_dw(dw, i);
- i = emit_store_imm_ppgtt_posted(job->user_fence.addr,
- job->user_fence.value,
- dw, i);
- }
-
- i = emit_flush_imm_ggtt(xe_lrc_seqno_ggtt_addr(lrc), seqno, 0, dw, i);
-
- i = emit_user_interrupt(dw, i);
-
- xe_gt_assert(gt, i <= MAX_JOB_SIZE_DW);
-
- xe_lrc_write_ring(lrc, dw, i * sizeof(*dw));
-}
-
static bool has_aux_ccs(struct xe_device *xe)
{
/*
@@ -302,40 +262,52 @@ static bool has_aux_ccs(struct xe_device *xe)
return !xe->info.has_flat_ccs;
}
-static void __emit_job_gen12_video(struct xe_sched_job *job, struct xe_lrc *lrc,
- u64 batch_addr, u32 *head, u32 seqno)
+static void __emit_job_gen12_xcs(struct xe_sched_job *job, struct xe_lrc *lrc,
+ u64 batch_addr, u32 *head, u32 seqno)
{
- u32 dw[MAX_JOB_SIZE_DW], i = 0;
- u32 ppgtt_flag = get_ppgtt_flag(job);
+ const unsigned int class = job->q->class;
struct xe_gt *gt = job->q->gt;
- struct xe_device *xe = gt_to_xe(gt);
- bool decode = job->q->class == XE_ENGINE_CLASS_VIDEO_DECODE;
+ const bool aux_ccs = has_aux_ccs(gt_to_xe(gt)) &&
+ (class == XE_ENGINE_CLASS_COPY ||
+ class == XE_ENGINE_CLASS_VIDEO_DECODE ||
+ class == XE_ENGINE_CLASS_VIDEO_ENHANCE);
+ const bool invalidate_tlb = aux_ccs || job->ring_ops_flush_tlb;
+ u32 dw[MAX_JOB_SIZE_DW], i = 0;
*head = lrc->ring.tail;
i = emit_copy_timestamp(lrc, dw, i);
- dw[i++] = preparser_disable(true);
-
- /* hsdes: 1809175790 */
- if (has_aux_ccs(xe)) {
- if (decode)
- i = emit_aux_table_inv(gt, VD0_AUX_INV, dw, i);
- else
- i = emit_aux_table_inv(gt, VE0_AUX_INV, dw, i);
- }
-
- if (job->ring_ops_flush_tlb)
+ if (invalidate_tlb) {
+ dw[i++] = preparser_disable(true);
i = emit_flush_imm_ggtt(xe_lrc_start_seqno_ggtt_addr(lrc),
- seqno, MI_INVALIDATE_TLB, dw, i);
+ seqno,
+ MI_INVALIDATE_TLB,
+ dw, i);
+ /* hsdes: 1809175790 */
+ if (aux_ccs) {
+ struct xe_reg reg;
- dw[i++] = preparser_disable(false);
+ switch (job->q->class) {
+ case XE_ENGINE_CLASS_COPY:
+ reg = BCS_AUX_INV;
+ break;
+ case XE_ENGINE_CLASS_VIDEO_DECODE:
+ reg = VD0_AUX_INV;
+ break;
+ default:
+ reg = VE0_AUX_INV;
+ };
- if (!job->ring_ops_flush_tlb)
+ i = emit_aux_table_inv(gt, reg, dw, i);
+ }
+ dw[i++] = preparser_disable(false);
+ } else {
i = emit_store_imm_ggtt(xe_lrc_start_seqno_ggtt_addr(lrc),
seqno, dw, i);
+ }
- i = emit_bb_start(batch_addr, ppgtt_flag, dw, i);
+ i = emit_bb_start(batch_addr, get_ppgtt_flag(job), dw, i);
if (job->user_fence.used) {
i = emit_flush_dw(dw, i);
@@ -455,10 +427,10 @@ static void emit_job_gen12_gsc(struct xe_sched_job *job)
xe_gt_assert(gt, job->q->width <= 1); /* no parallel submission for GSCCS */
- __emit_job_gen12_simple(job, job->q->lrc[0],
- job->ptrs[0].batch_addr,
- &job->ptrs[0].head,
- xe_sched_job_lrc_seqno(job));
+ __emit_job_gen12_xcs(job, job->q->lrc[0],
+ job->ptrs[0].batch_addr,
+ &job->ptrs[0].head,
+ xe_sched_job_lrc_seqno(job));
}
static void emit_job_gen12_copy(struct xe_sched_job *job)
@@ -473,10 +445,10 @@ static void emit_job_gen12_copy(struct xe_sched_job *job)
}
for (i = 0; i < job->q->width; ++i)
- __emit_job_gen12_simple(job, job->q->lrc[i],
- job->ptrs[i].batch_addr,
- &job->ptrs[i].head,
- xe_sched_job_lrc_seqno(job));
+ __emit_job_gen12_xcs(job, job->q->lrc[i],
+ job->ptrs[i].batch_addr,
+ &job->ptrs[0].head,
+ xe_sched_job_lrc_seqno(job));
}
static void emit_job_gen12_video(struct xe_sched_job *job)
@@ -485,10 +457,10 @@ static void emit_job_gen12_video(struct xe_sched_job *job)
/* FIXME: Not doing parallel handshake for now */
for (i = 0; i < job->q->width; ++i)
- __emit_job_gen12_video(job, job->q->lrc[i],
- job->ptrs[i].batch_addr,
- &job->ptrs[i].head,
- xe_sched_job_lrc_seqno(job));
+ __emit_job_gen12_xcs(job, job->q->lrc[i],
+ job->ptrs[i].batch_addr,
+ &job->ptrs[0].head,
+ xe_sched_job_lrc_seqno(job));
}
static void emit_job_gen12_render_compute(struct xe_sched_job *job)
--
2.48.0
next prev parent reply other threads:[~2025-10-22 7:30 UTC|newest]
Thread overview: 29+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-10-22 7:29 [CI 00/13] auxccs ci run no stolen Tvrtko Ursulin
2025-10-22 7:29 ` [CI 01/13] drm/xe: Fix ggtt fb alignment Tvrtko Ursulin
2025-10-22 7:29 ` [CI 02/13] drm/xe/xelpg: Flush CCS when flushing caches Tvrtko Ursulin
2025-10-22 7:29 ` [CI 03/13] drm/xe/xelp: Quiesce memory traffic before invalidating AuxCCS Tvrtko Ursulin
2025-10-22 7:29 ` Tvrtko Ursulin [this message]
2025-10-22 7:29 ` [CI 05/13] drm/xe/xelp: Use MI_FLUSH_DW_CCS on auxccs platforms Tvrtko Ursulin
2025-10-22 7:29 ` [CI 06/13] drm/xe/xelp: Wait for AuxCCS invalidation to complete Tvrtko Ursulin
2025-10-22 7:29 ` [CI 07/13] drm/xe: Export xe_emit_aux_table_inv Tvrtko Ursulin
2025-10-22 7:30 ` [CI 08/13] drm/xe/xelp: Add AuxCCS invalidation to the indirect context workarounds Tvrtko Ursulin
2025-10-22 7:30 ` [CI 09/13] drm/xe: Flush GGTT writes after populating DPT Tvrtko Ursulin
2025-10-22 7:30 ` [CI 10/13] drm/xe: Handle DPT in system memory Tvrtko Ursulin
2025-10-22 7:30 ` [CI 11/13] drm/xe: Do not use stolen memory for DPT on IGFX and AuxCCS Tvrtko Ursulin
2025-10-22 7:30 ` [CI 12/13] drm/xe/display: Add support for AuxCCS Tvrtko Ursulin
2025-10-22 7:30 ` [CI 13/13] drm/i915/display: Expose AuxCCS frame buffer modifiers for Xe Tvrtko Ursulin
2025-10-22 7:36 ` ✗ CI.checkpatch: warning for auxccs ci run no stolen Patchwork
2025-10-22 7:37 ` ✓ CI.KUnit: success " Patchwork
2025-10-22 8:47 ` ✓ Xe.CI.BAT: " Patchwork
2025-10-22 10:02 ` ✗ Xe.CI.Full: failure " Patchwork
2025-10-22 16:05 ` ✗ CI.checkpatch: warning for auxccs ci run no stolen (rev2) Patchwork
2025-10-22 16:07 ` ✓ CI.KUnit: success " Patchwork
2025-10-22 17:10 ` ✓ Xe.CI.BAT: " Patchwork
2025-10-22 20:00 ` ✗ Xe.CI.Full: failure " Patchwork
2025-10-23 8:37 ` ✗ CI.checkpatch: warning for auxccs ci run no stolen (rev3) Patchwork
2025-10-23 8:38 ` ✓ CI.KUnit: success " Patchwork
2025-10-23 9:26 ` ✓ Xe.CI.BAT: " Patchwork
2025-10-23 15:28 ` ✗ Xe.CI.Full: failure " Patchwork
-- strict thread matches above, loose matches on Subject: below --
2025-10-02 14:24 [CI 00/13] CCS uncached mocs 0 test run Tvrtko Ursulin
2025-10-02 14:24 ` [CI 04/13] drm/xe/xelp: Support auxccs invalidation on blitter Tvrtko Ursulin
2025-07-24 13:16 [CI 00/13] adl auxcss ci run Tvrtko Ursulin
2025-07-24 13:17 ` [CI 04/13] drm/xe/xelp: Support auxccs invalidation on blitter Tvrtko Ursulin
2025-07-24 12:03 [CI 00/13] adl auxcss ci run Tvrtko Ursulin
2025-07-24 12:03 ` [CI 04/13] drm/xe/xelp: Support auxccs invalidation on blitter Tvrtko Ursulin
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20251022073010.71285-5-tvrtko.ursulin@igalia.com \
--to=tvrtko.ursulin@igalia.com \
--cc=intel-xe@lists.freedesktop.org \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox