[FOR CI 0/5] drm/xe/display: Test series with PREEMPT_RT and preemption disable.

[FOR CI 0/5] drm/xe/display: Test series with PREEMPT_RT and preemption disable.

[Maarten Lankhorst]

Keep interrupts enabled, see what happens...

Maarten Lankhorst (3):
  drm/xe: Bump xe_device_l2_flush even higher
  drm/xe/display: Disable preemption in the most critical section
  PREEMPT_RT injection

Mike Galbraith (2):
  drm/i915: Use preempt_disable/enable_rt() where recommended
  drm/i915: Don't disable interrupts on PREEMPT_RT during atomic updates

 drivers/gpu/drm/i915/Kconfig.debug          | 15 ------
 drivers/gpu/drm/i915/display/intel_crtc.c   | 23 ++++++--
 drivers/gpu/drm/i915/display/intel_cursor.c | 27 ++++++++--
 drivers/gpu/drm/i915/display/intel_vblank.c | 58 ++++++++++++++++-----
 drivers/gpu/drm/xe/Kconfig.debug            |  5 ++
 drivers/gpu/drm/xe/xe_device.c              |  4 +-
 kernel/Kconfig.preempt                      |  4 +-
 7 files changed, 97 insertions(+), 39 deletions(-)

-- 
2.51.0

[FOR CI 1/5] drm/xe: Bump xe_device_l2_flush even higher

[Maarten Lankhorst]

It turns out for some applications 1 ms is not enough, and 2 ms is
needed.

Failing to flush causes a catastrophic display update failure,
so we should prevent it if possible.

Add an even bigger margin of 5 ms, and complain loudly if we ever exceed
it.

Closes: https://gitlab.freedesktop.org/drm/xe/kernel/-/issues/6097
Signed-off-by: Maarten Lankhorst <dev@lankhorst.se>
---
 drivers/gpu/drm/xe/xe_device.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/xe/xe_device.c b/drivers/gpu/drm/xe/xe_device.c
index 5f6a412b571c7..f6704c57e87ca 100644
--- a/drivers/gpu/drm/xe/xe_device.c
+++ b/drivers/gpu/drm/xe/xe_device.c
@@ -1077,8 +1077,8 @@ void xe_device_l2_flush(struct xe_device *xe)
 	spin_lock(&gt->global_invl_lock);
 
 	xe_mmio_write32(&gt->mmio, XE2_GLOBAL_INVAL, 0x1);
-	if (xe_mmio_wait32(&gt->mmio, XE2_GLOBAL_INVAL, 0x1, 0x0, 1000, NULL, true))
-		xe_gt_err_once(gt, "Global invalidation timeout\n");
+	if (xe_mmio_wait32(&gt->mmio, XE2_GLOBAL_INVAL, 0x1, 0x0, 5000, NULL, true))
+		xe_gt_err(gt, "Global invalidation timeout\n");
 
 	spin_unlock(&gt->global_invl_lock);
 
-- 
2.51.0

[FOR CI 2/5] drm/i915: Use preempt_disable/enable_rt() where recommended

[Maarten Lankhorst]

From: Mike Galbraith <umgwanakikbuti@gmail.com>

Mario Kleiner suggest in commit
  ad3543ede630f ("drm/intel: Push get_scanout_position() timestamping into kms driver.")

a spots where preemption should be disabled on PREEMPT_RT. The
difference is that on PREEMPT_RT the intel_uncore::lock disables neither
preemption nor interrupts and so region remains preemptible.

The area covers only register reads and writes. The part that worries me
is:
- __intel_get_crtc_scanline() the worst case is 100us if no match is
  found.

- intel_crtc_scanlines_since_frame_timestamp() not sure how long this
  may take in the worst case.

It was in the RT queue for a while and nobody complained.
Disable preemption on PREEPMPT_RT during timestamping.

[bigeasy: patch description.]

Cc: Mario Kleiner <mario.kleiner.de@gmail.com>
Signed-off-by: Mike Galbraith <umgwanakikbuti@gmail.com>
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Signed-off-by: Sebastian Andrzej Siewior <bigeasy@linutronix.de>
Signed-off-by: Maarten Lankhorst <dev@lankhorst.se>
---
 drivers/gpu/drm/i915/display/intel_vblank.c | 43 ++++++++++++++++-----
 1 file changed, 33 insertions(+), 10 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_vblank.c b/drivers/gpu/drm/i915/display/intel_vblank.c
index 2fc0c1c0bb876..5206a81f85554 100644
--- a/drivers/gpu/drm/i915/display/intel_vblank.c
+++ b/drivers/gpu/drm/i915/display/intel_vblank.c
@@ -315,6 +315,20 @@ static void intel_vblank_section_exit(struct intel_display *display)
 	struct drm_i915_private *i915 = to_i915(display->drm);
 	spin_unlock(&i915->uncore.lock);
 }
+
+static void intel_vblank_section_enter_irqf(struct intel_display *display, unsigned long *flags)
+	__acquires(i915->uncore.lock)
+{
+	struct drm_i915_private *i915 = to_i915(display->drm);
+	spin_lock_irqsave(&i915->uncore.lock, *flags);
+}
+
+static void intel_vblank_section_exit_irqf(struct intel_display *display, unsigned long flags)
+	__releases(i915->uncore.lock)
+{
+	struct drm_i915_private *i915 = to_i915(display->drm);
+	spin_unlock_irqrestore(&i915->uncore.lock, flags);
+}
 #else
 static void intel_vblank_section_enter(struct intel_display *display)
 {
@@ -323,6 +337,17 @@ static void intel_vblank_section_enter(struct intel_display *display)
 static void intel_vblank_section_exit(struct intel_display *display)
 {
 }
+
+static void intel_vblank_section_enter_irqf(struct intel_display *display, unsigned long *flags)
+{
+	*flags = 0;
+}
+
+static void intel_vblank_section_exit_irqf(struct intel_display *display, unsigned long flags)
+{
+	if (flags)
+		return;
+}
 #endif
 
 static bool i915_get_crtc_scanoutpos(struct drm_crtc *_crtc,
@@ -359,10 +384,10 @@ static bool i915_get_crtc_scanoutpos(struct drm_crtc *_crtc,
 	 * timing critical raw register reads, potentially with
 	 * preemption disabled, so the following code must not block.
 	 */
-	local_irq_save(irqflags);
-	intel_vblank_section_enter(display);
+	intel_vblank_section_enter_irqf(display, &irqflags);
 
-	/* preempt_disable_rt() should go right here in PREEMPT_RT patchset. */
+	if (IS_ENABLED(CONFIG_PREEMPT_RT))
+		preempt_disable();
 
 	/* Get optional system timestamp before query. */
 	if (stime)
@@ -426,10 +451,10 @@ static bool i915_get_crtc_scanoutpos(struct drm_crtc *_crtc,
 	if (etime)
 		*etime = ktime_get();
 
-	/* preempt_enable_rt() should go right here in PREEMPT_RT patchset. */
+	if (IS_ENABLED(CONFIG_PREEMPT_RT))
+		preempt_enable();
 
-	intel_vblank_section_exit(display);
-	local_irq_restore(irqflags);
+	intel_vblank_section_exit_irqf(display, irqflags);
 
 	/*
 	 * While in vblank, position will be negative
@@ -467,13 +492,11 @@ int intel_get_crtc_scanline(struct intel_crtc *crtc)
 	unsigned long irqflags;
 	int position;
 
-	local_irq_save(irqflags);
-	intel_vblank_section_enter(display);
+	intel_vblank_section_enter_irqf(display, &irqflags);
 
 	position = __intel_get_crtc_scanline(crtc);
 
-	intel_vblank_section_exit(display);
-	local_irq_restore(irqflags);
+	intel_vblank_section_exit_irqf(display, irqflags);
 
 	return position;
 }
-- 
2.51.0

[FOR CI 3/5] drm/i915: Don't disable interrupts on PREEMPT_RT during atomic updates

[Maarten Lankhorst]

From: Mike Galbraith <umgwanakikbuti@gmail.com>

Commit
   8d7849db3eab7 ("drm/i915: Make sprite updates atomic")

started disabling interrupts across atomic updates. This breaks on PREEMPT_RT
because within this section the code attempt to acquire spinlock_t locks which
are sleeping locks on PREEMPT_RT.

According to the comment the interrupts are disabled to avoid random delays and
not required for protection or synchronisation.
If this needs to happen with disabled interrupts on PREEMPT_RT, and the
whole section is restricted to register access then all sleeping locks
need to be acquired before interrupts are disabled and some function
maybe moved after enabling interrupts again.
This includes:
- prepare_to_wait() + finish_wait() due its wake queue.
- drm_crtc_vblank_put() -> vblank_disable_fn() drm_device::vbl_lock.
- skl_pfit_enable(), intel_update_plane(), vlv_atomic_update_fifo() and
  maybe others due to intel_uncore::lock
- drm_crtc_arm_vblank_event() due to drm_device::event_lock and
  drm_device::vblank_time_lock.

Don't disable interrupts on PREEMPT_RT during atomic updates.

[bigeasy: drop local locks, commit message]

Signed-off-by: Mike Galbraith <umgwanakikbuti@gmail.com>
Signed-off-by: Sebastian Andrzej Siewior <bigeasy@linutronix.de>
Signed-off-by: Maarten Lankhorst <dev@lankhorst.se>
---
 drivers/gpu/drm/i915/display/intel_crtc.c   | 9 ++++++---
 drivers/gpu/drm/i915/display/intel_cursor.c | 9 ++++++---
 drivers/gpu/drm/i915/display/intel_vblank.c | 6 ++++--
 3 files changed, 16 insertions(+), 8 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_crtc.c b/drivers/gpu/drm/i915/display/intel_crtc.c
index d300ba1dcd2c4..f34745b5ea497 100644
--- a/drivers/gpu/drm/i915/display/intel_crtc.c
+++ b/drivers/gpu/drm/i915/display/intel_crtc.c
@@ -567,7 +567,8 @@ void intel_pipe_update_start(struct intel_atomic_state *state,
 	 */
 	intel_psr_wait_for_idle_locked(new_crtc_state);
 
-	local_irq_disable();
+	if (!IS_ENABLED(CONFIG_PREEMPT_RT))
+		local_irq_disable();
 
 	crtc->debug.min_vbl = evade.min;
 	crtc->debug.max_vbl = evade.max;
@@ -585,7 +586,8 @@ void intel_pipe_update_start(struct intel_atomic_state *state,
 	return;
 
 irq_disable:
-	local_irq_disable();
+	if (!IS_ENABLED(CONFIG_PREEMPT_RT))
+		local_irq_disable();
 }
 
 #if IS_ENABLED(CONFIG_DRM_I915_DEBUG_VBLANK_EVADE)
@@ -731,7 +733,8 @@ void intel_pipe_update_end(struct intel_atomic_state *state,
 	if (!state->base.legacy_cursor_update)
 		intel_vrr_send_push(NULL, new_crtc_state);
 
-	local_irq_enable();
+	if (!IS_ENABLED(CONFIG_PREEMPT_RT))
+		local_irq_enable();
 
 	if (intel_vgpu_active(dev_priv))
 		goto out;
diff --git a/drivers/gpu/drm/i915/display/intel_cursor.c b/drivers/gpu/drm/i915/display/intel_cursor.c
index c47c849358714..780fcae77a984 100644
--- a/drivers/gpu/drm/i915/display/intel_cursor.c
+++ b/drivers/gpu/drm/i915/display/intel_cursor.c
@@ -919,13 +919,15 @@ intel_legacy_cursor_update(struct drm_plane *_plane,
 		 */
 		intel_psr_wait_for_idle_locked(crtc_state);
 
-		local_irq_disable();
+		if (!IS_ENABLED(CONFIG_PREEMPT_RT))
+			local_irq_disable();
 
 		intel_vblank_evade(&evade);
 
 		drm_crtc_vblank_put(&crtc->base);
 	} else {
-		local_irq_disable();
+		if (!IS_ENABLED(CONFIG_PREEMPT_RT))
+			local_irq_disable();
 	}
 
 	if (new_plane_state->uapi.visible) {
@@ -935,7 +937,8 @@ intel_legacy_cursor_update(struct drm_plane *_plane,
 		intel_plane_disable_arm(NULL, plane, crtc_state);
 	}
 
-	local_irq_enable();
+	if (!IS_ENABLED(CONFIG_PREEMPT_RT))
+		local_irq_enable();
 
 	intel_psr_unlock(crtc_state);
 
diff --git a/drivers/gpu/drm/i915/display/intel_vblank.c b/drivers/gpu/drm/i915/display/intel_vblank.c
index 5206a81f85554..7826f29619a14 100644
--- a/drivers/gpu/drm/i915/display/intel_vblank.c
+++ b/drivers/gpu/drm/i915/display/intel_vblank.c
@@ -761,11 +761,13 @@ int intel_vblank_evade(struct intel_vblank_evade_ctx *evade)
 			break;
 		}
 
-		local_irq_enable();
+		if (!IS_ENABLED(CONFIG_PREEMPT_RT))
+			local_irq_enable();
 
 		timeout = schedule_timeout(timeout);
 
-		local_irq_disable();
+		if (!IS_ENABLED(CONFIG_PREEMPT_RT))
+			local_irq_disable();
 	}
 
 	finish_wait(wq, &wait);
-- 
2.51.0

[FOR CI 4/5] drm/xe/display: Disable preemption in the most critical section

[Maarten Lankhorst]

Lets see what happens if we only disable preemption in the critical
section to ensure we do run as fast as possible without disabling
too much.

Second attempt: Disable preemption, but keep interrupts enabled.

Signed-off-by: Maarten Lankhorst <dev@lankhorst.se>
---
 drivers/gpu/drm/i915/display/intel_crtc.c   | 14 ++++++++++++++
 drivers/gpu/drm/i915/display/intel_cursor.c | 18 +++++++++++++++++-
 drivers/gpu/drm/i915/display/intel_vblank.c |  9 ++++++++-
 3 files changed, 39 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_crtc.c b/drivers/gpu/drm/i915/display/intel_crtc.c
index f34745b5ea497..939ef48859f16 100644
--- a/drivers/gpu/drm/i915/display/intel_crtc.c
+++ b/drivers/gpu/drm/i915/display/intel_crtc.c
@@ -569,6 +569,10 @@ void intel_pipe_update_start(struct intel_atomic_state *state,
 
 	if (!IS_ENABLED(CONFIG_PREEMPT_RT))
 		local_irq_disable();
+#ifndef I915
+	else
+		preempt_disable();
+#endif
 
 	crtc->debug.min_vbl = evade.min;
 	crtc->debug.max_vbl = evade.max;
@@ -588,6 +592,11 @@ void intel_pipe_update_start(struct intel_atomic_state *state,
 irq_disable:
 	if (!IS_ENABLED(CONFIG_PREEMPT_RT))
 		local_irq_disable();
+#ifndef I915
+	else
+		preempt_disable();
+#endif
+
 }
 
 #if IS_ENABLED(CONFIG_DRM_I915_DEBUG_VBLANK_EVADE)
@@ -686,6 +695,10 @@ void intel_pipe_update_end(struct intel_atomic_state *state,
 	    intel_crtc_has_type(new_crtc_state, INTEL_OUTPUT_DSI))
 		icl_dsi_frame_update(new_crtc_state);
 
+#if !defined(I915) && IS_ENABLED(CONFIG_PREEMPT_RT)
+	preempt_enable();
+#endif
+
 	/* We're still in the vblank-evade critical section, this can't race.
 	 * Would be slightly nice to just grab the vblank count and arm the
 	 * event outside of the critical section - the spinlock might spin for a
@@ -733,6 +746,7 @@ void intel_pipe_update_end(struct intel_atomic_state *state,
 	if (!state->base.legacy_cursor_update)
 		intel_vrr_send_push(NULL, new_crtc_state);
 
+	/* Re-enable irqs here for !RT */
 	if (!IS_ENABLED(CONFIG_PREEMPT_RT))
 		local_irq_enable();
 
diff --git a/drivers/gpu/drm/i915/display/intel_cursor.c b/drivers/gpu/drm/i915/display/intel_cursor.c
index 780fcae77a984..50ca39eb09145 100644
--- a/drivers/gpu/drm/i915/display/intel_cursor.c
+++ b/drivers/gpu/drm/i915/display/intel_cursor.c
@@ -912,6 +912,7 @@ intel_legacy_cursor_update(struct drm_plane *_plane,
 
 	intel_psr_lock(crtc_state);
 
+	bool vblanked = false;
 	if (!drm_WARN_ON(display->drm, drm_crtc_vblank_get(&crtc->base))) {
 		/*
 		 * TODO: maybe check if we're still in PSR
@@ -921,13 +922,21 @@ intel_legacy_cursor_update(struct drm_plane *_plane,
 
 		if (!IS_ENABLED(CONFIG_PREEMPT_RT))
 			local_irq_disable();
+#ifndef I915
+		else
+			preempt_disable();
+#endif
 
 		intel_vblank_evade(&evade);
 
-		drm_crtc_vblank_put(&crtc->base);
+		vblanked = true;
 	} else {
 		if (!IS_ENABLED(CONFIG_PREEMPT_RT))
 			local_irq_disable();
+#ifndef I915
+		else
+			preempt_disable();
+#endif
 	}
 
 	if (new_plane_state->uapi.visible) {
@@ -939,6 +948,10 @@ intel_legacy_cursor_update(struct drm_plane *_plane,
 
 	if (!IS_ENABLED(CONFIG_PREEMPT_RT))
 		local_irq_enable();
+#ifndef I915
+	else
+		preempt_enable();
+#endif
 
 	intel_psr_unlock(crtc_state);
 
@@ -955,6 +968,9 @@ intel_legacy_cursor_update(struct drm_plane *_plane,
 		intel_plane_unpin_fb(old_plane_state);
 	}
 
+	if (vblanked)
+		drm_crtc_vblank_put(&crtc->base);
+
 out_free:
 	if (new_crtc_state)
 		intel_crtc_destroy_state(&crtc->base, &new_crtc_state->uapi);
diff --git a/drivers/gpu/drm/i915/display/intel_vblank.c b/drivers/gpu/drm/i915/display/intel_vblank.c
index 7826f29619a14..1437a27ac5878 100644
--- a/drivers/gpu/drm/i915/display/intel_vblank.c
+++ b/drivers/gpu/drm/i915/display/intel_vblank.c
@@ -763,11 +763,18 @@ int intel_vblank_evade(struct intel_vblank_evade_ctx *evade)
 
 		if (!IS_ENABLED(CONFIG_PREEMPT_RT))
 			local_irq_enable();
+#ifndef I915
+		else
+			preempt_enable();
+#endif
 
 		timeout = schedule_timeout(timeout);
-
 		if (!IS_ENABLED(CONFIG_PREEMPT_RT))
 			local_irq_disable();
+#ifndef I915
+		else
+			preempt_disable();
+#endif
 	}
 
 	finish_wait(wq, &wait);
-- 
2.51.0

[FOR CI 5/5] PREEMPT_RT injection

[Maarten Lankhorst]

Signed-off-by: Maarten Lankhorst <dev@lankhorst.se>
---
 drivers/gpu/drm/i915/Kconfig.debug | 15 ---------------
 drivers/gpu/drm/xe/Kconfig.debug   |  5 +++++
 kernel/Kconfig.preempt             |  4 ++--
 3 files changed, 7 insertions(+), 17 deletions(-)

diff --git a/drivers/gpu/drm/i915/Kconfig.debug b/drivers/gpu/drm/i915/Kconfig.debug
index 3562a02ef7adc..0ab10ff41e38d 100644
--- a/drivers/gpu/drm/i915/Kconfig.debug
+++ b/drivers/gpu/drm/i915/Kconfig.debug
@@ -233,21 +233,6 @@ config DRM_I915_LOW_LEVEL_TRACEPOINTS
 
 	  If in doubt, say "N".
 
-config DRM_I915_DEBUG_VBLANK_EVADE
-	bool "Enable extra debug warnings for vblank evasion"
-	depends on DRM_I915
-	default n
-	help
-	  Choose this option to turn on extra debug warnings for the
-	  vblank evade mechanism. This gives a warning every time the
-	  the deadline allotted for the vblank evade critical section
-	  is exceeded, even if there isn't an actual risk of missing
-	  the vblank.
-
-	  Recommended for driver developers only.
-
-	  If in doubt, say "N".
-
 config DRM_I915_DEBUG_RUNTIME_PM
 	bool "Enable extra state checking for runtime PM"
 	depends on DRM_I915
diff --git a/drivers/gpu/drm/xe/Kconfig.debug b/drivers/gpu/drm/xe/Kconfig.debug
index 01227c77f6d70..1d5f11c6e88f3 100644
--- a/drivers/gpu/drm/xe/Kconfig.debug
+++ b/drivers/gpu/drm/xe/Kconfig.debug
@@ -30,6 +30,11 @@ config DRM_XE_DEBUG
 
 	  If in doubt, say "N".
 
+config DRM_I915_DEBUG_VBLANK_EVADE
+        def_bool y
+        depends on DRM_XE
+
+
 config DRM_XE_DEBUG_VM
 	bool "Enable extra VM debugging info"
 	default n
diff --git a/kernel/Kconfig.preempt b/kernel/Kconfig.preempt
index da326800c1c9b..68a6d42c55abe 100644
--- a/kernel/Kconfig.preempt
+++ b/kernel/Kconfig.preempt
@@ -87,9 +87,9 @@ config PREEMPT_LAZY
 endchoice
 
 config PREEMPT_RT
-	bool "Fully Preemptible Kernel (Real-Time)"
-	depends on EXPERT && ARCH_SUPPORTS_RT && !COMPILE_TEST
+	def_bool y
 	select PREEMPTION
+	depends on ARCH_SUPPORTS_RT
 	help
 	  This option turns the kernel into a real-time kernel by replacing
 	  various locking primitives (spinlocks, rwlocks, etc.) with
-- 
2.51.0

✗ CI.checkpatch: warning for drm/xe/display: Test series with PREEMPT_RT and preemption disable.

[Patchwork]

== Series Details ==

Series: drm/xe/display: Test series with PREEMPT_RT and preemption disable.
URL   : https://patchwork.freedesktop.org/series/156335/
State : warning

== Summary ==

+ KERNEL=/kernel
+ git clone https://gitlab.freedesktop.org/drm/maintainer-tools mt
Cloning into 'mt'...
warning: redirecting to https://gitlab.freedesktop.org/drm/maintainer-tools.git/
+ git -C mt rev-list -n1 origin/master
8677d3b99d5fd579c143b22605d99121e2482e8a
+ cd /kernel
+ git config --global --add safe.directory /kernel
+ git log -n1
commit af4bde47003a9180e5699ffb474f7beb9e6e9dfc
Author: Maarten Lankhorst <dev@lankhorst.se>
Date:   Wed Oct 22 14:13:07 2025 +0200

    PREEMPT_RT injection
    
    Signed-off-by: Maarten Lankhorst <dev@lankhorst.se>
+ /mt/dim checkpatch 74d9293d414f6967091764ccb2d2237d319558b5 drm-intel
db64d070a3c9 drm/xe: Bump xe_device_l2_flush even higher
5b03d5cccd5f drm/i915: Use preempt_disable/enable_rt() where recommended
-:7: WARNING:COMMIT_LOG_LONG_LINE: Prefer a maximum 75 chars per line (possible unwrapped commit description?)
#7: 
  ad3543ede630f ("drm/intel: Push get_scanout_position() timestamping into kms driver.")

-:45: WARNING:LINE_SPACING: Missing a blank line after declarations
#45: FILE: drivers/gpu/drm/i915/display/intel_vblank.c:323:
+	struct drm_i915_private *i915 = to_i915(display->drm);
+	spin_lock_irqsave(&i915->uncore.lock, *flags);

-:52: WARNING:LINE_SPACING: Missing a blank line after declarations
#52: FILE: drivers/gpu/drm/i915/display/intel_vblank.c:330:
+	struct drm_i915_private *i915 = to_i915(display->drm);
+	spin_unlock_irqrestore(&i915->uncore.lock, flags);

total: 0 errors, 3 warnings, 0 checks, 78 lines checked
e0ebaff63c92 drm/i915: Don't disable interrupts on PREEMPT_RT during atomic updates
-:10: WARNING:COMMIT_LOG_LONG_LINE: Prefer a maximum 75 chars per line (possible unwrapped commit description?)
#10: 
started disabling interrupts across atomic updates. This breaks on PREEMPT_RT

total: 0 errors, 1 warnings, 0 checks, 68 lines checked
598ed5be95e4 drm/xe/display: Disable preemption in the most critical section
af4bde47003a PREEMPT_RT injection
-:7: WARNING:COMMIT_MESSAGE: Missing commit description - Add an appropriate one

total: 0 errors, 1 warnings, 0 checks, 43 lines checked

✓ CI.KUnit: success for drm/xe/display: Test series with PREEMPT_RT and preemption disable.

[Patchwork]

== Series Details ==

Series: drm/xe/display: Test series with PREEMPT_RT and preemption disable.
URL   : https://patchwork.freedesktop.org/series/156335/
State : success

== Summary ==

+ trap cleanup EXIT
+ /kernel/tools/testing/kunit/kunit.py run --kunitconfig /kernel/drivers/gpu/drm/xe/.kunitconfig
[18:45:50] Configuring KUnit Kernel ...
Generating .config ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
[18:45:54] Building KUnit Kernel ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
Building with:
$ make all compile_commands.json scripts_gdb ARCH=um O=.kunit --jobs=48
[18:46:24] Starting KUnit Kernel (1/1)...
[18:46:24] ============================================================
Running tests with:
$ .kunit/linux kunit.enable=1 mem=1G console=tty kunit_shutdown=halt
[18:46:24] ================== guc_buf (11 subtests) ===================
[18:46:24] [PASSED] test_smallest
[18:46:24] [PASSED] test_largest
[18:46:24] [PASSED] test_granular
[18:46:24] [PASSED] test_unique
[18:46:24] [PASSED] test_overlap
[18:46:24] [PASSED] test_reusable
[18:46:24] [PASSED] test_too_big
[18:46:24] [PASSED] test_flush
[18:46:24] [PASSED] test_lookup
[18:46:24] [PASSED] test_data
[18:46:24] [PASSED] test_class
[18:46:24] ===================== [PASSED] guc_buf =====================
[18:46:24] =================== guc_dbm (7 subtests) ===================
[18:46:24] [PASSED] test_empty
[18:46:24] [PASSED] test_default
[18:46:24] ======================== test_size  ========================
[18:46:24] [PASSED] 4
[18:46:24] [PASSED] 8
[18:46:24] [PASSED] 32
[18:46:24] [PASSED] 256
[18:46:24] ==================== [PASSED] test_size ====================
[18:46:24] ======================= test_reuse  ========================
[18:46:24] [PASSED] 4
[18:46:24] [PASSED] 8
[18:46:24] [PASSED] 32
[18:46:24] [PASSED] 256
[18:46:24] =================== [PASSED] test_reuse ====================
[18:46:24] =================== test_range_overlap  ====================
[18:46:24] [PASSED] 4
[18:46:24] [PASSED] 8
[18:46:24] [PASSED] 32
[18:46:24] [PASSED] 256
[18:46:24] =============== [PASSED] test_range_overlap ================
[18:46:24] =================== test_range_compact  ====================
[18:46:24] [PASSED] 4
[18:46:24] [PASSED] 8
[18:46:24] [PASSED] 32
[18:46:24] [PASSED] 256
[18:46:24] =============== [PASSED] test_range_compact ================
[18:46:24] ==================== test_range_spare  =====================
[18:46:24] [PASSED] 4
[18:46:24] [PASSED] 8
[18:46:24] [PASSED] 32
[18:46:24] [PASSED] 256
[18:46:24] ================ [PASSED] test_range_spare =================
[18:46:24] ===================== [PASSED] guc_dbm =====================
[18:46:24] =================== guc_idm (6 subtests) ===================
[18:46:24] [PASSED] bad_init
[18:46:24] [PASSED] no_init
[18:46:24] [PASSED] init_fini
[18:46:24] [PASSED] check_used
[18:46:25] [PASSED] check_quota
[18:46:25] [PASSED] check_all
[18:46:25] ===================== [PASSED] guc_idm =====================
[18:46:25] ================== no_relay (3 subtests) ===================
[18:46:25] [PASSED] xe_drops_guc2pf_if_not_ready
[18:46:25] [PASSED] xe_drops_guc2vf_if_not_ready
[18:46:25] [PASSED] xe_rejects_send_if_not_ready
[18:46:25] ==================== [PASSED] no_relay =====================
[18:46:25] ================== pf_relay (14 subtests) ==================
[18:46:25] [PASSED] pf_rejects_guc2pf_too_short
[18:46:25] [PASSED] pf_rejects_guc2pf_too_long
[18:46:25] [PASSED] pf_rejects_guc2pf_no_payload
[18:46:25] [PASSED] pf_fails_no_payload
[18:46:25] [PASSED] pf_fails_bad_origin
[18:46:25] [PASSED] pf_fails_bad_type
[18:46:25] [PASSED] pf_txn_reports_error
[18:46:25] [PASSED] pf_txn_sends_pf2guc
[18:46:25] [PASSED] pf_sends_pf2guc
[18:46:25] [SKIPPED] pf_loopback_nop
[18:46:25] [SKIPPED] pf_loopback_echo
[18:46:25] [SKIPPED] pf_loopback_fail
[18:46:25] [SKIPPED] pf_loopback_busy
[18:46:25] [SKIPPED] pf_loopback_retry
[18:46:25] ==================== [PASSED] pf_relay =====================
[18:46:25] ================== vf_relay (3 subtests) ===================
[18:46:25] [PASSED] vf_rejects_guc2vf_too_short
[18:46:25] [PASSED] vf_rejects_guc2vf_too_long
[18:46:25] [PASSED] vf_rejects_guc2vf_no_payload
[18:46:25] ==================== [PASSED] vf_relay =====================
[18:46:25] ===================== lmtt (1 subtest) =====================
[18:46:25] ======================== test_ops  =========================
[18:46:25] [PASSED] 2-level
[18:46:25] [PASSED] multi-level
[18:46:25] ==================== [PASSED] test_ops =====================
[18:46:25] ====================== [PASSED] lmtt =======================
[18:46:25] ================= pf_service (11 subtests) =================
[18:46:25] [PASSED] pf_negotiate_any
[18:46:25] [PASSED] pf_negotiate_base_match
[18:46:25] [PASSED] pf_negotiate_base_newer
[18:46:25] [PASSED] pf_negotiate_base_next
[18:46:25] [SKIPPED] pf_negotiate_base_older
[18:46:25] [PASSED] pf_negotiate_base_prev
[18:46:25] [PASSED] pf_negotiate_latest_match
[18:46:25] [PASSED] pf_negotiate_latest_newer
[18:46:25] [PASSED] pf_negotiate_latest_next
[18:46:25] [SKIPPED] pf_negotiate_latest_older
[18:46:25] [SKIPPED] pf_negotiate_latest_prev
[18:46:25] =================== [PASSED] pf_service ====================
[18:46:25] ================= xe_guc_g2g (2 subtests) ==================
[18:46:25] ============== xe_live_guc_g2g_kunit_default  ==============
[18:46:25] ========= [SKIPPED] xe_live_guc_g2g_kunit_default ==========
[18:46:25] ============== xe_live_guc_g2g_kunit_allmem  ===============
[18:46:25] ========== [SKIPPED] xe_live_guc_g2g_kunit_allmem ==========
[18:46:25] =================== [SKIPPED] xe_guc_g2g ===================
[18:46:25] =================== xe_mocs (2 subtests) ===================
[18:46:25] ================ xe_live_mocs_kernel_kunit  ================
[18:46:25] =========== [SKIPPED] xe_live_mocs_kernel_kunit ============
[18:46:25] ================ xe_live_mocs_reset_kunit  =================
[18:46:25] ============ [SKIPPED] xe_live_mocs_reset_kunit ============
[18:46:25] ==================== [SKIPPED] xe_mocs =====================
[18:46:25] ================= xe_migrate (2 subtests) ==================
[18:46:25] ================= xe_migrate_sanity_kunit  =================
[18:46:25] ============ [SKIPPED] xe_migrate_sanity_kunit =============
[18:46:25] ================== xe_validate_ccs_kunit  ==================
[18:46:25] ============= [SKIPPED] xe_validate_ccs_kunit ==============
[18:46:25] =================== [SKIPPED] xe_migrate ===================
[18:46:25] ================== xe_dma_buf (1 subtest) ==================
[18:46:25] ==================== xe_dma_buf_kunit  =====================
[18:46:25] ================ [SKIPPED] xe_dma_buf_kunit ================
[18:46:25] =================== [SKIPPED] xe_dma_buf ===================
[18:46:25] ================= xe_bo_shrink (1 subtest) =================
[18:46:25] =================== xe_bo_shrink_kunit  ====================
[18:46:25] =============== [SKIPPED] xe_bo_shrink_kunit ===============
[18:46:25] ================== [SKIPPED] xe_bo_shrink ==================
[18:46:25] ==================== xe_bo (2 subtests) ====================
[18:46:25] ================== xe_ccs_migrate_kunit  ===================
[18:46:25] ============== [SKIPPED] xe_ccs_migrate_kunit ==============
[18:46:25] ==================== xe_bo_evict_kunit  ====================
[18:46:25] =============== [SKIPPED] xe_bo_evict_kunit ================
[18:46:25] ===================== [SKIPPED] xe_bo ======================
[18:46:25] ==================== args (11 subtests) ====================
[18:46:25] [PASSED] count_args_test
[18:46:25] [PASSED] call_args_example
[18:46:25] [PASSED] call_args_test
[18:46:25] [PASSED] drop_first_arg_example
[18:46:25] [PASSED] drop_first_arg_test
[18:46:25] [PASSED] first_arg_example
[18:46:25] [PASSED] first_arg_test
[18:46:25] [PASSED] last_arg_example
[18:46:25] [PASSED] last_arg_test
[18:46:25] [PASSED] pick_arg_example
[18:46:25] [PASSED] sep_comma_example
[18:46:25] ====================== [PASSED] args =======================
[18:46:25] =================== xe_pci (3 subtests) ====================
[18:46:25] ==================== check_graphics_ip  ====================
[18:46:25] [PASSED] 12.00 Xe_LP
[18:46:25] [PASSED] 12.10 Xe_LP+
[18:46:25] [PASSED] 12.55 Xe_HPG
[18:46:25] [PASSED] 12.60 Xe_HPC
[18:46:25] [PASSED] 12.70 Xe_LPG
[18:46:25] [PASSED] 12.71 Xe_LPG
[18:46:25] [PASSED] 12.74 Xe_LPG+
[18:46:25] [PASSED] 20.01 Xe2_HPG
[18:46:25] [PASSED] 20.02 Xe2_HPG
[18:46:25] [PASSED] 20.04 Xe2_LPG
[18:46:25] [PASSED] 30.00 Xe3_LPG
[18:46:25] [PASSED] 30.01 Xe3_LPG
[18:46:25] [PASSED] 30.03 Xe3_LPG
[18:46:25] [PASSED] 30.04 Xe3_LPG
[18:46:25] [PASSED] 30.05 Xe3_LPG
[18:46:25] [PASSED] 35.11 Xe3p_XPC
[18:46:25] ================ [PASSED] check_graphics_ip ================
[18:46:25] ===================== check_media_ip  ======================
[18:46:25] [PASSED] 12.00 Xe_M
[18:46:25] [PASSED] 12.55 Xe_HPM
[18:46:25] [PASSED] 13.00 Xe_LPM+
[18:46:25] [PASSED] 13.01 Xe2_HPM
[18:46:25] [PASSED] 20.00 Xe2_LPM
[18:46:25] [PASSED] 30.00 Xe3_LPM
[18:46:25] [PASSED] 30.02 Xe3_LPM
[18:46:25] [PASSED] 35.00 Xe3p_LPM
[18:46:25] [PASSED] 35.03 Xe3p_HPM
[18:46:25] ================= [PASSED] check_media_ip ==================
[18:46:25] =================== check_platform_desc  ===================
[18:46:25] [PASSED] 0x9A60 (TIGERLAKE)
[18:46:25] [PASSED] 0x9A68 (TIGERLAKE)
[18:46:25] [PASSED] 0x9A70 (TIGERLAKE)
[18:46:25] [PASSED] 0x9A40 (TIGERLAKE)
[18:46:25] [PASSED] 0x9A49 (TIGERLAKE)
[18:46:25] [PASSED] 0x9A59 (TIGERLAKE)
[18:46:25] [PASSED] 0x9A78 (TIGERLAKE)
[18:46:25] [PASSED] 0x9AC0 (TIGERLAKE)
[18:46:25] [PASSED] 0x9AC9 (TIGERLAKE)
[18:46:25] [PASSED] 0x9AD9 (TIGERLAKE)
[18:46:25] [PASSED] 0x9AF8 (TIGERLAKE)
[18:46:25] [PASSED] 0x4C80 (ROCKETLAKE)
[18:46:25] [PASSED] 0x4C8A (ROCKETLAKE)
[18:46:25] [PASSED] 0x4C8B (ROCKETLAKE)
[18:46:25] [PASSED] 0x4C8C (ROCKETLAKE)
[18:46:25] [PASSED] 0x4C90 (ROCKETLAKE)
[18:46:25] [PASSED] 0x4C9A (ROCKETLAKE)
[18:46:25] [PASSED] 0x4680 (ALDERLAKE_S)
[18:46:25] [PASSED] 0x4682 (ALDERLAKE_S)
[18:46:25] [PASSED] 0x4688 (ALDERLAKE_S)
[18:46:25] [PASSED] 0x468A (ALDERLAKE_S)
[18:46:25] [PASSED] 0x468B (ALDERLAKE_S)
[18:46:25] [PASSED] 0x4690 (ALDERLAKE_S)
[18:46:25] [PASSED] 0x4692 (ALDERLAKE_S)
[18:46:25] [PASSED] 0x4693 (ALDERLAKE_S)
[18:46:25] [PASSED] 0x46A0 (ALDERLAKE_P)
[18:46:25] [PASSED] 0x46A1 (ALDERLAKE_P)
[18:46:25] [PASSED] 0x46A2 (ALDERLAKE_P)
[18:46:25] [PASSED] 0x46A3 (ALDERLAKE_P)
[18:46:25] [PASSED] 0x46A6 (ALDERLAKE_P)
[18:46:25] [PASSED] 0x46A8 (ALDERLAKE_P)
[18:46:25] [PASSED] 0x46AA (ALDERLAKE_P)
[18:46:25] [PASSED] 0x462A (ALDERLAKE_P)
[18:46:25] [PASSED] 0x4626 (ALDERLAKE_P)
[18:46:25] [PASSED] 0x4628 (ALDERLAKE_P)
[18:46:25] [PASSED] 0x46B0 (ALDERLAKE_P)
[18:46:25] [PASSED] 0x46B1 (ALDERLAKE_P)
[18:46:25] [PASSED] 0x46B2 (ALDERLAKE_P)
[18:46:25] [PASSED] 0x46B3 (ALDERLAKE_P)
[18:46:25] [PASSED] 0x46C0 (ALDERLAKE_P)
[18:46:25] [PASSED] 0x46C1 (ALDERLAKE_P)
[18:46:25] [PASSED] 0x46C2 (ALDERLAKE_P)
[18:46:25] [PASSED] 0x46C3 (ALDERLAKE_P)
[18:46:25] [PASSED] 0x46D0 (ALDERLAKE_N)
[18:46:25] [PASSED] 0x46D1 (ALDERLAKE_N)
[18:46:25] [PASSED] 0x46D2 (ALDERLAKE_N)
[18:46:25] [PASSED] 0x46D3 (ALDERLAKE_N)
[18:46:25] [PASSED] 0x46D4 (ALDERLAKE_N)
[18:46:25] [PASSED] 0xA721 (ALDERLAKE_P)
[18:46:25] [PASSED] 0xA7A1 (ALDERLAKE_P)
[18:46:25] [PASSED] 0xA7A9 (ALDERLAKE_P)
[18:46:25] [PASSED] 0xA7AC (ALDERLAKE_P)
[18:46:25] [PASSED] 0xA7AD (ALDERLAKE_P)
[18:46:25] [PASSED] 0xA720 (ALDERLAKE_P)
[18:46:25] [PASSED] 0xA7A0 (ALDERLAKE_P)
[18:46:25] [PASSED] 0xA7A8 (ALDERLAKE_P)
[18:46:25] [PASSED] 0xA7AA (ALDERLAKE_P)
[18:46:25] [PASSED] 0xA7AB (ALDERLAKE_P)
[18:46:25] [PASSED] 0xA780 (ALDERLAKE_S)
[18:46:25] [PASSED] 0xA781 (ALDERLAKE_S)
[18:46:25] [PASSED] 0xA782 (ALDERLAKE_S)
[18:46:25] [PASSED] 0xA783 (ALDERLAKE_S)
[18:46:25] [PASSED] 0xA788 (ALDERLAKE_S)
[18:46:25] [PASSED] 0xA789 (ALDERLAKE_S)
[18:46:25] [PASSED] 0xA78A (ALDERLAKE_S)
[18:46:25] [PASSED] 0xA78B (ALDERLAKE_S)
[18:46:25] [PASSED] 0x4905 (DG1)
[18:46:25] [PASSED] 0x4906 (DG1)
[18:46:25] [PASSED] 0x4907 (DG1)
[18:46:25] [PASSED] 0x4908 (DG1)
[18:46:25] [PASSED] 0x4909 (DG1)
[18:46:25] [PASSED] 0x56C0 (DG2)
[18:46:25] [PASSED] 0x56C2 (DG2)
[18:46:25] [PASSED] 0x56C1 (DG2)
[18:46:25] [PASSED] 0x7D51 (METEORLAKE)
[18:46:25] [PASSED] 0x7DD1 (METEORLAKE)
[18:46:25] [PASSED] 0x7D41 (METEORLAKE)
[18:46:25] [PASSED] 0x7D67 (METEORLAKE)
[18:46:25] [PASSED] 0xB640 (METEORLAKE)
[18:46:25] [PASSED] 0x56A0 (DG2)
[18:46:25] [PASSED] 0x56A1 (DG2)
[18:46:25] [PASSED] 0x56A2 (DG2)
[18:46:25] [PASSED] 0x56BE (DG2)
[18:46:25] [PASSED] 0x56BF (DG2)
[18:46:25] [PASSED] 0x5690 (DG2)
[18:46:25] [PASSED] 0x5691 (DG2)
[18:46:25] [PASSED] 0x5692 (DG2)
[18:46:25] [PASSED] 0x56A5 (DG2)
[18:46:25] [PASSED] 0x56A6 (DG2)
[18:46:25] [PASSED] 0x56B0 (DG2)
[18:46:25] [PASSED] 0x56B1 (DG2)
[18:46:25] [PASSED] 0x56BA (DG2)
[18:46:25] [PASSED] 0x56BB (DG2)
[18:46:25] [PASSED] 0x56BC (DG2)
[18:46:25] [PASSED] 0x56BD (DG2)
[18:46:25] [PASSED] 0x5693 (DG2)
[18:46:25] [PASSED] 0x5694 (DG2)
[18:46:25] [PASSED] 0x5695 (DG2)
[18:46:25] [PASSED] 0x56A3 (DG2)
[18:46:25] [PASSED] 0x56A4 (DG2)
[18:46:25] [PASSED] 0x56B2 (DG2)
[18:46:25] [PASSED] 0x56B3 (DG2)
[18:46:25] [PASSED] 0x5696 (DG2)
[18:46:25] [PASSED] 0x5697 (DG2)
[18:46:25] [PASSED] 0xB69 (PVC)
[18:46:25] [PASSED] 0xB6E (PVC)
[18:46:25] [PASSED] 0xBD4 (PVC)
[18:46:25] [PASSED] 0xBD5 (PVC)
[18:46:25] [PASSED] 0xBD6 (PVC)
[18:46:25] [PASSED] 0xBD7 (PVC)
[18:46:25] [PASSED] 0xBD8 (PVC)
[18:46:25] [PASSED] 0xBD9 (PVC)
[18:46:25] [PASSED] 0xBDA (PVC)
[18:46:25] [PASSED] 0xBDB (PVC)
[18:46:25] [PASSED] 0xBE0 (PVC)
[18:46:25] [PASSED] 0xBE1 (PVC)
[18:46:25] [PASSED] 0xBE5 (PVC)
[18:46:25] [PASSED] 0x7D40 (METEORLAKE)
[18:46:25] [PASSED] 0x7D45 (METEORLAKE)
[18:46:25] [PASSED] 0x7D55 (METEORLAKE)
[18:46:25] [PASSED] 0x7D60 (METEORLAKE)
[18:46:25] [PASSED] 0x7DD5 (METEORLAKE)
[18:46:25] [PASSED] 0x6420 (LUNARLAKE)
[18:46:25] [PASSED] 0x64A0 (LUNARLAKE)
[18:46:25] [PASSED] 0x64B0 (LUNARLAKE)
[18:46:25] [PASSED] 0xE202 (BATTLEMAGE)
[18:46:25] [PASSED] 0xE209 (BATTLEMAGE)
[18:46:25] [PASSED] 0xE20B (BATTLEMAGE)
[18:46:25] [PASSED] 0xE20C (BATTLEMAGE)
[18:46:25] [PASSED] 0xE20D (BATTLEMAGE)
[18:46:25] [PASSED] 0xE210 (BATTLEMAGE)
[18:46:25] [PASSED] 0xE211 (BATTLEMAGE)
[18:46:25] [PASSED] 0xE212 (BATTLEMAGE)
[18:46:25] [PASSED] 0xE216 (BATTLEMAGE)
[18:46:25] [PASSED] 0xE220 (BATTLEMAGE)
[18:46:25] [PASSED] 0xE221 (BATTLEMAGE)
[18:46:25] [PASSED] 0xE222 (BATTLEMAGE)
[18:46:25] [PASSED] 0xE223 (BATTLEMAGE)
[18:46:25] [PASSED] 0xB080 (PANTHERLAKE)
[18:46:25] [PASSED] 0xB081 (PANTHERLAKE)
[18:46:25] [PASSED] 0xB082 (PANTHERLAKE)
[18:46:25] [PASSED] 0xB083 (PANTHERLAKE)
[18:46:25] [PASSED] 0xB084 (PANTHERLAKE)
[18:46:25] [PASSED] 0xB085 (PANTHERLAKE)
[18:46:25] [PASSED] 0xB086 (PANTHERLAKE)
[18:46:25] [PASSED] 0xB087 (PANTHERLAKE)
[18:46:25] [PASSED] 0xB08F (PANTHERLAKE)
[18:46:25] [PASSED] 0xB090 (PANTHERLAKE)
[18:46:25] [PASSED] 0xB0A0 (PANTHERLAKE)
[18:46:25] [PASSED] 0xB0B0 (PANTHERLAKE)
[18:46:25] [PASSED] 0xFD80 (PANTHERLAKE)
[18:46:25] [PASSED] 0xFD81 (PANTHERLAKE)
[18:46:25] [PASSED] 0xD740 (NOVALAKE_S)
[18:46:25] [PASSED] 0xD741 (NOVALAKE_S)
[18:46:25] [PASSED] 0xD742 (NOVALAKE_S)
[18:46:25] [PASSED] 0xD743 (NOVALAKE_S)
[18:46:25] [PASSED] 0xD744 (NOVALAKE_S)
[18:46:25] [PASSED] 0xD745 (NOVALAKE_S)
[18:46:25] =============== [PASSED] check_platform_desc ===============
[18:46:25] ===================== [PASSED] xe_pci ======================
[18:46:25] =================== xe_rtp (2 subtests) ====================
[18:46:25] =============== xe_rtp_process_to_sr_tests  ================
[18:46:25] [PASSED] coalesce-same-reg
[18:46:25] [PASSED] no-match-no-add
[18:46:25] [PASSED] match-or
[18:46:25] [PASSED] match-or-xfail
[18:46:25] [PASSED] no-match-no-add-multiple-rules
[18:46:25] [PASSED] two-regs-two-entries
[18:46:25] [PASSED] clr-one-set-other
[18:46:25] [PASSED] set-field
[18:46:25] [PASSED] conflict-duplicate
[18:46:25] [PASSED] conflict-not-disjoint
[18:46:25] [PASSED] conflict-reg-type
[18:46:25] =========== [PASSED] xe_rtp_process_to_sr_tests ============
[18:46:25] ================== xe_rtp_process_tests  ===================
[18:46:25] [PASSED] active1
[18:46:25] [PASSED] active2
[18:46:25] [PASSED] active-inactive
[18:46:25] [PASSED] inactive-active
[18:46:25] [PASSED] inactive-1st_or_active-inactive
[18:46:25] [PASSED] inactive-2nd_or_active-inactive
[18:46:25] [PASSED] inactive-last_or_active-inactive
[18:46:25] [PASSED] inactive-no_or_active-inactive
stty: 'standard input': Inappropriate ioctl for device
[18:46:25] ============== [PASSED] xe_rtp_process_tests ===============
[18:46:25] ===================== [PASSED] xe_rtp ======================
[18:46:25] ==================== xe_wa (1 subtest) =====================
[18:46:25] ======================== xe_wa_gt  =========================
[18:46:25] [PASSED] TIGERLAKE B0
[18:46:25] [PASSED] DG1 A0
[18:46:25] [PASSED] DG1 B0
[18:46:25] [PASSED] ALDERLAKE_S A0
[18:46:25] [PASSED] ALDERLAKE_S B0
[18:46:25] [PASSED] ALDERLAKE_S C0
[18:46:25] [PASSED] ALDERLAKE_S D0
[18:46:25] [PASSED] ALDERLAKE_P A0
[18:46:25] [PASSED] ALDERLAKE_P B0
[18:46:25] [PASSED] ALDERLAKE_P C0
[18:46:25] [PASSED] ALDERLAKE_S RPLS D0
[18:46:25] [PASSED] ALDERLAKE_P RPLU E0
[18:46:25] [PASSED] DG2 G10 C0
[18:46:25] [PASSED] DG2 G11 B1
[18:46:25] [PASSED] DG2 G12 A1
[18:46:25] [PASSED] METEORLAKE 12.70(Xe_LPG) A0 13.00(Xe_LPM+) A0
[18:46:25] [PASSED] METEORLAKE 12.71(Xe_LPG) A0 13.00(Xe_LPM+) A0
[18:46:25] [PASSED] METEORLAKE 12.74(Xe_LPG+) A0 13.00(Xe_LPM+) A0
[18:46:25] [PASSED] LUNARLAKE 20.04(Xe2_LPG) A0 20.00(Xe2_LPM) A0
[18:46:25] [PASSED] LUNARLAKE 20.04(Xe2_LPG) B0 20.00(Xe2_LPM) A0
[18:46:25] [PASSED] BATTLEMAGE 20.01(Xe2_HPG) A0 13.01(Xe2_HPM) A1
[18:46:25] [PASSED] PANTHERLAKE 30.00(Xe3_LPG) A0 30.00(Xe3_LPM) A0
[18:46:25] ==================== [PASSED] xe_wa_gt =====================
[18:46:25] ====================== [PASSED] xe_wa ======================
[18:46:25] ============================================================
[18:46:25] Testing complete. Ran 317 tests: passed: 299, skipped: 18
[18:46:25] Elapsed time: 34.717s total, 4.269s configuring, 30.081s building, 0.333s running

+ /kernel/tools/testing/kunit/kunit.py run --kunitconfig /kernel/drivers/gpu/drm/tests/.kunitconfig
[18:46:25] Configuring KUnit Kernel ...
Regenerating .config ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
[18:46:26] Building KUnit Kernel ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
Building with:
$ make all compile_commands.json scripts_gdb ARCH=um O=.kunit --jobs=48
[18:46:51] Starting KUnit Kernel (1/1)...
[18:46:51] ============================================================
Running tests with:
$ .kunit/linux kunit.enable=1 mem=1G console=tty kunit_shutdown=halt
[18:46:51] ============ drm_test_pick_cmdline (2 subtests) ============
[18:46:51] [PASSED] drm_test_pick_cmdline_res_1920_1080_60
[18:46:51] =============== drm_test_pick_cmdline_named  ===============
[18:46:51] [PASSED] NTSC
[18:46:51] [PASSED] NTSC-J
[18:46:51] [PASSED] PAL
[18:46:51] [PASSED] PAL-M
[18:46:51] =========== [PASSED] drm_test_pick_cmdline_named ===========
[18:46:51] ============== [PASSED] drm_test_pick_cmdline ==============
[18:46:51] == drm_test_atomic_get_connector_for_encoder (1 subtest) ===
[18:46:51] [PASSED] drm_test_drm_atomic_get_connector_for_encoder
[18:46:51] ==== [PASSED] drm_test_atomic_get_connector_for_encoder ====
[18:46:51] =========== drm_validate_clone_mode (2 subtests) ===========
[18:46:51] ============== drm_test_check_in_clone_mode  ===============
[18:46:51] [PASSED] in_clone_mode
[18:46:51] [PASSED] not_in_clone_mode
[18:46:51] ========== [PASSED] drm_test_check_in_clone_mode ===========
[18:46:51] =============== drm_test_check_valid_clones  ===============
[18:46:51] [PASSED] not_in_clone_mode
[18:46:51] [PASSED] valid_clone
[18:46:51] [PASSED] invalid_clone
[18:46:51] =========== [PASSED] drm_test_check_valid_clones ===========
[18:46:51] ============= [PASSED] drm_validate_clone_mode =============
[18:46:51] ============= drm_validate_modeset (1 subtest) =============
[18:46:51] [PASSED] drm_test_check_connector_changed_modeset
[18:46:51] ============== [PASSED] drm_validate_modeset ===============
[18:46:51] ====== drm_test_bridge_get_current_state (2 subtests) ======
[18:46:51] [PASSED] drm_test_drm_bridge_get_current_state_atomic
[18:46:51] [PASSED] drm_test_drm_bridge_get_current_state_legacy
[18:46:51] ======== [PASSED] drm_test_bridge_get_current_state ========
[18:46:51] ====== drm_test_bridge_helper_reset_crtc (3 subtests) ======
[18:46:51] [PASSED] drm_test_drm_bridge_helper_reset_crtc_atomic
[18:46:51] [PASSED] drm_test_drm_bridge_helper_reset_crtc_atomic_disabled
[18:46:51] [PASSED] drm_test_drm_bridge_helper_reset_crtc_legacy
[18:46:51] ======== [PASSED] drm_test_bridge_helper_reset_crtc ========
[18:46:51] ============== drm_bridge_alloc (2 subtests) ===============
[18:46:51] [PASSED] drm_test_drm_bridge_alloc_basic
[18:46:51] [PASSED] drm_test_drm_bridge_alloc_get_put
[18:46:51] ================ [PASSED] drm_bridge_alloc =================
[18:46:51] ================== drm_buddy (8 subtests) ==================
[18:46:51] [PASSED] drm_test_buddy_alloc_limit
[18:46:51] [PASSED] drm_test_buddy_alloc_optimistic
[18:46:51] [PASSED] drm_test_buddy_alloc_pessimistic
[18:46:51] [PASSED] drm_test_buddy_alloc_pathological
[18:46:51] [PASSED] drm_test_buddy_alloc_contiguous
[18:46:51] [PASSED] drm_test_buddy_alloc_clear
[18:46:51] [PASSED] drm_test_buddy_alloc_range_bias
[18:46:51] [PASSED] drm_test_buddy_fragmentation_performance
[18:46:51] ==================== [PASSED] drm_buddy ====================
[18:46:51] ============= drm_cmdline_parser (40 subtests) =============
[18:46:51] [PASSED] drm_test_cmdline_force_d_only
[18:46:51] [PASSED] drm_test_cmdline_force_D_only_dvi
[18:46:51] [PASSED] drm_test_cmdline_force_D_only_hdmi
[18:46:51] [PASSED] drm_test_cmdline_force_D_only_not_digital
[18:46:51] [PASSED] drm_test_cmdline_force_e_only
[18:46:51] [PASSED] drm_test_cmdline_res
[18:46:51] [PASSED] drm_test_cmdline_res_vesa
[18:46:51] [PASSED] drm_test_cmdline_res_vesa_rblank
[18:46:51] [PASSED] drm_test_cmdline_res_rblank
[18:46:51] [PASSED] drm_test_cmdline_res_bpp
[18:46:51] [PASSED] drm_test_cmdline_res_refresh
[18:46:51] [PASSED] drm_test_cmdline_res_bpp_refresh
[18:46:51] [PASSED] drm_test_cmdline_res_bpp_refresh_interlaced
[18:46:51] [PASSED] drm_test_cmdline_res_bpp_refresh_margins
[18:46:51] [PASSED] drm_test_cmdline_res_bpp_refresh_force_off
[18:46:51] [PASSED] drm_test_cmdline_res_bpp_refresh_force_on
[18:46:51] [PASSED] drm_test_cmdline_res_bpp_refresh_force_on_analog
[18:46:51] [PASSED] drm_test_cmdline_res_bpp_refresh_force_on_digital
[18:46:51] [PASSED] drm_test_cmdline_res_bpp_refresh_interlaced_margins_force_on
[18:46:51] [PASSED] drm_test_cmdline_res_margins_force_on
[18:46:51] [PASSED] drm_test_cmdline_res_vesa_margins
[18:46:51] [PASSED] drm_test_cmdline_name
[18:46:51] [PASSED] drm_test_cmdline_name_bpp
[18:46:51] [PASSED] drm_test_cmdline_name_option
[18:46:51] [PASSED] drm_test_cmdline_name_bpp_option
[18:46:51] [PASSED] drm_test_cmdline_rotate_0
[18:46:51] [PASSED] drm_test_cmdline_rotate_90
[18:46:51] [PASSED] drm_test_cmdline_rotate_180
[18:46:51] [PASSED] drm_test_cmdline_rotate_270
[18:46:51] [PASSED] drm_test_cmdline_hmirror
[18:46:51] [PASSED] drm_test_cmdline_vmirror
[18:46:51] [PASSED] drm_test_cmdline_margin_options
[18:46:51] [PASSED] drm_test_cmdline_multiple_options
[18:46:51] [PASSED] drm_test_cmdline_bpp_extra_and_option
[18:46:51] [PASSED] drm_test_cmdline_extra_and_option
[18:46:51] [PASSED] drm_test_cmdline_freestanding_options
[18:46:51] [PASSED] drm_test_cmdline_freestanding_force_e_and_options
[18:46:51] [PASSED] drm_test_cmdline_panel_orientation
[18:46:51] ================ drm_test_cmdline_invalid  =================
[18:46:51] [PASSED] margin_only
[18:46:51] [PASSED] interlace_only
[18:46:51] [PASSED] res_missing_x
[18:46:51] [PASSED] res_missing_y
[18:46:51] [PASSED] res_bad_y
[18:46:51] [PASSED] res_missing_y_bpp
[18:46:51] [PASSED] res_bad_bpp
[18:46:51] [PASSED] res_bad_refresh
[18:46:51] [PASSED] res_bpp_refresh_force_on_off
[18:46:51] [PASSED] res_invalid_mode
[18:46:51] [PASSED] res_bpp_wrong_place_mode
[18:46:51] [PASSED] name_bpp_refresh
[18:46:51] [PASSED] name_refresh
[18:46:51] [PASSED] name_refresh_wrong_mode
[18:46:51] [PASSED] name_refresh_invalid_mode
[18:46:51] [PASSED] rotate_multiple
[18:46:51] [PASSED] rotate_invalid_val
[18:46:51] [PASSED] rotate_truncated
[18:46:51] [PASSED] invalid_option
[18:46:51] [PASSED] invalid_tv_option
[18:46:51] [PASSED] truncated_tv_option
[18:46:51] ============ [PASSED] drm_test_cmdline_invalid =============
[18:46:51] =============== drm_test_cmdline_tv_options  ===============
[18:46:51] [PASSED] NTSC
[18:46:51] [PASSED] NTSC_443
[18:46:51] [PASSED] NTSC_J
[18:46:51] [PASSED] PAL
[18:46:51] [PASSED] PAL_M
[18:46:51] [PASSED] PAL_N
[18:46:51] [PASSED] SECAM
[18:46:51] [PASSED] MONO_525
[18:46:51] [PASSED] MONO_625
[18:46:51] =========== [PASSED] drm_test_cmdline_tv_options ===========
[18:46:51] =============== [PASSED] drm_cmdline_parser ================
[18:46:51] ========== drmm_connector_hdmi_init (20 subtests) ==========
[18:46:51] [PASSED] drm_test_connector_hdmi_init_valid
[18:46:51] [PASSED] drm_test_connector_hdmi_init_bpc_8
[18:46:51] [PASSED] drm_test_connector_hdmi_init_bpc_10
[18:46:51] [PASSED] drm_test_connector_hdmi_init_bpc_12
[18:46:51] [PASSED] drm_test_connector_hdmi_init_bpc_invalid
[18:46:51] [PASSED] drm_test_connector_hdmi_init_bpc_null
[18:46:51] [PASSED] drm_test_connector_hdmi_init_formats_empty
[18:46:51] [PASSED] drm_test_connector_hdmi_init_formats_no_rgb
[18:46:51] === drm_test_connector_hdmi_init_formats_yuv420_allowed  ===
[18:46:51] [PASSED] supported_formats=0x9 yuv420_allowed=1
[18:46:51] [PASSED] supported_formats=0x9 yuv420_allowed=0
[18:46:51] [PASSED] supported_formats=0x3 yuv420_allowed=1
[18:46:51] [PASSED] supported_formats=0x3 yuv420_allowed=0
[18:46:51] === [PASSED] drm_test_connector_hdmi_init_formats_yuv420_allowed ===
[18:46:51] [PASSED] drm_test_connector_hdmi_init_null_ddc
[18:46:51] [PASSED] drm_test_connector_hdmi_init_null_product
[18:46:51] [PASSED] drm_test_connector_hdmi_init_null_vendor
[18:46:51] [PASSED] drm_test_connector_hdmi_init_product_length_exact
[18:46:51] [PASSED] drm_test_connector_hdmi_init_product_length_too_long
[18:46:51] [PASSED] drm_test_connector_hdmi_init_product_valid
[18:46:51] [PASSED] drm_test_connector_hdmi_init_vendor_length_exact
[18:46:51] [PASSED] drm_test_connector_hdmi_init_vendor_length_too_long
[18:46:51] [PASSED] drm_test_connector_hdmi_init_vendor_valid
[18:46:51] ========= drm_test_connector_hdmi_init_type_valid  =========
[18:46:51] [PASSED] HDMI-A
[18:46:51] [PASSED] HDMI-B
[18:46:51] ===== [PASSED] drm_test_connector_hdmi_init_type_valid =====
[18:46:51] ======== drm_test_connector_hdmi_init_type_invalid  ========
[18:46:51] [PASSED] Unknown
[18:46:51] [PASSED] VGA
[18:46:51] [PASSED] DVI-I
[18:46:51] [PASSED] DVI-D
[18:46:51] [PASSED] DVI-A
[18:46:51] [PASSED] Composite
[18:46:51] [PASSED] SVIDEO
[18:46:51] [PASSED] LVDS
[18:46:51] [PASSED] Component
[18:46:51] [PASSED] DIN
[18:46:51] [PASSED] DP
[18:46:51] [PASSED] TV
[18:46:51] [PASSED] eDP
[18:46:51] [PASSED] Virtual
[18:46:51] [PASSED] DSI
[18:46:51] [PASSED] DPI
[18:46:51] [PASSED] Writeback
[18:46:51] [PASSED] SPI
[18:46:51] [PASSED] USB
[18:46:51] ==== [PASSED] drm_test_connector_hdmi_init_type_invalid ====
[18:46:51] ============ [PASSED] drmm_connector_hdmi_init =============
[18:46:51] ============= drmm_connector_init (3 subtests) =============
[18:46:51] [PASSED] drm_test_drmm_connector_init
[18:46:51] [PASSED] drm_test_drmm_connector_init_null_ddc
[18:46:51] ========= drm_test_drmm_connector_init_type_valid  =========
[18:46:51] [PASSED] Unknown
[18:46:51] [PASSED] VGA
[18:46:51] [PASSED] DVI-I
[18:46:51] [PASSED] DVI-D
[18:46:51] [PASSED] DVI-A
[18:46:51] [PASSED] Composite
[18:46:51] [PASSED] SVIDEO
[18:46:51] [PASSED] LVDS
[18:46:51] [PASSED] Component
[18:46:51] [PASSED] DIN
[18:46:51] [PASSED] DP
[18:46:51] [PASSED] HDMI-A
[18:46:51] [PASSED] HDMI-B
[18:46:51] [PASSED] TV
[18:46:51] [PASSED] eDP
[18:46:51] [PASSED] Virtual
[18:46:51] [PASSED] DSI
[18:46:51] [PASSED] DPI
[18:46:51] [PASSED] Writeback
[18:46:51] [PASSED] SPI
[18:46:51] [PASSED] USB
[18:46:51] ===== [PASSED] drm_test_drmm_connector_init_type_valid =====
[18:46:51] =============== [PASSED] drmm_connector_init ===============
[18:46:51] ========= drm_connector_dynamic_init (6 subtests) ==========
[18:46:51] [PASSED] drm_test_drm_connector_dynamic_init
[18:46:51] [PASSED] drm_test_drm_connector_dynamic_init_null_ddc
[18:46:51] [PASSED] drm_test_drm_connector_dynamic_init_not_added
[18:46:51] [PASSED] drm_test_drm_connector_dynamic_init_properties
[18:46:51] ===== drm_test_drm_connector_dynamic_init_type_valid  ======
[18:46:51] [PASSED] Unknown
[18:46:51] [PASSED] VGA
[18:46:51] [PASSED] DVI-I
[18:46:51] [PASSED] DVI-D
[18:46:51] [PASSED] DVI-A
[18:46:51] [PASSED] Composite
[18:46:51] [PASSED] SVIDEO
[18:46:51] [PASSED] LVDS
[18:46:51] [PASSED] Component
[18:46:51] [PASSED] DIN
[18:46:51] [PASSED] DP
[18:46:51] [PASSED] HDMI-A
[18:46:51] [PASSED] HDMI-B
[18:46:51] [PASSED] TV
[18:46:51] [PASSED] eDP
[18:46:51] [PASSED] Virtual
[18:46:51] [PASSED] DSI
[18:46:51] [PASSED] DPI
[18:46:51] [PASSED] Writeback
[18:46:51] [PASSED] SPI
[18:46:51] [PASSED] USB
[18:46:51] = [PASSED] drm_test_drm_connector_dynamic_init_type_valid ==
[18:46:51] ======== drm_test_drm_connector_dynamic_init_name  =========
[18:46:51] [PASSED] Unknown
[18:46:51] [PASSED] VGA
[18:46:51] [PASSED] DVI-I
[18:46:51] [PASSED] DVI-D
[18:46:51] [PASSED] DVI-A
[18:46:51] [PASSED] Composite
[18:46:51] [PASSED] SVIDEO
[18:46:51] [PASSED] LVDS
[18:46:51] [PASSED] Component
[18:46:51] [PASSED] DIN
[18:46:51] [PASSED] DP
[18:46:51] [PASSED] HDMI-A
[18:46:51] [PASSED] HDMI-B
[18:46:51] [PASSED] TV
[18:46:51] [PASSED] eDP
[18:46:51] [PASSED] Virtual
[18:46:51] [PASSED] DSI
[18:46:51] [PASSED] DPI
[18:46:51] [PASSED] Writeback
[18:46:51] [PASSED] SPI
[18:46:51] [PASSED] USB
[18:46:51] ==== [PASSED] drm_test_drm_connector_dynamic_init_name =====
[18:46:51] =========== [PASSED] drm_connector_dynamic_init ============
[18:46:51] ==== drm_connector_dynamic_register_early (4 subtests) =====
[18:46:51] [PASSED] drm_test_drm_connector_dynamic_register_early_on_list
[18:46:51] [PASSED] drm_test_drm_connector_dynamic_register_early_defer
[18:46:51] [PASSED] drm_test_drm_connector_dynamic_register_early_no_init
[18:46:51] [PASSED] drm_test_drm_connector_dynamic_register_early_no_mode_object
[18:46:51] ====== [PASSED] drm_connector_dynamic_register_early =======
[18:46:51] ======= drm_connector_dynamic_register (7 subtests) ========
[18:46:51] [PASSED] drm_test_drm_connector_dynamic_register_on_list
[18:46:51] [PASSED] drm_test_drm_connector_dynamic_register_no_defer
[18:46:51] [PASSED] drm_test_drm_connector_dynamic_register_no_init
[18:46:51] [PASSED] drm_test_drm_connector_dynamic_register_mode_object
[18:46:51] [PASSED] drm_test_drm_connector_dynamic_register_sysfs
[18:46:51] [PASSED] drm_test_drm_connector_dynamic_register_sysfs_name
[18:46:51] [PASSED] drm_test_drm_connector_dynamic_register_debugfs
[18:46:51] ========= [PASSED] drm_connector_dynamic_register ==========
[18:46:51] = drm_connector_attach_broadcast_rgb_property (2 subtests) =
[18:46:51] [PASSED] drm_test_drm_connector_attach_broadcast_rgb_property
[18:46:51] [PASSED] drm_test_drm_connector_attach_broadcast_rgb_property_hdmi_connector
[18:46:51] === [PASSED] drm_connector_attach_broadcast_rgb_property ===
[18:46:51] ========== drm_get_tv_mode_from_name (2 subtests) ==========
[18:46:51] ========== drm_test_get_tv_mode_from_name_valid  ===========
[18:46:51] [PASSED] NTSC
[18:46:51] [PASSED] NTSC-443
[18:46:51] [PASSED] NTSC-J
[18:46:51] [PASSED] PAL
[18:46:51] [PASSED] PAL-M
[18:46:51] [PASSED] PAL-N
[18:46:51] [PASSED] SECAM
[18:46:51] [PASSED] Mono
[18:46:51] ====== [PASSED] drm_test_get_tv_mode_from_name_valid =======
[18:46:51] [PASSED] drm_test_get_tv_mode_from_name_truncated
[18:46:51] ============ [PASSED] drm_get_tv_mode_from_name ============
[18:46:51] = drm_test_connector_hdmi_compute_mode_clock (12 subtests) =
[18:46:51] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb
[18:46:51] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_10bpc
[18:46:51] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_10bpc_vic_1
[18:46:51] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_12bpc
[18:46:51] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_12bpc_vic_1
[18:46:51] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_double
[18:46:51] = drm_test_connector_hdmi_compute_mode_clock_yuv420_valid  =
[18:46:51] [PASSED] VIC 96
[18:46:51] [PASSED] VIC 97
[18:46:51] [PASSED] VIC 101
[18:46:51] [PASSED] VIC 102
[18:46:51] [PASSED] VIC 106
[18:46:51] [PASSED] VIC 107
[18:46:51] === [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv420_valid ===
[18:46:51] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv420_10_bpc
[18:46:51] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv420_12_bpc
[18:46:51] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv422_8_bpc
[18:46:51] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv422_10_bpc
[18:46:51] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv422_12_bpc
[18:46:51] === [PASSED] drm_test_connector_hdmi_compute_mode_clock ====
[18:46:51] == drm_hdmi_connector_get_broadcast_rgb_name (2 subtests) ==
[18:46:51] === drm_test_drm_hdmi_connector_get_broadcast_rgb_name  ====
[18:46:51] [PASSED] Automatic
[18:46:51] [PASSED] Full
[18:46:51] [PASSED] Limited 16:235
[18:46:51] === [PASSED] drm_test_drm_hdmi_connector_get_broadcast_rgb_name ===
[18:46:51] [PASSED] drm_test_drm_hdmi_connector_get_broadcast_rgb_name_invalid
[18:46:51] ==== [PASSED] drm_hdmi_connector_get_broadcast_rgb_name ====
[18:46:51] == drm_hdmi_connector_get_output_format_name (2 subtests) ==
[18:46:51] === drm_test_drm_hdmi_connector_get_output_format_name  ====
[18:46:51] [PASSED] RGB
[18:46:51] [PASSED] YUV 4:2:0
[18:46:51] [PASSED] YUV 4:2:2
[18:46:51] [PASSED] YUV 4:4:4
[18:46:51] === [PASSED] drm_test_drm_hdmi_connector_get_output_format_name ===
[18:46:51] [PASSED] drm_test_drm_hdmi_connector_get_output_format_name_invalid
[18:46:51] ==== [PASSED] drm_hdmi_connector_get_output_format_name ====
[18:46:51] ============= drm_damage_helper (21 subtests) ==============
[18:46:51] [PASSED] drm_test_damage_iter_no_damage
[18:46:51] [PASSED] drm_test_damage_iter_no_damage_fractional_src
[18:46:51] [PASSED] drm_test_damage_iter_no_damage_src_moved
[18:46:51] [PASSED] drm_test_damage_iter_no_damage_fractional_src_moved
[18:46:51] [PASSED] drm_test_damage_iter_no_damage_not_visible
[18:46:51] [PASSED] drm_test_damage_iter_no_damage_no_crtc
[18:46:51] [PASSED] drm_test_damage_iter_no_damage_no_fb
[18:46:51] [PASSED] drm_test_damage_iter_simple_damage
[18:46:51] [PASSED] drm_test_damage_iter_single_damage
[18:46:51] [PASSED] drm_test_damage_iter_single_damage_intersect_src
[18:46:51] [PASSED] drm_test_damage_iter_single_damage_outside_src
[18:46:51] [PASSED] drm_test_damage_iter_single_damage_fractional_src
[18:46:51] [PASSED] drm_test_damage_iter_single_damage_intersect_fractional_src
[18:46:51] [PASSED] drm_test_damage_iter_single_damage_outside_fractional_src
[18:46:51] [PASSED] drm_test_damage_iter_single_damage_src_moved
[18:46:51] [PASSED] drm_test_damage_iter_single_damage_fractional_src_moved
[18:46:51] [PASSED] drm_test_damage_iter_damage
[18:46:51] [PASSED] drm_test_damage_iter_damage_one_intersect
[18:46:51] [PASSED] drm_test_damage_iter_damage_one_outside
[18:46:51] [PASSED] drm_test_damage_iter_damage_src_moved
[18:46:51] [PASSED] drm_test_damage_iter_damage_not_visible
[18:46:51] ================ [PASSED] drm_damage_helper ================
[18:46:51] ============== drm_dp_mst_helper (3 subtests) ==============
[18:46:51] ============== drm_test_dp_mst_calc_pbn_mode  ==============
[18:46:51] [PASSED] Clock 154000 BPP 30 DSC disabled
[18:46:51] [PASSED] Clock 234000 BPP 30 DSC disabled
[18:46:51] [PASSED] Clock 297000 BPP 24 DSC disabled
[18:46:51] [PASSED] Clock 332880 BPP 24 DSC enabled
[18:46:51] [PASSED] Clock 324540 BPP 24 DSC enabled
[18:46:51] ========== [PASSED] drm_test_dp_mst_calc_pbn_mode ==========
[18:46:51] ============== drm_test_dp_mst_calc_pbn_div  ===============
[18:46:51] [PASSED] Link rate 2000000 lane count 4
[18:46:51] [PASSED] Link rate 2000000 lane count 2
[18:46:51] [PASSED] Link rate 2000000 lane count 1
[18:46:51] [PASSED] Link rate 1350000 lane count 4
[18:46:51] [PASSED] Link rate 1350000 lane count 2
[18:46:51] [PASSED] Link rate 1350000 lane count 1
[18:46:51] [PASSED] Link rate 1000000 lane count 4
[18:46:51] [PASSED] Link rate 1000000 lane count 2
[18:46:51] [PASSED] Link rate 1000000 lane count 1
[18:46:51] [PASSED] Link rate 810000 lane count 4
[18:46:51] [PASSED] Link rate 810000 lane count 2
[18:46:51] [PASSED] Link rate 810000 lane count 1
[18:46:51] [PASSED] Link rate 540000 lane count 4
[18:46:51] [PASSED] Link rate 540000 lane count 2
[18:46:51] [PASSED] Link rate 540000 lane count 1
[18:46:51] [PASSED] Link rate 270000 lane count 4
[18:46:51] [PASSED] Link rate 270000 lane count 2
[18:46:51] [PASSED] Link rate 270000 lane count 1
[18:46:51] [PASSED] Link rate 162000 lane count 4
[18:46:51] [PASSED] Link rate 162000 lane count 2
[18:46:51] [PASSED] Link rate 162000 lane count 1
[18:46:51] ========== [PASSED] drm_test_dp_mst_calc_pbn_div ===========
[18:46:51] ========= drm_test_dp_mst_sideband_msg_req_decode  =========
[18:46:51] [PASSED] DP_ENUM_PATH_RESOURCES with port number
[18:46:51] [PASSED] DP_POWER_UP_PHY with port number
[18:46:51] [PASSED] DP_POWER_DOWN_PHY with port number
[18:46:51] [PASSED] DP_ALLOCATE_PAYLOAD with SDP stream sinks
[18:46:51] [PASSED] DP_ALLOCATE_PAYLOAD with port number
[18:46:51] [PASSED] DP_ALLOCATE_PAYLOAD with VCPI
[18:46:51] [PASSED] DP_ALLOCATE_PAYLOAD with PBN
[18:46:51] [PASSED] DP_QUERY_PAYLOAD with port number
[18:46:51] [PASSED] DP_QUERY_PAYLOAD with VCPI
[18:46:51] [PASSED] DP_REMOTE_DPCD_READ with port number
[18:46:51] [PASSED] DP_REMOTE_DPCD_READ with DPCD address
[18:46:51] [PASSED] DP_REMOTE_DPCD_READ with max number of bytes
[18:46:51] [PASSED] DP_REMOTE_DPCD_WRITE with port number
[18:46:51] [PASSED] DP_REMOTE_DPCD_WRITE with DPCD address
[18:46:51] [PASSED] DP_REMOTE_DPCD_WRITE with data array
[18:46:51] [PASSED] DP_REMOTE_I2C_READ with port number
[18:46:51] [PASSED] DP_REMOTE_I2C_READ with I2C device ID
[18:46:51] [PASSED] DP_REMOTE_I2C_READ with transactions array
[18:46:51] [PASSED] DP_REMOTE_I2C_WRITE with port number
[18:46:51] [PASSED] DP_REMOTE_I2C_WRITE with I2C device ID
[18:46:51] [PASSED] DP_REMOTE_I2C_WRITE with data array
[18:46:51] [PASSED] DP_QUERY_STREAM_ENC_STATUS with stream ID
[18:46:51] [PASSED] DP_QUERY_STREAM_ENC_STATUS with client ID
[18:46:51] [PASSED] DP_QUERY_STREAM_ENC_STATUS with stream event
[18:46:51] [PASSED] DP_QUERY_STREAM_ENC_STATUS with valid stream event
[18:46:51] [PASSED] DP_QUERY_STREAM_ENC_STATUS with stream behavior
[18:46:51] [PASSED] DP_QUERY_STREAM_ENC_STATUS with a valid stream behavior
[18:46:51] ===== [PASSED] drm_test_dp_mst_sideband_msg_req_decode =====
[18:46:51] ================ [PASSED] drm_dp_mst_helper ================
[18:46:51] ================== drm_exec (7 subtests) ===================
[18:46:51] [PASSED] sanitycheck
[18:46:51] [PASSED] test_lock
[18:46:51] [PASSED] test_lock_unlock
[18:46:51] [PASSED] test_duplicates
[18:46:51] [PASSED] test_prepare
[18:46:51] [PASSED] test_prepare_array
[18:46:51] [PASSED] test_multiple_loops
[18:46:51] ==================== [PASSED] drm_exec =====================
[18:46:51] =========== drm_format_helper_test (17 subtests) ===========
[18:46:51] ============== drm_test_fb_xrgb8888_to_gray8  ==============
[18:46:51] [PASSED] single_pixel_source_buffer
[18:46:51] [PASSED] single_pixel_clip_rectangle
[18:46:51] [PASSED] well_known_colors
[18:46:51] [PASSED] destination_pitch
[18:46:51] ========== [PASSED] drm_test_fb_xrgb8888_to_gray8 ==========
[18:46:51] ============= drm_test_fb_xrgb8888_to_rgb332  ==============
[18:46:51] [PASSED] single_pixel_source_buffer
[18:46:51] [PASSED] single_pixel_clip_rectangle
[18:46:51] [PASSED] well_known_colors
[18:46:51] [PASSED] destination_pitch
[18:46:51] ========= [PASSED] drm_test_fb_xrgb8888_to_rgb332 ==========
[18:46:51] ============= drm_test_fb_xrgb8888_to_rgb565  ==============
[18:46:51] [PASSED] single_pixel_source_buffer
[18:46:51] [PASSED] single_pixel_clip_rectangle
[18:46:51] [PASSED] well_known_colors
[18:46:51] [PASSED] destination_pitch
[18:46:51] ========= [PASSED] drm_test_fb_xrgb8888_to_rgb565 ==========
[18:46:51] ============ drm_test_fb_xrgb8888_to_xrgb1555  =============
[18:46:51] [PASSED] single_pixel_source_buffer
[18:46:51] [PASSED] single_pixel_clip_rectangle
[18:46:51] [PASSED] well_known_colors
[18:46:51] [PASSED] destination_pitch
[18:46:51] ======== [PASSED] drm_test_fb_xrgb8888_to_xrgb1555 =========
[18:46:51] ============ drm_test_fb_xrgb8888_to_argb1555  =============
[18:46:51] [PASSED] single_pixel_source_buffer
[18:46:51] [PASSED] single_pixel_clip_rectangle
[18:46:51] [PASSED] well_known_colors
[18:46:51] [PASSED] destination_pitch
[18:46:51] ======== [PASSED] drm_test_fb_xrgb8888_to_argb1555 =========
[18:46:51] ============ drm_test_fb_xrgb8888_to_rgba5551  =============
[18:46:51] [PASSED] single_pixel_source_buffer
[18:46:51] [PASSED] single_pixel_clip_rectangle
[18:46:51] [PASSED] well_known_colors
[18:46:51] [PASSED] destination_pitch
[18:46:51] ======== [PASSED] drm_test_fb_xrgb8888_to_rgba5551 =========
[18:46:51] ============= drm_test_fb_xrgb8888_to_rgb888  ==============
[18:46:51] [PASSED] single_pixel_source_buffer
[18:46:51] [PASSED] single_pixel_clip_rectangle
[18:46:51] [PASSED] well_known_colors
[18:46:51] [PASSED] destination_pitch
[18:46:51] ========= [PASSED] drm_test_fb_xrgb8888_to_rgb888 ==========
[18:46:51] ============= drm_test_fb_xrgb8888_to_bgr888  ==============
[18:46:51] [PASSED] single_pixel_source_buffer
[18:46:51] [PASSED] single_pixel_clip_rectangle
[18:46:51] [PASSED] well_known_colors
[18:46:51] [PASSED] destination_pitch
[18:46:51] ========= [PASSED] drm_test_fb_xrgb8888_to_bgr888 ==========
[18:46:51] ============ drm_test_fb_xrgb8888_to_argb8888  =============
[18:46:51] [PASSED] single_pixel_source_buffer
[18:46:52] [PASSED] single_pixel_clip_rectangle
[18:46:52] [PASSED] well_known_colors
[18:46:52] [PASSED] destination_pitch
[18:46:52] ======== [PASSED] drm_test_fb_xrgb8888_to_argb8888 =========
[18:46:52] =========== drm_test_fb_xrgb8888_to_xrgb2101010  ===========
[18:46:52] [PASSED] single_pixel_source_buffer
[18:46:52] [PASSED] single_pixel_clip_rectangle
[18:46:52] [PASSED] well_known_colors
[18:46:52] [PASSED] destination_pitch
[18:46:52] ======= [PASSED] drm_test_fb_xrgb8888_to_xrgb2101010 =======
[18:46:52] =========== drm_test_fb_xrgb8888_to_argb2101010  ===========
[18:46:52] [PASSED] single_pixel_source_buffer
[18:46:52] [PASSED] single_pixel_clip_rectangle
[18:46:52] [PASSED] well_known_colors
[18:46:52] [PASSED] destination_pitch
[18:46:52] ======= [PASSED] drm_test_fb_xrgb8888_to_argb2101010 =======
[18:46:52] ============== drm_test_fb_xrgb8888_to_mono  ===============
[18:46:52] [PASSED] single_pixel_source_buffer
[18:46:52] [PASSED] single_pixel_clip_rectangle
[18:46:52] [PASSED] well_known_colors
[18:46:52] [PASSED] destination_pitch
[18:46:52] ========== [PASSED] drm_test_fb_xrgb8888_to_mono ===========
[18:46:52] ==================== drm_test_fb_swab  =====================
[18:46:52] [PASSED] single_pixel_source_buffer
[18:46:52] [PASSED] single_pixel_clip_rectangle
[18:46:52] [PASSED] well_known_colors
[18:46:52] [PASSED] destination_pitch
[18:46:52] ================ [PASSED] drm_test_fb_swab =================
[18:46:52] ============ drm_test_fb_xrgb8888_to_xbgr8888  =============
[18:46:52] [PASSED] single_pixel_source_buffer
[18:46:52] [PASSED] single_pixel_clip_rectangle
[18:46:52] [PASSED] well_known_colors
[18:46:52] [PASSED] destination_pitch
[18:46:52] ======== [PASSED] drm_test_fb_xrgb8888_to_xbgr8888 =========
[18:46:52] ============ drm_test_fb_xrgb8888_to_abgr8888  =============
[18:46:52] [PASSED] single_pixel_source_buffer
[18:46:52] [PASSED] single_pixel_clip_rectangle
[18:46:52] [PASSED] well_known_colors
[18:46:52] [PASSED] destination_pitch
[18:46:52] ======== [PASSED] drm_test_fb_xrgb8888_to_abgr8888 =========
[18:46:52] ================= drm_test_fb_clip_offset  =================
[18:46:52] [PASSED] pass through
[18:46:52] [PASSED] horizontal offset
[18:46:52] [PASSED] vertical offset
[18:46:52] [PASSED] horizontal and vertical offset
[18:46:52] [PASSED] horizontal offset (custom pitch)
[18:46:52] [PASSED] vertical offset (custom pitch)
[18:46:52] [PASSED] horizontal and vertical offset (custom pitch)
[18:46:52] ============= [PASSED] drm_test_fb_clip_offset =============
[18:46:52] =================== drm_test_fb_memcpy  ====================
[18:46:52] [PASSED] single_pixel_source_buffer: XR24 little-endian (0x34325258)
[18:46:52] [PASSED] single_pixel_source_buffer: XRA8 little-endian (0x38415258)
[18:46:52] [PASSED] single_pixel_source_buffer: YU24 little-endian (0x34325559)
[18:46:52] [PASSED] single_pixel_clip_rectangle: XB24 little-endian (0x34324258)
[18:46:52] [PASSED] single_pixel_clip_rectangle: XRA8 little-endian (0x38415258)
[18:46:52] [PASSED] single_pixel_clip_rectangle: YU24 little-endian (0x34325559)
[18:46:52] [PASSED] well_known_colors: XB24 little-endian (0x34324258)
[18:46:52] [PASSED] well_known_colors: XRA8 little-endian (0x38415258)
[18:46:52] [PASSED] well_known_colors: YU24 little-endian (0x34325559)
[18:46:52] [PASSED] destination_pitch: XB24 little-endian (0x34324258)
[18:46:52] [PASSED] destination_pitch: XRA8 little-endian (0x38415258)
[18:46:52] [PASSED] destination_pitch: YU24 little-endian (0x34325559)
[18:46:52] =============== [PASSED] drm_test_fb_memcpy ================
[18:46:52] ============= [PASSED] drm_format_helper_test ==============
[18:46:52] ================= drm_format (18 subtests) =================
[18:46:52] [PASSED] drm_test_format_block_width_invalid
[18:46:52] [PASSED] drm_test_format_block_width_one_plane
[18:46:52] [PASSED] drm_test_format_block_width_two_plane
[18:46:52] [PASSED] drm_test_format_block_width_three_plane
[18:46:52] [PASSED] drm_test_format_block_width_tiled
[18:46:52] [PASSED] drm_test_format_block_height_invalid
[18:46:52] [PASSED] drm_test_format_block_height_one_plane
[18:46:52] [PASSED] drm_test_format_block_height_two_plane
[18:46:52] [PASSED] drm_test_format_block_height_three_plane
[18:46:52] [PASSED] drm_test_format_block_height_tiled
[18:46:52] [PASSED] drm_test_format_min_pitch_invalid
[18:46:52] [PASSED] drm_test_format_min_pitch_one_plane_8bpp
[18:46:52] [PASSED] drm_test_format_min_pitch_one_plane_16bpp
[18:46:52] [PASSED] drm_test_format_min_pitch_one_plane_24bpp
[18:46:52] [PASSED] drm_test_format_min_pitch_one_plane_32bpp
[18:46:52] [PASSED] drm_test_format_min_pitch_two_plane
[18:46:52] [PASSED] drm_test_format_min_pitch_three_plane_8bpp
[18:46:52] [PASSED] drm_test_format_min_pitch_tiled
[18:46:52] =================== [PASSED] drm_format ====================
[18:46:52] ============== drm_framebuffer (10 subtests) ===============
[18:46:52] ========== drm_test_framebuffer_check_src_coords  ==========
[18:46:52] [PASSED] Success: source fits into fb
[18:46:52] [PASSED] Fail: overflowing fb with x-axis coordinate
[18:46:52] [PASSED] Fail: overflowing fb with y-axis coordinate
[18:46:52] [PASSED] Fail: overflowing fb with source width
[18:46:52] [PASSED] Fail: overflowing fb with source height
[18:46:52] ====== [PASSED] drm_test_framebuffer_check_src_coords ======
[18:46:52] [PASSED] drm_test_framebuffer_cleanup
[18:46:52] =============== drm_test_framebuffer_create  ===============
[18:46:52] [PASSED] ABGR8888 normal sizes
[18:46:52] [PASSED] ABGR8888 max sizes
[18:46:52] [PASSED] ABGR8888 pitch greater than min required
[18:46:52] [PASSED] ABGR8888 pitch less than min required
[18:46:52] [PASSED] ABGR8888 Invalid width
[18:46:52] [PASSED] ABGR8888 Invalid buffer handle
[18:46:52] [PASSED] No pixel format
[18:46:52] [PASSED] ABGR8888 Width 0
[18:46:52] [PASSED] ABGR8888 Height 0
[18:46:52] [PASSED] ABGR8888 Out of bound height * pitch combination
[18:46:52] [PASSED] ABGR8888 Large buffer offset
[18:46:52] [PASSED] ABGR8888 Buffer offset for inexistent plane
[18:46:52] [PASSED] ABGR8888 Invalid flag
[18:46:52] [PASSED] ABGR8888 Set DRM_MODE_FB_MODIFIERS without modifiers
[18:46:52] [PASSED] ABGR8888 Valid buffer modifier
[18:46:52] [PASSED] ABGR8888 Invalid buffer modifier(DRM_FORMAT_MOD_SAMSUNG_64_32_TILE)
[18:46:52] [PASSED] ABGR8888 Extra pitches without DRM_MODE_FB_MODIFIERS
[18:46:52] [PASSED] ABGR8888 Extra pitches with DRM_MODE_FB_MODIFIERS
[18:46:52] [PASSED] NV12 Normal sizes
[18:46:52] [PASSED] NV12 Max sizes
[18:46:52] [PASSED] NV12 Invalid pitch
[18:46:52] [PASSED] NV12 Invalid modifier/missing DRM_MODE_FB_MODIFIERS flag
[18:46:52] [PASSED] NV12 different  modifier per-plane
[18:46:52] [PASSED] NV12 with DRM_FORMAT_MOD_SAMSUNG_64_32_TILE
[18:46:52] [PASSED] NV12 Valid modifiers without DRM_MODE_FB_MODIFIERS
[18:46:52] [PASSED] NV12 Modifier for inexistent plane
[18:46:52] [PASSED] NV12 Handle for inexistent plane
[18:46:52] [PASSED] NV12 Handle for inexistent plane without DRM_MODE_FB_MODIFIERS
[18:46:52] [PASSED] YVU420 DRM_MODE_FB_MODIFIERS set without modifier
[18:46:52] [PASSED] YVU420 Normal sizes
[18:46:52] [PASSED] YVU420 Max sizes
[18:46:52] [PASSED] YVU420 Invalid pitch
[18:46:52] [PASSED] YVU420 Different pitches
[18:46:52] [PASSED] YVU420 Different buffer offsets/pitches
[18:46:52] [PASSED] YVU420 Modifier set just for plane 0, without DRM_MODE_FB_MODIFIERS
[18:46:52] [PASSED] YVU420 Modifier set just for planes 0, 1, without DRM_MODE_FB_MODIFIERS
[18:46:52] [PASSED] YVU420 Modifier set just for plane 0, 1, with DRM_MODE_FB_MODIFIERS
[18:46:52] [PASSED] YVU420 Valid modifier
[18:46:52] [PASSED] YVU420 Different modifiers per plane
[18:46:52] [PASSED] YVU420 Modifier for inexistent plane
[18:46:52] [PASSED] YUV420_10BIT Invalid modifier(DRM_FORMAT_MOD_LINEAR)
[18:46:52] [PASSED] X0L2 Normal sizes
[18:46:52] [PASSED] X0L2 Max sizes
[18:46:52] [PASSED] X0L2 Invalid pitch
[18:46:52] [PASSED] X0L2 Pitch greater than minimum required
[18:46:52] [PASSED] X0L2 Handle for inexistent plane
[18:46:52] [PASSED] X0L2 Offset for inexistent plane, without DRM_MODE_FB_MODIFIERS set
[18:46:52] [PASSED] X0L2 Modifier without DRM_MODE_FB_MODIFIERS set
[18:46:52] [PASSED] X0L2 Valid modifier
[18:46:52] [PASSED] X0L2 Modifier for inexistent plane
[18:46:52] =========== [PASSED] drm_test_framebuffer_create ===========
[18:46:52] [PASSED] drm_test_framebuffer_free
[18:46:52] [PASSED] drm_test_framebuffer_init
[18:46:52] [PASSED] drm_test_framebuffer_init_bad_format
[18:46:52] [PASSED] drm_test_framebuffer_init_dev_mismatch
[18:46:52] [PASSED] drm_test_framebuffer_lookup
[18:46:52] [PASSED] drm_test_framebuffer_lookup_inexistent
[18:46:52] [PASSED] drm_test_framebuffer_modifiers_not_supported
[18:46:52] ================= [PASSED] drm_framebuffer =================
[18:46:52] ================ drm_gem_shmem (8 subtests) ================
[18:46:52] [PASSED] drm_gem_shmem_test_obj_create
[18:46:52] [PASSED] drm_gem_shmem_test_obj_create_private
[18:46:52] [PASSED] drm_gem_shmem_test_pin_pages
[18:46:52] [PASSED] drm_gem_shmem_test_vmap
[18:46:52] [PASSED] drm_gem_shmem_test_get_pages_sgt
[18:46:52] [PASSED] drm_gem_shmem_test_get_sg_table
[18:46:52] [PASSED] drm_gem_shmem_test_madvise
[18:46:52] [PASSED] drm_gem_shmem_test_purge
[18:46:52] ================== [PASSED] drm_gem_shmem ==================
[18:46:52] === drm_atomic_helper_connector_hdmi_check (27 subtests) ===
[18:46:52] [PASSED] drm_test_check_broadcast_rgb_auto_cea_mode
[18:46:52] [PASSED] drm_test_check_broadcast_rgb_auto_cea_mode_vic_1
[18:46:52] [PASSED] drm_test_check_broadcast_rgb_full_cea_mode
[18:46:52] [PASSED] drm_test_check_broadcast_rgb_full_cea_mode_vic_1
[18:46:52] [PASSED] drm_test_check_broadcast_rgb_limited_cea_mode
[18:46:52] [PASSED] drm_test_check_broadcast_rgb_limited_cea_mode_vic_1
[18:46:52] ====== drm_test_check_broadcast_rgb_cea_mode_yuv420  =======
[18:46:52] [PASSED] Automatic
[18:46:52] [PASSED] Full
[18:46:52] [PASSED] Limited 16:235
[18:46:52] == [PASSED] drm_test_check_broadcast_rgb_cea_mode_yuv420 ===
[18:46:52] [PASSED] drm_test_check_broadcast_rgb_crtc_mode_changed
[18:46:52] [PASSED] drm_test_check_broadcast_rgb_crtc_mode_not_changed
[18:46:52] [PASSED] drm_test_check_disable_connector
[18:46:52] [PASSED] drm_test_check_hdmi_funcs_reject_rate
[18:46:52] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_rgb
[18:46:52] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_yuv420
[18:46:52] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_ignore_yuv422
[18:46:52] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_ignore_yuv420
[18:46:52] [PASSED] drm_test_check_driver_unsupported_fallback_yuv420
[18:46:52] [PASSED] drm_test_check_output_bpc_crtc_mode_changed
[18:46:52] [PASSED] drm_test_check_output_bpc_crtc_mode_not_changed
[18:46:52] [PASSED] drm_test_check_output_bpc_dvi
[18:46:52] [PASSED] drm_test_check_output_bpc_format_vic_1
[18:46:52] [PASSED] drm_test_check_output_bpc_format_display_8bpc_only
[18:46:52] [PASSED] drm_test_check_output_bpc_format_display_rgb_only
[18:46:52] [PASSED] drm_test_check_output_bpc_format_driver_8bpc_only
[18:46:52] [PASSED] drm_test_check_output_bpc_format_driver_rgb_only
[18:46:52] [PASSED] drm_test_check_tmds_char_rate_rgb_8bpc
[18:46:52] [PASSED] drm_test_check_tmds_char_rate_rgb_10bpc
[18:46:52] [PASSED] drm_test_check_tmds_char_rate_rgb_12bpc
[18:46:52] ===== [PASSED] drm_atomic_helper_connector_hdmi_check ======
[18:46:52] === drm_atomic_helper_connector_hdmi_reset (6 subtests) ====
[18:46:52] [PASSED] drm_test_check_broadcast_rgb_value
[18:46:52] [PASSED] drm_test_check_bpc_8_value
[18:46:52] [PASSED] drm_test_check_bpc_10_value
[18:46:52] [PASSED] drm_test_check_bpc_12_value
[18:46:52] [PASSED] drm_test_check_format_value
[18:46:52] [PASSED] drm_test_check_tmds_char_value
[18:46:52] ===== [PASSED] drm_atomic_helper_connector_hdmi_reset ======
[18:46:52] = drm_atomic_helper_connector_hdmi_mode_valid (4 subtests) =
[18:46:52] [PASSED] drm_test_check_mode_valid
[18:46:52] [PASSED] drm_test_check_mode_valid_reject
[18:46:52] [PASSED] drm_test_check_mode_valid_reject_rate
[18:46:52] [PASSED] drm_test_check_mode_valid_reject_max_clock
[18:46:52] === [PASSED] drm_atomic_helper_connector_hdmi_mode_valid ===
[18:46:52] ================= drm_managed (2 subtests) =================
[18:46:52] [PASSED] drm_test_managed_release_action
[18:46:52] [PASSED] drm_test_managed_run_action
[18:46:52] =================== [PASSED] drm_managed ===================
[18:46:52] =================== drm_mm (6 subtests) ====================
[18:46:52] [PASSED] drm_test_mm_init
[18:46:52] [PASSED] drm_test_mm_debug
[18:46:52] [PASSED] drm_test_mm_align32
[18:46:52] [PASSED] drm_test_mm_align64
[18:46:52] [PASSED] drm_test_mm_lowest
[18:46:52] [PASSED] drm_test_mm_highest
[18:46:52] ===================== [PASSED] drm_mm ======================
[18:46:52] ============= drm_modes_analog_tv (5 subtests) =============
[18:46:52] [PASSED] drm_test_modes_analog_tv_mono_576i
[18:46:52] [PASSED] drm_test_modes_analog_tv_ntsc_480i
[18:46:52] [PASSED] drm_test_modes_analog_tv_ntsc_480i_inlined
[18:46:52] [PASSED] drm_test_modes_analog_tv_pal_576i
[18:46:52] [PASSED] drm_test_modes_analog_tv_pal_576i_inlined
[18:46:52] =============== [PASSED] drm_modes_analog_tv ===============
[18:46:52] ============== drm_plane_helper (2 subtests) ===============
[18:46:52] =============== drm_test_check_plane_state  ================
[18:46:52] [PASSED] clipping_simple
[18:46:52] [PASSED] clipping_rotate_reflect
[18:46:52] [PASSED] positioning_simple
[18:46:52] [PASSED] upscaling
[18:46:52] [PASSED] downscaling
[18:46:52] [PASSED] rounding1
[18:46:52] [PASSED] rounding2
[18:46:52] [PASSED] rounding3
[18:46:52] [PASSED] rounding4
[18:46:52] =========== [PASSED] drm_test_check_plane_state ============
[18:46:52] =========== drm_test_check_invalid_plane_state  ============
[18:46:52] [PASSED] positioning_invalid
[18:46:52] [PASSED] upscaling_invalid
[18:46:52] [PASSED] downscaling_invalid
[18:46:52] ======= [PASSED] drm_test_check_invalid_plane_state ========
[18:46:52] ================ [PASSED] drm_plane_helper =================
[18:46:52] ====== drm_connector_helper_tv_get_modes (1 subtest) =======
[18:46:52] ====== drm_test_connector_helper_tv_get_modes_check  =======
[18:46:52] [PASSED] None
[18:46:52] [PASSED] PAL
[18:46:52] [PASSED] NTSC
[18:46:52] [PASSED] Both, NTSC Default
[18:46:52] [PASSED] Both, PAL Default
[18:46:52] [PASSED] Both, NTSC Default, with PAL on command-line
[18:46:52] [PASSED] Both, PAL Default, with NTSC on command-line
[18:46:52] == [PASSED] drm_test_connector_helper_tv_get_modes_check ===
[18:46:52] ======== [PASSED] drm_connector_helper_tv_get_modes ========
[18:46:52] ================== drm_rect (9 subtests) ===================
[18:46:52] [PASSED] drm_test_rect_clip_scaled_div_by_zero
[18:46:52] [PASSED] drm_test_rect_clip_scaled_not_clipped
[18:46:52] [PASSED] drm_test_rect_clip_scaled_clipped
[18:46:52] [PASSED] drm_test_rect_clip_scaled_signed_vs_unsigned
[18:46:52] ================= drm_test_rect_intersect  =================
[18:46:52] [PASSED] top-left x bottom-right: 2x2+1+1 x 2x2+0+0
[18:46:52] [PASSED] top-right x bottom-left: 2x2+0+0 x 2x2+1-1
[18:46:52] [PASSED] bottom-left x top-right: 2x2+1-1 x 2x2+0+0
[18:46:52] [PASSED] bottom-right x top-left: 2x2+0+0 x 2x2+1+1
[18:46:52] [PASSED] right x left: 2x1+0+0 x 3x1+1+0
[18:46:52] [PASSED] left x right: 3x1+1+0 x 2x1+0+0
[18:46:52] [PASSED] up x bottom: 1x2+0+0 x 1x3+0-1
[18:46:52] [PASSED] bottom x up: 1x3+0-1 x 1x2+0+0
[18:46:52] [PASSED] touching corner: 1x1+0+0 x 2x2+1+1
[18:46:52] [PASSED] touching side: 1x1+0+0 x 1x1+1+0
[18:46:52] [PASSED] equal rects: 2x2+0+0 x 2x2+0+0
[18:46:52] [PASSED] inside another: 2x2+0+0 x 1x1+1+1
[18:46:52] [PASSED] far away: 1x1+0+0 x 1x1+3+6
[18:46:52] [PASSED] points intersecting: 0x0+5+10 x 0x0+5+10
[18:46:52] [PASSED] points not intersecting: 0x0+0+0 x 0x0+5+10
[18:46:52] ============= [PASSED] drm_test_rect_intersect =============
[18:46:52] ================ drm_test_rect_calc_hscale  ================
[18:46:52] [PASSED] normal use
[18:46:52] [PASSED] out of max range
[18:46:52] [PASSED] out of min range
[18:46:52] [PASSED] zero dst
[18:46:52] [PASSED] negative src
[18:46:52] [PASSED] negative dst
[18:46:52] ============ [PASSED] drm_test_rect_calc_hscale ============
[18:46:52] ================ drm_test_rect_calc_vscale  ================
[18:46:52] [PASSED] normal use
stty: 'standard input': Inappropriate ioctl for device
[18:46:52] [PASSED] out of max range
[18:46:52] [PASSED] out of min range
[18:46:52] [PASSED] zero dst
[18:46:52] [PASSED] negative src
[18:46:52] [PASSED] negative dst
[18:46:52] ============ [PASSED] drm_test_rect_calc_vscale ============
[18:46:52] ================== drm_test_rect_rotate  ===================
[18:46:52] [PASSED] reflect-x
[18:46:52] [PASSED] reflect-y
[18:46:52] [PASSED] rotate-0
[18:46:52] [PASSED] rotate-90
[18:46:52] [PASSED] rotate-180
[18:46:52] [PASSED] rotate-270
[18:46:52] ============== [PASSED] drm_test_rect_rotate ===============
[18:46:52] ================ drm_test_rect_rotate_inv  =================
[18:46:52] [PASSED] reflect-x
[18:46:52] [PASSED] reflect-y
[18:46:52] [PASSED] rotate-0
[18:46:52] [PASSED] rotate-90
[18:46:52] [PASSED] rotate-180
[18:46:52] [PASSED] rotate-270
[18:46:52] ============ [PASSED] drm_test_rect_rotate_inv =============
[18:46:52] ==================== [PASSED] drm_rect =====================
[18:46:52] ============ drm_sysfb_modeset_test (1 subtest) ============
[18:46:52] ============ drm_test_sysfb_build_fourcc_list  =============
[18:46:52] [PASSED] no native formats
[18:46:52] [PASSED] XRGB8888 as native format
[18:46:52] [PASSED] remove duplicates
[18:46:52] [PASSED] convert alpha formats
[18:46:52] [PASSED] random formats
[18:46:52] ======== [PASSED] drm_test_sysfb_build_fourcc_list =========
[18:46:52] ============= [PASSED] drm_sysfb_modeset_test ==============
[18:46:52] ============================================================
[18:46:52] Testing complete. Ran 622 tests: passed: 622
[18:46:52] Elapsed time: 26.844s total, 1.695s configuring, 24.731s building, 0.388s running

+ /kernel/tools/testing/kunit/kunit.py run --kunitconfig /kernel/drivers/gpu/drm/ttm/tests/.kunitconfig
[18:46:52] Configuring KUnit Kernel ...
Regenerating .config ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
[18:46:53] Building KUnit Kernel ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
Building with:
$ make all compile_commands.json scripts_gdb ARCH=um O=.kunit --jobs=48
[18:47:03] Starting KUnit Kernel (1/1)...
[18:47:03] ============================================================
Running tests with:
$ .kunit/linux kunit.enable=1 mem=1G console=tty kunit_shutdown=halt
[18:47:03] ================= ttm_device (5 subtests) ==================
[18:47:03] [PASSED] ttm_device_init_basic
[18:47:03] [PASSED] ttm_device_init_multiple
[18:47:03] [PASSED] ttm_device_fini_basic
[18:47:03] [PASSED] ttm_device_init_no_vma_man
[18:47:03] ================== ttm_device_init_pools  ==================
[18:47:03] [PASSED] No DMA allocations, no DMA32 required
[18:47:03] [PASSED] DMA allocations, DMA32 required
[18:47:03] [PASSED] No DMA allocations, DMA32 required
[18:47:03] [PASSED] DMA allocations, no DMA32 required
[18:47:03] ============== [PASSED] ttm_device_init_pools ==============
[18:47:03] =================== [PASSED] ttm_device ====================
[18:47:03] ================== ttm_pool (8 subtests) ===================
[18:47:03] ================== ttm_pool_alloc_basic  ===================
[18:47:03] [PASSED] One page
[18:47:03] [PASSED] More than one page
[18:47:03] [PASSED] Above the allocation limit
[18:47:03] [PASSED] One page, with coherent DMA mappings enabled
[18:47:03] [PASSED] Above the allocation limit, with coherent DMA mappings enabled
[18:47:03] ============== [PASSED] ttm_pool_alloc_basic ===============
[18:47:03] ============== ttm_pool_alloc_basic_dma_addr  ==============
[18:47:03] [PASSED] One page
[18:47:03] [PASSED] More than one page
[18:47:03] [PASSED] Above the allocation limit
[18:47:03] [PASSED] One page, with coherent DMA mappings enabled
[18:47:03] [PASSED] Above the allocation limit, with coherent DMA mappings enabled
[18:47:03] ========== [PASSED] ttm_pool_alloc_basic_dma_addr ==========
[18:47:03] [PASSED] ttm_pool_alloc_order_caching_match
[18:47:03] [PASSED] ttm_pool_alloc_caching_mismatch
[18:47:03] [PASSED] ttm_pool_alloc_order_mismatch
[18:47:03] [PASSED] ttm_pool_free_dma_alloc
[18:47:03] [PASSED] ttm_pool_free_no_dma_alloc
[18:47:03] [PASSED] ttm_pool_fini_basic
[18:47:03] ==================== [PASSED] ttm_pool =====================
[18:47:03] ================ ttm_resource (8 subtests) =================
[18:47:03] ================= ttm_resource_init_basic  =================
[18:47:03] [PASSED] Init resource in TTM_PL_SYSTEM
[18:47:03] [PASSED] Init resource in TTM_PL_VRAM
[18:47:03] [PASSED] Init resource in a private placement
[18:47:03] [PASSED] Init resource in TTM_PL_SYSTEM, set placement flags
[18:47:03] ============= [PASSED] ttm_resource_init_basic =============
[18:47:03] [PASSED] ttm_resource_init_pinned
[18:47:03] [PASSED] ttm_resource_fini_basic
[18:47:03] [PASSED] ttm_resource_manager_init_basic
[18:47:03] [PASSED] ttm_resource_manager_usage_basic
[18:47:03] [PASSED] ttm_resource_manager_set_used_basic
[18:47:03] [PASSED] ttm_sys_man_alloc_basic
[18:47:03] [PASSED] ttm_sys_man_free_basic
[18:47:03] ================== [PASSED] ttm_resource ===================
[18:47:03] =================== ttm_tt (15 subtests) ===================
[18:47:03] ==================== ttm_tt_init_basic  ====================
[18:47:03] [PASSED] Page-aligned size
[18:47:03] [PASSED] Extra pages requested
[18:47:03] ================ [PASSED] ttm_tt_init_basic ================
[18:47:03] [PASSED] ttm_tt_init_misaligned
[18:47:03] [PASSED] ttm_tt_fini_basic
[18:47:03] [PASSED] ttm_tt_fini_sg
[18:47:03] [PASSED] ttm_tt_fini_shmem
[18:47:03] [PASSED] ttm_tt_create_basic
[18:47:03] [PASSED] ttm_tt_create_invalid_bo_type
[18:47:03] [PASSED] ttm_tt_create_ttm_exists
[18:47:03] [PASSED] ttm_tt_create_failed
[18:47:03] [PASSED] ttm_tt_destroy_basic
[18:47:03] [PASSED] ttm_tt_populate_null_ttm
[18:47:03] [PASSED] ttm_tt_populate_populated_ttm
[18:47:03] [PASSED] ttm_tt_unpopulate_basic
[18:47:03] [PASSED] ttm_tt_unpopulate_empty_ttm
[18:47:03] [PASSED] ttm_tt_swapin_basic
[18:47:03] ===================== [PASSED] ttm_tt ======================
[18:47:03] =================== ttm_bo (14 subtests) ===================
[18:47:03] =========== ttm_bo_reserve_optimistic_no_ticket  ===========
[18:47:03] [PASSED] Cannot be interrupted and sleeps
[18:47:03] [PASSED] Cannot be interrupted, locks straight away
[18:47:03] [PASSED] Can be interrupted, sleeps
[18:47:03] ======= [PASSED] ttm_bo_reserve_optimistic_no_ticket =======
[18:47:03] [PASSED] ttm_bo_reserve_locked_no_sleep
[18:47:03] [PASSED] ttm_bo_reserve_no_wait_ticket
[18:47:03] [PASSED] ttm_bo_reserve_double_resv
[18:47:03] [PASSED] ttm_bo_reserve_interrupted
[18:47:03] [PASSED] ttm_bo_reserve_deadlock
[18:47:03] [PASSED] ttm_bo_unreserve_basic
[18:47:03] [PASSED] ttm_bo_unreserve_pinned
[18:47:03] [PASSED] ttm_bo_unreserve_bulk
[18:47:03] [PASSED] ttm_bo_fini_basic
[18:47:03] [PASSED] ttm_bo_fini_shared_resv
[18:47:03] [PASSED] ttm_bo_pin_basic
[18:47:03] [PASSED] ttm_bo_pin_unpin_resource
[18:47:03] [PASSED] ttm_bo_multiple_pin_one_unpin
[18:47:03] ===================== [PASSED] ttm_bo ======================
[18:47:03] ============== ttm_bo_validate (21 subtests) ===============
[18:47:03] ============== ttm_bo_init_reserved_sys_man  ===============
[18:47:03] [PASSED] Buffer object for userspace
[18:47:03] [PASSED] Kernel buffer object
[18:47:03] [PASSED] Shared buffer object
[18:47:03] ========== [PASSED] ttm_bo_init_reserved_sys_man ===========
[18:47:03] ============== ttm_bo_init_reserved_mock_man  ==============
[18:47:03] [PASSED] Buffer object for userspace
[18:47:03] [PASSED] Kernel buffer object
[18:47:03] [PASSED] Shared buffer object
[18:47:03] ========== [PASSED] ttm_bo_init_reserved_mock_man ==========
[18:47:03] [PASSED] ttm_bo_init_reserved_resv
[18:47:03] ================== ttm_bo_validate_basic  ==================
[18:47:03] [PASSED] Buffer object for userspace
[18:47:03] [PASSED] Kernel buffer object
[18:47:03] [PASSED] Shared buffer object
[18:47:03] ============== [PASSED] ttm_bo_validate_basic ==============
[18:47:03] [PASSED] ttm_bo_validate_invalid_placement
[18:47:03] ============= ttm_bo_validate_same_placement  ==============
[18:47:03] [PASSED] System manager
[18:47:03] [PASSED] VRAM manager
[18:47:03] ========= [PASSED] ttm_bo_validate_same_placement ==========
[18:47:03] [PASSED] ttm_bo_validate_failed_alloc
[18:47:03] [PASSED] ttm_bo_validate_pinned
[18:47:03] [PASSED] ttm_bo_validate_busy_placement
[18:47:03] ================ ttm_bo_validate_multihop  =================
[18:47:03] [PASSED] Buffer object for userspace
[18:47:03] [PASSED] Kernel buffer object
[18:47:03] [PASSED] Shared buffer object
[18:47:03] ============ [PASSED] ttm_bo_validate_multihop =============
[18:47:03] ========== ttm_bo_validate_no_placement_signaled  ==========
[18:47:03] [PASSED] Buffer object in system domain, no page vector
[18:47:03] [PASSED] Buffer object in system domain with an existing page vector
[18:47:03] ====== [PASSED] ttm_bo_validate_no_placement_signaled ======
[18:47:03] ======== ttm_bo_validate_no_placement_not_signaled  ========
[18:47:03] [PASSED] Buffer object for userspace
[18:47:03] [PASSED] Kernel buffer object
[18:47:03] [PASSED] Shared buffer object
[18:47:03] ==== [PASSED] ttm_bo_validate_no_placement_not_signaled ====
[18:47:03] [PASSED] ttm_bo_validate_move_fence_signaled
[18:47:03] ========= ttm_bo_validate_move_fence_not_signaled  =========
[18:47:03] [PASSED] Waits for GPU
[18:47:03] [PASSED] Tries to lock straight away
[18:47:03] ===== [PASSED] ttm_bo_validate_move_fence_not_signaled =====
[18:47:03] [PASSED] ttm_bo_validate_happy_evict
[18:47:03] [PASSED] ttm_bo_validate_all_pinned_evict
[18:47:03] [PASSED] ttm_bo_validate_allowed_only_evict
[18:47:03] [PASSED] ttm_bo_validate_deleted_evict
[18:47:03] [PASSED] ttm_bo_validate_busy_domain_evict
[18:47:03] [PASSED] ttm_bo_validate_evict_gutting
[18:47:03] [PASSED] ttm_bo_validate_recrusive_evict
stty: 'standard input': Inappropriate ioctl for device
[18:47:03] ================= [PASSED] ttm_bo_validate =================
[18:47:03] ============================================================
[18:47:03] Testing complete. Ran 101 tests: passed: 101
[18:47:03] Elapsed time: 11.074s total, 1.722s configuring, 9.136s building, 0.177s running

+ cleanup
++ stat -c %u:%g /kernel
+ chown -R 1003:1003 /kernel

✗ CI.checksparse: warning for drm/xe/display: Test series with PREEMPT_RT and preemption disable.

[Patchwork]

== Series Details ==

Series: drm/xe/display: Test series with PREEMPT_RT and preemption disable.
URL   : https://patchwork.freedesktop.org/series/156335/
State : warning

== Summary ==

+ trap cleanup EXIT
+ KERNEL=/kernel
+ MT=/root/linux/maintainer-tools
+ git clone https://gitlab.freedesktop.org/drm/maintainer-tools /root/linux/maintainer-tools
Cloning into '/root/linux/maintainer-tools'...
warning: redirecting to https://gitlab.freedesktop.org/drm/maintainer-tools.git/
+ make -C /root/linux/maintainer-tools
make: Entering directory '/root/linux/maintainer-tools'
cc -O2 -g -Wextra -o remap-log remap-log.c
make: Leaving directory '/root/linux/maintainer-tools'
+ cd /kernel
+ git config --global --add safe.directory /kernel
+ /root/linux/maintainer-tools/dim sparse --fast 74d9293d414f6967091764ccb2d2237d319558b5
Sparse version: 0.6.4 (Ubuntu: 0.6.4-4ubuntu3)
Fast mode used, each commit won't be checked separately.
-
+drivers/gpu/drm/drm_drv.c:449:6: warning: context imbalance in 'drm_dev_enter' - different lock contexts for basic block
+drivers/gpu/drm/drm_drv.c: note: in included file (through include/linux/notifier.h, arch/x86/include/asm/uprobes.h, include/linux/uprobes.h, include/linux/mm_types.h, include/linux/mmzone.h, include/linux/gfp.h, ...):
+drivers/gpu/drm/drm_gem.c:446:9: warning: context imbalance in 'drm_gem_handle_create_tail' - unexpected unlock
+drivers/gpu/drm/drm_plane.c:213:24: warning: Using plain integer as NULL pointer
+drivers/gpu/drm/drm_syncobj.c:602:24: warning: context imbalance in 'drm_syncobj_get_handle' - unexpected unlock
+drivers/gpu/drm/drm_syncobj.c:727:24: warning: context imbalance in 'drm_syncobj_fd_to_handle' - unexpected unlock
+./include/linux/srcu.h:389:9: warning: context imbalance in 'drm_dev_exit' - unexpected unlock

+ cleanup
++ stat -c %u:%g /kernel
+ chown -R 1003:1003 /kernel

✗ Xe.CI.BAT: failure for drm/xe/display: Test series with PREEMPT_RT and preemption disable.

[Patchwork]

[-- Attachment #1: Type: text/plain, Size: 6004 bytes --]

== Series Details ==

Series: drm/xe/display: Test series with PREEMPT_RT and preemption disable.
URL   : https://patchwork.freedesktop.org/series/156335/
State : failure

== Summary ==

CI Bug Log - changes from xe-3967-d510fc9fa0a94543429523987bf7e613fe485a61_BAT -> xe-pw-156335v1_BAT
====================================================

Summary
-------

  **FAILURE**

  Serious unknown changes coming with xe-pw-156335v1_BAT absolutely need to be
  verified manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in xe-pw-156335v1_BAT, please notify your bug team (I915-ci-infra@lists.freedesktop.org) to allow them
  to document this new failure mode, which will reduce false positives in CI.

  

Participating hosts (13 -> 13)
------------------------------

  No changes in participating hosts

Possible new issues
-------------------

  Here are the unknown changes that may have been introduced in xe-pw-156335v1_BAT:

### IGT changes ###

#### Possible regressions ####

  * igt@kms_force_connector_basic@force-connector-state:
    - bat-bmg-2:          [PASS][1] -> [ABORT][2]
   [1]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3967-d510fc9fa0a94543429523987bf7e613fe485a61/bat-bmg-2/igt@kms_force_connector_basic@force-connector-state.html
   [2]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-156335v1/bat-bmg-2/igt@kms_force_connector_basic@force-connector-state.html
    - bat-ptl-1:          [PASS][3] -> [ABORT][4]
   [3]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3967-d510fc9fa0a94543429523987bf7e613fe485a61/bat-ptl-1/igt@kms_force_connector_basic@force-connector-state.html
   [4]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-156335v1/bat-ptl-1/igt@kms_force_connector_basic@force-connector-state.html

  * igt@xe_module_load@load:
    - bat-ptl-2:          [PASS][5] -> [ABORT][6]
   [5]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3967-d510fc9fa0a94543429523987bf7e613fe485a61/bat-ptl-2/igt@xe_module_load@load.html
   [6]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-156335v1/bat-ptl-2/igt@xe_module_load@load.html
    - bat-dg2-oem2:       [PASS][7] -> [ABORT][8]
   [7]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3967-d510fc9fa0a94543429523987bf7e613fe485a61/bat-dg2-oem2/igt@xe_module_load@load.html
   [8]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-156335v1/bat-dg2-oem2/igt@xe_module_load@load.html
    - bat-lnl-1:          [PASS][9] -> [ABORT][10]
   [9]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3967-d510fc9fa0a94543429523987bf7e613fe485a61/bat-lnl-1/igt@xe_module_load@load.html
   [10]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-156335v1/bat-lnl-1/igt@xe_module_load@load.html
    - bat-bmg-1:          [PASS][11] -> [ABORT][12]
   [11]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3967-d510fc9fa0a94543429523987bf7e613fe485a61/bat-bmg-1/igt@xe_module_load@load.html
   [12]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-156335v1/bat-bmg-1/igt@xe_module_load@load.html
    - bat-adlp-7:         [PASS][13] -> [ABORT][14]
   [13]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3967-d510fc9fa0a94543429523987bf7e613fe485a61/bat-adlp-7/igt@xe_module_load@load.html
   [14]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-156335v1/bat-adlp-7/igt@xe_module_load@load.html

  
Known issues
------------

  Here are the changes found in xe-pw-156335v1_BAT that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@xe_evict@evict-beng-small-cm:
    - bat-ptl-vm:         NOTRUN -> [SKIP][15] ([Intel XE#5764]) +10 other tests skip
   [15]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-156335v1/bat-ptl-vm/igt@xe_evict@evict-beng-small-cm.html

  * igt@xe_live_ktest@xe_migrate@xe_validate_ccs_kunit:
    - bat-ptl-vm:         NOTRUN -> [SKIP][16] ([Intel XE#5775])
   [16]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-156335v1/bat-ptl-vm/igt@xe_live_ktest@xe_migrate@xe_validate_ccs_kunit.html

  * igt@xe_mmap@vram:
    - bat-ptl-vm:         NOTRUN -> [SKIP][17] ([Intel XE#5776])
   [17]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-156335v1/bat-ptl-vm/igt@xe_mmap@vram.html

  * igt@xe_pat@pat-index-xehpc:
    - bat-ptl-vm:         NOTRUN -> [SKIP][18] ([Intel XE#5777])
   [18]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-156335v1/bat-ptl-vm/igt@xe_pat@pat-index-xehpc.html

  * igt@xe_pat@pat-index-xelp:
    - bat-ptl-vm:         NOTRUN -> [SKIP][19] ([Intel XE#5771])
   [19]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-156335v1/bat-ptl-vm/igt@xe_pat@pat-index-xelp.html

  * igt@xe_pat@pat-index-xelpg:
    - bat-ptl-vm:         NOTRUN -> [SKIP][20] ([Intel XE#5780])
   [20]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-156335v1/bat-ptl-vm/igt@xe_pat@pat-index-xelpg.html

  
#### Possible fixes ####

  * igt@xe_module_load@load:
    - bat-ptl-vm:         [ABORT][21] ([Intel XE#6287]) -> [PASS][22]
   [21]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3967-d510fc9fa0a94543429523987bf7e613fe485a61/bat-ptl-vm/igt@xe_module_load@load.html
   [22]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-156335v1/bat-ptl-vm/igt@xe_module_load@load.html

  
  [Intel XE#5764]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5764
  [Intel XE#5771]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5771
  [Intel XE#5775]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5775
  [Intel XE#5776]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5776
  [Intel XE#5777]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5777
  [Intel XE#5780]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5780
  [Intel XE#6287]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6287


Build changes
-------------

  * Linux: xe-3967-d510fc9fa0a94543429523987bf7e613fe485a61 -> xe-pw-156335v1

  IGT_8594: 8594
  xe-3967-d510fc9fa0a94543429523987bf7e613fe485a61: d510fc9fa0a94543429523987bf7e613fe485a61
  xe-pw-156335v1: 156335v1

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-156335v1/index.html

[-- Attachment #2: Type: text/html, Size: 6815 bytes --]

✗ Xe.CI.Full: failure for drm/xe/display: Test series with PREEMPT_RT and preemption disable.

[Patchwork]

[-- Attachment #1: Type: text/plain, Size: 30427 bytes --]

== Series Details ==

Series: drm/xe/display: Test series with PREEMPT_RT and preemption disable.
URL   : https://patchwork.freedesktop.org/series/156335/
State : failure

== Summary ==

CI Bug Log - changes from xe-3967-d510fc9fa0a94543429523987bf7e613fe485a61_FULL -> xe-pw-156335v1_FULL
====================================================

Summary
-------

  **WARNING**

  Minor unknown changes coming with xe-pw-156335v1_FULL need to be verified
  manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in xe-pw-156335v1_FULL, please notify your bug team (I915-ci-infra@lists.freedesktop.org) to allow them
  to document this new failure mode, which will reduce false positives in CI.

  

Participating hosts (4 -> 4)
------------------------------

  No changes in participating hosts

Possible new issues
-------------------

  Here are the unknown changes that may have been introduced in xe-pw-156335v1_FULL:

### IGT changes ###

#### Warnings ####

  * igt@xe_module_load@load:
    - shard-lnl:          ([PASS][1], [PASS][2], [PASS][3], [PASS][4], [PASS][5], [PASS][6], [PASS][7], [PASS][8], [PASS][9], [PASS][10], [PASS][11], [PASS][12], [PASS][13], [PASS][14], [PASS][15], [PASS][16], [SKIP][17], [PASS][18], [PASS][19], [PASS][20], [PASS][21], [PASS][22], [PASS][23], [PASS][24], [PASS][25]) ([Intel XE#378]) -> ([DMESG-WARN][26], [DMESG-WARN][27], [DMESG-WARN][28], [DMESG-WARN][29], [DMESG-WARN][30], [DMESG-WARN][31], [DMESG-WARN][32], [DMESG-WARN][33], [DMESG-WARN][34], [DMESG-WARN][35], [DMESG-WARN][36], [DMESG-WARN][37], [DMESG-WARN][38], [DMESG-WARN][39], [DMESG-WARN][40], [DMESG-WARN][41], [DMESG-WARN][42], [DMESG-WARN][43], [DMESG-WARN][44], [DMESG-WARN][45], [DMESG-WARN][46], [DMESG-WARN][47], [DMESG-WARN][48], [DMESG-WARN][49], [DMESG-WARN][50])
   [1]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3967-d510fc9fa0a94543429523987bf7e613fe485a61/shard-lnl-8/igt@xe_module_load@load.html
   [2]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3967-d510fc9fa0a94543429523987bf7e613fe485a61/shard-lnl-1/igt@xe_module_load@load.html
   [3]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3967-d510fc9fa0a94543429523987bf7e613fe485a61/shard-lnl-1/igt@xe_module_load@load.html
   [4]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3967-d510fc9fa0a94543429523987bf7e613fe485a61/shard-lnl-1/igt@xe_module_load@load.html
   [5]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3967-d510fc9fa0a94543429523987bf7e613fe485a61/shard-lnl-5/igt@xe_module_load@load.html
   [6]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3967-d510fc9fa0a94543429523987bf7e613fe485a61/shard-lnl-5/igt@xe_module_load@load.html
   [7]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3967-d510fc9fa0a94543429523987bf7e613fe485a61/shard-lnl-3/igt@xe_module_load@load.html
   [8]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3967-d510fc9fa0a94543429523987bf7e613fe485a61/shard-lnl-4/igt@xe_module_load@load.html
   [9]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3967-d510fc9fa0a94543429523987bf7e613fe485a61/shard-lnl-3/igt@xe_module_load@load.html
   [10]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3967-d510fc9fa0a94543429523987bf7e613fe485a61/shard-lnl-3/igt@xe_module_load@load.html
   [11]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3967-d510fc9fa0a94543429523987bf7e613fe485a61/shard-lnl-3/igt@xe_module_load@load.html
   [12]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3967-d510fc9fa0a94543429523987bf7e613fe485a61/shard-lnl-7/igt@xe_module_load@load.html
   [13]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3967-d510fc9fa0a94543429523987bf7e613fe485a61/shard-lnl-2/igt@xe_module_load@load.html
   [14]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3967-d510fc9fa0a94543429523987bf7e613fe485a61/shard-lnl-5/igt@xe_module_load@load.html
   [15]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3967-d510fc9fa0a94543429523987bf7e613fe485a61/shard-lnl-7/igt@xe_module_load@load.html
   [16]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3967-d510fc9fa0a94543429523987bf7e613fe485a61/shard-lnl-7/igt@xe_module_load@load.html
   [17]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3967-d510fc9fa0a94543429523987bf7e613fe485a61/shard-lnl-1/igt@xe_module_load@load.html
   [18]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3967-d510fc9fa0a94543429523987bf7e613fe485a61/shard-lnl-8/igt@xe_module_load@load.html
   [19]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3967-d510fc9fa0a94543429523987bf7e613fe485a61/shard-lnl-8/igt@xe_module_load@load.html
   [20]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3967-d510fc9fa0a94543429523987bf7e613fe485a61/shard-lnl-2/igt@xe_module_load@load.html
   [21]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3967-d510fc9fa0a94543429523987bf7e613fe485a61/shard-lnl-7/igt@xe_module_load@load.html
   [22]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3967-d510fc9fa0a94543429523987bf7e613fe485a61/shard-lnl-5/igt@xe_module_load@load.html
   [23]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3967-d510fc9fa0a94543429523987bf7e613fe485a61/shard-lnl-1/igt@xe_module_load@load.html
   [24]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3967-d510fc9fa0a94543429523987bf7e613fe485a61/shard-lnl-4/igt@xe_module_load@load.html
   [25]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3967-d510fc9fa0a94543429523987bf7e613fe485a61/shard-lnl-4/igt@xe_module_load@load.html
   [26]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-156335v1/shard-lnl-1/igt@xe_module_load@load.html
   [27]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-156335v1/shard-lnl-1/igt@xe_module_load@load.html
   [28]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-156335v1/shard-lnl-1/igt@xe_module_load@load.html
   [29]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-156335v1/shard-lnl-1/igt@xe_module_load@load.html
   [30]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-156335v1/shard-lnl-8/igt@xe_module_load@load.html
   [31]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-156335v1/shard-lnl-8/igt@xe_module_load@load.html
   [32]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-156335v1/shard-lnl-8/igt@xe_module_load@load.html
   [33]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-156335v1/shard-lnl-4/igt@xe_module_load@load.html
   [34]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-156335v1/shard-lnl-4/igt@xe_module_load@load.html
   [35]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-156335v1/shard-lnl-4/igt@xe_module_load@load.html
   [36]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-156335v1/shard-lnl-3/igt@xe_module_load@load.html
   [37]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-156335v1/shard-lnl-3/igt@xe_module_load@load.html
   [38]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-156335v1/shard-lnl-3/igt@xe_module_load@load.html
   [39]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-156335v1/shard-lnl-3/igt@xe_module_load@load.html
   [40]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-156335v1/shard-lnl-2/igt@xe_module_load@load.html
   [41]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-156335v1/shard-lnl-2/igt@xe_module_load@load.html
   [42]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-156335v1/shard-lnl-2/igt@xe_module_load@load.html
   [43]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-156335v1/shard-lnl-2/igt@xe_module_load@load.html
   [44]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-156335v1/shard-lnl-7/igt@xe_module_load@load.html
   [45]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-156335v1/shard-lnl-7/igt@xe_module_load@load.html
   [46]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-156335v1/shard-lnl-7/igt@xe_module_load@load.html
   [47]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-156335v1/shard-lnl-5/igt@xe_module_load@load.html
   [48]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-156335v1/shard-lnl-5/igt@xe_module_load@load.html
   [49]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-156335v1/shard-lnl-5/igt@xe_module_load@load.html
   [50]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-156335v1/shard-lnl-5/igt@xe_module_load@load.html
    - shard-bmg:          ([PASS][51], [PASS][52], [PASS][53], [PASS][54], [PASS][55], [PASS][56], [PASS][57], [PASS][58], [PASS][59], [PASS][60], [PASS][61], [PASS][62], [PASS][63], [PASS][64], [PASS][65], [PASS][66], [PASS][67], [SKIP][68], [PASS][69], [PASS][70], [PASS][71], [PASS][72], [PASS][73], [PASS][74], [PASS][75], [PASS][76]) ([Intel XE#2457]) -> ([DMESG-WARN][77], [DMESG-WARN][78], [DMESG-WARN][79], [DMESG-WARN][80], [DMESG-WARN][81], [DMESG-WARN][82], [DMESG-WARN][83], [DMESG-WARN][84], [DMESG-WARN][85], [DMESG-WARN][86], [DMESG-WARN][87], [DMESG-WARN][88], [DMESG-WARN][89], [DMESG-WARN][90], [DMESG-WARN][91], [DMESG-WARN][92], [DMESG-WARN][93], [DMESG-WARN][94], [DMESG-WARN][95], [DMESG-WARN][96], [DMESG-WARN][97], [DMESG-WARN][98], [DMESG-WARN][99], [DMESG-WARN][100], [DMESG-WARN][101])
   [51]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3967-d510fc9fa0a94543429523987bf7e613fe485a61/shard-bmg-5/igt@xe_module_load@load.html
   [52]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3967-d510fc9fa0a94543429523987bf7e613fe485a61/shard-bmg-7/igt@xe_module_load@load.html
   [53]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3967-d510fc9fa0a94543429523987bf7e613fe485a61/shard-bmg-1/igt@xe_module_load@load.html
   [54]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3967-d510fc9fa0a94543429523987bf7e613fe485a61/shard-bmg-1/igt@xe_module_load@load.html
   [55]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3967-d510fc9fa0a94543429523987bf7e613fe485a61/shard-bmg-1/igt@xe_module_load@load.html
   [56]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3967-d510fc9fa0a94543429523987bf7e613fe485a61/shard-bmg-3/igt@xe_module_load@load.html
   [57]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3967-d510fc9fa0a94543429523987bf7e613fe485a61/shard-bmg-3/igt@xe_module_load@load.html
   [58]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3967-d510fc9fa0a94543429523987bf7e613fe485a61/shard-bmg-3/igt@xe_module_load@load.html
   [59]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3967-d510fc9fa0a94543429523987bf7e613fe485a61/shard-bmg-4/igt@xe_module_load@load.html
   [60]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3967-d510fc9fa0a94543429523987bf7e613fe485a61/shard-bmg-7/igt@xe_module_load@load.html
   [61]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3967-d510fc9fa0a94543429523987bf7e613fe485a61/shard-bmg-7/igt@xe_module_load@load.html
   [62]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3967-d510fc9fa0a94543429523987bf7e613fe485a61/shard-bmg-8/igt@xe_module_load@load.html
   [63]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3967-d510fc9fa0a94543429523987bf7e613fe485a61/shard-bmg-8/igt@xe_module_load@load.html
   [64]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3967-d510fc9fa0a94543429523987bf7e613fe485a61/shard-bmg-8/igt@xe_module_load@load.html
   [65]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3967-d510fc9fa0a94543429523987bf7e613fe485a61/shard-bmg-4/igt@xe_module_load@load.html
   [66]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3967-d510fc9fa0a94543429523987bf7e613fe485a61/shard-bmg-2/igt@xe_module_load@load.html
   [67]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3967-d510fc9fa0a94543429523987bf7e613fe485a61/shard-bmg-2/igt@xe_module_load@load.html
   [68]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3967-d510fc9fa0a94543429523987bf7e613fe485a61/shard-bmg-1/igt@xe_module_load@load.html
   [69]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3967-d510fc9fa0a94543429523987bf7e613fe485a61/shard-bmg-6/igt@xe_module_load@load.html
   [70]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3967-d510fc9fa0a94543429523987bf7e613fe485a61/shard-bmg-6/igt@xe_module_load@load.html
   [71]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3967-d510fc9fa0a94543429523987bf7e613fe485a61/shard-bmg-5/igt@xe_module_load@load.html
   [72]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3967-d510fc9fa0a94543429523987bf7e613fe485a61/shard-bmg-4/igt@xe_module_load@load.html
   [73]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3967-d510fc9fa0a94543429523987bf7e613fe485a61/shard-bmg-5/igt@xe_module_load@load.html
   [74]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3967-d510fc9fa0a94543429523987bf7e613fe485a61/shard-bmg-2/igt@xe_module_load@load.html
   [75]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3967-d510fc9fa0a94543429523987bf7e613fe485a61/shard-bmg-6/igt@xe_module_load@load.html
   [76]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3967-d510fc9fa0a94543429523987bf7e613fe485a61/shard-bmg-6/igt@xe_module_load@load.html
   [77]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-156335v1/shard-bmg-4/igt@xe_module_load@load.html
   [78]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-156335v1/shard-bmg-4/igt@xe_module_load@load.html
   [79]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-156335v1/shard-bmg-4/igt@xe_module_load@load.html
   [80]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-156335v1/shard-bmg-4/igt@xe_module_load@load.html
   [81]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-156335v1/shard-bmg-8/igt@xe_module_load@load.html
   [82]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-156335v1/shard-bmg-8/igt@xe_module_load@load.html
   [83]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-156335v1/shard-bmg-1/igt@xe_module_load@load.html
   [84]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-156335v1/shard-bmg-1/igt@xe_module_load@load.html
   [85]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-156335v1/shard-bmg-1/igt@xe_module_load@load.html
   [86]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-156335v1/shard-bmg-1/igt@xe_module_load@load.html
   [87]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-156335v1/shard-bmg-7/igt@xe_module_load@load.html
   [88]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-156335v1/shard-bmg-7/igt@xe_module_load@load.html
   [89]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-156335v1/shard-bmg-7/igt@xe_module_load@load.html
   [90]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-156335v1/shard-bmg-2/igt@xe_module_load@load.html
   [91]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-156335v1/shard-bmg-2/igt@xe_module_load@load.html
   [92]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-156335v1/shard-bmg-2/igt@xe_module_load@load.html
   [93]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-156335v1/shard-bmg-6/igt@xe_module_load@load.html
   [94]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-156335v1/shard-bmg-6/igt@xe_module_load@load.html
   [95]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-156335v1/shard-bmg-6/igt@xe_module_load@load.html
   [96]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-156335v1/shard-bmg-3/igt@xe_module_load@load.html
   [97]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-156335v1/shard-bmg-3/igt@xe_module_load@load.html
   [98]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-156335v1/shard-bmg-3/igt@xe_module_load@load.html
   [99]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-156335v1/shard-bmg-5/igt@xe_module_load@load.html
   [100]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-156335v1/shard-bmg-5/igt@xe_module_load@load.html
   [101]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-156335v1/shard-bmg-5/igt@xe_module_load@load.html
    - shard-adlp:         ([PASS][102], [PASS][103], [SKIP][104], [PASS][105], [PASS][106], [PASS][107], [PASS][108], [PASS][109], [PASS][110], [PASS][111], [PASS][112], [PASS][113], [PASS][114], [PASS][115], [PASS][116], [PASS][117], [PASS][118], [PASS][119], [PASS][120], [PASS][121], [PASS][122], [PASS][123], [PASS][124], [PASS][125], [PASS][126], [PASS][127]) ([Intel XE#378] / [Intel XE#5612]) -> ([DMESG-WARN][128], [DMESG-WARN][129], [DMESG-WARN][130], [DMESG-WARN][131], [DMESG-WARN][132], [DMESG-WARN][133], [DMESG-WARN][134], [DMESG-WARN][135], [DMESG-WARN][136], [DMESG-WARN][137], [DMESG-WARN][138], [DMESG-WARN][139], [DMESG-WARN][140], [DMESG-WARN][141], [DMESG-WARN][142], [DMESG-WARN][143], [DMESG-WARN][144], [DMESG-WARN][145], [DMESG-WARN][146], [DMESG-WARN][147], [DMESG-WARN][148], [DMESG-WARN][149], [DMESG-WARN][150], [DMESG-WARN][151], [DMESG-WARN][152])
   [102]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3967-d510fc9fa0a94543429523987bf7e613fe485a61/shard-adlp-6/igt@xe_module_load@load.html
   [103]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3967-d510fc9fa0a94543429523987bf7e613fe485a61/shard-adlp-8/igt@xe_module_load@load.html
   [104]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3967-d510fc9fa0a94543429523987bf7e613fe485a61/shard-adlp-6/igt@xe_module_load@load.html
   [105]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3967-d510fc9fa0a94543429523987bf7e613fe485a61/shard-adlp-2/igt@xe_module_load@load.html
   [106]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3967-d510fc9fa0a94543429523987bf7e613fe485a61/shard-adlp-2/igt@xe_module_load@load.html
   [107]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3967-d510fc9fa0a94543429523987bf7e613fe485a61/shard-adlp-4/igt@xe_module_load@load.html
   [108]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3967-d510fc9fa0a94543429523987bf7e613fe485a61/shard-adlp-4/igt@xe_module_load@load.html
   [109]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3967-d510fc9fa0a94543429523987bf7e613fe485a61/shard-adlp-4/igt@xe_module_load@load.html
   [110]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3967-d510fc9fa0a94543429523987bf7e613fe485a61/shard-adlp-4/igt@xe_module_load@load.html
   [111]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3967-d510fc9fa0a94543429523987bf7e613fe485a61/shard-adlp-9/igt@xe_module_load@load.html
   [112]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3967-d510fc9fa0a94543429523987bf7e613fe485a61/shard-adlp-6/igt@xe_module_load@load.html
   [113]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3967-d510fc9fa0a94543429523987bf7e613fe485a61/shard-adlp-6/igt@xe_module_load@load.html
   [114]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3967-d510fc9fa0a94543429523987bf7e613fe485a61/shard-adlp-6/igt@xe_module_load@load.html
   [115]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3967-d510fc9fa0a94543429523987bf7e613fe485a61/shard-adlp-1/igt@xe_module_load@load.html
   [116]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3967-d510fc9fa0a94543429523987bf7e613fe485a61/shard-adlp-1/igt@xe_module_load@load.html
   [117]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3967-d510fc9fa0a94543429523987bf7e613fe485a61/shard-adlp-2/igt@xe_module_load@load.html
   [118]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3967-d510fc9fa0a94543429523987bf7e613fe485a61/shard-adlp-3/igt@xe_module_load@load.html
   [119]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3967-d510fc9fa0a94543429523987bf7e613fe485a61/shard-adlp-3/igt@xe_module_load@load.html
   [120]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3967-d510fc9fa0a94543429523987bf7e613fe485a61/shard-adlp-3/igt@xe_module_load@load.html
   [121]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3967-d510fc9fa0a94543429523987bf7e613fe485a61/shard-adlp-1/igt@xe_module_load@load.html
   [122]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3967-d510fc9fa0a94543429523987bf7e613fe485a61/shard-adlp-8/igt@xe_module_load@load.html
   [123]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3967-d510fc9fa0a94543429523987bf7e613fe485a61/shard-adlp-9/igt@xe_module_load@load.html
   [124]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3967-d510fc9fa0a94543429523987bf7e613fe485a61/shard-adlp-9/igt@xe_module_load@load.html
   [125]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3967-d510fc9fa0a94543429523987bf7e613fe485a61/shard-adlp-9/igt@xe_module_load@load.html
   [126]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3967-d510fc9fa0a94543429523987bf7e613fe485a61/shard-adlp-8/igt@xe_module_load@load.html
   [127]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3967-d510fc9fa0a94543429523987bf7e613fe485a61/shard-adlp-8/igt@xe_module_load@load.html
   [128]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-156335v1/shard-adlp-6/igt@xe_module_load@load.html
   [129]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-156335v1/shard-adlp-6/igt@xe_module_load@load.html
   [130]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-156335v1/shard-adlp-6/igt@xe_module_load@load.html
   [131]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-156335v1/shard-adlp-6/igt@xe_module_load@load.html
   [132]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-156335v1/shard-adlp-9/igt@xe_module_load@load.html
   [133]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-156335v1/shard-adlp-9/igt@xe_module_load@load.html
   [134]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-156335v1/shard-adlp-9/igt@xe_module_load@load.html
   [135]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-156335v1/shard-adlp-8/igt@xe_module_load@load.html
   [136]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-156335v1/shard-adlp-8/igt@xe_module_load@load.html
   [137]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-156335v1/shard-adlp-8/igt@xe_module_load@load.html
   [138]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-156335v1/shard-adlp-8/igt@xe_module_load@load.html
   [139]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-156335v1/shard-adlp-2/igt@xe_module_load@load.html
   [140]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-156335v1/shard-adlp-2/igt@xe_module_load@load.html
   [141]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-156335v1/shard-adlp-2/igt@xe_module_load@load.html
   [142]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-156335v1/shard-adlp-3/igt@xe_module_load@load.html
   [143]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-156335v1/shard-adlp-3/igt@xe_module_load@load.html
   [144]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-156335v1/shard-adlp-3/igt@xe_module_load@load.html
   [145]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-156335v1/shard-adlp-4/igt@xe_module_load@load.html
   [146]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-156335v1/shard-adlp-4/igt@xe_module_load@load.html
   [147]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-156335v1/shard-adlp-4/igt@xe_module_load@load.html
   [148]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-156335v1/shard-adlp-1/igt@xe_module_load@load.html
   [149]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-156335v1/shard-adlp-1/igt@xe_module_load@load.html
   [150]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-156335v1/shard-adlp-1/igt@xe_module_load@load.html
   [151]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-156335v1/shard-adlp-1/igt@xe_module_load@load.html
   [152]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-156335v1/shard-adlp-1/igt@xe_module_load@load.html
    - shard-dg2-set2:     ([PASS][153], [PASS][154], [PASS][155], [PASS][156], [PASS][157], [PASS][158], [PASS][159], [PASS][160], [PASS][161], [PASS][162], [PASS][163], [PASS][164], [PASS][165], [PASS][166], [PASS][167], [PASS][168], [PASS][169], [PASS][170], [PASS][171], [PASS][172], [PASS][173], [PASS][174], [PASS][175], [PASS][176], [SKIP][177], [PASS][178]) ([Intel XE#378]) -> ([DMESG-WARN][179], [DMESG-WARN][180], [DMESG-WARN][181], [DMESG-WARN][182], [DMESG-WARN][183], [DMESG-WARN][184], [DMESG-WARN][185], [DMESG-WARN][186], [DMESG-WARN][187], [DMESG-WARN][188], [DMESG-WARN][189], [DMESG-WARN][190], [DMESG-WARN][191], [DMESG-WARN][192], [DMESG-WARN][193], [DMESG-WARN][194], [DMESG-WARN][195], [DMESG-WARN][196], [DMESG-WARN][197], [DMESG-WARN][198], [DMESG-WARN][199], [DMESG-WARN][200], [DMESG-WARN][201], [DMESG-WARN][202], [DMESG-WARN][203])
   [153]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3967-d510fc9fa0a94543429523987bf7e613fe485a61/shard-dg2-463/igt@xe_module_load@load.html
   [154]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3967-d510fc9fa0a94543429523987bf7e613fe485a61/shard-dg2-434/igt@xe_module_load@load.html
   [155]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3967-d510fc9fa0a94543429523987bf7e613fe485a61/shard-dg2-434/igt@xe_module_load@load.html
   [156]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3967-d510fc9fa0a94543429523987bf7e613fe485a61/shard-dg2-466/igt@xe_module_load@load.html
   [157]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3967-d510fc9fa0a94543429523987bf7e613fe485a61/shard-dg2-433/igt@xe_module_load@load.html
   [158]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3967-d510fc9fa0a94543429523987bf7e613fe485a61/shard-dg2-433/igt@xe_module_load@load.html
   [159]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3967-d510fc9fa0a94543429523987bf7e613fe485a61/shard-dg2-464/igt@xe_module_load@load.html
   [160]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3967-d510fc9fa0a94543429523987bf7e613fe485a61/shard-dg2-463/igt@xe_module_load@load.html
   [161]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3967-d510fc9fa0a94543429523987bf7e613fe485a61/shard-dg2-433/igt@xe_module_load@load.html
   [162]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3967-d510fc9fa0a94543429523987bf7e613fe485a61/shard-dg2-436/igt@xe_module_load@load.html
   [163]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3967-d510fc9fa0a94543429523987bf7e613fe485a61/shard-dg2-436/igt@xe_module_load@load.html
   [164]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3967-d510fc9fa0a94543429523987bf7e613fe485a61/shard-dg2-466/igt@xe_module_load@load.html
   [165]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3967-d510fc9fa0a94543429523987bf7e613fe485a61/shard-dg2-435/igt@xe_module_load@load.html
   [166]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3967-d510fc9fa0a94543429523987bf7e613fe485a61/shard-dg2-432/igt@xe_module_load@load.html
   [167]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3967-d510fc9fa0a94543429523987bf7e613fe485a61/shard-dg2-432/igt@xe_module_load@load.html
   [168]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3967-d510fc9fa0a94543429523987bf7e613fe485a61/shard-dg2-432/igt@xe_module_load@load.html
   [169]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3967-d510fc9fa0a94543429523987bf7e613fe485a61/shard-dg2-463/igt@xe_module_load@load.html
   [170]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3967-d510fc9fa0a94543429523987bf7e613fe485a61/shard-dg2-436/igt@xe_module_load@load.html
   [171]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3967-d510fc9fa0a94543429523987bf7e613fe485a61/shard-dg2-464/igt@xe_module_load@load.html
   [172]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3967-d510fc9fa0a94543429523987bf7e613fe485a61/shard-dg2-464/igt@xe_module_load@load.html
   [173]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3967-d510fc9fa0a94543429523987bf7e613fe485a61/shard-dg2-463/igt@xe_module_load@load.html
   [174]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3967-d510fc9fa0a94543429523987bf7e613fe485a61/shard-dg2-433/igt@xe_module_load@load.html
   [175]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3967-d510fc9fa0a94543429523987bf7e613fe485a61/shard-dg2-435/igt@xe_module_load@load.html
   [176]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3967-d510fc9fa0a94543429523987bf7e613fe485a61/shard-dg2-435/igt@xe_module_load@load.html
   [177]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3967-d510fc9fa0a94543429523987bf7e613fe485a61/shard-dg2-435/igt@xe_module_load@load.html
   [178]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3967-d510fc9fa0a94543429523987bf7e613fe485a61/shard-dg2-466/igt@xe_module_load@load.html
   [179]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-156335v1/shard-dg2-434/igt@xe_module_load@load.html
   [180]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-156335v1/shard-dg2-434/igt@xe_module_load@load.html
   [181]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-156335v1/shard-dg2-434/igt@xe_module_load@load.html
   [182]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-156335v1/shard-dg2-464/igt@xe_module_load@load.html
   [183]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-156335v1/shard-dg2-464/igt@xe_module_load@load.html
   [184]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-156335v1/shard-dg2-464/igt@xe_module_load@load.html
   [185]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-156335v1/shard-dg2-433/igt@xe_module_load@load.html
   [186]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-156335v1/shard-dg2-433/igt@xe_module_load@load.html
   [187]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-156335v1/shard-dg2-433/igt@xe_module_load@load.html
   [188]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-156335v1/shard-dg2-433/igt@xe_module_load@load.html
   [189]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-156335v1/shard-dg2-436/igt@xe_module_load@load.html
   [190]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-156335v1/shard-dg2-436/igt@xe_module_load@load.html
   [191]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-156335v1/shard-dg2-436/igt@xe_module_load@load.html
   [192]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-156335v1/shard-dg2-463/igt@xe_module_load@load.html
   [193]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-156335v1/shard-dg2-463/igt@xe_module_load@load.html
   [194]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-156335v1/shard-dg2-463/igt@xe_module_load@load.html
   [195]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-156335v1/shard-dg2-466/igt@xe_module_load@load.html
   [196]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-156335v1/shard-dg2-466/igt@xe_module_load@load.html
   [197]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-156335v1/shard-dg2-466/igt@xe_module_load@load.html
   [198]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-156335v1/shard-dg2-435/igt@xe_module_load@load.html
   [199]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-156335v1/shard-dg2-435/igt@xe_module_load@load.html
   [200]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-156335v1/shard-dg2-435/igt@xe_module_load@load.html
   [201]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-156335v1/shard-dg2-432/igt@xe_module_load@load.html
   [202]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-156335v1/shard-dg2-432/igt@xe_module_load@load.html
   [203]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-156335v1/shard-dg2-432/igt@xe_module_load@load.html

  
  [Intel XE#2457]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2457
  [Intel XE#378]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/378
  [Intel XE#5612]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5612


Build changes
-------------

  * Linux: xe-3967-d510fc9fa0a94543429523987bf7e613fe485a61 -> xe-pw-156335v1

  IGT_8594: 8594
  xe-3967-d510fc9fa0a94543429523987bf7e613fe485a61: d510fc9fa0a94543429523987bf7e613fe485a61
  xe-pw-156335v1: 156335v1

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-156335v1/index.html

[-- Attachment #2: Type: text/html, Size: 30808 bytes --]

[FOR CI 0/5] Testing PREEMPT_RT with disabling interrupts in the most critical section.

[Maarten Lankhorst]

Only disable preemption in this series.

Maarten Lankhorst (3):
  drm/xe: Bump xe_device_l2_flush even higher
  drm/xe/display: Disable preemption in the most critical section
  PREEMPT_RT injection

Mike Galbraith (2):
  drm/i915: Use preempt_disable/enable_rt() where recommended
  drm/i915: Don't disable interrupts on PREEMPT_RT during atomic updates

 drivers/gpu/drm/i915/Kconfig.debug          | 15 ----
 drivers/gpu/drm/i915/display/intel_crtc.c   | 23 +++++-
 drivers/gpu/drm/i915/display/intel_cursor.c | 27 ++++++-
 drivers/gpu/drm/i915/display/intel_vblank.c | 81 ++++++++++++++-------
 drivers/gpu/drm/xe/Kconfig.debug            |  5 ++
 drivers/gpu/drm/xe/xe_device.c              |  4 +-
 kernel/Kconfig.preempt                      |  4 +-
 7 files changed, 108 insertions(+), 51 deletions(-)

-- 
2.51.0

[FOR CI 4/5] drm/xe/display: Disable preemption in the most critical section

[Maarten Lankhorst]

Lets see what happens if we only disable preemption in the critical
section to ensure we do run as fast as possible without disabling
too much.

Second attempt: Disable preemption, but keep interrupts enabled.

Signed-off-by: Maarten Lankhorst <dev@lankhorst.se>
---
 drivers/gpu/drm/i915/display/intel_crtc.c   | 14 ++++++++
 drivers/gpu/drm/i915/display/intel_cursor.c | 18 +++++++++-
 drivers/gpu/drm/i915/display/intel_vblank.c | 40 ++++++++++++---------
 3 files changed, 54 insertions(+), 18 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_crtc.c b/drivers/gpu/drm/i915/display/intel_crtc.c
index f34745b5ea497..939ef48859f16 100644
--- a/drivers/gpu/drm/i915/display/intel_crtc.c
+++ b/drivers/gpu/drm/i915/display/intel_crtc.c
@@ -569,6 +569,10 @@ void intel_pipe_update_start(struct intel_atomic_state *state,
 
 	if (!IS_ENABLED(CONFIG_PREEMPT_RT))
 		local_irq_disable();
+#ifndef I915
+	else
+		preempt_disable();
+#endif
 
 	crtc->debug.min_vbl = evade.min;
 	crtc->debug.max_vbl = evade.max;
@@ -588,6 +592,11 @@ void intel_pipe_update_start(struct intel_atomic_state *state,
 irq_disable:
 	if (!IS_ENABLED(CONFIG_PREEMPT_RT))
 		local_irq_disable();
+#ifndef I915
+	else
+		preempt_disable();
+#endif
+
 }
 
 #if IS_ENABLED(CONFIG_DRM_I915_DEBUG_VBLANK_EVADE)
@@ -686,6 +695,10 @@ void intel_pipe_update_end(struct intel_atomic_state *state,
 	    intel_crtc_has_type(new_crtc_state, INTEL_OUTPUT_DSI))
 		icl_dsi_frame_update(new_crtc_state);
 
+#if !defined(I915) && IS_ENABLED(CONFIG_PREEMPT_RT)
+	preempt_enable();
+#endif
+
 	/* We're still in the vblank-evade critical section, this can't race.
 	 * Would be slightly nice to just grab the vblank count and arm the
 	 * event outside of the critical section - the spinlock might spin for a
@@ -733,6 +746,7 @@ void intel_pipe_update_end(struct intel_atomic_state *state,
 	if (!state->base.legacy_cursor_update)
 		intel_vrr_send_push(NULL, new_crtc_state);
 
+	/* Re-enable irqs here for !RT */
 	if (!IS_ENABLED(CONFIG_PREEMPT_RT))
 		local_irq_enable();
 
diff --git a/drivers/gpu/drm/i915/display/intel_cursor.c b/drivers/gpu/drm/i915/display/intel_cursor.c
index 780fcae77a984..50ca39eb09145 100644
--- a/drivers/gpu/drm/i915/display/intel_cursor.c
+++ b/drivers/gpu/drm/i915/display/intel_cursor.c
@@ -912,6 +912,7 @@ intel_legacy_cursor_update(struct drm_plane *_plane,
 
 	intel_psr_lock(crtc_state);
 
+	bool vblanked = false;
 	if (!drm_WARN_ON(display->drm, drm_crtc_vblank_get(&crtc->base))) {
 		/*
 		 * TODO: maybe check if we're still in PSR
@@ -921,13 +922,21 @@ intel_legacy_cursor_update(struct drm_plane *_plane,
 
 		if (!IS_ENABLED(CONFIG_PREEMPT_RT))
 			local_irq_disable();
+#ifndef I915
+		else
+			preempt_disable();
+#endif
 
 		intel_vblank_evade(&evade);
 
-		drm_crtc_vblank_put(&crtc->base);
+		vblanked = true;
 	} else {
 		if (!IS_ENABLED(CONFIG_PREEMPT_RT))
 			local_irq_disable();
+#ifndef I915
+		else
+			preempt_disable();
+#endif
 	}
 
 	if (new_plane_state->uapi.visible) {
@@ -939,6 +948,10 @@ intel_legacy_cursor_update(struct drm_plane *_plane,
 
 	if (!IS_ENABLED(CONFIG_PREEMPT_RT))
 		local_irq_enable();
+#ifndef I915
+	else
+		preempt_enable();
+#endif
 
 	intel_psr_unlock(crtc_state);
 
@@ -955,6 +968,9 @@ intel_legacy_cursor_update(struct drm_plane *_plane,
 		intel_plane_unpin_fb(old_plane_state);
 	}
 
+	if (vblanked)
+		drm_crtc_vblank_put(&crtc->base);
+
 out_free:
 	if (new_crtc_state)
 		intel_crtc_destroy_state(&crtc->base, &new_crtc_state->uapi);
diff --git a/drivers/gpu/drm/i915/display/intel_vblank.c b/drivers/gpu/drm/i915/display/intel_vblank.c
index 7826f29619a14..9dc839ed762ed 100644
--- a/drivers/gpu/drm/i915/display/intel_vblank.c
+++ b/drivers/gpu/drm/i915/display/intel_vblank.c
@@ -729,6 +729,13 @@ void intel_vblank_evade_init(const struct intel_crtc_state *old_crtc_state,
 		evade->min -= vblank_delay;
 }
 
+static inline int vblank_evadable(struct intel_vblank_evade_ctx *evade, int *scanline)
+{
+	*scanline = intel_get_crtc_scanline(evade->crtc);
+
+	return *scanline < evade->min || *scanline > evade->max;
+}
+
 /* must be called with vblank interrupt already enabled! */
 int intel_vblank_evade(struct intel_vblank_evade_ctx *evade)
 {
@@ -742,17 +749,24 @@ int intel_vblank_evade(struct intel_vblank_evade_ctx *evade)
 	if (evade->min <= 0 || evade->max <= 0)
 		return 0;
 
-	for (;;) {
-		/*
-		 * prepare_to_wait() has a memory barrier, which guarantees
-		 * other CPUs can see the task state update by the time we
-		 * read the scanline.
-		 */
+	while (!vblank_evadable(evade, &scanline)) {
+		if (!IS_ENABLED(CONFIG_PREEMPT_RT))
+			local_irq_enable();
+#ifndef I915
+		else
+			preempt_enable();
+#endif
+
 		prepare_to_wait(wq, &wait, TASK_UNINTERRUPTIBLE);
+		if (!vblank_evadable(evade, &scanline))
+			timeout = schedule_timeout(timeout);
 
-		scanline = intel_get_crtc_scanline(crtc);
-		if (scanline < evade->min || scanline > evade->max)
-			break;
+		if (!IS_ENABLED(CONFIG_PREEMPT_RT))
+			local_irq_disable();
+#ifndef I915
+		else
+			preempt_disable();
+#endif
 
 		if (!timeout) {
 			drm_dbg_kms(display->drm,
@@ -760,14 +774,6 @@ int intel_vblank_evade(struct intel_vblank_evade_ctx *evade)
 				    pipe_name(crtc->pipe));
 			break;
 		}
-
-		if (!IS_ENABLED(CONFIG_PREEMPT_RT))
-			local_irq_enable();
-
-		timeout = schedule_timeout(timeout);
-
-		if (!IS_ENABLED(CONFIG_PREEMPT_RT))
-			local_irq_disable();
 	}
 
 	finish_wait(wq, &wait);
-- 
2.51.0

[FOR CI 0/5] drm/xe/display: Test series with PREEMPT_RT and preemption disable.

[Maarten Lankhorst]

Fixing the issues with waiting from the previous version.

Maarten Lankhorst (3):
  drm/xe: Bump xe_device_l2_flush even higher
  drm/xe/display: Disable preemption in the most critical section
  PREEMPT_RT injection

Mike Galbraith (2):
  drm/i915: Use preempt_disable/enable_rt() where recommended
  drm/i915: Don't disable interrupts on PREEMPT_RT during atomic updates

 drivers/gpu/drm/i915/Kconfig.debug          | 15 ----
 drivers/gpu/drm/i915/display/intel_crtc.c   | 23 +++++-
 drivers/gpu/drm/i915/display/intel_cursor.c | 27 ++++++-
 drivers/gpu/drm/i915/display/intel_vblank.c | 88 ++++++++++++++-------
 drivers/gpu/drm/xe/Kconfig.debug            |  5 ++
 drivers/gpu/drm/xe/xe_device.c              |  4 +-
 kernel/Kconfig.preempt                      |  4 +-
 7 files changed, 112 insertions(+), 54 deletions(-)

-- 
2.51.0

[FOR CI 4/5] drm/xe/display: Disable preemption in the most critical section

[Maarten Lankhorst]

Lets see what happens if we only disable preemption in the critical
section to ensure we do run as fast as possible without disabling
too much.

Second attempt: Disable preemption, but keep interrupts enabled.

Signed-off-by: Maarten Lankhorst <dev@lankhorst.se>
---
 drivers/gpu/drm/i915/display/intel_crtc.c   | 14 ++++++
 drivers/gpu/drm/i915/display/intel_cursor.c | 18 +++++++-
 drivers/gpu/drm/i915/display/intel_vblank.c | 47 ++++++++++++---------
 3 files changed, 58 insertions(+), 21 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_crtc.c b/drivers/gpu/drm/i915/display/intel_crtc.c
index f34745b5ea497..939ef48859f16 100644
--- a/drivers/gpu/drm/i915/display/intel_crtc.c
+++ b/drivers/gpu/drm/i915/display/intel_crtc.c
@@ -569,6 +569,10 @@ void intel_pipe_update_start(struct intel_atomic_state *state,
 
 	if (!IS_ENABLED(CONFIG_PREEMPT_RT))
 		local_irq_disable();
+#ifndef I915
+	else
+		preempt_disable();
+#endif
 
 	crtc->debug.min_vbl = evade.min;
 	crtc->debug.max_vbl = evade.max;
@@ -588,6 +592,11 @@ void intel_pipe_update_start(struct intel_atomic_state *state,
 irq_disable:
 	if (!IS_ENABLED(CONFIG_PREEMPT_RT))
 		local_irq_disable();
+#ifndef I915
+	else
+		preempt_disable();
+#endif
+
 }
 
 #if IS_ENABLED(CONFIG_DRM_I915_DEBUG_VBLANK_EVADE)
@@ -686,6 +695,10 @@ void intel_pipe_update_end(struct intel_atomic_state *state,
 	    intel_crtc_has_type(new_crtc_state, INTEL_OUTPUT_DSI))
 		icl_dsi_frame_update(new_crtc_state);
 
+#if !defined(I915) && IS_ENABLED(CONFIG_PREEMPT_RT)
+	preempt_enable();
+#endif
+
 	/* We're still in the vblank-evade critical section, this can't race.
 	 * Would be slightly nice to just grab the vblank count and arm the
 	 * event outside of the critical section - the spinlock might spin for a
@@ -733,6 +746,7 @@ void intel_pipe_update_end(struct intel_atomic_state *state,
 	if (!state->base.legacy_cursor_update)
 		intel_vrr_send_push(NULL, new_crtc_state);
 
+	/* Re-enable irqs here for !RT */
 	if (!IS_ENABLED(CONFIG_PREEMPT_RT))
 		local_irq_enable();
 
diff --git a/drivers/gpu/drm/i915/display/intel_cursor.c b/drivers/gpu/drm/i915/display/intel_cursor.c
index 780fcae77a984..50ca39eb09145 100644
--- a/drivers/gpu/drm/i915/display/intel_cursor.c
+++ b/drivers/gpu/drm/i915/display/intel_cursor.c
@@ -912,6 +912,7 @@ intel_legacy_cursor_update(struct drm_plane *_plane,
 
 	intel_psr_lock(crtc_state);
 
+	bool vblanked = false;
 	if (!drm_WARN_ON(display->drm, drm_crtc_vblank_get(&crtc->base))) {
 		/*
 		 * TODO: maybe check if we're still in PSR
@@ -921,13 +922,21 @@ intel_legacy_cursor_update(struct drm_plane *_plane,
 
 		if (!IS_ENABLED(CONFIG_PREEMPT_RT))
 			local_irq_disable();
+#ifndef I915
+		else
+			preempt_disable();
+#endif
 
 		intel_vblank_evade(&evade);
 
-		drm_crtc_vblank_put(&crtc->base);
+		vblanked = true;
 	} else {
 		if (!IS_ENABLED(CONFIG_PREEMPT_RT))
 			local_irq_disable();
+#ifndef I915
+		else
+			preempt_disable();
+#endif
 	}
 
 	if (new_plane_state->uapi.visible) {
@@ -939,6 +948,10 @@ intel_legacy_cursor_update(struct drm_plane *_plane,
 
 	if (!IS_ENABLED(CONFIG_PREEMPT_RT))
 		local_irq_enable();
+#ifndef I915
+	else
+		preempt_enable();
+#endif
 
 	intel_psr_unlock(crtc_state);
 
@@ -955,6 +968,9 @@ intel_legacy_cursor_update(struct drm_plane *_plane,
 		intel_plane_unpin_fb(old_plane_state);
 	}
 
+	if (vblanked)
+		drm_crtc_vblank_put(&crtc->base);
+
 out_free:
 	if (new_crtc_state)
 		intel_crtc_destroy_state(&crtc->base, &new_crtc_state->uapi);
diff --git a/drivers/gpu/drm/i915/display/intel_vblank.c b/drivers/gpu/drm/i915/display/intel_vblank.c
index 7826f29619a14..448ae8e5b6e90 100644
--- a/drivers/gpu/drm/i915/display/intel_vblank.c
+++ b/drivers/gpu/drm/i915/display/intel_vblank.c
@@ -729,6 +729,13 @@ void intel_vblank_evade_init(const struct intel_crtc_state *old_crtc_state,
 		evade->min -= vblank_delay;
 }
 
+static inline int vblank_evadable(struct intel_vblank_evade_ctx *evade, int *scanline)
+{
+	*scanline = intel_get_crtc_scanline(evade->crtc);
+
+	return *scanline < evade->min || *scanline > evade->max;
+}
+
 /* must be called with vblank interrupt already enabled! */
 int intel_vblank_evade(struct intel_vblank_evade_ctx *evade)
 {
@@ -736,23 +743,33 @@ int intel_vblank_evade(struct intel_vblank_evade_ctx *evade)
 	struct intel_display *display = to_intel_display(crtc);
 	long timeout = msecs_to_jiffies_timeout(1);
 	wait_queue_head_t *wq = drm_crtc_vblank_waitqueue(&crtc->base);
-	DEFINE_WAIT(wait);
 	int scanline;
 
 	if (evade->min <= 0 || evade->max <= 0)
 		return 0;
 
-	for (;;) {
-		/*
-		 * prepare_to_wait() has a memory barrier, which guarantees
-		 * other CPUs can see the task state update by the time we
-		 * read the scanline.
-		 */
+	while (!vblank_evadable(evade, &scanline)) {
+		DEFINE_WAIT(wait);
+
+		if (!IS_ENABLED(CONFIG_PREEMPT_RT))
+			local_irq_enable();
+#ifndef I915
+		else
+			preempt_enable();
+#endif
+
 		prepare_to_wait(wq, &wait, TASK_UNINTERRUPTIBLE);
+		if (!vblank_evadable(evade, &scanline))
+			timeout = schedule_timeout(timeout);
 
-		scanline = intel_get_crtc_scanline(crtc);
-		if (scanline < evade->min || scanline > evade->max)
-			break;
+		finish_wait(wq, &wait);
+
+		if (!IS_ENABLED(CONFIG_PREEMPT_RT))
+			local_irq_disable();
+#ifndef I915
+		else
+			preempt_disable();
+#endif
 
 		if (!timeout) {
 			drm_dbg_kms(display->drm,
@@ -760,18 +777,8 @@ int intel_vblank_evade(struct intel_vblank_evade_ctx *evade)
 				    pipe_name(crtc->pipe));
 			break;
 		}
-
-		if (!IS_ENABLED(CONFIG_PREEMPT_RT))
-			local_irq_enable();
-
-		timeout = schedule_timeout(timeout);
-
-		if (!IS_ENABLED(CONFIG_PREEMPT_RT))
-			local_irq_disable();
 	}
 
-	finish_wait(wq, &wait);
-
 	/*
 	 * On VLV/CHV DSI the scanline counter would appear to
 	 * increment approx. 1/3 of a scanline before start of vblank.
-- 
2.51.0

[FOR CI 0/5] Testing PREEMPT_RT with disabling preemption in the most critical section.

[Maarten Lankhorst]

Fix get_vblank_counter() and try to disable preemption in the most critical part of the code.

Maarten Lankhorst (3):
  drm/i915/display: Make get_vblank_counter use intel_de_read_fw()
  drm/xe/display: Disable preemption in the most critical section
  PREEMPT_RT injection

Mike Galbraith (2):
  drm/i915: Use preempt_disable/enable_rt() where recommended
  drm/i915: Don't disable interrupts on PREEMPT_RT during atomic updates

 drivers/gpu/drm/i915/Kconfig.debug          | 15 ----
 drivers/gpu/drm/i915/display/intel_crtc.c   | 23 +++++-
 drivers/gpu/drm/i915/display/intel_cursor.c | 27 ++++++-
 drivers/gpu/drm/i915/display/intel_vblank.c | 90 ++++++++++++++-------
 drivers/gpu/drm/xe/Kconfig.debug            |  5 ++
 kernel/Kconfig.preempt                      |  4 +-
 6 files changed, 111 insertions(+), 53 deletions(-)

-- 
2.51.0

[FOR CI 4/5] drm/xe/display: Disable preemption in the most critical section

[Maarten Lankhorst]

Lets see what happens if we only disable preemption in the critical
section to ensure we do run as fast as possible without disabling
too much.

Second attempt: Disable preemption, but keep interrupts enabled.

Signed-off-by: Maarten Lankhorst <dev@lankhorst.se>
---
 drivers/gpu/drm/i915/display/intel_crtc.c   | 14 ++++++
 drivers/gpu/drm/i915/display/intel_cursor.c | 18 +++++++-
 drivers/gpu/drm/i915/display/intel_vblank.c | 47 ++++++++++++---------
 3 files changed, 58 insertions(+), 21 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_crtc.c b/drivers/gpu/drm/i915/display/intel_crtc.c
index f34745b5ea497..939ef48859f16 100644
--- a/drivers/gpu/drm/i915/display/intel_crtc.c
+++ b/drivers/gpu/drm/i915/display/intel_crtc.c
@@ -569,6 +569,10 @@ void intel_pipe_update_start(struct intel_atomic_state *state,
 
 	if (!IS_ENABLED(CONFIG_PREEMPT_RT))
 		local_irq_disable();
+#ifndef I915
+	else
+		preempt_disable();
+#endif
 
 	crtc->debug.min_vbl = evade.min;
 	crtc->debug.max_vbl = evade.max;
@@ -588,6 +592,11 @@ void intel_pipe_update_start(struct intel_atomic_state *state,
 irq_disable:
 	if (!IS_ENABLED(CONFIG_PREEMPT_RT))
 		local_irq_disable();
+#ifndef I915
+	else
+		preempt_disable();
+#endif
+
 }
 
 #if IS_ENABLED(CONFIG_DRM_I915_DEBUG_VBLANK_EVADE)
@@ -686,6 +695,10 @@ void intel_pipe_update_end(struct intel_atomic_state *state,
 	    intel_crtc_has_type(new_crtc_state, INTEL_OUTPUT_DSI))
 		icl_dsi_frame_update(new_crtc_state);
 
+#if !defined(I915) && IS_ENABLED(CONFIG_PREEMPT_RT)
+	preempt_enable();
+#endif
+
 	/* We're still in the vblank-evade critical section, this can't race.
 	 * Would be slightly nice to just grab the vblank count and arm the
 	 * event outside of the critical section - the spinlock might spin for a
@@ -733,6 +746,7 @@ void intel_pipe_update_end(struct intel_atomic_state *state,
 	if (!state->base.legacy_cursor_update)
 		intel_vrr_send_push(NULL, new_crtc_state);
 
+	/* Re-enable irqs here for !RT */
 	if (!IS_ENABLED(CONFIG_PREEMPT_RT))
 		local_irq_enable();
 
diff --git a/drivers/gpu/drm/i915/display/intel_cursor.c b/drivers/gpu/drm/i915/display/intel_cursor.c
index 780fcae77a984..50ca39eb09145 100644
--- a/drivers/gpu/drm/i915/display/intel_cursor.c
+++ b/drivers/gpu/drm/i915/display/intel_cursor.c
@@ -912,6 +912,7 @@ intel_legacy_cursor_update(struct drm_plane *_plane,
 
 	intel_psr_lock(crtc_state);
 
+	bool vblanked = false;
 	if (!drm_WARN_ON(display->drm, drm_crtc_vblank_get(&crtc->base))) {
 		/*
 		 * TODO: maybe check if we're still in PSR
@@ -921,13 +922,21 @@ intel_legacy_cursor_update(struct drm_plane *_plane,
 
 		if (!IS_ENABLED(CONFIG_PREEMPT_RT))
 			local_irq_disable();
+#ifndef I915
+		else
+			preempt_disable();
+#endif
 
 		intel_vblank_evade(&evade);
 
-		drm_crtc_vblank_put(&crtc->base);
+		vblanked = true;
 	} else {
 		if (!IS_ENABLED(CONFIG_PREEMPT_RT))
 			local_irq_disable();
+#ifndef I915
+		else
+			preempt_disable();
+#endif
 	}
 
 	if (new_plane_state->uapi.visible) {
@@ -939,6 +948,10 @@ intel_legacy_cursor_update(struct drm_plane *_plane,
 
 	if (!IS_ENABLED(CONFIG_PREEMPT_RT))
 		local_irq_enable();
+#ifndef I915
+	else
+		preempt_enable();
+#endif
 
 	intel_psr_unlock(crtc_state);
 
@@ -955,6 +968,9 @@ intel_legacy_cursor_update(struct drm_plane *_plane,
 		intel_plane_unpin_fb(old_plane_state);
 	}
 
+	if (vblanked)
+		drm_crtc_vblank_put(&crtc->base);
+
 out_free:
 	if (new_crtc_state)
 		intel_crtc_destroy_state(&crtc->base, &new_crtc_state->uapi);
diff --git a/drivers/gpu/drm/i915/display/intel_vblank.c b/drivers/gpu/drm/i915/display/intel_vblank.c
index cb060b5c04659..5fcf5c08187f7 100644
--- a/drivers/gpu/drm/i915/display/intel_vblank.c
+++ b/drivers/gpu/drm/i915/display/intel_vblank.c
@@ -729,6 +729,13 @@ void intel_vblank_evade_init(const struct intel_crtc_state *old_crtc_state,
 		evade->min -= vblank_delay;
 }
 
+static inline int vblank_evadable(struct intel_vblank_evade_ctx *evade, int *scanline)
+{
+	*scanline = intel_get_crtc_scanline(evade->crtc);
+
+	return *scanline < evade->min || *scanline > evade->max;
+}
+
 /* must be called with vblank interrupt already enabled! */
 int intel_vblank_evade(struct intel_vblank_evade_ctx *evade)
 {
@@ -736,23 +743,33 @@ int intel_vblank_evade(struct intel_vblank_evade_ctx *evade)
 	struct intel_display *display = to_intel_display(crtc);
 	long timeout = msecs_to_jiffies_timeout(1);
 	wait_queue_head_t *wq = drm_crtc_vblank_waitqueue(&crtc->base);
-	DEFINE_WAIT(wait);
 	int scanline;
 
 	if (evade->min <= 0 || evade->max <= 0)
 		return 0;
 
-	for (;;) {
-		/*
-		 * prepare_to_wait() has a memory barrier, which guarantees
-		 * other CPUs can see the task state update by the time we
-		 * read the scanline.
-		 */
+	while (!vblank_evadable(evade, &scanline)) {
+		DEFINE_WAIT(wait);
+
+		if (!IS_ENABLED(CONFIG_PREEMPT_RT))
+			local_irq_enable();
+#ifndef I915
+		else
+			preempt_enable();
+#endif
+
 		prepare_to_wait(wq, &wait, TASK_UNINTERRUPTIBLE);
+		if (!vblank_evadable(evade, &scanline))
+			timeout = schedule_timeout(timeout);
 
-		scanline = intel_get_crtc_scanline(crtc);
-		if (scanline < evade->min || scanline > evade->max)
-			break;
+		finish_wait(wq, &wait);
+
+		if (!IS_ENABLED(CONFIG_PREEMPT_RT))
+			local_irq_disable();
+#ifndef I915
+		else
+			preempt_disable();
+#endif
 
 		if (!timeout) {
 			drm_dbg_kms(display->drm,
@@ -760,18 +777,8 @@ int intel_vblank_evade(struct intel_vblank_evade_ctx *evade)
 				    pipe_name(crtc->pipe));
 			break;
 		}
-
-		if (!IS_ENABLED(CONFIG_PREEMPT_RT))
-			local_irq_enable();
-
-		timeout = schedule_timeout(timeout);
-
-		if (!IS_ENABLED(CONFIG_PREEMPT_RT))
-			local_irq_disable();
 	}
 
-	finish_wait(wq, &wait);
-
 	/*
 	 * On VLV/CHV DSI the scanline counter would appear to
 	 * increment approx. 1/3 of a scanline before start of vblank.
-- 
2.51.0