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From: Matthew Brost <matthew.brost@intel.com>
To: intel-xe@lists.freedesktop.org
Cc: stuart.summers@intel.com, lucas.demarchi@intel.com,
	matthew.d.roper@intel.com
Subject: [PATCH 06/12] drm/xe: Do not forward invalid TLB invalidation seqnos to upper layers
Date: Fri, 31 Oct 2025 18:02:19 -0700	[thread overview]
Message-ID: <20251101010225.3095457-7-matthew.brost@intel.com> (raw)
In-Reply-To: <20251101010225.3095457-1-matthew.brost@intel.com>

Context-based TLB invalidations send multiple H2G messages per seqno,
with only the final H2G containing a valid seqno — the others carry an
invalid seqno. The G2H handler drops these invalid seqnos to avoid
prematurely signaling a TLB invalidation fence.

Signed-off-by: Matthew Brost <matthew.brost@intel.com>
---
 drivers/gpu/drm/xe/xe_guc_tlb_inval.c   | 3 ++-
 drivers/gpu/drm/xe/xe_tlb_inval_types.h | 1 +
 2 files changed, 3 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/xe/xe_guc_tlb_inval.c b/drivers/gpu/drm/xe/xe_guc_tlb_inval.c
index 61bfa0d485f6..995789f0d31f 100644
--- a/drivers/gpu/drm/xe/xe_guc_tlb_inval.c
+++ b/drivers/gpu/drm/xe/xe_guc_tlb_inval.c
@@ -235,7 +235,8 @@ int xe_guc_tlb_inval_done_handler(struct xe_guc *guc, u32 *msg, u32 len)
 	if (unlikely(len != 1))
 		return -EPROTO;
 
-	xe_tlb_inval_done_handler(&gt->tlb_inval, msg[0]);
+	if (msg[0] != TLB_INVALIDATION_SEQNO_INVALID)
+		xe_tlb_inval_done_handler(&gt->tlb_inval, msg[0]);
 
 	return 0;
 }
diff --git a/drivers/gpu/drm/xe/xe_tlb_inval_types.h b/drivers/gpu/drm/xe/xe_tlb_inval_types.h
index 8f8b060e9005..7a6967ce3b76 100644
--- a/drivers/gpu/drm/xe/xe_tlb_inval_types.h
+++ b/drivers/gpu/drm/xe/xe_tlb_inval_types.h
@@ -80,6 +80,7 @@ struct xe_tlb_inval {
 	const struct xe_tlb_inval_ops *ops;
 	/** @tlb_inval.seqno: TLB invalidation seqno, protected by CT lock */
 #define TLB_INVALIDATION_SEQNO_MAX	0x100000
+#define TLB_INVALIDATION_SEQNO_INVALID	TLB_INVALIDATION_SEQNO_MAX
 	int seqno;
 	/** @tlb_invalidation.seqno_lock: protects @tlb_invalidation.seqno */
 	struct mutex seqno_lock;
-- 
2.34.1


  parent reply	other threads:[~2025-11-01  1:02 UTC|newest]

Thread overview: 17+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2025-11-01  1:02 [PATCH 00/12] Context based TLB invalidations Matthew Brost
2025-11-01  1:02 ` [PATCH 01/12] drm/xe: Add normalize_invalidation_range Matthew Brost
2025-11-01  1:02 ` [PATCH 02/12] drm/xe: Make usm.asid_to_vm allocation use GFP_NOWAIT Matthew Brost
2025-11-01  1:02 ` [PATCH 03/12] drm/xe: Add xe_device_asid_to_vm helper Matthew Brost
2025-11-01  1:02 ` [PATCH 04/12] drm/xe: Add vm to exec queues association Matthew Brost
2025-11-01  1:02 ` [PATCH 05/12] drm/xe: Taint TLB invalidation seqno lock with GFP_KERNEL Matthew Brost
2025-11-01  1:02 ` Matthew Brost [this message]
2025-11-01  1:02 ` [PATCH 07/12] drm/xe: Rename send_tlb_inval_ppgtt to send_tlb_inval_asid_ppgtt Matthew Brost
2025-11-01  1:02 ` [PATCH 08/12] drm/xe: Add send_tlb_inval_ppgtt helper Matthew Brost
2025-11-01  1:02 ` [PATCH 09/12] drm/xe: Add xe_tlb_inval_idle helper Matthew Brost
2025-11-01  1:02 ` [PATCH 10/12] drm/xe: Add exec queue active vfunc Matthew Brost
2025-11-01  1:02 ` [PATCH 11/12] drm/xe: Add context-based invalidation to GuC TLB invalidation backend Matthew Brost
2025-11-01  1:02 ` [PATCH 12/12] drm/xe: Enable context TLB invalidations for CI Matthew Brost
2025-11-01  3:43 ` ✗ CI.checkpatch: warning for Context based TLB invalidations Patchwork
2025-11-01  3:44 ` ✓ CI.KUnit: success " Patchwork
2025-11-01  4:48 ` ✓ Xe.CI.BAT: " Patchwork
2025-11-01 23:44 ` ✓ Xe.CI.Full: " Patchwork

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