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From: Matthew Brost <matthew.brost@intel.com>
To: intel-xe@lists.freedesktop.org
Cc: stuart.summers@intel.com, lucas.demarchi@intel.com,
	matthew.d.roper@intel.com
Subject: [PATCH 07/12] drm/xe: Rename send_tlb_inval_ppgtt to send_tlb_inval_asid_ppgtt
Date: Fri, 31 Oct 2025 18:02:20 -0700	[thread overview]
Message-ID: <20251101010225.3095457-8-matthew.brost@intel.com> (raw)
In-Reply-To: <20251101010225.3095457-1-matthew.brost@intel.com>

Context-based TLB invalidations have their own set of GuC TLB
invalidation operations. Rename the current PPGTT invalidation function,
which operates on ASIDs, to a more descriptive name that reflects its
purpose.

Signed-off-by: Matthew Brost <matthew.brost@intel.com>
---
 drivers/gpu/drm/xe/xe_guc_tlb_inval.c | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/xe/xe_guc_tlb_inval.c b/drivers/gpu/drm/xe/xe_guc_tlb_inval.c
index 995789f0d31f..42e9fbd062ba 100644
--- a/drivers/gpu/drm/xe/xe_guc_tlb_inval.c
+++ b/drivers/gpu/drm/xe/xe_guc_tlb_inval.c
@@ -131,8 +131,8 @@ static u64 normalize_invalidation_range(struct xe_gt *gt, u64 *start, u64 *end)
  */
 #define MAX_RANGE_TLB_INVALIDATION_LENGTH (rounddown_pow_of_two(ULONG_MAX))
 
-static int send_tlb_inval_ppgtt(struct xe_tlb_inval *tlb_inval, u32 seqno,
-				u64 start, u64 end, u32 asid)
+static int send_tlb_inval_asid_ppgtt(struct xe_tlb_inval *tlb_inval, u32 seqno,
+				     u64 start, u64 end, u32 asid)
 {
 #define MAX_TLB_INVALIDATION_LEN	7
 	struct xe_guc *guc = tlb_inval->private;
@@ -195,7 +195,7 @@ static long tlb_inval_timeout_delay(struct xe_tlb_inval *tlb_inval)
 static const struct xe_tlb_inval_ops guc_tlb_inval_ops = {
 	.all = send_tlb_inval_all,
 	.ggtt = send_tlb_inval_ggtt,
-	.ppgtt = send_tlb_inval_ppgtt,
+	.ppgtt = send_tlb_inval_asid_ppgtt,
 	.initialized = tlb_inval_initialized,
 	.flush = tlb_inval_flush,
 	.timeout_delay = tlb_inval_timeout_delay,
-- 
2.34.1


  parent reply	other threads:[~2025-11-01  1:02 UTC|newest]

Thread overview: 17+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2025-11-01  1:02 [PATCH 00/12] Context based TLB invalidations Matthew Brost
2025-11-01  1:02 ` [PATCH 01/12] drm/xe: Add normalize_invalidation_range Matthew Brost
2025-11-01  1:02 ` [PATCH 02/12] drm/xe: Make usm.asid_to_vm allocation use GFP_NOWAIT Matthew Brost
2025-11-01  1:02 ` [PATCH 03/12] drm/xe: Add xe_device_asid_to_vm helper Matthew Brost
2025-11-01  1:02 ` [PATCH 04/12] drm/xe: Add vm to exec queues association Matthew Brost
2025-11-01  1:02 ` [PATCH 05/12] drm/xe: Taint TLB invalidation seqno lock with GFP_KERNEL Matthew Brost
2025-11-01  1:02 ` [PATCH 06/12] drm/xe: Do not forward invalid TLB invalidation seqnos to upper layers Matthew Brost
2025-11-01  1:02 ` Matthew Brost [this message]
2025-11-01  1:02 ` [PATCH 08/12] drm/xe: Add send_tlb_inval_ppgtt helper Matthew Brost
2025-11-01  1:02 ` [PATCH 09/12] drm/xe: Add xe_tlb_inval_idle helper Matthew Brost
2025-11-01  1:02 ` [PATCH 10/12] drm/xe: Add exec queue active vfunc Matthew Brost
2025-11-01  1:02 ` [PATCH 11/12] drm/xe: Add context-based invalidation to GuC TLB invalidation backend Matthew Brost
2025-11-01  1:02 ` [PATCH 12/12] drm/xe: Enable context TLB invalidations for CI Matthew Brost
2025-11-01  3:43 ` ✗ CI.checkpatch: warning for Context based TLB invalidations Patchwork
2025-11-01  3:44 ` ✓ CI.KUnit: success " Patchwork
2025-11-01  4:48 ` ✓ Xe.CI.BAT: " Patchwork
2025-11-01 23:44 ` ✓ Xe.CI.Full: " Patchwork

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