[PATCH v5 0/8] drm/i915/display: Add initial support for Xe3p_LPD

[PATCH v5 0/8] drm/i915/display: Add initial support for Xe3p_LPD

[Gustavo Sousa]

This series adds initial support for Xe3p_LPD, Intel's display
architecture with IP version 35.

This series contains basic enabling patches and does not provide
complete support for the display IP yet. More involved features, like
the new PHY implementation and ALPM are implemented as separate patch
series.

Signed-off-by: Gustavo Sousa <gustavo.sousa@intel.com>
---
Changes in v5:
- Dropped patch "drm/i915/wm: Do not make latency values monotonic on
  Xe3 onward", as it needs a bit more discussion and is not critical for
  this series.
- Dropped patch "drm/i915/xe3p_lpd: Extend Type-C flow for static DDI
  allocation".  I'll send it as a standalone patch.
- Incorporated review feedback for the other patches. Please check the
  changelog in the individual patches for details.
- Link to v4: https://patch.msgid.link/20251107-xe3p_lpd-basic-enabling-v4-0-ab3367f65f15@intel.com

Changes in v4:
- Skipped patches from v3 that were already applied.
- Dropped patch "drm/i915/xe3p_lpd: Enable system caching for FBC" with
  the expectation that its next version will be sent as a standalone
  patch.
- Link to v3: https://patch.msgid.link/20251103-xe3p_lpd-basic-enabling-v3-0-00e87b510ae7@intel.com

Changes in v3:
- Reshuffled patches so that most of the ones already containing a r-b
  are placed at the start.
- Dropped "drm/i915/xe3p_lpd: Wait for AUX channel power status", as a
  similar patch was already applied from a patch series dedicated to LT
  PHY
  (https://lore.kernel.org/all/20251101032513.4171255-25-suraj.kandpal@intel.com/).
- Dropped patches related to UINT16 plane formats, as they were
  incomplete and were not specific to Xe3p_LPD.
- Dropped FBC related patches, as Vinod is handling them as a separated
  series
  (https://lore.kernel.org/intel-gfx/20251027134001.325064-1-vinod.govindapillai@intel.com/)
- Dropped "drm/i915/xe3p_lpd: PSR SU minimum lines is 4", since that
  change is not valid according to Bspec.
- Incorporated review feedback on the other patches. Please check the
  changelog in the individual patches for details.
- Link to v2: https://lore.kernel.org/r/20251021-xe3p_lpd-basic-enabling-v2-0-10eae6d655b8@intel.com

Changes in v2:
- Incorporated review feedback. Please check the changelog in the
  patches for details.
- Link to v1: https://lore.kernel.org/r/20251015-xe3p_lpd-basic-enabling-v1-0-d2d1e26520aa@intel.com

---
Gustavo Sousa (7):
      drm/i915/vbt: Add fields dedicated_external and dyn_port_over_tc
      drm/i915/power: Use intel_encoder_is_tc()
      drm/i915/display: Handle dedicated external ports in intel_encoder_is_tc()
      drm/i915/xe3p_lpd: Handle underrun debug bits
      drm/i915/display: Use platform check in HAS_LT_PHY()
      drm/i915/display: Move HAS_LT_PHY() to intel_display_device.h
      drm/i915/display: Use HAS_LT_PHY() for LT PHY AUX power

Sai Teja Pottumuttu (1):
      drm/i915/nvls: Add NVL-S display support

 drivers/gpu/drm/i915/display/intel_bios.c          |  73 +++++++++++++-
 drivers/gpu/drm/i915/display/intel_bios.h          |   2 +
 drivers/gpu/drm/i915/display/intel_ddi.c           |  11 +++
 drivers/gpu/drm/i915/display/intel_display.c       |  16 ++-
 .../gpu/drm/i915/display/intel_display_device.c    |   5 +
 .../gpu/drm/i915/display/intel_display_device.h    |   6 +-
 .../drm/i915/display/intel_display_power_well.c    |  49 +++++----
 drivers/gpu/drm/i915/display/intel_display_regs.h  |  16 +++
 drivers/gpu/drm/i915/display/intel_display_types.h |   1 +
 drivers/gpu/drm/i915/display/intel_fbc.c           |  50 ++++++++++
 drivers/gpu/drm/i915/display/intel_fbc.h           |   3 +
 drivers/gpu/drm/i915/display/intel_fbc_regs.h      |   2 +
 drivers/gpu/drm/i915/display/intel_fifo_underrun.c | 109 +++++++++++++++++++++
 drivers/gpu/drm/i915/display/intel_lt_phy.h        |   2 -
 drivers/gpu/drm/i915/display/intel_vbt_defs.h      |   3 +-
 15 files changed, 324 insertions(+), 24 deletions(-)
---
base-commit: 5f250ba2e3bb0b4541473f2bd5dd8a8f22305b61
change-id: 20251014-xe3p_lpd-basic-enabling-eb4424698b44

Best regards,
--  
Gustavo Sousa <gustavo.sousa@intel.com>

[PATCH v5 1/8] drm/i915/vbt: Add fields dedicated_external and dyn_port_over_tc

[Gustavo Sousa]

VBT version 264 adds new fields associated to Xe3p_LPD's new ways of
configuring SoC for TC ports and PHYs.  Update the code to match the
updates in VBT.

The new field dedicated_external is used to represent TC ports that are
connected to PHYs outside of the Type-C subsystem, meaning that they
behave like dedicated ports and don't require the extra Type-C
programming.  In an upcoming change, we will update the driver to take
this field into consideration when detecting the type of port.

The new field dyn_port_over_tc is used to inform that the TC port can be
dynamically allocated for a legacy connector in the Type-C subsystem,
which is a new feature in Xe3p_LPD.  In upcoming changes, we will use
that field in order to handle the IOM resource management programming
required for that.

Note that, when dedicated_external is set, the fields dp_usb_type_c and
tbt are tagged as "don't care" in the spec, so they should be ignored in
that case, so also add a sanitization function to take care of forcing
them to zero when dedicated_external is true.

v2:
  - Use sanitization function to force dp_usb_type_c and tbt fields to
    be zero instead of adding a
    intel_bios_encoder_is_dedicated_external() check in each of their
    respective accessor functions. (Jani)
  - Print info about dedicated external ports in print_ddi_port().
    (Jani)
v3:
  - Also zero out field dyn_port_over_tc when dedicated_external is set.
    (Imre)
  - Use intel_bios_encoder_is_dedicated_external() directly instead of
    storing return value into variable in print_ddi_port(). (Imre)
  - Also print info for dyn_port_over_tc in print_ddi_port(). (Imre)

Bspec: 20124, 68954, 74304
Cc: Imre Deak <imre.deak@intel.com>
Cc: Jani Nikula <jani.nikula@linux.intel.com>
Cc: Shekhar Chauhan <shekhar.chauhan@intel.com>
Signed-off-by: Gustavo Sousa <gustavo.sousa@intel.com>
---
 drivers/gpu/drm/i915/display/intel_bios.c     | 73 ++++++++++++++++++++++++++-
 drivers/gpu/drm/i915/display/intel_bios.h     |  2 +
 drivers/gpu/drm/i915/display/intel_vbt_defs.h |  3 +-
 3 files changed, 76 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_bios.c b/drivers/gpu/drm/i915/display/intel_bios.c
index 4b41068e9e35..0283c0d418cf 100644
--- a/drivers/gpu/drm/i915/display/intel_bios.c
+++ b/drivers/gpu/drm/i915/display/intel_bios.c
@@ -2529,6 +2529,54 @@ intel_bios_encoder_reject_edp_rate(const struct intel_bios_encoder_data *devdata
 	return devdata->child.edp_data_rate_override & edp_rate_override_mask(rate);
 }
 
+static void sanitize_dedicated_external(struct intel_bios_encoder_data *devdata,
+					enum port port)
+{
+	struct intel_display *display = devdata->display;
+
+	if (!intel_bios_encoder_is_dedicated_external(devdata))
+		return;
+
+	/*
+	 * Since dedicated_external is for ports connected to PHYs outside of
+	 * the Type-C subsystem, clear bits that would only make sense for ports
+	 * with PHYs in the Type-C subsystem.
+	 */
+
+	/*
+	 * Bit dp_usb_type_c is marked as "don't care" in Bspec when
+	 * dedicated_external is set.
+	 */
+	if (devdata->child.dp_usb_type_c) {
+		drm_dbg_kms(display->drm,
+			    "VBT claims Port %c supports USB Type-C, but the port is dedicated external, ignoring\n",
+			    port_name(port));
+		devdata->child.dp_usb_type_c = 0;
+	}
+
+	/*
+	 * Bit tbt is marked as "don't care" in Bspec when dedicated_external is
+	 * set.
+	 */
+	if (devdata->child.tbt) {
+		drm_dbg_kms(display->drm,
+			    "VBT claims Port %c supports TBT, but the port is dedicated external, ignoring\n",
+			    port_name(port));
+		devdata->child.tbt = 0;
+	}
+
+	/*
+	 * DDI allocation for TC capable ports only make sense for PHYs in the
+	 * Type-C subsystem.
+	 */
+	if (devdata->child.dyn_port_over_tc) {
+		drm_dbg_kms(display->drm,
+			    "VBT claims Port %c supports dynamic DDI allocation in TCSS, but the port is dedicated external, ignoring\n",
+			    port_name(port));
+		devdata->child.dyn_port_over_tc = 0;
+	}
+}
+
 static void sanitize_device_type(struct intel_bios_encoder_data *devdata,
 				 enum port port)
 {
@@ -2693,6 +2741,16 @@ static void print_ddi_port(const struct intel_bios_encoder_data *devdata)
 		    supports_typec_usb, supports_tbt,
 		    devdata->dsc != NULL);
 
+	if (intel_bios_encoder_is_dedicated_external(devdata))
+		drm_dbg_kms(display->drm,
+			    "Port %c is dedicated external\n",
+			    port_name(port));
+
+	if (intel_bios_encoder_supports_dyn_port_over_tc(devdata))
+		drm_dbg_kms(display->drm,
+			    "Port %c supports dynamic DDI allocation in TCSS\n",
+			    port_name(port));
+
 	hdmi_level_shift = intel_bios_hdmi_level_shift(devdata);
 	if (hdmi_level_shift >= 0) {
 		drm_dbg_kms(display->drm,
@@ -2750,6 +2808,7 @@ static void parse_ddi_port(struct intel_bios_encoder_data *devdata)
 		return;
 	}
 
+	sanitize_dedicated_external(devdata, port);
 	sanitize_device_type(devdata, port);
 	sanitize_hdmi_level_shift(devdata, port);
 }
@@ -2777,7 +2836,7 @@ static int child_device_expected_size(u16 version)
 {
 	BUILD_BUG_ON(sizeof(struct child_device_config) < 40);
 
-	if (version > 263)
+	if (version > 264)
 		return -ENOENT;
 	else if (version >= 263)
 		return 44;
@@ -3721,6 +3780,18 @@ bool intel_bios_encoder_supports_tbt(const struct intel_bios_encoder_data *devda
 	return devdata->display->vbt.version >= 209 && devdata->child.tbt;
 }
 
+bool intel_bios_encoder_is_dedicated_external(const struct intel_bios_encoder_data *devdata)
+{
+	return devdata->display->vbt.version >= 264 &&
+		devdata->child.dedicated_external;
+}
+
+bool intel_bios_encoder_supports_dyn_port_over_tc(const struct intel_bios_encoder_data *devdata)
+{
+	return devdata->display->vbt.version >= 264 &&
+		devdata->child.dyn_port_over_tc;
+}
+
 bool intel_bios_encoder_lane_reversal(const struct intel_bios_encoder_data *devdata)
 {
 	return devdata && devdata->child.lane_reversal;
diff --git a/drivers/gpu/drm/i915/display/intel_bios.h b/drivers/gpu/drm/i915/display/intel_bios.h
index f9e438b2787b..75dff27b4228 100644
--- a/drivers/gpu/drm/i915/display/intel_bios.h
+++ b/drivers/gpu/drm/i915/display/intel_bios.h
@@ -79,6 +79,8 @@ bool intel_bios_encoder_supports_dp(const struct intel_bios_encoder_data *devdat
 bool intel_bios_encoder_supports_edp(const struct intel_bios_encoder_data *devdata);
 bool intel_bios_encoder_supports_typec_usb(const struct intel_bios_encoder_data *devdata);
 bool intel_bios_encoder_supports_tbt(const struct intel_bios_encoder_data *devdata);
+bool intel_bios_encoder_is_dedicated_external(const struct intel_bios_encoder_data *devdata);
+bool intel_bios_encoder_supports_dyn_port_over_tc(const struct intel_bios_encoder_data *devdata);
 bool intel_bios_encoder_supports_dsi(const struct intel_bios_encoder_data *devdata);
 bool intel_bios_encoder_supports_dp_dual_mode(const struct intel_bios_encoder_data *devdata);
 bool intel_bios_encoder_is_lspcon(const struct intel_bios_encoder_data *devdata);
diff --git a/drivers/gpu/drm/i915/display/intel_vbt_defs.h b/drivers/gpu/drm/i915/display/intel_vbt_defs.h
index 70e31520c560..57fda5824c9c 100644
--- a/drivers/gpu/drm/i915/display/intel_vbt_defs.h
+++ b/drivers/gpu/drm/i915/display/intel_vbt_defs.h
@@ -554,7 +554,8 @@ struct child_device_config {
 	u8 dvo_function;
 	u8 dp_usb_type_c:1;					/* 195+ */
 	u8 tbt:1;						/* 209+ */
-	u8 flags2_reserved:2;					/* 195+ */
+	u8 dedicated_external:1;				/* 264+ */
+	u8 dyn_port_over_tc:1;					/* 264+ */
 	u8 dp_port_trace_length:4;				/* 209+ */
 	u8 dp_gpio_index;					/* 195+ */
 	u16 dp_gpio_pin_num;					/* 195+ */

-- 
2.51.0

[PATCH v5 2/8] drm/i915/power: Use intel_encoder_is_tc()

[Gustavo Sousa]

Starting with Xe3p_LPD, when intel_phy_is_tc() returns true, it does
not necessarily mean that the port is connected to a PHY in the Type-C
subsystem.  The reason is that there is now a VBT field called
dedicated_external that will indicate that a Type-C capable port is
connected to a (most likely) combo/dedicated PHY.  When that's the case,
we must not do the extra programming required for Type-C connections.

In an upcoming change, we will modify intel_encoder_is_tc() to take the
VBT field dedicated_external into consideration.  Update
intel_display_power_well.c to use that function instead of
intel_phy_is_tc().

Note that, even though icl_aux_power_well_{enable,disable} are not part
of Xe3p_LPD's display paths, we modify them anyway for uniformity.

v2:
  - Add and use icl_aux_pw_is_tc_phy() helper to avoid explicit encoder
    lookup. (Imre)

Cc: Imre Deak <imre.deak@intel.com>
Cc: Shekhar Chauhan <shekhar.chauhan@intel.com>
Reviewed-by: Suraj Kandpal <suraj.kandpal@intel.com> # v1
Signed-off-by: Gustavo Sousa <gustavo.sousa@intel.com>
---
 .../drm/i915/display/intel_display_power_well.c    | 33 +++++++++++++++-------
 1 file changed, 23 insertions(+), 10 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_display_power_well.c b/drivers/gpu/drm/i915/display/intel_display_power_well.c
index f4f7e73acc87..40d6b44c0b74 100644
--- a/drivers/gpu/drm/i915/display/intel_display_power_well.c
+++ b/drivers/gpu/drm/i915/display/intel_display_power_well.c
@@ -258,8 +258,9 @@ aux_ch_to_digital_port(struct intel_display *display,
 	return NULL;
 }
 
-static enum phy icl_aux_pw_to_phy(struct intel_display *display,
-				  const struct i915_power_well *power_well)
+static struct intel_encoder *
+icl_aux_pw_to_encoder(struct intel_display *display,
+		      const struct i915_power_well *power_well)
 {
 	enum aux_ch aux_ch = icl_aux_pw_to_ch(power_well);
 	struct intel_digital_port *dig_port = aux_ch_to_digital_port(display, aux_ch);
@@ -271,7 +272,23 @@ static enum phy icl_aux_pw_to_phy(struct intel_display *display,
 	 * as HDMI-only and routed to a combo PHY, the encoder either won't be
 	 * present at all or it will not have an aux_ch assigned.
 	 */
-	return dig_port ? intel_encoder_to_phy(&dig_port->base) : PHY_NONE;
+	return dig_port ? &dig_port->base : NULL;
+}
+
+static enum phy icl_aux_pw_to_phy(struct intel_display *display,
+				  const struct i915_power_well *power_well)
+{
+	struct intel_encoder *encoder = icl_aux_pw_to_encoder(display, power_well);
+
+	return encoder ? intel_encoder_to_phy(encoder) : PHY_NONE;
+}
+
+static bool icl_aux_pw_is_tc_phy(struct intel_display *display,
+				 const struct i915_power_well *power_well)
+{
+	struct intel_encoder *encoder = icl_aux_pw_to_encoder(display, power_well);
+
+	return encoder && intel_encoder_is_tc(encoder);
 }
 
 static void hsw_wait_for_power_well_enable(struct intel_display *display,
@@ -570,9 +587,7 @@ static void
 icl_aux_power_well_enable(struct intel_display *display,
 			  struct i915_power_well *power_well)
 {
-	enum phy phy = icl_aux_pw_to_phy(display, power_well);
-
-	if (intel_phy_is_tc(display, phy))
+	if (icl_aux_pw_is_tc_phy(display, power_well))
 		return icl_tc_phy_aux_power_well_enable(display, power_well);
 	else if (display->platform.icelake)
 		return icl_combo_phy_aux_power_well_enable(display,
@@ -585,9 +600,7 @@ static void
 icl_aux_power_well_disable(struct intel_display *display,
 			   struct i915_power_well *power_well)
 {
-	enum phy phy = icl_aux_pw_to_phy(display, power_well);
-
-	if (intel_phy_is_tc(display, phy))
+	if (icl_aux_pw_is_tc_phy(display, power_well))
 		return hsw_power_well_disable(display, power_well);
 	else if (display->platform.icelake)
 		return icl_combo_phy_aux_power_well_disable(display,
@@ -1852,7 +1865,7 @@ static void xelpdp_aux_power_well_enable(struct intel_display *display,
 	enum aux_ch aux_ch = i915_power_well_instance(power_well)->xelpdp.aux_ch;
 	enum phy phy = icl_aux_pw_to_phy(display, power_well);
 
-	if (intel_phy_is_tc(display, phy))
+	if (icl_aux_pw_is_tc_phy(display, power_well))
 		icl_tc_port_assert_ref_held(display, power_well,
 					    aux_ch_to_digital_port(display, aux_ch));
 

-- 
2.51.0

[PATCH v5 3/8] drm/i915/display: Handle dedicated external ports in intel_encoder_is_tc()

[Gustavo Sousa]

Starting with Xe3p_LPD, the VBT has a new field, called in the driver
"dedicated_external", which tells that a Type-C capable port is
physically connected to a PHY outside of the Type-C subsystem.  When
that's the case, the driver must not do the extra Type-C programming for
that port.  Update intel_encoder_is_tc() to check for that case.

While at it, add a note to intel_phy_is_tc() to remind us that it is
about whether the respective port is a Type-C capable port rather than
the PHY itself.

(Maybe it would be a nice idea to rename intel_phy_is_tc()?)

Note that this was handled with a new bool member added to struct
intel_digital_port instead of having querying the VBT directly because
VBT memory is freed (intel_bios_driver_remove) before encoder cleanup
(intel_ddi_encoder_destroy), which would cause an oops to happen when
the latter calls intel_encoder_is_tc().  This could be fixed by keeping
VBT data around longer, but that's left for a follow-up work, if deemed
necessary.

v2:
  - Drop printing info about dedicated external, now that we are doing
    it when parsing the VBT. (Jani)
  - Add a FIXME comment on the code explaining why we need to store
    dedicated_external in struct intel_digital_port. (Jani)
v3:
  - Simplify the code by using NULL check for dig_port to avoid using
    intel_encoder_is_dig_port(). (Imre)

Cc: Imre Deak <imre.deak@intel.com>
Cc: Jani Nikula <jani.nikula@linux.intel.com>
Cc: Shekhar Chauhan <shekhar.chauhan@intel.com>
Signed-off-by: Gustavo Sousa <gustavo.sousa@intel.com>
---
 drivers/gpu/drm/i915/display/intel_ddi.c           | 11 +++++++++++
 drivers/gpu/drm/i915/display/intel_display.c       | 16 +++++++++++++++-
 drivers/gpu/drm/i915/display/intel_display_types.h |  1 +
 3 files changed, 27 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
index 002ccd47856d..11ceb9355b75 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -5372,6 +5372,17 @@ void intel_ddi_init(struct intel_display *display,
 			goto err;
 	}
 
+	/*
+	 * FIXME: We currently need to store dedicated_external because devdata
+	 * does not live long enough for when intel_encoder_is_tc() is called on
+	 * the unbind path.  This needs to be fixed by making sure that the VBT
+	 * data is kept long enough, so that
+	 * intel_bios_encoder_is_dedicated_external() can be called directly
+	 * from intel_encoder_is_tc().
+	 */
+	if (intel_bios_encoder_is_dedicated_external(devdata))
+		dig_port->dedicated_external = true;
+
 	if (intel_encoder_is_tc(encoder)) {
 		bool is_legacy =
 			!intel_bios_encoder_supports_typec_usb(devdata) &&
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 069967114bd9..5071a0ae5235 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -1810,7 +1810,17 @@ bool intel_phy_is_combo(struct intel_display *display, enum phy phy)
 		return false;
 }
 
-/* Prefer intel_encoder_is_tc() */
+/*
+ * This function returns true if the DDI port respective to the PHY enumeration
+ * is a Type-C capable port.
+ *
+ * Depending on the VBT, the port might be configured
+ * as a "dedicated external" port, meaning that actual physical PHY is outside
+ * of the Type-C subsystem and, as such, not really a "Type-C PHY".
+ *
+ * Prefer intel_encoder_is_tc(), especially if you really need to know if we
+ * are dealing with Type-C connections.
+ */
 bool intel_phy_is_tc(struct intel_display *display, enum phy phy)
 {
 	/*
@@ -1894,6 +1904,10 @@ bool intel_encoder_is_snps(struct intel_encoder *encoder)
 bool intel_encoder_is_tc(struct intel_encoder *encoder)
 {
 	struct intel_display *display = to_intel_display(encoder);
+	struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
+
+	if (dig_port && dig_port->dedicated_external)
+		return false;
 
 	return intel_phy_is_tc(display, intel_encoder_to_phy(encoder));
 }
diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
index 38702a9e0f50..7b08d618776c 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -1936,6 +1936,7 @@ struct intel_digital_port {
 	bool lane_reversal;
 	bool ddi_a_4_lanes;
 	bool release_cl2_override;
+	bool dedicated_external;
 	u8 max_lanes;
 	/* Used for DP and ICL+ TypeC/DP and TypeC/HDMI ports. */
 	enum aux_ch aux_ch;

-- 
2.51.0

[PATCH v5 4/8] drm/i915/xe3p_lpd: Handle underrun debug bits

[Gustavo Sousa]

Xe3p_LPD added several bits containing information that can be relevant
to debugging FIFO underruns.  Add the logic necessary to handle them
when reporting underruns.

This was adapted from the initial patch[1] from Sai Teja Pottumuttu.

[1] https://lore.kernel.org/all/20251015-xe3p_lpd-basic-enabling-v1-12-d2d1e26520aa@intel.com/

v2:
  - Handle FBC-related bits in intel_fbc.c. (Ville)
  - Do not use intel_fbc_id_for_pipe (promoted from
    skl_fbc_id_for_pipe), but use pipe's primary plane to get the FBC
    instance. (Ville, Matt)
  - Improve code readability by moving logic specific to logging fields
    of UNDERRUN_DBG1 to a separate function. (Jani)

Bspec: 69111, 69561, 74411, 74412
Cc: Jani Nikula <jani.nikula@intel.com>
Cc: Matt Roper <matthew.d.roper@intel.com>
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Gustavo Sousa <gustavo.sousa@intel.com>
---
I tested this by adding a change on top of this series that updates
Xe3p_LPD's CDCLK table to use bad values and I got the following
messages:

    [  +0.000237] xe 0000:00:02.0: [drm:intel_modeset_verify_crtc [xe]] [CRTC:88:pipe A]
    [  +0.000674] xe 0000:00:02.0: [drm] *ERROR* CPU pipe A FIFO underrun
    [  +0.000015] xe 0000:00:02.0: [drm] *ERROR* Pipe A FIFO underrun info: DBUF block not valid on planes: [1]
    [  +0.000001] xe 0000:00:02.0: [drm] *ERROR* Pipe A FIFO underrun info: DDB empty on planes: [1]
    [  +0.000001] xe 0000:00:02.0: [drm] *ERROR* Pipe A FIFO underrun info: DBUF below WM0 on planes: [1]
    [  +0.000004] xe 0000:00:02.0: [drm] *ERROR* Pipe A FIFO underrun info: frame count: 1890, line count: 44
---
 .../gpu/drm/i915/display/intel_display_device.h    |   1 +
 drivers/gpu/drm/i915/display/intel_display_regs.h  |  16 +++
 drivers/gpu/drm/i915/display/intel_fbc.c           |  50 ++++++++++
 drivers/gpu/drm/i915/display/intel_fbc.h           |   3 +
 drivers/gpu/drm/i915/display/intel_fbc_regs.h      |   2 +
 drivers/gpu/drm/i915/display/intel_fifo_underrun.c | 109 +++++++++++++++++++++
 6 files changed, 181 insertions(+)

diff --git a/drivers/gpu/drm/i915/display/intel_display_device.h b/drivers/gpu/drm/i915/display/intel_display_device.h
index b559ef43d547..91d8cfac5eff 100644
--- a/drivers/gpu/drm/i915/display/intel_display_device.h
+++ b/drivers/gpu/drm/i915/display/intel_display_device.h
@@ -197,6 +197,7 @@ struct intel_display_platforms {
 #define HAS_TRANSCODER(__display, trans)	((DISPLAY_RUNTIME_INFO(__display)->cpu_transcoder_mask & \
 						  BIT(trans)) != 0)
 #define HAS_UNCOMPRESSED_JOINER(__display)	(DISPLAY_VER(__display) >= 13)
+#define HAS_UNDERRUN_DBG_INFO(__display)	(DISPLAY_VER(__display) >= 35)
 #define HAS_ULTRAJOINER(__display)	(((__display)->platform.dgfx && \
 					  DISPLAY_VER(__display) == 14) && HAS_DSC(__display))
 #define HAS_VRR(__display)		(DISPLAY_VER(__display) >= 11)
diff --git a/drivers/gpu/drm/i915/display/intel_display_regs.h b/drivers/gpu/drm/i915/display/intel_display_regs.h
index 9d71e26a4fa2..89ea0156ee06 100644
--- a/drivers/gpu/drm/i915/display/intel_display_regs.h
+++ b/drivers/gpu/drm/i915/display/intel_display_regs.h
@@ -882,6 +882,21 @@
 #define   PIPE_MISC2_FLIP_INFO_PLANE_SEL_MASK		REG_GENMASK(2, 0) /* tgl+ */
 #define   PIPE_MISC2_FLIP_INFO_PLANE_SEL(plane_id)	REG_FIELD_PREP(PIPE_MISC2_FLIP_INFO_PLANE_SEL_MASK, (plane_id))
 
+#define _UNDERRUN_DBG1_A			0x70064
+#define _UNDERRUN_DBG1_B			0x71064
+#define UNDERRUN_DBG1(pipe)			_MMIO_PIPE(pipe, _UNDERRUN_DBG1_A, _UNDERRUN_DBG1_B)
+#define   UNDERRUN_DBUF_BLOCK_NOT_VALID_MASK	REG_GENMASK(29, 24)
+#define   UNDERRUN_DDB_EMPTY_MASK		REG_GENMASK(21, 16)
+#define   UNDERRUN_DBUF_NOT_FILLED_MASK		REG_GENMASK(13, 8)
+#define   UNDERRUN_BELOW_WM0_MASK		REG_GENMASK(5, 0)
+
+#define _UNDERRUN_DBG2_A			0x70068
+#define _UNDERRUN_DBG2_B			0x71068
+#define UNDERRUN_DBG2(pipe)			_MMIO_PIPE(pipe, _UNDERRUN_DBG2_A, _UNDERRUN_DBG2_B)
+#define   UNDERRUN_FRAME_LINE_COUNTERS_FROZEN	REG_BIT(31)
+#define   UNDERRUN_PIPE_FRAME_COUNT_MASK	REG_GENMASK(30, 20)
+#define   UNDERRUN_LINE_COUNT_MASK		REG_GENMASK(19, 0)
+
 #define DPINVGTT				_MMIO(VLV_DISPLAY_BASE + 0x7002c) /* VLV/CHV only */
 #define   DPINVGTT_EN_MASK_CHV				REG_GENMASK(27, 16)
 #define   DPINVGTT_EN_MASK_VLV				REG_GENMASK(23, 16)
@@ -1416,6 +1431,7 @@
 
 #define GEN12_DCPR_STATUS_1				_MMIO(0x46440)
 #define  XELPDP_PMDEMAND_INFLIGHT_STATUS		REG_BIT(26)
+#define  XE3P_UNDERRUN_PKGC				REG_BIT(21)
 
 #define FUSE_STRAP		_MMIO(0x42014)
 #define   ILK_INTERNAL_GRAPHICS_DISABLE	REG_BIT(31)
diff --git a/drivers/gpu/drm/i915/display/intel_fbc.c b/drivers/gpu/drm/i915/display/intel_fbc.c
index 437d2fda20a7..ec316f9843c6 100644
--- a/drivers/gpu/drm/i915/display/intel_fbc.c
+++ b/drivers/gpu/drm/i915/display/intel_fbc.c
@@ -129,6 +129,25 @@ struct intel_fbc {
 	const char *no_fbc_reason;
 };
 
+static struct intel_fbc *intel_fbc_for_pipe(struct intel_display *display, enum pipe pipe)
+{
+	struct intel_crtc *crtc = intel_crtc_for_pipe(display, pipe);
+	struct intel_plane *primary = NULL;
+	struct intel_plane *plane;
+
+	for_each_intel_plane_on_crtc(display->drm, crtc, plane) {
+		if (plane->base.type == DRM_PLANE_TYPE_PRIMARY) {
+			primary = plane;
+			break;
+		}
+	}
+
+	if (drm_WARN_ON(display->drm, !primary))
+		return NULL;
+
+	return primary->fbc;
+}
+
 /* plane stride in pixels */
 static unsigned int intel_fbc_plane_stride(const struct intel_plane_state *plane_state)
 {
@@ -2119,6 +2138,37 @@ void intel_fbc_handle_fifo_underrun_irq(struct intel_display *display)
 		__intel_fbc_handle_fifo_underrun_irq(fbc);
 }
 
+/**
+ * intel_fbc_read_underrun_dbg_info - Read and log FBC-related FIFO underrun debug info
+ * @display: display device instance
+ * @pipe: the pipe possibly containing the FBC
+ * @log: log the info?
+ *
+ * If @pipe does not contain an FBC instance, this function bails early.
+ * Otherwise, FBC-related FIFO underrun is read and cleared, and then, if @log
+ * is true, printed with error level.
+ */
+void intel_fbc_read_underrun_dbg_info(struct intel_display *display,
+				      enum pipe pipe, bool log)
+{
+	struct intel_fbc *fbc = intel_fbc_for_pipe(display, pipe);
+	u32 val;
+
+	if (!fbc)
+		return;
+
+	val = intel_de_read(display, FBC_DEBUG_STATUS(fbc->id));
+	if (!(val & FBC_UNDERRUN_DECMPR))
+		return;
+
+	intel_de_write(display, FBC_DEBUG_STATUS(fbc->id), FBC_UNDERRUN_DECMPR);
+
+	if (log)
+		drm_err(display->drm,
+			"Pipe %c FIFO underrun info: FBC decompressing\n",
+			pipe_name(pipe));
+}
+
 /*
  * The DDX driver changes its behavior depending on the value it reads from
  * i915.enable_fbc, so sanitize it by translating the default value into either
diff --git a/drivers/gpu/drm/i915/display/intel_fbc.h b/drivers/gpu/drm/i915/display/intel_fbc.h
index 91424563206a..f0255ddae2b6 100644
--- a/drivers/gpu/drm/i915/display/intel_fbc.h
+++ b/drivers/gpu/drm/i915/display/intel_fbc.h
@@ -9,6 +9,7 @@
 #include <linux/types.h>
 
 enum fb_op_origin;
+enum pipe;
 struct intel_atomic_state;
 struct intel_crtc;
 struct intel_crtc_state;
@@ -46,6 +47,8 @@ void intel_fbc_flush(struct intel_display *display,
 		     unsigned int frontbuffer_bits, enum fb_op_origin origin);
 void intel_fbc_add_plane(struct intel_fbc *fbc, struct intel_plane *plane);
 void intel_fbc_handle_fifo_underrun_irq(struct intel_display *display);
+void intel_fbc_read_underrun_dbg_info(struct intel_display *display,
+				      enum pipe, bool log);
 void intel_fbc_reset_underrun(struct intel_display *display);
 void intel_fbc_crtc_debugfs_add(struct intel_crtc *crtc);
 void intel_fbc_debugfs_register(struct intel_display *display);
diff --git a/drivers/gpu/drm/i915/display/intel_fbc_regs.h b/drivers/gpu/drm/i915/display/intel_fbc_regs.h
index b1d0161a3196..77d8321c4fb3 100644
--- a/drivers/gpu/drm/i915/display/intel_fbc_regs.h
+++ b/drivers/gpu/drm/i915/display/intel_fbc_regs.h
@@ -88,6 +88,8 @@
 #define DPFC_FENCE_YOFF			_MMIO(0x3218)
 #define ILK_DPFC_FENCE_YOFF(fbc_id)	_MMIO_PIPE((fbc_id), 0x43218, 0x43258)
 #define DPFC_CHICKEN			_MMIO(0x3224)
+#define FBC_DEBUG_STATUS(fbc_id)	_MMIO_PIPE((fbc_id), 0x43220, 0x43260)
+#define   FBC_UNDERRUN_DECMPR			REG_BIT(27)
 #define ILK_DPFC_CHICKEN(fbc_id)	_MMIO_PIPE((fbc_id), 0x43224, 0x43264)
 #define   DPFC_HT_MODIFY			REG_BIT(31) /* pre-ivb */
 #define   DPFC_NUKE_ON_ANY_MODIFICATION		REG_BIT(23) /* bdw+ */
diff --git a/drivers/gpu/drm/i915/display/intel_fifo_underrun.c b/drivers/gpu/drm/i915/display/intel_fifo_underrun.c
index c2ce8461ac9e..b413b3e871d8 100644
--- a/drivers/gpu/drm/i915/display/intel_fifo_underrun.c
+++ b/drivers/gpu/drm/i915/display/intel_fifo_underrun.c
@@ -25,6 +25,8 @@
  *
  */
 
+#include <linux/seq_buf.h>
+
 #include <drm/drm_print.h>
 
 #include "i915_reg.h"
@@ -57,6 +59,100 @@
  * The code also supports underrun detection on the PCH transcoder.
  */
 
+#define UNDERRUN_DBG1_NUM_PLANES 6
+
+static void log_underrun_dbg1(struct intel_display *display, enum pipe pipe,
+			      unsigned long plane_mask, const char *info)
+{
+	DECLARE_SEQ_BUF(planes_desc, 32);
+	unsigned int i;
+
+	if (!plane_mask)
+		return;
+
+	for_each_set_bit(i, &plane_mask, UNDERRUN_DBG1_NUM_PLANES) {
+		if (i == 0)
+			seq_buf_puts(&planes_desc, "[C]");
+		else
+			seq_buf_printf(&planes_desc, "[%d]", i);
+	}
+
+	drm_err(display->drm, "Pipe %c FIFO underrun info: %s on planes: %s\n",
+		pipe_name(pipe), info, seq_buf_str(&planes_desc));
+
+	drm_WARN_ON(display->drm, seq_buf_has_overflowed(&planes_desc));
+}
+
+static void read_underrun_dbg1(struct intel_display *display, enum pipe pipe, bool log)
+{
+	u32 val = intel_de_read(display, UNDERRUN_DBG1(pipe));
+
+	if (!val)
+		return;
+
+	intel_de_write(display, UNDERRUN_DBG1(pipe), val);
+
+	if (!log)
+		return;
+
+	log_underrun_dbg1(display, pipe, REG_FIELD_GET(UNDERRUN_DBUF_BLOCK_NOT_VALID_MASK, val),
+			  "DBUF block not valid");
+	log_underrun_dbg1(display, pipe, REG_FIELD_GET(UNDERRUN_DDB_EMPTY_MASK, val),
+			  "DDB empty");
+	log_underrun_dbg1(display, pipe, REG_FIELD_GET(UNDERRUN_DBUF_NOT_FILLED_MASK, val),
+			  "DBUF not completely filled");
+	log_underrun_dbg1(display, pipe, REG_FIELD_GET(UNDERRUN_BELOW_WM0_MASK, val),
+			  "DBUF below WM0");
+}
+
+static void read_underrun_dbg2(struct intel_display *display, enum pipe pipe, bool log)
+{
+	u32 val = intel_de_read(display, UNDERRUN_DBG2(pipe));
+
+	if (!(val & UNDERRUN_FRAME_LINE_COUNTERS_FROZEN))
+		return;
+
+	intel_de_write(display, UNDERRUN_DBG2(pipe), UNDERRUN_FRAME_LINE_COUNTERS_FROZEN);
+
+	if (log)
+		drm_err(display->drm,
+			"Pipe %c FIFO underrun info: frame count: %u, line count: %u\n",
+			pipe_name(pipe),
+			REG_FIELD_GET(UNDERRUN_PIPE_FRAME_COUNT_MASK, val),
+			REG_FIELD_GET(UNDERRUN_LINE_COUNT_MASK, val));
+}
+
+static void read_underrun_dbg_pkgc(struct intel_display *display, bool log)
+{
+	u32 val = intel_de_read(display, GEN12_DCPR_STATUS_1);
+
+	if (!(val & XE3P_UNDERRUN_PKGC))
+		return;
+
+	/*
+	 * Note: If there are multiple pipes enabled, only one of them will see
+	 * XE3P_UNDERRUN_PKGC set.
+	 */
+	intel_de_write(display, GEN12_DCPR_STATUS_1, XE3P_UNDERRUN_PKGC);
+
+	if (log)
+		drm_err(display->drm,
+			"General FIFO underrun info: Package C-state blocking memory\n");
+}
+
+static void read_underrun_dbg_info(struct intel_display *display,
+				   enum pipe pipe,
+				   bool log)
+{
+	if (!HAS_UNDERRUN_DBG_INFO(display))
+		return;
+
+	read_underrun_dbg1(display, pipe, log);
+	read_underrun_dbg2(display, pipe, log);
+	intel_fbc_read_underrun_dbg_info(display, pipe, log);
+	read_underrun_dbg_pkgc(display, log);
+}
+
 static bool ivb_can_enable_err_int(struct intel_display *display)
 {
 	struct intel_crtc *crtc;
@@ -262,6 +358,17 @@ static bool __intel_set_cpu_fifo_underrun_reporting(struct intel_display *displa
 	old = !crtc->cpu_fifo_underrun_disabled;
 	crtc->cpu_fifo_underrun_disabled = !enable;
 
+	/*
+	 * The debug bits get latched at the time of the FIFO underrun ISR bit
+	 * getting set.  That means that any non-zero debug bit that is read when
+	 * handling a FIFO underrun interrupt has the potential to belong to
+	 * another underrun event (past or future).  To alleviate this problem,
+	 * let's clear existing bits before enabling the interrupt, so that at
+	 * least we don't get information that is too out-of-date.
+	 */
+	if (enable && !old)
+		read_underrun_dbg_info(display, pipe, false);
+
 	if (HAS_GMCH(display))
 		i9xx_set_fifo_underrun_reporting(display, pipe, enable, old);
 	else if (display->platform.ironlake || display->platform.sandybridge)
@@ -379,6 +486,8 @@ void intel_cpu_fifo_underrun_irq_handler(struct intel_display *display,
 		trace_intel_cpu_fifo_underrun(display, pipe);
 
 		drm_err(display->drm, "CPU pipe %c FIFO underrun\n", pipe_name(pipe));
+
+		read_underrun_dbg_info(display, pipe, true);
 	}
 
 	intel_fbc_handle_fifo_underrun_irq(display);

-- 
2.51.0

[PATCH v5 5/8] drm/i915/nvls: Add NVL-S display support

[Gustavo Sousa]

From: Sai Teja Pottumuttu <sai.teja.pottumuttu@intel.com>

Add platform description and PCI IDs for NVL-S.

BSpec: 74201
Signed-off-by: Sai Teja Pottumuttu <sai.teja.pottumuttu@intel.com>
Reviewed-by: Shekhar Chauhan <shekhar.chauhan@intel.com>
Signed-off-by: Gustavo Sousa <gustavo.sousa@intel.com>
---
 drivers/gpu/drm/i915/display/intel_display_device.c | 5 +++++
 drivers/gpu/drm/i915/display/intel_display_device.h | 4 +++-
 2 files changed, 8 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/display/intel_display_device.c b/drivers/gpu/drm/i915/display/intel_display_device.c
index 1170afaa8680..471f236c9ddf 100644
--- a/drivers/gpu/drm/i915/display/intel_display_device.c
+++ b/drivers/gpu/drm/i915/display/intel_display_device.c
@@ -1420,6 +1420,10 @@ static const struct platform_desc ptl_desc = {
 	}
 };
 
+static const struct platform_desc nvl_desc = {
+	PLATFORM(novalake),
+};
+
 __diag_pop();
 
 /*
@@ -1495,6 +1499,7 @@ static const struct {
 	INTEL_BMG_IDS(INTEL_DISPLAY_DEVICE, &bmg_desc),
 	INTEL_PTL_IDS(INTEL_DISPLAY_DEVICE, &ptl_desc),
 	INTEL_WCL_IDS(INTEL_DISPLAY_DEVICE, &ptl_desc),
+	INTEL_NVLS_IDS(INTEL_DISPLAY_DEVICE, &nvl_desc),
 };
 
 static const struct {
diff --git a/drivers/gpu/drm/i915/display/intel_display_device.h b/drivers/gpu/drm/i915/display/intel_display_device.h
index 91d8cfac5eff..9affb6a53da4 100644
--- a/drivers/gpu/drm/i915/display/intel_display_device.h
+++ b/drivers/gpu/drm/i915/display/intel_display_device.h
@@ -103,7 +103,9 @@ struct pci_dev;
 	func(battlemage) \
 	/* Display ver 30 (based on GMD ID) */ \
 	func(pantherlake) \
-	func(pantherlake_wildcatlake)
+	func(pantherlake_wildcatlake) \
+	/* Display ver 35 (based on GMD ID) */ \
+	func(novalake)
 
 
 #define __MEMBER(name) unsigned long name:1;

-- 
2.51.0

[PATCH v5 6/8] drm/i915/display: Use platform check in HAS_LT_PHY()

[Gustavo Sousa]

NVL uses the Lake Tahoe PHY for display output and the driver recently
added the macro HAS_LT_PHY() to allow selecting code paths specific for
that type of PHY.

While NVL uses Xe3p_LPD as display IP, the type of PHY is actually
defined at the SoC level, so use a platform check instead of display
version.

Bspec: 74199
Cc: Suraj Kandpal <suraj.kandpal@intel.com>
Cc: Matt Roper <matthew.d.roper@intel.com>
Reviewed-by: Matt Roper <matthew.d.roper@intel.com>
Reviewed-by: Dnyaneshwar Bhadane <dnyaneshwar.bhadane@intel.com>
Signed-off-by: Gustavo Sousa <gustavo.sousa@intel.com>
---
 drivers/gpu/drm/i915/display/intel_lt_phy.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/display/intel_lt_phy.h b/drivers/gpu/drm/i915/display/intel_lt_phy.h
index b7911acd7dcd..0820968e51b5 100644
--- a/drivers/gpu/drm/i915/display/intel_lt_phy.h
+++ b/drivers/gpu/drm/i915/display/intel_lt_phy.h
@@ -42,6 +42,6 @@ void intel_xe3plpd_pll_enable(struct intel_encoder *encoder,
 			      const struct intel_crtc_state *crtc_state);
 void intel_xe3plpd_pll_disable(struct intel_encoder *encoder);
 
-#define HAS_LT_PHY(display) (DISPLAY_VER(display) >= 35)
+#define HAS_LT_PHY(display) ((display)->platform.novalake)
 
 #endif /* __INTEL_LT_PHY_H__ */

-- 
2.51.0

[PATCH v5 7/8] drm/i915/display: Move HAS_LT_PHY() to intel_display_device.h

[Gustavo Sousa]

We will need to HAS_LT_PHY() that macro in code outside of LT PHY
implementation. Move its definition to intel_display_device.h.

Cc: Matt Roper <matthew.d.roper@intel.com>
Cc: Suraj Kandpal <suraj.kandpal@intel.com>
Reviewed-by: Matt Roper <matthew.d.roper@intel.com>
Signed-off-by: Gustavo Sousa <gustavo.sousa@intel.com>
---
 drivers/gpu/drm/i915/display/intel_display_device.h | 1 +
 drivers/gpu/drm/i915/display/intel_lt_phy.h         | 2 --
 2 files changed, 1 insertion(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_display_device.h b/drivers/gpu/drm/i915/display/intel_display_device.h
index 9affb6a53da4..2455ec826abe 100644
--- a/drivers/gpu/drm/i915/display/intel_display_device.h
+++ b/drivers/gpu/drm/i915/display/intel_display_device.h
@@ -187,6 +187,7 @@ struct intel_display_platforms {
 #define HAS_IPS(__display)		((__display)->platform.haswell_ult || (__display)->platform.broadwell)
 #define HAS_LRR(__display)		(DISPLAY_VER(__display) >= 12)
 #define HAS_LSPCON(__display)		(IS_DISPLAY_VER(__display, 9, 10))
+#define HAS_LT_PHY(__display)		((__display)->platform.novalake)
 #define HAS_MBUS_JOINING(__display)	((__display)->platform.alderlake_p || DISPLAY_VER(__display) >= 14)
 #define HAS_MSO(__display)		(DISPLAY_VER(__display) >= 12)
 #define HAS_OVERLAY(__display)		(DISPLAY_INFO(__display)->has_overlay)
diff --git a/drivers/gpu/drm/i915/display/intel_lt_phy.h b/drivers/gpu/drm/i915/display/intel_lt_phy.h
index 0820968e51b5..7659c92b6c3c 100644
--- a/drivers/gpu/drm/i915/display/intel_lt_phy.h
+++ b/drivers/gpu/drm/i915/display/intel_lt_phy.h
@@ -42,6 +42,4 @@ void intel_xe3plpd_pll_enable(struct intel_encoder *encoder,
 			      const struct intel_crtc_state *crtc_state);
 void intel_xe3plpd_pll_disable(struct intel_encoder *encoder);
 
-#define HAS_LT_PHY(display) ((display)->platform.novalake)
-
 #endif /* __INTEL_LT_PHY_H__ */

-- 
2.51.0

[PATCH v5 8/8] drm/i915/display: Use HAS_LT_PHY() for LT PHY AUX power

[Gustavo Sousa]

Bspec states that the new AUX power enable/disable sequences are
associated with the LT PHY.  As such, use HAS_LT_PHY() instead of IP
checks in those paths in the driver code.

While at it, also move the comment that we can't use the power status
flag to the "else" branch, since that comment is not applicable for the
LT PHY.

Bspec: 68967
Cc: Matt Roper <matthew.d.roper@intel.com>
Cc: Suraj Kandpal <suraj.kandpal@intel.com>
Suggested-by: Matt Roper <matthew.d.roper@intel.com>
Reviewed-by: Matt Roper <matthew.d.roper@intel.com>
Signed-off-by: Gustavo Sousa <gustavo.sousa@intel.com>
---
 drivers/gpu/drm/i915/display/intel_display_power_well.c | 16 ++++++++--------
 1 file changed, 8 insertions(+), 8 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_display_power_well.c b/drivers/gpu/drm/i915/display/intel_display_power_well.c
index 40d6b44c0b74..d2cb11626c1a 100644
--- a/drivers/gpu/drm/i915/display/intel_display_power_well.c
+++ b/drivers/gpu/drm/i915/display/intel_display_power_well.c
@@ -1873,19 +1873,19 @@ static void xelpdp_aux_power_well_enable(struct intel_display *display,
 		     XELPDP_DP_AUX_CH_CTL_POWER_REQUEST,
 		     XELPDP_DP_AUX_CH_CTL_POWER_REQUEST);
 
-	/*
-	 * The power status flag cannot be used to determine whether aux
-	 * power wells have finished powering up.  Instead we're
-	 * expected to just wait a fixed 600us after raising the request
-	 * bit.
-	 */
-	if (DISPLAY_VER(display) >= 35) {
+	if (HAS_LT_PHY(display)) {
 		if (intel_de_wait_for_set_ms(display, XELPDP_DP_AUX_CH_CTL(display, aux_ch),
 					     XELPDP_DP_AUX_CH_CTL_POWER_STATUS, 2))
 			drm_warn(display->drm,
 				 "Timeout waiting for PHY %c AUX channel power to be up\n",
 				 phy_name(phy));
 	} else {
+		/*
+		 * The power status flag cannot be used to determine whether aux
+		 * power wells have finished powering up.  Instead we're
+		 * expected to just wait a fixed 600us after raising the request
+		 * bit.
+		 */
 		usleep_range(600, 1200);
 	}
 }
@@ -1900,7 +1900,7 @@ static void xelpdp_aux_power_well_disable(struct intel_display *display,
 		     XELPDP_DP_AUX_CH_CTL_POWER_REQUEST,
 		     0);
 
-	if (DISPLAY_VER(display) >= 35) {
+	if (HAS_LT_PHY(display)) {
 		if (intel_de_wait_for_clear_ms(display, XELPDP_DP_AUX_CH_CTL(display, aux_ch),
 					       XELPDP_DP_AUX_CH_CTL_POWER_STATUS, 1))
 			drm_warn(display->drm,

-- 
2.51.0

✗ CI.checkpatch: warning for drm/i915/display: Add initial support for Xe3p_LPD (rev5)

[Patchwork]

== Series Details ==

Series: drm/i915/display: Add initial support for Xe3p_LPD (rev5)
URL   : https://patchwork.freedesktop.org/series/155951/
State : warning

== Summary ==

+ KERNEL=/kernel
+ git clone https://gitlab.freedesktop.org/drm/maintainer-tools mt
Cloning into 'mt'...
warning: redirecting to https://gitlab.freedesktop.org/drm/maintainer-tools.git/
+ git -C mt rev-list -n1 origin/master
2de9a3901bc28757c7906b454717b64e2a214021
+ cd /kernel
+ git config --global --add safe.directory /kernel
+ git log -n1
commit 1a6e55fa201c4ad354455b1a134db303070183d3
Author: Gustavo Sousa <gustavo.sousa@intel.com>
Date:   Fri Nov 14 17:52:15 2025 -0300

    drm/i915/display: Use HAS_LT_PHY() for LT PHY AUX power
    
    Bspec states that the new AUX power enable/disable sequences are
    associated with the LT PHY.  As such, use HAS_LT_PHY() instead of IP
    checks in those paths in the driver code.
    
    While at it, also move the comment that we can't use the power status
    flag to the "else" branch, since that comment is not applicable for the
    LT PHY.
    
    Bspec: 68967
    Cc: Matt Roper <matthew.d.roper@intel.com>
    Cc: Suraj Kandpal <suraj.kandpal@intel.com>
    Suggested-by: Matt Roper <matthew.d.roper@intel.com>
    Reviewed-by: Matt Roper <matthew.d.roper@intel.com>
    Signed-off-by: Gustavo Sousa <gustavo.sousa@intel.com>
+ /mt/dim checkpatch 0602386d452aeaa5f0abadb7d2805ea45f97d9f6 drm-intel
e7385f79870c drm/i915/vbt: Add fields dedicated_external and dyn_port_over_tc
7a2251517b90 drm/i915/power: Use intel_encoder_is_tc()
5f488a7e9658 drm/i915/display: Handle dedicated external ports in intel_encoder_is_tc()
244a52dbff2f drm/i915/xe3p_lpd: Handle underrun debug bits
-:15: WARNING:COMMIT_LOG_LONG_LINE: Prefer a maximum 75 chars per line (possible unwrapped commit description?)
#15: 
[1] https://lore.kernel.org/all/20251015-xe3p_lpd-basic-enabling-v1-12-d2d1e26520aa@intel.com/

total: 0 errors, 1 warnings, 0 checks, 253 lines checked
d0702dbc676e drm/i915/nvls: Add NVL-S display support
41438d575930 drm/i915/display: Use platform check in HAS_LT_PHY()
c7ac7aa8a149 drm/i915/display: Move HAS_LT_PHY() to intel_display_device.h
1a6e55fa201c drm/i915/display: Use HAS_LT_PHY() for LT PHY AUX power

✓ CI.KUnit: success for drm/i915/display: Add initial support for Xe3p_LPD (rev5)

[Patchwork]

== Series Details ==

Series: drm/i915/display: Add initial support for Xe3p_LPD (rev5)
URL   : https://patchwork.freedesktop.org/series/155951/
State : success

== Summary ==

+ trap cleanup EXIT
+ /kernel/tools/testing/kunit/kunit.py run --kunitconfig /kernel/drivers/gpu/drm/xe/.kunitconfig
[21:09:34] Configuring KUnit Kernel ...
Generating .config ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
[21:09:38] Building KUnit Kernel ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
Building with:
$ make all compile_commands.json scripts_gdb ARCH=um O=.kunit --jobs=48
[21:10:09] Starting KUnit Kernel (1/1)...
[21:10:09] ============================================================
Running tests with:
$ .kunit/linux kunit.enable=1 mem=1G console=tty kunit_shutdown=halt
[21:10:09] ================== guc_buf (11 subtests) ===================
[21:10:09] [PASSED] test_smallest
[21:10:09] [PASSED] test_largest
[21:10:09] [PASSED] test_granular
[21:10:09] [PASSED] test_unique
[21:10:09] [PASSED] test_overlap
[21:10:09] [PASSED] test_reusable
[21:10:09] [PASSED] test_too_big
[21:10:09] [PASSED] test_flush
[21:10:09] [PASSED] test_lookup
[21:10:09] [PASSED] test_data
[21:10:09] [PASSED] test_class
[21:10:09] ===================== [PASSED] guc_buf =====================
[21:10:09] =================== guc_dbm (7 subtests) ===================
[21:10:09] [PASSED] test_empty
[21:10:09] [PASSED] test_default
[21:10:09] ======================== test_size  ========================
[21:10:09] [PASSED] 4
[21:10:09] [PASSED] 8
[21:10:09] [PASSED] 32
[21:10:09] [PASSED] 256
[21:10:09] ==================== [PASSED] test_size ====================
[21:10:09] ======================= test_reuse  ========================
[21:10:09] [PASSED] 4
[21:10:09] [PASSED] 8
[21:10:09] [PASSED] 32
[21:10:09] [PASSED] 256
[21:10:09] =================== [PASSED] test_reuse ====================
[21:10:09] =================== test_range_overlap  ====================
[21:10:09] [PASSED] 4
[21:10:09] [PASSED] 8
[21:10:09] [PASSED] 32
[21:10:09] [PASSED] 256
[21:10:09] =============== [PASSED] test_range_overlap ================
[21:10:09] =================== test_range_compact  ====================
[21:10:09] [PASSED] 4
[21:10:09] [PASSED] 8
[21:10:09] [PASSED] 32
[21:10:09] [PASSED] 256
[21:10:09] =============== [PASSED] test_range_compact ================
[21:10:09] ==================== test_range_spare  =====================
[21:10:09] [PASSED] 4
[21:10:09] [PASSED] 8
[21:10:09] [PASSED] 32
[21:10:09] [PASSED] 256
[21:10:09] ================ [PASSED] test_range_spare =================
[21:10:09] ===================== [PASSED] guc_dbm =====================
[21:10:09] =================== guc_idm (6 subtests) ===================
[21:10:09] [PASSED] bad_init
[21:10:09] [PASSED] no_init
[21:10:09] [PASSED] init_fini
[21:10:09] [PASSED] check_used
[21:10:09] [PASSED] check_quota
[21:10:09] [PASSED] check_all
[21:10:09] ===================== [PASSED] guc_idm =====================
[21:10:09] ================== no_relay (3 subtests) ===================
[21:10:09] [PASSED] xe_drops_guc2pf_if_not_ready
[21:10:09] [PASSED] xe_drops_guc2vf_if_not_ready
[21:10:09] [PASSED] xe_rejects_send_if_not_ready
[21:10:09] ==================== [PASSED] no_relay =====================
[21:10:09] ================== pf_relay (14 subtests) ==================
[21:10:09] [PASSED] pf_rejects_guc2pf_too_short
[21:10:09] [PASSED] pf_rejects_guc2pf_too_long
[21:10:09] [PASSED] pf_rejects_guc2pf_no_payload
[21:10:09] [PASSED] pf_fails_no_payload
[21:10:09] [PASSED] pf_fails_bad_origin
[21:10:09] [PASSED] pf_fails_bad_type
[21:10:09] [PASSED] pf_txn_reports_error
[21:10:09] [PASSED] pf_txn_sends_pf2guc
[21:10:09] [PASSED] pf_sends_pf2guc
[21:10:09] [SKIPPED] pf_loopback_nop
[21:10:09] [SKIPPED] pf_loopback_echo
[21:10:09] [SKIPPED] pf_loopback_fail
[21:10:09] [SKIPPED] pf_loopback_busy
[21:10:09] [SKIPPED] pf_loopback_retry
[21:10:09] ==================== [PASSED] pf_relay =====================
[21:10:09] ================== vf_relay (3 subtests) ===================
[21:10:09] [PASSED] vf_rejects_guc2vf_too_short
[21:10:09] [PASSED] vf_rejects_guc2vf_too_long
[21:10:09] [PASSED] vf_rejects_guc2vf_no_payload
[21:10:09] ==================== [PASSED] vf_relay =====================
[21:10:09] ================ pf_gt_config (6 subtests) =================
[21:10:09] [PASSED] fair_contexts_1vf
[21:10:09] [PASSED] fair_doorbells_1vf
[21:10:09] [PASSED] fair_ggtt_1vf
[21:10:09] ====================== fair_contexts  ======================
[21:10:09] [PASSED] 1 VF
[21:10:09] [PASSED] 2 VFs
[21:10:09] [PASSED] 3 VFs
[21:10:09] [PASSED] 4 VFs
[21:10:09] [PASSED] 5 VFs
[21:10:09] [PASSED] 6 VFs
[21:10:09] [PASSED] 7 VFs
[21:10:09] [PASSED] 8 VFs
[21:10:09] [PASSED] 9 VFs
[21:10:09] [PASSED] 10 VFs
[21:10:09] [PASSED] 11 VFs
[21:10:09] [PASSED] 12 VFs
[21:10:09] [PASSED] 13 VFs
[21:10:09] [PASSED] 14 VFs
[21:10:09] [PASSED] 15 VFs
[21:10:09] [PASSED] 16 VFs
[21:10:09] [PASSED] 17 VFs
[21:10:09] [PASSED] 18 VFs
[21:10:09] [PASSED] 19 VFs
[21:10:09] [PASSED] 20 VFs
[21:10:09] [PASSED] 21 VFs
[21:10:09] [PASSED] 22 VFs
[21:10:09] [PASSED] 23 VFs
[21:10:09] [PASSED] 24 VFs
[21:10:09] [PASSED] 25 VFs
[21:10:09] [PASSED] 26 VFs
[21:10:09] [PASSED] 27 VFs
[21:10:09] [PASSED] 28 VFs
[21:10:09] [PASSED] 29 VFs
[21:10:09] [PASSED] 30 VFs
[21:10:09] [PASSED] 31 VFs
[21:10:09] [PASSED] 32 VFs
[21:10:09] [PASSED] 33 VFs
[21:10:09] [PASSED] 34 VFs
[21:10:09] [PASSED] 35 VFs
[21:10:09] [PASSED] 36 VFs
[21:10:09] [PASSED] 37 VFs
[21:10:09] [PASSED] 38 VFs
[21:10:09] [PASSED] 39 VFs
[21:10:09] [PASSED] 40 VFs
[21:10:09] [PASSED] 41 VFs
[21:10:09] [PASSED] 42 VFs
[21:10:09] [PASSED] 43 VFs
[21:10:09] [PASSED] 44 VFs
[21:10:09] [PASSED] 45 VFs
[21:10:09] [PASSED] 46 VFs
[21:10:09] [PASSED] 47 VFs
[21:10:09] [PASSED] 48 VFs
[21:10:09] [PASSED] 49 VFs
[21:10:09] [PASSED] 50 VFs
[21:10:09] [PASSED] 51 VFs
[21:10:09] [PASSED] 52 VFs
[21:10:09] [PASSED] 53 VFs
[21:10:09] [PASSED] 54 VFs
[21:10:09] [PASSED] 55 VFs
[21:10:09] [PASSED] 56 VFs
[21:10:09] [PASSED] 57 VFs
[21:10:09] [PASSED] 58 VFs
[21:10:09] [PASSED] 59 VFs
[21:10:09] [PASSED] 60 VFs
[21:10:09] [PASSED] 61 VFs
[21:10:09] [PASSED] 62 VFs
[21:10:09] [PASSED] 63 VFs
[21:10:09] ================== [PASSED] fair_contexts ==================
[21:10:09] ===================== fair_doorbells  ======================
[21:10:09] [PASSED] 1 VF
[21:10:09] [PASSED] 2 VFs
[21:10:09] [PASSED] 3 VFs
[21:10:09] [PASSED] 4 VFs
[21:10:09] [PASSED] 5 VFs
[21:10:09] [PASSED] 6 VFs
[21:10:09] [PASSED] 7 VFs
[21:10:09] [PASSED] 8 VFs
[21:10:09] [PASSED] 9 VFs
[21:10:09] [PASSED] 10 VFs
[21:10:09] [PASSED] 11 VFs
[21:10:09] [PASSED] 12 VFs
[21:10:09] [PASSED] 13 VFs
[21:10:09] [PASSED] 14 VFs
[21:10:09] [PASSED] 15 VFs
[21:10:09] [PASSED] 16 VFs
[21:10:09] [PASSED] 17 VFs
[21:10:09] [PASSED] 18 VFs
[21:10:09] [PASSED] 19 VFs
[21:10:09] [PASSED] 20 VFs
[21:10:09] [PASSED] 21 VFs
[21:10:09] [PASSED] 22 VFs
[21:10:09] [PASSED] 23 VFs
[21:10:09] [PASSED] 24 VFs
[21:10:09] [PASSED] 25 VFs
[21:10:09] [PASSED] 26 VFs
[21:10:09] [PASSED] 27 VFs
[21:10:09] [PASSED] 28 VFs
[21:10:09] [PASSED] 29 VFs
[21:10:09] [PASSED] 30 VFs
[21:10:09] [PASSED] 31 VFs
[21:10:09] [PASSED] 32 VFs
[21:10:09] [PASSED] 33 VFs
[21:10:09] [PASSED] 34 VFs
[21:10:09] [PASSED] 35 VFs
[21:10:09] [PASSED] 36 VFs
[21:10:09] [PASSED] 37 VFs
[21:10:09] [PASSED] 38 VFs
[21:10:09] [PASSED] 39 VFs
[21:10:09] [PASSED] 40 VFs
[21:10:09] [PASSED] 41 VFs
[21:10:09] [PASSED] 42 VFs
[21:10:09] [PASSED] 43 VFs
[21:10:09] [PASSED] 44 VFs
[21:10:09] [PASSED] 45 VFs
[21:10:09] [PASSED] 46 VFs
[21:10:09] [PASSED] 47 VFs
[21:10:09] [PASSED] 48 VFs
[21:10:09] [PASSED] 49 VFs
[21:10:09] [PASSED] 50 VFs
[21:10:09] [PASSED] 51 VFs
[21:10:09] [PASSED] 52 VFs
[21:10:09] [PASSED] 53 VFs
[21:10:09] [PASSED] 54 VFs
[21:10:09] [PASSED] 55 VFs
[21:10:09] [PASSED] 56 VFs
[21:10:09] [PASSED] 57 VFs
[21:10:09] [PASSED] 58 VFs
[21:10:09] [PASSED] 59 VFs
[21:10:09] [PASSED] 60 VFs
[21:10:09] [PASSED] 61 VFs
[21:10:09] [PASSED] 62 VFs
[21:10:09] [PASSED] 63 VFs
[21:10:09] ================= [PASSED] fair_doorbells ==================
[21:10:09] ======================== fair_ggtt  ========================
[21:10:09] [PASSED] 1 VF
[21:10:09] [PASSED] 2 VFs
[21:10:09] [PASSED] 3 VFs
[21:10:09] [PASSED] 4 VFs
[21:10:09] [PASSED] 5 VFs
[21:10:09] [PASSED] 6 VFs
[21:10:09] [PASSED] 7 VFs
[21:10:09] [PASSED] 8 VFs
[21:10:09] [PASSED] 9 VFs
[21:10:09] [PASSED] 10 VFs
[21:10:09] [PASSED] 11 VFs
[21:10:09] [PASSED] 12 VFs
[21:10:09] [PASSED] 13 VFs
[21:10:09] [PASSED] 14 VFs
[21:10:09] [PASSED] 15 VFs
[21:10:09] [PASSED] 16 VFs
[21:10:09] [PASSED] 17 VFs
[21:10:09] [PASSED] 18 VFs
[21:10:09] [PASSED] 19 VFs
[21:10:09] [PASSED] 20 VFs
[21:10:09] [PASSED] 21 VFs
[21:10:09] [PASSED] 22 VFs
[21:10:09] [PASSED] 23 VFs
[21:10:09] [PASSED] 24 VFs
[21:10:09] [PASSED] 25 VFs
[21:10:09] [PASSED] 26 VFs
[21:10:09] [PASSED] 27 VFs
[21:10:09] [PASSED] 28 VFs
[21:10:09] [PASSED] 29 VFs
[21:10:09] [PASSED] 30 VFs
[21:10:09] [PASSED] 31 VFs
[21:10:09] [PASSED] 32 VFs
[21:10:09] [PASSED] 33 VFs
[21:10:09] [PASSED] 34 VFs
[21:10:09] [PASSED] 35 VFs
[21:10:09] [PASSED] 36 VFs
[21:10:09] [PASSED] 37 VFs
[21:10:09] [PASSED] 38 VFs
[21:10:09] [PASSED] 39 VFs
[21:10:09] [PASSED] 40 VFs
[21:10:09] [PASSED] 41 VFs
[21:10:09] [PASSED] 42 VFs
[21:10:09] [PASSED] 43 VFs
[21:10:09] [PASSED] 44 VFs
[21:10:09] [PASSED] 45 VFs
[21:10:09] [PASSED] 46 VFs
[21:10:09] [PASSED] 47 VFs
[21:10:09] [PASSED] 48 VFs
[21:10:09] [PASSED] 49 VFs
[21:10:09] [PASSED] 50 VFs
[21:10:09] [PASSED] 51 VFs
[21:10:09] [PASSED] 52 VFs
[21:10:09] [PASSED] 53 VFs
[21:10:09] [PASSED] 54 VFs
[21:10:09] [PASSED] 55 VFs
[21:10:09] [PASSED] 56 VFs
[21:10:09] [PASSED] 57 VFs
[21:10:09] [PASSED] 58 VFs
[21:10:09] [PASSED] 59 VFs
[21:10:09] [PASSED] 60 VFs
[21:10:09] [PASSED] 61 VFs
[21:10:09] [PASSED] 62 VFs
[21:10:09] [PASSED] 63 VFs
[21:10:09] ==================== [PASSED] fair_ggtt ====================
[21:10:09] ================== [PASSED] pf_gt_config ===================
[21:10:09] ===================== lmtt (1 subtest) =====================
[21:10:09] ======================== test_ops  =========================
[21:10:09] [PASSED] 2-level
[21:10:09] [PASSED] multi-level
[21:10:09] ==================== [PASSED] test_ops =====================
[21:10:09] ====================== [PASSED] lmtt =======================
[21:10:09] ================= pf_service (11 subtests) =================
[21:10:09] [PASSED] pf_negotiate_any
[21:10:09] [PASSED] pf_negotiate_base_match
[21:10:09] [PASSED] pf_negotiate_base_newer
[21:10:09] [PASSED] pf_negotiate_base_next
[21:10:09] [SKIPPED] pf_negotiate_base_older
[21:10:09] [PASSED] pf_negotiate_base_prev
[21:10:09] [PASSED] pf_negotiate_latest_match
[21:10:09] [PASSED] pf_negotiate_latest_newer
[21:10:09] [PASSED] pf_negotiate_latest_next
[21:10:09] [SKIPPED] pf_negotiate_latest_older
[21:10:09] [SKIPPED] pf_negotiate_latest_prev
[21:10:09] =================== [PASSED] pf_service ====================
[21:10:09] ================= xe_guc_g2g (2 subtests) ==================
[21:10:09] ============== xe_live_guc_g2g_kunit_default  ==============
[21:10:09] ========= [SKIPPED] xe_live_guc_g2g_kunit_default ==========
[21:10:09] ============== xe_live_guc_g2g_kunit_allmem  ===============
[21:10:09] ========== [SKIPPED] xe_live_guc_g2g_kunit_allmem ==========
[21:10:09] =================== [SKIPPED] xe_guc_g2g ===================
[21:10:09] =================== xe_mocs (2 subtests) ===================
[21:10:09] ================ xe_live_mocs_kernel_kunit  ================
[21:10:09] =========== [SKIPPED] xe_live_mocs_kernel_kunit ============
[21:10:09] ================ xe_live_mocs_reset_kunit  =================
[21:10:09] ============ [SKIPPED] xe_live_mocs_reset_kunit ============
[21:10:09] ==================== [SKIPPED] xe_mocs =====================
[21:10:09] ================= xe_migrate (2 subtests) ==================
[21:10:09] ================= xe_migrate_sanity_kunit  =================
[21:10:09] ============ [SKIPPED] xe_migrate_sanity_kunit =============
[21:10:09] ================== xe_validate_ccs_kunit  ==================
[21:10:09] ============= [SKIPPED] xe_validate_ccs_kunit ==============
[21:10:09] =================== [SKIPPED] xe_migrate ===================
[21:10:09] ================== xe_dma_buf (1 subtest) ==================
[21:10:09] ==================== xe_dma_buf_kunit  =====================
[21:10:09] ================ [SKIPPED] xe_dma_buf_kunit ================
[21:10:09] =================== [SKIPPED] xe_dma_buf ===================
[21:10:09] ================= xe_bo_shrink (1 subtest) =================
[21:10:09] =================== xe_bo_shrink_kunit  ====================
[21:10:09] =============== [SKIPPED] xe_bo_shrink_kunit ===============
[21:10:09] ================== [SKIPPED] xe_bo_shrink ==================
[21:10:09] ==================== xe_bo (2 subtests) ====================
[21:10:09] ================== xe_ccs_migrate_kunit  ===================
[21:10:09] ============== [SKIPPED] xe_ccs_migrate_kunit ==============
[21:10:09] ==================== xe_bo_evict_kunit  ====================
[21:10:09] =============== [SKIPPED] xe_bo_evict_kunit ================
[21:10:09] ===================== [SKIPPED] xe_bo ======================
[21:10:09] ==================== args (11 subtests) ====================
[21:10:09] [PASSED] count_args_test
[21:10:09] [PASSED] call_args_example
[21:10:09] [PASSED] call_args_test
[21:10:09] [PASSED] drop_first_arg_example
[21:10:09] [PASSED] drop_first_arg_test
[21:10:09] [PASSED] first_arg_example
[21:10:09] [PASSED] first_arg_test
[21:10:09] [PASSED] last_arg_example
[21:10:09] [PASSED] last_arg_test
[21:10:09] [PASSED] pick_arg_example
[21:10:09] [PASSED] sep_comma_example
[21:10:09] ====================== [PASSED] args =======================
[21:10:09] =================== xe_pci (3 subtests) ====================
[21:10:09] ==================== check_graphics_ip  ====================
[21:10:09] [PASSED] 12.00 Xe_LP
[21:10:09] [PASSED] 12.10 Xe_LP+
[21:10:09] [PASSED] 12.55 Xe_HPG
[21:10:09] [PASSED] 12.60 Xe_HPC
[21:10:09] [PASSED] 12.70 Xe_LPG
[21:10:09] [PASSED] 12.71 Xe_LPG
[21:10:09] [PASSED] 12.74 Xe_LPG+
[21:10:09] [PASSED] 20.01 Xe2_HPG
[21:10:09] [PASSED] 20.02 Xe2_HPG
[21:10:09] [PASSED] 20.04 Xe2_LPG
[21:10:09] [PASSED] 30.00 Xe3_LPG
[21:10:09] [PASSED] 30.01 Xe3_LPG
[21:10:09] [PASSED] 30.03 Xe3_LPG
[21:10:09] [PASSED] 30.04 Xe3_LPG
[21:10:09] [PASSED] 30.05 Xe3_LPG
[21:10:09] [PASSED] 35.11 Xe3p_XPC
[21:10:09] ================ [PASSED] check_graphics_ip ================
[21:10:09] ===================== check_media_ip  ======================
[21:10:09] [PASSED] 12.00 Xe_M
[21:10:09] [PASSED] 12.55 Xe_HPM
[21:10:09] [PASSED] 13.00 Xe_LPM+
[21:10:09] [PASSED] 13.01 Xe2_HPM
[21:10:09] [PASSED] 20.00 Xe2_LPM
[21:10:09] [PASSED] 30.00 Xe3_LPM
[21:10:09] [PASSED] 30.02 Xe3_LPM
[21:10:09] [PASSED] 35.00 Xe3p_LPM
[21:10:09] [PASSED] 35.03 Xe3p_HPM
[21:10:09] ================= [PASSED] check_media_ip ==================
[21:10:09] =================== check_platform_desc  ===================
[21:10:09] [PASSED] 0x9A60 (TIGERLAKE)
[21:10:09] [PASSED] 0x9A68 (TIGERLAKE)
[21:10:09] [PASSED] 0x9A70 (TIGERLAKE)
[21:10:09] [PASSED] 0x9A40 (TIGERLAKE)
[21:10:09] [PASSED] 0x9A49 (TIGERLAKE)
[21:10:09] [PASSED] 0x9A59 (TIGERLAKE)
[21:10:09] [PASSED] 0x9A78 (TIGERLAKE)
[21:10:09] [PASSED] 0x9AC0 (TIGERLAKE)
[21:10:09] [PASSED] 0x9AC9 (TIGERLAKE)
[21:10:09] [PASSED] 0x9AD9 (TIGERLAKE)
[21:10:09] [PASSED] 0x9AF8 (TIGERLAKE)
[21:10:09] [PASSED] 0x4C80 (ROCKETLAKE)
[21:10:09] [PASSED] 0x4C8A (ROCKETLAKE)
[21:10:09] [PASSED] 0x4C8B (ROCKETLAKE)
[21:10:09] [PASSED] 0x4C8C (ROCKETLAKE)
[21:10:09] [PASSED] 0x4C90 (ROCKETLAKE)
[21:10:09] [PASSED] 0x4C9A (ROCKETLAKE)
[21:10:09] [PASSED] 0x4680 (ALDERLAKE_S)
[21:10:09] [PASSED] 0x4682 (ALDERLAKE_S)
[21:10:09] [PASSED] 0x4688 (ALDERLAKE_S)
[21:10:09] [PASSED] 0x468A (ALDERLAKE_S)
[21:10:09] [PASSED] 0x468B (ALDERLAKE_S)
[21:10:09] [PASSED] 0x4690 (ALDERLAKE_S)
[21:10:09] [PASSED] 0x4692 (ALDERLAKE_S)
[21:10:09] [PASSED] 0x4693 (ALDERLAKE_S)
[21:10:09] [PASSED] 0x46A0 (ALDERLAKE_P)
[21:10:09] [PASSED] 0x46A1 (ALDERLAKE_P)
[21:10:09] [PASSED] 0x46A2 (ALDERLAKE_P)
[21:10:09] [PASSED] 0x46A3 (ALDERLAKE_P)
[21:10:09] [PASSED] 0x46A6 (ALDERLAKE_P)
[21:10:09] [PASSED] 0x46A8 (ALDERLAKE_P)
[21:10:09] [PASSED] 0x46AA (ALDERLAKE_P)
[21:10:09] [PASSED] 0x462A (ALDERLAKE_P)
[21:10:09] [PASSED] 0x4626 (ALDERLAKE_P)
[21:10:09] [PASSED] 0x4628 (ALDERLAKE_P)
[21:10:09] [PASSED] 0x46B0 (ALDERLAKE_P)
stty: 'standard input': Inappropriate ioctl for device
[21:10:09] [PASSED] 0x46B1 (ALDERLAKE_P)
[21:10:09] [PASSED] 0x46B2 (ALDERLAKE_P)
[21:10:09] [PASSED] 0x46B3 (ALDERLAKE_P)
[21:10:09] [PASSED] 0x46C0 (ALDERLAKE_P)
[21:10:09] [PASSED] 0x46C1 (ALDERLAKE_P)
[21:10:09] [PASSED] 0x46C2 (ALDERLAKE_P)
[21:10:09] [PASSED] 0x46C3 (ALDERLAKE_P)
[21:10:09] [PASSED] 0x46D0 (ALDERLAKE_N)
[21:10:09] [PASSED] 0x46D1 (ALDERLAKE_N)
[21:10:09] [PASSED] 0x46D2 (ALDERLAKE_N)
[21:10:09] [PASSED] 0x46D3 (ALDERLAKE_N)
[21:10:09] [PASSED] 0x46D4 (ALDERLAKE_N)
[21:10:09] [PASSED] 0xA721 (ALDERLAKE_P)
[21:10:09] [PASSED] 0xA7A1 (ALDERLAKE_P)
[21:10:09] [PASSED] 0xA7A9 (ALDERLAKE_P)
[21:10:09] [PASSED] 0xA7AC (ALDERLAKE_P)
[21:10:09] [PASSED] 0xA7AD (ALDERLAKE_P)
[21:10:09] [PASSED] 0xA720 (ALDERLAKE_P)
[21:10:09] [PASSED] 0xA7A0 (ALDERLAKE_P)
[21:10:09] [PASSED] 0xA7A8 (ALDERLAKE_P)
[21:10:09] [PASSED] 0xA7AA (ALDERLAKE_P)
[21:10:09] [PASSED] 0xA7AB (ALDERLAKE_P)
[21:10:09] [PASSED] 0xA780 (ALDERLAKE_S)
[21:10:09] [PASSED] 0xA781 (ALDERLAKE_S)
[21:10:09] [PASSED] 0xA782 (ALDERLAKE_S)
[21:10:09] [PASSED] 0xA783 (ALDERLAKE_S)
[21:10:09] [PASSED] 0xA788 (ALDERLAKE_S)
[21:10:09] [PASSED] 0xA789 (ALDERLAKE_S)
[21:10:09] [PASSED] 0xA78A (ALDERLAKE_S)
[21:10:09] [PASSED] 0xA78B (ALDERLAKE_S)
[21:10:09] [PASSED] 0x4905 (DG1)
[21:10:09] [PASSED] 0x4906 (DG1)
[21:10:09] [PASSED] 0x4907 (DG1)
[21:10:09] [PASSED] 0x4908 (DG1)
[21:10:09] [PASSED] 0x4909 (DG1)
[21:10:09] [PASSED] 0x56C0 (DG2)
[21:10:09] [PASSED] 0x56C2 (DG2)
[21:10:09] [PASSED] 0x56C1 (DG2)
[21:10:09] [PASSED] 0x7D51 (METEORLAKE)
[21:10:09] [PASSED] 0x7DD1 (METEORLAKE)
[21:10:09] [PASSED] 0x7D41 (METEORLAKE)
[21:10:09] [PASSED] 0x7D67 (METEORLAKE)
[21:10:09] [PASSED] 0xB640 (METEORLAKE)
[21:10:09] [PASSED] 0x56A0 (DG2)
[21:10:09] [PASSED] 0x56A1 (DG2)
[21:10:09] [PASSED] 0x56A2 (DG2)
[21:10:09] [PASSED] 0x56BE (DG2)
[21:10:09] [PASSED] 0x56BF (DG2)
[21:10:09] [PASSED] 0x5690 (DG2)
[21:10:09] [PASSED] 0x5691 (DG2)
[21:10:09] [PASSED] 0x5692 (DG2)
[21:10:09] [PASSED] 0x56A5 (DG2)
[21:10:09] [PASSED] 0x56A6 (DG2)
[21:10:09] [PASSED] 0x56B0 (DG2)
[21:10:09] [PASSED] 0x56B1 (DG2)
[21:10:09] [PASSED] 0x56BA (DG2)
[21:10:09] [PASSED] 0x56BB (DG2)
[21:10:09] [PASSED] 0x56BC (DG2)
[21:10:09] [PASSED] 0x56BD (DG2)
[21:10:09] [PASSED] 0x5693 (DG2)
[21:10:09] [PASSED] 0x5694 (DG2)
[21:10:09] [PASSED] 0x5695 (DG2)
[21:10:09] [PASSED] 0x56A3 (DG2)
[21:10:09] [PASSED] 0x56A4 (DG2)
[21:10:09] [PASSED] 0x56B2 (DG2)
[21:10:09] [PASSED] 0x56B3 (DG2)
[21:10:09] [PASSED] 0x5696 (DG2)
[21:10:09] [PASSED] 0x5697 (DG2)
[21:10:09] [PASSED] 0xB69 (PVC)
[21:10:09] [PASSED] 0xB6E (PVC)
[21:10:09] [PASSED] 0xBD4 (PVC)
[21:10:09] [PASSED] 0xBD5 (PVC)
[21:10:09] [PASSED] 0xBD6 (PVC)
[21:10:09] [PASSED] 0xBD7 (PVC)
[21:10:09] [PASSED] 0xBD8 (PVC)
[21:10:09] [PASSED] 0xBD9 (PVC)
[21:10:09] [PASSED] 0xBDA (PVC)
[21:10:09] [PASSED] 0xBDB (PVC)
[21:10:09] [PASSED] 0xBE0 (PVC)
[21:10:09] [PASSED] 0xBE1 (PVC)
[21:10:09] [PASSED] 0xBE5 (PVC)
[21:10:09] [PASSED] 0x7D40 (METEORLAKE)
[21:10:09] [PASSED] 0x7D45 (METEORLAKE)
[21:10:09] [PASSED] 0x7D55 (METEORLAKE)
[21:10:09] [PASSED] 0x7D60 (METEORLAKE)
[21:10:09] [PASSED] 0x7DD5 (METEORLAKE)
[21:10:09] [PASSED] 0x6420 (LUNARLAKE)
[21:10:09] [PASSED] 0x64A0 (LUNARLAKE)
[21:10:09] [PASSED] 0x64B0 (LUNARLAKE)
[21:10:09] [PASSED] 0xE202 (BATTLEMAGE)
[21:10:09] [PASSED] 0xE209 (BATTLEMAGE)
[21:10:09] [PASSED] 0xE20B (BATTLEMAGE)
[21:10:09] [PASSED] 0xE20C (BATTLEMAGE)
[21:10:09] [PASSED] 0xE20D (BATTLEMAGE)
[21:10:09] [PASSED] 0xE210 (BATTLEMAGE)
[21:10:09] [PASSED] 0xE211 (BATTLEMAGE)
[21:10:09] [PASSED] 0xE212 (BATTLEMAGE)
[21:10:09] [PASSED] 0xE216 (BATTLEMAGE)
[21:10:09] [PASSED] 0xE220 (BATTLEMAGE)
[21:10:09] [PASSED] 0xE221 (BATTLEMAGE)
[21:10:09] [PASSED] 0xE222 (BATTLEMAGE)
[21:10:09] [PASSED] 0xE223 (BATTLEMAGE)
[21:10:09] [PASSED] 0xB080 (PANTHERLAKE)
[21:10:09] [PASSED] 0xB081 (PANTHERLAKE)
[21:10:09] [PASSED] 0xB082 (PANTHERLAKE)
[21:10:09] [PASSED] 0xB083 (PANTHERLAKE)
[21:10:09] [PASSED] 0xB084 (PANTHERLAKE)
[21:10:09] [PASSED] 0xB085 (PANTHERLAKE)
[21:10:09] [PASSED] 0xB086 (PANTHERLAKE)
[21:10:09] [PASSED] 0xB087 (PANTHERLAKE)
[21:10:09] [PASSED] 0xB08F (PANTHERLAKE)
[21:10:09] [PASSED] 0xB090 (PANTHERLAKE)
[21:10:09] [PASSED] 0xB0A0 (PANTHERLAKE)
[21:10:09] [PASSED] 0xB0B0 (PANTHERLAKE)
[21:10:09] [PASSED] 0xD740 (NOVALAKE_S)
[21:10:09] [PASSED] 0xD741 (NOVALAKE_S)
[21:10:09] [PASSED] 0xD742 (NOVALAKE_S)
[21:10:09] [PASSED] 0xD743 (NOVALAKE_S)
[21:10:09] [PASSED] 0xD744 (NOVALAKE_S)
[21:10:09] [PASSED] 0xD745 (NOVALAKE_S)
[21:10:09] [PASSED] 0x674C (CRESCENTISLAND)
[21:10:09] [PASSED] 0xFD80 (PANTHERLAKE)
[21:10:09] [PASSED] 0xFD81 (PANTHERLAKE)
[21:10:09] =============== [PASSED] check_platform_desc ===============
[21:10:09] ===================== [PASSED] xe_pci ======================
[21:10:09] =================== xe_rtp (2 subtests) ====================
[21:10:09] =============== xe_rtp_process_to_sr_tests  ================
[21:10:09] [PASSED] coalesce-same-reg
[21:10:09] [PASSED] no-match-no-add
[21:10:09] [PASSED] match-or
[21:10:09] [PASSED] match-or-xfail
[21:10:09] [PASSED] no-match-no-add-multiple-rules
[21:10:09] [PASSED] two-regs-two-entries
[21:10:09] [PASSED] clr-one-set-other
[21:10:09] [PASSED] set-field
[21:10:09] [PASSED] conflict-duplicate
[21:10:09] [PASSED] conflict-not-disjoint
[21:10:09] [PASSED] conflict-reg-type
[21:10:09] =========== [PASSED] xe_rtp_process_to_sr_tests ============
[21:10:09] ================== xe_rtp_process_tests  ===================
[21:10:09] [PASSED] active1
[21:10:09] [PASSED] active2
[21:10:09] [PASSED] active-inactive
[21:10:09] [PASSED] inactive-active
[21:10:09] [PASSED] inactive-1st_or_active-inactive
[21:10:09] [PASSED] inactive-2nd_or_active-inactive
[21:10:09] [PASSED] inactive-last_or_active-inactive
[21:10:09] [PASSED] inactive-no_or_active-inactive
[21:10:09] ============== [PASSED] xe_rtp_process_tests ===============
[21:10:09] ===================== [PASSED] xe_rtp ======================
[21:10:09] ==================== xe_wa (1 subtest) =====================
[21:10:09] ======================== xe_wa_gt  =========================
[21:10:09] [PASSED] TIGERLAKE B0
[21:10:09] [PASSED] DG1 A0
[21:10:09] [PASSED] DG1 B0
[21:10:09] [PASSED] ALDERLAKE_S A0
[21:10:09] [PASSED] ALDERLAKE_S B0
[21:10:09] [PASSED] ALDERLAKE_S C0
[21:10:09] [PASSED] ALDERLAKE_S D0
[21:10:09] [PASSED] ALDERLAKE_P A0
[21:10:09] [PASSED] ALDERLAKE_P B0
[21:10:09] [PASSED] ALDERLAKE_P C0
[21:10:09] [PASSED] ALDERLAKE_S RPLS D0
[21:10:09] [PASSED] ALDERLAKE_P RPLU E0
[21:10:09] [PASSED] DG2 G10 C0
[21:10:09] [PASSED] DG2 G11 B1
[21:10:09] [PASSED] DG2 G12 A1
[21:10:09] [PASSED] METEORLAKE 12.70(Xe_LPG) A0 13.00(Xe_LPM+) A0
[21:10:09] [PASSED] METEORLAKE 12.71(Xe_LPG) A0 13.00(Xe_LPM+) A0
[21:10:09] [PASSED] METEORLAKE 12.74(Xe_LPG+) A0 13.00(Xe_LPM+) A0
[21:10:09] [PASSED] LUNARLAKE 20.04(Xe2_LPG) A0 20.00(Xe2_LPM) A0
[21:10:09] [PASSED] LUNARLAKE 20.04(Xe2_LPG) B0 20.00(Xe2_LPM) A0
[21:10:09] [PASSED] BATTLEMAGE 20.01(Xe2_HPG) A0 13.01(Xe2_HPM) A1
[21:10:09] [PASSED] PANTHERLAKE 30.00(Xe3_LPG) A0 30.00(Xe3_LPM) A0
[21:10:09] ==================== [PASSED] xe_wa_gt =====================
[21:10:09] ====================== [PASSED] xe_wa ======================
[21:10:09] ============================================================
[21:10:09] Testing complete. Ran 510 tests: passed: 492, skipped: 18
[21:10:09] Elapsed time: 35.523s total, 4.127s configuring, 30.878s building, 0.474s running

+ /kernel/tools/testing/kunit/kunit.py run --kunitconfig /kernel/drivers/gpu/drm/tests/.kunitconfig
[21:10:09] Configuring KUnit Kernel ...
Regenerating .config ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
[21:10:11] Building KUnit Kernel ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
Building with:
$ make all compile_commands.json scripts_gdb ARCH=um O=.kunit --jobs=48
[21:10:36] Starting KUnit Kernel (1/1)...
[21:10:36] ============================================================
Running tests with:
$ .kunit/linux kunit.enable=1 mem=1G console=tty kunit_shutdown=halt
[21:10:36] ============ drm_test_pick_cmdline (2 subtests) ============
[21:10:36] [PASSED] drm_test_pick_cmdline_res_1920_1080_60
[21:10:36] =============== drm_test_pick_cmdline_named  ===============
[21:10:36] [PASSED] NTSC
[21:10:36] [PASSED] NTSC-J
[21:10:36] [PASSED] PAL
[21:10:36] [PASSED] PAL-M
[21:10:36] =========== [PASSED] drm_test_pick_cmdline_named ===========
[21:10:36] ============== [PASSED] drm_test_pick_cmdline ==============
[21:10:36] == drm_test_atomic_get_connector_for_encoder (1 subtest) ===
[21:10:36] [PASSED] drm_test_drm_atomic_get_connector_for_encoder
[21:10:36] ==== [PASSED] drm_test_atomic_get_connector_for_encoder ====
[21:10:36] =========== drm_validate_clone_mode (2 subtests) ===========
[21:10:36] ============== drm_test_check_in_clone_mode  ===============
[21:10:36] [PASSED] in_clone_mode
[21:10:36] [PASSED] not_in_clone_mode
[21:10:36] ========== [PASSED] drm_test_check_in_clone_mode ===========
[21:10:36] =============== drm_test_check_valid_clones  ===============
[21:10:36] [PASSED] not_in_clone_mode
[21:10:36] [PASSED] valid_clone
[21:10:36] [PASSED] invalid_clone
[21:10:36] =========== [PASSED] drm_test_check_valid_clones ===========
[21:10:36] ============= [PASSED] drm_validate_clone_mode =============
[21:10:36] ============= drm_validate_modeset (1 subtest) =============
[21:10:36] [PASSED] drm_test_check_connector_changed_modeset
[21:10:36] ============== [PASSED] drm_validate_modeset ===============
[21:10:36] ====== drm_test_bridge_get_current_state (2 subtests) ======
[21:10:36] [PASSED] drm_test_drm_bridge_get_current_state_atomic
[21:10:36] [PASSED] drm_test_drm_bridge_get_current_state_legacy
[21:10:36] ======== [PASSED] drm_test_bridge_get_current_state ========
[21:10:36] ====== drm_test_bridge_helper_reset_crtc (3 subtests) ======
[21:10:36] [PASSED] drm_test_drm_bridge_helper_reset_crtc_atomic
[21:10:36] [PASSED] drm_test_drm_bridge_helper_reset_crtc_atomic_disabled
[21:10:36] [PASSED] drm_test_drm_bridge_helper_reset_crtc_legacy
[21:10:36] ======== [PASSED] drm_test_bridge_helper_reset_crtc ========
[21:10:36] ============== drm_bridge_alloc (2 subtests) ===============
[21:10:36] [PASSED] drm_test_drm_bridge_alloc_basic
[21:10:36] [PASSED] drm_test_drm_bridge_alloc_get_put
[21:10:36] ================ [PASSED] drm_bridge_alloc =================
[21:10:36] ================== drm_buddy (8 subtests) ==================
[21:10:36] [PASSED] drm_test_buddy_alloc_limit
[21:10:36] [PASSED] drm_test_buddy_alloc_optimistic
[21:10:36] [PASSED] drm_test_buddy_alloc_pessimistic
[21:10:36] [PASSED] drm_test_buddy_alloc_pathological
[21:10:36] [PASSED] drm_test_buddy_alloc_contiguous
[21:10:36] [PASSED] drm_test_buddy_alloc_clear
[21:10:36] [PASSED] drm_test_buddy_alloc_range_bias
[21:10:36] [PASSED] drm_test_buddy_fragmentation_performance
[21:10:36] ==================== [PASSED] drm_buddy ====================
[21:10:36] ============= drm_cmdline_parser (40 subtests) =============
[21:10:36] [PASSED] drm_test_cmdline_force_d_only
[21:10:36] [PASSED] drm_test_cmdline_force_D_only_dvi
[21:10:36] [PASSED] drm_test_cmdline_force_D_only_hdmi
[21:10:36] [PASSED] drm_test_cmdline_force_D_only_not_digital
[21:10:36] [PASSED] drm_test_cmdline_force_e_only
[21:10:36] [PASSED] drm_test_cmdline_res
[21:10:36] [PASSED] drm_test_cmdline_res_vesa
[21:10:36] [PASSED] drm_test_cmdline_res_vesa_rblank
[21:10:36] [PASSED] drm_test_cmdline_res_rblank
[21:10:36] [PASSED] drm_test_cmdline_res_bpp
[21:10:36] [PASSED] drm_test_cmdline_res_refresh
[21:10:36] [PASSED] drm_test_cmdline_res_bpp_refresh
[21:10:36] [PASSED] drm_test_cmdline_res_bpp_refresh_interlaced
[21:10:36] [PASSED] drm_test_cmdline_res_bpp_refresh_margins
[21:10:36] [PASSED] drm_test_cmdline_res_bpp_refresh_force_off
[21:10:36] [PASSED] drm_test_cmdline_res_bpp_refresh_force_on
[21:10:36] [PASSED] drm_test_cmdline_res_bpp_refresh_force_on_analog
[21:10:36] [PASSED] drm_test_cmdline_res_bpp_refresh_force_on_digital
[21:10:36] [PASSED] drm_test_cmdline_res_bpp_refresh_interlaced_margins_force_on
[21:10:36] [PASSED] drm_test_cmdline_res_margins_force_on
[21:10:36] [PASSED] drm_test_cmdline_res_vesa_margins
[21:10:36] [PASSED] drm_test_cmdline_name
[21:10:36] [PASSED] drm_test_cmdline_name_bpp
[21:10:36] [PASSED] drm_test_cmdline_name_option
[21:10:36] [PASSED] drm_test_cmdline_name_bpp_option
[21:10:36] [PASSED] drm_test_cmdline_rotate_0
[21:10:36] [PASSED] drm_test_cmdline_rotate_90
[21:10:36] [PASSED] drm_test_cmdline_rotate_180
[21:10:36] [PASSED] drm_test_cmdline_rotate_270
[21:10:36] [PASSED] drm_test_cmdline_hmirror
[21:10:36] [PASSED] drm_test_cmdline_vmirror
[21:10:36] [PASSED] drm_test_cmdline_margin_options
[21:10:36] [PASSED] drm_test_cmdline_multiple_options
[21:10:36] [PASSED] drm_test_cmdline_bpp_extra_and_option
[21:10:36] [PASSED] drm_test_cmdline_extra_and_option
[21:10:36] [PASSED] drm_test_cmdline_freestanding_options
[21:10:36] [PASSED] drm_test_cmdline_freestanding_force_e_and_options
[21:10:36] [PASSED] drm_test_cmdline_panel_orientation
[21:10:36] ================ drm_test_cmdline_invalid  =================
[21:10:36] [PASSED] margin_only
[21:10:36] [PASSED] interlace_only
[21:10:36] [PASSED] res_missing_x
[21:10:36] [PASSED] res_missing_y
[21:10:36] [PASSED] res_bad_y
[21:10:36] [PASSED] res_missing_y_bpp
[21:10:36] [PASSED] res_bad_bpp
[21:10:36] [PASSED] res_bad_refresh
[21:10:36] [PASSED] res_bpp_refresh_force_on_off
[21:10:36] [PASSED] res_invalid_mode
[21:10:36] [PASSED] res_bpp_wrong_place_mode
[21:10:36] [PASSED] name_bpp_refresh
[21:10:36] [PASSED] name_refresh
[21:10:36] [PASSED] name_refresh_wrong_mode
[21:10:36] [PASSED] name_refresh_invalid_mode
[21:10:36] [PASSED] rotate_multiple
[21:10:36] [PASSED] rotate_invalid_val
[21:10:36] [PASSED] rotate_truncated
[21:10:36] [PASSED] invalid_option
[21:10:36] [PASSED] invalid_tv_option
[21:10:36] [PASSED] truncated_tv_option
[21:10:36] ============ [PASSED] drm_test_cmdline_invalid =============
[21:10:36] =============== drm_test_cmdline_tv_options  ===============
[21:10:36] [PASSED] NTSC
[21:10:36] [PASSED] NTSC_443
[21:10:36] [PASSED] NTSC_J
[21:10:36] [PASSED] PAL
[21:10:36] [PASSED] PAL_M
[21:10:36] [PASSED] PAL_N
[21:10:36] [PASSED] SECAM
[21:10:36] [PASSED] MONO_525
[21:10:36] [PASSED] MONO_625
[21:10:36] =========== [PASSED] drm_test_cmdline_tv_options ===========
[21:10:36] =============== [PASSED] drm_cmdline_parser ================
[21:10:36] ========== drmm_connector_hdmi_init (20 subtests) ==========
[21:10:36] [PASSED] drm_test_connector_hdmi_init_valid
[21:10:36] [PASSED] drm_test_connector_hdmi_init_bpc_8
[21:10:36] [PASSED] drm_test_connector_hdmi_init_bpc_10
[21:10:36] [PASSED] drm_test_connector_hdmi_init_bpc_12
[21:10:36] [PASSED] drm_test_connector_hdmi_init_bpc_invalid
[21:10:36] [PASSED] drm_test_connector_hdmi_init_bpc_null
[21:10:36] [PASSED] drm_test_connector_hdmi_init_formats_empty
[21:10:36] [PASSED] drm_test_connector_hdmi_init_formats_no_rgb
[21:10:36] === drm_test_connector_hdmi_init_formats_yuv420_allowed  ===
[21:10:36] [PASSED] supported_formats=0x9 yuv420_allowed=1
[21:10:36] [PASSED] supported_formats=0x9 yuv420_allowed=0
[21:10:36] [PASSED] supported_formats=0x3 yuv420_allowed=1
[21:10:36] [PASSED] supported_formats=0x3 yuv420_allowed=0
[21:10:36] === [PASSED] drm_test_connector_hdmi_init_formats_yuv420_allowed ===
[21:10:36] [PASSED] drm_test_connector_hdmi_init_null_ddc
[21:10:36] [PASSED] drm_test_connector_hdmi_init_null_product
[21:10:36] [PASSED] drm_test_connector_hdmi_init_null_vendor
[21:10:36] [PASSED] drm_test_connector_hdmi_init_product_length_exact
[21:10:36] [PASSED] drm_test_connector_hdmi_init_product_length_too_long
[21:10:36] [PASSED] drm_test_connector_hdmi_init_product_valid
[21:10:36] [PASSED] drm_test_connector_hdmi_init_vendor_length_exact
[21:10:36] [PASSED] drm_test_connector_hdmi_init_vendor_length_too_long
[21:10:36] [PASSED] drm_test_connector_hdmi_init_vendor_valid
[21:10:36] ========= drm_test_connector_hdmi_init_type_valid  =========
[21:10:36] [PASSED] HDMI-A
[21:10:36] [PASSED] HDMI-B
[21:10:36] ===== [PASSED] drm_test_connector_hdmi_init_type_valid =====
[21:10:36] ======== drm_test_connector_hdmi_init_type_invalid  ========
[21:10:36] [PASSED] Unknown
[21:10:36] [PASSED] VGA
[21:10:36] [PASSED] DVI-I
[21:10:36] [PASSED] DVI-D
[21:10:36] [PASSED] DVI-A
[21:10:36] [PASSED] Composite
[21:10:36] [PASSED] SVIDEO
[21:10:36] [PASSED] LVDS
[21:10:36] [PASSED] Component
[21:10:36] [PASSED] DIN
[21:10:36] [PASSED] DP
[21:10:36] [PASSED] TV
[21:10:36] [PASSED] eDP
[21:10:36] [PASSED] Virtual
[21:10:36] [PASSED] DSI
[21:10:36] [PASSED] DPI
[21:10:36] [PASSED] Writeback
[21:10:36] [PASSED] SPI
[21:10:36] [PASSED] USB
[21:10:36] ==== [PASSED] drm_test_connector_hdmi_init_type_invalid ====
[21:10:36] ============ [PASSED] drmm_connector_hdmi_init =============
[21:10:36] ============= drmm_connector_init (3 subtests) =============
[21:10:36] [PASSED] drm_test_drmm_connector_init
[21:10:36] [PASSED] drm_test_drmm_connector_init_null_ddc
[21:10:36] ========= drm_test_drmm_connector_init_type_valid  =========
[21:10:36] [PASSED] Unknown
[21:10:36] [PASSED] VGA
[21:10:36] [PASSED] DVI-I
[21:10:36] [PASSED] DVI-D
[21:10:36] [PASSED] DVI-A
[21:10:36] [PASSED] Composite
[21:10:36] [PASSED] SVIDEO
[21:10:36] [PASSED] LVDS
[21:10:36] [PASSED] Component
[21:10:36] [PASSED] DIN
[21:10:36] [PASSED] DP
[21:10:36] [PASSED] HDMI-A
[21:10:36] [PASSED] HDMI-B
[21:10:36] [PASSED] TV
[21:10:36] [PASSED] eDP
[21:10:36] [PASSED] Virtual
[21:10:36] [PASSED] DSI
[21:10:36] [PASSED] DPI
[21:10:36] [PASSED] Writeback
[21:10:36] [PASSED] SPI
[21:10:36] [PASSED] USB
[21:10:36] ===== [PASSED] drm_test_drmm_connector_init_type_valid =====
[21:10:36] =============== [PASSED] drmm_connector_init ===============
[21:10:36] ========= drm_connector_dynamic_init (6 subtests) ==========
[21:10:36] [PASSED] drm_test_drm_connector_dynamic_init
[21:10:36] [PASSED] drm_test_drm_connector_dynamic_init_null_ddc
[21:10:36] [PASSED] drm_test_drm_connector_dynamic_init_not_added
[21:10:36] [PASSED] drm_test_drm_connector_dynamic_init_properties
[21:10:36] ===== drm_test_drm_connector_dynamic_init_type_valid  ======
[21:10:36] [PASSED] Unknown
[21:10:36] [PASSED] VGA
[21:10:36] [PASSED] DVI-I
[21:10:36] [PASSED] DVI-D
[21:10:36] [PASSED] DVI-A
[21:10:36] [PASSED] Composite
[21:10:36] [PASSED] SVIDEO
[21:10:36] [PASSED] LVDS
[21:10:36] [PASSED] Component
[21:10:36] [PASSED] DIN
[21:10:36] [PASSED] DP
[21:10:36] [PASSED] HDMI-A
[21:10:36] [PASSED] HDMI-B
[21:10:36] [PASSED] TV
[21:10:36] [PASSED] eDP
[21:10:36] [PASSED] Virtual
[21:10:36] [PASSED] DSI
[21:10:36] [PASSED] DPI
[21:10:36] [PASSED] Writeback
[21:10:36] [PASSED] SPI
[21:10:36] [PASSED] USB
[21:10:36] = [PASSED] drm_test_drm_connector_dynamic_init_type_valid ==
[21:10:36] ======== drm_test_drm_connector_dynamic_init_name  =========
[21:10:36] [PASSED] Unknown
[21:10:36] [PASSED] VGA
[21:10:36] [PASSED] DVI-I
[21:10:36] [PASSED] DVI-D
[21:10:36] [PASSED] DVI-A
[21:10:36] [PASSED] Composite
[21:10:36] [PASSED] SVIDEO
[21:10:36] [PASSED] LVDS
[21:10:36] [PASSED] Component
[21:10:36] [PASSED] DIN
[21:10:36] [PASSED] DP
[21:10:36] [PASSED] HDMI-A
[21:10:36] [PASSED] HDMI-B
[21:10:36] [PASSED] TV
[21:10:36] [PASSED] eDP
[21:10:36] [PASSED] Virtual
[21:10:36] [PASSED] DSI
[21:10:36] [PASSED] DPI
[21:10:36] [PASSED] Writeback
[21:10:36] [PASSED] SPI
[21:10:36] [PASSED] USB
[21:10:36] ==== [PASSED] drm_test_drm_connector_dynamic_init_name =====
[21:10:36] =========== [PASSED] drm_connector_dynamic_init ============
[21:10:36] ==== drm_connector_dynamic_register_early (4 subtests) =====
[21:10:36] [PASSED] drm_test_drm_connector_dynamic_register_early_on_list
[21:10:36] [PASSED] drm_test_drm_connector_dynamic_register_early_defer
[21:10:36] [PASSED] drm_test_drm_connector_dynamic_register_early_no_init
[21:10:36] [PASSED] drm_test_drm_connector_dynamic_register_early_no_mode_object
[21:10:36] ====== [PASSED] drm_connector_dynamic_register_early =======
[21:10:36] ======= drm_connector_dynamic_register (7 subtests) ========
[21:10:36] [PASSED] drm_test_drm_connector_dynamic_register_on_list
[21:10:36] [PASSED] drm_test_drm_connector_dynamic_register_no_defer
[21:10:36] [PASSED] drm_test_drm_connector_dynamic_register_no_init
[21:10:36] [PASSED] drm_test_drm_connector_dynamic_register_mode_object
[21:10:36] [PASSED] drm_test_drm_connector_dynamic_register_sysfs
[21:10:36] [PASSED] drm_test_drm_connector_dynamic_register_sysfs_name
[21:10:36] [PASSED] drm_test_drm_connector_dynamic_register_debugfs
[21:10:36] ========= [PASSED] drm_connector_dynamic_register ==========
[21:10:36] = drm_connector_attach_broadcast_rgb_property (2 subtests) =
[21:10:36] [PASSED] drm_test_drm_connector_attach_broadcast_rgb_property
[21:10:36] [PASSED] drm_test_drm_connector_attach_broadcast_rgb_property_hdmi_connector
[21:10:36] === [PASSED] drm_connector_attach_broadcast_rgb_property ===
[21:10:36] ========== drm_get_tv_mode_from_name (2 subtests) ==========
[21:10:36] ========== drm_test_get_tv_mode_from_name_valid  ===========
[21:10:36] [PASSED] NTSC
[21:10:36] [PASSED] NTSC-443
[21:10:36] [PASSED] NTSC-J
[21:10:36] [PASSED] PAL
[21:10:36] [PASSED] PAL-M
[21:10:36] [PASSED] PAL-N
[21:10:36] [PASSED] SECAM
[21:10:36] [PASSED] Mono
[21:10:36] ====== [PASSED] drm_test_get_tv_mode_from_name_valid =======
[21:10:36] [PASSED] drm_test_get_tv_mode_from_name_truncated
[21:10:36] ============ [PASSED] drm_get_tv_mode_from_name ============
[21:10:36] = drm_test_connector_hdmi_compute_mode_clock (12 subtests) =
[21:10:36] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb
[21:10:36] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_10bpc
[21:10:36] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_10bpc_vic_1
[21:10:36] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_12bpc
[21:10:36] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_12bpc_vic_1
[21:10:36] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_double
[21:10:36] = drm_test_connector_hdmi_compute_mode_clock_yuv420_valid  =
[21:10:36] [PASSED] VIC 96
[21:10:36] [PASSED] VIC 97
[21:10:36] [PASSED] VIC 101
[21:10:36] [PASSED] VIC 102
[21:10:36] [PASSED] VIC 106
[21:10:36] [PASSED] VIC 107
[21:10:36] === [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv420_valid ===
[21:10:36] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv420_10_bpc
[21:10:36] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv420_12_bpc
[21:10:36] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv422_8_bpc
[21:10:36] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv422_10_bpc
[21:10:36] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv422_12_bpc
[21:10:36] === [PASSED] drm_test_connector_hdmi_compute_mode_clock ====
[21:10:36] == drm_hdmi_connector_get_broadcast_rgb_name (2 subtests) ==
[21:10:36] === drm_test_drm_hdmi_connector_get_broadcast_rgb_name  ====
[21:10:36] [PASSED] Automatic
[21:10:36] [PASSED] Full
[21:10:36] [PASSED] Limited 16:235
[21:10:36] === [PASSED] drm_test_drm_hdmi_connector_get_broadcast_rgb_name ===
[21:10:36] [PASSED] drm_test_drm_hdmi_connector_get_broadcast_rgb_name_invalid
[21:10:36] ==== [PASSED] drm_hdmi_connector_get_broadcast_rgb_name ====
[21:10:36] == drm_hdmi_connector_get_output_format_name (2 subtests) ==
[21:10:36] === drm_test_drm_hdmi_connector_get_output_format_name  ====
[21:10:36] [PASSED] RGB
[21:10:36] [PASSED] YUV 4:2:0
[21:10:36] [PASSED] YUV 4:2:2
[21:10:36] [PASSED] YUV 4:4:4
[21:10:36] === [PASSED] drm_test_drm_hdmi_connector_get_output_format_name ===
[21:10:36] [PASSED] drm_test_drm_hdmi_connector_get_output_format_name_invalid
[21:10:36] ==== [PASSED] drm_hdmi_connector_get_output_format_name ====
[21:10:36] ============= drm_damage_helper (21 subtests) ==============
[21:10:36] [PASSED] drm_test_damage_iter_no_damage
[21:10:36] [PASSED] drm_test_damage_iter_no_damage_fractional_src
[21:10:36] [PASSED] drm_test_damage_iter_no_damage_src_moved
[21:10:36] [PASSED] drm_test_damage_iter_no_damage_fractional_src_moved
[21:10:36] [PASSED] drm_test_damage_iter_no_damage_not_visible
[21:10:36] [PASSED] drm_test_damage_iter_no_damage_no_crtc
[21:10:36] [PASSED] drm_test_damage_iter_no_damage_no_fb
[21:10:36] [PASSED] drm_test_damage_iter_simple_damage
[21:10:36] [PASSED] drm_test_damage_iter_single_damage
[21:10:36] [PASSED] drm_test_damage_iter_single_damage_intersect_src
[21:10:36] [PASSED] drm_test_damage_iter_single_damage_outside_src
[21:10:36] [PASSED] drm_test_damage_iter_single_damage_fractional_src
[21:10:36] [PASSED] drm_test_damage_iter_single_damage_intersect_fractional_src
[21:10:36] [PASSED] drm_test_damage_iter_single_damage_outside_fractional_src
[21:10:36] [PASSED] drm_test_damage_iter_single_damage_src_moved
[21:10:36] [PASSED] drm_test_damage_iter_single_damage_fractional_src_moved
[21:10:36] [PASSED] drm_test_damage_iter_damage
[21:10:36] [PASSED] drm_test_damage_iter_damage_one_intersect
[21:10:36] [PASSED] drm_test_damage_iter_damage_one_outside
[21:10:36] [PASSED] drm_test_damage_iter_damage_src_moved
[21:10:36] [PASSED] drm_test_damage_iter_damage_not_visible
[21:10:36] ================ [PASSED] drm_damage_helper ================
[21:10:36] ============== drm_dp_mst_helper (3 subtests) ==============
[21:10:36] ============== drm_test_dp_mst_calc_pbn_mode  ==============
[21:10:36] [PASSED] Clock 154000 BPP 30 DSC disabled
[21:10:36] [PASSED] Clock 234000 BPP 30 DSC disabled
[21:10:36] [PASSED] Clock 297000 BPP 24 DSC disabled
[21:10:36] [PASSED] Clock 332880 BPP 24 DSC enabled
[21:10:36] [PASSED] Clock 324540 BPP 24 DSC enabled
[21:10:36] ========== [PASSED] drm_test_dp_mst_calc_pbn_mode ==========
[21:10:36] ============== drm_test_dp_mst_calc_pbn_div  ===============
[21:10:36] [PASSED] Link rate 2000000 lane count 4
[21:10:36] [PASSED] Link rate 2000000 lane count 2
[21:10:36] [PASSED] Link rate 2000000 lane count 1
[21:10:36] [PASSED] Link rate 1350000 lane count 4
[21:10:36] [PASSED] Link rate 1350000 lane count 2
[21:10:36] [PASSED] Link rate 1350000 lane count 1
[21:10:36] [PASSED] Link rate 1000000 lane count 4
[21:10:36] [PASSED] Link rate 1000000 lane count 2
[21:10:36] [PASSED] Link rate 1000000 lane count 1
[21:10:36] [PASSED] Link rate 810000 lane count 4
[21:10:36] [PASSED] Link rate 810000 lane count 2
[21:10:36] [PASSED] Link rate 810000 lane count 1
[21:10:36] [PASSED] Link rate 540000 lane count 4
[21:10:36] [PASSED] Link rate 540000 lane count 2
[21:10:36] [PASSED] Link rate 540000 lane count 1
[21:10:36] [PASSED] Link rate 270000 lane count 4
[21:10:36] [PASSED] Link rate 270000 lane count 2
[21:10:36] [PASSED] Link rate 270000 lane count 1
[21:10:36] [PASSED] Link rate 162000 lane count 4
[21:10:36] [PASSED] Link rate 162000 lane count 2
[21:10:36] [PASSED] Link rate 162000 lane count 1
[21:10:36] ========== [PASSED] drm_test_dp_mst_calc_pbn_div ===========
[21:10:36] ========= drm_test_dp_mst_sideband_msg_req_decode  =========
[21:10:36] [PASSED] DP_ENUM_PATH_RESOURCES with port number
[21:10:36] [PASSED] DP_POWER_UP_PHY with port number
[21:10:36] [PASSED] DP_POWER_DOWN_PHY with port number
[21:10:36] [PASSED] DP_ALLOCATE_PAYLOAD with SDP stream sinks
[21:10:36] [PASSED] DP_ALLOCATE_PAYLOAD with port number
[21:10:36] [PASSED] DP_ALLOCATE_PAYLOAD with VCPI
[21:10:36] [PASSED] DP_ALLOCATE_PAYLOAD with PBN
[21:10:36] [PASSED] DP_QUERY_PAYLOAD with port number
[21:10:36] [PASSED] DP_QUERY_PAYLOAD with VCPI
[21:10:36] [PASSED] DP_REMOTE_DPCD_READ with port number
[21:10:36] [PASSED] DP_REMOTE_DPCD_READ with DPCD address
[21:10:36] [PASSED] DP_REMOTE_DPCD_READ with max number of bytes
[21:10:36] [PASSED] DP_REMOTE_DPCD_WRITE with port number
[21:10:36] [PASSED] DP_REMOTE_DPCD_WRITE with DPCD address
[21:10:36] [PASSED] DP_REMOTE_DPCD_WRITE with data array
[21:10:36] [PASSED] DP_REMOTE_I2C_READ with port number
[21:10:36] [PASSED] DP_REMOTE_I2C_READ with I2C device ID
[21:10:36] [PASSED] DP_REMOTE_I2C_READ with transactions array
[21:10:36] [PASSED] DP_REMOTE_I2C_WRITE with port number
[21:10:36] [PASSED] DP_REMOTE_I2C_WRITE with I2C device ID
[21:10:36] [PASSED] DP_REMOTE_I2C_WRITE with data array
[21:10:36] [PASSED] DP_QUERY_STREAM_ENC_STATUS with stream ID
[21:10:36] [PASSED] DP_QUERY_STREAM_ENC_STATUS with client ID
[21:10:36] [PASSED] DP_QUERY_STREAM_ENC_STATUS with stream event
[21:10:36] [PASSED] DP_QUERY_STREAM_ENC_STATUS with valid stream event
[21:10:36] [PASSED] DP_QUERY_STREAM_ENC_STATUS with stream behavior
[21:10:36] [PASSED] DP_QUERY_STREAM_ENC_STATUS with a valid stream behavior
[21:10:36] ===== [PASSED] drm_test_dp_mst_sideband_msg_req_decode =====
[21:10:36] ================ [PASSED] drm_dp_mst_helper ================
[21:10:36] ================== drm_exec (7 subtests) ===================
[21:10:36] [PASSED] sanitycheck
[21:10:36] [PASSED] test_lock
[21:10:36] [PASSED] test_lock_unlock
[21:10:36] [PASSED] test_duplicates
[21:10:36] [PASSED] test_prepare
[21:10:36] [PASSED] test_prepare_array
[21:10:36] [PASSED] test_multiple_loops
[21:10:36] ==================== [PASSED] drm_exec =====================
[21:10:36] =========== drm_format_helper_test (17 subtests) ===========
[21:10:36] ============== drm_test_fb_xrgb8888_to_gray8  ==============
[21:10:36] [PASSED] single_pixel_source_buffer
[21:10:36] [PASSED] single_pixel_clip_rectangle
[21:10:36] [PASSED] well_known_colors
[21:10:36] [PASSED] destination_pitch
[21:10:36] ========== [PASSED] drm_test_fb_xrgb8888_to_gray8 ==========
[21:10:36] ============= drm_test_fb_xrgb8888_to_rgb332  ==============
[21:10:36] [PASSED] single_pixel_source_buffer
[21:10:36] [PASSED] single_pixel_clip_rectangle
[21:10:36] [PASSED] well_known_colors
[21:10:36] [PASSED] destination_pitch
[21:10:36] ========= [PASSED] drm_test_fb_xrgb8888_to_rgb332 ==========
[21:10:36] ============= drm_test_fb_xrgb8888_to_rgb565  ==============
[21:10:36] [PASSED] single_pixel_source_buffer
[21:10:36] [PASSED] single_pixel_clip_rectangle
[21:10:36] [PASSED] well_known_colors
[21:10:36] [PASSED] destination_pitch
[21:10:36] ========= [PASSED] drm_test_fb_xrgb8888_to_rgb565 ==========
[21:10:36] ============ drm_test_fb_xrgb8888_to_xrgb1555  =============
[21:10:36] [PASSED] single_pixel_source_buffer
[21:10:36] [PASSED] single_pixel_clip_rectangle
[21:10:36] [PASSED] well_known_colors
[21:10:36] [PASSED] destination_pitch
[21:10:36] ======== [PASSED] drm_test_fb_xrgb8888_to_xrgb1555 =========
[21:10:36] ============ drm_test_fb_xrgb8888_to_argb1555  =============
[21:10:36] [PASSED] single_pixel_source_buffer
[21:10:36] [PASSED] single_pixel_clip_rectangle
[21:10:36] [PASSED] well_known_colors
[21:10:36] [PASSED] destination_pitch
[21:10:36] ======== [PASSED] drm_test_fb_xrgb8888_to_argb1555 =========
[21:10:36] ============ drm_test_fb_xrgb8888_to_rgba5551  =============
[21:10:36] [PASSED] single_pixel_source_buffer
[21:10:36] [PASSED] single_pixel_clip_rectangle
[21:10:36] [PASSED] well_known_colors
[21:10:36] [PASSED] destination_pitch
[21:10:36] ======== [PASSED] drm_test_fb_xrgb8888_to_rgba5551 =========
[21:10:36] ============= drm_test_fb_xrgb8888_to_rgb888  ==============
[21:10:36] [PASSED] single_pixel_source_buffer
[21:10:36] [PASSED] single_pixel_clip_rectangle
[21:10:36] [PASSED] well_known_colors
[21:10:36] [PASSED] destination_pitch
[21:10:36] ========= [PASSED] drm_test_fb_xrgb8888_to_rgb888 ==========
[21:10:36] ============= drm_test_fb_xrgb8888_to_bgr888  ==============
[21:10:36] [PASSED] single_pixel_source_buffer
[21:10:36] [PASSED] single_pixel_clip_rectangle
[21:10:36] [PASSED] well_known_colors
[21:10:36] [PASSED] destination_pitch
[21:10:36] ========= [PASSED] drm_test_fb_xrgb8888_to_bgr888 ==========
[21:10:36] ============ drm_test_fb_xrgb8888_to_argb8888  =============
[21:10:36] [PASSED] single_pixel_source_buffer
[21:10:36] [PASSED] single_pixel_clip_rectangle
[21:10:36] [PASSED] well_known_colors
[21:10:36] [PASSED] destination_pitch
[21:10:36] ======== [PASSED] drm_test_fb_xrgb8888_to_argb8888 =========
[21:10:36] =========== drm_test_fb_xrgb8888_to_xrgb2101010  ===========
[21:10:36] [PASSED] single_pixel_source_buffer
[21:10:36] [PASSED] single_pixel_clip_rectangle
[21:10:36] [PASSED] well_known_colors
[21:10:36] [PASSED] destination_pitch
[21:10:36] ======= [PASSED] drm_test_fb_xrgb8888_to_xrgb2101010 =======
[21:10:36] =========== drm_test_fb_xrgb8888_to_argb2101010  ===========
[21:10:36] [PASSED] single_pixel_source_buffer
[21:10:36] [PASSED] single_pixel_clip_rectangle
[21:10:36] [PASSED] well_known_colors
[21:10:36] [PASSED] destination_pitch
[21:10:36] ======= [PASSED] drm_test_fb_xrgb8888_to_argb2101010 =======
[21:10:36] ============== drm_test_fb_xrgb8888_to_mono  ===============
[21:10:36] [PASSED] single_pixel_source_buffer
[21:10:36] [PASSED] single_pixel_clip_rectangle
[21:10:36] [PASSED] well_known_colors
[21:10:36] [PASSED] destination_pitch
[21:10:36] ========== [PASSED] drm_test_fb_xrgb8888_to_mono ===========
[21:10:36] ==================== drm_test_fb_swab  =====================
[21:10:36] [PASSED] single_pixel_source_buffer
[21:10:36] [PASSED] single_pixel_clip_rectangle
[21:10:36] [PASSED] well_known_colors
[21:10:36] [PASSED] destination_pitch
[21:10:36] ================ [PASSED] drm_test_fb_swab =================
[21:10:36] ============ drm_test_fb_xrgb8888_to_xbgr8888  =============
[21:10:36] [PASSED] single_pixel_source_buffer
[21:10:36] [PASSED] single_pixel_clip_rectangle
[21:10:36] [PASSED] well_known_colors
[21:10:36] [PASSED] destination_pitch
[21:10:36] ======== [PASSED] drm_test_fb_xrgb8888_to_xbgr8888 =========
[21:10:36] ============ drm_test_fb_xrgb8888_to_abgr8888  =============
[21:10:36] [PASSED] single_pixel_source_buffer
[21:10:36] [PASSED] single_pixel_clip_rectangle
[21:10:36] [PASSED] well_known_colors
[21:10:36] [PASSED] destination_pitch
[21:10:36] ======== [PASSED] drm_test_fb_xrgb8888_to_abgr8888 =========
[21:10:36] ================= drm_test_fb_clip_offset  =================
[21:10:36] [PASSED] pass through
[21:10:36] [PASSED] horizontal offset
[21:10:36] [PASSED] vertical offset
[21:10:36] [PASSED] horizontal and vertical offset
[21:10:36] [PASSED] horizontal offset (custom pitch)
[21:10:36] [PASSED] vertical offset (custom pitch)
[21:10:36] [PASSED] horizontal and vertical offset (custom pitch)
[21:10:36] ============= [PASSED] drm_test_fb_clip_offset =============
[21:10:36] =================== drm_test_fb_memcpy  ====================
[21:10:36] [PASSED] single_pixel_source_buffer: XR24 little-endian (0x34325258)
[21:10:36] [PASSED] single_pixel_source_buffer: XRA8 little-endian (0x38415258)
[21:10:36] [PASSED] single_pixel_source_buffer: YU24 little-endian (0x34325559)
[21:10:36] [PASSED] single_pixel_clip_rectangle: XB24 little-endian (0x34324258)
[21:10:36] [PASSED] single_pixel_clip_rectangle: XRA8 little-endian (0x38415258)
[21:10:36] [PASSED] single_pixel_clip_rectangle: YU24 little-endian (0x34325559)
[21:10:36] [PASSED] well_known_colors: XB24 little-endian (0x34324258)
[21:10:36] [PASSED] well_known_colors: XRA8 little-endian (0x38415258)
[21:10:36] [PASSED] well_known_colors: YU24 little-endian (0x34325559)
[21:10:36] [PASSED] destination_pitch: XB24 little-endian (0x34324258)
[21:10:36] [PASSED] destination_pitch: XRA8 little-endian (0x38415258)
[21:10:36] [PASSED] destination_pitch: YU24 little-endian (0x34325559)
[21:10:36] =============== [PASSED] drm_test_fb_memcpy ================
[21:10:36] ============= [PASSED] drm_format_helper_test ==============
[21:10:36] ================= drm_format (18 subtests) =================
[21:10:36] [PASSED] drm_test_format_block_width_invalid
[21:10:36] [PASSED] drm_test_format_block_width_one_plane
[21:10:36] [PASSED] drm_test_format_block_width_two_plane
[21:10:36] [PASSED] drm_test_format_block_width_three_plane
[21:10:36] [PASSED] drm_test_format_block_width_tiled
[21:10:36] [PASSED] drm_test_format_block_height_invalid
[21:10:36] [PASSED] drm_test_format_block_height_one_plane
[21:10:36] [PASSED] drm_test_format_block_height_two_plane
[21:10:36] [PASSED] drm_test_format_block_height_three_plane
[21:10:36] [PASSED] drm_test_format_block_height_tiled
[21:10:36] [PASSED] drm_test_format_min_pitch_invalid
[21:10:36] [PASSED] drm_test_format_min_pitch_one_plane_8bpp
[21:10:36] [PASSED] drm_test_format_min_pitch_one_plane_16bpp
[21:10:36] [PASSED] drm_test_format_min_pitch_one_plane_24bpp
[21:10:36] [PASSED] drm_test_format_min_pitch_one_plane_32bpp
[21:10:36] [PASSED] drm_test_format_min_pitch_two_plane
[21:10:36] [PASSED] drm_test_format_min_pitch_three_plane_8bpp
[21:10:36] [PASSED] drm_test_format_min_pitch_tiled
[21:10:36] =================== [PASSED] drm_format ====================
[21:10:36] ============== drm_framebuffer (10 subtests) ===============
[21:10:36] ========== drm_test_framebuffer_check_src_coords  ==========
[21:10:36] [PASSED] Success: source fits into fb
[21:10:36] [PASSED] Fail: overflowing fb with x-axis coordinate
[21:10:36] [PASSED] Fail: overflowing fb with y-axis coordinate
[21:10:36] [PASSED] Fail: overflowing fb with source width
[21:10:36] [PASSED] Fail: overflowing fb with source height
[21:10:36] ====== [PASSED] drm_test_framebuffer_check_src_coords ======
[21:10:36] [PASSED] drm_test_framebuffer_cleanup
[21:10:36] =============== drm_test_framebuffer_create  ===============
[21:10:36] [PASSED] ABGR8888 normal sizes
[21:10:36] [PASSED] ABGR8888 max sizes
[21:10:36] [PASSED] ABGR8888 pitch greater than min required
[21:10:36] [PASSED] ABGR8888 pitch less than min required
[21:10:36] [PASSED] ABGR8888 Invalid width
[21:10:36] [PASSED] ABGR8888 Invalid buffer handle
[21:10:36] [PASSED] No pixel format
[21:10:36] [PASSED] ABGR8888 Width 0
[21:10:36] [PASSED] ABGR8888 Height 0
[21:10:36] [PASSED] ABGR8888 Out of bound height * pitch combination
[21:10:36] [PASSED] ABGR8888 Large buffer offset
[21:10:36] [PASSED] ABGR8888 Buffer offset for inexistent plane
[21:10:36] [PASSED] ABGR8888 Invalid flag
[21:10:36] [PASSED] ABGR8888 Set DRM_MODE_FB_MODIFIERS without modifiers
[21:10:36] [PASSED] ABGR8888 Valid buffer modifier
[21:10:36] [PASSED] ABGR8888 Invalid buffer modifier(DRM_FORMAT_MOD_SAMSUNG_64_32_TILE)
[21:10:36] [PASSED] ABGR8888 Extra pitches without DRM_MODE_FB_MODIFIERS
[21:10:36] [PASSED] ABGR8888 Extra pitches with DRM_MODE_FB_MODIFIERS
[21:10:36] [PASSED] NV12 Normal sizes
[21:10:36] [PASSED] NV12 Max sizes
[21:10:36] [PASSED] NV12 Invalid pitch
[21:10:36] [PASSED] NV12 Invalid modifier/missing DRM_MODE_FB_MODIFIERS flag
[21:10:36] [PASSED] NV12 different  modifier per-plane
[21:10:36] [PASSED] NV12 with DRM_FORMAT_MOD_SAMSUNG_64_32_TILE
[21:10:36] [PASSED] NV12 Valid modifiers without DRM_MODE_FB_MODIFIERS
[21:10:36] [PASSED] NV12 Modifier for inexistent plane
[21:10:36] [PASSED] NV12 Handle for inexistent plane
[21:10:36] [PASSED] NV12 Handle for inexistent plane without DRM_MODE_FB_MODIFIERS
[21:10:36] [PASSED] YVU420 DRM_MODE_FB_MODIFIERS set without modifier
[21:10:36] [PASSED] YVU420 Normal sizes
[21:10:36] [PASSED] YVU420 Max sizes
[21:10:36] [PASSED] YVU420 Invalid pitch
[21:10:36] [PASSED] YVU420 Different pitches
[21:10:36] [PASSED] YVU420 Different buffer offsets/pitches
[21:10:36] [PASSED] YVU420 Modifier set just for plane 0, without DRM_MODE_FB_MODIFIERS
[21:10:36] [PASSED] YVU420 Modifier set just for planes 0, 1, without DRM_MODE_FB_MODIFIERS
[21:10:36] [PASSED] YVU420 Modifier set just for plane 0, 1, with DRM_MODE_FB_MODIFIERS
[21:10:36] [PASSED] YVU420 Valid modifier
[21:10:36] [PASSED] YVU420 Different modifiers per plane
[21:10:36] [PASSED] YVU420 Modifier for inexistent plane
[21:10:36] [PASSED] YUV420_10BIT Invalid modifier(DRM_FORMAT_MOD_LINEAR)
[21:10:36] [PASSED] X0L2 Normal sizes
[21:10:36] [PASSED] X0L2 Max sizes
[21:10:36] [PASSED] X0L2 Invalid pitch
[21:10:36] [PASSED] X0L2 Pitch greater than minimum required
[21:10:36] [PASSED] X0L2 Handle for inexistent plane
[21:10:36] [PASSED] X0L2 Offset for inexistent plane, without DRM_MODE_FB_MODIFIERS set
[21:10:36] [PASSED] X0L2 Modifier without DRM_MODE_FB_MODIFIERS set
[21:10:36] [PASSED] X0L2 Valid modifier
[21:10:36] [PASSED] X0L2 Modifier for inexistent plane
[21:10:36] =========== [PASSED] drm_test_framebuffer_create ===========
[21:10:36] [PASSED] drm_test_framebuffer_free
[21:10:36] [PASSED] drm_test_framebuffer_init
[21:10:36] [PASSED] drm_test_framebuffer_init_bad_format
[21:10:36] [PASSED] drm_test_framebuffer_init_dev_mismatch
[21:10:36] [PASSED] drm_test_framebuffer_lookup
[21:10:36] [PASSED] drm_test_framebuffer_lookup_inexistent
[21:10:36] [PASSED] drm_test_framebuffer_modifiers_not_supported
[21:10:36] ================= [PASSED] drm_framebuffer =================
[21:10:36] ================ drm_gem_shmem (8 subtests) ================
[21:10:36] [PASSED] drm_gem_shmem_test_obj_create
[21:10:36] [PASSED] drm_gem_shmem_test_obj_create_private
[21:10:36] [PASSED] drm_gem_shmem_test_pin_pages
[21:10:36] [PASSED] drm_gem_shmem_test_vmap
[21:10:36] [PASSED] drm_gem_shmem_test_get_pages_sgt
[21:10:36] [PASSED] drm_gem_shmem_test_get_sg_table
[21:10:36] [PASSED] drm_gem_shmem_test_madvise
[21:10:36] [PASSED] drm_gem_shmem_test_purge
[21:10:36] ================== [PASSED] drm_gem_shmem ==================
[21:10:36] === drm_atomic_helper_connector_hdmi_check (27 subtests) ===
[21:10:36] [PASSED] drm_test_check_broadcast_rgb_auto_cea_mode
[21:10:36] [PASSED] drm_test_check_broadcast_rgb_auto_cea_mode_vic_1
[21:10:36] [PASSED] drm_test_check_broadcast_rgb_full_cea_mode
[21:10:36] [PASSED] drm_test_check_broadcast_rgb_full_cea_mode_vic_1
[21:10:36] [PASSED] drm_test_check_broadcast_rgb_limited_cea_mode
[21:10:36] [PASSED] drm_test_check_broadcast_rgb_limited_cea_mode_vic_1
[21:10:36] ====== drm_test_check_broadcast_rgb_cea_mode_yuv420  =======
[21:10:36] [PASSED] Automatic
[21:10:36] [PASSED] Full
[21:10:36] [PASSED] Limited 16:235
[21:10:36] == [PASSED] drm_test_check_broadcast_rgb_cea_mode_yuv420 ===
[21:10:36] [PASSED] drm_test_check_broadcast_rgb_crtc_mode_changed
[21:10:36] [PASSED] drm_test_check_broadcast_rgb_crtc_mode_not_changed
[21:10:36] [PASSED] drm_test_check_disable_connector
[21:10:36] [PASSED] drm_test_check_hdmi_funcs_reject_rate
[21:10:36] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_rgb
[21:10:36] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_yuv420
[21:10:36] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_ignore_yuv422
[21:10:36] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_ignore_yuv420
[21:10:36] [PASSED] drm_test_check_driver_unsupported_fallback_yuv420
[21:10:36] [PASSED] drm_test_check_output_bpc_crtc_mode_changed
[21:10:36] [PASSED] drm_test_check_output_bpc_crtc_mode_not_changed
[21:10:36] [PASSED] drm_test_check_output_bpc_dvi
[21:10:36] [PASSED] drm_test_check_output_bpc_format_vic_1
[21:10:36] [PASSED] drm_test_check_output_bpc_format_display_8bpc_only
[21:10:36] [PASSED] drm_test_check_output_bpc_format_display_rgb_only
[21:10:36] [PASSED] drm_test_check_output_bpc_format_driver_8bpc_only
[21:10:36] [PASSED] drm_test_check_output_bpc_format_driver_rgb_only
[21:10:36] [PASSED] drm_test_check_tmds_char_rate_rgb_8bpc
[21:10:36] [PASSED] drm_test_check_tmds_char_rate_rgb_10bpc
[21:10:36] [PASSED] drm_test_check_tmds_char_rate_rgb_12bpc
[21:10:36] ===== [PASSED] drm_atomic_helper_connector_hdmi_check ======
[21:10:36] === drm_atomic_helper_connector_hdmi_reset (6 subtests) ====
[21:10:36] [PASSED] drm_test_check_broadcast_rgb_value
[21:10:36] [PASSED] drm_test_check_bpc_8_value
[21:10:36] [PASSED] drm_test_check_bpc_10_value
[21:10:36] [PASSED] drm_test_check_bpc_12_value
[21:10:36] [PASSED] drm_test_check_format_value
[21:10:36] [PASSED] drm_test_check_tmds_char_value
[21:10:36] ===== [PASSED] drm_atomic_helper_connector_hdmi_reset ======
[21:10:36] = drm_atomic_helper_connector_hdmi_mode_valid (4 subtests) =
[21:10:36] [PASSED] drm_test_check_mode_valid
[21:10:36] [PASSED] drm_test_check_mode_valid_reject
[21:10:36] [PASSED] drm_test_check_mode_valid_reject_rate
[21:10:36] [PASSED] drm_test_check_mode_valid_reject_max_clock
[21:10:36] === [PASSED] drm_atomic_helper_connector_hdmi_mode_valid ===
[21:10:36] ================= drm_managed (2 subtests) =================
[21:10:36] [PASSED] drm_test_managed_release_action
[21:10:36] [PASSED] drm_test_managed_run_action
[21:10:36] =================== [PASSED] drm_managed ===================
[21:10:36] =================== drm_mm (6 subtests) ====================
[21:10:36] [PASSED] drm_test_mm_init
[21:10:36] [PASSED] drm_test_mm_debug
[21:10:36] [PASSED] drm_test_mm_align32
[21:10:36] [PASSED] drm_test_mm_align64
[21:10:36] [PASSED] drm_test_mm_lowest
[21:10:36] [PASSED] drm_test_mm_highest
[21:10:36] ===================== [PASSED] drm_mm ======================
[21:10:36] ============= drm_modes_analog_tv (5 subtests) =============
[21:10:36] [PASSED] drm_test_modes_analog_tv_mono_576i
[21:10:36] [PASSED] drm_test_modes_analog_tv_ntsc_480i
[21:10:36] [PASSED] drm_test_modes_analog_tv_ntsc_480i_inlined
[21:10:36] [PASSED] drm_test_modes_analog_tv_pal_576i
[21:10:36] [PASSED] drm_test_modes_analog_tv_pal_576i_inlined
[21:10:36] =============== [PASSED] drm_modes_analog_tv ===============
[21:10:36] ============== drm_plane_helper (2 subtests) ===============
[21:10:36] =============== drm_test_check_plane_state  ================
[21:10:36] [PASSED] clipping_simple
[21:10:36] [PASSED] clipping_rotate_reflect
[21:10:36] [PASSED] positioning_simple
[21:10:36] [PASSED] upscaling
[21:10:36] [PASSED] downscaling
[21:10:36] [PASSED] rounding1
[21:10:36] [PASSED] rounding2
[21:10:36] [PASSED] rounding3
[21:10:36] [PASSED] rounding4
[21:10:36] =========== [PASSED] drm_test_check_plane_state ============
[21:10:36] =========== drm_test_check_invalid_plane_state  ============
[21:10:36] [PASSED] positioning_invalid
[21:10:36] [PASSED] upscaling_invalid
[21:10:36] [PASSED] downscaling_invalid
[21:10:36] ======= [PASSED] drm_test_check_invalid_plane_state ========
[21:10:36] ================ [PASSED] drm_plane_helper =================
[21:10:36] ====== drm_connector_helper_tv_get_modes (1 subtest) =======
[21:10:36] ====== drm_test_connector_helper_tv_get_modes_check  =======
[21:10:36] [PASSED] None
[21:10:36] [PASSED] PAL
[21:10:36] [PASSED] NTSC
[21:10:36] [PASSED] Both, NTSC Default
[21:10:36] [PASSED] Both, PAL Default
[21:10:36] [PASSED] Both, NTSC Default, with PAL on command-line
[21:10:36] [PASSED] Both, PAL Default, with NTSC on command-line
[21:10:36] == [PASSED] drm_test_connector_helper_tv_get_modes_check ===
[21:10:36] ======== [PASSED] drm_connector_helper_tv_get_modes ========
[21:10:36] ================== drm_rect (9 subtests) ===================
[21:10:36] [PASSED] drm_test_rect_clip_scaled_div_by_zero
[21:10:36] [PASSED] drm_test_rect_clip_scaled_not_clipped
[21:10:36] [PASSED] drm_test_rect_clip_scaled_clipped
[21:10:36] [PASSED] drm_test_rect_clip_scaled_signed_vs_unsigned
[21:10:36] ================= drm_test_rect_intersect  =================
[21:10:36] [PASSED] top-left x bottom-right: 2x2+1+1 x 2x2+0+0
[21:10:36] [PASSED] top-right x bottom-left: 2x2+0+0 x 2x2+1-1
[21:10:36] [PASSED] bottom-left x top-right: 2x2+1-1 x 2x2+0+0
[21:10:36] [PASSED] bottom-right x top-left: 2x2+0+0 x 2x2+1+1
[21:10:36] [PASSED] right x left: 2x1+0+0 x 3x1+1+0
[21:10:36] [PASSED] left x right: 3x1+1+0 x 2x1+0+0
[21:10:36] [PASSED] up x bottom: 1x2+0+0 x 1x3+0-1
[21:10:36] [PASSED] bottom x up: 1x3+0-1 x 1x2+0+0
[21:10:36] [PASSED] touching corner: 1x1+0+0 x 2x2+1+1
[21:10:36] [PASSED] touching side: 1x1+0+0 x 1x1+1+0
[21:10:36] [PASSED] equal rects: 2x2+0+0 x 2x2+0+0
[21:10:36] [PASSED] inside another: 2x2+0+0 x 1x1+1+1
[21:10:36] [PASSED] far away: 1x1+0+0 x 1x1+3+6
[21:10:36] [PASSED] points intersecting: 0x0+5+10 x 0x0+5+10
[21:10:36] [PASSED] points not intersecting: 0x0+0+0 x 0x0+5+10
[21:10:36] ============= [PASSED] drm_test_rect_intersect =============
[21:10:36] ================ drm_test_rect_calc_hscale  ================
[21:10:36] [PASSED] normal use
[21:10:36] [PASSED] out of max range
[21:10:36] [PASSED] out of min range
[21:10:36] [PASSED] zero dst
[21:10:36] [PASSED] negative src
[21:10:36] [PASSED] negative dst
[21:10:36] ============ [PASSED] drm_test_rect_calc_hscale ============
[21:10:36] ================ drm_test_rect_calc_vscale  ================
[21:10:36] [PASSED] normal use
stty: 'standard input': Inappropriate ioctl for device
[21:10:36] [PASSED] out of max range
[21:10:36] [PASSED] out of min range
[21:10:36] [PASSED] zero dst
[21:10:36] [PASSED] negative src
[21:10:36] [PASSED] negative dst
[21:10:36] ============ [PASSED] drm_test_rect_calc_vscale ============
[21:10:36] ================== drm_test_rect_rotate  ===================
[21:10:36] [PASSED] reflect-x
[21:10:36] [PASSED] reflect-y
[21:10:36] [PASSED] rotate-0
[21:10:36] [PASSED] rotate-90
[21:10:36] [PASSED] rotate-180
[21:10:36] [PASSED] rotate-270
[21:10:36] ============== [PASSED] drm_test_rect_rotate ===============
[21:10:36] ================ drm_test_rect_rotate_inv  =================
[21:10:36] [PASSED] reflect-x
[21:10:36] [PASSED] reflect-y
[21:10:36] [PASSED] rotate-0
[21:10:36] [PASSED] rotate-90
[21:10:36] [PASSED] rotate-180
[21:10:36] [PASSED] rotate-270
[21:10:36] ============ [PASSED] drm_test_rect_rotate_inv =============
[21:10:36] ==================== [PASSED] drm_rect =====================
[21:10:36] ============ drm_sysfb_modeset_test (1 subtest) ============
[21:10:36] ============ drm_test_sysfb_build_fourcc_list  =============
[21:10:36] [PASSED] no native formats
[21:10:36] [PASSED] XRGB8888 as native format
[21:10:36] [PASSED] remove duplicates
[21:10:36] [PASSED] convert alpha formats
[21:10:36] [PASSED] random formats
[21:10:36] ======== [PASSED] drm_test_sysfb_build_fourcc_list =========
[21:10:36] ============= [PASSED] drm_sysfb_modeset_test ==============
[21:10:36] ============================================================
[21:10:36] Testing complete. Ran 622 tests: passed: 622
[21:10:36] Elapsed time: 27.155s total, 1.718s configuring, 25.016s building, 0.391s running

+ /kernel/tools/testing/kunit/kunit.py run --kunitconfig /kernel/drivers/gpu/drm/ttm/tests/.kunitconfig
[21:10:36] Configuring KUnit Kernel ...
Regenerating .config ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
[21:10:38] Building KUnit Kernel ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
Building with:
$ make all compile_commands.json scripts_gdb ARCH=um O=.kunit --jobs=48
[21:10:48] Starting KUnit Kernel (1/1)...
[21:10:48] ============================================================
Running tests with:
$ .kunit/linux kunit.enable=1 mem=1G console=tty kunit_shutdown=halt
[21:10:48] ================= ttm_device (5 subtests) ==================
[21:10:48] [PASSED] ttm_device_init_basic
[21:10:48] [PASSED] ttm_device_init_multiple
[21:10:48] [PASSED] ttm_device_fini_basic
[21:10:48] [PASSED] ttm_device_init_no_vma_man
[21:10:48] ================== ttm_device_init_pools  ==================
[21:10:48] [PASSED] No DMA allocations, no DMA32 required
[21:10:48] [PASSED] DMA allocations, DMA32 required
[21:10:48] [PASSED] No DMA allocations, DMA32 required
[21:10:48] [PASSED] DMA allocations, no DMA32 required
[21:10:48] ============== [PASSED] ttm_device_init_pools ==============
[21:10:48] =================== [PASSED] ttm_device ====================
[21:10:48] ================== ttm_pool (8 subtests) ===================
[21:10:48] ================== ttm_pool_alloc_basic  ===================
[21:10:48] [PASSED] One page
[21:10:48] [PASSED] More than one page
[21:10:48] [PASSED] Above the allocation limit
[21:10:48] [PASSED] One page, with coherent DMA mappings enabled
[21:10:48] [PASSED] Above the allocation limit, with coherent DMA mappings enabled
[21:10:48] ============== [PASSED] ttm_pool_alloc_basic ===============
[21:10:48] ============== ttm_pool_alloc_basic_dma_addr  ==============
[21:10:48] [PASSED] One page
[21:10:48] [PASSED] More than one page
[21:10:48] [PASSED] Above the allocation limit
[21:10:48] [PASSED] One page, with coherent DMA mappings enabled
[21:10:48] [PASSED] Above the allocation limit, with coherent DMA mappings enabled
[21:10:48] ========== [PASSED] ttm_pool_alloc_basic_dma_addr ==========
[21:10:48] [PASSED] ttm_pool_alloc_order_caching_match
[21:10:48] [PASSED] ttm_pool_alloc_caching_mismatch
[21:10:48] [PASSED] ttm_pool_alloc_order_mismatch
[21:10:48] [PASSED] ttm_pool_free_dma_alloc
[21:10:48] [PASSED] ttm_pool_free_no_dma_alloc
[21:10:48] [PASSED] ttm_pool_fini_basic
[21:10:48] ==================== [PASSED] ttm_pool =====================
[21:10:48] ================ ttm_resource (8 subtests) =================
[21:10:48] ================= ttm_resource_init_basic  =================
[21:10:48] [PASSED] Init resource in TTM_PL_SYSTEM
[21:10:48] [PASSED] Init resource in TTM_PL_VRAM
[21:10:48] [PASSED] Init resource in a private placement
[21:10:48] [PASSED] Init resource in TTM_PL_SYSTEM, set placement flags
[21:10:48] ============= [PASSED] ttm_resource_init_basic =============
[21:10:48] [PASSED] ttm_resource_init_pinned
[21:10:48] [PASSED] ttm_resource_fini_basic
[21:10:48] [PASSED] ttm_resource_manager_init_basic
[21:10:48] [PASSED] ttm_resource_manager_usage_basic
[21:10:48] [PASSED] ttm_resource_manager_set_used_basic
[21:10:48] [PASSED] ttm_sys_man_alloc_basic
[21:10:48] [PASSED] ttm_sys_man_free_basic
[21:10:48] ================== [PASSED] ttm_resource ===================
[21:10:48] =================== ttm_tt (15 subtests) ===================
[21:10:48] ==================== ttm_tt_init_basic  ====================
[21:10:48] [PASSED] Page-aligned size
[21:10:48] [PASSED] Extra pages requested
[21:10:48] ================ [PASSED] ttm_tt_init_basic ================
[21:10:48] [PASSED] ttm_tt_init_misaligned
[21:10:48] [PASSED] ttm_tt_fini_basic
[21:10:48] [PASSED] ttm_tt_fini_sg
[21:10:48] [PASSED] ttm_tt_fini_shmem
[21:10:48] [PASSED] ttm_tt_create_basic
[21:10:48] [PASSED] ttm_tt_create_invalid_bo_type
[21:10:48] [PASSED] ttm_tt_create_ttm_exists
[21:10:48] [PASSED] ttm_tt_create_failed
[21:10:48] [PASSED] ttm_tt_destroy_basic
[21:10:48] [PASSED] ttm_tt_populate_null_ttm
[21:10:48] [PASSED] ttm_tt_populate_populated_ttm
[21:10:48] [PASSED] ttm_tt_unpopulate_basic
[21:10:48] [PASSED] ttm_tt_unpopulate_empty_ttm
[21:10:48] [PASSED] ttm_tt_swapin_basic
[21:10:48] ===================== [PASSED] ttm_tt ======================
[21:10:48] =================== ttm_bo (14 subtests) ===================
[21:10:48] =========== ttm_bo_reserve_optimistic_no_ticket  ===========
[21:10:48] [PASSED] Cannot be interrupted and sleeps
[21:10:48] [PASSED] Cannot be interrupted, locks straight away
[21:10:48] [PASSED] Can be interrupted, sleeps
[21:10:48] ======= [PASSED] ttm_bo_reserve_optimistic_no_ticket =======
[21:10:48] [PASSED] ttm_bo_reserve_locked_no_sleep
[21:10:48] [PASSED] ttm_bo_reserve_no_wait_ticket
[21:10:48] [PASSED] ttm_bo_reserve_double_resv
[21:10:48] [PASSED] ttm_bo_reserve_interrupted
[21:10:48] [PASSED] ttm_bo_reserve_deadlock
[21:10:48] [PASSED] ttm_bo_unreserve_basic
[21:10:48] [PASSED] ttm_bo_unreserve_pinned
[21:10:48] [PASSED] ttm_bo_unreserve_bulk
[21:10:48] [PASSED] ttm_bo_fini_basic
[21:10:48] [PASSED] ttm_bo_fini_shared_resv
[21:10:48] [PASSED] ttm_bo_pin_basic
[21:10:48] [PASSED] ttm_bo_pin_unpin_resource
[21:10:48] [PASSED] ttm_bo_multiple_pin_one_unpin
[21:10:48] ===================== [PASSED] ttm_bo ======================
[21:10:48] ============== ttm_bo_validate (21 subtests) ===============
[21:10:48] ============== ttm_bo_init_reserved_sys_man  ===============
[21:10:48] [PASSED] Buffer object for userspace
[21:10:48] [PASSED] Kernel buffer object
[21:10:48] [PASSED] Shared buffer object
[21:10:48] ========== [PASSED] ttm_bo_init_reserved_sys_man ===========
[21:10:48] ============== ttm_bo_init_reserved_mock_man  ==============
[21:10:48] [PASSED] Buffer object for userspace
[21:10:48] [PASSED] Kernel buffer object
[21:10:48] [PASSED] Shared buffer object
[21:10:48] ========== [PASSED] ttm_bo_init_reserved_mock_man ==========
[21:10:48] [PASSED] ttm_bo_init_reserved_resv
[21:10:48] ================== ttm_bo_validate_basic  ==================
[21:10:48] [PASSED] Buffer object for userspace
[21:10:48] [PASSED] Kernel buffer object
[21:10:48] [PASSED] Shared buffer object
[21:10:48] ============== [PASSED] ttm_bo_validate_basic ==============
[21:10:48] [PASSED] ttm_bo_validate_invalid_placement
[21:10:48] ============= ttm_bo_validate_same_placement  ==============
[21:10:48] [PASSED] System manager
[21:10:48] [PASSED] VRAM manager
[21:10:48] ========= [PASSED] ttm_bo_validate_same_placement ==========
[21:10:48] [PASSED] ttm_bo_validate_failed_alloc
[21:10:48] [PASSED] ttm_bo_validate_pinned
[21:10:48] [PASSED] ttm_bo_validate_busy_placement
[21:10:48] ================ ttm_bo_validate_multihop  =================
[21:10:48] [PASSED] Buffer object for userspace
[21:10:48] [PASSED] Kernel buffer object
[21:10:48] [PASSED] Shared buffer object
[21:10:48] ============ [PASSED] ttm_bo_validate_multihop =============
[21:10:48] ========== ttm_bo_validate_no_placement_signaled  ==========
[21:10:48] [PASSED] Buffer object in system domain, no page vector
[21:10:48] [PASSED] Buffer object in system domain with an existing page vector
[21:10:48] ====== [PASSED] ttm_bo_validate_no_placement_signaled ======
[21:10:48] ======== ttm_bo_validate_no_placement_not_signaled  ========
[21:10:48] [PASSED] Buffer object for userspace
[21:10:48] [PASSED] Kernel buffer object
[21:10:48] [PASSED] Shared buffer object
[21:10:48] ==== [PASSED] ttm_bo_validate_no_placement_not_signaled ====
[21:10:48] [PASSED] ttm_bo_validate_move_fence_signaled
[21:10:48] ========= ttm_bo_validate_move_fence_not_signaled  =========
[21:10:48] [PASSED] Waits for GPU
[21:10:48] [PASSED] Tries to lock straight away
[21:10:48] ===== [PASSED] ttm_bo_validate_move_fence_not_signaled =====
[21:10:48] [PASSED] ttm_bo_validate_happy_evict
[21:10:48] [PASSED] ttm_bo_validate_all_pinned_evict
[21:10:48] [PASSED] ttm_bo_validate_allowed_only_evict
[21:10:48] [PASSED] ttm_bo_validate_deleted_evict
[21:10:48] [PASSED] ttm_bo_validate_busy_domain_evict
[21:10:48] [PASSED] ttm_bo_validate_evict_gutting
[21:10:48] [PASSED] ttm_bo_validate_recrusive_evict
stty: 'standard input': Inappropriate ioctl for device
[21:10:48] ================= [PASSED] ttm_bo_validate =================
[21:10:48] ============================================================
[21:10:48] Testing complete. Ran 101 tests: passed: 101
[21:10:48] Elapsed time: 11.343s total, 1.710s configuring, 9.417s building, 0.183s running

+ cleanup
++ stat -c %u:%g /kernel
+ chown -R 1003:1003 /kernel

✗ CI.checksparse: warning for drm/i915/display: Add initial support for Xe3p_LPD (rev5)

[Patchwork]

== Series Details ==

Series: drm/i915/display: Add initial support for Xe3p_LPD (rev5)
URL   : https://patchwork.freedesktop.org/series/155951/
State : warning

== Summary ==

+ trap cleanup EXIT
+ KERNEL=/kernel
+ MT=/root/linux/maintainer-tools
+ git clone https://gitlab.freedesktop.org/drm/maintainer-tools /root/linux/maintainer-tools
Cloning into '/root/linux/maintainer-tools'...
warning: redirecting to https://gitlab.freedesktop.org/drm/maintainer-tools.git/
+ make -C /root/linux/maintainer-tools
make: Entering directory '/root/linux/maintainer-tools'
cc -O2 -g -Wextra -o remap-log remap-log.c
make: Leaving directory '/root/linux/maintainer-tools'
+ cd /kernel
+ git config --global --add safe.directory /kernel
+ /root/linux/maintainer-tools/dim sparse --fast 0602386d452aeaa5f0abadb7d2805ea45f97d9f6
Sparse version: 0.6.4 (Ubuntu: 0.6.4-4ubuntu3)
Fast mode used, each commit won't be checked separately.
-
+drivers/gpu/drm/i915/display/intel_alpm.c: note: in included file:
+drivers/gpu/drm/i915/display/intel_casf.c:147:21: error: too long token expansion
+drivers/gpu/drm/i915/display/intel_cdclk.c: note: in included file:
+drivers/gpu/drm/i915/display/intel_ddi.c: note: in included file:
+drivers/gpu/drm/i915/display/intel_display_types.h:2073:24: warning: unreplaced symbol '<noident>'
+drivers/gpu/drm/i915/display/intel_display_types.h:2073:24: warning: unreplaced symbol '<noident>'
+drivers/gpu/drm/i915/display/intel_display_types.h:2073:24: warning: unreplaced symbol '<noident>'
+drivers/gpu/drm/i915/display/intel_display_types.h:2073:24: warning: unreplaced symbol '<noident>'
+drivers/gpu/drm/i915/display/intel_display_types.h:2073:24: warning: unreplaced symbol '<noident>'
+drivers/gpu/drm/i915/display/intel_display_types.h:2073:24: warning: unreplaced symbol '<noident>'
+drivers/gpu/drm/i915/display/intel_display_types.h:2073:24: warning: unreplaced symbol '<noident>'
+drivers/gpu/drm/i915/display/intel_display_types.h:2073:24: warning: unreplaced symbol '<noident>'
+drivers/gpu/drm/i915/display/intel_display_types.h:2073:24: warning: unreplaced symbol '<noident>'
+drivers/gpu/drm/i915/display/intel_display_types.h:2073:24: warning: unreplaced symbol '<noident>'
+drivers/gpu/drm/i915/display/intel_display_types.h:2073:24: warning: unreplaced symbol '<noident>'
+drivers/gpu/drm/i915/display/intel_display_types.h:2073:24: warning: unreplaced symbol '<noident>'
+drivers/gpu/drm/i915/display/intel_display_types.h:2073:24: warning: unreplaced symbol '<noident>'
+drivers/gpu/drm/i915/display/intel_display_types.h:2073:24: warning: unreplaced symbol '<noident>'
+drivers/gpu/drm/i915/display/intel_display_types.h:2073:24: warning: unreplaced symbol '<noident>'
+drivers/gpu/drm/i915/display/intel_display_types.h:2073:24: warning: unreplaced symbol '<noident>'
+drivers/gpu/drm/i915/display/intel_display_types.h:2086:24: warning: unreplaced symbol '<noident>'
+drivers/gpu/drm/i915/display/intel_display_types.h:2086:24: warning: unreplaced symbol '<noident>'
+drivers/gpu/drm/i915/display/intel_display_types.h:2086:24: warning: unreplaced symbol '<noident>'
+drivers/gpu/drm/i915/display/intel_hdcp.c: note: in included file:
+drivers/gpu/drm/i915/display/intel_hotplug.c: note: in included file:
+drivers/gpu/drm/i915/display/intel_lt_phy.c:1935:35: warning: Using plain integer as NULL pointer
+drivers/gpu/drm/i915/display/intel_pps.c: note: in included file:
+drivers/gpu/drm/i915/display/intel_psr.c: note: in included file:
+drivers/gpu/drm/i915/intel_uncore.c:1930:1: warning: context imbalance in 'fwtable_read8' - unexpected unlock
+drivers/gpu/drm/i915/intel_uncore.c:1931:1: warning: context imbalance in 'fwtable_read16' - unexpected unlock
+drivers/gpu/drm/i915/intel_uncore.c:1932:1: warning: context imbalance in 'fwtable_read32' - unexpected unlock
+drivers/gpu/drm/i915/intel_uncore.c:1933:1: warning: context imbalance in 'fwtable_read64' - unexpected unlock
+drivers/gpu/drm/i915/intel_uncore.c:1998:1: warning: context imbalance in 'gen6_write8' - unexpected unlock
+drivers/gpu/drm/i915/intel_uncore.c:1999:1: warning: context imbalance in 'gen6_write16' - unexpected unlock
+drivers/gpu/drm/i915/intel_uncore.c:2000:1: warning: context imbalance in 'gen6_write32' - unexpected unlock
+drivers/gpu/drm/i915/intel_uncore.c:2020:1: warning: context imbalance in 'fwtable_write8' - unexpected unlock
+drivers/gpu/drm/i915/intel_uncore.c:2021:1: warning: context imbalance in 'fwtable_write16' - unexpected unlock
+drivers/gpu/drm/i915/intel_uncore.c:2022:1: warning: context imbalance in 'fwtable_write32' - unexpected unlock

+ cleanup
++ stat -c %u:%g /kernel
+ chown -R 1003:1003 /kernel

✗ Xe.CI.Full: failure for drm/i915/display: Add initial support for Xe3p_LPD (rev5)

[Patchwork]

[-- Attachment #1: Type: text/plain, Size: 388 bytes --]

== Series Details ==

Series: drm/i915/display: Add initial support for Xe3p_LPD (rev5)
URL   : https://patchwork.freedesktop.org/series/155951/
State : failure

== Summary ==

ERROR: The runconfig 'xe-4110-5f250ba2e3bb0b4541473f2bd5dd8a8f22305b61_FULL' does not exist in the database

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155951v5/index.html

[-- Attachment #2: Type: text/html, Size: 953 bytes --]

Re: [PATCH v5 1/8] drm/i915/vbt: Add fields dedicated_external and dyn_port_over_tc

[Imre Deak]

On Fri, Nov 14, 2025 at 05:52:08PM -0300, Gustavo Sousa wrote:
> VBT version 264 adds new fields associated to Xe3p_LPD's new ways of
> configuring SoC for TC ports and PHYs.  Update the code to match the
> updates in VBT.
> 
> The new field dedicated_external is used to represent TC ports that are
> connected to PHYs outside of the Type-C subsystem, meaning that they
> behave like dedicated ports and don't require the extra Type-C
> programming.  In an upcoming change, we will update the driver to take
> this field into consideration when detecting the type of port.
> 
> The new field dyn_port_over_tc is used to inform that the TC port can be
> dynamically allocated for a legacy connector in the Type-C subsystem,
> which is a new feature in Xe3p_LPD.  In upcoming changes, we will use
> that field in order to handle the IOM resource management programming
> required for that.
> 
> Note that, when dedicated_external is set, the fields dp_usb_type_c and
> tbt are tagged as "don't care" in the spec, so they should be ignored in
> that case, so also add a sanitization function to take care of forcing
> them to zero when dedicated_external is true.
> 
> v2:
>   - Use sanitization function to force dp_usb_type_c and tbt fields to
>     be zero instead of adding a
>     intel_bios_encoder_is_dedicated_external() check in each of their
>     respective accessor functions. (Jani)
>   - Print info about dedicated external ports in print_ddi_port().
>     (Jani)
> v3:
>   - Also zero out field dyn_port_over_tc when dedicated_external is set.
>     (Imre)
>   - Use intel_bios_encoder_is_dedicated_external() directly instead of
>     storing return value into variable in print_ddi_port(). (Imre)
>   - Also print info for dyn_port_over_tc in print_ddi_port(). (Imre)
> 
> Bspec: 20124, 68954, 74304
> Cc: Imre Deak <imre.deak@intel.com>
> Cc: Jani Nikula <jani.nikula@linux.intel.com>
> Cc: Shekhar Chauhan <shekhar.chauhan@intel.com>
> Signed-off-by: Gustavo Sousa <gustavo.sousa@intel.com>

Reviewed-by: Imre Deak <imre.deak@intel.com>

> ---
>  drivers/gpu/drm/i915/display/intel_bios.c     | 73 ++++++++++++++++++++++++++-
>  drivers/gpu/drm/i915/display/intel_bios.h     |  2 +
>  drivers/gpu/drm/i915/display/intel_vbt_defs.h |  3 +-
>  3 files changed, 76 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_bios.c b/drivers/gpu/drm/i915/display/intel_bios.c
> index 4b41068e9e35..0283c0d418cf 100644
> --- a/drivers/gpu/drm/i915/display/intel_bios.c
> +++ b/drivers/gpu/drm/i915/display/intel_bios.c
> @@ -2529,6 +2529,54 @@ intel_bios_encoder_reject_edp_rate(const struct intel_bios_encoder_data *devdata
>  	return devdata->child.edp_data_rate_override & edp_rate_override_mask(rate);
>  }
>  
> +static void sanitize_dedicated_external(struct intel_bios_encoder_data *devdata,
> +					enum port port)
> +{
> +	struct intel_display *display = devdata->display;
> +
> +	if (!intel_bios_encoder_is_dedicated_external(devdata))
> +		return;
> +
> +	/*
> +	 * Since dedicated_external is for ports connected to PHYs outside of
> +	 * the Type-C subsystem, clear bits that would only make sense for ports
> +	 * with PHYs in the Type-C subsystem.
> +	 */
> +
> +	/*
> +	 * Bit dp_usb_type_c is marked as "don't care" in Bspec when
> +	 * dedicated_external is set.
> +	 */
> +	if (devdata->child.dp_usb_type_c) {
> +		drm_dbg_kms(display->drm,
> +			    "VBT claims Port %c supports USB Type-C, but the port is dedicated external, ignoring\n",
> +			    port_name(port));
> +		devdata->child.dp_usb_type_c = 0;
> +	}
> +
> +	/*
> +	 * Bit tbt is marked as "don't care" in Bspec when dedicated_external is
> +	 * set.
> +	 */
> +	if (devdata->child.tbt) {
> +		drm_dbg_kms(display->drm,
> +			    "VBT claims Port %c supports TBT, but the port is dedicated external, ignoring\n",
> +			    port_name(port));
> +		devdata->child.tbt = 0;
> +	}
> +
> +	/*
> +	 * DDI allocation for TC capable ports only make sense for PHYs in the
> +	 * Type-C subsystem.
> +	 */
> +	if (devdata->child.dyn_port_over_tc) {
> +		drm_dbg_kms(display->drm,
> +			    "VBT claims Port %c supports dynamic DDI allocation in TCSS, but the port is dedicated external, ignoring\n",
> +			    port_name(port));
> +		devdata->child.dyn_port_over_tc = 0;
> +	}
> +}
> +
>  static void sanitize_device_type(struct intel_bios_encoder_data *devdata,
>  				 enum port port)
>  {
> @@ -2693,6 +2741,16 @@ static void print_ddi_port(const struct intel_bios_encoder_data *devdata)
>  		    supports_typec_usb, supports_tbt,
>  		    devdata->dsc != NULL);
>  
> +	if (intel_bios_encoder_is_dedicated_external(devdata))
> +		drm_dbg_kms(display->drm,
> +			    "Port %c is dedicated external\n",
> +			    port_name(port));
> +
> +	if (intel_bios_encoder_supports_dyn_port_over_tc(devdata))
> +		drm_dbg_kms(display->drm,
> +			    "Port %c supports dynamic DDI allocation in TCSS\n",
> +			    port_name(port));
> +
>  	hdmi_level_shift = intel_bios_hdmi_level_shift(devdata);
>  	if (hdmi_level_shift >= 0) {
>  		drm_dbg_kms(display->drm,
> @@ -2750,6 +2808,7 @@ static void parse_ddi_port(struct intel_bios_encoder_data *devdata)
>  		return;
>  	}
>  
> +	sanitize_dedicated_external(devdata, port);
>  	sanitize_device_type(devdata, port);
>  	sanitize_hdmi_level_shift(devdata, port);
>  }
> @@ -2777,7 +2836,7 @@ static int child_device_expected_size(u16 version)
>  {
>  	BUILD_BUG_ON(sizeof(struct child_device_config) < 40);
>  
> -	if (version > 263)
> +	if (version > 264)
>  		return -ENOENT;
>  	else if (version >= 263)
>  		return 44;
> @@ -3721,6 +3780,18 @@ bool intel_bios_encoder_supports_tbt(const struct intel_bios_encoder_data *devda
>  	return devdata->display->vbt.version >= 209 && devdata->child.tbt;
>  }
>  
> +bool intel_bios_encoder_is_dedicated_external(const struct intel_bios_encoder_data *devdata)
> +{
> +	return devdata->display->vbt.version >= 264 &&
> +		devdata->child.dedicated_external;
> +}
> +
> +bool intel_bios_encoder_supports_dyn_port_over_tc(const struct intel_bios_encoder_data *devdata)
> +{
> +	return devdata->display->vbt.version >= 264 &&
> +		devdata->child.dyn_port_over_tc;
> +}
> +
>  bool intel_bios_encoder_lane_reversal(const struct intel_bios_encoder_data *devdata)
>  {
>  	return devdata && devdata->child.lane_reversal;
> diff --git a/drivers/gpu/drm/i915/display/intel_bios.h b/drivers/gpu/drm/i915/display/intel_bios.h
> index f9e438b2787b..75dff27b4228 100644
> --- a/drivers/gpu/drm/i915/display/intel_bios.h
> +++ b/drivers/gpu/drm/i915/display/intel_bios.h
> @@ -79,6 +79,8 @@ bool intel_bios_encoder_supports_dp(const struct intel_bios_encoder_data *devdat
>  bool intel_bios_encoder_supports_edp(const struct intel_bios_encoder_data *devdata);
>  bool intel_bios_encoder_supports_typec_usb(const struct intel_bios_encoder_data *devdata);
>  bool intel_bios_encoder_supports_tbt(const struct intel_bios_encoder_data *devdata);
> +bool intel_bios_encoder_is_dedicated_external(const struct intel_bios_encoder_data *devdata);
> +bool intel_bios_encoder_supports_dyn_port_over_tc(const struct intel_bios_encoder_data *devdata);
>  bool intel_bios_encoder_supports_dsi(const struct intel_bios_encoder_data *devdata);
>  bool intel_bios_encoder_supports_dp_dual_mode(const struct intel_bios_encoder_data *devdata);
>  bool intel_bios_encoder_is_lspcon(const struct intel_bios_encoder_data *devdata);
> diff --git a/drivers/gpu/drm/i915/display/intel_vbt_defs.h b/drivers/gpu/drm/i915/display/intel_vbt_defs.h
> index 70e31520c560..57fda5824c9c 100644
> --- a/drivers/gpu/drm/i915/display/intel_vbt_defs.h
> +++ b/drivers/gpu/drm/i915/display/intel_vbt_defs.h
> @@ -554,7 +554,8 @@ struct child_device_config {
>  	u8 dvo_function;
>  	u8 dp_usb_type_c:1;					/* 195+ */
>  	u8 tbt:1;						/* 209+ */
> -	u8 flags2_reserved:2;					/* 195+ */
> +	u8 dedicated_external:1;				/* 264+ */
> +	u8 dyn_port_over_tc:1;					/* 264+ */
>  	u8 dp_port_trace_length:4;				/* 209+ */
>  	u8 dp_gpio_index;					/* 195+ */
>  	u16 dp_gpio_pin_num;					/* 195+ */
> 
> -- 
> 2.51.0
> 

Re: [PATCH v5 2/8] drm/i915/power: Use intel_encoder_is_tc()

[Imre Deak]

On Fri, Nov 14, 2025 at 05:52:09PM -0300, Gustavo Sousa wrote:
> Starting with Xe3p_LPD, when intel_phy_is_tc() returns true, it does
> not necessarily mean that the port is connected to a PHY in the Type-C
> subsystem.  The reason is that there is now a VBT field called
> dedicated_external that will indicate that a Type-C capable port is
> connected to a (most likely) combo/dedicated PHY.  When that's the case,
> we must not do the extra programming required for Type-C connections.
> 
> In an upcoming change, we will modify intel_encoder_is_tc() to take the
> VBT field dedicated_external into consideration.  Update
> intel_display_power_well.c to use that function instead of
> intel_phy_is_tc().
> 
> Note that, even though icl_aux_power_well_{enable,disable} are not part
> of Xe3p_LPD's display paths, we modify them anyway for uniformity.
> 
> v2:
>   - Add and use icl_aux_pw_is_tc_phy() helper to avoid explicit encoder
>     lookup. (Imre)
> 
> Cc: Imre Deak <imre.deak@intel.com>
> Cc: Shekhar Chauhan <shekhar.chauhan@intel.com>
> Reviewed-by: Suraj Kandpal <suraj.kandpal@intel.com> # v1
> Signed-off-by: Gustavo Sousa <gustavo.sousa@intel.com>

Reviewed-by: Imre Deak <imre.deak@intel.com>

> ---
>  .../drm/i915/display/intel_display_power_well.c    | 33 +++++++++++++++-------
>  1 file changed, 23 insertions(+), 10 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_display_power_well.c b/drivers/gpu/drm/i915/display/intel_display_power_well.c
> index f4f7e73acc87..40d6b44c0b74 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_power_well.c
> +++ b/drivers/gpu/drm/i915/display/intel_display_power_well.c
> @@ -258,8 +258,9 @@ aux_ch_to_digital_port(struct intel_display *display,
>  	return NULL;
>  }
>  
> -static enum phy icl_aux_pw_to_phy(struct intel_display *display,
> -				  const struct i915_power_well *power_well)
> +static struct intel_encoder *
> +icl_aux_pw_to_encoder(struct intel_display *display,
> +		      const struct i915_power_well *power_well)
>  {
>  	enum aux_ch aux_ch = icl_aux_pw_to_ch(power_well);
>  	struct intel_digital_port *dig_port = aux_ch_to_digital_port(display, aux_ch);
> @@ -271,7 +272,23 @@ static enum phy icl_aux_pw_to_phy(struct intel_display *display,
>  	 * as HDMI-only and routed to a combo PHY, the encoder either won't be
>  	 * present at all or it will not have an aux_ch assigned.
>  	 */
> -	return dig_port ? intel_encoder_to_phy(&dig_port->base) : PHY_NONE;
> +	return dig_port ? &dig_port->base : NULL;
> +}
> +
> +static enum phy icl_aux_pw_to_phy(struct intel_display *display,
> +				  const struct i915_power_well *power_well)
> +{
> +	struct intel_encoder *encoder = icl_aux_pw_to_encoder(display, power_well);
> +
> +	return encoder ? intel_encoder_to_phy(encoder) : PHY_NONE;
> +}
> +
> +static bool icl_aux_pw_is_tc_phy(struct intel_display *display,
> +				 const struct i915_power_well *power_well)
> +{
> +	struct intel_encoder *encoder = icl_aux_pw_to_encoder(display, power_well);
> +
> +	return encoder && intel_encoder_is_tc(encoder);
>  }
>  
>  static void hsw_wait_for_power_well_enable(struct intel_display *display,
> @@ -570,9 +587,7 @@ static void
>  icl_aux_power_well_enable(struct intel_display *display,
>  			  struct i915_power_well *power_well)
>  {
> -	enum phy phy = icl_aux_pw_to_phy(display, power_well);
> -
> -	if (intel_phy_is_tc(display, phy))
> +	if (icl_aux_pw_is_tc_phy(display, power_well))
>  		return icl_tc_phy_aux_power_well_enable(display, power_well);
>  	else if (display->platform.icelake)
>  		return icl_combo_phy_aux_power_well_enable(display,
> @@ -585,9 +600,7 @@ static void
>  icl_aux_power_well_disable(struct intel_display *display,
>  			   struct i915_power_well *power_well)
>  {
> -	enum phy phy = icl_aux_pw_to_phy(display, power_well);
> -
> -	if (intel_phy_is_tc(display, phy))
> +	if (icl_aux_pw_is_tc_phy(display, power_well))
>  		return hsw_power_well_disable(display, power_well);
>  	else if (display->platform.icelake)
>  		return icl_combo_phy_aux_power_well_disable(display,
> @@ -1852,7 +1865,7 @@ static void xelpdp_aux_power_well_enable(struct intel_display *display,
>  	enum aux_ch aux_ch = i915_power_well_instance(power_well)->xelpdp.aux_ch;
>  	enum phy phy = icl_aux_pw_to_phy(display, power_well);
>  
> -	if (intel_phy_is_tc(display, phy))
> +	if (icl_aux_pw_is_tc_phy(display, power_well))
>  		icl_tc_port_assert_ref_held(display, power_well,
>  					    aux_ch_to_digital_port(display, aux_ch));
>  
> 
> -- 
> 2.51.0
> 

Re: [PATCH v5 3/8] drm/i915/display: Handle dedicated external ports in intel_encoder_is_tc()

[Imre Deak]

On Fri, Nov 14, 2025 at 05:52:10PM -0300, Gustavo Sousa wrote:
> Starting with Xe3p_LPD, the VBT has a new field, called in the driver
> "dedicated_external", which tells that a Type-C capable port is
> physically connected to a PHY outside of the Type-C subsystem.  When
> that's the case, the driver must not do the extra Type-C programming for
> that port.  Update intel_encoder_is_tc() to check for that case.
> 
> While at it, add a note to intel_phy_is_tc() to remind us that it is
> about whether the respective port is a Type-C capable port rather than
> the PHY itself.
> 
> (Maybe it would be a nice idea to rename intel_phy_is_tc()?)
> 
> Note that this was handled with a new bool member added to struct
> intel_digital_port instead of having querying the VBT directly because
> VBT memory is freed (intel_bios_driver_remove) before encoder cleanup
> (intel_ddi_encoder_destroy), which would cause an oops to happen when
> the latter calls intel_encoder_is_tc().  This could be fixed by keeping
> VBT data around longer, but that's left for a follow-up work, if deemed
> necessary.
> 
> v2:
>   - Drop printing info about dedicated external, now that we are doing
>     it when parsing the VBT. (Jani)
>   - Add a FIXME comment on the code explaining why we need to store
>     dedicated_external in struct intel_digital_port. (Jani)
> v3:
>   - Simplify the code by using NULL check for dig_port to avoid using
>     intel_encoder_is_dig_port(). (Imre)
> 
> Cc: Imre Deak <imre.deak@intel.com>
> Cc: Jani Nikula <jani.nikula@linux.intel.com>
> Cc: Shekhar Chauhan <shekhar.chauhan@intel.com>
> Signed-off-by: Gustavo Sousa <gustavo.sousa@intel.com>

Reviewed-by: Imre Deak <imre.deak@intel.com>

> ---
>  drivers/gpu/drm/i915/display/intel_ddi.c           | 11 +++++++++++
>  drivers/gpu/drm/i915/display/intel_display.c       | 16 +++++++++++++++-
>  drivers/gpu/drm/i915/display/intel_display_types.h |  1 +
>  3 files changed, 27 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
> index 002ccd47856d..11ceb9355b75 100644
> --- a/drivers/gpu/drm/i915/display/intel_ddi.c
> +++ b/drivers/gpu/drm/i915/display/intel_ddi.c
> @@ -5372,6 +5372,17 @@ void intel_ddi_init(struct intel_display *display,
>  			goto err;
>  	}
>  
> +	/*
> +	 * FIXME: We currently need to store dedicated_external because devdata
> +	 * does not live long enough for when intel_encoder_is_tc() is called on
> +	 * the unbind path.  This needs to be fixed by making sure that the VBT
> +	 * data is kept long enough, so that
> +	 * intel_bios_encoder_is_dedicated_external() can be called directly
> +	 * from intel_encoder_is_tc().
> +	 */
> +	if (intel_bios_encoder_is_dedicated_external(devdata))
> +		dig_port->dedicated_external = true;
> +
>  	if (intel_encoder_is_tc(encoder)) {
>  		bool is_legacy =
>  			!intel_bios_encoder_supports_typec_usb(devdata) &&
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
> index 069967114bd9..5071a0ae5235 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -1810,7 +1810,17 @@ bool intel_phy_is_combo(struct intel_display *display, enum phy phy)
>  		return false;
>  }
>  
> -/* Prefer intel_encoder_is_tc() */
> +/*
> + * This function returns true if the DDI port respective to the PHY enumeration
> + * is a Type-C capable port.
> + *
> + * Depending on the VBT, the port might be configured
> + * as a "dedicated external" port, meaning that actual physical PHY is outside
> + * of the Type-C subsystem and, as such, not really a "Type-C PHY".
> + *
> + * Prefer intel_encoder_is_tc(), especially if you really need to know if we
> + * are dealing with Type-C connections.
> + */
>  bool intel_phy_is_tc(struct intel_display *display, enum phy phy)
>  {
>  	/*
> @@ -1894,6 +1904,10 @@ bool intel_encoder_is_snps(struct intel_encoder *encoder)
>  bool intel_encoder_is_tc(struct intel_encoder *encoder)
>  {
>  	struct intel_display *display = to_intel_display(encoder);
> +	struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
> +
> +	if (dig_port && dig_port->dedicated_external)
> +		return false;
>  
>  	return intel_phy_is_tc(display, intel_encoder_to_phy(encoder));
>  }
> diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
> index 38702a9e0f50..7b08d618776c 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_types.h
> +++ b/drivers/gpu/drm/i915/display/intel_display_types.h
> @@ -1936,6 +1936,7 @@ struct intel_digital_port {
>  	bool lane_reversal;
>  	bool ddi_a_4_lanes;
>  	bool release_cl2_override;
> +	bool dedicated_external;
>  	u8 max_lanes;
>  	/* Used for DP and ICL+ TypeC/DP and TypeC/HDMI ports. */
>  	enum aux_ch aux_ch;
> 
> -- 
> 2.51.0
> 

Re: [PATCH v5 4/8] drm/i915/xe3p_lpd: Handle underrun debug bits

[Matt Roper]

On Fri, Nov 14, 2025 at 05:52:11PM -0300, Gustavo Sousa wrote:
> Xe3p_LPD added several bits containing information that can be relevant
> to debugging FIFO underruns.  Add the logic necessary to handle them
> when reporting underruns.
> 
> This was adapted from the initial patch[1] from Sai Teja Pottumuttu.
> 
> [1] https://lore.kernel.org/all/20251015-xe3p_lpd-basic-enabling-v1-12-d2d1e26520aa@intel.com/
> 
> v2:
>   - Handle FBC-related bits in intel_fbc.c. (Ville)
>   - Do not use intel_fbc_id_for_pipe (promoted from
>     skl_fbc_id_for_pipe), but use pipe's primary plane to get the FBC
>     instance. (Ville, Matt)
>   - Improve code readability by moving logic specific to logging fields
>     of UNDERRUN_DBG1 to a separate function. (Jani)
> 
> Bspec: 69111, 69561, 74411, 74412
> Cc: Jani Nikula <jani.nikula@intel.com>
> Cc: Matt Roper <matthew.d.roper@intel.com>
> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
> Signed-off-by: Gustavo Sousa <gustavo.sousa@intel.com>
> ---
> I tested this by adding a change on top of this series that updates
> Xe3p_LPD's CDCLK table to use bad values and I got the following
> messages:
> 
>     [  +0.000237] xe 0000:00:02.0: [drm:intel_modeset_verify_crtc [xe]] [CRTC:88:pipe A]
>     [  +0.000674] xe 0000:00:02.0: [drm] *ERROR* CPU pipe A FIFO underrun
>     [  +0.000015] xe 0000:00:02.0: [drm] *ERROR* Pipe A FIFO underrun info: DBUF block not valid on planes: [1]
>     [  +0.000001] xe 0000:00:02.0: [drm] *ERROR* Pipe A FIFO underrun info: DDB empty on planes: [1]
>     [  +0.000001] xe 0000:00:02.0: [drm] *ERROR* Pipe A FIFO underrun info: DBUF below WM0 on planes: [1]
>     [  +0.000004] xe 0000:00:02.0: [drm] *ERROR* Pipe A FIFO underrun info: frame count: 1890, line count: 44
> ---
>  .../gpu/drm/i915/display/intel_display_device.h    |   1 +
>  drivers/gpu/drm/i915/display/intel_display_regs.h  |  16 +++
>  drivers/gpu/drm/i915/display/intel_fbc.c           |  50 ++++++++++
>  drivers/gpu/drm/i915/display/intel_fbc.h           |   3 +
>  drivers/gpu/drm/i915/display/intel_fbc_regs.h      |   2 +
>  drivers/gpu/drm/i915/display/intel_fifo_underrun.c | 109 +++++++++++++++++++++
>  6 files changed, 181 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_display_device.h b/drivers/gpu/drm/i915/display/intel_display_device.h
> index b559ef43d547..91d8cfac5eff 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_device.h
> +++ b/drivers/gpu/drm/i915/display/intel_display_device.h
> @@ -197,6 +197,7 @@ struct intel_display_platforms {
>  #define HAS_TRANSCODER(__display, trans)	((DISPLAY_RUNTIME_INFO(__display)->cpu_transcoder_mask & \
>  						  BIT(trans)) != 0)
>  #define HAS_UNCOMPRESSED_JOINER(__display)	(DISPLAY_VER(__display) >= 13)
> +#define HAS_UNDERRUN_DBG_INFO(__display)	(DISPLAY_VER(__display) >= 35)
>  #define HAS_ULTRAJOINER(__display)	(((__display)->platform.dgfx && \
>  					  DISPLAY_VER(__display) == 14) && HAS_DSC(__display))
>  #define HAS_VRR(__display)		(DISPLAY_VER(__display) >= 11)
> diff --git a/drivers/gpu/drm/i915/display/intel_display_regs.h b/drivers/gpu/drm/i915/display/intel_display_regs.h
> index 9d71e26a4fa2..89ea0156ee06 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_regs.h
> +++ b/drivers/gpu/drm/i915/display/intel_display_regs.h
> @@ -882,6 +882,21 @@
>  #define   PIPE_MISC2_FLIP_INFO_PLANE_SEL_MASK		REG_GENMASK(2, 0) /* tgl+ */
>  #define   PIPE_MISC2_FLIP_INFO_PLANE_SEL(plane_id)	REG_FIELD_PREP(PIPE_MISC2_FLIP_INFO_PLANE_SEL_MASK, (plane_id))
>  
> +#define _UNDERRUN_DBG1_A			0x70064
> +#define _UNDERRUN_DBG1_B			0x71064
> +#define UNDERRUN_DBG1(pipe)			_MMIO_PIPE(pipe, _UNDERRUN_DBG1_A, _UNDERRUN_DBG1_B)
> +#define   UNDERRUN_DBUF_BLOCK_NOT_VALID_MASK	REG_GENMASK(29, 24)
> +#define   UNDERRUN_DDB_EMPTY_MASK		REG_GENMASK(21, 16)
> +#define   UNDERRUN_DBUF_NOT_FILLED_MASK		REG_GENMASK(13, 8)
> +#define   UNDERRUN_BELOW_WM0_MASK		REG_GENMASK(5, 0)
> +
> +#define _UNDERRUN_DBG2_A			0x70068
> +#define _UNDERRUN_DBG2_B			0x71068
> +#define UNDERRUN_DBG2(pipe)			_MMIO_PIPE(pipe, _UNDERRUN_DBG2_A, _UNDERRUN_DBG2_B)
> +#define   UNDERRUN_FRAME_LINE_COUNTERS_FROZEN	REG_BIT(31)
> +#define   UNDERRUN_PIPE_FRAME_COUNT_MASK	REG_GENMASK(30, 20)
> +#define   UNDERRUN_LINE_COUNT_MASK		REG_GENMASK(19, 0)
> +
>  #define DPINVGTT				_MMIO(VLV_DISPLAY_BASE + 0x7002c) /* VLV/CHV only */
>  #define   DPINVGTT_EN_MASK_CHV				REG_GENMASK(27, 16)
>  #define   DPINVGTT_EN_MASK_VLV				REG_GENMASK(23, 16)
> @@ -1416,6 +1431,7 @@
>  
>  #define GEN12_DCPR_STATUS_1				_MMIO(0x46440)
>  #define  XELPDP_PMDEMAND_INFLIGHT_STATUS		REG_BIT(26)
> +#define  XE3P_UNDERRUN_PKGC				REG_BIT(21)
>  
>  #define FUSE_STRAP		_MMIO(0x42014)
>  #define   ILK_INTERNAL_GRAPHICS_DISABLE	REG_BIT(31)
> diff --git a/drivers/gpu/drm/i915/display/intel_fbc.c b/drivers/gpu/drm/i915/display/intel_fbc.c
> index 437d2fda20a7..ec316f9843c6 100644
> --- a/drivers/gpu/drm/i915/display/intel_fbc.c
> +++ b/drivers/gpu/drm/i915/display/intel_fbc.c
> @@ -129,6 +129,25 @@ struct intel_fbc {
>  	const char *no_fbc_reason;
>  };
>  
> +static struct intel_fbc *intel_fbc_for_pipe(struct intel_display *display, enum pipe pipe)
> +{
> +	struct intel_crtc *crtc = intel_crtc_for_pipe(display, pipe);
> +	struct intel_plane *primary = NULL;
> +	struct intel_plane *plane;
> +
> +	for_each_intel_plane_on_crtc(display->drm, crtc, plane) {
> +		if (plane->base.type == DRM_PLANE_TYPE_PRIMARY) {

Can't we just use crtc->base.primary rather than looping to find it?
While it's legal at the DRM layer for modern drivers to not register a
primary plane (which in turn means no support for some pre-atomic KMS
APIs), i915 has always always created and registered one in
intel_crtc_init().  Other FBC code already uses the primary pointer to
grab the FBC associated with a CRTC (intel_fbc_min_cdclk,
intel_fbc_crtc_debugfs_add, etc.).


Matt

> +			primary = plane;
> +			break;
> +		}
> +	}
> +
> +	if (drm_WARN_ON(display->drm, !primary))
> +		return NULL;
> +
> +	return primary->fbc;
> +}
> +
>  /* plane stride in pixels */
>  static unsigned int intel_fbc_plane_stride(const struct intel_plane_state *plane_state)
>  {
> @@ -2119,6 +2138,37 @@ void intel_fbc_handle_fifo_underrun_irq(struct intel_display *display)
>  		__intel_fbc_handle_fifo_underrun_irq(fbc);
>  }
>  
> +/**
> + * intel_fbc_read_underrun_dbg_info - Read and log FBC-related FIFO underrun debug info
> + * @display: display device instance
> + * @pipe: the pipe possibly containing the FBC
> + * @log: log the info?
> + *
> + * If @pipe does not contain an FBC instance, this function bails early.
> + * Otherwise, FBC-related FIFO underrun is read and cleared, and then, if @log
> + * is true, printed with error level.
> + */
> +void intel_fbc_read_underrun_dbg_info(struct intel_display *display,
> +				      enum pipe pipe, bool log)
> +{
> +	struct intel_fbc *fbc = intel_fbc_for_pipe(display, pipe);
> +	u32 val;
> +
> +	if (!fbc)
> +		return;
> +
> +	val = intel_de_read(display, FBC_DEBUG_STATUS(fbc->id));
> +	if (!(val & FBC_UNDERRUN_DECMPR))
> +		return;
> +
> +	intel_de_write(display, FBC_DEBUG_STATUS(fbc->id), FBC_UNDERRUN_DECMPR);
> +
> +	if (log)
> +		drm_err(display->drm,
> +			"Pipe %c FIFO underrun info: FBC decompressing\n",
> +			pipe_name(pipe));
> +}
> +
>  /*
>   * The DDX driver changes its behavior depending on the value it reads from
>   * i915.enable_fbc, so sanitize it by translating the default value into either
> diff --git a/drivers/gpu/drm/i915/display/intel_fbc.h b/drivers/gpu/drm/i915/display/intel_fbc.h
> index 91424563206a..f0255ddae2b6 100644
> --- a/drivers/gpu/drm/i915/display/intel_fbc.h
> +++ b/drivers/gpu/drm/i915/display/intel_fbc.h
> @@ -9,6 +9,7 @@
>  #include <linux/types.h>
>  
>  enum fb_op_origin;
> +enum pipe;
>  struct intel_atomic_state;
>  struct intel_crtc;
>  struct intel_crtc_state;
> @@ -46,6 +47,8 @@ void intel_fbc_flush(struct intel_display *display,
>  		     unsigned int frontbuffer_bits, enum fb_op_origin origin);
>  void intel_fbc_add_plane(struct intel_fbc *fbc, struct intel_plane *plane);
>  void intel_fbc_handle_fifo_underrun_irq(struct intel_display *display);
> +void intel_fbc_read_underrun_dbg_info(struct intel_display *display,
> +				      enum pipe, bool log);
>  void intel_fbc_reset_underrun(struct intel_display *display);
>  void intel_fbc_crtc_debugfs_add(struct intel_crtc *crtc);
>  void intel_fbc_debugfs_register(struct intel_display *display);
> diff --git a/drivers/gpu/drm/i915/display/intel_fbc_regs.h b/drivers/gpu/drm/i915/display/intel_fbc_regs.h
> index b1d0161a3196..77d8321c4fb3 100644
> --- a/drivers/gpu/drm/i915/display/intel_fbc_regs.h
> +++ b/drivers/gpu/drm/i915/display/intel_fbc_regs.h
> @@ -88,6 +88,8 @@
>  #define DPFC_FENCE_YOFF			_MMIO(0x3218)
>  #define ILK_DPFC_FENCE_YOFF(fbc_id)	_MMIO_PIPE((fbc_id), 0x43218, 0x43258)
>  #define DPFC_CHICKEN			_MMIO(0x3224)
> +#define FBC_DEBUG_STATUS(fbc_id)	_MMIO_PIPE((fbc_id), 0x43220, 0x43260)
> +#define   FBC_UNDERRUN_DECMPR			REG_BIT(27)
>  #define ILK_DPFC_CHICKEN(fbc_id)	_MMIO_PIPE((fbc_id), 0x43224, 0x43264)
>  #define   DPFC_HT_MODIFY			REG_BIT(31) /* pre-ivb */
>  #define   DPFC_NUKE_ON_ANY_MODIFICATION		REG_BIT(23) /* bdw+ */
> diff --git a/drivers/gpu/drm/i915/display/intel_fifo_underrun.c b/drivers/gpu/drm/i915/display/intel_fifo_underrun.c
> index c2ce8461ac9e..b413b3e871d8 100644
> --- a/drivers/gpu/drm/i915/display/intel_fifo_underrun.c
> +++ b/drivers/gpu/drm/i915/display/intel_fifo_underrun.c
> @@ -25,6 +25,8 @@
>   *
>   */
>  
> +#include <linux/seq_buf.h>
> +
>  #include <drm/drm_print.h>
>  
>  #include "i915_reg.h"
> @@ -57,6 +59,100 @@
>   * The code also supports underrun detection on the PCH transcoder.
>   */
>  
> +#define UNDERRUN_DBG1_NUM_PLANES 6
> +
> +static void log_underrun_dbg1(struct intel_display *display, enum pipe pipe,
> +			      unsigned long plane_mask, const char *info)
> +{
> +	DECLARE_SEQ_BUF(planes_desc, 32);
> +	unsigned int i;
> +
> +	if (!plane_mask)
> +		return;
> +
> +	for_each_set_bit(i, &plane_mask, UNDERRUN_DBG1_NUM_PLANES) {
> +		if (i == 0)
> +			seq_buf_puts(&planes_desc, "[C]");
> +		else
> +			seq_buf_printf(&planes_desc, "[%d]", i);
> +	}
> +
> +	drm_err(display->drm, "Pipe %c FIFO underrun info: %s on planes: %s\n",
> +		pipe_name(pipe), info, seq_buf_str(&planes_desc));
> +
> +	drm_WARN_ON(display->drm, seq_buf_has_overflowed(&planes_desc));
> +}
> +
> +static void read_underrun_dbg1(struct intel_display *display, enum pipe pipe, bool log)
> +{
> +	u32 val = intel_de_read(display, UNDERRUN_DBG1(pipe));
> +
> +	if (!val)
> +		return;
> +
> +	intel_de_write(display, UNDERRUN_DBG1(pipe), val);
> +
> +	if (!log)
> +		return;
> +
> +	log_underrun_dbg1(display, pipe, REG_FIELD_GET(UNDERRUN_DBUF_BLOCK_NOT_VALID_MASK, val),
> +			  "DBUF block not valid");
> +	log_underrun_dbg1(display, pipe, REG_FIELD_GET(UNDERRUN_DDB_EMPTY_MASK, val),
> +			  "DDB empty");
> +	log_underrun_dbg1(display, pipe, REG_FIELD_GET(UNDERRUN_DBUF_NOT_FILLED_MASK, val),
> +			  "DBUF not completely filled");
> +	log_underrun_dbg1(display, pipe, REG_FIELD_GET(UNDERRUN_BELOW_WM0_MASK, val),
> +			  "DBUF below WM0");
> +}
> +
> +static void read_underrun_dbg2(struct intel_display *display, enum pipe pipe, bool log)
> +{
> +	u32 val = intel_de_read(display, UNDERRUN_DBG2(pipe));
> +
> +	if (!(val & UNDERRUN_FRAME_LINE_COUNTERS_FROZEN))
> +		return;
> +
> +	intel_de_write(display, UNDERRUN_DBG2(pipe), UNDERRUN_FRAME_LINE_COUNTERS_FROZEN);
> +
> +	if (log)
> +		drm_err(display->drm,
> +			"Pipe %c FIFO underrun info: frame count: %u, line count: %u\n",
> +			pipe_name(pipe),
> +			REG_FIELD_GET(UNDERRUN_PIPE_FRAME_COUNT_MASK, val),
> +			REG_FIELD_GET(UNDERRUN_LINE_COUNT_MASK, val));
> +}
> +
> +static void read_underrun_dbg_pkgc(struct intel_display *display, bool log)
> +{
> +	u32 val = intel_de_read(display, GEN12_DCPR_STATUS_1);
> +
> +	if (!(val & XE3P_UNDERRUN_PKGC))
> +		return;
> +
> +	/*
> +	 * Note: If there are multiple pipes enabled, only one of them will see
> +	 * XE3P_UNDERRUN_PKGC set.
> +	 */
> +	intel_de_write(display, GEN12_DCPR_STATUS_1, XE3P_UNDERRUN_PKGC);
> +
> +	if (log)
> +		drm_err(display->drm,
> +			"General FIFO underrun info: Package C-state blocking memory\n");
> +}
> +
> +static void read_underrun_dbg_info(struct intel_display *display,
> +				   enum pipe pipe,
> +				   bool log)
> +{
> +	if (!HAS_UNDERRUN_DBG_INFO(display))
> +		return;
> +
> +	read_underrun_dbg1(display, pipe, log);
> +	read_underrun_dbg2(display, pipe, log);
> +	intel_fbc_read_underrun_dbg_info(display, pipe, log);
> +	read_underrun_dbg_pkgc(display, log);
> +}
> +
>  static bool ivb_can_enable_err_int(struct intel_display *display)
>  {
>  	struct intel_crtc *crtc;
> @@ -262,6 +358,17 @@ static bool __intel_set_cpu_fifo_underrun_reporting(struct intel_display *displa
>  	old = !crtc->cpu_fifo_underrun_disabled;
>  	crtc->cpu_fifo_underrun_disabled = !enable;
>  
> +	/*
> +	 * The debug bits get latched at the time of the FIFO underrun ISR bit
> +	 * getting set.  That means that any non-zero debug bit that is read when
> +	 * handling a FIFO underrun interrupt has the potential to belong to
> +	 * another underrun event (past or future).  To alleviate this problem,
> +	 * let's clear existing bits before enabling the interrupt, so that at
> +	 * least we don't get information that is too out-of-date.
> +	 */
> +	if (enable && !old)
> +		read_underrun_dbg_info(display, pipe, false);
> +
>  	if (HAS_GMCH(display))
>  		i9xx_set_fifo_underrun_reporting(display, pipe, enable, old);
>  	else if (display->platform.ironlake || display->platform.sandybridge)
> @@ -379,6 +486,8 @@ void intel_cpu_fifo_underrun_irq_handler(struct intel_display *display,
>  		trace_intel_cpu_fifo_underrun(display, pipe);
>  
>  		drm_err(display->drm, "CPU pipe %c FIFO underrun\n", pipe_name(pipe));
> +
> +		read_underrun_dbg_info(display, pipe, true);
>  	}
>  
>  	intel_fbc_handle_fifo_underrun_irq(display);
> 
> -- 
> 2.51.0
> 

-- 
Matt Roper
Graphics Software Engineer
Linux GPU Platform Enablement
Intel Corporation

Re: [PATCH v5 4/8] drm/i915/xe3p_lpd: Handle underrun debug bits

[Matt Atwood]

On Wed, Nov 19, 2025 at 11:06:21AM -0800, Matt Roper wrote:
> On Fri, Nov 14, 2025 at 05:52:11PM -0300, Gustavo Sousa wrote:
> > Xe3p_LPD added several bits containing information that can be relevant
> > to debugging FIFO underruns.  Add the logic necessary to handle them
> > when reporting underruns.
> > 
> > This was adapted from the initial patch[1] from Sai Teja Pottumuttu.
> > 
> > [1] https://lore.kernel.org/all/20251015-xe3p_lpd-basic-enabling-v1-12-d2d1e26520aa@intel.com/
> > 
> > v2:
> >   - Handle FBC-related bits in intel_fbc.c. (Ville)
> >   - Do not use intel_fbc_id_for_pipe (promoted from
> >     skl_fbc_id_for_pipe), but use pipe's primary plane to get the FBC
> >     instance. (Ville, Matt)
> >   - Improve code readability by moving logic specific to logging fields
> >     of UNDERRUN_DBG1 to a separate function. (Jani)
> > 
> > Bspec: 69111, 69561, 74411, 74412
> > Cc: Jani Nikula <jani.nikula@intel.com>
> > Cc: Matt Roper <matthew.d.roper@intel.com>
> > Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > Signed-off-by: Gustavo Sousa <gustavo.sousa@intel.com>
> > ---
> > I tested this by adding a change on top of this series that updates
> > Xe3p_LPD's CDCLK table to use bad values and I got the following
> > messages:
> > 
> >     [  +0.000237] xe 0000:00:02.0: [drm:intel_modeset_verify_crtc [xe]] [CRTC:88:pipe A]
> >     [  +0.000674] xe 0000:00:02.0: [drm] *ERROR* CPU pipe A FIFO underrun
> >     [  +0.000015] xe 0000:00:02.0: [drm] *ERROR* Pipe A FIFO underrun info: DBUF block not valid on planes: [1]
> >     [  +0.000001] xe 0000:00:02.0: [drm] *ERROR* Pipe A FIFO underrun info: DDB empty on planes: [1]
> >     [  +0.000001] xe 0000:00:02.0: [drm] *ERROR* Pipe A FIFO underrun info: DBUF below WM0 on planes: [1]
> >     [  +0.000004] xe 0000:00:02.0: [drm] *ERROR* Pipe A FIFO underrun info: frame count: 1890, line count: 44
> > ---
> >  .../gpu/drm/i915/display/intel_display_device.h    |   1 +
> >  drivers/gpu/drm/i915/display/intel_display_regs.h  |  16 +++
> >  drivers/gpu/drm/i915/display/intel_fbc.c           |  50 ++++++++++
> >  drivers/gpu/drm/i915/display/intel_fbc.h           |   3 +
> >  drivers/gpu/drm/i915/display/intel_fbc_regs.h      |   2 +
> >  drivers/gpu/drm/i915/display/intel_fifo_underrun.c | 109 +++++++++++++++++++++
> >  6 files changed, 181 insertions(+)
> > 
> > diff --git a/drivers/gpu/drm/i915/display/intel_display_device.h b/drivers/gpu/drm/i915/display/intel_display_device.h
> > index b559ef43d547..91d8cfac5eff 100644
> > --- a/drivers/gpu/drm/i915/display/intel_display_device.h
> > +++ b/drivers/gpu/drm/i915/display/intel_display_device.h
> > @@ -197,6 +197,7 @@ struct intel_display_platforms {
> >  #define HAS_TRANSCODER(__display, trans)	((DISPLAY_RUNTIME_INFO(__display)->cpu_transcoder_mask & \
> >  						  BIT(trans)) != 0)
> >  #define HAS_UNCOMPRESSED_JOINER(__display)	(DISPLAY_VER(__display) >= 13)
> > +#define HAS_UNDERRUN_DBG_INFO(__display)	(DISPLAY_VER(__display) >= 35)
> >  #define HAS_ULTRAJOINER(__display)	(((__display)->platform.dgfx && \
> >  					  DISPLAY_VER(__display) == 14) && HAS_DSC(__display))
> >  #define HAS_VRR(__display)		(DISPLAY_VER(__display) >= 11)
> > diff --git a/drivers/gpu/drm/i915/display/intel_display_regs.h b/drivers/gpu/drm/i915/display/intel_display_regs.h
> > index 9d71e26a4fa2..89ea0156ee06 100644
> > --- a/drivers/gpu/drm/i915/display/intel_display_regs.h
> > +++ b/drivers/gpu/drm/i915/display/intel_display_regs.h
> > @@ -882,6 +882,21 @@
> >  #define   PIPE_MISC2_FLIP_INFO_PLANE_SEL_MASK		REG_GENMASK(2, 0) /* tgl+ */
> >  #define   PIPE_MISC2_FLIP_INFO_PLANE_SEL(plane_id)	REG_FIELD_PREP(PIPE_MISC2_FLIP_INFO_PLANE_SEL_MASK, (plane_id))
> >  
> > +#define _UNDERRUN_DBG1_A			0x70064
> > +#define _UNDERRUN_DBG1_B			0x71064
> > +#define UNDERRUN_DBG1(pipe)			_MMIO_PIPE(pipe, _UNDERRUN_DBG1_A, _UNDERRUN_DBG1_B)
> > +#define   UNDERRUN_DBUF_BLOCK_NOT_VALID_MASK	REG_GENMASK(29, 24)
> > +#define   UNDERRUN_DDB_EMPTY_MASK		REG_GENMASK(21, 16)
> > +#define   UNDERRUN_DBUF_NOT_FILLED_MASK		REG_GENMASK(13, 8)
> > +#define   UNDERRUN_BELOW_WM0_MASK		REG_GENMASK(5, 0)
> > +
> > +#define _UNDERRUN_DBG2_A			0x70068
> > +#define _UNDERRUN_DBG2_B			0x71068
> > +#define UNDERRUN_DBG2(pipe)			_MMIO_PIPE(pipe, _UNDERRUN_DBG2_A, _UNDERRUN_DBG2_B)
> > +#define   UNDERRUN_FRAME_LINE_COUNTERS_FROZEN	REG_BIT(31)
> > +#define   UNDERRUN_PIPE_FRAME_COUNT_MASK	REG_GENMASK(30, 20)
> > +#define   UNDERRUN_LINE_COUNT_MASK		REG_GENMASK(19, 0)
> > +
> >  #define DPINVGTT				_MMIO(VLV_DISPLAY_BASE + 0x7002c) /* VLV/CHV only */
> >  #define   DPINVGTT_EN_MASK_CHV				REG_GENMASK(27, 16)
> >  #define   DPINVGTT_EN_MASK_VLV				REG_GENMASK(23, 16)
> > @@ -1416,6 +1431,7 @@
> >  
> >  #define GEN12_DCPR_STATUS_1				_MMIO(0x46440)
> >  #define  XELPDP_PMDEMAND_INFLIGHT_STATUS		REG_BIT(26)
> > +#define  XE3P_UNDERRUN_PKGC				REG_BIT(21)
> >  
> >  #define FUSE_STRAP		_MMIO(0x42014)
> >  #define   ILK_INTERNAL_GRAPHICS_DISABLE	REG_BIT(31)
> > diff --git a/drivers/gpu/drm/i915/display/intel_fbc.c b/drivers/gpu/drm/i915/display/intel_fbc.c
> > index 437d2fda20a7..ec316f9843c6 100644
> > --- a/drivers/gpu/drm/i915/display/intel_fbc.c
> > +++ b/drivers/gpu/drm/i915/display/intel_fbc.c
> > @@ -129,6 +129,25 @@ struct intel_fbc {
> >  	const char *no_fbc_reason;
> >  };
> >  
> > +static struct intel_fbc *intel_fbc_for_pipe(struct intel_display *display, enum pipe pipe)
> > +{
> > +	struct intel_crtc *crtc = intel_crtc_for_pipe(display, pipe);
> > +	struct intel_plane *primary = NULL;
> > +	struct intel_plane *plane;
> > +
> > +	for_each_intel_plane_on_crtc(display->drm, crtc, plane) {
> > +		if (plane->base.type == DRM_PLANE_TYPE_PRIMARY) {
> 
> Can't we just use crtc->base.primary rather than looping to find it?
> While it's legal at the DRM layer for modern drivers to not register a
> primary plane (which in turn means no support for some pre-atomic KMS
> APIs), i915 has always always created and registered one in
> intel_crtc_init().  Other FBC code already uses the primary pointer to
> grab the FBC associated with a CRTC (intel_fbc_min_cdclk,
> intel_fbc_crtc_debugfs_add, etc.).
Yes, I think this is correct as well.
MattA
> 
> 
> Matt
> 
> > +			primary = plane;
> > +			break;
> > +		}
> > +	}
> > +
> > +	if (drm_WARN_ON(display->drm, !primary))
> > +		return NULL;
> > +
> > +	return primary->fbc;
> > +}
> > +
> >  /* plane stride in pixels */
> >  static unsigned int intel_fbc_plane_stride(const struct intel_plane_state *plane_state)
> >  {
> > @@ -2119,6 +2138,37 @@ void intel_fbc_handle_fifo_underrun_irq(struct intel_display *display)
> >  		__intel_fbc_handle_fifo_underrun_irq(fbc);
> >  }
> >  
> > +/**
> > + * intel_fbc_read_underrun_dbg_info - Read and log FBC-related FIFO underrun debug info
> > + * @display: display device instance
> > + * @pipe: the pipe possibly containing the FBC
> > + * @log: log the info?
> > + *
> > + * If @pipe does not contain an FBC instance, this function bails early.
> > + * Otherwise, FBC-related FIFO underrun is read and cleared, and then, if @log
> > + * is true, printed with error level.
> > + */
> > +void intel_fbc_read_underrun_dbg_info(struct intel_display *display,
> > +				      enum pipe pipe, bool log)
> > +{
> > +	struct intel_fbc *fbc = intel_fbc_for_pipe(display, pipe);
> > +	u32 val;
> > +
> > +	if (!fbc)
> > +		return;
> > +
> > +	val = intel_de_read(display, FBC_DEBUG_STATUS(fbc->id));
> > +	if (!(val & FBC_UNDERRUN_DECMPR))
> > +		return;
> > +
> > +	intel_de_write(display, FBC_DEBUG_STATUS(fbc->id), FBC_UNDERRUN_DECMPR);
> > +
> > +	if (log)
> > +		drm_err(display->drm,
> > +			"Pipe %c FIFO underrun info: FBC decompressing\n",
> > +			pipe_name(pipe));
> > +}
> > +
> >  /*
> >   * The DDX driver changes its behavior depending on the value it reads from
> >   * i915.enable_fbc, so sanitize it by translating the default value into either
> > diff --git a/drivers/gpu/drm/i915/display/intel_fbc.h b/drivers/gpu/drm/i915/display/intel_fbc.h
> > index 91424563206a..f0255ddae2b6 100644
> > --- a/drivers/gpu/drm/i915/display/intel_fbc.h
> > +++ b/drivers/gpu/drm/i915/display/intel_fbc.h
> > @@ -9,6 +9,7 @@
> >  #include <linux/types.h>
> >  
> >  enum fb_op_origin;
> > +enum pipe;
> >  struct intel_atomic_state;
> >  struct intel_crtc;
> >  struct intel_crtc_state;
> > @@ -46,6 +47,8 @@ void intel_fbc_flush(struct intel_display *display,
> >  		     unsigned int frontbuffer_bits, enum fb_op_origin origin);
> >  void intel_fbc_add_plane(struct intel_fbc *fbc, struct intel_plane *plane);
> >  void intel_fbc_handle_fifo_underrun_irq(struct intel_display *display);
> > +void intel_fbc_read_underrun_dbg_info(struct intel_display *display,
> > +				      enum pipe, bool log);
> >  void intel_fbc_reset_underrun(struct intel_display *display);
> >  void intel_fbc_crtc_debugfs_add(struct intel_crtc *crtc);
> >  void intel_fbc_debugfs_register(struct intel_display *display);
> > diff --git a/drivers/gpu/drm/i915/display/intel_fbc_regs.h b/drivers/gpu/drm/i915/display/intel_fbc_regs.h
> > index b1d0161a3196..77d8321c4fb3 100644
> > --- a/drivers/gpu/drm/i915/display/intel_fbc_regs.h
> > +++ b/drivers/gpu/drm/i915/display/intel_fbc_regs.h
> > @@ -88,6 +88,8 @@
> >  #define DPFC_FENCE_YOFF			_MMIO(0x3218)
> >  #define ILK_DPFC_FENCE_YOFF(fbc_id)	_MMIO_PIPE((fbc_id), 0x43218, 0x43258)
> >  #define DPFC_CHICKEN			_MMIO(0x3224)
> > +#define FBC_DEBUG_STATUS(fbc_id)	_MMIO_PIPE((fbc_id), 0x43220, 0x43260)
> > +#define   FBC_UNDERRUN_DECMPR			REG_BIT(27)
> >  #define ILK_DPFC_CHICKEN(fbc_id)	_MMIO_PIPE((fbc_id), 0x43224, 0x43264)
> >  #define   DPFC_HT_MODIFY			REG_BIT(31) /* pre-ivb */
> >  #define   DPFC_NUKE_ON_ANY_MODIFICATION		REG_BIT(23) /* bdw+ */
> > diff --git a/drivers/gpu/drm/i915/display/intel_fifo_underrun.c b/drivers/gpu/drm/i915/display/intel_fifo_underrun.c
> > index c2ce8461ac9e..b413b3e871d8 100644
> > --- a/drivers/gpu/drm/i915/display/intel_fifo_underrun.c
> > +++ b/drivers/gpu/drm/i915/display/intel_fifo_underrun.c
> > @@ -25,6 +25,8 @@
> >   *
> >   */
> >  
> > +#include <linux/seq_buf.h>
> > +
> >  #include <drm/drm_print.h>
> >  
> >  #include "i915_reg.h"
> > @@ -57,6 +59,100 @@
> >   * The code also supports underrun detection on the PCH transcoder.
> >   */
> >  
> > +#define UNDERRUN_DBG1_NUM_PLANES 6
> > +
> > +static void log_underrun_dbg1(struct intel_display *display, enum pipe pipe,
> > +			      unsigned long plane_mask, const char *info)
> > +{
> > +	DECLARE_SEQ_BUF(planes_desc, 32);
> > +	unsigned int i;
> > +
> > +	if (!plane_mask)
> > +		return;
> > +
> > +	for_each_set_bit(i, &plane_mask, UNDERRUN_DBG1_NUM_PLANES) {
> > +		if (i == 0)
> > +			seq_buf_puts(&planes_desc, "[C]");
> > +		else
> > +			seq_buf_printf(&planes_desc, "[%d]", i);
> > +	}
> > +
> > +	drm_err(display->drm, "Pipe %c FIFO underrun info: %s on planes: %s\n",
> > +		pipe_name(pipe), info, seq_buf_str(&planes_desc));
> > +
> > +	drm_WARN_ON(display->drm, seq_buf_has_overflowed(&planes_desc));
> > +}
> > +
> > +static void read_underrun_dbg1(struct intel_display *display, enum pipe pipe, bool log)
> > +{
> > +	u32 val = intel_de_read(display, UNDERRUN_DBG1(pipe));
> > +
> > +	if (!val)
> > +		return;
> > +
> > +	intel_de_write(display, UNDERRUN_DBG1(pipe), val);
> > +
> > +	if (!log)
> > +		return;
> > +
> > +	log_underrun_dbg1(display, pipe, REG_FIELD_GET(UNDERRUN_DBUF_BLOCK_NOT_VALID_MASK, val),
> > +			  "DBUF block not valid");
> > +	log_underrun_dbg1(display, pipe, REG_FIELD_GET(UNDERRUN_DDB_EMPTY_MASK, val),
> > +			  "DDB empty");
> > +	log_underrun_dbg1(display, pipe, REG_FIELD_GET(UNDERRUN_DBUF_NOT_FILLED_MASK, val),
> > +			  "DBUF not completely filled");
> > +	log_underrun_dbg1(display, pipe, REG_FIELD_GET(UNDERRUN_BELOW_WM0_MASK, val),
> > +			  "DBUF below WM0");
> > +}
> > +
> > +static void read_underrun_dbg2(struct intel_display *display, enum pipe pipe, bool log)
> > +{
> > +	u32 val = intel_de_read(display, UNDERRUN_DBG2(pipe));
> > +
> > +	if (!(val & UNDERRUN_FRAME_LINE_COUNTERS_FROZEN))
> > +		return;
> > +
> > +	intel_de_write(display, UNDERRUN_DBG2(pipe), UNDERRUN_FRAME_LINE_COUNTERS_FROZEN);
> > +
> > +	if (log)
> > +		drm_err(display->drm,
> > +			"Pipe %c FIFO underrun info: frame count: %u, line count: %u\n",
> > +			pipe_name(pipe),
> > +			REG_FIELD_GET(UNDERRUN_PIPE_FRAME_COUNT_MASK, val),
> > +			REG_FIELD_GET(UNDERRUN_LINE_COUNT_MASK, val));
> > +}
> > +
> > +static void read_underrun_dbg_pkgc(struct intel_display *display, bool log)
> > +{
> > +	u32 val = intel_de_read(display, GEN12_DCPR_STATUS_1);
> > +
> > +	if (!(val & XE3P_UNDERRUN_PKGC))
> > +		return;
> > +
> > +	/*
> > +	 * Note: If there are multiple pipes enabled, only one of them will see
> > +	 * XE3P_UNDERRUN_PKGC set.
> > +	 */
> > +	intel_de_write(display, GEN12_DCPR_STATUS_1, XE3P_UNDERRUN_PKGC);
> > +
> > +	if (log)
> > +		drm_err(display->drm,
> > +			"General FIFO underrun info: Package C-state blocking memory\n");
> > +}
> > +
> > +static void read_underrun_dbg_info(struct intel_display *display,
> > +				   enum pipe pipe,
> > +				   bool log)
> > +{
> > +	if (!HAS_UNDERRUN_DBG_INFO(display))
> > +		return;
> > +
> > +	read_underrun_dbg1(display, pipe, log);
> > +	read_underrun_dbg2(display, pipe, log);
> > +	intel_fbc_read_underrun_dbg_info(display, pipe, log);
> > +	read_underrun_dbg_pkgc(display, log);
> > +}
> > +
> >  static bool ivb_can_enable_err_int(struct intel_display *display)
> >  {
> >  	struct intel_crtc *crtc;
> > @@ -262,6 +358,17 @@ static bool __intel_set_cpu_fifo_underrun_reporting(struct intel_display *displa
> >  	old = !crtc->cpu_fifo_underrun_disabled;
> >  	crtc->cpu_fifo_underrun_disabled = !enable;
> >  
> > +	/*
> > +	 * The debug bits get latched at the time of the FIFO underrun ISR bit
> > +	 * getting set.  That means that any non-zero debug bit that is read when
> > +	 * handling a FIFO underrun interrupt has the potential to belong to
> > +	 * another underrun event (past or future).  To alleviate this problem,
> > +	 * let's clear existing bits before enabling the interrupt, so that at
> > +	 * least we don't get information that is too out-of-date.
> > +	 */
> > +	if (enable && !old)
> > +		read_underrun_dbg_info(display, pipe, false);
> > +
> >  	if (HAS_GMCH(display))
> >  		i9xx_set_fifo_underrun_reporting(display, pipe, enable, old);
> >  	else if (display->platform.ironlake || display->platform.sandybridge)
> > @@ -379,6 +486,8 @@ void intel_cpu_fifo_underrun_irq_handler(struct intel_display *display,
> >  		trace_intel_cpu_fifo_underrun(display, pipe);
> >  
> >  		drm_err(display->drm, "CPU pipe %c FIFO underrun\n", pipe_name(pipe));
> > +
> > +		read_underrun_dbg_info(display, pipe, true);
> >  	}
> >  
> >  	intel_fbc_handle_fifo_underrun_irq(display);
> > 
> > -- 
> > 2.51.0
> > 
> 
> -- 
> Matt Roper
> Graphics Software Engineer
> Linux GPU Platform Enablement
> Intel Corporation