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From: Imre Deak <imre.deak@intel.com>
To: <intel-gfx@lists.freedesktop.org>, <intel-xe@lists.freedesktop.org>
Cc: Suraj Kandpal <suraj.kandpal@intel.com>,
	Mika Kahola <mika.kahola@intel.com>
Subject: [PATCH 3/5] drm/i915/cx0: Use intel_port_to_tc() instead of open coding it
Date: Thu, 20 Nov 2025 19:23:56 +0200	[thread overview]
Message-ID: <20251120172358.1282765-3-imre.deak@intel.com> (raw)
In-Reply-To: <20251120172358.1282765-1-imre.deak@intel.com>

USe intel_port_to_tc() in mtl_port_to_pll_id(), instead of open coding
the same.

Cc: Suraj Kandpal <suraj.kandpal@intel.com>
Cc: Mika Kahola <mika.kahola@intel.com>
Signed-off-by: Imre Deak <imre.deak@intel.com>
---
 drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
index 8ae8cc7ad79d3..e0e5e5f65d193 100644
--- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
+++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
@@ -206,7 +206,7 @@ enum intel_dpll_id icl_tc_port_to_pll_id(enum tc_port tc_port)
 enum intel_dpll_id mtl_port_to_pll_id(struct intel_display *display, enum port port)
 {
 	if (port >= PORT_TC1)
-		return icl_tc_port_to_pll_id(port - PORT_TC1 + TC_PORT_1);
+		return icl_tc_port_to_pll_id(intel_port_to_tc(display, port));
 
 	switch (port) {
 	case PORT_A:
-- 
2.49.1


  parent reply	other threads:[~2025-11-20 17:24 UTC|newest]

Thread overview: 20+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2025-11-20 17:23 [PATCH 1/5] drm/i915/cx0: Fix port to PLL ID mapping on BMG Imre Deak
2025-11-20 17:23 ` [PATCH 2/5] drm/i915/tc: Add separate intel_tc_phy_port_to_tc() for TC DDI/PHY ports Imre Deak
2025-11-21  2:56   ` Kandpal, Suraj
2025-11-21 11:19   ` Jani Nikula
2025-11-21 15:26     ` Imre Deak
2025-11-20 17:23 ` Imre Deak [this message]
2025-11-21  3:08   ` [PATCH 3/5] drm/i915/cx0: Use intel_port_to_tc() instead of open coding it Kandpal, Suraj
2025-11-21 11:28   ` Jani Nikula
2025-11-21 15:30     ` Imre Deak
2025-11-20 17:23 ` [PATCH 4/5] drm/i915/cx0: Read out power-down state of both TXs in PHY lane 0 Imre Deak
2025-11-21  3:50   ` Kandpal, Suraj
2025-11-20 17:23 ` [PATCH 5/5] drm/i915/cx0: Read out power-down state of both PHY lanes for reversed lanes Imre Deak
2025-11-21  3:54   ` Kandpal, Suraj
2025-11-21  8:31     ` Imre Deak
2025-11-21  8:45       ` Kandpal, Suraj
2025-11-20 22:05 ` ✓ CI.KUnit: success for series starting with [1/5] drm/i915/cx0: Fix port to PLL ID mapping on BMG Patchwork
2025-11-20 22:20 ` ✗ CI.checksparse: warning " Patchwork
2025-11-20 22:44 ` ✓ Xe.CI.BAT: success " Patchwork
2025-11-21  3:43 ` ✗ Xe.CI.Full: failure " Patchwork
     [not found] ` <176372186635.17117.13640185361724504300@a3b018990fe9>
2025-11-21 19:47   ` ✗ i915.CI.Full: " Imre Deak

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