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From: Ashutosh Dixit <ashutosh.dixit@intel.com>
To: intel-xe@lists.freedesktop.org
Cc: Umesh Nerlige Ramappa <umesh.nerlige.ramappa@intel.com>
Subject: [PATCH 2/5] drm/xe/oa/uapi: Add gt_id to struct drm_xe_oa_unit
Date: Tue, 25 Nov 2025 19:52:17 -0800	[thread overview]
Message-ID: <20251126035220.13089-3-ashutosh.dixit@intel.com> (raw)
In-Reply-To: <20251126035220.13089-1-ashutosh.dixit@intel.com>

gt_id was previously omitted from 'struct drm_xe_oa_unit' because it could
be determine from hwe's attached to the OA unit. However, we now have OA
units which don't have any hwe's attached to them. Hence add gt_id to
'struct drm_xe_oa_unit' in order to provide this needed information to
userspace.

Signed-off-by: Ashutosh Dixit <ashutosh.dixit@intel.com>
---
 drivers/gpu/drm/xe/xe_query.c | 4 +++-
 include/uapi/drm/xe_drm.h     | 6 +++++-
 2 files changed, 8 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/xe/xe_query.c b/drivers/gpu/drm/xe/xe_query.c
index a7bf1fd6dd6ac..18bd8047ebfdb 100644
--- a/drivers/gpu/drm/xe/xe_query.c
+++ b/drivers/gpu/drm/xe/xe_query.c
@@ -682,7 +682,9 @@ static int query_oa_units(struct xe_device *xe,
 			du->capabilities = DRM_XE_OA_CAPS_BASE | DRM_XE_OA_CAPS_SYNCS |
 					   DRM_XE_OA_CAPS_OA_BUFFER_SIZE |
 					   DRM_XE_OA_CAPS_WAIT_NUM_REPORTS |
-					   DRM_XE_OA_CAPS_OAM;
+					   DRM_XE_OA_CAPS_OAM |
+					   DRM_XE_OA_CAPS_OA_UNIT_GT_ID;
+			du->gt_id = u->gt->info.id;
 			j = 0;
 			for_each_hw_engine(hwe, gt, hwe_id) {
 				if (!xe_hw_engine_is_reserved(hwe) &&
diff --git a/include/uapi/drm/xe_drm.h b/include/uapi/drm/xe_drm.h
index 47853659a705e..ec09b281eafe7 100644
--- a/include/uapi/drm/xe_drm.h
+++ b/include/uapi/drm/xe_drm.h
@@ -1676,12 +1676,16 @@ struct drm_xe_oa_unit {
 #define DRM_XE_OA_CAPS_OA_BUFFER_SIZE	(1 << 2)
 #define DRM_XE_OA_CAPS_WAIT_NUM_REPORTS	(1 << 3)
 #define DRM_XE_OA_CAPS_OAM		(1 << 4)
+#define DRM_XE_OA_CAPS_OA_UNIT_GT_ID	(1 << 5)
 
 	/** @oa_timestamp_freq: OA timestamp freq */
 	__u64 oa_timestamp_freq;
 
+	/** @gt_id: gt id for this OA unit */
+	__u64 gt_id;
+
 	/** @reserved: MBZ */
-	__u64 reserved[4];
+	__u64 reserved[3];
 
 	/** @num_engines: number of engines in @eci array */
 	__u64 num_engines;
-- 
2.48.1


  parent reply	other threads:[~2025-11-26  3:52 UTC|newest]

Thread overview: 18+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2025-11-26  3:52 [PATCH 0/5] OA: More OA and register whitelist changes Ashutosh Dixit
2025-11-26  3:52 ` [PATCH 1/5] drm/xe/oa: Use explicit struct initialization for struct xe_oa_regs Ashutosh Dixit
2025-11-26 18:41   ` Umesh Nerlige Ramappa
2025-11-26  3:52 ` Ashutosh Dixit [this message]
2025-11-26 20:14   ` [PATCH 2/5] drm/xe/oa/uapi: Add gt_id to struct drm_xe_oa_unit Umesh Nerlige Ramappa
2025-11-26 20:42   ` Matthew Brost
2025-11-26 23:08     ` Dixit, Ashutosh
2025-12-01 18:01       ` Rodrigo Vivi
2025-11-26  3:52 ` [PATCH 3/5] drm/xe/oa: Allow exec_queue's to be specified only for OAG OA unit Ashutosh Dixit
2025-11-26 20:15   ` Umesh Nerlige Ramappa
2025-11-26  3:52 ` [PATCH 4/5] drm/xe/rtp: Refactor OAG MMIO trigger register whitelisting Ashutosh Dixit
2025-11-26 21:49   ` Umesh Nerlige Ramappa
2025-11-26  3:52 ` [PATCH 5/5] drm/xe/rtp: Whitelist OAM MMIO trigger registers Ashutosh Dixit
2025-11-26 21:53   ` Umesh Nerlige Ramappa
2025-11-26  5:35 ` ✗ CI.checkpatch: warning for OA: More OA and register whitelist changes Patchwork
2025-11-26  5:36 ` ✓ CI.KUnit: success " Patchwork
2025-11-26  6:14 ` ✓ Xe.CI.BAT: " Patchwork
2025-11-26  9:02 ` ✗ Xe.CI.Full: failure " Patchwork

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