From: Arun R Murthy <arun.r.murthy@intel.com>
To: "Maarten Lankhorst" <maarten.lankhorst@linux.intel.com>,
"Maxime Ripard" <mripard@kernel.org>,
"Thomas Zimmermann" <tzimmermann@suse.de>,
"David Airlie" <airlied@gmail.com>,
"Simona Vetter" <simona@ffwll.ch>,
"Harry Wentland" <harry.wentland@amd.com>,
"Leo Li" <sunpeng.li@amd.com>,
"Rodrigo Siqueira" <siqueira@igalia.com>,
"Alex Deucher" <alexander.deucher@amd.com>,
"Christian König" <christian.koenig@amd.com>,
"Jani Nikula" <jani.nikula@linux.intel.com>,
"Rodrigo Vivi" <rodrigo.vivi@intel.com>,
"Joonas Lahtinen" <joonas.lahtinen@linux.intel.com>,
"Tvrtko Ursulin" <tursulin@ursulin.net>,
"Lucas De Marchi" <lucas.demarchi@intel.com>,
"Thomas Hellström" <thomas.hellstrom@linux.intel.com>,
uma.shankar@intel.com, chaitanya.kumar.borah@intel.com,
suraj.kandpal@intel.com
Cc: dri-devel@lists.freedesktop.org, amd-gfx@lists.freedesktop.org,
intel-gfx@lists.freedesktop.org, intel-xe@lists.freedesktop.org,
Arun R Murthy <arun.r.murthy@intel.com>
Subject: [PATCH [RESEND] v9 02/20] drm: Define histogram structures exposed to user
Date: Tue, 02 Dec 2025 11:56:56 +0530 [thread overview]
Message-ID: <20251202-dpst-v9-2-f2abb2ca2465@intel.com> (raw)
In-Reply-To: <20251202-dpst-v9-0-f2abb2ca2465@intel.com>
Display Histogram is an array of bins and can be generated in many ways
referred to as modes.
Ex: HSV max(RGB), Wighted RGB etc.
Understanding the histogram data format(Ex: HSV max(RGB))
Histogram is just the pixel count.
For a maximum resolution of 10k (10240 x 4320 = 44236800)
25 bits should be sufficient to represent this along with a buffer of 7
bits(future use) u32 is being considered.
max(RGB) can be 255 i.e 0xFF 8 bit, considering the most significant 5
bits, hence 32 bins.
Below mentioned algorithm illustrates the histogram generation in
hardware.
hist[32] = {0};
for (i = 0; i < resolution; i++) {
bin = max(RGB[i]);
bin = bin >> 3; /* consider the most significant bits */
hist[bin]++;
}
If the entire image is Red color then max(255,0,0) is 255 so the pixel
count of each pixels will be placed in the last bin. Hence except
hist[31] all other bins will have a value zero.
Generated histogram in this case would be hist[32] = {0,0,....44236800}
Description of the structures, properties defined are documented in the
header file include/uapi/drm/drm_mode.h
v8: Added doc for HDR planes, removed reserved variables (Dmitry)
Signed-off-by: Arun R Murthy <arun.r.murthy@intel.com>
---
include/uapi/drm/drm_mode.h | 65 +++++++++++++++++++++++++++++++++++++++++++++
1 file changed, 65 insertions(+)
diff --git a/include/uapi/drm/drm_mode.h b/include/uapi/drm/drm_mode.h
index cbbbfc1dfe2b806c641c720b0215e825e350bd03..aa24fef15da708f3e6804d07ffae5b0312dfdce0 100644
--- a/include/uapi/drm/drm_mode.h
+++ b/include/uapi/drm/drm_mode.h
@@ -1545,6 +1545,71 @@ struct drm_mode_closefb {
__u32 pad;
};
+/**
+ * enum drm_mode_histogram
+ *
+ * @DRM_MODE_HISTOGRAM_HSV_MAX_RGB:
+ * Maximum resolution at present 10k, 10240x4320 = 44236800
+ * can be denoted in 25bits. With an additional 7 bits in buffer each bin
+ * can be a u32 value.
+ * For SDL, Maximum value of max(RGB) is 255, so max 255 bins.
+ * If the most significant 5 bits are considered, then bins = 2^5
+ * will be 32 bins.
+ * For HDR, maximum value of max(RGB) is 65535, so max 65535 bins.
+ * For illustration consider a full RED image of 10k resolution considering all
+ * 8 bits histogram would look like hist[255] = {0,0,....44236800} with SDR
+ * plane similarly with HDR the same would look like hist[65535] =
+ * {0,0,0,....44236800}
+ */
+enum drm_mode_histogram {
+ DRM_MODE_HISTOGRAM_HSV_MAX_RGB = 0x01,
+};
+
+/**
+ * struct drm_histogram_caps
+ *
+ * @histogram_mode: histogram generation modes, defined in the
+ * enum drm_mode_histogram
+ * @bins_count: number of bins for a chosen histogram mode. For illustration
+ * refer the above defined histogram mode.
+ */
+struct drm_histogram_caps {
+ __u32 histogram_mode;
+ __u32 bins_count;
+};
+
+/**
+ * struct drm_histogram_config
+ *
+ * @hist_mode_data: address to the histogram mode specific data if any
+ * @nr_hist_mode_data: number of elements pointed by the address in
+ * hist_mode_data
+ * @hist_mode: histogram mode(HSV max(RGB), RGB, LUMA etc)
+ * @enable: flag to enable/disable histogram
+ */
+struct drm_histogram_config {
+ __u64 hist_mode_data;
+ __u32 nr_hist_mode_data;
+ enum drm_mode_histogram hist_mode;
+ bool enable;
+};
+
+/**
+ * struct drm_histogram
+ *
+ * @config: histogram configuration data pointed by struct drm_histogram_config
+ * @data_ptr: pointer to the array of histogram.
+ * Histogram is an array of bins. Data format for each bin depends
+ * on the histogram mode. Refer to the above histogram modes for
+ * more information.
+ * @nr_elements: number of bins in the histogram.
+ */
+struct drm_histogram {
+ struct drm_histogram_config config;
+ __u64 data_ptr;
+ __u32 nr_elements;
+};
+
#if defined(__cplusplus)
}
#endif
--
2.25.1
next prev parent reply other threads:[~2025-12-02 6:26 UTC|newest]
Thread overview: 27+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-12-02 6:26 [PATCH RESEND v9 00/20] Display Global Histogram Arun R Murthy
2025-12-02 6:26 ` [PATCH [RESEND] v9 01/20] DO_NOT_REVIEW: plane/crtc color pipeline Arun R Murthy
2025-12-02 6:26 ` Arun R Murthy [this message]
2025-12-10 9:35 ` [PATCH [RESEND] v9 02/20] drm: Define histogram structures exposed to user Jani Nikula
2025-12-02 6:26 ` [PATCH [RESEND] v9 03/20] drm: Add new element histogram for colorop Arun R Murthy
2025-12-02 6:26 ` [PATCH [RESEND] v9 04/20] drm/colorop: Export function to create pipeline element histogram Arun R Murthy
2025-12-02 6:26 ` [PATCH [RESEND] v9 05/20] drm: Define ImageEnhancemenT LUT structures exposed to user Arun R Murthy
2025-12-02 6:27 ` [PATCH [RESEND] v9 06/20] drm: Add new element Image EnhancemenT for colorop Arun R Murthy
2025-12-02 6:27 ` [PATCH [RESEND] v9 07/20] drm/colorop: Export function to create pipeline element iet lut Arun R Murthy
2025-12-02 6:27 ` [PATCH [RESEND] v9 08/20] drm/i915/histogram: Define registers for histogram Arun R Murthy
2025-12-02 6:27 ` [PATCH [RESEND] v9 09/20] drm/i915/histogram: Add support " Arun R Murthy
2025-12-02 6:27 ` [PATCH [RESEND] v9 10/20] drm/xe: Add histogram support to Xe builds Arun R Murthy
2025-12-02 6:27 ` [PATCH [RESEND] v9 11/20] drm/i915/histogram: histogram interrupt handling Arun R Murthy
2025-12-02 6:27 ` [PATCH DO_NOT_RTEVIEW [RESEND] v9 12/20] Plane Color Pipeline support for Intel platforms Arun R Murthy
2025-12-02 6:27 ` [PATCH [RESEND] v9 13/20] drm/i915/colorop: Add crtc color pipeline for i915 Arun R Murthy
2025-12-02 6:27 ` [PATCH [RESEND] v9 14/20] drm/i915/histogram: Hook i915 histogram with drm histogram Arun R Murthy
2025-12-02 6:27 ` [PATCH [RESEND] v9 15/20] drm/i915/iet: Add support to writing the IET LUT data Arun R Murthy
2025-12-02 6:27 ` [PATCH [RESEND] v9 16/20] drm/i915/colorop: create IET LUT properties Arun R Murthy
2025-12-02 6:27 ` [PATCH [RESEND] v9 17/20] drm/i915/crtc: Hook i915 IET LUT with the drm IET properties Arun R Murthy
2025-12-02 6:27 ` [PATCH [RESEND] v9 18/20] drm/i915/histogram: histogram delay counter doesn't reset Arun R Murthy
2025-12-02 6:27 ` [PATCH [RESEND] v9 19/20] drm/i915/histogram: Histogram changes for Display 20+ Arun R Murthy
2025-12-02 6:27 ` [PATCH [RESEND] v9 20/20] drm/i915/histogram: Enable pipe dithering Arun R Murthy
2025-12-02 6:32 ` ✗ CI.checkpatch: warning for v9 19/20] drm/i915/histogram: Histogram changes for Display 20+ Patchwork
2025-12-02 6:34 ` ✓ CI.KUnit: success for v9 20/20] drm/i915/histogram: Enable pipe dithering Patchwork
2025-12-02 6:48 ` ✗ CI.checksparse: warning " Patchwork
2025-12-02 7:35 ` ✓ Xe.CI.BAT: success " Patchwork
2025-12-02 9:17 ` ✓ Xe.CI.Full: " Patchwork
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