From: Imre Deak <imre.deak@intel.com>
To: <intel-gfx@lists.freedesktop.org>, <intel-xe@lists.freedesktop.org>
Cc: <dri-devel@lists.freedesktop.org>,
Luca Coelho <luciano.coelho@intel.com>
Subject: [PATCH 01/16] drm/dp: Parse all DSC slice count caps for eDP 1.5
Date: Mon, 15 Dec 2025 21:23:41 +0200 [thread overview]
Message-ID: <20251215192357.172201-2-imre.deak@intel.com> (raw)
In-Reply-To: <20251215192357.172201-1-imre.deak@intel.com>
eDP 1.5 supports all the slice counts reported via DP_DSC_SLICE_CAP_1,
so adjust drm_dp_dsc_sink_max_slice_count() accordingly.
Cc: dri-devel@lists.freedesktop.org
Reviewed-by: Luca Coelho <luciano.coelho@intel.com>
Signed-off-by: Imre Deak <imre.deak@intel.com>
---
drivers/gpu/drm/display/drm_dp_helper.c | 41 +++++++++++--------------
1 file changed, 18 insertions(+), 23 deletions(-)
diff --git a/drivers/gpu/drm/display/drm_dp_helper.c b/drivers/gpu/drm/display/drm_dp_helper.c
index f9fdf19de74a9..19564c1afba6c 100644
--- a/drivers/gpu/drm/display/drm_dp_helper.c
+++ b/drivers/gpu/drm/display/drm_dp_helper.c
@@ -2725,15 +2725,7 @@ u8 drm_dp_dsc_sink_max_slice_count(const u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE],
{
u8 slice_cap1 = dsc_dpcd[DP_DSC_SLICE_CAP_1 - DP_DSC_SUPPORT];
- if (is_edp) {
- /* For eDP, register DSC_SLICE_CAPABILITIES_1 gives slice count */
- if (slice_cap1 & DP_DSC_4_PER_DP_DSC_SINK)
- return 4;
- if (slice_cap1 & DP_DSC_2_PER_DP_DSC_SINK)
- return 2;
- if (slice_cap1 & DP_DSC_1_PER_DP_DSC_SINK)
- return 1;
- } else {
+ if (!is_edp) {
/* For DP, use values from DSC_SLICE_CAP_1 and DSC_SLICE_CAP2 */
u8 slice_cap2 = dsc_dpcd[DP_DSC_SLICE_CAP_2 - DP_DSC_SUPPORT];
@@ -2743,22 +2735,25 @@ u8 drm_dp_dsc_sink_max_slice_count(const u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE],
return 20;
if (slice_cap2 & DP_DSC_16_PER_DP_DSC_SINK)
return 16;
- if (slice_cap1 & DP_DSC_12_PER_DP_DSC_SINK)
- return 12;
- if (slice_cap1 & DP_DSC_10_PER_DP_DSC_SINK)
- return 10;
- if (slice_cap1 & DP_DSC_8_PER_DP_DSC_SINK)
- return 8;
- if (slice_cap1 & DP_DSC_6_PER_DP_DSC_SINK)
- return 6;
- if (slice_cap1 & DP_DSC_4_PER_DP_DSC_SINK)
- return 4;
- if (slice_cap1 & DP_DSC_2_PER_DP_DSC_SINK)
- return 2;
- if (slice_cap1 & DP_DSC_1_PER_DP_DSC_SINK)
- return 1;
}
+ /* DP, eDP v1.5+ */
+ if (slice_cap1 & DP_DSC_12_PER_DP_DSC_SINK)
+ return 12;
+ if (slice_cap1 & DP_DSC_10_PER_DP_DSC_SINK)
+ return 10;
+ if (slice_cap1 & DP_DSC_8_PER_DP_DSC_SINK)
+ return 8;
+ if (slice_cap1 & DP_DSC_6_PER_DP_DSC_SINK)
+ return 6;
+ /* DP, eDP v1.4+ */
+ if (slice_cap1 & DP_DSC_4_PER_DP_DSC_SINK)
+ return 4;
+ if (slice_cap1 & DP_DSC_2_PER_DP_DSC_SINK)
+ return 2;
+ if (slice_cap1 & DP_DSC_1_PER_DP_DSC_SINK)
+ return 1;
+
return 0;
}
EXPORT_SYMBOL(drm_dp_dsc_sink_max_slice_count);
--
2.49.1
next prev parent reply other threads:[~2025-12-15 19:24 UTC|newest]
Thread overview: 26+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-12-15 19:23 [PATCH 00/16] drm/i915/dp: Clean up link BW/DSC slice config computation (fixes) Imre Deak
2025-12-15 19:23 ` Imre Deak [this message]
2025-12-15 19:23 ` [PATCH 02/16] drm/dp: Add drm_dp_dsc_sink_slice_count_mask() Imre Deak
2025-12-15 19:23 ` [PATCH 03/16] drm/i915/dp: Fix DSC sink's slice count capability check Imre Deak
2025-12-15 19:23 ` [PATCH 04/16] drm/i915/dp: Return a fixed point BPP value from intel_dp_output_bpp() Imre Deak
2025-12-15 19:23 ` [PATCH 05/16] drm/i915/dp: Use a mode's crtc_clock vs. clock during state computation Imre Deak
2025-12-15 19:23 ` [PATCH 06/16] drm/i915/dp: Factor out intel_dp_link_bw_overhead() Imre Deak
2025-12-15 19:23 ` [PATCH 07/16] drm/i915/dp: Fix BW check in is_bw_sufficient_for_dsc_config() Imre Deak
2025-12-15 19:23 ` [PATCH 08/16] drm/i915/dp: Use the effective data rate for DP BW calculation Imre Deak
2025-12-15 19:23 ` [PATCH 09/16] drm/i915/dp: Use the effective data rate for DP compressed " Imre Deak
2025-12-15 19:23 ` [PATCH 10/16] drm/i915/dp: Account with MST, SSC BW overhead for uncompressed DP-MST stream BW Imre Deak
2025-12-15 19:23 ` [PATCH 11/16] drm/i915/dp: Account with DSC BW overhead for compressed DP-SST " Imre Deak
2025-12-15 19:23 ` [PATCH 12/16] drm/i915/dp: Account with pipe joiner max compressed BPP limit for DP-MST and eDP Imre Deak
2025-12-15 19:23 ` [PATCH 13/16] drm/i915/dp: Fail state computation for invalid min/max link BPP values Imre Deak
2025-12-15 19:23 ` [PATCH 14/16] drm/i915/dp: Fail state computation for invalid max throughput BPP value Imre Deak
2025-12-15 19:23 ` [PATCH 15/16] drm/i915/dp: Fail state computation for invalid max sink compressed " Imre Deak
2025-12-15 19:23 ` [PATCH 16/16] drm/i915/dp: Fail state computation for invalid DSC source input BPP values Imre Deak
2025-12-15 22:16 ` ✗ CI.checkpatch: warning for drm/i915/dp: Clean up link BW/DSC slice config computation (fixes) Patchwork
2025-12-15 22:17 ` ✓ CI.KUnit: success " Patchwork
2025-12-15 22:36 ` ✗ CI.checksparse: warning " Patchwork
2025-12-15 23:31 ` ✓ Xe.CI.BAT: success " Patchwork
2025-12-16 9:27 ` ✗ Xe.CI.Full: failure " Patchwork
2025-12-16 17:30 ` [PATCH 00/16] " Imre Deak
2025-12-18 12:00 ` Imre Deak
2025-12-19 13:28 ` Maarten Lankhorst
[not found] ` <176585164976.91286.8511052780566467299@a3b018990fe9>
2025-12-19 15:21 ` ✓ i915.CI.Full: success for " Imre Deak
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