From: Uma Shankar <uma.shankar@intel.com>
To: intel-gfx@lists.freedesktop.org, intel-xe@lists.freedesktop.org
Cc: jani.nikula@intel.com, ville.syrjala@linux.intel.com,
Uma Shankar <uma.shankar@intel.com>
Subject: [PATCH 16/19] drm/{i915, xe}: Remove i915_reg.h from intel_display_irq.c
Date: Wed, 17 Dec 2025 11:52:06 +0530 [thread overview]
Message-ID: <20251217062209.852324-17-uma.shankar@intel.com> (raw)
In-Reply-To: <20251217062209.852324-1-uma.shankar@intel.com>
Move VLV_IRQ_REGS to common header to make intel_display_irq.c
free from including i915_reg.h.
Signed-off-by: Uma Shankar <uma.shankar@intel.com>
---
.../gpu/drm/i915/display/intel_display_irq.c | 2 +-
.../gpu/drm/i915/display/intel_display_regs.h | 28 +++++-----
drivers/gpu/drm/i915/i915_reg.h | 52 ------------------
include/drm/intel/intel_gmd_common_regs.h | 55 +++++++++++++++++++
4 files changed, 70 insertions(+), 67 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display_irq.c b/drivers/gpu/drm/i915/display/intel_display_irq.c
index 9adeebb376b1..206c0d004646 100644
--- a/drivers/gpu/drm/i915/display/intel_display_irq.c
+++ b/drivers/gpu/drm/i915/display/intel_display_irq.c
@@ -5,8 +5,8 @@
#include <drm/drm_print.h>
#include <drm/drm_vblank.h>
+#include <drm/intel/intel_gmd_common_regs.h>
-#include "i915_reg.h"
#include "icl_dsi_regs.h"
#include "intel_crtc.h"
#include "intel_de.h"
diff --git a/drivers/gpu/drm/i915/display/intel_display_regs.h b/drivers/gpu/drm/i915/display/intel_display_regs.h
index ecae358c5b0e..b433982cee56 100644
--- a/drivers/gpu/drm/i915/display/intel_display_regs.h
+++ b/drivers/gpu/drm/i915/display/intel_display_regs.h
@@ -82,20 +82,6 @@
#define DERRMR_PIPEC_VBLANK (1 << 21)
#define DERRMR_PIPEC_HBLANK (1 << 22)
-#define VLV_IRQ_REGS I915_IRQ_REGS(VLV_IMR, \
- VLV_IER, \
- VLV_IIR)
-
-#define VLV_EIR _MMIO(VLV_DISPLAY_BASE + 0x20b0)
-#define VLV_EMR _MMIO(VLV_DISPLAY_BASE + 0x20b4)
-#define VLV_ESR _MMIO(VLV_DISPLAY_BASE + 0x20b8)
-#define VLV_ERROR_GUNIT_TLB_DATA (1 << 6)
-#define VLV_ERROR_GUNIT_TLB_PTE (1 << 5)
-#define VLV_ERROR_PAGE_TABLE (1 << 4)
-#define VLV_ERROR_CLAIM (1 << 0)
-
-#define VLV_ERROR_REGS I915_ERROR_REGS(VLV_EMR, VLV_EIR)
-
#define _MBUS_ABOX0_CTL 0x45038
#define _MBUS_ABOX1_CTL 0x45048
#define _MBUS_ABOX2_CTL 0x4504C
@@ -3009,4 +2995,18 @@ enum skl_power_gate {
#define FW_BLC_SELF_FIFO_MASK REG_BIT(16) /* 945 only */
#define FW_BLC_SELF_EN REG_BIT(15) /* 945 only */
+#define VLV_IRQ_REGS I915_IRQ_REGS(VLV_IMR, \
+ VLV_IER, \
+ VLV_IIR)
+
+#define VLV_EIR _MMIO(VLV_DISPLAY_BASE + 0x20b0)
+#define VLV_EMR _MMIO(VLV_DISPLAY_BASE + 0x20b4)
+#define VLV_ESR _MMIO(VLV_DISPLAY_BASE + 0x20b8)
+#define VLV_ERROR_GUNIT_TLB_DATA (1 << 6)
+#define VLV_ERROR_GUNIT_TLB_PTE (1 << 5)
+#define VLV_ERROR_PAGE_TABLE (1 << 4)
+#define VLV_ERROR_CLAIM (1 << 0)
+
+#define VLV_ERROR_REGS I915_ERROR_REGS(VLV_EMR, VLV_EIR)
+
#endif /* __INTEL_DISPLAY_REGS_H__ */
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index ef2b33bbebee..44df40e25e37 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -336,9 +336,6 @@
#define VLV_GU_CTL0 _MMIO(VLV_DISPLAY_BASE + 0x2030)
#define VLV_GU_CTL1 _MMIO(VLV_DISPLAY_BASE + 0x2034)
-#define SCPD0 _MMIO(0x209c) /* 915+ only */
-#define SCPD_FBC_IGNORE_3D (1 << 6)
-#define CSTATE_RENDER_CLOCK_GATE_DISABLE (1 << 5)
#define GEN2_IER _MMIO(0x20a0)
#define GEN2_IIR _MMIO(0x20a4)
#define GEN2_IMR _MMIO(0x20a8)
@@ -352,13 +349,6 @@
#define GINT_DIS (1 << 22)
#define GCFG_DIS (1 << 8)
#define VLV_GUNIT_CLOCK_GATE2 _MMIO(VLV_DISPLAY_BASE + 0x2064)
-#define VLV_IIR_RW _MMIO(VLV_DISPLAY_BASE + 0x2084)
-#define VLV_IER _MMIO(VLV_DISPLAY_BASE + 0x20a0)
-#define VLV_IIR _MMIO(VLV_DISPLAY_BASE + 0x20a4)
-#define VLV_IMR _MMIO(VLV_DISPLAY_BASE + 0x20a8)
-#define VLV_ISR _MMIO(VLV_DISPLAY_BASE + 0x20ac)
-#define VLV_PCBR _MMIO(VLV_DISPLAY_BASE + 0x2120)
-#define VLV_PCBR_ADDR_SHIFT 12
#define EIR _MMIO(0x20b0)
#define EMR _MMIO(0x20b4)
@@ -683,11 +673,6 @@
#define PCH_3DCGDIS1 _MMIO(0x46024)
# define VFMUNIT_CLOCK_GATE_DISABLE (1 << 11)
-/* Display Internal Timeout Register */
-#define RM_TIMEOUT _MMIO(0x42060)
-#define RM_TIMEOUT_REG_CAPTURE _MMIO(0x420E0)
-#define MMIO_TIMEOUT_US(us) ((us) << 0)
-
#define VLV_MASTER_IER _MMIO(0x4400c) /* Gunit master IER */
#define MASTER_INTERRUPT_ENABLE (1 << 31)
@@ -700,24 +685,6 @@
GTIER, \
GTIIR)
-#define GEN8_MASTER_IRQ _MMIO(0x44200)
-#define GEN8_MASTER_IRQ_CONTROL (1 << 31)
-#define GEN8_PCU_IRQ (1 << 30)
-#define GEN8_DE_PCH_IRQ (1 << 23)
-#define GEN8_DE_MISC_IRQ (1 << 22)
-#define GEN8_DE_PORT_IRQ (1 << 20)
-#define GEN8_DE_PIPE_C_IRQ (1 << 18)
-#define GEN8_DE_PIPE_B_IRQ (1 << 17)
-#define GEN8_DE_PIPE_A_IRQ (1 << 16)
-#define GEN8_DE_PIPE_IRQ(pipe) (1 << (16 + (pipe)))
-#define GEN8_GT_VECS_IRQ (1 << 6)
-#define GEN8_GT_GUC_IRQ (1 << 5)
-#define GEN8_GT_PM_IRQ (1 << 4)
-#define GEN8_GT_VCS1_IRQ (1 << 3) /* NB: VCS2 in bspec! */
-#define GEN8_GT_VCS0_IRQ (1 << 2) /* NB: VCS1 in bpsec! */
-#define GEN8_GT_BCS_IRQ (1 << 1)
-#define GEN8_GT_RCS_IRQ (1 << 0)
-
#define GEN8_GT_ISR(which) _MMIO(0x44300 + (0x10 * (which)))
#define GEN8_GT_IMR(which) _MMIO(0x44304 + (0x10 * (which)))
#define GEN8_GT_IIR(which) _MMIO(0x44308 + (0x10 * (which)))
@@ -743,25 +710,6 @@
GEN8_PCU_IER, \
GEN8_PCU_IIR)
-#define GEN11_GU_MISC_ISR _MMIO(0x444f0)
-#define GEN11_GU_MISC_IMR _MMIO(0x444f4)
-#define GEN11_GU_MISC_IIR _MMIO(0x444f8)
-#define GEN11_GU_MISC_IER _MMIO(0x444fc)
-#define GEN11_GU_MISC_GSE (1 << 27)
-
-#define GEN11_GU_MISC_IRQ_REGS I915_IRQ_REGS(GEN11_GU_MISC_IMR, \
- GEN11_GU_MISC_IER, \
- GEN11_GU_MISC_IIR)
-
-#define GEN11_GFX_MSTR_IRQ _MMIO(0x190010)
-#define GEN11_MASTER_IRQ (1 << 31)
-#define GEN11_PCU_IRQ (1 << 30)
-#define GEN11_GU_MISC_IRQ (1 << 29)
-#define GEN11_DISPLAY_IRQ (1 << 16)
-#define GEN11_GT_DW_IRQ(x) (1 << (x))
-#define GEN11_GT_DW1_IRQ (1 << 1)
-#define GEN11_GT_DW0_IRQ (1 << 0)
-
#define DG1_MSTR_TILE_INTR _MMIO(0x190008)
#define DG1_MSTR_IRQ REG_BIT(31)
#define DG1_MSTR_TILE(t) REG_BIT(t)
diff --git a/include/drm/intel/intel_gmd_common_regs.h b/include/drm/intel/intel_gmd_common_regs.h
index db7a03699bcb..5a42b473de8a 100644
--- a/include/drm/intel/intel_gmd_common_regs.h
+++ b/include/drm/intel/intel_gmd_common_regs.h
@@ -233,6 +233,10 @@
#define GMD_ID_STEP REG_GENMASK(5, 0)
#define GEN2_ISR _MMIO(0x20ac)
+#define SCPD0 _MMIO(0x209c) /* 915+ only */
+#define SCPD_FBC_IGNORE_3D (1 << 6)
+#define CSTATE_RENDER_CLOCK_GATE_DISABLE (1 << 5)
+
#define I915_PM_INTERRUPT (1 << 31)
#define I915_ISP_INTERRUPT (1 << 22)
@@ -348,4 +352,55 @@
#define ERR_INT_FIFO_UNDERRUN_A (1 << 0)
#define ERR_INT_FIFO_UNDERRUN(pipe) (1 << ((pipe) * 3))
+#define VLV_IIR_RW _MMIO(VLV_DISPLAY_BASE + 0x2084)
+#define VLV_IER _MMIO(VLV_DISPLAY_BASE + 0x20a0)
+#define VLV_IIR _MMIO(VLV_DISPLAY_BASE + 0x20a4)
+#define VLV_IMR _MMIO(VLV_DISPLAY_BASE + 0x20a8)
+#define VLV_ISR _MMIO(VLV_DISPLAY_BASE + 0x20ac)
+#define VLV_PCBR _MMIO(VLV_DISPLAY_BASE + 0x2120)
+#define VLV_PCBR_ADDR_SHIFT 12
+
+#define GEN8_MASTER_IRQ _MMIO(0x44200)
+#define GEN8_MASTER_IRQ_CONTROL (1 << 31)
+#define GEN8_PCU_IRQ (1 << 30)
+#define GEN8_DE_PCH_IRQ (1 << 23)
+#define GEN8_DE_MISC_IRQ (1 << 22)
+#define GEN8_DE_PORT_IRQ (1 << 20)
+#define GEN8_DE_PIPE_C_IRQ (1 << 18)
+#define GEN8_DE_PIPE_B_IRQ (1 << 17)
+#define GEN8_DE_PIPE_A_IRQ (1 << 16)
+#define GEN8_DE_PIPE_IRQ(pipe) (1 << (16 + (pipe)))
+#define GEN8_GT_VECS_IRQ (1 << 6)
+#define GEN8_GT_GUC_IRQ (1 << 5)
+#define GEN8_GT_PM_IRQ (1 << 4)
+#define GEN8_GT_VCS1_IRQ (1 << 3) /* NB: VCS2 in bspec! */
+#define GEN8_GT_VCS0_IRQ (1 << 2) /* NB: VCS1 in bpsec! */
+#define GEN8_GT_BCS_IRQ (1 << 1)
+#define GEN8_GT_RCS_IRQ (1 << 0)
+
+
+#define GEN11_GU_MISC_ISR _MMIO(0x444f0)
+#define GEN11_GU_MISC_IMR _MMIO(0x444f4)
+#define GEN11_GU_MISC_IIR _MMIO(0x444f8)
+#define GEN11_GU_MISC_IER _MMIO(0x444fc)
+#define GEN11_GU_MISC_GSE (1 << 27)
+
+#define GEN11_GU_MISC_IRQ_REGS I915_IRQ_REGS(GEN11_GU_MISC_IMR, \
+ GEN11_GU_MISC_IER, \
+ GEN11_GU_MISC_IIR)
+
+/* Display Internal Timeout Register */
+#define RM_TIMEOUT _MMIO(0x42060)
+#define RM_TIMEOUT_REG_CAPTURE _MMIO(0x420E0)
+#define MMIO_TIMEOUT_US(us) ((us) << 0)
+
+#define GEN11_GFX_MSTR_IRQ _MMIO(0x190010)
+#define GEN11_MASTER_IRQ (1 << 31)
+#define GEN11_PCU_IRQ (1 << 30)
+#define GEN11_GU_MISC_IRQ (1 << 29)
+#define GEN11_DISPLAY_IRQ (1 << 16)
+#define GEN11_GT_DW_IRQ(x) (1 << (x))
+#define GEN11_GT_DW1_IRQ (1 << 1)
+#define GEN11_GT_DW0_IRQ (1 << 0)
+
#endif
--
2.50.1
next prev parent reply other threads:[~2025-12-17 6:10 UTC|newest]
Thread overview: 33+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-12-17 6:21 [PATCH 00/19] Make Display free from i915_reg.h Uma Shankar
2025-12-17 6:21 ` [PATCH 01/19] drm/{i915, xe}: Extract common registers into a separate file Uma Shankar
2025-12-17 13:57 ` Jani Nikula
2025-12-18 9:06 ` Shankar, Uma
2025-12-17 6:21 ` [PATCH 02/19] drm/{i915, xe}: Extract South chicken registers Uma Shankar
2025-12-17 13:58 ` Jani Nikula
2025-12-17 6:21 ` [PATCH 03/19] drm/{i915, xe}: Extract display interrupt definitions Uma Shankar
2025-12-17 6:21 ` [PATCH 04/19] drm/{i915, xe}: Extract DSPCLK_GATE_D Uma Shankar
2025-12-17 14:01 ` Jani Nikula
2025-12-17 6:21 ` [PATCH 05/19] drm/{i915, xe}: Extract pcode definitions Uma Shankar
2025-12-17 6:21 ` [PATCH 06/19] drm/{i915, xe}: Remove i915_reg.h from intel_display_device.c Uma Shankar
2025-12-17 6:21 ` [PATCH 07/19] drm/{i915, xe}: Remove i915_reg.h from intel_dram.c Uma Shankar
2025-12-17 14:03 ` Jani Nikula
2025-12-17 6:21 ` [PATCH 08/19] drm/{i915, xe}: Removed i915_reg.h from intel_display.c Uma Shankar
2025-12-17 14:04 ` Jani Nikula
2025-12-17 6:21 ` [PATCH 09/19] drm/{i915, xe}: Remove i915_reg.h from intel_overlay.c Uma Shankar
2025-12-17 6:22 ` [PATCH 10/19] drm/{i915, xe}: Remove i915_reg.h from g4x_dp.c Uma Shankar
2025-12-17 6:22 ` [PATCH 11/19] drm/{i915, xe}: Remove i915_reg.h from i9xx_wm.c Uma Shankar
2025-12-17 6:22 ` [PATCH 12/19] drm/{i915, xe}: Remove i915_reg.h from g4x_hdmi.c Uma Shankar
2025-12-17 6:22 ` [PATCH 13/19] drm/{i915, xe}: Remove i915_reg.h from intel_rom.c Uma Shankar
2025-12-17 6:22 ` [PATCH 14/19] drm/{i915, xe}: Remove i915_reg.h from intel_psr.c Uma Shankar
2025-12-17 6:22 ` [PATCH 15/19] drm/{i915, xe}: Remove i915_reg.h from intel_fifo_underrun.c Uma Shankar
2025-12-17 6:22 ` Uma Shankar [this message]
2025-12-17 6:22 ` [PATCH 17/19] drm/{i915, xe}: Remove i915_reg.h from intel_display_power_well.c Uma Shankar
2025-12-17 6:22 ` [PATCH 18/19] drm/{i915, xe}: Remove i915_reg.h from intel_modeset_setup.c Uma Shankar
2025-12-17 6:22 ` [PATCH 19/19] drm/{i915, xe}: Removed i915_reg.h from display Uma Shankar
2025-12-17 6:26 ` ✗ CI.checkpatch: warning for Make Display free from i915_reg.h Patchwork
2025-12-17 6:27 ` ✓ CI.KUnit: success " Patchwork
2025-12-17 6:46 ` ✗ CI.checksparse: warning " Patchwork
2025-12-17 7:53 ` ✓ Xe.CI.BAT: success " Patchwork
2025-12-17 14:06 ` [PATCH 00/19] " Jani Nikula
2025-12-18 9:08 ` Shankar, Uma
2025-12-18 6:11 ` ✗ Xe.CI.Full: failure for " Patchwork
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