From: Jani Nikula <jani.nikula@intel.com>
To: Uma Shankar <uma.shankar@intel.com>,
intel-gfx@lists.freedesktop.org, intel-xe@lists.freedesktop.org
Cc: ville.syrjala@linux.intel.com, Uma Shankar <uma.shankar@intel.com>
Subject: Re: [PATCH 04/19] drm/{i915, xe}: Extract DSPCLK_GATE_D
Date: Wed, 17 Dec 2025 16:01:21 +0200 [thread overview]
Message-ID: <d3f267d6cbe746ace8ea9a0237489eca7d8b82cd@intel.com> (raw)
In-Reply-To: <20251217062209.852324-5-uma.shankar@intel.com>
On Wed, 17 Dec 2025, Uma Shankar <uma.shankar@intel.com> wrote:
> Move DSPCLK_GATE_D register definition to common header.
> This allows intel_gmbus.c free of i915_reg.h include.
I think these too should be moved to intel_display_regs.h (or some
suitable new file) instead of include/drm/intel.
The intel_clock_gating.c users of the registers should be moved under
display/, though not necessarily in this series. For starters,
intel_clock_gating.c and gvt can include the necessary headers from
display/.
BR,
Jani.
>
> Signed-off-by: Uma Shankar <uma.shankar@intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_gmbus.c | 2 +-
> drivers/gpu/drm/i915/i915_reg.h | 50 ----------------------
> include/drm/intel/intel_gmd_common_regs.h | 49 +++++++++++++++++++++
> 3 files changed, 50 insertions(+), 51 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_gmbus.c b/drivers/gpu/drm/i915/display/intel_gmbus.c
> index 2caff677600c..b77860c5d649 100644
> --- a/drivers/gpu/drm/i915/display/intel_gmbus.c
> +++ b/drivers/gpu/drm/i915/display/intel_gmbus.c
> @@ -34,8 +34,8 @@
>
> #include <drm/drm_print.h>
> #include <drm/display/drm_hdcp_helper.h>
> +#include <drm/intel/intel_gmd_common_regs.h>
>
> -#include "i915_reg.h"
> #include "intel_de.h"
> #include "intel_display_regs.h"
> #include "intel_display_types.h"
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index a338f01a539b..30f504a47593 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -614,47 +614,6 @@
> #define DSTATE_GFX_CLOCK_GATING (1 << 1)
> #define DSTATE_DOT_CLOCK_GATING (1 << 0)
>
> -#define DSPCLK_GATE_D _MMIO(0x6200)
> -#define VLV_DSPCLK_GATE_D _MMIO(VLV_DISPLAY_BASE + 0x6200)
> -# define DPUNIT_B_CLOCK_GATE_DISABLE (1 << 30) /* 965 */
> -# define VSUNIT_CLOCK_GATE_DISABLE (1 << 29) /* 965 */
> -# define VRHUNIT_CLOCK_GATE_DISABLE (1 << 28) /* 965 */
> -# define VRDUNIT_CLOCK_GATE_DISABLE (1 << 27) /* 965 */
> -# define AUDUNIT_CLOCK_GATE_DISABLE (1 << 26) /* 965 */
> -# define DPUNIT_A_CLOCK_GATE_DISABLE (1 << 25) /* 965 */
> -# define DPCUNIT_CLOCK_GATE_DISABLE (1 << 24) /* 965 */
> -# define PNV_GMBUSUNIT_CLOCK_GATE_DISABLE (1 << 24) /* pnv */
> -# define TVRUNIT_CLOCK_GATE_DISABLE (1 << 23) /* 915-945 */
> -# define TVCUNIT_CLOCK_GATE_DISABLE (1 << 22) /* 915-945 */
> -# define TVFUNIT_CLOCK_GATE_DISABLE (1 << 21) /* 915-945 */
> -# define TVEUNIT_CLOCK_GATE_DISABLE (1 << 20) /* 915-945 */
> -# define DVSUNIT_CLOCK_GATE_DISABLE (1 << 19) /* 915-945 */
> -# define DSSUNIT_CLOCK_GATE_DISABLE (1 << 18) /* 915-945 */
> -# define DDBUNIT_CLOCK_GATE_DISABLE (1 << 17) /* 915-945 */
> -# define DPRUNIT_CLOCK_GATE_DISABLE (1 << 16) /* 915-945 */
> -# define DPFUNIT_CLOCK_GATE_DISABLE (1 << 15) /* 915-945 */
> -# define DPBMUNIT_CLOCK_GATE_DISABLE (1 << 14) /* 915-945 */
> -# define DPLSUNIT_CLOCK_GATE_DISABLE (1 << 13) /* 915-945 */
> -# define DPLUNIT_CLOCK_GATE_DISABLE (1 << 12) /* 915-945 */
> -# define DPOUNIT_CLOCK_GATE_DISABLE (1 << 11)
> -# define DPBUNIT_CLOCK_GATE_DISABLE (1 << 10)
> -# define DCUNIT_CLOCK_GATE_DISABLE (1 << 9)
> -# define DPUNIT_CLOCK_GATE_DISABLE (1 << 8)
> -# define VRUNIT_CLOCK_GATE_DISABLE (1 << 7) /* 915+: reserved */
> -# define OVHUNIT_CLOCK_GATE_DISABLE (1 << 6) /* 830-865 */
> -# define DPIOUNIT_CLOCK_GATE_DISABLE (1 << 6) /* 915-945 */
> -# define OVFUNIT_CLOCK_GATE_DISABLE (1 << 5)
> -# define OVBUNIT_CLOCK_GATE_DISABLE (1 << 4)
> -/*
> - * This bit must be set on the 830 to prevent hangs when turning off the
> - * overlay scaler.
> - */
> -# define OVRUNIT_CLOCK_GATE_DISABLE (1 << 3)
> -# define OVCUNIT_CLOCK_GATE_DISABLE (1 << 2)
> -# define OVUUNIT_CLOCK_GATE_DISABLE (1 << 1)
> -# define ZVUNIT_CLOCK_GATE_DISABLE (1 << 0) /* 830 */
> -# define OVLUNIT_CLOCK_GATE_DISABLE (1 << 0) /* 845,865 */
> -
> #define RENCLK_GATE_D1 _MMIO(0x6204)
> # define BLITTER_CLOCK_GATE_DISABLE (1 << 13) /* 945GM only */
> # define MPEG_CLOCK_GATE_DISABLE (1 << 12) /* 945GM only */
> @@ -990,15 +949,6 @@
> #define TRANS_CHICKEN1_HDMIUNIT_GC_DISABLE REG_BIT(10)
> #define TRANS_CHICKEN1_DP0UNIT_GC_DISABLE REG_BIT(4)
>
> -#define SOUTH_DSPCLK_GATE_D _MMIO(0xc2020)
> -#define PCH_GMBUSUNIT_CLOCK_GATE_DISABLE (1 << 31)
> -#define PCH_DPLUNIT_CLOCK_GATE_DISABLE (1 << 30)
> -#define PCH_DPLSUNIT_CLOCK_GATE_DISABLE (1 << 29)
> -#define PCH_DPMGUNIT_CLOCK_GATE_DISABLE (1 << 15)
> -#define PCH_CPUNIT_CLOCK_GATE_DISABLE (1 << 14)
> -#define CNP_PWM_CGE_GATING_DISABLE (1 << 13)
> -#define PCH_LP_PARTITION_LEVEL_DISABLE (1 << 12)
> -
> #define VLV_PMWGICZ _MMIO(0x1300a4)
>
> #define HSW_EDRAM_CAP _MMIO(0x120010)
> diff --git a/include/drm/intel/intel_gmd_common_regs.h b/include/drm/intel/intel_gmd_common_regs.h
> index b4cfd186d5c0..fb2a327befd8 100644
> --- a/include/drm/intel/intel_gmd_common_regs.h
> +++ b/include/drm/intel/intel_gmd_common_regs.h
> @@ -4,6 +4,46 @@
> #ifndef _INTEL_GMD_COMMON_REG_H_
> #define _INTEL_GMD_COMMON_REG_H_
>
> +#define DSPCLK_GATE_D _MMIO(0x6200)
> +#define VLV_DSPCLK_GATE_D _MMIO(VLV_DISPLAY_BASE + 0x6200)
> +# define DPUNIT_B_CLOCK_GATE_DISABLE (1 << 30) /* 965 */
> +# define VSUNIT_CLOCK_GATE_DISABLE (1 << 29) /* 965 */
> +# define VRHUNIT_CLOCK_GATE_DISABLE (1 << 28) /* 965 */
> +# define VRDUNIT_CLOCK_GATE_DISABLE (1 << 27) /* 965 */
> +# define AUDUNIT_CLOCK_GATE_DISABLE (1 << 26) /* 965 */
> +# define DPUNIT_A_CLOCK_GATE_DISABLE (1 << 25) /* 965 */
> +# define DPCUNIT_CLOCK_GATE_DISABLE (1 << 24) /* 965 */
> +# define PNV_GMBUSUNIT_CLOCK_GATE_DISABLE (1 << 24) /* pnv */
> +# define TVRUNIT_CLOCK_GATE_DISABLE (1 << 23) /* 915-945 */
> +# define TVCUNIT_CLOCK_GATE_DISABLE (1 << 22) /* 915-945 */
> +# define TVFUNIT_CLOCK_GATE_DISABLE (1 << 21) /* 915-945 */
> +# define TVEUNIT_CLOCK_GATE_DISABLE (1 << 20) /* 915-945 */
> +# define DVSUNIT_CLOCK_GATE_DISABLE (1 << 19) /* 915-945 */
> +# define DSSUNIT_CLOCK_GATE_DISABLE (1 << 18) /* 915-945 */
> +# define DDBUNIT_CLOCK_GATE_DISABLE (1 << 17) /* 915-945 */
> +# define DPRUNIT_CLOCK_GATE_DISABLE (1 << 16) /* 915-945 */
> +# define DPFUNIT_CLOCK_GATE_DISABLE (1 << 15) /* 915-945 */
> +# define DPBMUNIT_CLOCK_GATE_DISABLE (1 << 14) /* 915-945 */
> +# define DPLSUNIT_CLOCK_GATE_DISABLE (1 << 13) /* 915-945 */
> +# define DPLUNIT_CLOCK_GATE_DISABLE (1 << 12) /* 915-945 */
> +# define DPOUNIT_CLOCK_GATE_DISABLE (1 << 11)
> +# define DPBUNIT_CLOCK_GATE_DISABLE (1 << 10)
> +# define DCUNIT_CLOCK_GATE_DISABLE (1 << 9)
> +# define DPUNIT_CLOCK_GATE_DISABLE (1 << 8)
> +# define VRUNIT_CLOCK_GATE_DISABLE (1 << 7) /* 915+: reserved */
> +# define OVHUNIT_CLOCK_GATE_DISABLE (1 << 6) /* 830-865 */
> +# define DPIOUNIT_CLOCK_GATE_DISABLE (1 << 6) /* 915-945 */
> +# define OVFUNIT_CLOCK_GATE_DISABLE (1 << 5)
> +# define OVBUNIT_CLOCK_GATE_DISABLE (1 << 4)
> +/*
> + * This bit must be set on the 830 to prevent hangs when turning off the
> + * overlay scaler.
> + */
> +# define OVRUNIT_CLOCK_GATE_DISABLE (1 << 3)
> +# define OVCUNIT_CLOCK_GATE_DISABLE (1 << 2)
> +# define OVUUNIT_CLOCK_GATE_DISABLE (1 << 1)
> +# define ZVUNIT_CLOCK_GATE_DISABLE (1 << 0) /* 830 */
> +# define OVLUNIT_CLOCK_GATE_DISABLE (1 << 0) /* 845,865 */
> #define SOUTH_CHICKEN1 _MMIO(0xc2000)
> #define FDIA_PHASE_SYNC_SHIFT_OVR 19
> #define FDIA_PHASE_SYNC_SHIFT_EN 18
> @@ -31,6 +71,15 @@
> #define LPT_PWM_GRANULARITY (1 << 5)
> #define DPLS_EDP_PPS_FIX_DIS (1 << 0)
>
> +#define SOUTH_DSPCLK_GATE_D _MMIO(0xc2020)
> +#define PCH_GMBUSUNIT_CLOCK_GATE_DISABLE (1 << 31)
> +#define PCH_DPLUNIT_CLOCK_GATE_DISABLE (1 << 30)
> +#define PCH_DPLSUNIT_CLOCK_GATE_DISABLE (1 << 29)
> +#define PCH_DPMGUNIT_CLOCK_GATE_DISABLE (1 << 15)
> +#define PCH_CPUNIT_CLOCK_GATE_DISABLE (1 << 14)
> +#define CNP_PWM_CGE_GATING_DISABLE (1 << 13)
> +#define PCH_LP_PARTITION_LEVEL_DISABLE (1 << 12)
> +
> #define _TRANSA_CHICKEN2 0xf0064
> #define _TRANSB_CHICKEN2 0xf1064
> #define TRANS_CHICKEN2(pipe) _MMIO_PIPE(pipe, _TRANSA_CHICKEN2, _TRANSB_CHICKEN2)
--
Jani Nikula, Intel
next prev parent reply other threads:[~2025-12-17 14:01 UTC|newest]
Thread overview: 33+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-12-17 6:21 [PATCH 00/19] Make Display free from i915_reg.h Uma Shankar
2025-12-17 6:21 ` [PATCH 01/19] drm/{i915, xe}: Extract common registers into a separate file Uma Shankar
2025-12-17 13:57 ` Jani Nikula
2025-12-18 9:06 ` Shankar, Uma
2025-12-17 6:21 ` [PATCH 02/19] drm/{i915, xe}: Extract South chicken registers Uma Shankar
2025-12-17 13:58 ` Jani Nikula
2025-12-17 6:21 ` [PATCH 03/19] drm/{i915, xe}: Extract display interrupt definitions Uma Shankar
2025-12-17 6:21 ` [PATCH 04/19] drm/{i915, xe}: Extract DSPCLK_GATE_D Uma Shankar
2025-12-17 14:01 ` Jani Nikula [this message]
2025-12-17 6:21 ` [PATCH 05/19] drm/{i915, xe}: Extract pcode definitions Uma Shankar
2025-12-17 6:21 ` [PATCH 06/19] drm/{i915, xe}: Remove i915_reg.h from intel_display_device.c Uma Shankar
2025-12-17 6:21 ` [PATCH 07/19] drm/{i915, xe}: Remove i915_reg.h from intel_dram.c Uma Shankar
2025-12-17 14:03 ` Jani Nikula
2025-12-17 6:21 ` [PATCH 08/19] drm/{i915, xe}: Removed i915_reg.h from intel_display.c Uma Shankar
2025-12-17 14:04 ` Jani Nikula
2025-12-17 6:21 ` [PATCH 09/19] drm/{i915, xe}: Remove i915_reg.h from intel_overlay.c Uma Shankar
2025-12-17 6:22 ` [PATCH 10/19] drm/{i915, xe}: Remove i915_reg.h from g4x_dp.c Uma Shankar
2025-12-17 6:22 ` [PATCH 11/19] drm/{i915, xe}: Remove i915_reg.h from i9xx_wm.c Uma Shankar
2025-12-17 6:22 ` [PATCH 12/19] drm/{i915, xe}: Remove i915_reg.h from g4x_hdmi.c Uma Shankar
2025-12-17 6:22 ` [PATCH 13/19] drm/{i915, xe}: Remove i915_reg.h from intel_rom.c Uma Shankar
2025-12-17 6:22 ` [PATCH 14/19] drm/{i915, xe}: Remove i915_reg.h from intel_psr.c Uma Shankar
2025-12-17 6:22 ` [PATCH 15/19] drm/{i915, xe}: Remove i915_reg.h from intel_fifo_underrun.c Uma Shankar
2025-12-17 6:22 ` [PATCH 16/19] drm/{i915, xe}: Remove i915_reg.h from intel_display_irq.c Uma Shankar
2025-12-17 6:22 ` [PATCH 17/19] drm/{i915, xe}: Remove i915_reg.h from intel_display_power_well.c Uma Shankar
2025-12-17 6:22 ` [PATCH 18/19] drm/{i915, xe}: Remove i915_reg.h from intel_modeset_setup.c Uma Shankar
2025-12-17 6:22 ` [PATCH 19/19] drm/{i915, xe}: Removed i915_reg.h from display Uma Shankar
2025-12-17 6:26 ` ✗ CI.checkpatch: warning for Make Display free from i915_reg.h Patchwork
2025-12-17 6:27 ` ✓ CI.KUnit: success " Patchwork
2025-12-17 6:46 ` ✗ CI.checksparse: warning " Patchwork
2025-12-17 7:53 ` ✓ Xe.CI.BAT: success " Patchwork
2025-12-17 14:06 ` [PATCH 00/19] " Jani Nikula
2025-12-18 9:08 ` Shankar, Uma
2025-12-18 6:11 ` ✗ Xe.CI.Full: failure for " Patchwork
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