[PATCH v11 00/18] Enable/Disable DC balance along with VRR DSB

[PATCH v11 00/18] Enable/Disable DC balance along with VRR DSB

[Mitul Golani]

Control DC Balance Adjustment bit to accomodate changes along
with VRR DSB implementation.

Mitul Golani (12):
  drm/i915/display: Add source param for dc balance
  drm/i915/vrr: Add VRR DC balance registers
  drm/i915/vrr: Add DC Balance params to crtc_state
  drm/i915/vrr: Add state dump for DC Balance params
  drm/i915/vrr: Add compute config for DC Balance params
  drm/i915/vrr: Add function to check if DC Balance Possible
  drm/i915/vrr: Add function to reset DC balance accumulated params
  drm/i915/display: Add DC Balance flip count operations
  drm/i915/vrr: Write DC balance params to hw registers
  drm/i915/display: Wait for VRR PUSH status update
  drm/i915/display: Add function to configure event for dc balance
  drm/i915/vrr: Enable DC Balance

Ville Syrjälä (6):
  drm/i915/dmc: Add pipe dmc registers and bits for DC Balance
  drm/i915/vrr: Add functions to read out vmin/vmax stuff
  drm/i915/vblank: Extract vrr_vblank_start()
  drm/i915/vrr: Implement vblank evasion with DC balancing
  drm/i915/dsb: Add pipedmc dc balance enable/disable
  drm/i915/vrr: Pause DC Balancing for DSB commits

 .../drm/i915/display/intel_crtc_state_dump.c  |   8 +
 drivers/gpu/drm/i915/display/intel_display.c  |  30 ++
 .../drm/i915/display/intel_display_device.h   |   1 +
 .../drm/i915/display/intel_display_types.h    |  11 +
 drivers/gpu/drm/i915/display/intel_dmc.c      |  25 ++
 drivers/gpu/drm/i915/display/intel_dmc.h      |   5 +
 drivers/gpu/drm/i915/display/intel_dmc_regs.h |  60 ++++
 drivers/gpu/drm/i915/display/intel_dsb.c      |  31 +-
 drivers/gpu/drm/i915/display/intel_vblank.c   |  33 +-
 drivers/gpu/drm/i915/display/intel_vrr.c      | 281 +++++++++++++++++-
 drivers/gpu/drm/i915/display/intel_vrr.h      |  10 +
 drivers/gpu/drm/i915/display/intel_vrr_regs.h |  68 +++++
 12 files changed, 556 insertions(+), 7 deletions(-)

-- 
2.48.1

[PATCH v11 01/18] drm/i915/display: Add source param for dc balance

[Mitul Golani]

Add source param for dc balance enablement.

--v2:
- Arrange in alphabetic order. (Ankit)
- Update name. (Ankit)

--v3:
- Commit message update. (Ankit)

Signed-off-by: Mitul Golani <mitulkumar.ajitkumar.golani@intel.com>
Reviewed-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
---
 drivers/gpu/drm/i915/display/intel_display_device.h | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/gpu/drm/i915/display/intel_display_device.h b/drivers/gpu/drm/i915/display/intel_display_device.h
index 50b2e9ae2c18..c0b5fb11c292 100644
--- a/drivers/gpu/drm/i915/display/intel_display_device.h
+++ b/drivers/gpu/drm/i915/display/intel_display_device.h
@@ -205,6 +205,7 @@ struct intel_display_platforms {
 #define HAS_ULTRAJOINER(__display)	(((__display)->platform.dgfx && \
 					  DISPLAY_VER(__display) == 14) && HAS_DSC(__display))
 #define HAS_VRR(__display)		(DISPLAY_VER(__display) >= 11)
+#define HAS_VRR_DC_BALANCE(__display)	(DISPLAY_VER(__display) >= 30)
 #define INTEL_NUM_PIPES(__display)	(hweight8(DISPLAY_RUNTIME_INFO(__display)->pipe_mask))
 #define OVERLAY_NEEDS_PHYSICAL(__display)	(DISPLAY_INFO(__display)->overlay_needs_physical)
 #define SUPPORTS_TV(__display)		(DISPLAY_INFO(__display)->supports_tv)
-- 
2.48.1

[PATCH v11 02/18] drm/i915/dmc: Add pipe dmc registers and bits for DC Balance

[Mitul Golani]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

Add pipe dmc registers and  access bits for DC Balance params
configuration and enablement.

--v2:
- Separate register definitions for transcoder and
pipe dmc. (Ankit)
- Use MMIO pipe macros instead of transcoder ones. (Ankit)
- Remove dev_priv use. (Jani, Nikula)

--v3:
- Add all register address, from capital alphabet to small. (Ankit)
- Add EVT CTL registers.
- Add co-author tag.
- Add event flag for Triggering DC Balance.

--v4:
- Add DCB Flip count and balance reset registers.

--v5:
- Correct macro usage for flip count. (Ankit)
- Use register offset in lower case.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Mitul Golani <mitulkumar.ajitkumar.golani@intel.com>
Reviewed-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
---
 drivers/gpu/drm/i915/display/intel_dmc_regs.h | 60 +++++++++++++++++++
 1 file changed, 60 insertions(+)

diff --git a/drivers/gpu/drm/i915/display/intel_dmc_regs.h b/drivers/gpu/drm/i915/display/intel_dmc_regs.h
index c5aa49921cb9..38e342b45af0 100644
--- a/drivers/gpu/drm/i915/display/intel_dmc_regs.h
+++ b/drivers/gpu/drm/i915/display/intel_dmc_regs.h
@@ -584,4 +584,64 @@ enum pipedmc_event_id {
 #define PTL_PIPEDMC_EXEC_TIME_LINES(start_mmioaddr) _MMIO((start_mmioaddr) + 0x6b8)
 #define PTL_PIPEDMC_END_OF_EXEC_GB(start_mmioaddr) _MMIO((start_mmioaddr) + 0x6c0)
 
+#define _PIPEDMC_DCB_CTL_A			0x5f1a0
+#define _PIPEDMC_DCB_CTL_B			0x5f5a0
+#define PIPEDMC_DCB_CTL(pipe)			_MMIO_PIPE((pipe), _PIPEDMC_DCB_CTL_A,\
+							   _PIPEDMC_DCB_CTL_B)
+#define  PIPEDMC_ADAPTIVE_DCB_ENABLE		REG_BIT(31)
+
+#define _PIPEDMC_DCB_VBLANK_A			0x5f1bc
+#define _PIPEDMC_DCB_VBLANK_B			0x5f5bc
+#define PIPEDMC_DCB_VBLANK(pipe)		_MMIO_PIPE((pipe), _PIPEDMC_DCB_VBLANK_A,\
+							   _PIPEDMC_DCB_VBLANK_B)
+
+#define _PIPEDMC_DCB_SLOPE_A			0x5f1b8
+#define _PIPEDMC_DCB_SLOPE_B			0x5f5b8
+#define PIPEDMC_DCB_SLOPE(pipe)			_MMIO_PIPE((pipe), _PIPEDMC_DCB_SLOPE_A,\
+							   _PIPEDMC_DCB_SLOPE_B)
+
+#define _PIPEDMC_DCB_GUARDBAND_A		0x5f1b4
+#define _PIPEDMC_DCB_GUARDBAND_B		0x5f5b4
+#define PIPEDMC_DCB_GUARDBAND(pipe)		_MMIO_PIPE((pipe), _PIPEDMC_DCB_GUARDBAND_A,\
+							   _PIPEDMC_DCB_GUARDBAND_B)
+
+#define _PIPEDMC_DCB_MAX_INCREASE_A		0x5f1ac
+#define _PIPEDMC_DCB_MAX_INCREASE_B		0x5f5ac
+#define PIPEDMC_DCB_MAX_INCREASE(pipe)		_MMIO_PIPE((pipe), _PIPEDMC_DCB_MAX_INCREASE_A,\
+							   _PIPEDMC_DCB_MAX_INCREASE_B)
+
+#define _PIPEDMC_DCB_MAX_DECREASE_A		0x5f1b0
+#define _PIPEDMC_DCB_MAX_DECREASE_B		0x5f5b0
+#define PIPEDMC_DCB_MAX_DECREASE(pipe)		_MMIO_PIPE((pipe), _PIPEDMC_DCB_MAX_DECREASE_A,\
+							   _PIPEDMC_DCB_MAX_DECREASE_B)
+
+#define _PIPEDMC_DCB_VMIN_A			0x5f1a4
+#define _PIPEDMC_DCB_VMIN_B			0x5f5a4
+#define PIPEDMC_DCB_VMIN(pipe)			_MMIO_PIPE((pipe), _PIPEDMC_DCB_VMIN_A,\
+							   _PIPEDMC_DCB_VMIN_B)
+
+#define _PIPEDMC_DCB_VMAX_A			0x5f1a8
+#define _PIPEDMC_DCB_VMAX_B			0x5f5a8
+#define PIPEDMC_DCB_VMAX(pipe)			_MMIO_PIPE((pipe), _PIPEDMC_DCB_VMAX_A,\
+							   _PIPEDMC_DCB_VMAX_B)
+
+#define _PIPEDMC_DCB_DEBUG_A			0x5f1c0
+#define _PIPEDMC_DCB_DEBUG_B			0x5f5c0
+#define PIPEDMC_DCB_DEBUG(pipe)			_MMIO_PIPE(pipe, _PIPEDMC_DCB_DEBUG_A,\
+							   _PIPEDMC_DCB_DEBUG_B)
+
+#define _PIPEDMC_EVT_CTL_3_A			0x5f040
+#define _PIPEDMC_EVT_CTL_3_B			0x5f440
+#define PIPEDMC_EVT_CTL_3(pipe)			_MMIO_PIPE(pipe, _PIPEDMC_EVT_CTL_3_A,\
+							   _PIPEDMC_EVT_CTL_3_B)
+
+#define _PIPEDMC_DCB_FLIP_COUNT_A		0x906a4
+#define _PIPEDMC_DCB_FLIP_COUNT_B		0x986a4
+#define PIPEDMC_DCB_FLIP_COUNT(pipe)		_MMIO_PIPE(pipe, _PIPEDMC_DCB_FLIP_COUNT_A,\
+							   _PIPEDMC_DCB_FLIP_COUNT_B)
+
+#define _PIPEDMC_DCB_BALANCE_RESET_A		0x906a8
+#define _PIPEDMC_DCB_BALANCE_RESET_B		0x986a8
+#define PIPEDMC_DCB_BALANCE_RESET(pipe)		_MMIO_PIPE(pipe, _PIPEDMC_DCB_BALANCE_RESET_A,\
+							   _PIPEDMC_DCB_BALANCE_RESET_B)
 #endif /* __INTEL_DMC_REGS_H__ */
-- 
2.48.1

[PATCH v11 03/18] drm/i915/vrr: Add VRR DC balance registers

[Mitul Golani]

Add VRR register offsets and bits to access DC Balance configuration.

--v2:
- Separate register definitions. (Ankit)
- Remove usage of dev_priv. (Jani, Nikula)

--v3:
- Convert register address offset, from capital to small. (Ankit)
- Move mask bits near to register offsets. (Ankit)

--v4:
- Use _MMIO_TRANS wherever possible. (Jani)

--v5:
- Added LIVE Value registers for VMAX and FLIPLINE as provided by DMC fw
- For pipe B it is temporary and expected to change later once finalised.

--v6:
- Add live value registers for DCB VMAX/FLIPLINE.

--v7:
- Correct commit message file. (Jani Nikula)
- Add bits in highest to lowest order. (Jani Nikula)

--v8:
- Register/bitfields indentation changes as per i915_reg.h
mentioned format (Jani, Ankit)

--v9:
- Remove comment. (Ankit)

Signed-off-by: Mitul Golani <mitulkumar.ajitkumar.golani@intel.com>
Reviewed-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
---
 drivers/gpu/drm/i915/display/intel_vrr_regs.h | 68 +++++++++++++++++++
 1 file changed, 68 insertions(+)

diff --git a/drivers/gpu/drm/i915/display/intel_vrr_regs.h b/drivers/gpu/drm/i915/display/intel_vrr_regs.h
index ba9b9215dc11..427ada0d3973 100644
--- a/drivers/gpu/drm/i915/display/intel_vrr_regs.h
+++ b/drivers/gpu/drm/i915/display/intel_vrr_regs.h
@@ -8,6 +8,73 @@
 
 #include "intel_display_reg_defs.h"
 
+#define _TRANS_VRR_DCB_ADJ_FLIPLINE_CFG_A	0x604d4
+#define _TRANS_VRR_DCB_ADJ_FLIPLINE_CFG_B	0x614d4
+#define TRANS_VRR_DCB_ADJ_FLIPLINE_CFG(trans)	_MMIO_TRANS(trans, \
+							    _TRANS_VRR_DCB_ADJ_FLIPLINE_CFG_A, \
+							    _TRANS_VRR_DCB_ADJ_FLIPLINE_CFG_B)
+#define  VRR_DCB_ADJ_FLIPLINE_CNT_MASK		REG_GENMASK(31, 24)
+#define  VRR_DCB_ADJ_FLIPLINE_MASK		REG_GENMASK(19, 0)
+#define  VRR_DCB_ADJ_FLIPLINE(flipline)		REG_FIELD_PREP(VRR_DCB_ADJ_FLIPLINE_MASK, \
+							       (flipline))
+
+#define _TRANS_VRR_DCB_ADJ_FLIPLINE_CFG_LIVE_A		0x90700
+#define _TRANS_VRR_DCB_ADJ_FLIPLINE_CFG_LIVE_B		0x98700
+#define TRANS_VRR_DCB_ADJ_FLIPLINE_CFG_LIVE(trans)	_MMIO_TRANS(trans, \
+								    _TRANS_VRR_DCB_ADJ_FLIPLINE_CFG_LIVE_A, \
+								    _TRANS_VRR_DCB_ADJ_FLIPLINE_CFG_LIVE_B)
+
+#define _TRANS_VRR_DCB_ADJ_VMAX_CFG_A		0x604d8
+#define _TRANS_VRR_DCB_ADJ_VMAX_CFG_B		0x614d8
+#define TRANS_VRR_DCB_ADJ_VMAX_CFG(trans)	_MMIO_TRANS(trans, \
+							    _TRANS_VRR_DCB_ADJ_VMAX_CFG_A, \
+							    _TRANS_VRR_DCB_ADJ_VMAX_CFG_B)
+#define  VRR_DCB_ADJ_VMAX_CNT_MASK		REG_GENMASK(31, 24)
+#define  VRR_DCB_ADJ_VMAX_MASK			REG_GENMASK(19, 0)
+#define  VRR_DCB_ADJ_VMAX(vmax)			REG_FIELD_PREP(VRR_DCB_ADJ_VMAX_MASK, (vmax))
+
+#define _TRANS_VRR_DCB_ADJ_VMAX_CFG_LIVE_A	0x906f8
+#define _TRANS_VRR_DCB_ADJ_VMAX_CFG_LIVE_B	0x986f8
+#define TRANS_VRR_DCB_ADJ_VMAX_CFG_LIVE(trans)	_MMIO_TRANS(trans, \
+							    _TRANS_VRR_DCB_ADJ_VMAX_CFG_LIVE_A, \
+							    _TRANS_VRR_DCB_ADJ_VMAX_CFG_LIVE_B)
+
+#define _TRANS_VRR_DCB_FLIPLINE_A		0x60418
+#define _TRANS_VRR_DCB_FLIPLINE_B		0x61418
+#define TRANS_VRR_DCB_FLIPLINE(trans)		_MMIO_TRANS(trans, \
+							    _TRANS_VRR_DCB_FLIPLINE_A, \
+							    _TRANS_VRR_DCB_FLIPLINE_B)
+#define  VRR_DCB_FLIPLINE_MASK			REG_GENMASK(19, 0)
+#define  VRR_DCB_FLIPLINE(flipline)		REG_FIELD_PREP(VRR_DCB_FLIPLINE_MASK, \
+							       (flipline))
+
+#define _TRANS_VRR_DCB_FLIPLINE_LIVE_A		0x906fc
+#define _TRANS_VRR_DCB_FLIPLINE_LIVE_B		0x986fc
+#define TRANS_VRR_DCB_FLIPLINE_LIVE(trans)	_MMIO_TRANS(trans, \
+							    _TRANS_VRR_DCB_FLIPLINE_LIVE_A, \
+							    _TRANS_VRR_DCB_FLIPLINE_LIVE_B)
+
+#define _TRANS_VRR_DCB_VMAX_A			0x60414
+#define _TRANS_VRR_DCB_VMAX_B			0x61414
+#define TRANS_VRR_DCB_VMAX(trans)		_MMIO_TRANS(trans, \
+							     _TRANS_VRR_DCB_VMAX_A, \
+							     _TRANS_VRR_DCB_VMAX_B)
+#define  VRR_DCB_VMAX_MASK			REG_GENMASK(19, 0)
+#define  VRR_DCB_VMAX(vmax)			REG_FIELD_PREP(VRR_DCB_VMAX_MASK, (vmax))
+
+#define _TRANS_VRR_DCB_VMAX_LIVE_A		0x906f4
+#define _TRANS_VRR_DCB_VMAX_LIVE_B		0x986f4
+#define TRANS_VRR_DCB_VMAX_LIVE(trans)		_MMIO_TRANS(trans, \
+							    _TRANS_VRR_DCB_VMAX_LIVE_A, \
+							    _TRANS_VRR_DCB_VMAX_LIVE_B)
+
+#define _TRANS_ADAPTIVE_SYNC_DCB_CTL_A		0x604c0
+#define _TRANS_ADAPTIVE_SYNC_DCB_CTL_B		0x614c0
+#define TRANS_ADAPTIVE_SYNC_DCB_CTL(trans)	_MMIO_TRANS(trans, \
+							     _TRANS_ADAPTIVE_SYNC_DCB_CTL_A, \
+							     _TRANS_ADAPTIVE_SYNC_DCB_CTL_B)
+#define  ADAPTIVE_SYNC_COUNTER_EN		REG_BIT(31)
+
 #define _TRANS_VRR_CTL_A			0x60420
 #define _TRANS_VRR_CTL_B			0x61420
 #define _TRANS_VRR_CTL_C			0x62420
@@ -19,6 +86,7 @@
 #define   VRR_CTL_CMRR_ENABLE			REG_BIT(27)
 #define   VRR_CTL_PIPELINE_FULL_MASK		REG_GENMASK(10, 3)
 #define   VRR_CTL_PIPELINE_FULL(x)		REG_FIELD_PREP(VRR_CTL_PIPELINE_FULL_MASK, (x))
+#define   VRR_CTL_DCB_ADJ_ENABLE		REG_BIT(28)
 #define   VRR_CTL_PIPELINE_FULL_OVERRIDE	REG_BIT(0)
 #define   XELPD_VRR_CTL_VRR_GUARDBAND_MASK	REG_GENMASK(15, 0)
 #define   XELPD_VRR_CTL_VRR_GUARDBAND(x)	REG_FIELD_PREP(XELPD_VRR_CTL_VRR_GUARDBAND_MASK, (x))
-- 
2.48.1

[PATCH v11 04/18] drm/i915/vrr: Add functions to read out vmin/vmax stuff

[Mitul Golani]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

Calculate delayed vblank start position with the help of added
vmin/vmax stuff for next frame and final computation.

--v2:
- Correct Author details.

--v3:
- Separate register details from this  patch.

--v4:
- Add mask macros.

--v5:
- As live prefix params indicate timings for current frame,
read just _live prefix values instead of next frame timings as
done previously.
- Squash Refactor vrr params patch.

--v6:
- Use error code while returning invalid values. (Jani, Nikula)

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Mitul Golani <mitulkumar.ajitkumar.golani@intel.com>
Reviewed-by: Uma Shankar <uma.shankar@intel.com>
Reviewed-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
---
 drivers/gpu/drm/i915/display/intel_vrr.c | 56 ++++++++++++++++++++++++
 drivers/gpu/drm/i915/display/intel_vrr.h |  5 +++
 2 files changed, 61 insertions(+)

diff --git a/drivers/gpu/drm/i915/display/intel_vrr.c b/drivers/gpu/drm/i915/display/intel_vrr.c
index b92c42fde937..31f3a7b6e00d 100644
--- a/drivers/gpu/drm/i915/display/intel_vrr.c
+++ b/drivers/gpu/drm/i915/display/intel_vrr.c
@@ -261,6 +261,12 @@ static int intel_vrr_hw_value(const struct intel_crtc_state *crtc_state,
 		return value - crtc_state->set_context_latency;
 }
 
+static int intel_vrr_vblank_start(const struct intel_crtc_state *crtc_state,
+				  int vmin_vmax)
+{
+	return intel_vrr_hw_value(crtc_state, vmin_vmax) - crtc_state->vrr.guardband;
+}
+
 /*
  * For fixed refresh rate mode Vmin, Vmax and Flipline all are set to
  * Vtotal value.
@@ -898,3 +904,53 @@ int intel_vrr_vmin_safe_window_end(const struct intel_crtc_state *crtc_state)
 	return intel_vrr_vmin_vblank_start(crtc_state) -
 	       crtc_state->set_context_latency;
 }
+
+int intel_vrr_dcb_vmin_vblank_start_next(const struct intel_crtc_state *crtc_state)
+{
+	struct intel_display *display = to_intel_display(crtc_state);
+	enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
+	u32 tmp = 0;
+
+	tmp = intel_de_read(display, TRANS_VRR_DCB_ADJ_FLIPLINE_CFG_LIVE(cpu_transcoder));
+
+	if (REG_FIELD_GET(VRR_DCB_ADJ_FLIPLINE_CNT_MASK, tmp) == 0)
+		return -EINVAL;
+
+	return intel_vrr_vblank_start(crtc_state, VRR_DCB_ADJ_FLIPLINE(tmp) + 1);
+}
+
+int intel_vrr_dcb_vmax_vblank_start_next(const struct intel_crtc_state *crtc_state)
+{
+	struct intel_display *display = to_intel_display(crtc_state);
+	enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
+	u32 tmp = 0;
+
+	tmp = intel_de_read(display, TRANS_VRR_DCB_ADJ_VMAX_CFG_LIVE(cpu_transcoder));
+
+	if (REG_FIELD_GET(VRR_DCB_ADJ_VMAX_CNT_MASK, tmp) == 0)
+		return -EINVAL;
+
+	return intel_vrr_vblank_start(crtc_state, VRR_DCB_ADJ_VMAX(tmp) + 1);
+}
+
+int intel_vrr_dcb_vmin_vblank_start_final(const struct intel_crtc_state *crtc_state)
+{
+	struct intel_display *display = to_intel_display(crtc_state);
+	enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
+	u32 tmp = 0;
+
+	tmp = intel_de_read(display, TRANS_VRR_DCB_FLIPLINE_LIVE(cpu_transcoder));
+
+	return intel_vrr_vblank_start(crtc_state, VRR_DCB_FLIPLINE(tmp) + 1);
+}
+
+int intel_vrr_dcb_vmax_vblank_start_final(const struct intel_crtc_state *crtc_state)
+{
+	struct intel_display *display = to_intel_display(crtc_state);
+	enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
+	u32 tmp = 0;
+
+	tmp = intel_de_read(display, TRANS_VRR_DCB_VMAX_LIVE(cpu_transcoder));
+
+	return intel_vrr_vblank_start(crtc_state, VRR_DCB_VMAX(tmp) + 1);
+}
diff --git a/drivers/gpu/drm/i915/display/intel_vrr.h b/drivers/gpu/drm/i915/display/intel_vrr.h
index bc9044621635..66fb9ad846f2 100644
--- a/drivers/gpu/drm/i915/display/intel_vrr.h
+++ b/drivers/gpu/drm/i915/display/intel_vrr.h
@@ -43,4 +43,9 @@ bool intel_vrr_always_use_vrr_tg(struct intel_display *display);
 int intel_vrr_safe_window_start(const struct intel_crtc_state *crtc_state);
 int intel_vrr_vmin_safe_window_end(const struct intel_crtc_state *crtc_state);
 
+int intel_vrr_dcb_vmin_vblank_start_next(const struct intel_crtc_state *crtc_state);
+int intel_vrr_dcb_vmax_vblank_start_next(const struct intel_crtc_state *crtc_state);
+int intel_vrr_dcb_vmin_vblank_start_final(const struct intel_crtc_state *crtc_state);
+int intel_vrr_dcb_vmax_vblank_start_final(const struct intel_crtc_state *crtc_state);
+
 #endif /* __INTEL_VRR_H__ */
-- 
2.48.1

[PATCH v11 05/18] drm/i915/vrr: Add DC Balance params to crtc_state

[Mitul Golani]

Add DC Balance params to crtc_state, also add state checker
params for related properties.

--v3:
- Seggregate crtc_state params with this patch. (Ankit)

--v4:
- Update commit message and header. (Ankit)
- Add +1 to VMIN and VMAX only when it is non-zero. (Ankit)

--v5:
- Add headers in sorted order. (Jani Nikula)

--v6:
- Add a separate function to get and check dc_balance params.
- Avoid repeatative use of MMIO read. (Ankit)

Signed-off-by: Mitul Golani <mitulkumar.ajitkumar.golani@intel.com>
Reviewed-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
---
 drivers/gpu/drm/i915/display/intel_display.c  |  7 ++++
 .../drm/i915/display/intel_display_types.h    |  7 ++++
 drivers/gpu/drm/i915/display/intel_vrr.c      | 32 +++++++++++++++++++
 3 files changed, 46 insertions(+)

diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index d5947cc9b94c..ecea404fbf91 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -5476,6 +5476,13 @@ intel_pipe_config_compare(const struct intel_crtc_state *current_config,
 		PIPE_CONF_CHECK_LLI(cmrr.cmrr_m);
 		PIPE_CONF_CHECK_LLI(cmrr.cmrr_n);
 		PIPE_CONF_CHECK_BOOL(cmrr.enable);
+		PIPE_CONF_CHECK_I(vrr.dc_balance.vmin);
+		PIPE_CONF_CHECK_I(vrr.dc_balance.vmax);
+		PIPE_CONF_CHECK_I(vrr.dc_balance.guardband);
+		PIPE_CONF_CHECK_I(vrr.dc_balance.slope);
+		PIPE_CONF_CHECK_I(vrr.dc_balance.max_increase);
+		PIPE_CONF_CHECK_I(vrr.dc_balance.max_decrease);
+		PIPE_CONF_CHECK_I(vrr.dc_balance.vblank_target);
 	}
 
 	if (!fastset || intel_vrr_always_use_vrr_tg(display)) {
diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
index 6ff53cd58052..75acfe043997 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -1384,6 +1384,13 @@ struct intel_crtc_state {
 		u8 pipeline_full;
 		u16 flipline, vmin, vmax, guardband;
 		u32 vsync_end, vsync_start;
+		struct {
+			bool enable;
+			u16 vmin, vmax;
+			u16 guardband, slope;
+			u16 max_increase, max_decrease;
+			u16 vblank_target;
+		} dc_balance;
 	} vrr;
 
 	/* Content Match Refresh Rate state */
diff --git a/drivers/gpu/drm/i915/display/intel_vrr.c b/drivers/gpu/drm/i915/display/intel_vrr.c
index 31f3a7b6e00d..427ef1741051 100644
--- a/drivers/gpu/drm/i915/display/intel_vrr.c
+++ b/drivers/gpu/drm/i915/display/intel_vrr.c
@@ -9,6 +9,7 @@
 #include "intel_de.h"
 #include "intel_display_regs.h"
 #include "intel_display_types.h"
+#include "intel_dmc_regs.h"
 #include "intel_dp.h"
 #include "intel_psr.h"
 #include "intel_vrr.h"
@@ -785,6 +786,35 @@ bool intel_vrr_is_fixed_rr(const struct intel_crtc_state *crtc_state)
 	       crtc_state->vrr.flipline == crtc_state->vrr.vmin;
 }
 
+static
+void intel_vrr_get_dc_balance_config(struct intel_crtc_state *crtc_state)
+{
+	u32 reg_val;
+	struct intel_display *display = to_intel_display(crtc_state);
+	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
+	enum pipe pipe = crtc->pipe;
+
+	if (!HAS_VRR_DC_BALANCE(display))
+		return;
+
+	reg_val = intel_de_read(display, PIPEDMC_DCB_VMIN(pipe));
+	crtc_state->vrr.dc_balance.vmin = reg_val ? reg_val + 1 : 0;
+
+	reg_val = intel_de_read(display, PIPEDMC_DCB_VMAX(pipe));
+	crtc_state->vrr.dc_balance.vmax = reg_val ? reg_val + 1 : 0;
+
+	crtc_state->vrr.dc_balance.guardband =
+		intel_de_read(display, PIPEDMC_DCB_GUARDBAND(pipe));
+	crtc_state->vrr.dc_balance.max_increase =
+		intel_de_read(display, PIPEDMC_DCB_MAX_INCREASE(pipe));
+	crtc_state->vrr.dc_balance.max_decrease =
+		intel_de_read(display, PIPEDMC_DCB_MAX_DECREASE(pipe));
+	crtc_state->vrr.dc_balance.slope =
+		intel_de_read(display, PIPEDMC_DCB_SLOPE(pipe));
+	crtc_state->vrr.dc_balance.vblank_target =
+		intel_de_read(display, PIPEDMC_DCB_VBLANK(pipe));
+}
+
 void intel_vrr_get_config(struct intel_crtc_state *crtc_state)
 {
 	struct intel_display *display = to_intel_display(crtc_state);
@@ -866,6 +896,8 @@ void intel_vrr_get_config(struct intel_crtc_state *crtc_state)
 	else
 		crtc_state->vrr.enable = vrr_enable;
 
+	intel_vrr_get_dc_balance_config(crtc_state);
+
 	/*
 	 * #TODO: For Both VRR and CMRR the flag I915_MODE_FLAG_VRR is set for mode_flags.
 	 * Since CMRR is currently disabled, set this flag for VRR for now.
-- 
2.48.1

[PATCH v11 06/18] drm/i915/vrr: Add state dump for DC Balance params

[Mitul Golani]

Add state dump for dc balance params to track DC Balance
crtc state config.

-v1:
-- nitpick: s/Vblank target/vblank target. (Ankit)

Signed-off-by: Mitul Golani <mitulkumar.ajitkumar.golani@intel.com>
Reviewed-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
---
 drivers/gpu/drm/i915/display/intel_crtc_state_dump.c | 8 ++++++++
 1 file changed, 8 insertions(+)

diff --git a/drivers/gpu/drm/i915/display/intel_crtc_state_dump.c b/drivers/gpu/drm/i915/display/intel_crtc_state_dump.c
index c2a6217c2262..234843b8f83a 100644
--- a/drivers/gpu/drm/i915/display/intel_crtc_state_dump.c
+++ b/drivers/gpu/drm/i915/display/intel_crtc_state_dump.c
@@ -303,6 +303,14 @@ void intel_crtc_state_dump(const struct intel_crtc_state *pipe_config,
 	drm_printf(&p, "vrr: vmin vblank: %d, vmax vblank: %d, vmin vtotal: %d, vmax vtotal: %d\n",
 		   intel_vrr_vmin_vblank_start(pipe_config), intel_vrr_vmax_vblank_start(pipe_config),
 		   intel_vrr_vmin_vtotal(pipe_config), intel_vrr_vmax_vtotal(pipe_config));
+	drm_printf(&p, "vrr: dc balance: %s, vmin: %d vmax: %d guardband: %d, slope: %d max increase: %d max decrease: %d vblank target: %d\n",
+		   str_yes_no(pipe_config->vrr.dc_balance.enable),
+		   pipe_config->vrr.dc_balance.vmin, pipe_config->vrr.dc_balance.vmax,
+		   pipe_config->vrr.dc_balance.guardband,
+		   pipe_config->vrr.dc_balance.slope,
+		   pipe_config->vrr.dc_balance.max_increase,
+		   pipe_config->vrr.dc_balance.max_decrease,
+		   pipe_config->vrr.dc_balance.vblank_target);
 
 	drm_printf(&p, "requested mode: " DRM_MODE_FMT "\n",
 		   DRM_MODE_ARG(&pipe_config->hw.mode));
-- 
2.48.1

[PATCH v11 07/18] drm/i915/vrr: Add compute config for DC Balance params

[Mitul Golani]

Compute DC Balance parameters and tunable params based on
experiments.

--v2:
- Document tunable params. (Ankit)

--v3:
- Add line spaces to compute config. (Ankit)
- Remove redundancy checks.

--v4:
- Separate out conpute config to separate function.
- As all the valuse are being computed in scanlines, and slope
is still in usec, convert and store it to scanlines.

--v5:
- Update and add comments for slope calculation. (Ankit)
- Update early return conditions for dc balance compute. (Ankit)

--v6:
- Early return condition simplified for dc balance compute config. (Ankit)
- Make use of pipe restrictions to this patch. (Ankit)

--v7:
- Separate out PIPE_A and PIPE_B restrictions to other patch.(Ankit)

Signed-off-by: Mitul Golani <mitulkumar.ajitkumar.golani@intel.com>
Reviewed-by: Uma Shankar <uma.shankar@intel.com>
---
 drivers/gpu/drm/i915/display/intel_vrr.c | 45 ++++++++++++++++++++++++
 1 file changed, 45 insertions(+)

diff --git a/drivers/gpu/drm/i915/display/intel_vrr.c b/drivers/gpu/drm/i915/display/intel_vrr.c
index 427ef1741051..952e3c31bacc 100644
--- a/drivers/gpu/drm/i915/display/intel_vrr.c
+++ b/drivers/gpu/drm/i915/display/intel_vrr.c
@@ -6,6 +6,7 @@
 
 #include <drm/drm_print.h>
 
+#include "intel_crtc.h"
 #include "intel_de.h"
 #include "intel_display_regs.h"
 #include "intel_display_types.h"
@@ -20,6 +21,14 @@
 #define FIXED_POINT_PRECISION		100
 #define CMRR_PRECISION_TOLERANCE	10
 
+/*
+ * Tunable parameters for DC Balance correction.
+ * These are captured based on experimentations.
+ */
+#define DCB_CORRECTION_SENSITIVITY	30
+#define DCB_CORRECTION_AGGRESSIVENESS	1000 /* ms × 100; 10 ms */
+#define DCB_BLANK_TARGET		50
+
 bool intel_vrr_is_capable(struct intel_connector *connector)
 {
 	struct intel_display *display = to_intel_display(connector);
@@ -342,6 +351,40 @@ int intel_vrr_compute_vmax(struct intel_connector *connector,
 	return vmax;
 }
 
+static void
+intel_vrr_dc_balance_compute_config(struct intel_crtc_state *crtc_state)
+{
+	int guardband_usec, adjustment_usec;
+	struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode;
+
+	if (!HAS_VRR_DC_BALANCE(display) || !crtc_state->vrr.enable)
+		return;
+
+	crtc_state->vrr.dc_balance.vmax = crtc_state->vrr.vmax;
+	crtc_state->vrr.dc_balance.vmin = crtc_state->vrr.vmin;
+	crtc_state->vrr.dc_balance.max_increase =
+		crtc_state->vrr.vmax - crtc_state->vrr.vmin;
+	crtc_state->vrr.dc_balance.max_decrease =
+		crtc_state->vrr.vmax - crtc_state->vrr.vmin;
+	crtc_state->vrr.dc_balance.guardband =
+		DIV_ROUND_UP(crtc_state->vrr.dc_balance.vmax *
+			     DCB_CORRECTION_SENSITIVITY, 100);
+	guardband_usec =
+		intel_scanlines_to_usecs(adjusted_mode,
+					 crtc_state->vrr.dc_balance.guardband);
+	/*
+	 *  The correction_aggressiveness/100 is the number of milliseconds to
+	 *  adjust by when the balance is at twice the guardband.
+	 *  guardband_slope = correction_aggressiveness / (guardband * 100)
+	 */
+	adjustment_usec = DCB_CORRECTION_AGGRESSIVENESS * 10;
+	crtc_state->vrr.dc_balance.slope =
+		DIV_ROUND_UP(adjustment_usec, guardband_usec);
+	crtc_state->vrr.dc_balance.vblank_target =
+		DIV_ROUND_UP((crtc_state->vrr.vmax - crtc_state->vrr.vmin) *
+			     DCB_BLANK_TARGET, 100);
+}
+
 void
 intel_vrr_compute_config(struct intel_crtc_state *crtc_state,
 			 struct drm_connector_state *conn_state)
@@ -399,6 +442,8 @@ intel_vrr_compute_config(struct intel_crtc_state *crtc_state,
 			(crtc_state->hw.adjusted_mode.crtc_vtotal -
 			 crtc_state->hw.adjusted_mode.crtc_vsync_end);
 	}
+
+	intel_vrr_dc_balance_compute_config(crtc_state);
 }
 
 static int
-- 
2.48.1

[PATCH v11 08/18] drm/i915/vrr: Add function to check if DC Balance Possible

[Mitul Golani]

Add function to check if DC Balance possibile on
requested PIPE and also validate along with DISPLAY_VER
check.

Signed-off-by: Mitul Golani <mitulkumar.ajitkumar.golani@intel.com>
---
 drivers/gpu/drm/i915/display/intel_vrr.c | 19 +++++++++++++++++--
 1 file changed, 17 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_vrr.c b/drivers/gpu/drm/i915/display/intel_vrr.c
index 952e3c31bacc..dbfe56e8973d 100644
--- a/drivers/gpu/drm/i915/display/intel_vrr.c
+++ b/drivers/gpu/drm/i915/display/intel_vrr.c
@@ -351,13 +351,28 @@ int intel_vrr_compute_vmax(struct intel_connector *connector,
 	return vmax;
 }
 
+static bool intel_vrr_dc_balance_possible(const struct intel_crtc_state *crtc_state)
+{
+	struct intel_display *display = to_intel_display(crtc_state);
+	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
+	enum pipe pipe = crtc->pipe;
+
+	/*
+	 * FIXME: Currently Firmware supports DC Balancing on PIPE A
+	 * and PIPE B. Account those limitation while computing DC
+	 * Balance parameters.
+	 */
+	return (HAS_VRR_DC_BALANCE(display) &&
+		((pipe == PIPE_A) || (pipe == PIPE_B)));
+}
+
 static void
 intel_vrr_dc_balance_compute_config(struct intel_crtc_state *crtc_state)
 {
 	int guardband_usec, adjustment_usec;
 	struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode;
 
-	if (!HAS_VRR_DC_BALANCE(display) || !crtc_state->vrr.enable)
+	if (!intel_vrr_dc_balance_possible(crtc_state) || !crtc_state->vrr.enable)
 		return;
 
 	crtc_state->vrr.dc_balance.vmax = crtc_state->vrr.vmax;
@@ -839,7 +854,7 @@ void intel_vrr_get_dc_balance_config(struct intel_crtc_state *crtc_state)
 	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
 	enum pipe pipe = crtc->pipe;
 
-	if (!HAS_VRR_DC_BALANCE(display))
+	if (!intel_vrr_dc_balance_possible(crtc_state))
 		return;
 
 	reg_val = intel_de_read(display, PIPEDMC_DCB_VMIN(pipe));
-- 
2.48.1

Re: [PATCH v11 08/18] drm/i915/vrr: Add function to check if DC Balance Possible

[Nautiyal, Ankit K]

On 12/23/2025 4:15 PM, Mitul Golani wrote:
> Add function to check if DC Balance possibile on
> requested PIPE and also validate along with DISPLAY_VER
> check.

s/possibile/possible

Perhaps it can be rephrased as:

Add a function that checks if DC Balance enabling is possible on the
requested PIPE. Apart from the DISPLAY_VER check, account for current
firmware limitations, which only allow DC Balance on PIPE A and PIPE B.

With the above changes:

Reviewed-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>

>
> Signed-off-by: Mitul Golani <mitulkumar.ajitkumar.golani@intel.com>
> ---
>   drivers/gpu/drm/i915/display/intel_vrr.c | 19 +++++++++++++++++--
>   1 file changed, 17 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_vrr.c b/drivers/gpu/drm/i915/display/intel_vrr.c
> index 952e3c31bacc..dbfe56e8973d 100644
> --- a/drivers/gpu/drm/i915/display/intel_vrr.c
> +++ b/drivers/gpu/drm/i915/display/intel_vrr.c
> @@ -351,13 +351,28 @@ int intel_vrr_compute_vmax(struct intel_connector *connector,
>   	return vmax;
>   }
>   
> +static bool intel_vrr_dc_balance_possible(const struct intel_crtc_state *crtc_state)
> +{
> +	struct intel_display *display = to_intel_display(crtc_state);
> +	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> +	enum pipe pipe = crtc->pipe;
> +
> +	/*
> +	 * FIXME: Currently Firmware supports DC Balancing on PIPE A
> +	 * and PIPE B. Account those limitation while computing DC
> +	 * Balance parameters.
> +	 */
> +	return (HAS_VRR_DC_BALANCE(display) &&
> +		((pipe == PIPE_A) || (pipe == PIPE_B)));
> +}
> +
>   static void
>   intel_vrr_dc_balance_compute_config(struct intel_crtc_state *crtc_state)
>   {
>   	int guardband_usec, adjustment_usec;
>   	struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode;
>   
> -	if (!HAS_VRR_DC_BALANCE(display) || !crtc_state->vrr.enable)
> +	if (!intel_vrr_dc_balance_possible(crtc_state) || !crtc_state->vrr.enable)
>   		return;
>   
>   	crtc_state->vrr.dc_balance.vmax = crtc_state->vrr.vmax;
> @@ -839,7 +854,7 @@ void intel_vrr_get_dc_balance_config(struct intel_crtc_state *crtc_state)
>   	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
>   	enum pipe pipe = crtc->pipe;
>   
> -	if (!HAS_VRR_DC_BALANCE(display))
> +	if (!intel_vrr_dc_balance_possible(crtc_state))
>   		return;
>   
>   	reg_val = intel_de_read(display, PIPEDMC_DCB_VMIN(pipe));

[PATCH v11 09/18] drm/i915/vrr: Add function to reset DC balance accumulated params

[Mitul Golani]

Add function which resets all accumulated DC Balance parameters
whenever adaptive mode of VRR goes off. This helps to give a
fresh start when VRR is re-enabled.

--v2:
- Typo, change crtc_state to old_crtc_state. (Ankit)

Signed-off-by: Mitul Golani <mitulkumar.ajitkumar.golani@intel.com>
Reviewed-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
---
 drivers/gpu/drm/i915/display/intel_display.c |  1 +
 drivers/gpu/drm/i915/display/intel_vrr.c     | 13 +++++++++++++
 drivers/gpu/drm/i915/display/intel_vrr.h     |  3 +++
 3 files changed, 17 insertions(+)

diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index ecea404fbf91..ab0a8b791635 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -1158,6 +1158,7 @@ static void intel_pre_plane_update(struct intel_atomic_state *state,
 
 	if (intel_crtc_vrr_disabling(state, crtc)) {
 		intel_vrr_disable(old_crtc_state);
+		intel_vrr_dcb_reset(old_crtc_state, crtc);
 		intel_crtc_update_active_timings(old_crtc_state, false);
 	}
 
diff --git a/drivers/gpu/drm/i915/display/intel_vrr.c b/drivers/gpu/drm/i915/display/intel_vrr.c
index dbfe56e8973d..c3a8161fb8e1 100644
--- a/drivers/gpu/drm/i915/display/intel_vrr.c
+++ b/drivers/gpu/drm/i915/display/intel_vrr.c
@@ -646,6 +646,19 @@ void intel_vrr_set_transcoder_timings(const struct intel_crtc_state *crtc_state)
 			       EMP_AS_SDP_DB_TL(crtc_state->vrr.vsync_start));
 }
 
+void
+intel_vrr_dcb_reset(const struct intel_crtc_state *old_crtc_state,
+		    struct intel_crtc *crtc)
+{
+	struct intel_display *display = to_intel_display(old_crtc_state);
+	enum pipe pipe = crtc->pipe;
+
+	if (!old_crtc_state->vrr.dc_balance.enable)
+		return;
+
+	intel_de_write(display, PIPEDMC_DCB_BALANCE_RESET(pipe), 0);
+}
+
 void intel_vrr_send_push(struct intel_dsb *dsb,
 			 const struct intel_crtc_state *crtc_state)
 {
diff --git a/drivers/gpu/drm/i915/display/intel_vrr.h b/drivers/gpu/drm/i915/display/intel_vrr.h
index 66fb9ad846f2..d40ed5504180 100644
--- a/drivers/gpu/drm/i915/display/intel_vrr.h
+++ b/drivers/gpu/drm/i915/display/intel_vrr.h
@@ -11,6 +11,7 @@
 struct drm_connector_state;
 struct intel_atomic_state;
 struct intel_connector;
+struct intel_crtc;
 struct intel_crtc_state;
 struct intel_dsb;
 struct intel_display;
@@ -39,6 +40,8 @@ bool intel_vrr_is_fixed_rr(const struct intel_crtc_state *crtc_state);
 void intel_vrr_transcoder_enable(const struct intel_crtc_state *crtc_state);
 void intel_vrr_transcoder_disable(const struct intel_crtc_state *crtc_state);
 void intel_vrr_set_fixed_rr_timings(const struct intel_crtc_state *crtc_state);
+void intel_vrr_dcb_reset(const struct intel_crtc_state *old_crtc_state,
+			 struct intel_crtc *crtc);
 bool intel_vrr_always_use_vrr_tg(struct intel_display *display);
 int intel_vrr_safe_window_start(const struct intel_crtc_state *crtc_state);
 int intel_vrr_vmin_safe_window_end(const struct intel_crtc_state *crtc_state);
-- 
2.48.1

[PATCH v11 10/18] drm/i915/display: Add DC Balance flip count operations

[Mitul Golani]

Track dc balance flip count with params per crtc. Increment
DC Balance Flip count before every flip to indicate DMC
firmware about new flip occurrence which needs to be adjusted
for dc balancing. This is tracked separately from legacy
FLIP_COUNT register also Reset DC balance flip count value
while disabling VRR adaptive mode, this is to start with
fresh counts when VRR adaptive refresh mode is triggered again.

--v2:
- Call during intel_update_crtc.(Ankit)

Signed-off-by: Mitul Golani <mitulkumar.ajitkumar.golani@intel.com>
Reviewed-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
---
 drivers/gpu/drm/i915/display/intel_display.c      |  3 +++
 .../gpu/drm/i915/display/intel_display_types.h    |  4 ++++
 drivers/gpu/drm/i915/display/intel_vrr.c          | 15 +++++++++++++++
 drivers/gpu/drm/i915/display/intel_vrr.h          |  2 ++
 4 files changed, 24 insertions(+)

diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index ab0a8b791635..70ae5582ab0b 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -6864,6 +6864,9 @@ static void intel_update_crtc(struct intel_atomic_state *state,
 		intel_crtc_update_active_timings(new_crtc_state,
 						 new_crtc_state->vrr.enable);
 
+	if (new_crtc_state->vrr.dc_balance.enable)
+		intel_vrr_dcb_increment_flip_count(new_crtc_state, crtc);
+
 	/*
 	 * We usually enable FIFO underrun interrupts as part of the
 	 * CRTC enable sequence during modesets.  But when we inherit a
diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
index 75acfe043997..113e43bc1f6d 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -1531,6 +1531,10 @@ struct intel_crtc {
 		struct intel_link_m_n m_n, m2_n2;
 	} drrs;
 
+	struct {
+		u64 flip_count;
+	} dc_balance;
+
 	int scanline_offset;
 
 	struct {
diff --git a/drivers/gpu/drm/i915/display/intel_vrr.c b/drivers/gpu/drm/i915/display/intel_vrr.c
index c3a8161fb8e1..92be789a6500 100644
--- a/drivers/gpu/drm/i915/display/intel_vrr.c
+++ b/drivers/gpu/drm/i915/display/intel_vrr.c
@@ -646,6 +646,20 @@ void intel_vrr_set_transcoder_timings(const struct intel_crtc_state *crtc_state)
 			       EMP_AS_SDP_DB_TL(crtc_state->vrr.vsync_start));
 }
 
+void
+intel_vrr_dcb_increment_flip_count(struct intel_crtc_state *crtc_state,
+				   struct intel_crtc *crtc)
+{
+	struct intel_display *display = to_intel_display(crtc_state);
+	enum pipe pipe = crtc->pipe;
+
+	if (!crtc_state->vrr.dc_balance.enable)
+		return;
+
+	intel_de_write(display, PIPEDMC_DCB_FLIP_COUNT(pipe),
+		       ++crtc->dc_balance.flip_count);
+}
+
 void
 intel_vrr_dcb_reset(const struct intel_crtc_state *old_crtc_state,
 		    struct intel_crtc *crtc)
@@ -656,6 +670,7 @@ intel_vrr_dcb_reset(const struct intel_crtc_state *old_crtc_state,
 	if (!old_crtc_state->vrr.dc_balance.enable)
 		return;
 
+	intel_de_write(display, PIPEDMC_DCB_FLIP_COUNT(pipe), 0);
 	intel_de_write(display, PIPEDMC_DCB_BALANCE_RESET(pipe), 0);
 }
 
diff --git a/drivers/gpu/drm/i915/display/intel_vrr.h b/drivers/gpu/drm/i915/display/intel_vrr.h
index d40ed5504180..bedcc8c4bff2 100644
--- a/drivers/gpu/drm/i915/display/intel_vrr.h
+++ b/drivers/gpu/drm/i915/display/intel_vrr.h
@@ -29,6 +29,8 @@ void intel_vrr_send_push(struct intel_dsb *dsb,
 			 const struct intel_crtc_state *crtc_state);
 void intel_vrr_check_push_sent(struct intel_dsb *dsb,
 			       const struct intel_crtc_state *crtc_state);
+void intel_vrr_dcb_increment_flip_count(struct intel_crtc_state *crtc_state,
+					struct intel_crtc *crtc);
 bool intel_vrr_is_push_sent(const struct intel_crtc_state *crtc_state);
 void intel_vrr_disable(const struct intel_crtc_state *old_crtc_state);
 void intel_vrr_get_config(struct intel_crtc_state *crtc_state);
-- 
2.48.1

[PATCH v11 11/18] drm/i915/vrr: Write DC balance params to hw registers

[Mitul Golani]

Write DC Balance parameters to hw registers.

--v2:
- Update commit header.
- Separate crtc_state params from this patch. (Ankit)

--v3:
- Write registers at compute config.
- Update condition for write.

--v4:
- Address issue with state checker.

--v5:
- Initialise some more dc balance register while enabling VRR.

--v6:
- FLIPLINE_CFG need to be configure at last, as it is double buffer
arming point.

--v7:
- Initialise and reset live value of vmax and vmin as well.

--v8:
- Add separate functions while writing hw registers. (Ankit)

--v9:
- Add DC Balance counter enable bit to this patch. (Ankit)

--v10:
- Add rigister writes to vrr_enable/disable. (Ankit)

Signed-off-by: Mitul Golani <mitulkumar.ajitkumar.golani@intel.com>
Reviewed-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
---
 drivers/gpu/drm/i915/display/intel_vrr.c | 76 ++++++++++++++++++++++++
 1 file changed, 76 insertions(+)

diff --git a/drivers/gpu/drm/i915/display/intel_vrr.c b/drivers/gpu/drm/i915/display/intel_vrr.c
index 92be789a6500..68b39fe0f7bc 100644
--- a/drivers/gpu/drm/i915/display/intel_vrr.c
+++ b/drivers/gpu/drm/i915/display/intel_vrr.c
@@ -781,6 +781,80 @@ static void intel_vrr_set_vrr_timings(const struct intel_crtc_state *crtc_state)
 		       intel_vrr_hw_flipline(crtc_state) - 1);
 }
 
+static void
+intel_vrr_enable_dc_balancing(const struct intel_crtc_state *crtc_state)
+{
+	struct intel_display *display = to_intel_display(crtc_state);
+	enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
+	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
+	enum pipe pipe = crtc->pipe;
+
+	if (!crtc_state->vrr.dc_balance.enable)
+		return;
+
+	intel_de_write(display, TRANS_VRR_DCB_ADJ_VMAX_CFG(cpu_transcoder),
+		       VRR_DCB_ADJ_VMAX(crtc_state->vrr.vmax - 1));
+	intel_de_write(display, TRANS_VRR_DCB_ADJ_VMAX_CFG_LIVE(cpu_transcoder),
+		       VRR_DCB_ADJ_VMAX(crtc_state->vrr.vmax - 1));
+	intel_de_write(display, TRANS_VRR_DCB_VMAX(cpu_transcoder),
+		       VRR_DCB_VMAX(crtc_state->vrr.vmax - 1));
+	intel_de_write(display, TRANS_VRR_DCB_VMAX_LIVE(cpu_transcoder),
+		       VRR_DCB_VMAX(crtc_state->vrr.vmax - 1));
+	intel_de_write(display, TRANS_VRR_DCB_FLIPLINE(cpu_transcoder),
+		       VRR_DCB_FLIPLINE(crtc_state->vrr.flipline - 1));
+	intel_de_write(display, TRANS_VRR_DCB_FLIPLINE_LIVE(cpu_transcoder),
+		       VRR_DCB_FLIPLINE(crtc_state->vrr.flipline - 1));
+	intel_de_write(display, TRANS_VRR_DCB_ADJ_FLIPLINE_CFG_LIVE(cpu_transcoder),
+		       VRR_DCB_ADJ_FLIPLINE(crtc_state->vrr.flipline - 1));
+	intel_de_write(display, TRANS_VRR_DCB_ADJ_FLIPLINE_CFG(cpu_transcoder),
+		       VRR_DCB_ADJ_FLIPLINE(crtc_state->vrr.flipline - 1));
+	intel_de_write(display, PIPEDMC_DCB_VMIN(pipe),
+		       crtc_state->vrr.dc_balance.vmin - 1);
+	intel_de_write(display, PIPEDMC_DCB_VMAX(pipe),
+		       crtc_state->vrr.dc_balance.vmax - 1);
+	intel_de_write(display, PIPEDMC_DCB_MAX_INCREASE(pipe),
+		       crtc_state->vrr.dc_balance.max_increase);
+	intel_de_write(display, PIPEDMC_DCB_MAX_DECREASE(pipe),
+		       crtc_state->vrr.dc_balance.max_decrease);
+	intel_de_write(display, PIPEDMC_DCB_GUARDBAND(pipe),
+		       crtc_state->vrr.dc_balance.guardband);
+	intel_de_write(display, PIPEDMC_DCB_SLOPE(pipe),
+		       crtc_state->vrr.dc_balance.slope);
+	intel_de_write(display, PIPEDMC_DCB_VBLANK(pipe),
+		       crtc_state->vrr.dc_balance.vblank_target);
+	intel_de_write(display, TRANS_ADAPTIVE_SYNC_DCB_CTL(cpu_transcoder),
+		       ADAPTIVE_SYNC_COUNTER_EN);
+}
+
+static void
+intel_vrr_disable_dc_balancing(const struct intel_crtc_state *old_crtc_state)
+{
+	struct intel_display *display = to_intel_display(old_crtc_state);
+	enum transcoder cpu_transcoder = old_crtc_state->cpu_transcoder;
+	struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc);
+	enum pipe pipe = crtc->pipe;
+
+	if (!old_crtc_state->vrr.dc_balance.enable)
+		return;
+
+	intel_de_write(display, TRANS_ADAPTIVE_SYNC_DCB_CTL(cpu_transcoder), 0);
+	intel_de_write(display, PIPEDMC_DCB_VMIN(pipe), 0);
+	intel_de_write(display, PIPEDMC_DCB_VMAX(pipe), 0);
+	intel_de_write(display, PIPEDMC_DCB_MAX_INCREASE(pipe), 0);
+	intel_de_write(display, PIPEDMC_DCB_MAX_DECREASE(pipe), 0);
+	intel_de_write(display, PIPEDMC_DCB_GUARDBAND(pipe), 0);
+	intel_de_write(display, PIPEDMC_DCB_SLOPE(pipe), 0);
+	intel_de_write(display, PIPEDMC_DCB_VBLANK(pipe), 0);
+	intel_de_write(display, TRANS_VRR_DCB_ADJ_VMAX_CFG_LIVE(cpu_transcoder), 0);
+	intel_de_write(display, TRANS_VRR_DCB_ADJ_FLIPLINE_CFG_LIVE(cpu_transcoder), 0);
+	intel_de_write(display, TRANS_VRR_DCB_VMAX_LIVE(cpu_transcoder), 0);
+	intel_de_write(display, TRANS_VRR_DCB_FLIPLINE_LIVE(cpu_transcoder), 0);
+	intel_de_write(display, TRANS_VRR_DCB_ADJ_VMAX_CFG(cpu_transcoder), 0);
+	intel_de_write(display, TRANS_VRR_DCB_ADJ_FLIPLINE_CFG(cpu_transcoder), 0);
+	intel_de_write(display, TRANS_VRR_DCB_VMAX(cpu_transcoder), 0);
+	intel_de_write(display, TRANS_VRR_DCB_FLIPLINE(cpu_transcoder), 0);
+}
+
 static void intel_vrr_tg_enable(const struct intel_crtc_state *crtc_state,
 				bool cmrr_enable)
 {
@@ -827,6 +901,7 @@ void intel_vrr_enable(const struct intel_crtc_state *crtc_state)
 		return;
 
 	intel_vrr_set_vrr_timings(crtc_state);
+	intel_vrr_enable_dc_balancing(crtc_state);
 
 	if (!intel_vrr_always_use_vrr_tg(display))
 		intel_vrr_tg_enable(crtc_state, crtc_state->cmrr.enable);
@@ -842,6 +917,7 @@ void intel_vrr_disable(const struct intel_crtc_state *old_crtc_state)
 	if (!intel_vrr_always_use_vrr_tg(display))
 		intel_vrr_tg_disable(old_crtc_state);
 
+	intel_vrr_disable_dc_balancing(old_crtc_state);
 	intel_vrr_set_fixed_rr_timings(old_crtc_state);
 }
 
-- 
2.48.1

[PATCH v11 12/18] drm/i915/vblank: Extract vrr_vblank_start()

[Mitul Golani]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

Initialise delayed vblank position for evasion logic.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Mitul Golani <mitulkumar.ajitkumar.golani@intel.com>
Reviewed-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
---
 drivers/gpu/drm/i915/display/intel_vblank.c | 13 +++++++++----
 1 file changed, 9 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_vblank.c b/drivers/gpu/drm/i915/display/intel_vblank.c
index 671f357c6563..de20baeb9d99 100644
--- a/drivers/gpu/drm/i915/display/intel_vblank.c
+++ b/drivers/gpu/drm/i915/display/intel_vblank.c
@@ -652,6 +652,14 @@ intel_pre_commit_crtc_state(struct intel_atomic_state *state,
 	return pre_commit_crtc_state(old_crtc_state, new_crtc_state);
 }
 
+static int vrr_vblank_start(const struct intel_crtc_state *crtc_state)
+{
+	if (intel_vrr_is_push_sent(crtc_state))
+		return intel_vrr_vmin_vblank_start(crtc_state);
+	else
+		return intel_vrr_vmax_vblank_start(crtc_state);
+}
+
 void intel_vblank_evade_init(const struct intel_crtc_state *old_crtc_state,
 			     const struct intel_crtc_state *new_crtc_state,
 			     struct intel_vblank_evade_ctx *evade)
@@ -678,10 +686,7 @@ void intel_vblank_evade_init(const struct intel_crtc_state *old_crtc_state,
 		drm_WARN_ON(crtc->base.dev, intel_crtc_needs_modeset(new_crtc_state) ||
 			    new_crtc_state->update_m_n || new_crtc_state->update_lrr);
 
-		if (intel_vrr_is_push_sent(crtc_state))
-			evade->vblank_start = intel_vrr_vmin_vblank_start(crtc_state);
-		else
-			evade->vblank_start = intel_vrr_vmax_vblank_start(crtc_state);
+		evade->vblank_start = vrr_vblank_start(crtc_state);
 
 		vblank_delay = crtc_state->set_context_latency;
 	} else {
-- 
2.48.1

[PATCH v11 13/18] drm/i915/vrr: Implement vblank evasion with DC balancing

[Mitul Golani]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

Add vblank evasion logic when vrr is already enabled along with
dc balance is computed.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Mitul Golani <mitulkumar.ajitkumar.golani@intel.com>
Reviewed-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
---
 drivers/gpu/drm/i915/display/intel_dsb.c    | 31 ++++++++++++++++++++-
 drivers/gpu/drm/i915/display/intel_vblank.c | 26 +++++++++++++++--
 2 files changed, 53 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_dsb.c b/drivers/gpu/drm/i915/display/intel_dsb.c
index ec2a3fb171ab..91060e2a5762 100644
--- a/drivers/gpu/drm/i915/display/intel_dsb.c
+++ b/drivers/gpu/drm/i915/display/intel_dsb.c
@@ -704,7 +704,36 @@ void intel_dsb_vblank_evade(struct intel_atomic_state *state,
 	if (crtc_state->has_psr)
 		intel_dsb_emit_wait_dsl(dsb, DSB_OPCODE_WAIT_DSL_OUT, 0, 0);
 
-	if (pre_commit_is_vrr_active(state, crtc)) {
+	if (pre_commit_is_vrr_active(state, crtc) && crtc_state->vrr.dc_balance.enable) {
+		int vblank_delay = crtc_state->set_context_latency;
+		int vmin_vblank_start, vmax_vblank_start;
+
+		vmin_vblank_start = intel_vrr_dcb_vmin_vblank_start_next(crtc_state);
+
+		if (vmin_vblank_start >= 0) {
+			end = vmin_vblank_start;
+			start = end - vblank_delay - latency;
+			intel_dsb_wait_scanline_out(state, dsb, start, end);
+		}
+
+		vmax_vblank_start = intel_vrr_dcb_vmax_vblank_start_next(crtc_state);
+
+		if (vmax_vblank_start >= 0) {
+			end = vmax_vblank_start;
+			start = end - vblank_delay - latency;
+			intel_dsb_wait_scanline_out(state, dsb, start, end);
+		}
+
+		vmin_vblank_start = intel_vrr_dcb_vmin_vblank_start_final(crtc_state);
+		end = vmin_vblank_start;
+		start = end - vblank_delay - latency;
+		intel_dsb_wait_scanline_out(state, dsb, start, end);
+
+		vmax_vblank_start = intel_vrr_dcb_vmax_vblank_start_final(crtc_state);
+		end = vmax_vblank_start;
+		start = end - vblank_delay - latency;
+		intel_dsb_wait_scanline_out(state, dsb, start, end);
+	} else if (pre_commit_is_vrr_active(state, crtc)) {
 		int vblank_delay = crtc_state->set_context_latency;
 
 		end = intel_vrr_vmin_vblank_start(crtc_state);
diff --git a/drivers/gpu/drm/i915/display/intel_vblank.c b/drivers/gpu/drm/i915/display/intel_vblank.c
index de20baeb9d99..df5879489963 100644
--- a/drivers/gpu/drm/i915/display/intel_vblank.c
+++ b/drivers/gpu/drm/i915/display/intel_vblank.c
@@ -654,10 +654,30 @@ intel_pre_commit_crtc_state(struct intel_atomic_state *state,
 
 static int vrr_vblank_start(const struct intel_crtc_state *crtc_state)
 {
-	if (intel_vrr_is_push_sent(crtc_state))
-		return intel_vrr_vmin_vblank_start(crtc_state);
+	bool is_push_sent = intel_vrr_is_push_sent(crtc_state);
+	int vblank_start;
+
+	if (!crtc_state->vrr.dc_balance.enable) {
+		if (is_push_sent)
+			return intel_vrr_vmin_vblank_start(crtc_state);
+		else
+			return intel_vrr_vmax_vblank_start(crtc_state);
+	}
+
+	if (is_push_sent)
+		vblank_start = intel_vrr_dcb_vmin_vblank_start_next(crtc_state);
 	else
-		return intel_vrr_vmax_vblank_start(crtc_state);
+		vblank_start = intel_vrr_dcb_vmax_vblank_start_next(crtc_state);
+
+	if (vblank_start >= 0)
+		return vblank_start;
+
+	if (is_push_sent)
+		vblank_start = intel_vrr_dcb_vmin_vblank_start_final(crtc_state);
+	else
+		vblank_start = intel_vrr_dcb_vmax_vblank_start_final(crtc_state);
+
+	return vblank_start;
 }
 
 void intel_vblank_evade_init(const struct intel_crtc_state *old_crtc_state,
-- 
2.48.1

[PATCH v11 14/18] drm/i915/display: Wait for VRR PUSH status update

[Mitul Golani]

After VRR Push is sent, need to wait till flipline decision boundary
to get Push bit to get cleared.

--v2:
- Adjust delays to vrr vmin vblank delays. (Ankit)

--v3:
- Change intel_vrr_vmin_safe_window_end() so that
intel_dsb_wait_for_delayed_vblank() uses correct delay. (Ankit)

--v4:
- Simplify intel_vrr_vmin_safe_window_end implementation. (Ankit)

Signed-off-by: Mitul Golani <mitulkumar.ajitkumar.golani@intel.com>
Reviewed-by: Uma Shankar <uma.shankar@intel.com>
Reviewed-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
---
 drivers/gpu/drm/i915/display/intel_vrr.c | 15 +++++++++++++--
 1 file changed, 13 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_vrr.c b/drivers/gpu/drm/i915/display/intel_vrr.c
index 68b39fe0f7bc..a4a198a28519 100644
--- a/drivers/gpu/drm/i915/display/intel_vrr.c
+++ b/drivers/gpu/drm/i915/display/intel_vrr.c
@@ -1095,10 +1095,21 @@ int intel_vrr_safe_window_start(const struct intel_crtc_state *crtc_state)
 		return crtc_state->hw.adjusted_mode.crtc_vdisplay;
 }
 
+static int
+intel_vrr_dcb_vmin_vblank_start(const struct intel_crtc_state *crtc_state)
+{
+	return (intel_vrr_dcb_vmin_vblank_start_next(crtc_state) < 0) ?
+		intel_vrr_dcb_vmin_vblank_start_final(crtc_state) :
+		intel_vrr_dcb_vmin_vblank_start_next(crtc_state);
+}
+
 int intel_vrr_vmin_safe_window_end(const struct intel_crtc_state *crtc_state)
 {
-	return intel_vrr_vmin_vblank_start(crtc_state) -
-	       crtc_state->set_context_latency;
+	int vmin_vblank_start = crtc_state->vrr.dc_balance.enable ?
+			intel_vrr_dcb_vmin_vblank_start(crtc_state) :
+			intel_vrr_vmin_vblank_start(crtc_state);
+
+	return vmin_vblank_start - crtc_state->set_context_latency;
 }
 
 int intel_vrr_dcb_vmin_vblank_start_next(const struct intel_crtc_state *crtc_state)
-- 
2.48.1

[PATCH v11 15/18] drm/i915/dsb: Add pipedmc dc balance enable/disable

[Mitul Golani]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

Add function to control DC balance enable/disable bit via DSB.

--v2:
Remove redundant forward declaration.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Mitul Golani <mitulkumar.ajitkumar.golani@intel.com>
Reviewed-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
---
 drivers/gpu/drm/i915/display/intel_dmc.c | 17 +++++++++++++++++
 drivers/gpu/drm/i915/display/intel_dmc.h |  3 +++
 2 files changed, 20 insertions(+)

diff --git a/drivers/gpu/drm/i915/display/intel_dmc.c b/drivers/gpu/drm/i915/display/intel_dmc.c
index 2fb6fec6dc99..e076ba7e0f28 100644
--- a/drivers/gpu/drm/i915/display/intel_dmc.c
+++ b/drivers/gpu/drm/i915/display/intel_dmc.c
@@ -1755,3 +1755,20 @@ u32 intel_pipedmc_start_mmioaddr(struct intel_crtc *crtc)
 
 	return dmc ? dmc->dmc_info[dmc_id].start_mmioaddr : 0;
 }
+
+void intel_pipedmc_dcb_enable(struct intel_dsb *dsb, struct intel_crtc *crtc)
+{
+	struct intel_display *display = to_intel_display(crtc);
+	enum pipe pipe = crtc->pipe;
+
+	intel_de_write_dsb(display, dsb, PIPEDMC_DCB_CTL(pipe),
+			   PIPEDMC_ADAPTIVE_DCB_ENABLE);
+}
+
+void intel_pipedmc_dcb_disable(struct intel_dsb *dsb, struct intel_crtc *crtc)
+{
+	struct intel_display *display = to_intel_display(crtc);
+	enum pipe pipe = crtc->pipe;
+
+	intel_de_write_dsb(display, dsb, PIPEDMC_DCB_CTL(pipe), 0);
+}
diff --git a/drivers/gpu/drm/i915/display/intel_dmc.h b/drivers/gpu/drm/i915/display/intel_dmc.h
index 40e9dcb033cc..9c6a42fc820e 100644
--- a/drivers/gpu/drm/i915/display/intel_dmc.h
+++ b/drivers/gpu/drm/i915/display/intel_dmc.h
@@ -15,6 +15,7 @@ struct intel_crtc;
 struct intel_crtc_state;
 struct intel_display;
 struct intel_dmc_snapshot;
+struct intel_dsb;
 
 void intel_dmc_init(struct intel_display *display);
 void intel_dmc_load_program(struct intel_display *display);
@@ -39,6 +40,8 @@ void intel_dmc_update_dc6_allowed_count(struct intel_display *display, bool star
 void assert_main_dmc_loaded(struct intel_display *display);
 
 void intel_pipedmc_irq_handler(struct intel_display *display, enum pipe pipe);
+void intel_pipedmc_dcb_enable(struct intel_dsb *dsb, struct intel_crtc *crtc);
+void intel_pipedmc_dcb_disable(struct intel_dsb *dsb, struct intel_crtc *crtc);
 
 u32 intel_pipedmc_start_mmioaddr(struct intel_crtc *crtc);
 void intel_pipedmc_enable_event(struct intel_crtc *crtc,
-- 
2.48.1

[PATCH v11 16/18] drm/i915/vrr: Pause DC Balancing for DSB commits

[Mitul Golani]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

Pause the DMC DC Balancing for the remainder of the
commit so that vmin/vmax won't change after we've baked
them into the DSB vblank evasion commands.

--v2:
- Remove typo. (Ankit)
- Separate vrr enable structuring. (Ankit)

--v3:
- Add gaurd before accessing DC balance bits.
- Remove redundancy checks.

--v4:
- Move events to separate function.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Mitul Golani <mitulkumar.ajitkumar.golani@intel.com>
Reviewed-by: Uma Shankar <uma.shankar@intel.com>
Reviewed-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
---
 drivers/gpu/drm/i915/display/intel_display.c | 19 +++++++++++++++++++
 drivers/gpu/drm/i915/display/intel_vrr.c     |  3 +++
 2 files changed, 22 insertions(+)

diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 70ae5582ab0b..5b03b0cb5332 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -7330,6 +7330,21 @@ static void intel_atomic_dsb_finish(struct intel_atomic_state *state,
 		if (new_crtc_state->use_flipq)
 			intel_flipq_wait_dmc_halt(new_crtc_state->dsb_commit, crtc);
 
+		if (new_crtc_state->vrr.dc_balance.enable) {
+			/*
+			 * Pause the DMC DC balancing for the remainder of
+			 * the commit so that vmin/vmax won't change after
+			 * we've baked them into the DSB vblank evasion
+			 * commands.
+			 *
+			 * FIXME maybe need a small delay here to make sure
+			 * DMC has finished updating the values? Or we need
+			 * a better DMC<->driver protocol that gives is real
+			 * guarantees about that...
+			 */
+			intel_pipedmc_dcb_disable(NULL, crtc);
+		}
+
 		if (intel_crtc_needs_color_update(new_crtc_state))
 			intel_color_commit_noarm(new_crtc_state->dsb_commit,
 						 new_crtc_state);
@@ -7383,6 +7398,10 @@ static void intel_atomic_dsb_finish(struct intel_atomic_state *state,
 		intel_dsb_wait_for_delayed_vblank(state, new_crtc_state->dsb_commit);
 		intel_vrr_check_push_sent(new_crtc_state->dsb_commit,
 					  new_crtc_state);
+
+		if (new_crtc_state->vrr.dc_balance.enable)
+			intel_pipedmc_dcb_enable(new_crtc_state->dsb_commit, crtc);
+
 		intel_dsb_interrupt(new_crtc_state->dsb_commit);
 	}
 
diff --git a/drivers/gpu/drm/i915/display/intel_vrr.c b/drivers/gpu/drm/i915/display/intel_vrr.c
index a4a198a28519..ac612cf08d98 100644
--- a/drivers/gpu/drm/i915/display/intel_vrr.c
+++ b/drivers/gpu/drm/i915/display/intel_vrr.c
@@ -10,6 +10,7 @@
 #include "intel_de.h"
 #include "intel_display_regs.h"
 #include "intel_display_types.h"
+#include "intel_dmc.h"
 #include "intel_dmc_regs.h"
 #include "intel_dp.h"
 #include "intel_psr.h"
@@ -824,6 +825,7 @@ intel_vrr_enable_dc_balancing(const struct intel_crtc_state *crtc_state)
 		       crtc_state->vrr.dc_balance.vblank_target);
 	intel_de_write(display, TRANS_ADAPTIVE_SYNC_DCB_CTL(cpu_transcoder),
 		       ADAPTIVE_SYNC_COUNTER_EN);
+	intel_pipedmc_dcb_enable(NULL, crtc);
 }
 
 static void
@@ -837,6 +839,7 @@ intel_vrr_disable_dc_balancing(const struct intel_crtc_state *old_crtc_state)
 	if (!old_crtc_state->vrr.dc_balance.enable)
 		return;
 
+	intel_pipedmc_dcb_disable(NULL, crtc);
 	intel_de_write(display, TRANS_ADAPTIVE_SYNC_DCB_CTL(cpu_transcoder), 0);
 	intel_de_write(display, PIPEDMC_DCB_VMIN(pipe), 0);
 	intel_de_write(display, PIPEDMC_DCB_VMAX(pipe), 0);
-- 
2.48.1

[PATCH v11 17/18] drm/i915/display: Add function to configure event for dc balance

[Mitul Golani]

Configure pipe dmc event for dc balance enable/disable.

--v2:
- Keeping function and removing unnecessary comments. (Jani, Nikula)

Signed-off-by: Mitul Golani <mitulkumar.ajitkumar.golani@intel.com>
Reviewed-by: Uma Shankar <uma.shankar@intel.com>
Reviewed-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
---
 drivers/gpu/drm/i915/display/intel_dmc.c | 8 ++++++++
 drivers/gpu/drm/i915/display/intel_dmc.h | 2 ++
 drivers/gpu/drm/i915/display/intel_vrr.c | 2 ++
 3 files changed, 12 insertions(+)

diff --git a/drivers/gpu/drm/i915/display/intel_dmc.c b/drivers/gpu/drm/i915/display/intel_dmc.c
index e076ba7e0f28..1182bc9a2e6d 100644
--- a/drivers/gpu/drm/i915/display/intel_dmc.c
+++ b/drivers/gpu/drm/i915/display/intel_dmc.c
@@ -859,6 +859,14 @@ static void dmc_configure_event(struct intel_display *display,
 		      dmc_id, num_handlers, event_id);
 }
 
+void intel_dmc_configure_dc_balance_event(struct intel_display *display,
+					  enum pipe pipe, bool enable)
+{
+	enum intel_dmc_id dmc_id = PIPE_TO_DMC_ID(pipe);
+
+	dmc_configure_event(display, dmc_id, PIPEDMC_EVENT_ADAPTIVE_DCB_TRIGGER, enable);
+}
+
 /**
  * intel_dmc_block_pkgc() - block PKG C-state
  * @display: display instance
diff --git a/drivers/gpu/drm/i915/display/intel_dmc.h b/drivers/gpu/drm/i915/display/intel_dmc.h
index 9c6a42fc820e..3d8a9a593319 100644
--- a/drivers/gpu/drm/i915/display/intel_dmc.h
+++ b/drivers/gpu/drm/i915/display/intel_dmc.h
@@ -25,6 +25,8 @@ void intel_dmc_enable_pipe(const struct intel_crtc_state *crtc_state);
 void intel_dmc_disable_pipe(const struct intel_crtc_state *crtc_state);
 void intel_dmc_block_pkgc(struct intel_display *display, enum pipe pipe,
 			  bool block);
+void intel_dmc_configure_dc_balance_event(struct intel_display *display,
+					  enum pipe pipe, bool enable);
 void intel_dmc_start_pkgc_exit_at_start_of_undelayed_vblank(struct intel_display *display,
 							    enum pipe pipe, bool enable);
 void intel_dmc_fini(struct intel_display *display);
diff --git a/drivers/gpu/drm/i915/display/intel_vrr.c b/drivers/gpu/drm/i915/display/intel_vrr.c
index ac612cf08d98..1522ec3a98b8 100644
--- a/drivers/gpu/drm/i915/display/intel_vrr.c
+++ b/drivers/gpu/drm/i915/display/intel_vrr.c
@@ -823,6 +823,7 @@ intel_vrr_enable_dc_balancing(const struct intel_crtc_state *crtc_state)
 		       crtc_state->vrr.dc_balance.slope);
 	intel_de_write(display, PIPEDMC_DCB_VBLANK(pipe),
 		       crtc_state->vrr.dc_balance.vblank_target);
+	intel_dmc_configure_dc_balance_event(display, pipe, true);
 	intel_de_write(display, TRANS_ADAPTIVE_SYNC_DCB_CTL(cpu_transcoder),
 		       ADAPTIVE_SYNC_COUNTER_EN);
 	intel_pipedmc_dcb_enable(NULL, crtc);
@@ -840,6 +841,7 @@ intel_vrr_disable_dc_balancing(const struct intel_crtc_state *old_crtc_state)
 		return;
 
 	intel_pipedmc_dcb_disable(NULL, crtc);
+	intel_dmc_configure_dc_balance_event(display, pipe, false);
 	intel_de_write(display, TRANS_ADAPTIVE_SYNC_DCB_CTL(cpu_transcoder), 0);
 	intel_de_write(display, PIPEDMC_DCB_VMIN(pipe), 0);
 	intel_de_write(display, PIPEDMC_DCB_VMAX(pipe), 0);
-- 
2.48.1

[PATCH v11 18/18] drm/i915/vrr: Enable DC Balance

[Mitul Golani]

Enable DC Balance from vrr compute config and related hw flag.
Also to add pipe restrictions along with this.

--v2:
- Use dc balance check instead of source restriction.
--v3:
- Club pipe restriction check with dc balance enablement. (Ankit)
--v4:
- Separate out Pipe restrictions to patch#7

Signed-off-by: Mitul Golani <mitulkumar.ajitkumar.golani@intel.com>
Reviewed-by: Uma Shankar <uma.shankar@intel.com>
---
 drivers/gpu/drm/i915/display/intel_vrr.c | 9 +++++++++
 1 file changed, 9 insertions(+)

diff --git a/drivers/gpu/drm/i915/display/intel_vrr.c b/drivers/gpu/drm/i915/display/intel_vrr.c
index 1522ec3a98b8..db74744ddb31 100644
--- a/drivers/gpu/drm/i915/display/intel_vrr.c
+++ b/drivers/gpu/drm/i915/display/intel_vrr.c
@@ -399,6 +399,7 @@ intel_vrr_dc_balance_compute_config(struct intel_crtc_state *crtc_state)
 	crtc_state->vrr.dc_balance.vblank_target =
 		DIV_ROUND_UP((crtc_state->vrr.vmax - crtc_state->vrr.vmin) *
 			     DCB_BLANK_TARGET, 100);
+	crtc_state->vrr.dc_balance.enable = true;
 }
 
 void
@@ -789,6 +790,7 @@ intel_vrr_enable_dc_balancing(const struct intel_crtc_state *crtc_state)
 	enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
 	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
 	enum pipe pipe = crtc->pipe;
+	u32 vrr_ctl = intel_de_read(display, TRANS_VRR_CTL(display, cpu_transcoder));
 
 	if (!crtc_state->vrr.dc_balance.enable)
 		return;
@@ -827,6 +829,9 @@ intel_vrr_enable_dc_balancing(const struct intel_crtc_state *crtc_state)
 	intel_de_write(display, TRANS_ADAPTIVE_SYNC_DCB_CTL(cpu_transcoder),
 		       ADAPTIVE_SYNC_COUNTER_EN);
 	intel_pipedmc_dcb_enable(NULL, crtc);
+
+	vrr_ctl |= VRR_CTL_DCB_ADJ_ENABLE;
+	intel_de_write(display, TRANS_VRR_CTL(display, cpu_transcoder), vrr_ctl);
 }
 
 static void
@@ -836,6 +841,7 @@ intel_vrr_disable_dc_balancing(const struct intel_crtc_state *old_crtc_state)
 	enum transcoder cpu_transcoder = old_crtc_state->cpu_transcoder;
 	struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc);
 	enum pipe pipe = crtc->pipe;
+	u32 vrr_ctl = intel_de_read(display, TRANS_VRR_CTL(display, cpu_transcoder));
 
 	if (!old_crtc_state->vrr.dc_balance.enable)
 		return;
@@ -858,6 +864,9 @@ intel_vrr_disable_dc_balancing(const struct intel_crtc_state *old_crtc_state)
 	intel_de_write(display, TRANS_VRR_DCB_ADJ_FLIPLINE_CFG(cpu_transcoder), 0);
 	intel_de_write(display, TRANS_VRR_DCB_VMAX(cpu_transcoder), 0);
 	intel_de_write(display, TRANS_VRR_DCB_FLIPLINE(cpu_transcoder), 0);
+
+	vrr_ctl &= ~VRR_CTL_DCB_ADJ_ENABLE;
+	intel_de_write(display, TRANS_VRR_CTL(display, cpu_transcoder), vrr_ctl);
 }
 
 static void intel_vrr_tg_enable(const struct intel_crtc_state *crtc_state,
-- 
2.48.1

✗ CI.checkpatch: warning for Enable/Disable DC balance along with VRR DSB

[Patchwork]

== Series Details ==

Series: Enable/Disable DC balance along with VRR DSB
URL   : https://patchwork.freedesktop.org/series/159419/
State : warning

== Summary ==

+ KERNEL=/kernel
+ git clone https://gitlab.freedesktop.org/drm/maintainer-tools mt
Cloning into 'mt'...
warning: redirecting to https://gitlab.freedesktop.org/drm/maintainer-tools.git/
+ git -C mt rev-list -n1 origin/master
99339247d1ae4378b24366da182e712bdc623311
+ cd /kernel
+ git config --global --add safe.directory /kernel
+ git log -n1
commit 5e3b6585a69caeb28d807edeeb6a80857b9baeaf
Author: Mitul Golani <mitulkumar.ajitkumar.golani@intel.com>
Date:   Tue Dec 23 16:15:40 2025 +0530

    drm/i915/vrr: Enable DC Balance
    
    Enable DC Balance from vrr compute config and related hw flag.
    Also to add pipe restrictions along with this.
    
    --v2:
    - Use dc balance check instead of source restriction.
    --v3:
    - Club pipe restriction check with dc balance enablement. (Ankit)
    --v4:
    - Separate out Pipe restrictions to patch#7
    
    Signed-off-by: Mitul Golani <mitulkumar.ajitkumar.golani@intel.com>
    Reviewed-by: Uma Shankar <uma.shankar@intel.com>
+ /mt/dim checkpatch cab246648fd89efbe8d20ed4c86e7fcebd7606da drm-intel
2a066cfa123a drm/i915/display: Add source param for dc balance
655a677b2695 drm/i915/dmc: Add pipe dmc registers and bits for DC Balance
f6c9cf937a88 drm/i915/vrr: Add VRR DC balance registers
-:61: WARNING:LONG_LINE: line length of 109 exceeds 100 columns
#61: FILE: drivers/gpu/drm/i915/display/intel_vrr_regs.h:24:
+								    _TRANS_VRR_DCB_ADJ_FLIPLINE_CFG_LIVE_A, \

-:62: WARNING:LONG_LINE: line length of 107 exceeds 100 columns
#62: FILE: drivers/gpu/drm/i915/display/intel_vrr_regs.h:25:
+								    _TRANS_VRR_DCB_ADJ_FLIPLINE_CFG_LIVE_B)

total: 0 errors, 2 warnings, 0 checks, 80 lines checked
04209352278b drm/i915/vrr: Add functions to read out vmin/vmax stuff
42e9ec95ddb4 drm/i915/vrr: Add DC Balance params to crtc_state
63771037fb5e drm/i915/vrr: Add state dump for DC Balance params
f463dcc52a75 drm/i915/vrr: Add compute config for DC Balance params
6a2967f904f3 drm/i915/vrr: Add function to check if DC Balance Possible
935694999a7f drm/i915/vrr: Add function to reset DC balance accumulated params
60cebc07492f drm/i915/display: Add DC Balance flip count operations
eec9aa0e770d drm/i915/vrr: Write DC balance params to hw registers
d73900b9bcc6 drm/i915/vblank: Extract vrr_vblank_start()
b68dba468c99 drm/i915/vrr: Implement vblank evasion with DC balancing
bf2cc78c6422 drm/i915/display: Wait for VRR PUSH status update
4f8d9c906cdd drm/i915/dsb: Add pipedmc dc balance enable/disable
a61cfeac524c drm/i915/vrr: Pause DC Balancing for DSB commits
689b924aff95 drm/i915/display: Add function to configure event for dc balance
5e3b6585a69c drm/i915/vrr: Enable DC Balance

✓ CI.KUnit: success for Enable/Disable DC balance along with VRR DSB

[Patchwork]

== Series Details ==

Series: Enable/Disable DC balance along with VRR DSB
URL   : https://patchwork.freedesktop.org/series/159419/
State : success

== Summary ==

+ trap cleanup EXIT
+ /kernel/tools/testing/kunit/kunit.py run --kunitconfig /kernel/drivers/gpu/drm/xe/.kunitconfig
[10:57:02] Configuring KUnit Kernel ...
Generating .config ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
[10:57:06] Building KUnit Kernel ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
Building with:
$ make all compile_commands.json scripts_gdb ARCH=um O=.kunit --jobs=48
[10:57:38] Starting KUnit Kernel (1/1)...
[10:57:38] ============================================================
Running tests with:
$ .kunit/linux kunit.enable=1 mem=1G console=tty kunit_shutdown=halt
[10:57:38] ================== guc_buf (11 subtests) ===================
[10:57:38] [PASSED] test_smallest
[10:57:38] [PASSED] test_largest
[10:57:38] [PASSED] test_granular
[10:57:38] [PASSED] test_unique
[10:57:38] [PASSED] test_overlap
[10:57:38] [PASSED] test_reusable
[10:57:38] [PASSED] test_too_big
[10:57:38] [PASSED] test_flush
[10:57:38] [PASSED] test_lookup
[10:57:38] [PASSED] test_data
[10:57:38] [PASSED] test_class
[10:57:38] ===================== [PASSED] guc_buf =====================
[10:57:38] =================== guc_dbm (7 subtests) ===================
[10:57:38] [PASSED] test_empty
[10:57:38] [PASSED] test_default
[10:57:38] ======================== test_size  ========================
[10:57:38] [PASSED] 4
[10:57:38] [PASSED] 8
[10:57:38] [PASSED] 32
[10:57:38] [PASSED] 256
[10:57:38] ==================== [PASSED] test_size ====================
[10:57:38] ======================= test_reuse  ========================
[10:57:38] [PASSED] 4
[10:57:38] [PASSED] 8
[10:57:38] [PASSED] 32
[10:57:38] [PASSED] 256
[10:57:38] =================== [PASSED] test_reuse ====================
[10:57:38] =================== test_range_overlap  ====================
[10:57:38] [PASSED] 4
[10:57:38] [PASSED] 8
[10:57:38] [PASSED] 32
[10:57:38] [PASSED] 256
[10:57:38] =============== [PASSED] test_range_overlap ================
[10:57:38] =================== test_range_compact  ====================
[10:57:38] [PASSED] 4
[10:57:38] [PASSED] 8
[10:57:38] [PASSED] 32
[10:57:38] [PASSED] 256
[10:57:38] =============== [PASSED] test_range_compact ================
[10:57:38] ==================== test_range_spare  =====================
[10:57:38] [PASSED] 4
[10:57:38] [PASSED] 8
[10:57:38] [PASSED] 32
[10:57:38] [PASSED] 256
[10:57:38] ================ [PASSED] test_range_spare =================
[10:57:38] ===================== [PASSED] guc_dbm =====================
[10:57:38] =================== guc_idm (6 subtests) ===================
[10:57:38] [PASSED] bad_init
[10:57:38] [PASSED] no_init
[10:57:38] [PASSED] init_fini
[10:57:38] [PASSED] check_used
[10:57:38] [PASSED] check_quota
[10:57:38] [PASSED] check_all
[10:57:38] ===================== [PASSED] guc_idm =====================
[10:57:38] ================== no_relay (3 subtests) ===================
[10:57:38] [PASSED] xe_drops_guc2pf_if_not_ready
[10:57:38] [PASSED] xe_drops_guc2vf_if_not_ready
[10:57:38] [PASSED] xe_rejects_send_if_not_ready
[10:57:38] ==================== [PASSED] no_relay =====================
[10:57:38] ================== pf_relay (14 subtests) ==================
[10:57:38] [PASSED] pf_rejects_guc2pf_too_short
[10:57:38] [PASSED] pf_rejects_guc2pf_too_long
[10:57:38] [PASSED] pf_rejects_guc2pf_no_payload
[10:57:38] [PASSED] pf_fails_no_payload
[10:57:38] [PASSED] pf_fails_bad_origin
[10:57:38] [PASSED] pf_fails_bad_type
[10:57:38] [PASSED] pf_txn_reports_error
[10:57:38] [PASSED] pf_txn_sends_pf2guc
[10:57:38] [PASSED] pf_sends_pf2guc
[10:57:38] [SKIPPED] pf_loopback_nop
[10:57:38] [SKIPPED] pf_loopback_echo
[10:57:38] [SKIPPED] pf_loopback_fail
[10:57:38] [SKIPPED] pf_loopback_busy
[10:57:38] [SKIPPED] pf_loopback_retry
[10:57:38] ==================== [PASSED] pf_relay =====================
[10:57:38] ================== vf_relay (3 subtests) ===================
[10:57:38] [PASSED] vf_rejects_guc2vf_too_short
[10:57:38] [PASSED] vf_rejects_guc2vf_too_long
[10:57:38] [PASSED] vf_rejects_guc2vf_no_payload
[10:57:38] ==================== [PASSED] vf_relay =====================
[10:57:38] ================ pf_gt_config (6 subtests) =================
[10:57:38] [PASSED] fair_contexts_1vf
[10:57:38] [PASSED] fair_doorbells_1vf
[10:57:38] [PASSED] fair_ggtt_1vf
[10:57:38] ====================== fair_contexts  ======================
[10:57:38] [PASSED] 1 VF
[10:57:38] [PASSED] 2 VFs
[10:57:38] [PASSED] 3 VFs
[10:57:38] [PASSED] 4 VFs
[10:57:38] [PASSED] 5 VFs
[10:57:38] [PASSED] 6 VFs
[10:57:38] [PASSED] 7 VFs
[10:57:38] [PASSED] 8 VFs
[10:57:38] [PASSED] 9 VFs
[10:57:38] [PASSED] 10 VFs
[10:57:38] [PASSED] 11 VFs
[10:57:38] [PASSED] 12 VFs
[10:57:38] [PASSED] 13 VFs
[10:57:38] [PASSED] 14 VFs
[10:57:38] [PASSED] 15 VFs
[10:57:38] [PASSED] 16 VFs
[10:57:38] [PASSED] 17 VFs
[10:57:38] [PASSED] 18 VFs
[10:57:38] [PASSED] 19 VFs
[10:57:38] [PASSED] 20 VFs
[10:57:38] [PASSED] 21 VFs
[10:57:38] [PASSED] 22 VFs
[10:57:38] [PASSED] 23 VFs
[10:57:38] [PASSED] 24 VFs
[10:57:38] [PASSED] 25 VFs
[10:57:38] [PASSED] 26 VFs
[10:57:38] [PASSED] 27 VFs
[10:57:38] [PASSED] 28 VFs
[10:57:38] [PASSED] 29 VFs
[10:57:38] [PASSED] 30 VFs
[10:57:38] [PASSED] 31 VFs
[10:57:38] [PASSED] 32 VFs
[10:57:38] [PASSED] 33 VFs
[10:57:38] [PASSED] 34 VFs
[10:57:38] [PASSED] 35 VFs
[10:57:38] [PASSED] 36 VFs
[10:57:38] [PASSED] 37 VFs
[10:57:38] [PASSED] 38 VFs
[10:57:38] [PASSED] 39 VFs
[10:57:38] [PASSED] 40 VFs
[10:57:38] [PASSED] 41 VFs
[10:57:38] [PASSED] 42 VFs
[10:57:38] [PASSED] 43 VFs
[10:57:38] [PASSED] 44 VFs
[10:57:38] [PASSED] 45 VFs
[10:57:38] [PASSED] 46 VFs
[10:57:38] [PASSED] 47 VFs
[10:57:38] [PASSED] 48 VFs
[10:57:38] [PASSED] 49 VFs
[10:57:38] [PASSED] 50 VFs
[10:57:38] [PASSED] 51 VFs
[10:57:38] [PASSED] 52 VFs
[10:57:38] [PASSED] 53 VFs
[10:57:38] [PASSED] 54 VFs
[10:57:38] [PASSED] 55 VFs
[10:57:38] [PASSED] 56 VFs
[10:57:38] [PASSED] 57 VFs
[10:57:38] [PASSED] 58 VFs
[10:57:38] [PASSED] 59 VFs
[10:57:38] [PASSED] 60 VFs
[10:57:38] [PASSED] 61 VFs
[10:57:38] [PASSED] 62 VFs
[10:57:38] [PASSED] 63 VFs
[10:57:38] ================== [PASSED] fair_contexts ==================
[10:57:38] ===================== fair_doorbells  ======================
[10:57:38] [PASSED] 1 VF
[10:57:38] [PASSED] 2 VFs
[10:57:38] [PASSED] 3 VFs
[10:57:38] [PASSED] 4 VFs
[10:57:38] [PASSED] 5 VFs
[10:57:38] [PASSED] 6 VFs
[10:57:38] [PASSED] 7 VFs
[10:57:38] [PASSED] 8 VFs
[10:57:38] [PASSED] 9 VFs
[10:57:38] [PASSED] 10 VFs
[10:57:38] [PASSED] 11 VFs
[10:57:38] [PASSED] 12 VFs
[10:57:38] [PASSED] 13 VFs
[10:57:38] [PASSED] 14 VFs
[10:57:38] [PASSED] 15 VFs
[10:57:38] [PASSED] 16 VFs
[10:57:38] [PASSED] 17 VFs
[10:57:38] [PASSED] 18 VFs
[10:57:38] [PASSED] 19 VFs
[10:57:38] [PASSED] 20 VFs
[10:57:38] [PASSED] 21 VFs
[10:57:38] [PASSED] 22 VFs
[10:57:38] [PASSED] 23 VFs
[10:57:38] [PASSED] 24 VFs
[10:57:38] [PASSED] 25 VFs
[10:57:38] [PASSED] 26 VFs
[10:57:38] [PASSED] 27 VFs
[10:57:38] [PASSED] 28 VFs
[10:57:38] [PASSED] 29 VFs
[10:57:38] [PASSED] 30 VFs
[10:57:38] [PASSED] 31 VFs
[10:57:38] [PASSED] 32 VFs
[10:57:38] [PASSED] 33 VFs
[10:57:38] [PASSED] 34 VFs
[10:57:38] [PASSED] 35 VFs
[10:57:38] [PASSED] 36 VFs
[10:57:38] [PASSED] 37 VFs
[10:57:38] [PASSED] 38 VFs
[10:57:38] [PASSED] 39 VFs
[10:57:38] [PASSED] 40 VFs
[10:57:38] [PASSED] 41 VFs
[10:57:38] [PASSED] 42 VFs
[10:57:38] [PASSED] 43 VFs
[10:57:38] [PASSED] 44 VFs
[10:57:38] [PASSED] 45 VFs
[10:57:38] [PASSED] 46 VFs
[10:57:38] [PASSED] 47 VFs
[10:57:38] [PASSED] 48 VFs
[10:57:38] [PASSED] 49 VFs
[10:57:38] [PASSED] 50 VFs
[10:57:38] [PASSED] 51 VFs
[10:57:38] [PASSED] 52 VFs
[10:57:38] [PASSED] 53 VFs
[10:57:38] [PASSED] 54 VFs
[10:57:38] [PASSED] 55 VFs
[10:57:38] [PASSED] 56 VFs
[10:57:38] [PASSED] 57 VFs
[10:57:38] [PASSED] 58 VFs
[10:57:38] [PASSED] 59 VFs
[10:57:38] [PASSED] 60 VFs
[10:57:38] [PASSED] 61 VFs
[10:57:38] [PASSED] 62 VFs
[10:57:38] [PASSED] 63 VFs
[10:57:38] ================= [PASSED] fair_doorbells ==================
[10:57:38] ======================== fair_ggtt  ========================
[10:57:38] [PASSED] 1 VF
[10:57:38] [PASSED] 2 VFs
[10:57:38] [PASSED] 3 VFs
[10:57:38] [PASSED] 4 VFs
[10:57:38] [PASSED] 5 VFs
[10:57:38] [PASSED] 6 VFs
[10:57:38] [PASSED] 7 VFs
[10:57:38] [PASSED] 8 VFs
[10:57:38] [PASSED] 9 VFs
[10:57:38] [PASSED] 10 VFs
[10:57:38] [PASSED] 11 VFs
[10:57:38] [PASSED] 12 VFs
[10:57:38] [PASSED] 13 VFs
[10:57:38] [PASSED] 14 VFs
[10:57:38] [PASSED] 15 VFs
[10:57:38] [PASSED] 16 VFs
[10:57:38] [PASSED] 17 VFs
[10:57:38] [PASSED] 18 VFs
[10:57:38] [PASSED] 19 VFs
[10:57:38] [PASSED] 20 VFs
[10:57:38] [PASSED] 21 VFs
[10:57:38] [PASSED] 22 VFs
[10:57:38] [PASSED] 23 VFs
[10:57:38] [PASSED] 24 VFs
[10:57:38] [PASSED] 25 VFs
[10:57:38] [PASSED] 26 VFs
[10:57:38] [PASSED] 27 VFs
[10:57:38] [PASSED] 28 VFs
[10:57:38] [PASSED] 29 VFs
[10:57:38] [PASSED] 30 VFs
[10:57:38] [PASSED] 31 VFs
[10:57:38] [PASSED] 32 VFs
[10:57:38] [PASSED] 33 VFs
[10:57:38] [PASSED] 34 VFs
[10:57:38] [PASSED] 35 VFs
[10:57:38] [PASSED] 36 VFs
[10:57:38] [PASSED] 37 VFs
[10:57:38] [PASSED] 38 VFs
[10:57:38] [PASSED] 39 VFs
[10:57:38] [PASSED] 40 VFs
[10:57:38] [PASSED] 41 VFs
[10:57:38] [PASSED] 42 VFs
[10:57:38] [PASSED] 43 VFs
[10:57:38] [PASSED] 44 VFs
[10:57:38] [PASSED] 45 VFs
[10:57:38] [PASSED] 46 VFs
[10:57:38] [PASSED] 47 VFs
[10:57:38] [PASSED] 48 VFs
[10:57:38] [PASSED] 49 VFs
[10:57:38] [PASSED] 50 VFs
[10:57:38] [PASSED] 51 VFs
[10:57:38] [PASSED] 52 VFs
[10:57:38] [PASSED] 53 VFs
[10:57:38] [PASSED] 54 VFs
[10:57:38] [PASSED] 55 VFs
[10:57:38] [PASSED] 56 VFs
[10:57:38] [PASSED] 57 VFs
[10:57:38] [PASSED] 58 VFs
[10:57:38] [PASSED] 59 VFs
[10:57:38] [PASSED] 60 VFs
[10:57:38] [PASSED] 61 VFs
[10:57:38] [PASSED] 62 VFs
[10:57:38] [PASSED] 63 VFs
[10:57:38] ==================== [PASSED] fair_ggtt ====================
[10:57:38] ================== [PASSED] pf_gt_config ===================
[10:57:38] ===================== lmtt (1 subtest) =====================
[10:57:38] ======================== test_ops  =========================
[10:57:38] [PASSED] 2-level
[10:57:38] [PASSED] multi-level
[10:57:38] ==================== [PASSED] test_ops =====================
[10:57:38] ====================== [PASSED] lmtt =======================
[10:57:38] ================= pf_service (11 subtests) =================
[10:57:38] [PASSED] pf_negotiate_any
[10:57:38] [PASSED] pf_negotiate_base_match
[10:57:38] [PASSED] pf_negotiate_base_newer
[10:57:38] [PASSED] pf_negotiate_base_next
[10:57:38] [SKIPPED] pf_negotiate_base_older
[10:57:38] [PASSED] pf_negotiate_base_prev
[10:57:38] [PASSED] pf_negotiate_latest_match
[10:57:38] [PASSED] pf_negotiate_latest_newer
[10:57:38] [PASSED] pf_negotiate_latest_next
[10:57:38] [SKIPPED] pf_negotiate_latest_older
[10:57:38] [SKIPPED] pf_negotiate_latest_prev
[10:57:38] =================== [PASSED] pf_service ====================
[10:57:38] ================= xe_guc_g2g (2 subtests) ==================
[10:57:38] ============== xe_live_guc_g2g_kunit_default  ==============
[10:57:38] ========= [SKIPPED] xe_live_guc_g2g_kunit_default ==========
[10:57:38] ============== xe_live_guc_g2g_kunit_allmem  ===============
[10:57:38] ========== [SKIPPED] xe_live_guc_g2g_kunit_allmem ==========
[10:57:38] =================== [SKIPPED] xe_guc_g2g ===================
[10:57:38] =================== xe_mocs (2 subtests) ===================
[10:57:38] ================ xe_live_mocs_kernel_kunit  ================
[10:57:38] =========== [SKIPPED] xe_live_mocs_kernel_kunit ============
[10:57:38] ================ xe_live_mocs_reset_kunit  =================
[10:57:38] ============ [SKIPPED] xe_live_mocs_reset_kunit ============
[10:57:38] ==================== [SKIPPED] xe_mocs =====================
[10:57:38] ================= xe_migrate (2 subtests) ==================
[10:57:38] ================= xe_migrate_sanity_kunit  =================
[10:57:38] ============ [SKIPPED] xe_migrate_sanity_kunit =============
[10:57:38] ================== xe_validate_ccs_kunit  ==================
[10:57:38] ============= [SKIPPED] xe_validate_ccs_kunit ==============
[10:57:38] =================== [SKIPPED] xe_migrate ===================
[10:57:38] ================== xe_dma_buf (1 subtest) ==================
[10:57:38] ==================== xe_dma_buf_kunit  =====================
[10:57:38] ================ [SKIPPED] xe_dma_buf_kunit ================
[10:57:38] =================== [SKIPPED] xe_dma_buf ===================
[10:57:38] ================= xe_bo_shrink (1 subtest) =================
[10:57:38] =================== xe_bo_shrink_kunit  ====================
[10:57:38] =============== [SKIPPED] xe_bo_shrink_kunit ===============
[10:57:38] ================== [SKIPPED] xe_bo_shrink ==================
[10:57:38] ==================== xe_bo (2 subtests) ====================
[10:57:38] ================== xe_ccs_migrate_kunit  ===================
[10:57:38] ============== [SKIPPED] xe_ccs_migrate_kunit ==============
[10:57:38] ==================== xe_bo_evict_kunit  ====================
[10:57:38] =============== [SKIPPED] xe_bo_evict_kunit ================
[10:57:38] ===================== [SKIPPED] xe_bo ======================
[10:57:38] ==================== args (13 subtests) ====================
[10:57:38] [PASSED] count_args_test
[10:57:38] [PASSED] call_args_example
[10:57:38] [PASSED] call_args_test
[10:57:38] [PASSED] drop_first_arg_example
[10:57:38] [PASSED] drop_first_arg_test
[10:57:38] [PASSED] first_arg_example
[10:57:38] [PASSED] first_arg_test
[10:57:38] [PASSED] last_arg_example
[10:57:38] [PASSED] last_arg_test
[10:57:38] [PASSED] pick_arg_example
[10:57:38] [PASSED] if_args_example
[10:57:38] [PASSED] if_args_test
[10:57:38] [PASSED] sep_comma_example
[10:57:38] ====================== [PASSED] args =======================
[10:57:38] =================== xe_pci (3 subtests) ====================
[10:57:38] ==================== check_graphics_ip  ====================
[10:57:38] [PASSED] 12.00 Xe_LP
[10:57:38] [PASSED] 12.10 Xe_LP+
[10:57:38] [PASSED] 12.55 Xe_HPG
[10:57:38] [PASSED] 12.60 Xe_HPC
[10:57:38] [PASSED] 12.70 Xe_LPG
[10:57:38] [PASSED] 12.71 Xe_LPG
[10:57:38] [PASSED] 12.74 Xe_LPG+
[10:57:38] [PASSED] 20.01 Xe2_HPG
[10:57:38] [PASSED] 20.02 Xe2_HPG
[10:57:38] [PASSED] 20.04 Xe2_LPG
[10:57:38] [PASSED] 30.00 Xe3_LPG
[10:57:38] [PASSED] 30.01 Xe3_LPG
[10:57:38] [PASSED] 30.03 Xe3_LPG
[10:57:38] [PASSED] 30.04 Xe3_LPG
[10:57:38] [PASSED] 30.05 Xe3_LPG
[10:57:38] [PASSED] 35.11 Xe3p_XPC
[10:57:38] ================ [PASSED] check_graphics_ip ================
[10:57:38] ===================== check_media_ip  ======================
[10:57:38] [PASSED] 12.00 Xe_M
[10:57:38] [PASSED] 12.55 Xe_HPM
[10:57:38] [PASSED] 13.00 Xe_LPM+
[10:57:38] [PASSED] 13.01 Xe2_HPM
[10:57:38] [PASSED] 20.00 Xe2_LPM
[10:57:38] [PASSED] 30.00 Xe3_LPM
[10:57:38] [PASSED] 30.02 Xe3_LPM
[10:57:38] [PASSED] 35.00 Xe3p_LPM
[10:57:38] [PASSED] 35.03 Xe3p_HPM
[10:57:38] ================= [PASSED] check_media_ip ==================
[10:57:38] =================== check_platform_desc  ===================
[10:57:38] [PASSED] 0x9A60 (TIGERLAKE)
[10:57:38] [PASSED] 0x9A68 (TIGERLAKE)
[10:57:38] [PASSED] 0x9A70 (TIGERLAKE)
[10:57:38] [PASSED] 0x9A40 (TIGERLAKE)
[10:57:38] [PASSED] 0x9A49 (TIGERLAKE)
[10:57:38] [PASSED] 0x9A59 (TIGERLAKE)
[10:57:38] [PASSED] 0x9A78 (TIGERLAKE)
[10:57:38] [PASSED] 0x9AC0 (TIGERLAKE)
[10:57:38] [PASSED] 0x9AC9 (TIGERLAKE)
[10:57:38] [PASSED] 0x9AD9 (TIGERLAKE)
[10:57:38] [PASSED] 0x9AF8 (TIGERLAKE)
[10:57:38] [PASSED] 0x4C80 (ROCKETLAKE)
[10:57:38] [PASSED] 0x4C8A (ROCKETLAKE)
[10:57:38] [PASSED] 0x4C8B (ROCKETLAKE)
[10:57:38] [PASSED] 0x4C8C (ROCKETLAKE)
[10:57:38] [PASSED] 0x4C90 (ROCKETLAKE)
[10:57:38] [PASSED] 0x4C9A (ROCKETLAKE)
[10:57:38] [PASSED] 0x4680 (ALDERLAKE_S)
[10:57:38] [PASSED] 0x4682 (ALDERLAKE_S)
[10:57:38] [PASSED] 0x4688 (ALDERLAKE_S)
[10:57:38] [PASSED] 0x468A (ALDERLAKE_S)
[10:57:38] [PASSED] 0x468B (ALDERLAKE_S)
[10:57:38] [PASSED] 0x4690 (ALDERLAKE_S)
[10:57:38] [PASSED] 0x4692 (ALDERLAKE_S)
[10:57:38] [PASSED] 0x4693 (ALDERLAKE_S)
[10:57:38] [PASSED] 0x46A0 (ALDERLAKE_P)
[10:57:38] [PASSED] 0x46A1 (ALDERLAKE_P)
[10:57:38] [PASSED] 0x46A2 (ALDERLAKE_P)
[10:57:38] [PASSED] 0x46A3 (ALDERLAKE_P)
[10:57:38] [PASSED] 0x46A6 (ALDERLAKE_P)
[10:57:38] [PASSED] 0x46A8 (ALDERLAKE_P)
[10:57:38] [PASSED] 0x46AA (ALDERLAKE_P)
[10:57:38] [PASSED] 0x462A (ALDERLAKE_P)
[10:57:38] [PASSED] 0x4626 (ALDERLAKE_P)
[10:57:38] [PASSED] 0x4628 (ALDERLAKE_P)
stty: 'standard input': Inappropriate ioctl for device
[10:57:38] [PASSED] 0x46B0 (ALDERLAKE_P)
[10:57:38] [PASSED] 0x46B1 (ALDERLAKE_P)
[10:57:38] [PASSED] 0x46B2 (ALDERLAKE_P)
[10:57:38] [PASSED] 0x46B3 (ALDERLAKE_P)
[10:57:38] [PASSED] 0x46C0 (ALDERLAKE_P)
[10:57:38] [PASSED] 0x46C1 (ALDERLAKE_P)
[10:57:38] [PASSED] 0x46C2 (ALDERLAKE_P)
[10:57:38] [PASSED] 0x46C3 (ALDERLAKE_P)
[10:57:38] [PASSED] 0x46D0 (ALDERLAKE_N)
[10:57:38] [PASSED] 0x46D1 (ALDERLAKE_N)
[10:57:38] [PASSED] 0x46D2 (ALDERLAKE_N)
[10:57:38] [PASSED] 0x46D3 (ALDERLAKE_N)
[10:57:38] [PASSED] 0x46D4 (ALDERLAKE_N)
[10:57:38] [PASSED] 0xA721 (ALDERLAKE_P)
[10:57:38] [PASSED] 0xA7A1 (ALDERLAKE_P)
[10:57:38] [PASSED] 0xA7A9 (ALDERLAKE_P)
[10:57:38] [PASSED] 0xA7AC (ALDERLAKE_P)
[10:57:38] [PASSED] 0xA7AD (ALDERLAKE_P)
[10:57:38] [PASSED] 0xA720 (ALDERLAKE_P)
[10:57:38] [PASSED] 0xA7A0 (ALDERLAKE_P)
[10:57:38] [PASSED] 0xA7A8 (ALDERLAKE_P)
[10:57:38] [PASSED] 0xA7AA (ALDERLAKE_P)
[10:57:38] [PASSED] 0xA7AB (ALDERLAKE_P)
[10:57:38] [PASSED] 0xA780 (ALDERLAKE_S)
[10:57:38] [PASSED] 0xA781 (ALDERLAKE_S)
[10:57:38] [PASSED] 0xA782 (ALDERLAKE_S)
[10:57:38] [PASSED] 0xA783 (ALDERLAKE_S)
[10:57:38] [PASSED] 0xA788 (ALDERLAKE_S)
[10:57:38] [PASSED] 0xA789 (ALDERLAKE_S)
[10:57:38] [PASSED] 0xA78A (ALDERLAKE_S)
[10:57:38] [PASSED] 0xA78B (ALDERLAKE_S)
[10:57:38] [PASSED] 0x4905 (DG1)
[10:57:38] [PASSED] 0x4906 (DG1)
[10:57:38] [PASSED] 0x4907 (DG1)
[10:57:38] [PASSED] 0x4908 (DG1)
[10:57:38] [PASSED] 0x4909 (DG1)
[10:57:38] [PASSED] 0x56C0 (DG2)
[10:57:38] [PASSED] 0x56C2 (DG2)
[10:57:38] [PASSED] 0x56C1 (DG2)
[10:57:38] [PASSED] 0x7D51 (METEORLAKE)
[10:57:38] [PASSED] 0x7DD1 (METEORLAKE)
[10:57:38] [PASSED] 0x7D41 (METEORLAKE)
[10:57:38] [PASSED] 0x7D67 (METEORLAKE)
[10:57:38] [PASSED] 0xB640 (METEORLAKE)
[10:57:38] [PASSED] 0x56A0 (DG2)
[10:57:38] [PASSED] 0x56A1 (DG2)
[10:57:38] [PASSED] 0x56A2 (DG2)
[10:57:38] [PASSED] 0x56BE (DG2)
[10:57:38] [PASSED] 0x56BF (DG2)
[10:57:38] [PASSED] 0x5690 (DG2)
[10:57:38] [PASSED] 0x5691 (DG2)
[10:57:38] [PASSED] 0x5692 (DG2)
[10:57:38] [PASSED] 0x56A5 (DG2)
[10:57:38] [PASSED] 0x56A6 (DG2)
[10:57:38] [PASSED] 0x56B0 (DG2)
[10:57:38] [PASSED] 0x56B1 (DG2)
[10:57:38] [PASSED] 0x56BA (DG2)
[10:57:38] [PASSED] 0x56BB (DG2)
[10:57:38] [PASSED] 0x56BC (DG2)
[10:57:38] [PASSED] 0x56BD (DG2)
[10:57:38] [PASSED] 0x5693 (DG2)
[10:57:38] [PASSED] 0x5694 (DG2)
[10:57:38] [PASSED] 0x5695 (DG2)
[10:57:38] [PASSED] 0x56A3 (DG2)
[10:57:38] [PASSED] 0x56A4 (DG2)
[10:57:38] [PASSED] 0x56B2 (DG2)
[10:57:38] [PASSED] 0x56B3 (DG2)
[10:57:38] [PASSED] 0x5696 (DG2)
[10:57:38] [PASSED] 0x5697 (DG2)
[10:57:38] [PASSED] 0xB69 (PVC)
[10:57:38] [PASSED] 0xB6E (PVC)
[10:57:38] [PASSED] 0xBD4 (PVC)
[10:57:38] [PASSED] 0xBD5 (PVC)
[10:57:38] [PASSED] 0xBD6 (PVC)
[10:57:38] [PASSED] 0xBD7 (PVC)
[10:57:38] [PASSED] 0xBD8 (PVC)
[10:57:38] [PASSED] 0xBD9 (PVC)
[10:57:38] [PASSED] 0xBDA (PVC)
[10:57:38] [PASSED] 0xBDB (PVC)
[10:57:38] [PASSED] 0xBE0 (PVC)
[10:57:38] [PASSED] 0xBE1 (PVC)
[10:57:38] [PASSED] 0xBE5 (PVC)
[10:57:38] [PASSED] 0x7D40 (METEORLAKE)
[10:57:38] [PASSED] 0x7D45 (METEORLAKE)
[10:57:38] [PASSED] 0x7D55 (METEORLAKE)
[10:57:38] [PASSED] 0x7D60 (METEORLAKE)
[10:57:38] [PASSED] 0x7DD5 (METEORLAKE)
[10:57:38] [PASSED] 0x6420 (LUNARLAKE)
[10:57:38] [PASSED] 0x64A0 (LUNARLAKE)
[10:57:38] [PASSED] 0x64B0 (LUNARLAKE)
[10:57:38] [PASSED] 0xE202 (BATTLEMAGE)
[10:57:38] [PASSED] 0xE209 (BATTLEMAGE)
[10:57:38] [PASSED] 0xE20B (BATTLEMAGE)
[10:57:38] [PASSED] 0xE20C (BATTLEMAGE)
[10:57:38] [PASSED] 0xE20D (BATTLEMAGE)
[10:57:38] [PASSED] 0xE210 (BATTLEMAGE)
[10:57:38] [PASSED] 0xE211 (BATTLEMAGE)
[10:57:38] [PASSED] 0xE212 (BATTLEMAGE)
[10:57:38] [PASSED] 0xE216 (BATTLEMAGE)
[10:57:38] [PASSED] 0xE220 (BATTLEMAGE)
[10:57:38] [PASSED] 0xE221 (BATTLEMAGE)
[10:57:38] [PASSED] 0xE222 (BATTLEMAGE)
[10:57:38] [PASSED] 0xE223 (BATTLEMAGE)
[10:57:38] [PASSED] 0xB080 (PANTHERLAKE)
[10:57:38] [PASSED] 0xB081 (PANTHERLAKE)
[10:57:38] [PASSED] 0xB082 (PANTHERLAKE)
[10:57:38] [PASSED] 0xB083 (PANTHERLAKE)
[10:57:38] [PASSED] 0xB084 (PANTHERLAKE)
[10:57:38] [PASSED] 0xB085 (PANTHERLAKE)
[10:57:38] [PASSED] 0xB086 (PANTHERLAKE)
[10:57:38] [PASSED] 0xB087 (PANTHERLAKE)
[10:57:38] [PASSED] 0xB08F (PANTHERLAKE)
[10:57:38] [PASSED] 0xB090 (PANTHERLAKE)
[10:57:38] [PASSED] 0xB0A0 (PANTHERLAKE)
[10:57:38] [PASSED] 0xB0B0 (PANTHERLAKE)
[10:57:38] [PASSED] 0xFD80 (PANTHERLAKE)
[10:57:38] [PASSED] 0xFD81 (PANTHERLAKE)
[10:57:38] [PASSED] 0xD740 (NOVALAKE_S)
[10:57:38] [PASSED] 0xD741 (NOVALAKE_S)
[10:57:38] [PASSED] 0xD742 (NOVALAKE_S)
[10:57:38] [PASSED] 0xD743 (NOVALAKE_S)
[10:57:38] [PASSED] 0xD744 (NOVALAKE_S)
[10:57:38] [PASSED] 0xD745 (NOVALAKE_S)
[10:57:38] [PASSED] 0x674C (CRESCENTISLAND)
[10:57:38] =============== [PASSED] check_platform_desc ===============
[10:57:38] ===================== [PASSED] xe_pci ======================
[10:57:38] =================== xe_rtp (2 subtests) ====================
[10:57:38] =============== xe_rtp_process_to_sr_tests  ================
[10:57:38] [PASSED] coalesce-same-reg
[10:57:38] [PASSED] no-match-no-add
[10:57:38] [PASSED] match-or
[10:57:38] [PASSED] match-or-xfail
[10:57:38] [PASSED] no-match-no-add-multiple-rules
[10:57:38] [PASSED] two-regs-two-entries
[10:57:38] [PASSED] clr-one-set-other
[10:57:38] [PASSED] set-field
[10:57:38] [PASSED] conflict-duplicate
[10:57:38] [PASSED] conflict-not-disjoint
[10:57:38] [PASSED] conflict-reg-type
[10:57:38] =========== [PASSED] xe_rtp_process_to_sr_tests ============
[10:57:38] ================== xe_rtp_process_tests  ===================
[10:57:38] [PASSED] active1
[10:57:38] [PASSED] active2
[10:57:38] [PASSED] active-inactive
[10:57:38] [PASSED] inactive-active
[10:57:38] [PASSED] inactive-1st_or_active-inactive
[10:57:38] [PASSED] inactive-2nd_or_active-inactive
[10:57:38] [PASSED] inactive-last_or_active-inactive
[10:57:38] [PASSED] inactive-no_or_active-inactive
[10:57:38] ============== [PASSED] xe_rtp_process_tests ===============
[10:57:38] ===================== [PASSED] xe_rtp ======================
[10:57:38] ==================== xe_wa (1 subtest) =====================
[10:57:38] ======================== xe_wa_gt  =========================
[10:57:38] [PASSED] TIGERLAKE B0
[10:57:38] [PASSED] DG1 A0
[10:57:38] [PASSED] DG1 B0
[10:57:38] [PASSED] ALDERLAKE_S A0
[10:57:38] [PASSED] ALDERLAKE_S B0
[10:57:38] [PASSED] ALDERLAKE_S C0
[10:57:38] [PASSED] ALDERLAKE_S D0
[10:57:38] [PASSED] ALDERLAKE_P A0
[10:57:38] [PASSED] ALDERLAKE_P B0
[10:57:38] [PASSED] ALDERLAKE_P C0
[10:57:38] [PASSED] ALDERLAKE_S RPLS D0
[10:57:38] [PASSED] ALDERLAKE_P RPLU E0
[10:57:38] [PASSED] DG2 G10 C0
[10:57:38] [PASSED] DG2 G11 B1
[10:57:38] [PASSED] DG2 G12 A1
[10:57:38] [PASSED] METEORLAKE 12.70(Xe_LPG) A0 13.00(Xe_LPM+) A0
[10:57:38] [PASSED] METEORLAKE 12.71(Xe_LPG) A0 13.00(Xe_LPM+) A0
[10:57:38] [PASSED] METEORLAKE 12.74(Xe_LPG+) A0 13.00(Xe_LPM+) A0
[10:57:38] [PASSED] LUNARLAKE 20.04(Xe2_LPG) A0 20.00(Xe2_LPM) A0
[10:57:38] [PASSED] LUNARLAKE 20.04(Xe2_LPG) B0 20.00(Xe2_LPM) A0
[10:57:38] [PASSED] BATTLEMAGE 20.01(Xe2_HPG) A0 13.01(Xe2_HPM) A1
[10:57:38] [PASSED] PANTHERLAKE 30.00(Xe3_LPG) A0 30.00(Xe3_LPM) A0
[10:57:38] ==================== [PASSED] xe_wa_gt =====================
[10:57:38] ====================== [PASSED] xe_wa ======================
[10:57:38] ============================================================
[10:57:38] Testing complete. Ran 512 tests: passed: 494, skipped: 18
[10:57:38] Elapsed time: 36.125s total, 4.189s configuring, 31.419s building, 0.465s running

+ /kernel/tools/testing/kunit/kunit.py run --kunitconfig /kernel/drivers/gpu/drm/tests/.kunitconfig
[10:57:38] Configuring KUnit Kernel ...
Regenerating .config ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
[10:57:40] Building KUnit Kernel ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
Building with:
$ make all compile_commands.json scripts_gdb ARCH=um O=.kunit --jobs=48
[10:58:05] Starting KUnit Kernel (1/1)...
[10:58:05] ============================================================
Running tests with:
$ .kunit/linux kunit.enable=1 mem=1G console=tty kunit_shutdown=halt
[10:58:06] ============ drm_test_pick_cmdline (2 subtests) ============
[10:58:06] [PASSED] drm_test_pick_cmdline_res_1920_1080_60
[10:58:06] =============== drm_test_pick_cmdline_named  ===============
[10:58:06] [PASSED] NTSC
[10:58:06] [PASSED] NTSC-J
[10:58:06] [PASSED] PAL
[10:58:06] [PASSED] PAL-M
[10:58:06] =========== [PASSED] drm_test_pick_cmdline_named ===========
[10:58:06] ============== [PASSED] drm_test_pick_cmdline ==============
[10:58:06] == drm_test_atomic_get_connector_for_encoder (1 subtest) ===
[10:58:06] [PASSED] drm_test_drm_atomic_get_connector_for_encoder
[10:58:06] ==== [PASSED] drm_test_atomic_get_connector_for_encoder ====
[10:58:06] =========== drm_validate_clone_mode (2 subtests) ===========
[10:58:06] ============== drm_test_check_in_clone_mode  ===============
[10:58:06] [PASSED] in_clone_mode
[10:58:06] [PASSED] not_in_clone_mode
[10:58:06] ========== [PASSED] drm_test_check_in_clone_mode ===========
[10:58:06] =============== drm_test_check_valid_clones  ===============
[10:58:06] [PASSED] not_in_clone_mode
[10:58:06] [PASSED] valid_clone
[10:58:06] [PASSED] invalid_clone
[10:58:06] =========== [PASSED] drm_test_check_valid_clones ===========
[10:58:06] ============= [PASSED] drm_validate_clone_mode =============
[10:58:06] ============= drm_validate_modeset (1 subtest) =============
[10:58:06] [PASSED] drm_test_check_connector_changed_modeset
[10:58:06] ============== [PASSED] drm_validate_modeset ===============
[10:58:06] ====== drm_test_bridge_get_current_state (2 subtests) ======
[10:58:06] [PASSED] drm_test_drm_bridge_get_current_state_atomic
[10:58:06] [PASSED] drm_test_drm_bridge_get_current_state_legacy
[10:58:06] ======== [PASSED] drm_test_bridge_get_current_state ========
[10:58:06] ====== drm_test_bridge_helper_reset_crtc (3 subtests) ======
[10:58:06] [PASSED] drm_test_drm_bridge_helper_reset_crtc_atomic
[10:58:06] [PASSED] drm_test_drm_bridge_helper_reset_crtc_atomic_disabled
[10:58:06] [PASSED] drm_test_drm_bridge_helper_reset_crtc_legacy
[10:58:06] ======== [PASSED] drm_test_bridge_helper_reset_crtc ========
[10:58:06] ============== drm_bridge_alloc (2 subtests) ===============
[10:58:06] [PASSED] drm_test_drm_bridge_alloc_basic
[10:58:06] [PASSED] drm_test_drm_bridge_alloc_get_put
[10:58:06] ================ [PASSED] drm_bridge_alloc =================
[10:58:06] ================== drm_buddy (8 subtests) ==================
[10:58:06] [PASSED] drm_test_buddy_alloc_limit
[10:58:06] [PASSED] drm_test_buddy_alloc_optimistic
[10:58:06] [PASSED] drm_test_buddy_alloc_pessimistic
[10:58:06] [PASSED] drm_test_buddy_alloc_pathological
[10:58:06] [PASSED] drm_test_buddy_alloc_contiguous
[10:58:06] [PASSED] drm_test_buddy_alloc_clear
[10:58:06] [PASSED] drm_test_buddy_alloc_range_bias
[10:58:06] [PASSED] drm_test_buddy_fragmentation_performance
[10:58:06] ==================== [PASSED] drm_buddy ====================
[10:58:06] ============= drm_cmdline_parser (40 subtests) =============
[10:58:06] [PASSED] drm_test_cmdline_force_d_only
[10:58:06] [PASSED] drm_test_cmdline_force_D_only_dvi
[10:58:06] [PASSED] drm_test_cmdline_force_D_only_hdmi
[10:58:06] [PASSED] drm_test_cmdline_force_D_only_not_digital
[10:58:06] [PASSED] drm_test_cmdline_force_e_only
[10:58:06] [PASSED] drm_test_cmdline_res
[10:58:06] [PASSED] drm_test_cmdline_res_vesa
[10:58:06] [PASSED] drm_test_cmdline_res_vesa_rblank
[10:58:06] [PASSED] drm_test_cmdline_res_rblank
[10:58:06] [PASSED] drm_test_cmdline_res_bpp
[10:58:06] [PASSED] drm_test_cmdline_res_refresh
[10:58:06] [PASSED] drm_test_cmdline_res_bpp_refresh
[10:58:06] [PASSED] drm_test_cmdline_res_bpp_refresh_interlaced
[10:58:06] [PASSED] drm_test_cmdline_res_bpp_refresh_margins
[10:58:06] [PASSED] drm_test_cmdline_res_bpp_refresh_force_off
[10:58:06] [PASSED] drm_test_cmdline_res_bpp_refresh_force_on
[10:58:06] [PASSED] drm_test_cmdline_res_bpp_refresh_force_on_analog
[10:58:06] [PASSED] drm_test_cmdline_res_bpp_refresh_force_on_digital
[10:58:06] [PASSED] drm_test_cmdline_res_bpp_refresh_interlaced_margins_force_on
[10:58:06] [PASSED] drm_test_cmdline_res_margins_force_on
[10:58:06] [PASSED] drm_test_cmdline_res_vesa_margins
[10:58:06] [PASSED] drm_test_cmdline_name
[10:58:06] [PASSED] drm_test_cmdline_name_bpp
[10:58:06] [PASSED] drm_test_cmdline_name_option
[10:58:06] [PASSED] drm_test_cmdline_name_bpp_option
[10:58:06] [PASSED] drm_test_cmdline_rotate_0
[10:58:06] [PASSED] drm_test_cmdline_rotate_90
[10:58:06] [PASSED] drm_test_cmdline_rotate_180
[10:58:06] [PASSED] drm_test_cmdline_rotate_270
[10:58:06] [PASSED] drm_test_cmdline_hmirror
[10:58:06] [PASSED] drm_test_cmdline_vmirror
[10:58:06] [PASSED] drm_test_cmdline_margin_options
[10:58:06] [PASSED] drm_test_cmdline_multiple_options
[10:58:06] [PASSED] drm_test_cmdline_bpp_extra_and_option
[10:58:06] [PASSED] drm_test_cmdline_extra_and_option
[10:58:06] [PASSED] drm_test_cmdline_freestanding_options
[10:58:06] [PASSED] drm_test_cmdline_freestanding_force_e_and_options
[10:58:06] [PASSED] drm_test_cmdline_panel_orientation
[10:58:06] ================ drm_test_cmdline_invalid  =================
[10:58:06] [PASSED] margin_only
[10:58:06] [PASSED] interlace_only
[10:58:06] [PASSED] res_missing_x
[10:58:06] [PASSED] res_missing_y
[10:58:06] [PASSED] res_bad_y
[10:58:06] [PASSED] res_missing_y_bpp
[10:58:06] [PASSED] res_bad_bpp
[10:58:06] [PASSED] res_bad_refresh
[10:58:06] [PASSED] res_bpp_refresh_force_on_off
[10:58:06] [PASSED] res_invalid_mode
[10:58:06] [PASSED] res_bpp_wrong_place_mode
[10:58:06] [PASSED] name_bpp_refresh
[10:58:06] [PASSED] name_refresh
[10:58:06] [PASSED] name_refresh_wrong_mode
[10:58:06] [PASSED] name_refresh_invalid_mode
[10:58:06] [PASSED] rotate_multiple
[10:58:06] [PASSED] rotate_invalid_val
[10:58:06] [PASSED] rotate_truncated
[10:58:06] [PASSED] invalid_option
[10:58:06] [PASSED] invalid_tv_option
[10:58:06] [PASSED] truncated_tv_option
[10:58:06] ============ [PASSED] drm_test_cmdline_invalid =============
[10:58:06] =============== drm_test_cmdline_tv_options  ===============
[10:58:06] [PASSED] NTSC
[10:58:06] [PASSED] NTSC_443
[10:58:06] [PASSED] NTSC_J
[10:58:06] [PASSED] PAL
[10:58:06] [PASSED] PAL_M
[10:58:06] [PASSED] PAL_N
[10:58:06] [PASSED] SECAM
[10:58:06] [PASSED] MONO_525
[10:58:06] [PASSED] MONO_625
[10:58:06] =========== [PASSED] drm_test_cmdline_tv_options ===========
[10:58:06] =============== [PASSED] drm_cmdline_parser ================
[10:58:06] ========== drmm_connector_hdmi_init (20 subtests) ==========
[10:58:06] [PASSED] drm_test_connector_hdmi_init_valid
[10:58:06] [PASSED] drm_test_connector_hdmi_init_bpc_8
[10:58:06] [PASSED] drm_test_connector_hdmi_init_bpc_10
[10:58:06] [PASSED] drm_test_connector_hdmi_init_bpc_12
[10:58:06] [PASSED] drm_test_connector_hdmi_init_bpc_invalid
[10:58:06] [PASSED] drm_test_connector_hdmi_init_bpc_null
[10:58:06] [PASSED] drm_test_connector_hdmi_init_formats_empty
[10:58:06] [PASSED] drm_test_connector_hdmi_init_formats_no_rgb
[10:58:06] === drm_test_connector_hdmi_init_formats_yuv420_allowed  ===
[10:58:06] [PASSED] supported_formats=0x9 yuv420_allowed=1
[10:58:06] [PASSED] supported_formats=0x9 yuv420_allowed=0
[10:58:06] [PASSED] supported_formats=0x3 yuv420_allowed=1
[10:58:06] [PASSED] supported_formats=0x3 yuv420_allowed=0
[10:58:06] === [PASSED] drm_test_connector_hdmi_init_formats_yuv420_allowed ===
[10:58:06] [PASSED] drm_test_connector_hdmi_init_null_ddc
[10:58:06] [PASSED] drm_test_connector_hdmi_init_null_product
[10:58:06] [PASSED] drm_test_connector_hdmi_init_null_vendor
[10:58:06] [PASSED] drm_test_connector_hdmi_init_product_length_exact
[10:58:06] [PASSED] drm_test_connector_hdmi_init_product_length_too_long
[10:58:06] [PASSED] drm_test_connector_hdmi_init_product_valid
[10:58:06] [PASSED] drm_test_connector_hdmi_init_vendor_length_exact
[10:58:06] [PASSED] drm_test_connector_hdmi_init_vendor_length_too_long
[10:58:06] [PASSED] drm_test_connector_hdmi_init_vendor_valid
[10:58:06] ========= drm_test_connector_hdmi_init_type_valid  =========
[10:58:06] [PASSED] HDMI-A
[10:58:06] [PASSED] HDMI-B
[10:58:06] ===== [PASSED] drm_test_connector_hdmi_init_type_valid =====
[10:58:06] ======== drm_test_connector_hdmi_init_type_invalid  ========
[10:58:06] [PASSED] Unknown
[10:58:06] [PASSED] VGA
[10:58:06] [PASSED] DVI-I
[10:58:06] [PASSED] DVI-D
[10:58:06] [PASSED] DVI-A
[10:58:06] [PASSED] Composite
[10:58:06] [PASSED] SVIDEO
[10:58:06] [PASSED] LVDS
[10:58:06] [PASSED] Component
[10:58:06] [PASSED] DIN
[10:58:06] [PASSED] DP
[10:58:06] [PASSED] TV
[10:58:06] [PASSED] eDP
[10:58:06] [PASSED] Virtual
[10:58:06] [PASSED] DSI
[10:58:06] [PASSED] DPI
[10:58:06] [PASSED] Writeback
[10:58:06] [PASSED] SPI
[10:58:06] [PASSED] USB
[10:58:06] ==== [PASSED] drm_test_connector_hdmi_init_type_invalid ====
[10:58:06] ============ [PASSED] drmm_connector_hdmi_init =============
[10:58:06] ============= drmm_connector_init (3 subtests) =============
[10:58:06] [PASSED] drm_test_drmm_connector_init
[10:58:06] [PASSED] drm_test_drmm_connector_init_null_ddc
[10:58:06] ========= drm_test_drmm_connector_init_type_valid  =========
[10:58:06] [PASSED] Unknown
[10:58:06] [PASSED] VGA
[10:58:06] [PASSED] DVI-I
[10:58:06] [PASSED] DVI-D
[10:58:06] [PASSED] DVI-A
[10:58:06] [PASSED] Composite
[10:58:06] [PASSED] SVIDEO
[10:58:06] [PASSED] LVDS
[10:58:06] [PASSED] Component
[10:58:06] [PASSED] DIN
[10:58:06] [PASSED] DP
[10:58:06] [PASSED] HDMI-A
[10:58:06] [PASSED] HDMI-B
[10:58:06] [PASSED] TV
[10:58:06] [PASSED] eDP
[10:58:06] [PASSED] Virtual
[10:58:06] [PASSED] DSI
[10:58:06] [PASSED] DPI
[10:58:06] [PASSED] Writeback
[10:58:06] [PASSED] SPI
[10:58:06] [PASSED] USB
[10:58:06] ===== [PASSED] drm_test_drmm_connector_init_type_valid =====
[10:58:06] =============== [PASSED] drmm_connector_init ===============
[10:58:06] ========= drm_connector_dynamic_init (6 subtests) ==========
[10:58:06] [PASSED] drm_test_drm_connector_dynamic_init
[10:58:06] [PASSED] drm_test_drm_connector_dynamic_init_null_ddc
[10:58:06] [PASSED] drm_test_drm_connector_dynamic_init_not_added
[10:58:06] [PASSED] drm_test_drm_connector_dynamic_init_properties
[10:58:06] ===== drm_test_drm_connector_dynamic_init_type_valid  ======
[10:58:06] [PASSED] Unknown
[10:58:06] [PASSED] VGA
[10:58:06] [PASSED] DVI-I
[10:58:06] [PASSED] DVI-D
[10:58:06] [PASSED] DVI-A
[10:58:06] [PASSED] Composite
[10:58:06] [PASSED] SVIDEO
[10:58:06] [PASSED] LVDS
[10:58:06] [PASSED] Component
[10:58:06] [PASSED] DIN
[10:58:06] [PASSED] DP
[10:58:06] [PASSED] HDMI-A
[10:58:06] [PASSED] HDMI-B
[10:58:06] [PASSED] TV
[10:58:06] [PASSED] eDP
[10:58:06] [PASSED] Virtual
[10:58:06] [PASSED] DSI
[10:58:06] [PASSED] DPI
[10:58:06] [PASSED] Writeback
[10:58:06] [PASSED] SPI
[10:58:06] [PASSED] USB
[10:58:06] = [PASSED] drm_test_drm_connector_dynamic_init_type_valid ==
[10:58:06] ======== drm_test_drm_connector_dynamic_init_name  =========
[10:58:06] [PASSED] Unknown
[10:58:06] [PASSED] VGA
[10:58:06] [PASSED] DVI-I
[10:58:06] [PASSED] DVI-D
[10:58:06] [PASSED] DVI-A
[10:58:06] [PASSED] Composite
[10:58:06] [PASSED] SVIDEO
[10:58:06] [PASSED] LVDS
[10:58:06] [PASSED] Component
[10:58:06] [PASSED] DIN
[10:58:06] [PASSED] DP
[10:58:06] [PASSED] HDMI-A
[10:58:06] [PASSED] HDMI-B
[10:58:06] [PASSED] TV
[10:58:06] [PASSED] eDP
[10:58:06] [PASSED] Virtual
[10:58:06] [PASSED] DSI
[10:58:06] [PASSED] DPI
[10:58:06] [PASSED] Writeback
[10:58:06] [PASSED] SPI
[10:58:06] [PASSED] USB
[10:58:06] ==== [PASSED] drm_test_drm_connector_dynamic_init_name =====
[10:58:06] =========== [PASSED] drm_connector_dynamic_init ============
[10:58:06] ==== drm_connector_dynamic_register_early (4 subtests) =====
[10:58:06] [PASSED] drm_test_drm_connector_dynamic_register_early_on_list
[10:58:06] [PASSED] drm_test_drm_connector_dynamic_register_early_defer
[10:58:06] [PASSED] drm_test_drm_connector_dynamic_register_early_no_init
[10:58:06] [PASSED] drm_test_drm_connector_dynamic_register_early_no_mode_object
[10:58:06] ====== [PASSED] drm_connector_dynamic_register_early =======
[10:58:06] ======= drm_connector_dynamic_register (7 subtests) ========
[10:58:06] [PASSED] drm_test_drm_connector_dynamic_register_on_list
[10:58:06] [PASSED] drm_test_drm_connector_dynamic_register_no_defer
[10:58:06] [PASSED] drm_test_drm_connector_dynamic_register_no_init
[10:58:06] [PASSED] drm_test_drm_connector_dynamic_register_mode_object
[10:58:06] [PASSED] drm_test_drm_connector_dynamic_register_sysfs
[10:58:06] [PASSED] drm_test_drm_connector_dynamic_register_sysfs_name
[10:58:06] [PASSED] drm_test_drm_connector_dynamic_register_debugfs
[10:58:06] ========= [PASSED] drm_connector_dynamic_register ==========
[10:58:06] = drm_connector_attach_broadcast_rgb_property (2 subtests) =
[10:58:06] [PASSED] drm_test_drm_connector_attach_broadcast_rgb_property
[10:58:06] [PASSED] drm_test_drm_connector_attach_broadcast_rgb_property_hdmi_connector
[10:58:06] === [PASSED] drm_connector_attach_broadcast_rgb_property ===
[10:58:06] ========== drm_get_tv_mode_from_name (2 subtests) ==========
[10:58:06] ========== drm_test_get_tv_mode_from_name_valid  ===========
[10:58:06] [PASSED] NTSC
[10:58:06] [PASSED] NTSC-443
[10:58:06] [PASSED] NTSC-J
[10:58:06] [PASSED] PAL
[10:58:06] [PASSED] PAL-M
[10:58:06] [PASSED] PAL-N
[10:58:06] [PASSED] SECAM
[10:58:06] [PASSED] Mono
[10:58:06] ====== [PASSED] drm_test_get_tv_mode_from_name_valid =======
[10:58:06] [PASSED] drm_test_get_tv_mode_from_name_truncated
[10:58:06] ============ [PASSED] drm_get_tv_mode_from_name ============
[10:58:06] = drm_test_connector_hdmi_compute_mode_clock (12 subtests) =
[10:58:06] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb
[10:58:06] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_10bpc
[10:58:06] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_10bpc_vic_1
[10:58:06] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_12bpc
[10:58:06] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_12bpc_vic_1
[10:58:06] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_double
[10:58:06] = drm_test_connector_hdmi_compute_mode_clock_yuv420_valid  =
[10:58:06] [PASSED] VIC 96
[10:58:06] [PASSED] VIC 97
[10:58:06] [PASSED] VIC 101
[10:58:06] [PASSED] VIC 102
[10:58:06] [PASSED] VIC 106
[10:58:06] [PASSED] VIC 107
[10:58:06] === [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv420_valid ===
[10:58:06] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv420_10_bpc
[10:58:06] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv420_12_bpc
[10:58:06] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv422_8_bpc
[10:58:06] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv422_10_bpc
[10:58:06] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv422_12_bpc
[10:58:06] === [PASSED] drm_test_connector_hdmi_compute_mode_clock ====
[10:58:06] == drm_hdmi_connector_get_broadcast_rgb_name (2 subtests) ==
[10:58:06] === drm_test_drm_hdmi_connector_get_broadcast_rgb_name  ====
[10:58:06] [PASSED] Automatic
[10:58:06] [PASSED] Full
[10:58:06] [PASSED] Limited 16:235
[10:58:06] === [PASSED] drm_test_drm_hdmi_connector_get_broadcast_rgb_name ===
[10:58:06] [PASSED] drm_test_drm_hdmi_connector_get_broadcast_rgb_name_invalid
[10:58:06] ==== [PASSED] drm_hdmi_connector_get_broadcast_rgb_name ====
[10:58:06] == drm_hdmi_connector_get_output_format_name (2 subtests) ==
[10:58:06] === drm_test_drm_hdmi_connector_get_output_format_name  ====
[10:58:06] [PASSED] RGB
[10:58:06] [PASSED] YUV 4:2:0
[10:58:06] [PASSED] YUV 4:2:2
[10:58:06] [PASSED] YUV 4:4:4
[10:58:06] === [PASSED] drm_test_drm_hdmi_connector_get_output_format_name ===
[10:58:06] [PASSED] drm_test_drm_hdmi_connector_get_output_format_name_invalid
[10:58:06] ==== [PASSED] drm_hdmi_connector_get_output_format_name ====
[10:58:06] ============= drm_damage_helper (21 subtests) ==============
[10:58:06] [PASSED] drm_test_damage_iter_no_damage
[10:58:06] [PASSED] drm_test_damage_iter_no_damage_fractional_src
[10:58:06] [PASSED] drm_test_damage_iter_no_damage_src_moved
[10:58:06] [PASSED] drm_test_damage_iter_no_damage_fractional_src_moved
[10:58:06] [PASSED] drm_test_damage_iter_no_damage_not_visible
[10:58:06] [PASSED] drm_test_damage_iter_no_damage_no_crtc
[10:58:06] [PASSED] drm_test_damage_iter_no_damage_no_fb
[10:58:06] [PASSED] drm_test_damage_iter_simple_damage
[10:58:06] [PASSED] drm_test_damage_iter_single_damage
[10:58:06] [PASSED] drm_test_damage_iter_single_damage_intersect_src
[10:58:06] [PASSED] drm_test_damage_iter_single_damage_outside_src
[10:58:06] [PASSED] drm_test_damage_iter_single_damage_fractional_src
[10:58:06] [PASSED] drm_test_damage_iter_single_damage_intersect_fractional_src
[10:58:06] [PASSED] drm_test_damage_iter_single_damage_outside_fractional_src
[10:58:06] [PASSED] drm_test_damage_iter_single_damage_src_moved
[10:58:06] [PASSED] drm_test_damage_iter_single_damage_fractional_src_moved
[10:58:06] [PASSED] drm_test_damage_iter_damage
[10:58:06] [PASSED] drm_test_damage_iter_damage_one_intersect
[10:58:06] [PASSED] drm_test_damage_iter_damage_one_outside
[10:58:06] [PASSED] drm_test_damage_iter_damage_src_moved
[10:58:06] [PASSED] drm_test_damage_iter_damage_not_visible
[10:58:06] ================ [PASSED] drm_damage_helper ================
[10:58:06] ============== drm_dp_mst_helper (3 subtests) ==============
[10:58:06] ============== drm_test_dp_mst_calc_pbn_mode  ==============
[10:58:06] [PASSED] Clock 154000 BPP 30 DSC disabled
[10:58:06] [PASSED] Clock 234000 BPP 30 DSC disabled
[10:58:06] [PASSED] Clock 297000 BPP 24 DSC disabled
[10:58:06] [PASSED] Clock 332880 BPP 24 DSC enabled
[10:58:06] [PASSED] Clock 324540 BPP 24 DSC enabled
[10:58:06] ========== [PASSED] drm_test_dp_mst_calc_pbn_mode ==========
[10:58:06] ============== drm_test_dp_mst_calc_pbn_div  ===============
[10:58:06] [PASSED] Link rate 2000000 lane count 4
[10:58:06] [PASSED] Link rate 2000000 lane count 2
[10:58:06] [PASSED] Link rate 2000000 lane count 1
[10:58:06] [PASSED] Link rate 1350000 lane count 4
[10:58:06] [PASSED] Link rate 1350000 lane count 2
[10:58:06] [PASSED] Link rate 1350000 lane count 1
[10:58:06] [PASSED] Link rate 1000000 lane count 4
[10:58:06] [PASSED] Link rate 1000000 lane count 2
[10:58:06] [PASSED] Link rate 1000000 lane count 1
[10:58:06] [PASSED] Link rate 810000 lane count 4
[10:58:06] [PASSED] Link rate 810000 lane count 2
[10:58:06] [PASSED] Link rate 810000 lane count 1
[10:58:06] [PASSED] Link rate 540000 lane count 4
[10:58:06] [PASSED] Link rate 540000 lane count 2
[10:58:06] [PASSED] Link rate 540000 lane count 1
[10:58:06] [PASSED] Link rate 270000 lane count 4
[10:58:06] [PASSED] Link rate 270000 lane count 2
[10:58:06] [PASSED] Link rate 270000 lane count 1
[10:58:06] [PASSED] Link rate 162000 lane count 4
[10:58:06] [PASSED] Link rate 162000 lane count 2
[10:58:06] [PASSED] Link rate 162000 lane count 1
[10:58:06] ========== [PASSED] drm_test_dp_mst_calc_pbn_div ===========
[10:58:06] ========= drm_test_dp_mst_sideband_msg_req_decode  =========
[10:58:06] [PASSED] DP_ENUM_PATH_RESOURCES with port number
[10:58:06] [PASSED] DP_POWER_UP_PHY with port number
[10:58:06] [PASSED] DP_POWER_DOWN_PHY with port number
[10:58:06] [PASSED] DP_ALLOCATE_PAYLOAD with SDP stream sinks
[10:58:06] [PASSED] DP_ALLOCATE_PAYLOAD with port number
[10:58:06] [PASSED] DP_ALLOCATE_PAYLOAD with VCPI
[10:58:06] [PASSED] DP_ALLOCATE_PAYLOAD with PBN
[10:58:06] [PASSED] DP_QUERY_PAYLOAD with port number
[10:58:06] [PASSED] DP_QUERY_PAYLOAD with VCPI
[10:58:06] [PASSED] DP_REMOTE_DPCD_READ with port number
[10:58:06] [PASSED] DP_REMOTE_DPCD_READ with DPCD address
[10:58:06] [PASSED] DP_REMOTE_DPCD_READ with max number of bytes
[10:58:06] [PASSED] DP_REMOTE_DPCD_WRITE with port number
[10:58:06] [PASSED] DP_REMOTE_DPCD_WRITE with DPCD address
[10:58:06] [PASSED] DP_REMOTE_DPCD_WRITE with data array
[10:58:06] [PASSED] DP_REMOTE_I2C_READ with port number
[10:58:06] [PASSED] DP_REMOTE_I2C_READ with I2C device ID
[10:58:06] [PASSED] DP_REMOTE_I2C_READ with transactions array
[10:58:06] [PASSED] DP_REMOTE_I2C_WRITE with port number
[10:58:06] [PASSED] DP_REMOTE_I2C_WRITE with I2C device ID
[10:58:06] [PASSED] DP_REMOTE_I2C_WRITE with data array
[10:58:06] [PASSED] DP_QUERY_STREAM_ENC_STATUS with stream ID
[10:58:06] [PASSED] DP_QUERY_STREAM_ENC_STATUS with client ID
[10:58:06] [PASSED] DP_QUERY_STREAM_ENC_STATUS with stream event
[10:58:06] [PASSED] DP_QUERY_STREAM_ENC_STATUS with valid stream event
[10:58:06] [PASSED] DP_QUERY_STREAM_ENC_STATUS with stream behavior
[10:58:06] [PASSED] DP_QUERY_STREAM_ENC_STATUS with a valid stream behavior
[10:58:06] ===== [PASSED] drm_test_dp_mst_sideband_msg_req_decode =====
[10:58:06] ================ [PASSED] drm_dp_mst_helper ================
[10:58:06] ================== drm_exec (7 subtests) ===================
[10:58:06] [PASSED] sanitycheck
[10:58:06] [PASSED] test_lock
[10:58:06] [PASSED] test_lock_unlock
[10:58:06] [PASSED] test_duplicates
[10:58:06] [PASSED] test_prepare
[10:58:06] [PASSED] test_prepare_array
[10:58:06] [PASSED] test_multiple_loops
[10:58:06] ==================== [PASSED] drm_exec =====================
[10:58:06] =========== drm_format_helper_test (17 subtests) ===========
[10:58:06] ============== drm_test_fb_xrgb8888_to_gray8  ==============
[10:58:06] [PASSED] single_pixel_source_buffer
[10:58:06] [PASSED] single_pixel_clip_rectangle
[10:58:06] [PASSED] well_known_colors
[10:58:06] [PASSED] destination_pitch
[10:58:06] ========== [PASSED] drm_test_fb_xrgb8888_to_gray8 ==========
[10:58:06] ============= drm_test_fb_xrgb8888_to_rgb332  ==============
[10:58:06] [PASSED] single_pixel_source_buffer
[10:58:06] [PASSED] single_pixel_clip_rectangle
[10:58:06] [PASSED] well_known_colors
[10:58:06] [PASSED] destination_pitch
[10:58:06] ========= [PASSED] drm_test_fb_xrgb8888_to_rgb332 ==========
[10:58:06] ============= drm_test_fb_xrgb8888_to_rgb565  ==============
[10:58:06] [PASSED] single_pixel_source_buffer
[10:58:06] [PASSED] single_pixel_clip_rectangle
[10:58:06] [PASSED] well_known_colors
[10:58:06] [PASSED] destination_pitch
[10:58:06] ========= [PASSED] drm_test_fb_xrgb8888_to_rgb565 ==========
[10:58:06] ============ drm_test_fb_xrgb8888_to_xrgb1555  =============
[10:58:06] [PASSED] single_pixel_source_buffer
[10:58:06] [PASSED] single_pixel_clip_rectangle
[10:58:06] [PASSED] well_known_colors
[10:58:06] [PASSED] destination_pitch
[10:58:06] ======== [PASSED] drm_test_fb_xrgb8888_to_xrgb1555 =========
[10:58:06] ============ drm_test_fb_xrgb8888_to_argb1555  =============
[10:58:06] [PASSED] single_pixel_source_buffer
[10:58:06] [PASSED] single_pixel_clip_rectangle
[10:58:06] [PASSED] well_known_colors
[10:58:06] [PASSED] destination_pitch
[10:58:06] ======== [PASSED] drm_test_fb_xrgb8888_to_argb1555 =========
[10:58:06] ============ drm_test_fb_xrgb8888_to_rgba5551  =============
[10:58:06] [PASSED] single_pixel_source_buffer
[10:58:06] [PASSED] single_pixel_clip_rectangle
[10:58:06] [PASSED] well_known_colors
[10:58:06] [PASSED] destination_pitch
[10:58:06] ======== [PASSED] drm_test_fb_xrgb8888_to_rgba5551 =========
[10:58:06] ============= drm_test_fb_xrgb8888_to_rgb888  ==============
[10:58:06] [PASSED] single_pixel_source_buffer
[10:58:06] [PASSED] single_pixel_clip_rectangle
[10:58:06] [PASSED] well_known_colors
[10:58:06] [PASSED] destination_pitch
[10:58:06] ========= [PASSED] drm_test_fb_xrgb8888_to_rgb888 ==========
[10:58:06] ============= drm_test_fb_xrgb8888_to_bgr888  ==============
[10:58:06] [PASSED] single_pixel_source_buffer
[10:58:06] [PASSED] single_pixel_clip_rectangle
[10:58:06] [PASSED] well_known_colors
[10:58:06] [PASSED] destination_pitch
[10:58:06] ========= [PASSED] drm_test_fb_xrgb8888_to_bgr888 ==========
[10:58:06] ============ drm_test_fb_xrgb8888_to_argb8888  =============
[10:58:06] [PASSED] single_pixel_source_buffer
[10:58:06] [PASSED] single_pixel_clip_rectangle
[10:58:06] [PASSED] well_known_colors
[10:58:06] [PASSED] destination_pitch
[10:58:06] ======== [PASSED] drm_test_fb_xrgb8888_to_argb8888 =========
[10:58:06] =========== drm_test_fb_xrgb8888_to_xrgb2101010  ===========
[10:58:06] [PASSED] single_pixel_source_buffer
[10:58:06] [PASSED] single_pixel_clip_rectangle
[10:58:06] [PASSED] well_known_colors
[10:58:06] [PASSED] destination_pitch
[10:58:06] ======= [PASSED] drm_test_fb_xrgb8888_to_xrgb2101010 =======
[10:58:06] =========== drm_test_fb_xrgb8888_to_argb2101010  ===========
[10:58:06] [PASSED] single_pixel_source_buffer
[10:58:06] [PASSED] single_pixel_clip_rectangle
[10:58:06] [PASSED] well_known_colors
[10:58:06] [PASSED] destination_pitch
[10:58:06] ======= [PASSED] drm_test_fb_xrgb8888_to_argb2101010 =======
[10:58:06] ============== drm_test_fb_xrgb8888_to_mono  ===============
[10:58:06] [PASSED] single_pixel_source_buffer
[10:58:06] [PASSED] single_pixel_clip_rectangle
[10:58:06] [PASSED] well_known_colors
[10:58:06] [PASSED] destination_pitch
[10:58:06] ========== [PASSED] drm_test_fb_xrgb8888_to_mono ===========
[10:58:06] ==================== drm_test_fb_swab  =====================
[10:58:06] [PASSED] single_pixel_source_buffer
[10:58:06] [PASSED] single_pixel_clip_rectangle
[10:58:06] [PASSED] well_known_colors
[10:58:06] [PASSED] destination_pitch
[10:58:06] ================ [PASSED] drm_test_fb_swab =================
[10:58:06] ============ drm_test_fb_xrgb8888_to_xbgr8888  =============
[10:58:06] [PASSED] single_pixel_source_buffer
[10:58:06] [PASSED] single_pixel_clip_rectangle
[10:58:06] [PASSED] well_known_colors
[10:58:06] [PASSED] destination_pitch
[10:58:06] ======== [PASSED] drm_test_fb_xrgb8888_to_xbgr8888 =========
[10:58:06] ============ drm_test_fb_xrgb8888_to_abgr8888  =============
[10:58:06] [PASSED] single_pixel_source_buffer
[10:58:06] [PASSED] single_pixel_clip_rectangle
[10:58:06] [PASSED] well_known_colors
[10:58:06] [PASSED] destination_pitch
[10:58:06] ======== [PASSED] drm_test_fb_xrgb8888_to_abgr8888 =========
[10:58:06] ================= drm_test_fb_clip_offset  =================
[10:58:06] [PASSED] pass through
[10:58:06] [PASSED] horizontal offset
[10:58:06] [PASSED] vertical offset
[10:58:06] [PASSED] horizontal and vertical offset
[10:58:06] [PASSED] horizontal offset (custom pitch)
[10:58:06] [PASSED] vertical offset (custom pitch)
[10:58:06] [PASSED] horizontal and vertical offset (custom pitch)
[10:58:06] ============= [PASSED] drm_test_fb_clip_offset =============
[10:58:06] =================== drm_test_fb_memcpy  ====================
[10:58:06] [PASSED] single_pixel_source_buffer: XR24 little-endian (0x34325258)
[10:58:06] [PASSED] single_pixel_source_buffer: XRA8 little-endian (0x38415258)
[10:58:06] [PASSED] single_pixel_source_buffer: YU24 little-endian (0x34325559)
[10:58:06] [PASSED] single_pixel_clip_rectangle: XB24 little-endian (0x34324258)
[10:58:06] [PASSED] single_pixel_clip_rectangle: XRA8 little-endian (0x38415258)
[10:58:06] [PASSED] single_pixel_clip_rectangle: YU24 little-endian (0x34325559)
[10:58:06] [PASSED] well_known_colors: XB24 little-endian (0x34324258)
[10:58:06] [PASSED] well_known_colors: XRA8 little-endian (0x38415258)
[10:58:06] [PASSED] well_known_colors: YU24 little-endian (0x34325559)
[10:58:06] [PASSED] destination_pitch: XB24 little-endian (0x34324258)
[10:58:06] [PASSED] destination_pitch: XRA8 little-endian (0x38415258)
[10:58:06] [PASSED] destination_pitch: YU24 little-endian (0x34325559)
[10:58:06] =============== [PASSED] drm_test_fb_memcpy ================
[10:58:06] ============= [PASSED] drm_format_helper_test ==============
[10:58:06] ================= drm_format (18 subtests) =================
[10:58:06] [PASSED] drm_test_format_block_width_invalid
[10:58:06] [PASSED] drm_test_format_block_width_one_plane
[10:58:06] [PASSED] drm_test_format_block_width_two_plane
[10:58:06] [PASSED] drm_test_format_block_width_three_plane
[10:58:06] [PASSED] drm_test_format_block_width_tiled
[10:58:06] [PASSED] drm_test_format_block_height_invalid
[10:58:06] [PASSED] drm_test_format_block_height_one_plane
[10:58:06] [PASSED] drm_test_format_block_height_two_plane
[10:58:06] [PASSED] drm_test_format_block_height_three_plane
[10:58:06] [PASSED] drm_test_format_block_height_tiled
[10:58:06] [PASSED] drm_test_format_min_pitch_invalid
[10:58:06] [PASSED] drm_test_format_min_pitch_one_plane_8bpp
[10:58:06] [PASSED] drm_test_format_min_pitch_one_plane_16bpp
[10:58:06] [PASSED] drm_test_format_min_pitch_one_plane_24bpp
[10:58:06] [PASSED] drm_test_format_min_pitch_one_plane_32bpp
[10:58:06] [PASSED] drm_test_format_min_pitch_two_plane
[10:58:06] [PASSED] drm_test_format_min_pitch_three_plane_8bpp
[10:58:06] [PASSED] drm_test_format_min_pitch_tiled
[10:58:06] =================== [PASSED] drm_format ====================
[10:58:06] ============== drm_framebuffer (10 subtests) ===============
[10:58:06] ========== drm_test_framebuffer_check_src_coords  ==========
[10:58:06] [PASSED] Success: source fits into fb
[10:58:06] [PASSED] Fail: overflowing fb with x-axis coordinate
[10:58:06] [PASSED] Fail: overflowing fb with y-axis coordinate
[10:58:06] [PASSED] Fail: overflowing fb with source width
[10:58:06] [PASSED] Fail: overflowing fb with source height
[10:58:06] ====== [PASSED] drm_test_framebuffer_check_src_coords ======
[10:58:06] [PASSED] drm_test_framebuffer_cleanup
[10:58:06] =============== drm_test_framebuffer_create  ===============
[10:58:06] [PASSED] ABGR8888 normal sizes
[10:58:06] [PASSED] ABGR8888 max sizes
[10:58:06] [PASSED] ABGR8888 pitch greater than min required
[10:58:06] [PASSED] ABGR8888 pitch less than min required
[10:58:06] [PASSED] ABGR8888 Invalid width
[10:58:06] [PASSED] ABGR8888 Invalid buffer handle
[10:58:06] [PASSED] No pixel format
[10:58:06] [PASSED] ABGR8888 Width 0
[10:58:06] [PASSED] ABGR8888 Height 0
[10:58:06] [PASSED] ABGR8888 Out of bound height * pitch combination
[10:58:06] [PASSED] ABGR8888 Large buffer offset
[10:58:06] [PASSED] ABGR8888 Buffer offset for inexistent plane
[10:58:06] [PASSED] ABGR8888 Invalid flag
[10:58:06] [PASSED] ABGR8888 Set DRM_MODE_FB_MODIFIERS without modifiers
[10:58:06] [PASSED] ABGR8888 Valid buffer modifier
[10:58:06] [PASSED] ABGR8888 Invalid buffer modifier(DRM_FORMAT_MOD_SAMSUNG_64_32_TILE)
[10:58:06] [PASSED] ABGR8888 Extra pitches without DRM_MODE_FB_MODIFIERS
[10:58:06] [PASSED] ABGR8888 Extra pitches with DRM_MODE_FB_MODIFIERS
[10:58:06] [PASSED] NV12 Normal sizes
[10:58:06] [PASSED] NV12 Max sizes
[10:58:06] [PASSED] NV12 Invalid pitch
[10:58:06] [PASSED] NV12 Invalid modifier/missing DRM_MODE_FB_MODIFIERS flag
[10:58:06] [PASSED] NV12 different  modifier per-plane
[10:58:06] [PASSED] NV12 with DRM_FORMAT_MOD_SAMSUNG_64_32_TILE
[10:58:06] [PASSED] NV12 Valid modifiers without DRM_MODE_FB_MODIFIERS
[10:58:06] [PASSED] NV12 Modifier for inexistent plane
[10:58:06] [PASSED] NV12 Handle for inexistent plane
[10:58:06] [PASSED] NV12 Handle for inexistent plane without DRM_MODE_FB_MODIFIERS
[10:58:06] [PASSED] YVU420 DRM_MODE_FB_MODIFIERS set without modifier
[10:58:06] [PASSED] YVU420 Normal sizes
[10:58:06] [PASSED] YVU420 Max sizes
[10:58:06] [PASSED] YVU420 Invalid pitch
[10:58:06] [PASSED] YVU420 Different pitches
[10:58:06] [PASSED] YVU420 Different buffer offsets/pitches
[10:58:06] [PASSED] YVU420 Modifier set just for plane 0, without DRM_MODE_FB_MODIFIERS
[10:58:06] [PASSED] YVU420 Modifier set just for planes 0, 1, without DRM_MODE_FB_MODIFIERS
[10:58:06] [PASSED] YVU420 Modifier set just for plane 0, 1, with DRM_MODE_FB_MODIFIERS
[10:58:06] [PASSED] YVU420 Valid modifier
[10:58:06] [PASSED] YVU420 Different modifiers per plane
[10:58:06] [PASSED] YVU420 Modifier for inexistent plane
[10:58:06] [PASSED] YUV420_10BIT Invalid modifier(DRM_FORMAT_MOD_LINEAR)
[10:58:06] [PASSED] X0L2 Normal sizes
[10:58:06] [PASSED] X0L2 Max sizes
[10:58:06] [PASSED] X0L2 Invalid pitch
[10:58:06] [PASSED] X0L2 Pitch greater than minimum required
[10:58:06] [PASSED] X0L2 Handle for inexistent plane
[10:58:06] [PASSED] X0L2 Offset for inexistent plane, without DRM_MODE_FB_MODIFIERS set
[10:58:06] [PASSED] X0L2 Modifier without DRM_MODE_FB_MODIFIERS set
[10:58:06] [PASSED] X0L2 Valid modifier
[10:58:06] [PASSED] X0L2 Modifier for inexistent plane
[10:58:06] =========== [PASSED] drm_test_framebuffer_create ===========
[10:58:06] [PASSED] drm_test_framebuffer_free
[10:58:06] [PASSED] drm_test_framebuffer_init
[10:58:06] [PASSED] drm_test_framebuffer_init_bad_format
[10:58:06] [PASSED] drm_test_framebuffer_init_dev_mismatch
[10:58:06] [PASSED] drm_test_framebuffer_lookup
[10:58:06] [PASSED] drm_test_framebuffer_lookup_inexistent
[10:58:06] [PASSED] drm_test_framebuffer_modifiers_not_supported
[10:58:06] ================= [PASSED] drm_framebuffer =================
[10:58:06] ================ drm_gem_shmem (8 subtests) ================
[10:58:06] [PASSED] drm_gem_shmem_test_obj_create
[10:58:06] [PASSED] drm_gem_shmem_test_obj_create_private
[10:58:06] [PASSED] drm_gem_shmem_test_pin_pages
[10:58:06] [PASSED] drm_gem_shmem_test_vmap
[10:58:06] [PASSED] drm_gem_shmem_test_get_sg_table
[10:58:06] [PASSED] drm_gem_shmem_test_get_pages_sgt
[10:58:06] [PASSED] drm_gem_shmem_test_madvise
[10:58:06] [PASSED] drm_gem_shmem_test_purge
[10:58:06] ================== [PASSED] drm_gem_shmem ==================
[10:58:06] === drm_atomic_helper_connector_hdmi_check (27 subtests) ===
[10:58:06] [PASSED] drm_test_check_broadcast_rgb_auto_cea_mode
[10:58:06] [PASSED] drm_test_check_broadcast_rgb_auto_cea_mode_vic_1
[10:58:06] [PASSED] drm_test_check_broadcast_rgb_full_cea_mode
[10:58:06] [PASSED] drm_test_check_broadcast_rgb_full_cea_mode_vic_1
[10:58:06] [PASSED] drm_test_check_broadcast_rgb_limited_cea_mode
[10:58:06] [PASSED] drm_test_check_broadcast_rgb_limited_cea_mode_vic_1
[10:58:06] ====== drm_test_check_broadcast_rgb_cea_mode_yuv420  =======
[10:58:06] [PASSED] Automatic
[10:58:06] [PASSED] Full
[10:58:06] [PASSED] Limited 16:235
[10:58:06] == [PASSED] drm_test_check_broadcast_rgb_cea_mode_yuv420 ===
[10:58:06] [PASSED] drm_test_check_broadcast_rgb_crtc_mode_changed
[10:58:06] [PASSED] drm_test_check_broadcast_rgb_crtc_mode_not_changed
[10:58:06] [PASSED] drm_test_check_disable_connector
[10:58:06] [PASSED] drm_test_check_hdmi_funcs_reject_rate
[10:58:06] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_rgb
[10:58:06] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_yuv420
[10:58:06] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_ignore_yuv422
[10:58:06] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_ignore_yuv420
[10:58:06] [PASSED] drm_test_check_driver_unsupported_fallback_yuv420
[10:58:06] [PASSED] drm_test_check_output_bpc_crtc_mode_changed
[10:58:06] [PASSED] drm_test_check_output_bpc_crtc_mode_not_changed
[10:58:06] [PASSED] drm_test_check_output_bpc_dvi
[10:58:06] [PASSED] drm_test_check_output_bpc_format_vic_1
[10:58:06] [PASSED] drm_test_check_output_bpc_format_display_8bpc_only
[10:58:06] [PASSED] drm_test_check_output_bpc_format_display_rgb_only
[10:58:06] [PASSED] drm_test_check_output_bpc_format_driver_8bpc_only
[10:58:06] [PASSED] drm_test_check_output_bpc_format_driver_rgb_only
[10:58:06] [PASSED] drm_test_check_tmds_char_rate_rgb_8bpc
[10:58:06] [PASSED] drm_test_check_tmds_char_rate_rgb_10bpc
[10:58:06] [PASSED] drm_test_check_tmds_char_rate_rgb_12bpc
[10:58:06] ===== [PASSED] drm_atomic_helper_connector_hdmi_check ======
[10:58:06] === drm_atomic_helper_connector_hdmi_reset (6 subtests) ====
[10:58:06] [PASSED] drm_test_check_broadcast_rgb_value
[10:58:06] [PASSED] drm_test_check_bpc_8_value
[10:58:06] [PASSED] drm_test_check_bpc_10_value
[10:58:06] [PASSED] drm_test_check_bpc_12_value
[10:58:06] [PASSED] drm_test_check_format_value
[10:58:06] [PASSED] drm_test_check_tmds_char_value
[10:58:06] ===== [PASSED] drm_atomic_helper_connector_hdmi_reset ======
[10:58:06] = drm_atomic_helper_connector_hdmi_mode_valid (4 subtests) =
[10:58:06] [PASSED] drm_test_check_mode_valid
[10:58:06] [PASSED] drm_test_check_mode_valid_reject
[10:58:06] [PASSED] drm_test_check_mode_valid_reject_rate
[10:58:06] [PASSED] drm_test_check_mode_valid_reject_max_clock
[10:58:06] === [PASSED] drm_atomic_helper_connector_hdmi_mode_valid ===
[10:58:06] ================= drm_managed (2 subtests) =================
[10:58:06] [PASSED] drm_test_managed_release_action
[10:58:06] [PASSED] drm_test_managed_run_action
[10:58:06] =================== [PASSED] drm_managed ===================
[10:58:06] =================== drm_mm (6 subtests) ====================
[10:58:06] [PASSED] drm_test_mm_init
[10:58:06] [PASSED] drm_test_mm_debug
[10:58:06] [PASSED] drm_test_mm_align32
[10:58:06] [PASSED] drm_test_mm_align64
[10:58:06] [PASSED] drm_test_mm_lowest
[10:58:06] [PASSED] drm_test_mm_highest
[10:58:06] ===================== [PASSED] drm_mm ======================
[10:58:06] ============= drm_modes_analog_tv (5 subtests) =============
[10:58:06] [PASSED] drm_test_modes_analog_tv_mono_576i
[10:58:06] [PASSED] drm_test_modes_analog_tv_ntsc_480i
[10:58:06] [PASSED] drm_test_modes_analog_tv_ntsc_480i_inlined
[10:58:06] [PASSED] drm_test_modes_analog_tv_pal_576i
[10:58:06] [PASSED] drm_test_modes_analog_tv_pal_576i_inlined
[10:58:06] =============== [PASSED] drm_modes_analog_tv ===============
[10:58:06] ============== drm_plane_helper (2 subtests) ===============
[10:58:06] =============== drm_test_check_plane_state  ================
[10:58:06] [PASSED] clipping_simple
[10:58:06] [PASSED] clipping_rotate_reflect
[10:58:06] [PASSED] positioning_simple
[10:58:06] [PASSED] upscaling
[10:58:06] [PASSED] downscaling
[10:58:06] [PASSED] rounding1
[10:58:06] [PASSED] rounding2
[10:58:06] [PASSED] rounding3
[10:58:06] [PASSED] rounding4
[10:58:06] =========== [PASSED] drm_test_check_plane_state ============
[10:58:06] =========== drm_test_check_invalid_plane_state  ============
[10:58:06] [PASSED] positioning_invalid
[10:58:06] [PASSED] upscaling_invalid
[10:58:06] [PASSED] downscaling_invalid
[10:58:06] ======= [PASSED] drm_test_check_invalid_plane_state ========
[10:58:06] ================ [PASSED] drm_plane_helper =================
[10:58:06] ====== drm_connector_helper_tv_get_modes (1 subtest) =======
[10:58:06] ====== drm_test_connector_helper_tv_get_modes_check  =======
[10:58:06] [PASSED] None
[10:58:06] [PASSED] PAL
[10:58:06] [PASSED] NTSC
[10:58:06] [PASSED] Both, NTSC Default
[10:58:06] [PASSED] Both, PAL Default
[10:58:06] [PASSED] Both, NTSC Default, with PAL on command-line
[10:58:06] [PASSED] Both, PAL Default, with NTSC on command-line
[10:58:06] == [PASSED] drm_test_connector_helper_tv_get_modes_check ===
[10:58:06] ======== [PASSED] drm_connector_helper_tv_get_modes ========
[10:58:06] ================== drm_rect (9 subtests) ===================
[10:58:06] [PASSED] drm_test_rect_clip_scaled_div_by_zero
[10:58:06] [PASSED] drm_test_rect_clip_scaled_not_clipped
[10:58:06] [PASSED] drm_test_rect_clip_scaled_clipped
[10:58:06] [PASSED] drm_test_rect_clip_scaled_signed_vs_unsigned
[10:58:06] ================= drm_test_rect_intersect  =================
[10:58:06] [PASSED] top-left x bottom-right: 2x2+1+1 x 2x2+0+0
[10:58:06] [PASSED] top-right x bottom-left: 2x2+0+0 x 2x2+1-1
[10:58:06] [PASSED] bottom-left x top-right: 2x2+1-1 x 2x2+0+0
[10:58:06] [PASSED] bottom-right x top-left: 2x2+0+0 x 2x2+1+1
[10:58:06] [PASSED] right x left: 2x1+0+0 x 3x1+1+0
[10:58:06] [PASSED] left x right: 3x1+1+0 x 2x1+0+0
[10:58:06] [PASSED] up x bottom: 1x2+0+0 x 1x3+0-1
[10:58:06] [PASSED] bottom x up: 1x3+0-1 x 1x2+0+0
[10:58:06] [PASSED] touching corner: 1x1+0+0 x 2x2+1+1
[10:58:06] [PASSED] touching side: 1x1+0+0 x 1x1+1+0
[10:58:06] [PASSED] equal rects: 2x2+0+0 x 2x2+0+0
[10:58:06] [PASSED] inside another: 2x2+0+0 x 1x1+1+1
[10:58:06] [PASSED] far away: 1x1+0+0 x 1x1+3+6
[10:58:06] [PASSED] points intersecting: 0x0+5+10 x 0x0+5+10
[10:58:06] [PASSED] points not intersecting: 0x0+0+0 x 0x0+5+10
[10:58:06] ============= [PASSED] drm_test_rect_intersect =============
[10:58:06] ================ drm_test_rect_calc_hscale  ================
[10:58:06] [PASSED] normal use
[10:58:06] [PASSED] out of max range
[10:58:06] [PASSED] out of min range
[10:58:06] [PASSED] zero dst
[10:58:06] [PASSED] negative src
[10:58:06] [PASSED] negative dst
[10:58:06] ============ [PASSED] drm_test_rect_calc_hscale ============
[10:58:06] ================ drm_test_rect_calc_vscale  ================
[10:58:06] [PASSED] normal use
stty: 'standard input': Inappropriate ioctl for device
[10:58:06] [PASSED] out of max range
[10:58:06] [PASSED] out of min range
[10:58:06] [PASSED] zero dst
[10:58:06] [PASSED] negative src
[10:58:06] [PASSED] negative dst
[10:58:06] ============ [PASSED] drm_test_rect_calc_vscale ============
[10:58:06] ================== drm_test_rect_rotate  ===================
[10:58:06] [PASSED] reflect-x
[10:58:06] [PASSED] reflect-y
[10:58:06] [PASSED] rotate-0
[10:58:06] [PASSED] rotate-90
[10:58:06] [PASSED] rotate-180
[10:58:06] [PASSED] rotate-270
[10:58:06] ============== [PASSED] drm_test_rect_rotate ===============
[10:58:06] ================ drm_test_rect_rotate_inv  =================
[10:58:06] [PASSED] reflect-x
[10:58:06] [PASSED] reflect-y
[10:58:06] [PASSED] rotate-0
[10:58:06] [PASSED] rotate-90
[10:58:06] [PASSED] rotate-180
[10:58:06] [PASSED] rotate-270
[10:58:06] ============ [PASSED] drm_test_rect_rotate_inv =============
[10:58:06] ==================== [PASSED] drm_rect =====================
[10:58:06] ============ drm_sysfb_modeset_test (1 subtest) ============
[10:58:06] ============ drm_test_sysfb_build_fourcc_list  =============
[10:58:06] [PASSED] no native formats
[10:58:06] [PASSED] XRGB8888 as native format
[10:58:06] [PASSED] remove duplicates
[10:58:06] [PASSED] convert alpha formats
[10:58:06] [PASSED] random formats
[10:58:06] ======== [PASSED] drm_test_sysfb_build_fourcc_list =========
[10:58:06] ============= [PASSED] drm_sysfb_modeset_test ==============
[10:58:06] ================== drm_fixp (2 subtests) ===================
[10:58:06] [PASSED] drm_test_int2fixp
[10:58:06] [PASSED] drm_test_sm2fixp
[10:58:06] ==================== [PASSED] drm_fixp =====================
[10:58:06] ============================================================
[10:58:06] Testing complete. Ran 624 tests: passed: 624
[10:58:06] Elapsed time: 27.600s total, 1.699s configuring, 25.435s building, 0.408s running

+ /kernel/tools/testing/kunit/kunit.py run --kunitconfig /kernel/drivers/gpu/drm/ttm/tests/.kunitconfig
[10:58:06] Configuring KUnit Kernel ...
Regenerating .config ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
[10:58:08] Building KUnit Kernel ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
Building with:
$ make all compile_commands.json scripts_gdb ARCH=um O=.kunit --jobs=48
[10:58:17] Starting KUnit Kernel (1/1)...
[10:58:17] ============================================================
Running tests with:
$ .kunit/linux kunit.enable=1 mem=1G console=tty kunit_shutdown=halt
[10:58:17] ================= ttm_device (5 subtests) ==================
[10:58:17] [PASSED] ttm_device_init_basic
[10:58:17] [PASSED] ttm_device_init_multiple
[10:58:17] [PASSED] ttm_device_fini_basic
[10:58:17] [PASSED] ttm_device_init_no_vma_man
[10:58:17] ================== ttm_device_init_pools  ==================
[10:58:17] [PASSED] No DMA allocations, no DMA32 required
[10:58:17] [PASSED] DMA allocations, DMA32 required
[10:58:17] [PASSED] No DMA allocations, DMA32 required
[10:58:17] [PASSED] DMA allocations, no DMA32 required
[10:58:17] ============== [PASSED] ttm_device_init_pools ==============
[10:58:17] =================== [PASSED] ttm_device ====================
[10:58:17] ================== ttm_pool (8 subtests) ===================
[10:58:17] ================== ttm_pool_alloc_basic  ===================
[10:58:17] [PASSED] One page
[10:58:17] [PASSED] More than one page
[10:58:17] [PASSED] Above the allocation limit
[10:58:17] [PASSED] One page, with coherent DMA mappings enabled
[10:58:17] [PASSED] Above the allocation limit, with coherent DMA mappings enabled
[10:58:17] ============== [PASSED] ttm_pool_alloc_basic ===============
[10:58:17] ============== ttm_pool_alloc_basic_dma_addr  ==============
[10:58:17] [PASSED] One page
[10:58:17] [PASSED] More than one page
[10:58:17] [PASSED] Above the allocation limit
[10:58:17] [PASSED] One page, with coherent DMA mappings enabled
[10:58:17] [PASSED] Above the allocation limit, with coherent DMA mappings enabled
[10:58:17] ========== [PASSED] ttm_pool_alloc_basic_dma_addr ==========
[10:58:17] [PASSED] ttm_pool_alloc_order_caching_match
[10:58:17] [PASSED] ttm_pool_alloc_caching_mismatch
[10:58:17] [PASSED] ttm_pool_alloc_order_mismatch
[10:58:17] [PASSED] ttm_pool_free_dma_alloc
[10:58:17] [PASSED] ttm_pool_free_no_dma_alloc
[10:58:17] [PASSED] ttm_pool_fini_basic
[10:58:17] ==================== [PASSED] ttm_pool =====================
[10:58:17] ================ ttm_resource (8 subtests) =================
[10:58:17] ================= ttm_resource_init_basic  =================
[10:58:17] [PASSED] Init resource in TTM_PL_SYSTEM
[10:58:17] [PASSED] Init resource in TTM_PL_VRAM
[10:58:17] [PASSED] Init resource in a private placement
[10:58:17] [PASSED] Init resource in TTM_PL_SYSTEM, set placement flags
[10:58:17] ============= [PASSED] ttm_resource_init_basic =============
[10:58:17] [PASSED] ttm_resource_init_pinned
[10:58:17] [PASSED] ttm_resource_fini_basic
[10:58:17] [PASSED] ttm_resource_manager_init_basic
[10:58:17] [PASSED] ttm_resource_manager_usage_basic
[10:58:17] [PASSED] ttm_resource_manager_set_used_basic
[10:58:17] [PASSED] ttm_sys_man_alloc_basic
[10:58:17] [PASSED] ttm_sys_man_free_basic
[10:58:17] ================== [PASSED] ttm_resource ===================
[10:58:17] =================== ttm_tt (15 subtests) ===================
[10:58:17] ==================== ttm_tt_init_basic  ====================
[10:58:17] [PASSED] Page-aligned size
[10:58:17] [PASSED] Extra pages requested
[10:58:17] ================ [PASSED] ttm_tt_init_basic ================
[10:58:17] [PASSED] ttm_tt_init_misaligned
[10:58:17] [PASSED] ttm_tt_fini_basic
[10:58:17] [PASSED] ttm_tt_fini_sg
[10:58:17] [PASSED] ttm_tt_fini_shmem
[10:58:17] [PASSED] ttm_tt_create_basic
[10:58:17] [PASSED] ttm_tt_create_invalid_bo_type
[10:58:17] [PASSED] ttm_tt_create_ttm_exists
[10:58:17] [PASSED] ttm_tt_create_failed
[10:58:17] [PASSED] ttm_tt_destroy_basic
[10:58:17] [PASSED] ttm_tt_populate_null_ttm
[10:58:17] [PASSED] ttm_tt_populate_populated_ttm
[10:58:17] [PASSED] ttm_tt_unpopulate_basic
[10:58:17] [PASSED] ttm_tt_unpopulate_empty_ttm
[10:58:17] [PASSED] ttm_tt_swapin_basic
[10:58:17] ===================== [PASSED] ttm_tt ======================
[10:58:17] =================== ttm_bo (14 subtests) ===================
[10:58:17] =========== ttm_bo_reserve_optimistic_no_ticket  ===========
[10:58:17] [PASSED] Cannot be interrupted and sleeps
[10:58:17] [PASSED] Cannot be interrupted, locks straight away
[10:58:17] [PASSED] Can be interrupted, sleeps
[10:58:17] ======= [PASSED] ttm_bo_reserve_optimistic_no_ticket =======
[10:58:17] [PASSED] ttm_bo_reserve_locked_no_sleep
[10:58:17] [PASSED] ttm_bo_reserve_no_wait_ticket
[10:58:17] [PASSED] ttm_bo_reserve_double_resv
[10:58:17] [PASSED] ttm_bo_reserve_interrupted
[10:58:17] [PASSED] ttm_bo_reserve_deadlock
[10:58:17] [PASSED] ttm_bo_unreserve_basic
[10:58:17] [PASSED] ttm_bo_unreserve_pinned
[10:58:17] [PASSED] ttm_bo_unreserve_bulk
[10:58:17] [PASSED] ttm_bo_fini_basic
[10:58:17] [PASSED] ttm_bo_fini_shared_resv
[10:58:17] [PASSED] ttm_bo_pin_basic
[10:58:17] [PASSED] ttm_bo_pin_unpin_resource
[10:58:17] [PASSED] ttm_bo_multiple_pin_one_unpin
[10:58:17] ===================== [PASSED] ttm_bo ======================
[10:58:17] ============== ttm_bo_validate (21 subtests) ===============
[10:58:17] ============== ttm_bo_init_reserved_sys_man  ===============
[10:58:17] [PASSED] Buffer object for userspace
[10:58:17] [PASSED] Kernel buffer object
[10:58:17] [PASSED] Shared buffer object
[10:58:17] ========== [PASSED] ttm_bo_init_reserved_sys_man ===========
[10:58:17] ============== ttm_bo_init_reserved_mock_man  ==============
[10:58:17] [PASSED] Buffer object for userspace
[10:58:17] [PASSED] Kernel buffer object
[10:58:17] [PASSED] Shared buffer object
[10:58:17] ========== [PASSED] ttm_bo_init_reserved_mock_man ==========
[10:58:17] [PASSED] ttm_bo_init_reserved_resv
[10:58:17] ================== ttm_bo_validate_basic  ==================
[10:58:17] [PASSED] Buffer object for userspace
[10:58:17] [PASSED] Kernel buffer object
[10:58:17] [PASSED] Shared buffer object
[10:58:17] ============== [PASSED] ttm_bo_validate_basic ==============
[10:58:17] [PASSED] ttm_bo_validate_invalid_placement
[10:58:17] ============= ttm_bo_validate_same_placement  ==============
[10:58:17] [PASSED] System manager
[10:58:17] [PASSED] VRAM manager
[10:58:17] ========= [PASSED] ttm_bo_validate_same_placement ==========
[10:58:17] [PASSED] ttm_bo_validate_failed_alloc
[10:58:17] [PASSED] ttm_bo_validate_pinned
[10:58:17] [PASSED] ttm_bo_validate_busy_placement
[10:58:17] ================ ttm_bo_validate_multihop  =================
[10:58:17] [PASSED] Buffer object for userspace
[10:58:17] [PASSED] Kernel buffer object
[10:58:17] [PASSED] Shared buffer object
[10:58:17] ============ [PASSED] ttm_bo_validate_multihop =============
[10:58:17] ========== ttm_bo_validate_no_placement_signaled  ==========
[10:58:17] [PASSED] Buffer object in system domain, no page vector
[10:58:17] [PASSED] Buffer object in system domain with an existing page vector
[10:58:17] ====== [PASSED] ttm_bo_validate_no_placement_signaled ======
[10:58:17] ======== ttm_bo_validate_no_placement_not_signaled  ========
[10:58:17] [PASSED] Buffer object for userspace
[10:58:17] [PASSED] Kernel buffer object
[10:58:17] [PASSED] Shared buffer object
[10:58:17] ==== [PASSED] ttm_bo_validate_no_placement_not_signaled ====
[10:58:17] [PASSED] ttm_bo_validate_move_fence_signaled
[10:58:17] ========= ttm_bo_validate_move_fence_not_signaled  =========
[10:58:17] [PASSED] Waits for GPU
[10:58:17] [PASSED] Tries to lock straight away
[10:58:17] ===== [PASSED] ttm_bo_validate_move_fence_not_signaled =====
[10:58:17] [PASSED] ttm_bo_validate_happy_evict
[10:58:17] [PASSED] ttm_bo_validate_all_pinned_evict
[10:58:17] [PASSED] ttm_bo_validate_allowed_only_evict
[10:58:17] [PASSED] ttm_bo_validate_deleted_evict
[10:58:17] [PASSED] ttm_bo_validate_busy_domain_evict
[10:58:17] [PASSED] ttm_bo_validate_evict_gutting
[10:58:17] [PASSED] ttm_bo_validate_recrusive_evict
stty: 'standard input': Inappropriate ioctl for device
[10:58:17] ================= [PASSED] ttm_bo_validate =================
[10:58:17] ============================================================
[10:58:17] Testing complete. Ran 101 tests: passed: 101
[10:58:17] Elapsed time: 11.243s total, 1.673s configuring, 9.355s building, 0.179s running

+ cleanup
++ stat -c %u:%g /kernel
+ chown -R 1003:1003 /kernel

✗ CI.checksparse: warning for Enable/Disable DC balance along with VRR DSB

[Patchwork]

== Series Details ==

Series: Enable/Disable DC balance along with VRR DSB
URL   : https://patchwork.freedesktop.org/series/159419/
State : warning

== Summary ==

+ trap cleanup EXIT
+ KERNEL=/kernel
+ MT=/root/linux/maintainer-tools
+ git clone https://gitlab.freedesktop.org/drm/maintainer-tools /root/linux/maintainer-tools
Cloning into '/root/linux/maintainer-tools'...
warning: redirecting to https://gitlab.freedesktop.org/drm/maintainer-tools.git/
+ make -C /root/linux/maintainer-tools
make: Entering directory '/root/linux/maintainer-tools'
cc -O2 -g -Wextra -o remap-log remap-log.c
make: Leaving directory '/root/linux/maintainer-tools'
+ cd /kernel
+ git config --global --add safe.directory /kernel
+ /root/linux/maintainer-tools/dim sparse --fast cab246648fd89efbe8d20ed4c86e7fcebd7606da
Sparse version: 0.6.4 (Ubuntu: 0.6.4-4ubuntu3)
Fast mode used, each commit won't be checked separately.
+:
+drivers/gpu/drm/i915/display/dvo_ch7017.c: note: in included file (through drivers/gpu/drm/i915/display/intel_display_types.h):
+drivers/gpu/drm/i915/display/dvo_ch7xxx.c: note: in included file (through drivers/gpu/drm/i915/display/intel_display_types.h):
+drivers/gpu/drm/i915/display/dvo_ivch.c: note: in included file (through drivers/gpu/drm/i915/display/intel_display_types.h):
+drivers/gpu/drm/i915/display/dvo_ns2501.c: note: in included file (through drivers/gpu/drm/i915/display/intel_display_types.h):
+drivers/gpu/drm/i915/display/dvo_sil164.c: note: in included file (through drivers/gpu/drm/i915/display/intel_display_types.h):
+drivers/gpu/drm/i915/display/dvo_tfp410.c: note: in included file (through drivers/gpu/drm/i915/display/intel_display_types.h):
+drivers/gpu/drm/i915/display/g4x_dp.c: note: in included file (through drivers/gpu/drm/i915/display/intel_display_types.h):
+drivers/gpu/drm/i915/display/g4x_hdmi.c: note: in included file (through drivers/gpu/drm/i915/display/intel_display_types.h):
+drivers/gpu/drm/i915/display/hsw_ips.c: note: in included file (through drivers/gpu/drm/i915/display/intel_display_types.h):
+drivers/gpu/drm/i915/display/i9xx_plane.c: note: in included file (through drivers/gpu/drm/i915/display/intel_display_types.h):
+drivers/gpu/drm/i915/display/i9xx_wm.c: note: in included file (through drivers/gpu/drm/i915/display/intel_display_types.h, drivers/gpu/drm/i915/display/intel_display_trace.h):
+drivers/gpu/drm/i915/display/icl_dsi.c: note: in included file (through drivers/gpu/drm/i915/display/intel_display_types.h, drivers/gpu/drm/i915/display/intel_dsi.h):
+drivers/gpu/drm/i915/display/intel_acpi.c: note: in included file (through drivers/gpu/drm/i915/display/intel_display_types.h):
+drivers/gpu/drm/i915/display/intel_alpm.c: note: in included file (through drivers/gpu/drm/i915/display/intel_display_types.h):
+drivers/gpu/drm/i915/display/intel_atomic.c: note: in included file (through drivers/gpu/drm/i915/display/intel_display_types.h):
+drivers/gpu/drm/i915/display/intel_audio.c: note: in included file (through drivers/gpu/drm/i915/display/intel_display_types.h):
+drivers/gpu/drm/i915/display/intel_backlight.c: note: in included file:
+drivers/gpu/drm/i915/display/intel_bios.c: note: in included file (through drivers/gpu/drm/i915/display/intel_display_types.h):
+drivers/gpu/drm/i915/display/intel_bw.c: note: in included file (through drivers/gpu/drm/i915/display/intel_display_types.h):
+drivers/gpu/drm/i915/display/intel_casf.c:147:21: error: too long token expansion
+drivers/gpu/drm/i915/display/intel_casf.c: note: in included file (through drivers/gpu/drm/i915/display/intel_display_types.h):
+drivers/gpu/drm/i915/display/intel_cdclk.c: note: in included file (through drivers/gpu/drm/i915/display/intel_display_types.h):
+drivers/gpu/drm/i915/display/intel_color.c: note: in included file (through drivers/gpu/drm/i915/display/intel_display_types.h):
+drivers/gpu/drm/i915/display/intel_colorop.c: note: in included file (through drivers/gpu/drm/i915/display/intel_display_types.h):
+drivers/gpu/drm/i915/display/intel_color_pipeline.c: note: in included file (through drivers/gpu/drm/i915/display/intel_display_types.h):
+drivers/gpu/drm/i915/display/intel_combo_phy.c: note: in included file (through drivers/gpu/drm/i915/display/intel_display_types.h):
+drivers/gpu/drm/i915/display/intel_connector.c: note: in included file (through drivers/gpu/drm/i915/display/intel_display_types.h):
+drivers/gpu/drm/i915/display/intel_crtc.c: note: in included file (through drivers/gpu/drm/i915/display/intel_display_types.h, drivers/gpu/drm/i915/display/intel_display_trace.h):
+drivers/gpu/drm/i915/display/intel_crt.c: note: in included file (through drivers/gpu/drm/i915/display/intel_display_types.h):
+drivers/gpu/drm/i915/display/intel_crtc_state_dump.c: note: in included file (through drivers/gpu/drm/i915/display/intel_display_types.h):
+drivers/gpu/drm/i915/display/intel_cursor.c: note: in included file (through drivers/gpu/drm/i915/display/intel_display_types.h):
+drivers/gpu/drm/i915/display/intel_cx0_phy.c: note: in included file (through drivers/gpu/drm/i915/display/intel_display_types.h):
+drivers/gpu/drm/i915/display/intel_dbuf_bw.c: note: in included file (through drivers/gpu/drm/i915/display/intel_display_types.h):
+drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c: note: in included file (through drivers/gpu/drm/i915/display/intel_display_types.h):
+drivers/gpu/drm/i915/display/intel_ddi.c: note: in included file (through drivers/gpu/drm/i915/display/intel_display_types.h):
+drivers/gpu/drm/i915/display/intel_display.c: note: in included file (through drivers/gpu/drm/i915/display/intel_display_types.h):
+drivers/gpu/drm/i915/display/intel_display_debugfs.c: note: in included file (through drivers/gpu/drm/i915/display/intel_display_types.h):
+drivers/gpu/drm/i915/display/intel_display_device.c: note: in included file (through drivers/gpu/drm/i915/display/intel_display_types.h):
+drivers/gpu/drm/i915/display/intel_display_driver.c: note: in included file (through drivers/gpu/drm/i915/display/intel_display_types.h):
+drivers/gpu/drm/i915/display/intel_display_irq.c: note: in included file (through drivers/gpu/drm/i915/display/intel_display_types.h, drivers/gpu/drm/i915/display/intel_display_trace.h):
+drivers/gpu/drm/i915/display/intel_display_power.c: note: in included file (through drivers/gpu/drm/i915/display/intel_display_types.h):
+drivers/gpu/drm/i915/display/intel_display_power_map.c: note: in included file (through drivers/gpu/drm/i915/display/intel_display_types.h):
+drivers/gpu/drm/i915/display/intel_display_power_well.c: note: in included file (through drivers/gpu/drm/i915/display/intel_display_types.h):
+drivers/gpu/drm/i915/display/intel_display_reset.c: note: in included file (through drivers/gpu/drm/i915/display/intel_display_types.h):
+drivers/gpu/drm/i915/display/intel_display_rps.c: note: in included file (through drivers/gpu/drm/i915/display/intel_display_types.h):
+drivers/gpu/drm/i915/display/intel_dmc.c:131:1: error: bad constant expression
+drivers/gpu/drm/i915/display/intel_dmc.c:134:1: error: bad constant expression
+drivers/gpu/drm/i915/display/intel_dmc.c:137:1: error: bad constant expression
+drivers/gpu/drm/i915/display/intel_dmc.c:140:1: error: bad constant expression
+drivers/gpu/drm/i915/display/intel_dmc.c:143:1: error: bad constant expression
+drivers/gpu/drm/i915/display/intel_dmc.c:146:1: error: bad constant expression
+drivers/gpu/drm/i915/display/intel_dmc.c:149:1: error: bad constant expression
+drivers/gpu/drm/i915/display/intel_dmc.c:153:1: error: bad constant expression
+drivers/gpu/drm/i915/display/intel_dmc.c:154:1: error: bad constant expression
+drivers/gpu/drm/i915/display/intel_dmc.c:157:1: error: bad constant expression
+drivers/gpu/drm/i915/display/intel_dmc.c:160:1: error: bad constant expression
+drivers/gpu/drm/i915/display/intel_dmc.c:163:1: error: bad constant expression
+drivers/gpu/drm/i915/display/intel_dmc.c:166:1: error: bad constant expression
+drivers/gpu/drm/i915/display/intel_dmc.c:170:1: error: bad constant expression
+drivers/gpu/drm/i915/display/intel_dmc.c:174:1: error: bad constant expression
+drivers/gpu/drm/i915/display/intel_dmc.c:178:1: error: bad constant expression
+drivers/gpu/drm/i915/display/intel_dmc.c:182:1: error: bad constant expression
+drivers/gpu/drm/i915/display/intel_dmc.c:186:1: error: bad constant expression
+drivers/gpu/drm/i915/display/intel_dmc.c: note: in included file (through drivers/gpu/drm/i915/display/intel_display_types.h):
+drivers/gpu/drm/i915/display/intel_dp_aux_backlight.c: note: in included file (through drivers/gpu/drm/i915/display/intel_display_types.h):
+drivers/gpu/drm/i915/display/intel_dp_aux.c: note: in included file (through drivers/gpu/drm/i915/display/intel_display_types.h):
+drivers/gpu/drm/i915/display/intel_dp.c: note: in included file (through drivers/gpu/drm/i915/display/intel_display_types.h):
+drivers/gpu/drm/i915/display/intel_dp_hdcp.c: note: in included file (through drivers/gpu/drm/i915/display/intel_display_types.h):
+drivers/gpu/drm/i915/display/intel_dpio_phy.c: note: in included file (through drivers/gpu/drm/i915/display/intel_display_types.h):
+drivers/gpu/drm/i915/display/intel_dp_link_training.c: note: in included file (through drivers/gpu/drm/i915/display/intel_display_types.h):
+drivers/gpu/drm/i915/display/intel_dpll.c: note: in included file (through drivers/gpu/drm/i915/display/intel_display_types.h):
+drivers/gpu/drm/i915/display/intel_dpll_mgr.c: note: in included file (through drivers/gpu/drm/i915/display/intel_display_types.h):
+drivers/gpu/drm/i915/display/intel_dp_mst.c: note: in included file (through drivers/gpu/drm/i915/display/intel_display_types.h):
+drivers/gpu/drm/i915/display/intel_dpt.c: note: in included file (through drivers/gpu/drm/i915/display/intel_display_types.h):
+drivers/gpu/drm/i915/display/intel_dpt_common.c: note: in included file (through drivers/gpu/drm/i915/display/intel_display_types.h):
+drivers/gpu/drm/i915/display/intel_dp_test.c: note: in included file (through drivers/gpu/drm/i915/display/intel_display_types.h):
+drivers/gpu/drm/i915/display/intel_drrs.c: note: in included file (through drivers/gpu/drm/i915/display/intel_display_types.h):
+drivers/gpu/drm/i915/display/intel_dsb.c: note: in included file (through drivers/gpu/drm/i915/display/intel_display_types.h):
+drivers/gpu/drm/i915/display/intel_dsi.c: note: in included file (through drivers/gpu/drm/i915/display/intel_display_types.h, drivers/gpu/drm/i915/display/intel_dsi.h):
+drivers/gpu/drm/i915/display/intel_dsi_dcs_backlight.c: note: in included file (through drivers/gpu/drm/i915/display/intel_display_types.h):
+drivers/gpu/drm/i915/display/intel_dsi_vbt.c: note: in included file (through drivers/gpu/drm/i915/display/intel_display_types.h):
+drivers/gpu/drm/i915/display/intel_dvo.c: note: in included file (through drivers/gpu/drm/i915/display/intel_display_types.h):
+drivers/gpu/drm/i915/display/intel_encoder.c: note: in included file (through drivers/gpu/drm/i915/display/intel_display_types.h):
+drivers/gpu/drm/i915/display/intel_fb_bo.c: note: in included file (through drivers/gpu/drm/i915/display/intel_display_types.h):
+drivers/gpu/drm/i915/display/intel_fbc.c: note: in included file (through drivers/gpu/drm/i915/display/intel_display_types.h, drivers/gpu/drm/i915/display/intel_display_trace.h):
+drivers/gpu/drm/i915/display/intel_fb.c: note: in included file (through drivers/gpu/drm/i915/display/intel_display_types.h):
+drivers/gpu/drm/i915/display/intel_fb_pin.c: note: in included file (through drivers/gpu/drm/i915/display/intel_display_types.h):
+drivers/gpu/drm/i915/display/intel_fdi.c: note: in included file (through drivers/gpu/drm/i915/display/intel_display_types.h):
+drivers/gpu/drm/i915/display/intel_fifo_underrun.c: note: in included file (through drivers/gpu/drm/i915/display/intel_display_types.h, drivers/gpu/drm/i915/display/intel_display_trace.h):
+drivers/gpu/drm/i915/display/intel_flipq.c: note: in included file (through drivers/gpu/drm/i915/display/intel_display_types.h):
+drivers/gpu/drm/i915/display/intel_frontbuffer.c: note: in included file (through drivers/gpu/drm/i915/display/intel_display_types.h, drivers/gpu/drm/i915/display/intel_display_trace.h):
+drivers/gpu/drm/i915/display/intel_global_state.c: note: in included file (through drivers/gpu/drm/i915/display/intel_display_types.h):
+drivers/gpu/drm/i915/display/intel_gmbus.c: note: in included file (through drivers/gpu/drm/i915/display/intel_display_types.h):
+drivers/gpu/drm/i915/display/intel_hdcp.c: note: in included file (through drivers/gpu/drm/i915/display/intel_display_types.h):
+drivers/gpu/drm/i915/display/intel_hdcp_gsc_message.c: note: in included file (through drivers/gpu/drm/i915/display/intel_display_types.h):
+drivers/gpu/drm/i915/display/intel_hdmi.c: note: in included file (through drivers/gpu/drm/i915/display/intel_display_types.h):
+drivers/gpu/drm/i915/display/intel_hotplug.c: note: in included file (through drivers/gpu/drm/i915/display/intel_display_types.h):
+drivers/gpu/drm/i915/display/intel_hotplug_irq.c: note: in included file (through drivers/gpu/drm/i915/display/intel_display_types.h):
+drivers/gpu/drm/i915/display/intel_initial_plane.c: note: in included file (through drivers/gpu/drm/i915/display/intel_display_types.h):
+drivers/gpu/drm/i915/display/intel_link_bw.c: note: in included file (through drivers/gpu/drm/i915/display/intel_display_types.h):
+drivers/gpu/drm/i915/display/intel_load_detect.c: note: in included file (through drivers/gpu/drm/i915/display/intel_display_types.h):
+drivers/gpu/drm/i915/display/intel_lspcon.c: note: in included file (through drivers/gpu/drm/i915/display/intel_display_types.h):
+drivers/gpu/drm/i915/display/intel_lt_phy.c: note: in included file (through drivers/gpu/drm/i915/display/intel_display_types.h):
+drivers/gpu/drm/i915/display/intel_lvds.c: note: in included file (through drivers/gpu/drm/i915/display/intel_display_types.h):
+drivers/gpu/drm/i915/display/intel_modeset_lock.c: note: in included file (through drivers/gpu/drm/i915/display/intel_display_types.h):
+drivers/gpu/drm/i915/display/intel_modeset_verify.c: note: in included file (through drivers/gpu/drm/i915/display/intel_display_types.h):
+drivers/gpu/drm/i915/display/intel_opregion.c: note: in included file (through drivers/gpu/drm/i915/display/intel_display_types.h):
+drivers/gpu/drm/i915/display/intel_overlay.c: note: in included file (through drivers/gpu/drm/i915/display/intel_display_types.h):
+drivers/gpu/drm/i915/display/intel_panel.c: note: in included file:
+drivers/gpu/drm/i915/display/intel_pch_display.c: note: in included file (through drivers/gpu/drm/i915/display/intel_display_types.h):
+drivers/gpu/drm/i915/display/intel_pch_refclk.c: note: in included file (through drivers/gpu/drm/i915/display/intel_display_types.h):
+drivers/gpu/drm/i915/display/intel_pfit.c: note: in included file (through drivers/gpu/drm/i915/display/intel_display_types.h):
+drivers/gpu/drm/i915/display/intel_pipe_crc.c: note: in included file (through drivers/gpu/drm/i915/display/intel_display_types.h):
+drivers/gpu/drm/i915/display/intel_plane.c: note: in included file (through drivers/gpu/drm/i915/display/intel_display_types.h, drivers/gpu/drm/i915/display/intel_display_trace.h):
+drivers/gpu/drm/i915/display/intel_pmdemand.c: note: in included file (through drivers/gpu/drm/i915/display/intel_display_types.h, drivers/gpu/drm/i915/display/intel_display_trace.h):
+drivers/gpu/drm/i915/display/intel_pps.c: note: in included file (through drivers/gpu/drm/i915/display/intel_display_types.h):
+drivers/gpu/drm/i915/display/intel_psr.c: note: in included file (through drivers/gpu/drm/i915/display/intel_display_types.h):
+drivers/gpu/drm/i915/display/intel_quirks.c: note: in included file (through drivers/gpu/drm/i915/display/intel_display_types.h)drivers/gpu/drm/i915/display/intel_modeset_setup.c: note: in included file (through drivers/gpu/drm/i915/display/intel_display_types.h):
+drivers/gpu/drm/i915/display/intel_sdvo.c: note: in included file (through drivers/gpu/drm/i915/display/intel_display_types.h):
+drivers/gpu/drm/i915/display/intel_snps_hdmi_pll.c: note: in included file (through drivers/gpu/drm/i915/display/intel_display_types.h):
+drivers/gpu/drm/i915/display/intel_snps_phy.c: note: in included file (through drivers/gpu/drm/i915/display/intel_display_types.h):
+drivers/gpu/drm/i915/display/intel_sprite.c: note: in included file (through drivers/gpu/drm/i915/display/intel_display_types.h):
+drivers/gpu/drm/i915/display/intel_sprite_uapi.c: note: in included file (through drivers/gpu/drm/i915/display/intel_display_types.h):
+drivers/gpu/drm/i915/display/intel_tc.c: note: in included file (through drivers/gpu/drm/i915/display/intel_display_types.h):
+drivers/gpu/drm/i915/display/intel_tv.c: note: in included file (through drivers/gpu/drm/i915/display/intel_display_types.h):
+drivers/gpu/drm/i915/display/intel_vblank.c: note: in included file (through drivers/gpu/drm/i915/display/intel_display_types.h):
+drivers/gpu/drm/i915/display/intel_vdsc.c: note: in included file (through drivers/gpu/drm/i915/display/intel_display_types.h):
+drivers/gpu/drm/i915/display/intel_vga.c: note: in included file (through drivers/gpu/drm/i915/display/intel_display_types.h):
+drivers/gpu/drm/i915/display/intel_wm.c: note: in included file (through drivers/gpu/drm/i915/display/intel_display_types.h):
+drivers/gpu/drm/i915/display/skl_prefill.c: note: in included file (through drivers/gpu/drm/i915/display/intel_display_types.h):
+drivers/gpu/drm/i915/display/skl_scaler.c: note: in included file (through drivers/gpu/drm/i915/display/intel_display_types.h, drivers/gpu/drm/i915/display/intel_display_trace.h):
+drivers/gpu/drm/i915/display/skl_universal_plane.c: note: in included file (through drivers/gpu/drm/i915/display/intel_display_types.h):
+drivers/gpu/drm/i915/display/skl_watermark.c: note: in included file (through drivers/gpu/drm/i915/display/intel_display_types.h):
+drivers/gpu/drm/i915/display/vlv_clock.c: note: in included file (through drivers/gpu/drm/i915/display/intel_display_types.h):
+drivers/gpu/drm/i915/display/vlv_dsi.c: note: in included file (through drivers/gpu/drm/i915/display/intel_display_types.h):
+drivers/gpu/drm/i915/display/vlv_dsi_pll.c: note: in included file (through drivers/gpu/drm/i915/display/intel_display_types.h):
+drivers/gpu/drm/i915/display/vlv_sideband.c: note: in included file (through drivers/gpu/drm/i915/display/intel_display_types.h):
+drivers/gpu/drm/i915/gem/i915_gem_pages.c: note: in included file (through drivers/gpu/drm/i915/display/intel_display_types.h):
+drivers/gpu/drm/i915/i915_initial_plane.c: note: in included file (through drivers/gpu/drm/i915/display/intel_display_types.h):
+drivers/gpu/drm/i915/i915_panic.c: note: in included file (through drivers/gpu/drm/i915/display/intel_display_types.h):
+drivers/gpu/drm/i915/intel_uncore.c:1930:1: warning: context imbalance in 'fwtable_read8' - unexpected unlock
+drivers/gpu/drm/i915/intel_uncore.c:1931:1: warning: context imbalance in 'fwtable_read16' - unexpected unlock
+drivers/gpu/drm/i915/intel_uncore.c:1932:1: warning: context imbalance in 'fwtable_read32' - unexpected unlock
+drivers/gpu/drm/i915/intel_uncore.c:1933:1: warning: context imbalance in 'fwtable_read64' - unexpected unlock
+drivers/gpu/drm/i915/intel_uncore.c:1998:1: warning: context imbalance in 'gen6_write8' - unexpected unlock
+drivers/gpu/drm/i915/intel_uncore.c:1999:1: warning: context imbalance in 'gen6_write16' - unexpected unlock
+drivers/gpu/drm/i915/intel_uncore.c:2000:1: warning: context imbalance in 'gen6_write32' - unexpected unlock
+drivers/gpu/drm/i915/intel_uncore.c:2020:1: warning: context imbalance in 'fwtable_write8' - unexpected unlock
+drivers/gpu/drm/i915/intel_uncore.c:2021:1: warning: context imbalance in 'fwtable_write16' - unexpected unlock
+drivers/gpu/drm/i915/intel_uncore.c:2022:1: warning: context imbalance in 'fwtable_write32' - unexpected unlock
+./include/linux/pwm.h:13:1: error: bad constant expression
+./include/linux/pwm.h:13:1: error: bad constant expression
+./include/linux/pwm.h:13:1: error: bad constant expression
+./include/linux/pwm.h:13:1: error: bad constant expression
+./include/linux/pwm.h:13:1: error: bad constant expression
+./include/linux/pwm.h:13:1: error: bad constant expression
+./include/linux/pwm.h:13:1: error: bad constant expression
+./include/linux/pwm.h:13:1: error: bad constant expression
+./include/linux/pwm.h:13:1: error: bad constant expression
+./include/linux/pwm.h:13:1: error: bad constant expression
+./include/linux/pwm.h:13:1: error: bad constant expression
+./include/linux/pwm.h:13:1: error: bad constant expression
+./include/linux/pwm.h:13:1: error: bad constant expression
+./include/linux/pwm.h:13:1: error: bad constant expression
+./include/linux/pwm.h:13:1: error: bad constant expression
+./include/linux/pwm.h:13:1: error: bad constant expression
+./include/linux/pwm.h:13:1: error: bad constant expression
+./include/linux/pwm.h:13:1: error: bad constant expression
+./include/linux/pwm.h:13:1: error: bad constant expression
+./include/linux/pwm.h:13:1: error: bad constant expression
+./include/linux/pwm.h:13:1: error: bad constant expression
+./include/linux/pwm.h:13:1: error: bad constant expression
+./include/linux/pwm.h:13:1: error: bad constant expression
+./include/linux/pwm.h:13:1: error: bad constant expression
+./include/linux/pwm.h:13:1: error: bad constant expression
+./include/linux/pwm.h:13:1: error: bad constant expression
+./include/linux/pwm.h:13:1: error: bad constant expression
+./include/linux/pwm.h:13:1: error: bad constant expression
+./include/linux/pwm.h:13:1: error: bad constant expression
+./include/linux/pwm.h:13:1: error: bad constant expression
+./include/linux/pwm.h:13:1: error: bad constant expression
+./include/linux/pwm.h:13:1: error: bad constant expression
+./include/linux/pwm.h:13:1: error: bad constant expression
+./include/linux/pwm.h:13:1: error: bad constant expression
+./include/linux/pwm.h:13:1: error: bad constant expression
+./include/linux/pwm.h:13:1: error: bad constant expression
+./include/linux/pwm.h:13:1: error: bad constant expression
+./include/linux/pwm.h:13:1: error: bad constant expression
+./include/linux/pwm.h:13:1: error: bad constant expression
+./include/linux/pwm.h:13:1: error: bad constant expression
+./include/linux/pwm.h:13:1: error: bad constant expression
+./include/linux/pwm.h:13:1: error: bad constant expression
+./include/linux/pwm.h:13:1: error: bad constant expression
+./include/linux/pwm.h:13:1: error: bad constant expression
+./include/linux/pwm.h:13:1: error: bad constant expression
+./include/linux/pwm.h:13:1: error: bad constant expression
+./include/linux/pwm.h:13:1: error: bad constant expression
+./include/linux/pwm.h:13:1: error: bad constant expression
+./include/linux/pwm.h:13:1: error: bad constant expression
+./include/linux/pwm.h:13:1: error: bad constant expression
+./include/linux/pwm.h:13:1: error: bad constant expression
+./include/linux/pwm.h:13:1: error: bad constant expression
+./include/linux/pwm.h:13:1: error: bad constant expression
+./include/linux/pwm.h:13:1: error: bad constant expression
+./include/linux/pwm.h:13:1: error: bad constant expression
+./include/linux/pwm.h:13:1: error: bad constant expression
+./include/linux/pwm.h:13:1: error: bad constant expression
+./include/linux/pwm.h:13:1: error: bad constant expression
+./include/linux/pwm.h:13:1: error: bad constant expression
+./include/linux/pwm.h:13:1: error: bad constant expression
+./include/linux/pwm.h:13:1: error: bad constant expression
+./include/linux/pwm.h:13:1: error: bad constant expression
+./include/linux/pwm.h:13:1: error: bad constant expression
+./include/linux/pwm.h:13:1: error: bad constant expression
+./include/linux/pwm.h:13:1: error: bad constant expression
+./include/linux/pwm.h:13:1: error: bad constant expression
+./include/linux/pwm.h:13:1: error: bad constant expression
+./include/linux/pwm.h:13:1: error: bad constant expression
+./include/linux/pwm.h:13:1: error: bad constant expression
+./include/linux/pwm.h:13:1: error: bad constant expression
+./include/linux/pwm.h:13:1: error: bad constant expression
+./include/linux/pwm.h:13:1: error: bad constant expression
+./include/linux/pwm.h:13:1: error: bad constant expression
+./include/linux/pwm.h:13:1: error: bad constant expression
+./include/linux/pwm.h:13:1: error: bad constant expression
+./include/linux/pwm.h:13:1: error: bad constant expression
+./include/linux/pwm.h:13:1: error: bad constant expression
+./include/linux/pwm.h:13:1: error: bad constant expression
+./include/linux/pwm.h:13:1: error: bad constant expression
+./include/linux/pwm.h:13:1: error: bad constant expression
+./include/linux/pwm.h:13:1: error: bad constant expression
+./include/linux/pwm.h:13:1: error: bad constant expression
+./include/linux/pwm.h:13:1: error: bad constant expression
+./include/linux/pwm.h:13:1: error: bad constant expression
+./include/linux/pwm.h:13:1: error: bad constant expression
+./include/linux/pwm.h:13:1: error: bad constant expression
+./include/linux/pwm.h:13:1: error: bad constant expression
+./include/linux/pwm.h:13:1: error: bad constant expression
+./include/linux/pwm.h:13:1: error: bad constant expression
+./include/linux/pwm.h:13:1: error: bad constant expression
+./include/linux/pwm.h:13:1: error: bad constant expression
+./include/linux/pwm.h:13:1: error: bad constant expression
+./include/linux/pwm.h:13:1: error: bad constant expression
+./include/linux/pwm.h:13:1: error: bad constant expression
+./include/linux/pwm.h:13:1: error: bad constant expression
+./include/linux/pwm.h:13:1: error: bad constant expression
+./include/linux/pwm.h:13:1: error: bad constant expression
+./include/linux/pwm.h:13:1: error: bad constant expression
+./include/linux/pwm.h:13:1: error: bad constant expression
+./include/linux/pwm.h:13:1: error: bad constant expression
+./include/linux/pwm.h:13:1: error: bad constant expression
+./include/linux/pwm.h:13:1: error: bad constant expression
+./include/linux/pwm.h:13:1: error: bad constant expression
+./include/linux/pwm.h:13:1: error: bad constant expression
+./include/linux/pwm.h:13:1: error: bad constant expression
+./include/linux/pwm.h:13:1: error: bad constant expression
+./include/linux/pwm.h:13:1: error: bad constant expression
+./include/linux/pwm.h:13:1: error: bad constant expression
+./include/linux/pwm.h:13:1: error: bad constant expression
+./include/linux/pwm.h:13:1: error: bad constant expression
+./include/linux/pwm.h:13:1: error: bad constant expression
+./include/linux/pwm.h:13:1: error: bad constant expression
+./include/linux/pwm.h:13:1: error: bad constant expression
+./include/linux/pwm.h:13:1: error: bad constant expression
+./include/linux/pwm.h:13:1: error: bad constant expression
+./include/linux/pwm.h:13:1: error: bad constant expression
+./include/linux/pwm.h:13:1: error: bad constant expression
+./include/linux/pwm.h:13:1: error: bad constant expression
+./include/linux/pwm.h:13:1: error: bad constant expression
+./include/linux/pwm.h:13:1: error: bad constant expression
+./include/linux/pwm.h:13:1: error: bad constant expression
+./include/linux/pwm.h:13:1: error: bad constant expression

+ cleanup
++ stat -c %u:%g /kernel
+ chown -R 1003:1003 /kernel

✓ Xe.CI.BAT: success for Enable/Disable DC balance along with VRR DSB

[Patchwork]

[-- Attachment #1: Type: text/plain, Size: 1503 bytes --]

== Series Details ==

Series: Enable/Disable DC balance along with VRR DSB
URL   : https://patchwork.freedesktop.org/series/159419/
State : success

== Summary ==

CI Bug Log - changes from xe-4296-cab246648fd89efbe8d20ed4c86e7fcebd7606da_BAT -> xe-pw-159419v1_BAT
====================================================

Summary
-------

  **SUCCESS**

  No regressions found.

  

Participating hosts (12 -> 12)
------------------------------

  No changes in participating hosts

Known issues
------------

  Here are the changes found in xe-pw-159419v1_BAT that come from known issues:

### IGT changes ###

#### Possible fixes ####

  * igt@xe_waitfence@reltime:
    - bat-dg2-oem2:       [FAIL][1] ([Intel XE#6520]) -> [PASS][2]
   [1]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4296-cab246648fd89efbe8d20ed4c86e7fcebd7606da/bat-dg2-oem2/igt@xe_waitfence@reltime.html
   [2]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159419v1/bat-dg2-oem2/igt@xe_waitfence@reltime.html

  
  [Intel XE#6520]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6520


Build changes
-------------

  * Linux: xe-4296-cab246648fd89efbe8d20ed4c86e7fcebd7606da -> xe-pw-159419v1

  IGT_8674: f38f4d8e9c65aff45ac807e646d06e38bc3193a2 @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
  xe-4296-cab246648fd89efbe8d20ed4c86e7fcebd7606da: cab246648fd89efbe8d20ed4c86e7fcebd7606da
  xe-pw-159419v1: 159419v1

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159419v1/index.html

[-- Attachment #2: Type: text/html, Size: 2068 bytes --]

✗ Xe.CI.Full: failure for Enable/Disable DC balance along with VRR DSB

[Patchwork]

[-- Attachment #1: Type: text/plain, Size: 44456 bytes --]

== Series Details ==

Series: Enable/Disable DC balance along with VRR DSB
URL   : https://patchwork.freedesktop.org/series/159419/
State : failure

== Summary ==

CI Bug Log - changes from xe-4296-cab246648fd89efbe8d20ed4c86e7fcebd7606da_FULL -> xe-pw-159419v1_FULL
====================================================

Summary
-------

  **FAILURE**

  Serious unknown changes coming with xe-pw-159419v1_FULL absolutely need to be
  verified manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in xe-pw-159419v1_FULL, please notify your bug team (I915-ci-infra@lists.freedesktop.org) to allow them
  to document this new failure mode, which will reduce false positives in CI.

  

Participating hosts (2 -> 2)
------------------------------

  No changes in participating hosts

Possible new issues
-------------------

  Here are the unknown changes that may have been introduced in xe-pw-159419v1_FULL:

### IGT changes ###

#### Possible regressions ####

  * igt@xe_exec_reset@parallel-close-fd:
    - shard-bmg:          [PASS][1] -> [DMESG-WARN][2]
   [1]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4296-cab246648fd89efbe8d20ed4c86e7fcebd7606da/shard-bmg-2/igt@xe_exec_reset@parallel-close-fd.html
   [2]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159419v1/shard-bmg-2/igt@xe_exec_reset@parallel-close-fd.html

  * igt@xe_exec_system_allocator@threads-shared-vm-many-large-execqueues-mmap-new-race:
    - shard-bmg:          [PASS][3] -> [ABORT][4]
   [3]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4296-cab246648fd89efbe8d20ed4c86e7fcebd7606da/shard-bmg-2/igt@xe_exec_system_allocator@threads-shared-vm-many-large-execqueues-mmap-new-race.html
   [4]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159419v1/shard-bmg-2/igt@xe_exec_system_allocator@threads-shared-vm-many-large-execqueues-mmap-new-race.html

  
Known issues
------------

  Here are the changes found in xe-pw-159419v1_FULL that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@kms_big_fb@yf-tiled-8bpp-rotate-0:
    - shard-bmg:          NOTRUN -> [SKIP][5] ([Intel XE#1124]) +5 other tests skip
   [5]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159419v1/shard-bmg-1/igt@kms_big_fb@yf-tiled-8bpp-rotate-0.html

  * igt@kms_bw@linear-tiling-1-displays-2160x1440p:
    - shard-bmg:          NOTRUN -> [SKIP][6] ([Intel XE#367])
   [6]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159419v1/shard-bmg-1/igt@kms_bw@linear-tiling-1-displays-2160x1440p.html

  * igt@kms_ccs@bad-aux-stride-y-tiled-gen12-rc-ccs-cc:
    - shard-bmg:          NOTRUN -> [SKIP][7] ([Intel XE#2887]) +3 other tests skip
   [7]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159419v1/shard-bmg-1/igt@kms_ccs@bad-aux-stride-y-tiled-gen12-rc-ccs-cc.html

  * igt@kms_ccs@random-ccs-data-4-tiled-lnl-ccs@pipe-c-dp-2:
    - shard-bmg:          NOTRUN -> [SKIP][8] ([Intel XE#2652] / [Intel XE#787]) +7 other tests skip
   [8]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159419v1/shard-bmg-1/igt@kms_ccs@random-ccs-data-4-tiled-lnl-ccs@pipe-c-dp-2.html

  * igt@kms_cdclk@plane-scaling:
    - shard-bmg:          NOTRUN -> [SKIP][9] ([Intel XE#2724])
   [9]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159419v1/shard-bmg-1/igt@kms_cdclk@plane-scaling.html

  * igt@kms_chamelium_hpd@hdmi-hpd-fast:
    - shard-bmg:          NOTRUN -> [SKIP][10] ([Intel XE#2252]) +1 other test skip
   [10]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159419v1/shard-bmg-1/igt@kms_chamelium_hpd@hdmi-hpd-fast.html

  * igt@kms_content_protection@dp-mst-type-0:
    - shard-bmg:          NOTRUN -> [SKIP][11] ([Intel XE#2390])
   [11]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159419v1/shard-bmg-1/igt@kms_content_protection@dp-mst-type-0.html

  * igt@kms_content_protection@suspend-resume@pipe-a-dp-2:
    - shard-bmg:          NOTRUN -> [FAIL][12] ([Intel XE#1178]) +1 other test fail
   [12]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159419v1/shard-bmg-4/igt@kms_content_protection@suspend-resume@pipe-a-dp-2.html

  * igt@kms_cursor_crc@cursor-onscreen-512x170:
    - shard-bmg:          NOTRUN -> [SKIP][13] ([Intel XE#2321])
   [13]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159419v1/shard-bmg-4/igt@kms_cursor_crc@cursor-onscreen-512x170.html

  * igt@kms_cursor_crc@cursor-onscreen-max-size:
    - shard-bmg:          NOTRUN -> [SKIP][14] ([Intel XE#2320]) +1 other test skip
   [14]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159419v1/shard-bmg-1/igt@kms_cursor_crc@cursor-onscreen-max-size.html

  * igt@kms_cursor_legacy@2x-long-flip-vs-cursor-atomic:
    - shard-bmg:          NOTRUN -> [SKIP][15] ([Intel XE#2291])
   [15]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159419v1/shard-bmg-4/igt@kms_cursor_legacy@2x-long-flip-vs-cursor-atomic.html

  * igt@kms_cursor_legacy@cursora-vs-flipb-atomic-transitions:
    - shard-bmg:          [PASS][16] -> [SKIP][17] ([Intel XE#2291])
   [16]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4296-cab246648fd89efbe8d20ed4c86e7fcebd7606da/shard-bmg-10/igt@kms_cursor_legacy@cursora-vs-flipb-atomic-transitions.html
   [17]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159419v1/shard-bmg-4/igt@kms_cursor_legacy@cursora-vs-flipb-atomic-transitions.html

  * igt@kms_dirtyfb@drrs-dirtyfb-ioctl:
    - shard-bmg:          NOTRUN -> [SKIP][18] ([Intel XE#1508])
   [18]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159419v1/shard-bmg-4/igt@kms_dirtyfb@drrs-dirtyfb-ioctl.html

  * igt@kms_dp_link_training@non-uhbr-mst:
    - shard-bmg:          NOTRUN -> [SKIP][19] ([Intel XE#4354])
   [19]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159419v1/shard-bmg-1/igt@kms_dp_link_training@non-uhbr-mst.html

  * igt@kms_fbc_dirty_rect@fbc-dirty-rectangle-dirtyfb-tests:
    - shard-bmg:          NOTRUN -> [SKIP][20] ([Intel XE#4422])
   [20]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159419v1/shard-bmg-4/igt@kms_fbc_dirty_rect@fbc-dirty-rectangle-dirtyfb-tests.html

  * igt@kms_fbcon_fbt@psr-suspend:
    - shard-bmg:          NOTRUN -> [SKIP][21] ([Intel XE#776])
   [21]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159419v1/shard-bmg-1/igt@kms_fbcon_fbt@psr-suspend.html

  * igt@kms_feature_discovery@display-3x:
    - shard-bmg:          NOTRUN -> [SKIP][22] ([Intel XE#2373])
   [22]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159419v1/shard-bmg-4/igt@kms_feature_discovery@display-3x.html

  * igt@kms_feature_discovery@psr2:
    - shard-bmg:          NOTRUN -> [SKIP][23] ([Intel XE#2374])
   [23]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159419v1/shard-bmg-1/igt@kms_feature_discovery@psr2.html

  * igt@kms_flip@2x-nonexisting-fb:
    - shard-bmg:          [PASS][24] -> [SKIP][25] ([Intel XE#2316]) +5 other tests skip
   [24]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4296-cab246648fd89efbe8d20ed4c86e7fcebd7606da/shard-bmg-8/igt@kms_flip@2x-nonexisting-fb.html
   [25]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159419v1/shard-bmg-4/igt@kms_flip@2x-nonexisting-fb.html

  * igt@kms_flip@flip-vs-expired-vblank-interruptible@b-edp1:
    - shard-lnl:          [PASS][26] -> [FAIL][27] ([Intel XE#301])
   [26]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4296-cab246648fd89efbe8d20ed4c86e7fcebd7606da/shard-lnl-2/igt@kms_flip@flip-vs-expired-vblank-interruptible@b-edp1.html
   [27]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159419v1/shard-lnl-7/igt@kms_flip@flip-vs-expired-vblank-interruptible@b-edp1.html

  * igt@kms_flip@flip-vs-expired-vblank@c-dp2:
    - shard-bmg:          [PASS][28] -> [FAIL][29] ([Intel XE#3321]) +1 other test fail
   [28]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4296-cab246648fd89efbe8d20ed4c86e7fcebd7606da/shard-bmg-10/igt@kms_flip@flip-vs-expired-vblank@c-dp2.html
   [29]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159419v1/shard-bmg-4/igt@kms_flip@flip-vs-expired-vblank@c-dp2.html

  * igt@kms_flip_scaled_crc@flip-32bpp-yftile-to-32bpp-yftileccs-upscaling:
    - shard-bmg:          NOTRUN -> [SKIP][30] ([Intel XE#2293] / [Intel XE#2380])
   [30]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159419v1/shard-bmg-1/igt@kms_flip_scaled_crc@flip-32bpp-yftile-to-32bpp-yftileccs-upscaling.html

  * igt@kms_flip_scaled_crc@flip-32bpp-yftile-to-32bpp-yftileccs-upscaling@pipe-a-valid-mode:
    - shard-bmg:          NOTRUN -> [SKIP][31] ([Intel XE#2293]) +1 other test skip
   [31]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159419v1/shard-bmg-1/igt@kms_flip_scaled_crc@flip-32bpp-yftile-to-32bpp-yftileccs-upscaling@pipe-a-valid-mode.html

  * igt@kms_frontbuffer_tracking@drrs-rgb565-draw-render:
    - shard-bmg:          NOTRUN -> [SKIP][32] ([Intel XE#2311]) +6 other tests skip
   [32]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159419v1/shard-bmg-1/igt@kms_frontbuffer_tracking@drrs-rgb565-draw-render.html

  * igt@kms_frontbuffer_tracking@fbc-1p-pri-indfb-multidraw:
    - shard-bmg:          NOTRUN -> [SKIP][33] ([Intel XE#4141]) +2 other tests skip
   [33]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159419v1/shard-bmg-1/igt@kms_frontbuffer_tracking@fbc-1p-pri-indfb-multidraw.html

  * igt@kms_frontbuffer_tracking@psr-1p-primscrn-indfb-msflip-blt:
    - shard-bmg:          NOTRUN -> [SKIP][34] ([Intel XE#2313]) +7 other tests skip
   [34]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159419v1/shard-bmg-1/igt@kms_frontbuffer_tracking@psr-1p-primscrn-indfb-msflip-blt.html

  * igt@kms_frontbuffer_tracking@psr-2p-primscrn-spr-indfb-fullscreen:
    - shard-bmg:          NOTRUN -> [SKIP][35] ([Intel XE#2312]) +5 other tests skip
   [35]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159419v1/shard-bmg-4/igt@kms_frontbuffer_tracking@psr-2p-primscrn-spr-indfb-fullscreen.html

  * igt@kms_hdr@bpc-switch-dpms@pipe-a-dp-2:
    - shard-bmg:          [PASS][36] -> [ABORT][37] ([Intel XE#6740]) +3 other tests abort
   [36]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4296-cab246648fd89efbe8d20ed4c86e7fcebd7606da/shard-bmg-4/igt@kms_hdr@bpc-switch-dpms@pipe-a-dp-2.html
   [37]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159419v1/shard-bmg-7/igt@kms_hdr@bpc-switch-dpms@pipe-a-dp-2.html

  * igt@kms_hdr@invalid-hdr@pipe-a-hdmi-a-3:
    - shard-bmg:          NOTRUN -> [ABORT][38] ([Intel XE#6740])
   [38]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159419v1/shard-bmg-3/igt@kms_hdr@invalid-hdr@pipe-a-hdmi-a-3.html

  * igt@kms_plane_lowres@tiling-y:
    - shard-bmg:          NOTRUN -> [SKIP][39] ([Intel XE#2393])
   [39]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159419v1/shard-bmg-1/igt@kms_plane_lowres@tiling-y.html

  * igt@kms_plane_multiple@2x-tiling-none:
    - shard-bmg:          [PASS][40] -> [SKIP][41] ([Intel XE#4596])
   [40]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4296-cab246648fd89efbe8d20ed4c86e7fcebd7606da/shard-bmg-10/igt@kms_plane_multiple@2x-tiling-none.html
   [41]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159419v1/shard-bmg-4/igt@kms_plane_multiple@2x-tiling-none.html

  * igt@kms_pm_backlight@brightness-with-dpms:
    - shard-bmg:          NOTRUN -> [SKIP][42] ([Intel XE#2938])
   [42]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159419v1/shard-bmg-1/igt@kms_pm_backlight@brightness-with-dpms.html

  * igt@kms_psr2_sf@fbc-pr-overlay-primary-update-sf-dmg-area:
    - shard-bmg:          NOTRUN -> [SKIP][43] ([Intel XE#1406] / [Intel XE#1489]) +2 other tests skip
   [43]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159419v1/shard-bmg-4/igt@kms_psr2_sf@fbc-pr-overlay-primary-update-sf-dmg-area.html

  * igt@kms_psr@psr-primary-page-flip:
    - shard-bmg:          NOTRUN -> [SKIP][44] ([Intel XE#1406] / [Intel XE#2234] / [Intel XE#2850]) +6 other tests skip
   [44]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159419v1/shard-bmg-1/igt@kms_psr@psr-primary-page-flip.html

  * igt@kms_rotation_crc@primary-yf-tiled-reflect-x-0:
    - shard-bmg:          NOTRUN -> [SKIP][45] ([Intel XE#2330])
   [45]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159419v1/shard-bmg-4/igt@kms_rotation_crc@primary-yf-tiled-reflect-x-0.html

  * igt@kms_sharpness_filter@filter-dpms:
    - shard-bmg:          NOTRUN -> [SKIP][46] ([Intel XE#6503]) +1 other test skip
   [46]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159419v1/shard-bmg-4/igt@kms_sharpness_filter@filter-dpms.html

  * igt@xe_eudebug@basic-vm-access-userptr:
    - shard-bmg:          NOTRUN -> [SKIP][47] ([Intel XE#4837]) +2 other tests skip
   [47]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159419v1/shard-bmg-1/igt@xe_eudebug@basic-vm-access-userptr.html

  * igt@xe_eudebug_online@pagefault-write:
    - shard-bmg:          NOTRUN -> [SKIP][48] ([Intel XE#4837] / [Intel XE#6665]) +1 other test skip
   [48]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159419v1/shard-bmg-4/igt@xe_eudebug_online@pagefault-write.html

  * igt@xe_evict@evict-mixed-many-threads-small:
    - shard-bmg:          [PASS][49] -> [INCOMPLETE][50] ([Intel XE#6321])
   [49]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4296-cab246648fd89efbe8d20ed4c86e7fcebd7606da/shard-bmg-2/igt@xe_evict@evict-mixed-many-threads-small.html
   [50]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159419v1/shard-bmg-10/igt@xe_evict@evict-mixed-many-threads-small.html

  * igt@xe_exec_basic@multigpu-once-bindexecqueue-userptr-rebind:
    - shard-bmg:          NOTRUN -> [SKIP][51] ([Intel XE#2322]) +2 other tests skip
   [51]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159419v1/shard-bmg-1/igt@xe_exec_basic@multigpu-once-bindexecqueue-userptr-rebind.html

  * igt@xe_exec_multi_queue@many-execs-close-fd-smem:
    - shard-bmg:          NOTRUN -> [SKIP][52] ([Intel XE#6874]) +7 other tests skip
   [52]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159419v1/shard-bmg-1/igt@xe_exec_multi_queue@many-execs-close-fd-smem.html

  * igt@xe_exec_system_allocator@many-64k-mmap-free-huge-nomemset:
    - shard-bmg:          NOTRUN -> [SKIP][53] ([Intel XE#5007])
   [53]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159419v1/shard-bmg-4/igt@xe_exec_system_allocator@many-64k-mmap-free-huge-nomemset.html

  * igt@xe_exec_system_allocator@process-many-stride-mmap-file:
    - shard-bmg:          [PASS][54] -> [DMESG-FAIL][55] ([Intel XE#5213])
   [54]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4296-cab246648fd89efbe8d20ed4c86e7fcebd7606da/shard-bmg-2/igt@xe_exec_system_allocator@process-many-stride-mmap-file.html
   [55]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159419v1/shard-bmg-2/igt@xe_exec_system_allocator@process-many-stride-mmap-file.html

  * igt@xe_exec_system_allocator@threads-many-mmap-free-huge-nomemset:
    - shard-bmg:          NOTRUN -> [SKIP][56] ([Intel XE#4943]) +7 other tests skip
   [56]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159419v1/shard-bmg-4/igt@xe_exec_system_allocator@threads-many-mmap-free-huge-nomemset.html

  * igt@xe_fault_injection@exec-queue-create-fail-xe_pxp_exec_queue_add:
    - shard-bmg:          NOTRUN -> [SKIP][57] ([Intel XE#6281])
   [57]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159419v1/shard-bmg-1/igt@xe_fault_injection@exec-queue-create-fail-xe_pxp_exec_queue_add.html

  * igt@xe_pm@d3hot-i2c:
    - shard-bmg:          NOTRUN -> [SKIP][58] ([Intel XE#5742])
   [58]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159419v1/shard-bmg-1/igt@xe_pm@d3hot-i2c.html

  * igt@xe_pmu@engine-activity-accuracy-90@engine-drm_xe_engine_class_video_enhance0:
    - shard-lnl:          [PASS][59] -> [FAIL][60] ([Intel XE#6251]) +1 other test fail
   [59]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4296-cab246648fd89efbe8d20ed4c86e7fcebd7606da/shard-lnl-7/igt@xe_pmu@engine-activity-accuracy-90@engine-drm_xe_engine_class_video_enhance0.html
   [60]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159419v1/shard-lnl-2/igt@xe_pmu@engine-activity-accuracy-90@engine-drm_xe_engine_class_video_enhance0.html

  * igt@xe_pxp@pxp-stale-bo-exec-post-termination-irq:
    - shard-bmg:          NOTRUN -> [SKIP][61] ([Intel XE#4733]) +1 other test skip
   [61]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159419v1/shard-bmg-4/igt@xe_pxp@pxp-stale-bo-exec-post-termination-irq.html

  * igt@xe_query@multigpu-query-uc-fw-version-huc:
    - shard-bmg:          NOTRUN -> [SKIP][62] ([Intel XE#944])
   [62]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159419v1/shard-bmg-1/igt@xe_query@multigpu-query-uc-fw-version-huc.html

  
#### Possible fixes ####

  * igt@intel_hwmon@hwmon-read:
    - shard-bmg:          [SKIP][63] ([Intel XE#5177] / [Intel XE#6703]) -> [PASS][64]
   [63]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4296-cab246648fd89efbe8d20ed4c86e7fcebd7606da/shard-bmg-2/igt@intel_hwmon@hwmon-read.html
   [64]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159419v1/shard-bmg-1/igt@intel_hwmon@hwmon-read.html

  * igt@kms_atomic_transition@plane-all-transition-fencing:
    - shard-bmg:          [INCOMPLETE][65] ([Intel XE#1727] / [Intel XE#6819]) -> [PASS][66]
   [65]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4296-cab246648fd89efbe8d20ed4c86e7fcebd7606da/shard-bmg-3/igt@kms_atomic_transition@plane-all-transition-fencing.html
   [66]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159419v1/shard-bmg-1/igt@kms_atomic_transition@plane-all-transition-fencing.html

  * igt@kms_atomic_transition@plane-all-transition-fencing@pipe-a-hdmi-a-3:
    - shard-bmg:          [DMESG-FAIL][67] ([Intel XE#1727] / [Intel XE#6819]) -> [PASS][68]
   [67]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4296-cab246648fd89efbe8d20ed4c86e7fcebd7606da/shard-bmg-3/igt@kms_atomic_transition@plane-all-transition-fencing@pipe-a-hdmi-a-3.html
   [68]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159419v1/shard-bmg-1/igt@kms_atomic_transition@plane-all-transition-fencing@pipe-a-hdmi-a-3.html

  * igt@kms_bw@connected-linear-tiling-2-displays-2160x1440p:
    - shard-bmg:          [SKIP][69] ([Intel XE#2314] / [Intel XE#2894]) -> [PASS][70]
   [69]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4296-cab246648fd89efbe8d20ed4c86e7fcebd7606da/shard-bmg-4/igt@kms_bw@connected-linear-tiling-2-displays-2160x1440p.html
   [70]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159419v1/shard-bmg-7/igt@kms_bw@connected-linear-tiling-2-displays-2160x1440p.html

  * igt@kms_cursor_legacy@cursorb-vs-flipb-legacy:
    - shard-bmg:          [SKIP][71] ([Intel XE#2291]) -> [PASS][72] +2 other tests pass
   [71]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4296-cab246648fd89efbe8d20ed4c86e7fcebd7606da/shard-bmg-4/igt@kms_cursor_legacy@cursorb-vs-flipb-legacy.html
   [72]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159419v1/shard-bmg-7/igt@kms_cursor_legacy@cursorb-vs-flipb-legacy.html

  * igt@kms_cursor_legacy@flip-vs-cursor-legacy:
    - shard-bmg:          [FAIL][73] ([Intel XE#5299]) -> [PASS][74]
   [73]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4296-cab246648fd89efbe8d20ed4c86e7fcebd7606da/shard-bmg-1/igt@kms_cursor_legacy@flip-vs-cursor-legacy.html
   [74]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159419v1/shard-bmg-8/igt@kms_cursor_legacy@flip-vs-cursor-legacy.html

  * igt@kms_flip@2x-blocking-absolute-wf_vblank:
    - shard-bmg:          [DMESG-WARN][75] -> [PASS][76] +1 other test pass
   [75]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4296-cab246648fd89efbe8d20ed4c86e7fcebd7606da/shard-bmg-2/igt@kms_flip@2x-blocking-absolute-wf_vblank.html
   [76]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159419v1/shard-bmg-1/igt@kms_flip@2x-blocking-absolute-wf_vblank.html

  * igt@kms_flip@2x-single-buffer-flip-vs-dpms-off-vs-modeset-interruptible:
    - shard-bmg:          [SKIP][77] ([Intel XE#2316]) -> [PASS][78] +4 other tests pass
   [77]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4296-cab246648fd89efbe8d20ed4c86e7fcebd7606da/shard-bmg-4/igt@kms_flip@2x-single-buffer-flip-vs-dpms-off-vs-modeset-interruptible.html
   [78]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159419v1/shard-bmg-7/igt@kms_flip@2x-single-buffer-flip-vs-dpms-off-vs-modeset-interruptible.html

  * igt@kms_flip@flip-vs-expired-vblank@c-edp1:
    - shard-lnl:          [FAIL][79] ([Intel XE#301] / [Intel XE#3149]) -> [PASS][80] +2 other tests pass
   [79]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4296-cab246648fd89efbe8d20ed4c86e7fcebd7606da/shard-lnl-5/igt@kms_flip@flip-vs-expired-vblank@c-edp1.html
   [80]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159419v1/shard-lnl-8/igt@kms_flip@flip-vs-expired-vblank@c-edp1.html

  * igt@kms_hdr@bpc-switch@pipe-a-dp-2:
    - shard-bmg:          [ABORT][81] ([Intel XE#6740]) -> [PASS][82] +1 other test pass
   [81]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4296-cab246648fd89efbe8d20ed4c86e7fcebd7606da/shard-bmg-8/igt@kms_hdr@bpc-switch@pipe-a-dp-2.html
   [82]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159419v1/shard-bmg-4/igt@kms_hdr@bpc-switch@pipe-a-dp-2.html

  * igt@kms_pm_rpm@basic-rte:
    - shard-bmg:          [SKIP][83] ([Intel XE#6693]) -> [PASS][84]
   [83]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4296-cab246648fd89efbe8d20ed4c86e7fcebd7606da/shard-bmg-2/igt@kms_pm_rpm@basic-rte.html
   [84]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159419v1/shard-bmg-1/igt@kms_pm_rpm@basic-rte.html

  * igt@xe_exec_balancer@twice-virtual-basic:
    - shard-bmg:          [SKIP][85] ([Intel XE#6557] / [Intel XE#6703]) -> [PASS][86] +2 other tests pass
   [85]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4296-cab246648fd89efbe8d20ed4c86e7fcebd7606da/shard-bmg-2/igt@xe_exec_balancer@twice-virtual-basic.html
   [86]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159419v1/shard-bmg-1/igt@xe_exec_balancer@twice-virtual-basic.html

  * igt@xe_exec_system_allocator@many-execqueues-mmap-race:
    - shard-bmg:          [SKIP][87] ([Intel XE#6703]) -> [PASS][88] +133 other tests pass
   [87]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4296-cab246648fd89efbe8d20ed4c86e7fcebd7606da/shard-bmg-2/igt@xe_exec_system_allocator@many-execqueues-mmap-race.html
   [88]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159419v1/shard-bmg-1/igt@xe_exec_system_allocator@many-execqueues-mmap-race.html

  * igt@xe_fault_injection@vm-bind-fail-vm_bind_ioctl_ops_execute:
    - shard-bmg:          [ABORT][89] -> [PASS][90]
   [89]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4296-cab246648fd89efbe8d20ed4c86e7fcebd7606da/shard-bmg-9/igt@xe_fault_injection@vm-bind-fail-vm_bind_ioctl_ops_execute.html
   [90]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159419v1/shard-bmg-4/igt@xe_fault_injection@vm-bind-fail-vm_bind_ioctl_ops_execute.html

  * igt@xe_live_ktest@xe_migrate@xe_migrate_sanity_kunit:
    - shard-bmg:          [FAIL][91] ([Intel XE#6558]) -> [PASS][92] +2 other tests pass
   [91]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4296-cab246648fd89efbe8d20ed4c86e7fcebd7606da/shard-bmg-2/igt@xe_live_ktest@xe_migrate@xe_migrate_sanity_kunit.html
   [92]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159419v1/shard-bmg-1/igt@xe_live_ktest@xe_migrate@xe_migrate_sanity_kunit.html

  
#### Warnings ####

  * igt@kms_big_fb@4-tiled-64bpp-rotate-270:
    - shard-bmg:          [SKIP][93] ([Intel XE#6703]) -> [SKIP][94] ([Intel XE#2327])
   [93]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4296-cab246648fd89efbe8d20ed4c86e7fcebd7606da/shard-bmg-2/igt@kms_big_fb@4-tiled-64bpp-rotate-270.html
   [94]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159419v1/shard-bmg-1/igt@kms_big_fb@4-tiled-64bpp-rotate-270.html

  * igt@kms_big_fb@y-tiled-max-hw-stride-64bpp-rotate-180-async-flip:
    - shard-bmg:          [SKIP][95] ([Intel XE#6703]) -> [SKIP][96] ([Intel XE#1124]) +2 other tests skip
   [95]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4296-cab246648fd89efbe8d20ed4c86e7fcebd7606da/shard-bmg-2/igt@kms_big_fb@y-tiled-max-hw-stride-64bpp-rotate-180-async-flip.html
   [96]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159419v1/shard-bmg-1/igt@kms_big_fb@y-tiled-max-hw-stride-64bpp-rotate-180-async-flip.html

  * igt@kms_bw@linear-tiling-3-displays-2160x1440p:
    - shard-bmg:          [SKIP][97] ([Intel XE#6703]) -> [SKIP][98] ([Intel XE#367])
   [97]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4296-cab246648fd89efbe8d20ed4c86e7fcebd7606da/shard-bmg-2/igt@kms_bw@linear-tiling-3-displays-2160x1440p.html
   [98]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159419v1/shard-bmg-1/igt@kms_bw@linear-tiling-3-displays-2160x1440p.html

  * igt@kms_ccs@missing-ccs-buffer-yf-tiled-ccs:
    - shard-bmg:          [SKIP][99] ([Intel XE#6703]) -> [SKIP][100] ([Intel XE#2887]) +3 other tests skip
   [99]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4296-cab246648fd89efbe8d20ed4c86e7fcebd7606da/shard-bmg-2/igt@kms_ccs@missing-ccs-buffer-yf-tiled-ccs.html
   [100]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159419v1/shard-bmg-1/igt@kms_ccs@missing-ccs-buffer-yf-tiled-ccs.html

  * igt@kms_ccs@random-ccs-data-4-tiled-lnl-ccs:
    - shard-bmg:          [SKIP][101] ([Intel XE#6703]) -> [SKIP][102] ([Intel XE#2652] / [Intel XE#787])
   [101]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4296-cab246648fd89efbe8d20ed4c86e7fcebd7606da/shard-bmg-2/igt@kms_ccs@random-ccs-data-4-tiled-lnl-ccs.html
   [102]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159419v1/shard-bmg-1/igt@kms_ccs@random-ccs-data-4-tiled-lnl-ccs.html

  * igt@kms_chamelium_frames@hdmi-frame-dump:
    - shard-bmg:          [SKIP][103] ([Intel XE#6703]) -> [SKIP][104] ([Intel XE#2252]) +1 other test skip
   [103]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4296-cab246648fd89efbe8d20ed4c86e7fcebd7606da/shard-bmg-2/igt@kms_chamelium_frames@hdmi-frame-dump.html
   [104]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159419v1/shard-bmg-1/igt@kms_chamelium_frames@hdmi-frame-dump.html

  * igt@kms_chamelium_sharpness_filter@filter-basic:
    - shard-bmg:          [SKIP][105] ([Intel XE#6703]) -> [SKIP][106] ([Intel XE#6507])
   [105]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4296-cab246648fd89efbe8d20ed4c86e7fcebd7606da/shard-bmg-2/igt@kms_chamelium_sharpness_filter@filter-basic.html
   [106]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159419v1/shard-bmg-1/igt@kms_chamelium_sharpness_filter@filter-basic.html

  * igt@kms_cursor_crc@cursor-offscreen-256x85:
    - shard-bmg:          [SKIP][107] ([Intel XE#6703]) -> [SKIP][108] ([Intel XE#2320])
   [107]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4296-cab246648fd89efbe8d20ed4c86e7fcebd7606da/shard-bmg-2/igt@kms_cursor_crc@cursor-offscreen-256x85.html
   [108]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159419v1/shard-bmg-1/igt@kms_cursor_crc@cursor-offscreen-256x85.html

  * igt@kms_flip@flip-vs-expired-vblank-interruptible:
    - shard-lnl:          [FAIL][109] ([Intel XE#301] / [Intel XE#3149]) -> [FAIL][110] ([Intel XE#301])
   [109]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4296-cab246648fd89efbe8d20ed4c86e7fcebd7606da/shard-lnl-2/igt@kms_flip@flip-vs-expired-vblank-interruptible.html
   [110]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159419v1/shard-lnl-7/igt@kms_flip@flip-vs-expired-vblank-interruptible.html

  * igt@kms_flip_scaled_crc@flip-32bpp-ytileccs-to-64bpp-ytile-downscaling:
    - shard-bmg:          [SKIP][111] ([Intel XE#6703]) -> [SKIP][112] ([Intel XE#2293] / [Intel XE#2380])
   [111]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4296-cab246648fd89efbe8d20ed4c86e7fcebd7606da/shard-bmg-2/igt@kms_flip_scaled_crc@flip-32bpp-ytileccs-to-64bpp-ytile-downscaling.html
   [112]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159419v1/shard-bmg-1/igt@kms_flip_scaled_crc@flip-32bpp-ytileccs-to-64bpp-ytile-downscaling.html

  * igt@kms_frontbuffer_tracking@drrs-2p-scndscrn-indfb-pgflip-blt:
    - shard-bmg:          [SKIP][113] ([Intel XE#2311]) -> [SKIP][114] ([Intel XE#2312]) +12 other tests skip
   [113]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4296-cab246648fd89efbe8d20ed4c86e7fcebd7606da/shard-bmg-8/igt@kms_frontbuffer_tracking@drrs-2p-scndscrn-indfb-pgflip-blt.html
   [114]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159419v1/shard-bmg-4/igt@kms_frontbuffer_tracking@drrs-2p-scndscrn-indfb-pgflip-blt.html

  * igt@kms_frontbuffer_tracking@drrs-2p-scndscrn-pri-indfb-draw-mmap-wc:
    - shard-bmg:          [SKIP][115] ([Intel XE#6703]) -> [SKIP][116] ([Intel XE#2311]) +6 other tests skip
   [115]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4296-cab246648fd89efbe8d20ed4c86e7fcebd7606da/shard-bmg-2/igt@kms_frontbuffer_tracking@drrs-2p-scndscrn-pri-indfb-draw-mmap-wc.html
   [116]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159419v1/shard-bmg-1/igt@kms_frontbuffer_tracking@drrs-2p-scndscrn-pri-indfb-draw-mmap-wc.html

  * igt@kms_frontbuffer_tracking@drrs-2p-scndscrn-spr-indfb-draw-blt:
    - shard-bmg:          [SKIP][117] ([Intel XE#2312]) -> [SKIP][118] ([Intel XE#2311]) +13 other tests skip
   [117]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4296-cab246648fd89efbe8d20ed4c86e7fcebd7606da/shard-bmg-4/igt@kms_frontbuffer_tracking@drrs-2p-scndscrn-spr-indfb-draw-blt.html
   [118]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159419v1/shard-bmg-3/igt@kms_frontbuffer_tracking@drrs-2p-scndscrn-spr-indfb-draw-blt.html

  * igt@kms_frontbuffer_tracking@fbc-2p-primscrn-pri-shrfb-draw-mmap-wc:
    - shard-bmg:          [SKIP][119] ([Intel XE#4141]) -> [SKIP][120] ([Intel XE#2312]) +4 other tests skip
   [119]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4296-cab246648fd89efbe8d20ed4c86e7fcebd7606da/shard-bmg-10/igt@kms_frontbuffer_tracking@fbc-2p-primscrn-pri-shrfb-draw-mmap-wc.html
   [120]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159419v1/shard-bmg-4/igt@kms_frontbuffer_tracking@fbc-2p-primscrn-pri-shrfb-draw-mmap-wc.html

  * igt@kms_frontbuffer_tracking@fbc-2p-primscrn-shrfb-pgflip-blt:
    - shard-bmg:          [SKIP][121] ([Intel XE#6703]) -> [SKIP][122] ([Intel XE#4141]) +2 other tests skip
   [121]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4296-cab246648fd89efbe8d20ed4c86e7fcebd7606da/shard-bmg-2/igt@kms_frontbuffer_tracking@fbc-2p-primscrn-shrfb-pgflip-blt.html
   [122]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159419v1/shard-bmg-1/igt@kms_frontbuffer_tracking@fbc-2p-primscrn-shrfb-pgflip-blt.html

  * igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-shrfb-pgflip-blt:
    - shard-bmg:          [SKIP][123] ([Intel XE#2312]) -> [SKIP][124] ([Intel XE#4141]) +3 other tests skip
   [123]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4296-cab246648fd89efbe8d20ed4c86e7fcebd7606da/shard-bmg-4/igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-shrfb-pgflip-blt.html
   [124]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159419v1/shard-bmg-7/igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-shrfb-pgflip-blt.html

  * igt@kms_frontbuffer_tracking@fbcdrrs-2p-scndscrn-shrfb-pgflip-blt:
    - shard-bmg:          [SKIP][125] ([Intel XE#6557] / [Intel XE#6703]) -> [SKIP][126] ([Intel XE#2311])
   [125]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4296-cab246648fd89efbe8d20ed4c86e7fcebd7606da/shard-bmg-2/igt@kms_frontbuffer_tracking@fbcdrrs-2p-scndscrn-shrfb-pgflip-blt.html
   [126]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159419v1/shard-bmg-1/igt@kms_frontbuffer_tracking@fbcdrrs-2p-scndscrn-shrfb-pgflip-blt.html

  * igt@kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-pri-indfb-draw-mmap-wc:
    - shard-bmg:          [SKIP][127] ([Intel XE#2313]) -> [SKIP][128] ([Intel XE#2312]) +8 other tests skip
   [127]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4296-cab246648fd89efbe8d20ed4c86e7fcebd7606da/shard-bmg-10/igt@kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-pri-indfb-draw-mmap-wc.html
   [128]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159419v1/shard-bmg-4/igt@kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-pri-indfb-draw-mmap-wc.html

  * igt@kms_frontbuffer_tracking@psr-1p-offscreen-pri-shrfb-draw-mmap-wc:
    - shard-bmg:          [SKIP][129] ([Intel XE#6703]) -> [SKIP][130] ([Intel XE#2313]) +6 other tests skip
   [129]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4296-cab246648fd89efbe8d20ed4c86e7fcebd7606da/shard-bmg-2/igt@kms_frontbuffer_tracking@psr-1p-offscreen-pri-shrfb-draw-mmap-wc.html
   [130]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159419v1/shard-bmg-1/igt@kms_frontbuffer_tracking@psr-1p-offscreen-pri-shrfb-draw-mmap-wc.html

  * igt@kms_frontbuffer_tracking@psr-2p-primscrn-indfb-plflip-blt:
    - shard-bmg:          [SKIP][131] ([Intel XE#2312]) -> [SKIP][132] ([Intel XE#2313]) +13 other tests skip
   [131]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4296-cab246648fd89efbe8d20ed4c86e7fcebd7606da/shard-bmg-4/igt@kms_frontbuffer_tracking@psr-2p-primscrn-indfb-plflip-blt.html
   [132]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159419v1/shard-bmg-7/igt@kms_frontbuffer_tracking@psr-2p-primscrn-indfb-plflip-blt.html

  * igt@kms_hdr@brightness-with-hdr:
    - shard-bmg:          [SKIP][133] ([Intel XE#3374] / [Intel XE#3544]) -> [SKIP][134] ([Intel XE#3544])
   [133]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4296-cab246648fd89efbe8d20ed4c86e7fcebd7606da/shard-bmg-7/igt@kms_hdr@brightness-with-hdr.html
   [134]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159419v1/shard-bmg-10/igt@kms_hdr@brightness-with-hdr.html

  * igt@kms_hdr@invalid-hdr:
    - shard-bmg:          [SKIP][135] ([Intel XE#1503]) -> [ABORT][136] ([Intel XE#6740])
   [135]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4296-cab246648fd89efbe8d20ed4c86e7fcebd7606da/shard-bmg-9/igt@kms_hdr@invalid-hdr.html
   [136]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159419v1/shard-bmg-3/igt@kms_hdr@invalid-hdr.html

  * igt@kms_panel_fitting@atomic-fastset:
    - shard-bmg:          [SKIP][137] ([Intel XE#6703]) -> [SKIP][138] ([Intel XE#2486])
   [137]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4296-cab246648fd89efbe8d20ed4c86e7fcebd7606da/shard-bmg-2/igt@kms_panel_fitting@atomic-fastset.html
   [138]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159419v1/shard-bmg-1/igt@kms_panel_fitting@atomic-fastset.html

  * igt@kms_plane_multiple@2x-tiling-yf:
    - shard-bmg:          [SKIP][139] ([Intel XE#4596]) -> [SKIP][140] ([Intel XE#5021])
   [139]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4296-cab246648fd89efbe8d20ed4c86e7fcebd7606da/shard-bmg-4/igt@kms_plane_multiple@2x-tiling-yf.html
   [140]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159419v1/shard-bmg-3/igt@kms_plane_multiple@2x-tiling-yf.html

  * igt@kms_psr2_sf@fbc-psr2-cursor-plane-update-sf:
    - shard-bmg:          [SKIP][141] ([Intel XE#1406] / [Intel XE#6703]) -> [SKIP][142] ([Intel XE#1406] / [Intel XE#1489])
   [141]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4296-cab246648fd89efbe8d20ed4c86e7fcebd7606da/shard-bmg-2/igt@kms_psr2_sf@fbc-psr2-cursor-plane-update-sf.html
   [142]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159419v1/shard-bmg-1/igt@kms_psr2_sf@fbc-psr2-cursor-plane-update-sf.html

  * igt@kms_psr@fbc-psr-suspend:
    - shard-bmg:          [SKIP][143] ([Intel XE#1406] / [Intel XE#6703]) -> [SKIP][144] ([Intel XE#1406] / [Intel XE#2234] / [Intel XE#2850]) +3 other tests skip
   [143]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4296-cab246648fd89efbe8d20ed4c86e7fcebd7606da/shard-bmg-2/igt@kms_psr@fbc-psr-suspend.html
   [144]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159419v1/shard-bmg-1/igt@kms_psr@fbc-psr-suspend.html

  * igt@kms_rotation_crc@primary-yf-tiled-reflect-x-180:
    - shard-bmg:          [SKIP][145] ([Intel XE#6703]) -> [SKIP][146] ([Intel XE#2330])
   [145]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4296-cab246648fd89efbe8d20ed4c86e7fcebd7606da/shard-bmg-2/igt@kms_rotation_crc@primary-yf-tiled-reflect-x-180.html
   [146]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159419v1/shard-bmg-1/igt@kms_rotation_crc@primary-yf-tiled-reflect-x-180.html

  * igt@kms_sharpness_filter@filter-basic:
    - shard-bmg:          [SKIP][147] ([Intel XE#6703]) -> [SKIP][148] ([Intel XE#6503])
   [147]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4296-cab246648fd89efbe8d20ed4c86e7fcebd7606da/shard-bmg-2/igt@kms_sharpness_filter@filter-basic.html
   [148]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159419v1/shard-bmg-1/igt@kms_sharpness_filter@filter-basic.html

  * igt@kms_vrr@cmrr:
    - shard-bmg:          [SKIP][149] ([Intel XE#6703]) -> [SKIP][150] ([Intel XE#2168])
   [149]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4296-cab246648fd89efbe8d20ed4c86e7fcebd7606da/shard-bmg-2/igt@kms_vrr@cmrr.html
   [150]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159419v1/shard-bmg-1/igt@kms_vrr@cmrr.html

  * igt@xe_eudebug@basic-vms:
    - shard-bmg:          [SKIP][151] ([Intel XE#6703]) -> [SKIP][152] ([Intel XE#4837])
   [151]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4296-cab246648fd89efbe8d20ed4c86e7fcebd7606da/shard-bmg-2/igt@xe_eudebug@basic-vms.html
   [152]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159419v1/shard-bmg-1/igt@xe_eudebug@basic-vms.html

  * igt@xe_eudebug_online@interrupt-all:
    - shard-bmg:          [SKIP][153] ([Intel XE#6703]) -> [SKIP][154] ([Intel XE#4837] / [Intel XE#6665])
   [153]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4296-cab246648fd89efbe8d20ed4c86e7fcebd7606da/shard-bmg-2/igt@xe_eudebug_online@interrupt-all.html
   [154]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159419v1/shard-bmg-1/igt@xe_eudebug_online@interrupt-all.html

  * igt@xe_exec_multi_queue@two-queues-preempt-mode-fault-dyn-priority-smem:
    - shard-bmg:          [SKIP][155] ([Intel XE#6703]) -> [SKIP][156] ([Intel XE#6874]) +7 other tests skip
   [155]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4296-cab246648fd89efbe8d20ed4c86e7fcebd7606da/shard-bmg-2/igt@xe_exec_multi_queue@two-queues-preempt-mode-fault-dyn-priority-smem.html
   [156]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159419v1/shard-bmg-1/igt@xe_exec_multi_queue@two-queues-preempt-mode-fault-dyn-priority-smem.html

  * igt@xe_exec_system_allocator@threads-many-large-mmap-huge-nomemset:
    - shard-bmg:          [SKIP][157] ([Intel XE#6703]) -> [SKIP][158] ([Intel XE#4943]) +8 other tests skip
   [157]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4296-cab246648fd89efbe8d20ed4c86e7fcebd7606da/shard-bmg-2/igt@xe_exec_system_allocator@threads-many-large-mmap-huge-nomemset.html
   [158]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159419v1/shard-bmg-1/igt@xe_exec_system_allocator@threads-many-large-mmap-huge-nomemset.html

  * igt@xe_query@multigpu-query-invalid-uc-fw-version-mbz:
    - shard-bmg:          [SKIP][159] ([Intel XE#6703]) -> [SKIP][160] ([Intel XE#944]) +1 other test skip
   [159]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4296-cab246648fd89efbe8d20ed4c86e7fcebd7606da/shard-bmg-2/igt@xe_query@multigpu-query-invalid-uc-fw-version-mbz.html
   [160]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159419v1/shard-bmg-1/igt@xe_query@multigpu-query-invalid-uc-fw-version-mbz.html

  
  [Intel XE#1124]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1124
  [Intel XE#1178]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1178
  [Intel XE#1406]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1406
  [Intel XE#1489]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1489
  [Intel XE#1503]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1503
  [Intel XE#1508]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1508
  [Intel XE#1727]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1727
  [Intel XE#2168]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2168
  [Intel XE#2234]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2234
  [Intel XE#2252]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2252
  [Intel XE#2291]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2291
  [Intel XE#2293]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2293
  [Intel XE#2311]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2311
  [Intel XE#2312]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2312
  [Intel XE#2313]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2313
  [Intel XE#2314]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2314
  [Intel XE#2316]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2316
  [Intel XE#2320]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2320
  [Intel XE#2321]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2321
  [Intel XE#2322]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2322
  [Intel XE#2327]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2327
  [Intel XE#2330]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2330
  [Intel XE#2373]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2373
  [Intel XE#2374]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2374
  [Intel XE#2380]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2380
  [Intel XE#2390]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2390
  [Intel XE#2393]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2393
  [Intel XE#2486]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2486
  [Intel XE#2652]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2652
  [Intel XE#2724]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2724
  [Intel XE#2850]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2850
  [Intel XE#2887]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2887
  [Intel XE#2894]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2894
  [Intel XE#2938]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2938
  [Intel XE#301]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/301
  [Intel XE#3149]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3149
  [Intel XE#3321]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3321
  [Intel XE#3374]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3374
  [Intel XE#3544]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3544
  [Intel XE#367]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/367
  [Intel XE#4141]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4141
  [Intel XE#4354]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4354
  [Intel XE#4422]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4422
  [Intel XE#4596]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4596
  [Intel XE#4733]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4733
  [Intel XE#4837]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4837
  [Intel XE#4943]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4943
  [Intel XE#5007]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5007
  [Intel XE#5021]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5021
  [Intel XE#5177]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5177
  [Intel XE#5213]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5213
  [Intel XE#5299]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5299
  [Intel XE#5742]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5742
  [Intel XE#6251]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6251
  [Intel XE#6281]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6281
  [Intel XE#6321]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6321
  [Intel XE#6503]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6503
  [Intel XE#6507]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6507
  [Intel XE#6557]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6557
  [Intel XE#6558]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6558
  [Intel XE#6665]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6665
  [Intel XE#6693]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6693
  [Intel XE#6703]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6703
  [Intel XE#6740]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6740
  [Intel XE#6819]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6819
  [Intel XE#6874]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6874
  [Intel XE#776]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/776
  [Intel XE#787]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/787
  [Intel XE#944]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/944


Build changes
-------------

  * Linux: xe-4296-cab246648fd89efbe8d20ed4c86e7fcebd7606da -> xe-pw-159419v1

  IGT_8674: f38f4d8e9c65aff45ac807e646d06e38bc3193a2 @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
  xe-4296-cab246648fd89efbe8d20ed4c86e7fcebd7606da: cab246648fd89efbe8d20ed4c86e7fcebd7606da
  xe-pw-159419v1: 159419v1

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159419v1/index.html

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