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From: Matthew Brost <matthew.brost@intel.com>
To: intel-xe@lists.freedesktop.org
Cc: Stuart Summers <stuart.summers@intel.com>
Subject: [PATCH v5 03/11] drm/xe: Add has_ctx_tlb_inval to device info
Date: Fri, 16 Jan 2026 14:17:23 -0800	[thread overview]
Message-ID: <20260116221731.868657-4-matthew.brost@intel.com> (raw)
In-Reply-To: <20260116221731.868657-1-matthew.brost@intel.com>

Add has_ctx_tlb_inval to device info indicating a device has context
basd TLB invalidation.

Signed-off-by: Matthew Brost <matthew.brost@intel.com>
Reviewed-by: Stuart Summers <stuart.summers@intel.com>
Tested-by: Stuart Summers <stuart.summers@intel.com>
---
 drivers/gpu/drm/xe/xe_device_types.h | 2 ++
 drivers/gpu/drm/xe/xe_pci.c          | 1 +
 drivers/gpu/drm/xe/xe_pci_types.h    | 1 +
 3 files changed, 4 insertions(+)

diff --git a/drivers/gpu/drm/xe/xe_device_types.h b/drivers/gpu/drm/xe/xe_device_types.h
index f689766adcb1..72453206267b 100644
--- a/drivers/gpu/drm/xe/xe_device_types.h
+++ b/drivers/gpu/drm/xe/xe_device_types.h
@@ -353,6 +353,8 @@ struct xe_device {
 		u8 has_pre_prod_wa:1;
 		/** @info.has_pxp: Device has PXP support */
 		u8 has_pxp:1;
+		/** @info.has_ctx_tlb_inval: Has context based TLB invalidations */
+		u8 has_ctx_tlb_inval:1;
 		/** @info.has_range_tlb_inval: Has range based TLB invalidations */
 		u8 has_range_tlb_inval:1;
 		/** @info.has_soc_remapper_sysctrl: Has SoC remapper system controller */
diff --git a/drivers/gpu/drm/xe/xe_pci.c b/drivers/gpu/drm/xe/xe_pci.c
index 2c3656126751..f6600a661860 100644
--- a/drivers/gpu/drm/xe/xe_pci.c
+++ b/drivers/gpu/drm/xe/xe_pci.c
@@ -892,6 +892,7 @@ static int xe_info_init(struct xe_device *xe,
 		xe->info.has_device_atomics_on_smem = 1;
 
 	xe->info.has_range_tlb_inval = graphics_desc->has_range_tlb_inval;
+	xe->info.has_ctx_tlb_inval = graphics_desc->has_ctx_tlb_inval;
 	xe->info.has_usm = graphics_desc->has_usm;
 	xe->info.has_64bit_timestamp = graphics_desc->has_64bit_timestamp;
 
diff --git a/drivers/gpu/drm/xe/xe_pci_types.h b/drivers/gpu/drm/xe/xe_pci_types.h
index 20acc5349ee6..7ccb0ab7a53b 100644
--- a/drivers/gpu/drm/xe/xe_pci_types.h
+++ b/drivers/gpu/drm/xe/xe_pci_types.h
@@ -72,6 +72,7 @@ struct xe_graphics_desc {
 	u8 has_atomic_enable_pte_bit:1;
 	u8 has_indirect_ring_state:1;
 	u8 has_range_tlb_inval:1;
+	u8 has_ctx_tlb_inval:1;
 	u8 has_usm:1;
 	u8 has_64bit_timestamp:1;
 };
-- 
2.34.1


  parent reply	other threads:[~2026-01-16 22:17 UTC|newest]

Thread overview: 17+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2026-01-16 22:17 [PATCH v5 00/11] Context based TLB invalidations Matthew Brost
2026-01-16 22:17 ` [PATCH v5 01/11] drm/xe: Add normalize_invalidation_range Matthew Brost
2026-01-16 22:17 ` [PATCH v5 02/11] drm/xe: Make usm.asid_to_vm allocation use GFP_NOWAIT Matthew Brost
2026-01-16 22:17 ` Matthew Brost [this message]
2026-01-16 22:17 ` [PATCH v5 04/11] drm/xe: Add xe_device_asid_to_vm helper Matthew Brost
2026-01-16 22:17 ` [PATCH v5 05/11] drm/xe: Add vm to exec queues association Matthew Brost
2026-01-16 22:17 ` [PATCH v5 06/11] drm/xe: Taint TLB invalidation seqno lock with GFP_KERNEL Matthew Brost
2026-01-16 22:17 ` [PATCH v5 07/11] drm/xe: Rename send_tlb_inval_ppgtt to send_tlb_inval_asid_ppgtt Matthew Brost
2026-01-16 22:17 ` [PATCH v5 08/11] drm/xe: Add send_tlb_inval_ppgtt helper Matthew Brost
2026-01-16 22:17 ` [PATCH v5 09/11] drm/xe: Add xe_tlb_inval_idle helper Matthew Brost
2026-01-16 22:17 ` [PATCH v5 10/11] drm/xe: Add exec queue active vfunc Matthew Brost
2026-01-16 22:30   ` Summers, Stuart
2026-01-16 22:17 ` [PATCH v5 11/11] drm/xe: Add context-based invalidation to GuC TLB invalidation backend Matthew Brost
2026-01-16 22:36   ` Summers, Stuart
2026-01-16 23:30 ` ✓ CI.KUnit: success for Context based TLB invalidations (rev5) Patchwork
2026-01-17  0:05 ` ✓ Xe.CI.BAT: " Patchwork
2026-01-17  2:15 ` ✓ Xe.CI.Full: " Patchwork

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