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From: Gustavo Sousa <gustavo.sousa@intel.com>
To: intel-xe@lists.freedesktop.org, intel-gfx@lists.freedesktop.org
Cc: Gustavo Sousa <gustavo.sousa@intel.com>,
	 Matt Roper <matthew.d.roper@intel.com>
Subject: [PATCH 06/16] drm/xe/xe3p_lpg: Add LRC parsing for additional RCS engine state
Date: Mon, 02 Feb 2026 18:43:12 -0300	[thread overview]
Message-ID: <20260202-nvl-p-upstreaming-v1-6-653e4ff105dc@intel.com> (raw)
In-Reply-To: <20260202-nvl-p-upstreaming-v1-0-653e4ff105dc@intel.com>

From: Matt Roper <matthew.d.roper@intel.com>

Xe3p_LPG adds some additional state instructions to the RCS engine's
LRC.  Add support for these to the debugfs LRC parser.

Note that the bspec's LRC description page seems to have a few mistakes
in the name/spelling of these new instructions (e.g.,
"3DSTATE_TASK_DATA_EXT" instead of "3DSTATE_TASK_SHADER_DATA_EXT" or
"3DSTATE_VIEWPORT_STATE_POINTERS_CL_SF_2" instead of
"3DSTATE_VIEWPORT_STATE_POINTERS_SF_CLIP_2").

Bspec: 65182
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Signed-off-by: Gustavo Sousa <gustavo.sousa@intel.com>
---
 drivers/gpu/drm/xe/instructions/xe_gfxpipe_commands.h | 10 ++++++++++
 drivers/gpu/drm/xe/xe_lrc.c                           | 10 ++++++++++
 2 files changed, 20 insertions(+)

diff --git a/drivers/gpu/drm/xe/instructions/xe_gfxpipe_commands.h b/drivers/gpu/drm/xe/instructions/xe_gfxpipe_commands.h
index 457881af8af9..4d854c85e588 100644
--- a/drivers/gpu/drm/xe/instructions/xe_gfxpipe_commands.h
+++ b/drivers/gpu/drm/xe/instructions/xe_gfxpipe_commands.h
@@ -55,6 +55,7 @@
 #define PIPELINE_SELECT				GFXPIPE_SINGLE_DW_CMD(0x1, 0x4)
 
 #define CMD_3DSTATE_DRAWING_RECTANGLE_FAST	GFXPIPE_3D_CMD(0x0, 0x0)
+#define CMD_3DSTATE_CUSTOM_SAMPLE_PATTERN	GFXPIPE_3D_CMD(0x0, 0x2)
 #define CMD_3DSTATE_CLEAR_PARAMS		GFXPIPE_3D_CMD(0x0, 0x4)
 #define CMD_3DSTATE_DEPTH_BUFFER		GFXPIPE_3D_CMD(0x0, 0x5)
 #define CMD_3DSTATE_STENCIL_BUFFER		GFXPIPE_3D_CMD(0x0, 0x6)
@@ -138,8 +139,16 @@
 #define CMD_3DSTATE_SBE_MESH			GFXPIPE_3D_CMD(0x0, 0x82)
 #define CMD_3DSTATE_CPSIZE_CONTROL_BUFFER	GFXPIPE_3D_CMD(0x0, 0x83)
 #define CMD_3DSTATE_COARSE_PIXEL		GFXPIPE_3D_CMD(0x0, 0x89)
+#define CMD_3DSTATE_MESH_SHADER_DATA_EXT	GFXPIPE_3D_CMD(0x0, 0x8A)
+#define CMD_3DSTATE_TASK_SHADER_DATA_EXT	GFXPIPE_3D_CMD(0x0, 0x8B)
+#define CMD_3DSTATE_VIEWPORT_STATE_POINTERS_CC_2	GFXPIPE_3D_CMD(0x0, 0x8D)
+#define CMD_3DSTATE_CC_STATE_POINTERS_2		GFXPIPE_3D_CMD(0x0, 0x8E)
+#define CMD_3DSTATE_SCISSOR_STATE_POINTERS_2	GFXPIPE_3D_CMD(0x0, 0x8F)
+#define CMD_3DSTATE_BLEND_STATE_POINTERS_2	GFXPIPE_3D_CMD(0x0, 0xA0)
+#define CMD_3DSTATE_VIEWPORT_STATE_POINTERS_SF_CLIP_2	GFXPIPE_3D_CMD(0x0, 0xA1)
 
 #define CMD_3DSTATE_DRAWING_RECTANGLE		GFXPIPE_3D_CMD(0x1, 0x0)
+#define CMD_3DSTATE_URB_MEMORY			GFXPIPE_3D_CMD(0x1, 0x1)
 #define CMD_3DSTATE_CHROMA_KEY			GFXPIPE_3D_CMD(0x1, 0x4)
 #define CMD_3DSTATE_POLY_STIPPLE_OFFSET		GFXPIPE_3D_CMD(0x1, 0x6)
 #define CMD_3DSTATE_POLY_STIPPLE_PATTERN	GFXPIPE_3D_CMD(0x1, 0x7)
@@ -160,5 +169,6 @@
 #define CMD_3DSTATE_SUBSLICE_HASH_TABLE		GFXPIPE_3D_CMD(0x1, 0x1F)
 #define CMD_3DSTATE_SLICE_TABLE_STATE_POINTERS	GFXPIPE_3D_CMD(0x1, 0x20)
 #define CMD_3DSTATE_PTBR_TILE_PASS_INFO		GFXPIPE_3D_CMD(0x1, 0x22)
+#define CMD_3DSTATE_SLICE_TABLE_STATE_POINTER_2	GFXPIPE_3D_CMD(0x1, 0xA0)
 
 #endif
diff --git a/drivers/gpu/drm/xe/xe_lrc.c b/drivers/gpu/drm/xe/xe_lrc.c
index 3db7968aa5e2..e58eb8b9db78 100644
--- a/drivers/gpu/drm/xe/xe_lrc.c
+++ b/drivers/gpu/drm/xe/xe_lrc.c
@@ -1966,6 +1966,7 @@ static int dump_gfxpipe_command(struct drm_printer *p,
 	MATCH(PIPELINE_SELECT);
 
 	MATCH3D(3DSTATE_DRAWING_RECTANGLE_FAST);
+	MATCH3D(3DSTATE_CUSTOM_SAMPLE_PATTERN);
 	MATCH3D(3DSTATE_CLEAR_PARAMS);
 	MATCH3D(3DSTATE_DEPTH_BUFFER);
 	MATCH3D(3DSTATE_STENCIL_BUFFER);
@@ -2049,8 +2050,16 @@ static int dump_gfxpipe_command(struct drm_printer *p,
 	MATCH3D(3DSTATE_SBE_MESH);
 	MATCH3D(3DSTATE_CPSIZE_CONTROL_BUFFER);
 	MATCH3D(3DSTATE_COARSE_PIXEL);
+	MATCH3D(3DSTATE_MESH_SHADER_DATA_EXT);
+	MATCH3D(3DSTATE_TASK_SHADER_DATA_EXT);
+	MATCH3D(3DSTATE_VIEWPORT_STATE_POINTERS_CC_2);
+	MATCH3D(3DSTATE_CC_STATE_POINTERS_2);
+	MATCH3D(3DSTATE_SCISSOR_STATE_POINTERS_2);
+	MATCH3D(3DSTATE_BLEND_STATE_POINTERS_2);
+	MATCH3D(3DSTATE_VIEWPORT_STATE_POINTERS_SF_CLIP_2);
 
 	MATCH3D(3DSTATE_DRAWING_RECTANGLE);
+	MATCH3D(3DSTATE_URB_MEMORY);
 	MATCH3D(3DSTATE_CHROMA_KEY);
 	MATCH3D(3DSTATE_POLY_STIPPLE_OFFSET);
 	MATCH3D(3DSTATE_POLY_STIPPLE_PATTERN);
@@ -2070,6 +2079,7 @@ static int dump_gfxpipe_command(struct drm_printer *p,
 	MATCH3D(3DSTATE_SUBSLICE_HASH_TABLE);
 	MATCH3D(3DSTATE_SLICE_TABLE_STATE_POINTERS);
 	MATCH3D(3DSTATE_PTBR_TILE_PASS_INFO);
+	MATCH3D(3DSTATE_SLICE_TABLE_STATE_POINTER_2);
 
 	default:
 		drm_printf(p, "[%#010x] unknown GFXPIPE command (pipeline=%#x, opcode=%#x, subopcode=%#x), likely %d dwords\n",

-- 
2.52.0


  parent reply	other threads:[~2026-02-02 21:44 UTC|newest]

Thread overview: 42+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2026-02-02 21:43 [PATCH 00/16] Basic enabling patches for Xe3p_LPG and NVL-P Gustavo Sousa
2026-02-02 21:43 ` [PATCH 01/16] drm/xe/xe3p_lpg: Add support for graphics IP 35.10 Gustavo Sousa
2026-02-02 22:11   ` Matt Roper
2026-02-02 23:36     ` Matt Roper
2026-02-03 23:53       ` Gustavo Sousa
2026-02-02 21:43 ` [PATCH 02/16] drm/xe/xe3p_lpg: Add initial workarounds for graphics version 35.10 Gustavo Sousa
2026-02-02 22:47   ` Matt Roper
2026-02-04  0:25     ` Gustavo Sousa
2026-02-02 21:43 ` [PATCH 03/16] drm/xe/pat: Differentiate between primary and media for PTA Gustavo Sousa
2026-02-02 22:51   ` Matt Roper
2026-02-02 21:43 ` [PATCH 04/16] drm/xe/xe3p_lpg: Add new PAT table Gustavo Sousa
2026-02-05 17:05   ` Matt Atwood
2026-02-02 21:43 ` [PATCH 05/16] drm/xe/xe3p_lpg: Add MCR steering Gustavo Sousa
2026-02-03 10:32   ` Bhadane, Dnyaneshwar
2026-02-04  0:33     ` Gustavo Sousa
2026-02-06  8:29       ` Bhadane, Dnyaneshwar
2026-02-06 12:38         ` Gustavo Sousa
2026-02-02 21:43 ` Gustavo Sousa [this message]
2026-02-05 22:12   ` [PATCH 06/16] drm/xe/xe3p_lpg: Add LRC parsing for additional RCS engine state Matt Atwood
2026-02-02 21:43 ` [PATCH 07/16] drm/xe/xe3p_lpg: Disable reporting of context switch status to GHWSP Gustavo Sousa
2026-02-05 17:31   ` Matt Atwood
2026-02-02 21:43 ` [PATCH 08/16] drm/xe/xe3p_lpg: Drop unnecessary tuning settings Gustavo Sousa
2026-02-05 17:28   ` Matt Atwood
2026-02-02 21:43 ` [PATCH 09/16] drm/xe/xe3p_lpg: Extend 'group ID' mask size Gustavo Sousa
2026-02-04 12:18   ` Bhadane, Dnyaneshwar
2026-02-02 21:43 ` [PATCH 10/16] drm/xe/xe3p_lpg: Update LRC sizes Gustavo Sousa
2026-02-02 23:29   ` Matt Roper
2026-02-02 21:43 ` [PATCH 11/16] drm/xe/xe3p_lpg: Set STLB bank hash mode to 4KB Gustavo Sousa
2026-02-02 23:34   ` Matt Roper
2026-02-02 21:43 ` [PATCH 12/16] drm/xe/xe3p_lpg: Enable multi-queue feature Gustavo Sousa
2026-02-02 23:35   ` Matt Roper
2026-02-02 21:43 ` [PATCH 13/16] drm/xe/nvlp: Add NVL-P platform definition Gustavo Sousa
2026-02-02 23:48   ` Matt Roper
2026-02-04 12:59     ` Gustavo Sousa
2026-02-04 18:08       ` Matt Roper
2026-02-04 18:36         ` Gustavo Sousa
2026-02-02 21:43 ` [PATCH 14/16] drm/xe/nvlp: Attach MOCS table for nvlp Gustavo Sousa
2026-02-02 23:48   ` Matt Roper
2026-02-02 21:43 ` [PATCH 15/16] drm/i915/nvlp: Hook up display support Gustavo Sousa
2026-02-03  4:19   ` Kandpal, Suraj
2026-02-02 21:43 ` [PATCH 16/16] drm/xe/nvlp: Define GuC firmware for NVL-P Gustavo Sousa
2026-02-02 23:52   ` Matt Roper

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