[PATCH v2 00/10] CMTG enablement

[Animesh Manna <animesh.manna@intel.com>]

Common mode timing generator (CMTG) support is added LNL onwards.
Enable CMTG which will be needed by other fearure like dynamic dc
state enablement later.

Testing ongoing, currently counters are incrementing as expected.

Animesh Manna (8):
  drm/i915/cmtg: enable cmtg LNL onwards
  drm/i915/cmtg: cmtg set clock select
  drm/i915/cmtg: set timings for cmtg
  drm/i915/cmtg: program vrr registers of cmtg
  drm/i915/cmtg: program set context latency of cmtg
  drm/i915/cmtg: set transcoder mn for cmtg
  drm/i915/cmtg: program sync to port for cmtg
  drm/i915/cmtg: enable cmtg ctl

Dibin Moolakadan Subrahmanian (2):
  drm/i915/cmtg: enable cmtg in secondary mode
  drm/i915/cmtg: disable CMTG on transcoder disable

 drivers/gpu/drm/i915/display/intel_cmtg.c     | 140 +++++++++++++++++-
 drivers/gpu/drm/i915/display/intel_cmtg.h     |   4 +
 .../gpu/drm/i915/display/intel_cmtg_regs.h    |  22 +++
 drivers/gpu/drm/i915/display/intel_crt.c      |   1 +
 drivers/gpu/drm/i915/display/intel_cx0_phy.c  |   5 +
 drivers/gpu/drm/i915/display/intel_display.c  |  52 ++++---
 .../drm/i915/display/intel_display_types.h    |   7 +
 drivers/gpu/drm/i915/display/intel_dp.c       |   4 +
 drivers/gpu/drm/i915/display/intel_lt_phy.c   |   9 +-
 drivers/gpu/drm/i915/display/intel_vrr.c      |   4 +
 10 files changed, 225 insertions(+), 23 deletions(-)

-- 
2.29.0