[PATCH 0/5] drm/i915/dp_tunnel: Preparation for UHBR DP tunnels

[PATCH 0/5] drm/i915/dp_tunnel: Preparation for UHBR DP tunnels

[Imre Deak]

This patchset prepares the DP tunnel handling for upcoming UHBR DP
tunnel support by ensuring that a bandwidth change notification is
sent when a DP tunnel is created.

Imre Deak (5):
  drm/i915/dp_tunnel: Don't update tunnel state during system resume
  drm/i915/dp_tunnel: Simplify detection of link BW change
  drm/i915/dp_tunnel: Split update_tunnel_state()
  drm/i915/dp_tunnel: Sanitize documentation of intel_dp_tunnel_detect()
  drm/i915/dp_tunnel: Send BW change notification after tunnel creation

 .../gpu/drm/i915/display/intel_dp_tunnel.c    | 96 +++++++++++++------
 1 file changed, 67 insertions(+), 29 deletions(-)

-- 
2.49.1

[PATCH 1/5] drm/i915/dp_tunnel: Don't update tunnel state during system resume

[Imre Deak]

During system resume, restoring the pre-suspend display state must not
fail. This requires preserving the sink capabilities from before
suspend, including the available link bandwidth.

If these capabilities are not preserved, the restore modeset may fail,
either due to a missing sink capability or insufficient link bandwidth
for the restored mode.

When the sink is connected through a DP tunnel, prevent such capability
changes by skipping tunnel state updates during resume. This also avoids
updating the sink state via the tunnel while it is being resumed.

Signed-off-by: Imre Deak <imre.deak@intel.com>
---
 drivers/gpu/drm/i915/display/intel_dp_tunnel.c | 11 ++++++-----
 1 file changed, 6 insertions(+), 5 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_dp_tunnel.c b/drivers/gpu/drm/i915/display/intel_dp_tunnel.c
index faa2b7a46699d..eb1eed1c8c7bb 100644
--- a/drivers/gpu/drm/i915/display/intel_dp_tunnel.c
+++ b/drivers/gpu/drm/i915/display/intel_dp_tunnel.c
@@ -150,11 +150,9 @@ static int allocate_initial_tunnel_bw_for_pipes(struct intel_dp *intel_dp, u8 pi
 			    drm_dp_tunnel_name(intel_dp->tunnel),
 			    encoder->base.base.id, encoder->base.name,
 			    ERR_PTR(err));
-
-		return err;
 	}
 
-	return update_tunnel_state(intel_dp);
+	return err;
 }
 
 static int allocate_initial_tunnel_bw(struct intel_dp *intel_dp,
@@ -200,10 +198,13 @@ static int detect_new_tunnel(struct intel_dp *intel_dp, struct drm_modeset_acqui
 	}
 
 	ret = allocate_initial_tunnel_bw(intel_dp, ctx);
-	if (ret < 0)
+	if (ret < 0) {
 		intel_dp_tunnel_destroy(intel_dp);
 
-	return ret;
+		return ret;
+	}
+
+	return update_tunnel_state(intel_dp);
 }
 
 /**
-- 
2.49.1

RE: [PATCH 1/5] drm/i915/dp_tunnel: Don't update tunnel state during system resume

[Murthy, Arun R]

> -----Original Message-----
> From: Intel-gfx <intel-gfx-bounces@lists.freedesktop.org> On Behalf Of Imre
> Deak
> Sent: Thursday, February 19, 2026 11:58 PM
> To: intel-gfx@lists.freedesktop.org; intel-xe@lists.freedesktop.org
> Subject: [PATCH 1/5] drm/i915/dp_tunnel: Don't update tunnel state during
> system resume
> 
> During system resume, restoring the pre-suspend display state must not fail.
> This requires preserving the sink capabilities from before suspend, including the
> available link bandwidth.
> 
I don't see the sink capabilities being stored in this patch.

> If these capabilities are not preserved, the restore modeset may fail, either due
> to a missing sink capability or insufficient link bandwidth for the restored mode.
Don't see this in the patch.

> 
> When the sink is connected through a DP tunnel, prevent such capability
> changes by skipping tunnel state updates during resume. This also avoids
> updating the sink state via the tunnel while it is being resumed.
> 
> Signed-off-by: Imre Deak <imre.deak@intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_dp_tunnel.c | 11 ++++++-----
>  1 file changed, 6 insertions(+), 5 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_dp_tunnel.c
> b/drivers/gpu/drm/i915/display/intel_dp_tunnel.c
> index faa2b7a46699d..eb1eed1c8c7bb 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp_tunnel.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp_tunnel.c
> @@ -150,11 +150,9 @@ static int allocate_initial_tunnel_bw_for_pipes(struct
> intel_dp *intel_dp, u8 pi
>  			    drm_dp_tunnel_name(intel_dp->tunnel),
>  			    encoder->base.base.id, encoder->base.name,
>  			    ERR_PTR(err));
> -
> -		return err;
>  	}
> 
> -	return update_tunnel_state(intel_dp);
> +	return err;
>  }
> 
>  static int allocate_initial_tunnel_bw(struct intel_dp *intel_dp, @@ -200,10
> +198,13 @@ static int detect_new_tunnel(struct intel_dp *intel_dp, struct
> drm_modeset_acqui
>  	}
> 
>  	ret = allocate_initial_tunnel_bw(intel_dp, ctx);
> -	if (ret < 0)
> +	if (ret < 0) {
>  		intel_dp_tunnel_destroy(intel_dp);
> 
> -	return ret;
> +		return ret;
> +	}
> +
> +	return update_tunnel_state(intel_dp);
>  }
> 
>  /**
> --
> 2.49.1

Thanks and Regards,
Arun R Murthy
--------------------

Re: [PATCH 1/5] drm/i915/dp_tunnel: Don't update tunnel state during system resume

[Imre Deak]

On Mon, Feb 23, 2026 at 05:54:38PM +0200, Murthy, Arun R wrote:
> 
> > -----Original Message-----
> > From: Intel-gfx <intel-gfx-bounces@lists.freedesktop.org> On Behalf Of Imre
> > Deak
> > Sent: Thursday, February 19, 2026 11:58 PM
> > To: intel-gfx@lists.freedesktop.org; intel-xe@lists.freedesktop.org
> > Subject: [PATCH 1/5] drm/i915/dp_tunnel: Don't update tunnel state during
> > system resume
> > 
> > During system resume, restoring the pre-suspend display state must not fail.
> > This requires preserving the sink capabilities from before suspend, including the
> > available link bandwidth.
> > 
> I don't see the sink capabilities being stored in this patch.

The sink capabilities are stored in intel_dp and intel_connector,
including the maximum link rate and lane count, which determine the link
bandwidth. This patch preserves those capabilities across suspend/resume
by preventing the tunnel state from being updated during resume.

> 
> > If these capabilities are not preserved, the restore modeset may fail, either due
> > to a missing sink capability or insufficient link bandwidth for the restored mode.
> Don't see this in the patch.
> 
> > 
> > When the sink is connected through a DP tunnel, prevent such capability
> > changes by skipping tunnel state updates during resume. This also avoids
> > updating the sink state via the tunnel while it is being resumed.
> > 
> > Signed-off-by: Imre Deak <imre.deak@intel.com>
> > ---
> >  drivers/gpu/drm/i915/display/intel_dp_tunnel.c | 11 ++++++-----
> >  1 file changed, 6 insertions(+), 5 deletions(-)
> > 
> > diff --git a/drivers/gpu/drm/i915/display/intel_dp_tunnel.c
> > b/drivers/gpu/drm/i915/display/intel_dp_tunnel.c
> > index faa2b7a46699d..eb1eed1c8c7bb 100644
> > --- a/drivers/gpu/drm/i915/display/intel_dp_tunnel.c
> > +++ b/drivers/gpu/drm/i915/display/intel_dp_tunnel.c
> > @@ -150,11 +150,9 @@ static int allocate_initial_tunnel_bw_for_pipes(struct
> > intel_dp *intel_dp, u8 pi
> >  			    drm_dp_tunnel_name(intel_dp->tunnel),
> >  			    encoder->base.base.id, encoder->base.name,
> >  			    ERR_PTR(err));
> > -
> > -		return err;
> >  	}
> > 
> > -	return update_tunnel_state(intel_dp);
> > +	return err;
> >  }
> > 
> >  static int allocate_initial_tunnel_bw(struct intel_dp *intel_dp, @@ -200,10
> > +198,13 @@ static int detect_new_tunnel(struct intel_dp *intel_dp, struct
> > drm_modeset_acqui
> >  	}
> > 
> >  	ret = allocate_initial_tunnel_bw(intel_dp, ctx);
> > -	if (ret < 0)
> > +	if (ret < 0) {
> >  		intel_dp_tunnel_destroy(intel_dp);
> > 
> > -	return ret;
> > +		return ret;
> > +	}
> > +
> > +	return update_tunnel_state(intel_dp);
> >  }
> > 
> >  /**
> > --
> > 2.49.1
> 
> Thanks and Regards,
> Arun R Murthy
> --------------------

RE: [PATCH 1/5] drm/i915/dp_tunnel: Don't update tunnel state during system resume

[Murthy, Arun R]

> -----Original Message-----
> From: Deak, Imre <imre.deak@intel.com>
> Sent: Monday, February 23, 2026 10:00 PM
> To: Murthy, Arun R <arun.r.murthy@intel.com>
> Cc: intel-gfx@lists.freedesktop.org; intel-xe@lists.freedesktop.org
> Subject: Re: [PATCH 1/5] drm/i915/dp_tunnel: Don't update tunnel state during
> system resume
> 
> On Mon, Feb 23, 2026 at 05:54:38PM +0200, Murthy, Arun R wrote:
> >
> > > -----Original Message-----
> > > From: Intel-gfx <intel-gfx-bounces@lists.freedesktop.org> On Behalf
> > > Of Imre Deak
> > > Sent: Thursday, February 19, 2026 11:58 PM
> > > To: intel-gfx@lists.freedesktop.org; intel-xe@lists.freedesktop.org
> > > Subject: [PATCH 1/5] drm/i915/dp_tunnel: Don't update tunnel state
> > > during system resume
> > >
> > > During system resume, restoring the pre-suspend display state must not fail.
> > > This requires preserving the sink capabilities from before suspend,
> > > including the available link bandwidth.
> > >
> > I don't see the sink capabilities being stored in this patch.
> 
> The sink capabilities are stored in intel_dp and intel_connector, including the
> maximum link rate and lane count, which determine the link bandwidth. This
> patch preserves those capabilities across suspend/resume by preventing the
> tunnel state from being updated during resume.
> 
I understand, but what I meant was this patch doesn't handle anything on the suspend part but only controls the updates on resume.
So explaining what happens on resume is un-necessary.

Thanks and Regards,
Arun R Murthy
--------------------
> >
> > > If these capabilities are not preserved, the restore modeset may
> > > fail, either due to a missing sink capability or insufficient link bandwidth for
> the restored mode.
> > Don't see this in the patch.
> >
> > >
> > > When the sink is connected through a DP tunnel, prevent such
> > > capability changes by skipping tunnel state updates during resume.
> > > This also avoids updating the sink state via the tunnel while it is being
> resumed.
> > >
> > > Signed-off-by: Imre Deak <imre.deak@intel.com>
> > > ---
> > >  drivers/gpu/drm/i915/display/intel_dp_tunnel.c | 11 ++++++-----
> > >  1 file changed, 6 insertions(+), 5 deletions(-)
> > >
> > > diff --git a/drivers/gpu/drm/i915/display/intel_dp_tunnel.c
> > > b/drivers/gpu/drm/i915/display/intel_dp_tunnel.c
> > > index faa2b7a46699d..eb1eed1c8c7bb 100644
> > > --- a/drivers/gpu/drm/i915/display/intel_dp_tunnel.c
> > > +++ b/drivers/gpu/drm/i915/display/intel_dp_tunnel.c
> > > @@ -150,11 +150,9 @@ static int
> > > allocate_initial_tunnel_bw_for_pipes(struct
> > > intel_dp *intel_dp, u8 pi
> > >  			    drm_dp_tunnel_name(intel_dp->tunnel),
> > >  			    encoder->base.base.id, encoder->base.name,
> > >  			    ERR_PTR(err));
> > > -
> > > -		return err;
> > >  	}
> > >
> > > -	return update_tunnel_state(intel_dp);
> > > +	return err;
> > >  }
> > >
> > >  static int allocate_initial_tunnel_bw(struct intel_dp *intel_dp, @@
> > > -200,10
> > > +198,13 @@ static int detect_new_tunnel(struct intel_dp *intel_dp,
> > > +struct
> > > drm_modeset_acqui
> > >  	}
> > >
> > >  	ret = allocate_initial_tunnel_bw(intel_dp, ctx);
> > > -	if (ret < 0)
> > > +	if (ret < 0) {
> > >  		intel_dp_tunnel_destroy(intel_dp);
> > >
> > > -	return ret;
> > > +		return ret;
> > > +	}
> > > +
> > > +	return update_tunnel_state(intel_dp);
> > >  }
> > >
> > >  /**
> > > --
> > > 2.49.1
> >
> > Thanks and Regards,
> > Arun R Murthy
> > --------------------

Re: [PATCH 1/5] drm/i915/dp_tunnel: Don't update tunnel state during system resume

[Imre Deak]

On Tue, Feb 24, 2026 at 04:33:58AM +0200, Murthy, Arun R wrote:
> 
> > -----Original Message-----
> > From: Deak, Imre <imre.deak@intel.com>
> > Sent: Monday, February 23, 2026 10:00 PM
> > To: Murthy, Arun R <arun.r.murthy@intel.com>
> > Cc: intel-gfx@lists.freedesktop.org; intel-xe@lists.freedesktop.org
> > Subject: Re: [PATCH 1/5] drm/i915/dp_tunnel: Don't update tunnel state during
> > system resume
> > 
> > On Mon, Feb 23, 2026 at 05:54:38PM +0200, Murthy, Arun R wrote:
> > >
> > > > -----Original Message-----
> > > > From: Intel-gfx <intel-gfx-bounces@lists.freedesktop.org> On Behalf
> > > > Of Imre Deak
> > > > Sent: Thursday, February 19, 2026 11:58 PM
> > > > To: intel-gfx@lists.freedesktop.org; intel-xe@lists.freedesktop.org
> > > > Subject: [PATCH 1/5] drm/i915/dp_tunnel: Don't update tunnel state
> > > > during system resume
> > > >
> > > > During system resume, restoring the pre-suspend display state must not fail.
> > > > This requires preserving the sink capabilities from before suspend,
> > > > including the available link bandwidth.
> > > >
> > > I don't see the sink capabilities being stored in this patch.
> > 
> > The sink capabilities are stored in intel_dp and intel_connector, including the
> > maximum link rate and lane count, which determine the link bandwidth. This
> > patch preserves those capabilities across suspend/resume by preventing the
> > tunnel state from being updated during resume.
> > 
> I understand, but what I meant was this patch doesn't handle anything
> on the suspend part but only controls the updates on resume.  So
> explaining what happens on resume is un-necessary.

What happens during resume - restoring the state of display outputs to
the pre-suspend state - is what requires the change in this patch.

The commit message must describe the reason for the change, so this
commit must describe what happens during resume.

> Thanks and Regards,
> Arun R Murthy
> --------------------
> > >
> > > > If these capabilities are not preserved, the restore modeset may
> > > > fail, either due to a missing sink capability or insufficient link bandwidth for
> > the restored mode.
> > > Don't see this in the patch.
> > >
> > > >
> > > > When the sink is connected through a DP tunnel, prevent such
> > > > capability changes by skipping tunnel state updates during resume.
> > > > This also avoids updating the sink state via the tunnel while it is being
> > resumed.
> > > >
> > > > Signed-off-by: Imre Deak <imre.deak@intel.com>
> > > > ---
> > > >  drivers/gpu/drm/i915/display/intel_dp_tunnel.c | 11 ++++++-----
> > > >  1 file changed, 6 insertions(+), 5 deletions(-)
> > > >
> > > > diff --git a/drivers/gpu/drm/i915/display/intel_dp_tunnel.c
> > > > b/drivers/gpu/drm/i915/display/intel_dp_tunnel.c
> > > > index faa2b7a46699d..eb1eed1c8c7bb 100644
> > > > --- a/drivers/gpu/drm/i915/display/intel_dp_tunnel.c
> > > > +++ b/drivers/gpu/drm/i915/display/intel_dp_tunnel.c
> > > > @@ -150,11 +150,9 @@ static int
> > > > allocate_initial_tunnel_bw_for_pipes(struct
> > > > intel_dp *intel_dp, u8 pi
> > > >  			    drm_dp_tunnel_name(intel_dp->tunnel),
> > > >  			    encoder->base.base.id, encoder->base.name,
> > > >  			    ERR_PTR(err));
> > > > -
> > > > -		return err;
> > > >  	}
> > > >
> > > > -	return update_tunnel_state(intel_dp);
> > > > +	return err;
> > > >  }
> > > >
> > > >  static int allocate_initial_tunnel_bw(struct intel_dp *intel_dp, @@
> > > > -200,10
> > > > +198,13 @@ static int detect_new_tunnel(struct intel_dp *intel_dp,
> > > > +struct
> > > > drm_modeset_acqui
> > > >  	}
> > > >
> > > >  	ret = allocate_initial_tunnel_bw(intel_dp, ctx);
> > > > -	if (ret < 0)
> > > > +	if (ret < 0) {
> > > >  		intel_dp_tunnel_destroy(intel_dp);
> > > >
> > > > -	return ret;
> > > > +		return ret;
> > > > +	}
> > > > +
> > > > +	return update_tunnel_state(intel_dp);
> > > >  }
> > > >
> > > >  /**
> > > > --
> > > > 2.49.1
> > >
> > > Thanks and Regards,
> > > Arun R Murthy
> > > --------------------

RE: [PATCH 1/5] drm/i915/dp_tunnel: Don't update tunnel state during system resume

[Murthy, Arun R]

Reviewed-by: Arun R Murthy <arun.r.murthy@intel.com>

Thanks and Regards,
Arun R Murthy
--------------------

> -----Original Message-----
> From: Deak, Imre <imre.deak@intel.com>
> Sent: Tuesday, February 24, 2026 1:20 PM
> To: Murthy, Arun R <arun.r.murthy@intel.com>
> Cc: intel-gfx@lists.freedesktop.org; intel-xe@lists.freedesktop.org
> Subject: Re: [PATCH 1/5] drm/i915/dp_tunnel: Don't update tunnel state during
> system resume
> 
> On Tue, Feb 24, 2026 at 04:33:58AM +0200, Murthy, Arun R wrote:
> >
> > > -----Original Message-----
> > > From: Deak, Imre <imre.deak@intel.com>
> > > Sent: Monday, February 23, 2026 10:00 PM
> > > To: Murthy, Arun R <arun.r.murthy@intel.com>
> > > Cc: intel-gfx@lists.freedesktop.org; intel-xe@lists.freedesktop.org
> > > Subject: Re: [PATCH 1/5] drm/i915/dp_tunnel: Don't update tunnel
> > > state during system resume
> > >
> > > On Mon, Feb 23, 2026 at 05:54:38PM +0200, Murthy, Arun R wrote:
> > > >
> > > > > -----Original Message-----
> > > > > From: Intel-gfx <intel-gfx-bounces@lists.freedesktop.org> On
> > > > > Behalf Of Imre Deak
> > > > > Sent: Thursday, February 19, 2026 11:58 PM
> > > > > To: intel-gfx@lists.freedesktop.org;
> > > > > intel-xe@lists.freedesktop.org
> > > > > Subject: [PATCH 1/5] drm/i915/dp_tunnel: Don't update tunnel
> > > > > state during system resume
> > > > >
> > > > > During system resume, restoring the pre-suspend display state must not
> fail.
> > > > > This requires preserving the sink capabilities from before
> > > > > suspend, including the available link bandwidth.
> > > > >
> > > > I don't see the sink capabilities being stored in this patch.
> > >
> > > The sink capabilities are stored in intel_dp and intel_connector,
> > > including the maximum link rate and lane count, which determine the
> > > link bandwidth. This patch preserves those capabilities across
> > > suspend/resume by preventing the tunnel state from being updated during
> resume.
> > >
> > I understand, but what I meant was this patch doesn't handle anything
> > on the suspend part but only controls the updates on resume.  So
> > explaining what happens on resume is un-necessary.
> 
> What happens during resume - restoring the state of display outputs to the pre-
> suspend state - is what requires the change in this patch.
> 
> The commit message must describe the reason for the change, so this commit
> must describe what happens during resume.
> 
> > Thanks and Regards,
> > Arun R Murthy
> > --------------------
> > > >
> > > > > If these capabilities are not preserved, the restore modeset may
> > > > > fail, either due to a missing sink capability or insufficient
> > > > > link bandwidth for
> > > the restored mode.
> > > > Don't see this in the patch.
> > > >
> > > > >
> > > > > When the sink is connected through a DP tunnel, prevent such
> > > > > capability changes by skipping tunnel state updates during resume.
> > > > > This also avoids updating the sink state via the tunnel while it
> > > > > is being
> > > resumed.
> > > > >
> > > > > Signed-off-by: Imre Deak <imre.deak@intel.com>
> > > > > ---
> > > > >  drivers/gpu/drm/i915/display/intel_dp_tunnel.c | 11 ++++++-----
> > > > >  1 file changed, 6 insertions(+), 5 deletions(-)
> > > > >
> > > > > diff --git a/drivers/gpu/drm/i915/display/intel_dp_tunnel.c
> > > > > b/drivers/gpu/drm/i915/display/intel_dp_tunnel.c
> > > > > index faa2b7a46699d..eb1eed1c8c7bb 100644
> > > > > --- a/drivers/gpu/drm/i915/display/intel_dp_tunnel.c
> > > > > +++ b/drivers/gpu/drm/i915/display/intel_dp_tunnel.c
> > > > > @@ -150,11 +150,9 @@ static int
> > > > > allocate_initial_tunnel_bw_for_pipes(struct
> > > > > intel_dp *intel_dp, u8 pi
> > > > >  			    drm_dp_tunnel_name(intel_dp->tunnel),
> > > > >  			    encoder->base.base.id, encoder->base.name,
> > > > >  			    ERR_PTR(err));
> > > > > -
> > > > > -		return err;
> > > > >  	}
> > > > >
> > > > > -	return update_tunnel_state(intel_dp);
> > > > > +	return err;
> > > > >  }
> > > > >
> > > > >  static int allocate_initial_tunnel_bw(struct intel_dp
> > > > > *intel_dp, @@
> > > > > -200,10
> > > > > +198,13 @@ static int detect_new_tunnel(struct intel_dp
> > > > > +*intel_dp, struct
> > > > > drm_modeset_acqui
> > > > >  	}
> > > > >
> > > > >  	ret = allocate_initial_tunnel_bw(intel_dp, ctx);
> > > > > -	if (ret < 0)
> > > > > +	if (ret < 0) {
> > > > >  		intel_dp_tunnel_destroy(intel_dp);
> > > > >
> > > > > -	return ret;
> > > > > +		return ret;
> > > > > +	}
> > > > > +
> > > > > +	return update_tunnel_state(intel_dp);
> > > > >  }
> > > > >
> > > > >  /**
> > > > > --
> > > > > 2.49.1
> > > >
> > > > Thanks and Regards,
> > > > Arun R Murthy
> > > > --------------------

[PATCH 2/5] drm/i915/dp_tunnel: Simplify detection of link BW change

[Imre Deak]

update_tunnel_state() checks whether a tunnel state change (e.g.
available tunnel bandwidth) affects the list of valid modes for the
sink connected through the tunnel. If so, its caller sends a hotplug
event so userspace can re-enumerate the modes.

A change in tunnel bandwidth does not affect the mode list if the
bandwidth was above the sink's DPRX bandwidth both before and after the
update, since in that case the effective bandwidth remains limited by
the DPRX.

As get_current_link_bw() via intel_dp_max_link_data_rate() already
returns bandwidth values clamped to the DPRX limit, the condition for
detecting a mode list change can be simplified to:

    old_bw != new_bw

Remove the explicit checks for whether the bandwidth was below the
maximum DPRX bandwidth before and after the update, and rely on the
clamped bandwidth values instead.

Signed-off-by: Imre Deak <imre.deak@intel.com>
---
 drivers/gpu/drm/i915/display/intel_dp_tunnel.c | 18 +++++-------------
 1 file changed, 5 insertions(+), 13 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_dp_tunnel.c b/drivers/gpu/drm/i915/display/intel_dp_tunnel.c
index eb1eed1c8c7bb..9f3750035f68e 100644
--- a/drivers/gpu/drm/i915/display/intel_dp_tunnel.c
+++ b/drivers/gpu/drm/i915/display/intel_dp_tunnel.c
@@ -54,30 +54,23 @@ static int kbytes_to_mbits(int kbytes)
 	return DIV_ROUND_UP(kbytes * 8, 1000);
 }
 
-static int get_current_link_bw(struct intel_dp *intel_dp,
-			       bool *below_dprx_bw)
+static int get_current_link_bw(struct intel_dp *intel_dp)
 {
 	int rate = intel_dp_max_common_rate(intel_dp);
 	int lane_count = intel_dp_max_common_lane_count(intel_dp);
-	int bw;
 
-	bw = intel_dp_max_link_data_rate(intel_dp, rate, lane_count);
-	*below_dprx_bw = bw < drm_dp_max_dprx_data_rate(rate, lane_count);
-
-	return bw;
+	return intel_dp_max_link_data_rate(intel_dp, rate, lane_count);
 }
 
 static int update_tunnel_state(struct intel_dp *intel_dp)
 {
 	struct intel_display *display = to_intel_display(intel_dp);
 	struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
-	bool old_bw_below_dprx;
-	bool new_bw_below_dprx;
 	int old_bw;
 	int new_bw;
 	int ret;
 
-	old_bw = get_current_link_bw(intel_dp, &old_bw_below_dprx);
+	old_bw = get_current_link_bw(intel_dp);
 
 	ret = drm_dp_tunnel_update_state(intel_dp->tunnel);
 	if (ret < 0) {
@@ -96,11 +89,10 @@ static int update_tunnel_state(struct intel_dp *intel_dp)
 
 	intel_dp_update_sink_caps(intel_dp);
 
-	new_bw = get_current_link_bw(intel_dp, &new_bw_below_dprx);
+	new_bw = get_current_link_bw(intel_dp);
 
 	/* Suppress the notification if the mode list can't change due to bw. */
-	if (old_bw_below_dprx == new_bw_below_dprx &&
-	    !new_bw_below_dprx)
+	if (old_bw == new_bw)
 		return 0;
 
 	drm_dbg_kms(display->drm,
-- 
2.49.1

RE: [PATCH 2/5] drm/i915/dp_tunnel: Simplify detection of link BW change

[Murthy, Arun R]

> -----Original Message-----
> From: Intel-gfx <intel-gfx-bounces@lists.freedesktop.org> On Behalf Of Imre
> Deak
> Sent: Thursday, February 19, 2026 11:58 PM
> To: intel-gfx@lists.freedesktop.org; intel-xe@lists.freedesktop.org
> Subject: [PATCH 2/5] drm/i915/dp_tunnel: Simplify detection of link BW change
> 
> update_tunnel_state() checks whether a tunnel state change (e.g.
> available tunnel bandwidth) affects the list of valid modes for the sink
> connected through the tunnel. If so, its caller sends a hotplug event so
> userspace can re-enumerate the modes.
> 
> A change in tunnel bandwidth does not affect the mode list if the bandwidth
> was above the sink's DPRX bandwidth both before and after the update, since in
> that case the effective bandwidth remains limited by the DPRX.
> 
> As get_current_link_bw() via intel_dp_max_link_data_rate() already returns
> bandwidth values clamped to the DPRX limit, the condition for detecting a
> mode list change can be simplified to:
> 
>     old_bw != new_bw
> 
> Remove the explicit checks for whether the bandwidth was below the
> maximum DPRX bandwidth before and after the update, and rely on the
> clamped bandwidth values instead.
> 
> Signed-off-by: Imre Deak <imre.deak@intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_dp_tunnel.c | 18 +++++-------------
>  1 file changed, 5 insertions(+), 13 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_dp_tunnel.c
> b/drivers/gpu/drm/i915/display/intel_dp_tunnel.c
> index eb1eed1c8c7bb..9f3750035f68e 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp_tunnel.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp_tunnel.c
> @@ -54,30 +54,23 @@ static int kbytes_to_mbits(int kbytes)
>  	return DIV_ROUND_UP(kbytes * 8, 1000);  }
> 
> -static int get_current_link_bw(struct intel_dp *intel_dp,
> -			       bool *below_dprx_bw)
> +static int get_current_link_bw(struct intel_dp *intel_dp)
>  {
>  	int rate = intel_dp_max_common_rate(intel_dp);
>  	int lane_count = intel_dp_max_common_lane_count(intel_dp);
> -	int bw;
> 
> -	bw = intel_dp_max_link_data_rate(intel_dp, rate, lane_count);
> -	*below_dprx_bw = bw < drm_dp_max_dprx_data_rate(rate,
> lane_count);
> -
> -	return bw;
> +	return intel_dp_max_link_data_rate(intel_dp, rate, lane_count);
>  }
Function name says get the current data rate, but we are returning the max data rate here.

Thanks and Regards,
Arun R Murthy
-------------------
> 
>  static int update_tunnel_state(struct intel_dp *intel_dp)  {
>  	struct intel_display *display = to_intel_display(intel_dp);
>  	struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
> -	bool old_bw_below_dprx;
> -	bool new_bw_below_dprx;
>  	int old_bw;
>  	int new_bw;
>  	int ret;
> 
> -	old_bw = get_current_link_bw(intel_dp, &old_bw_below_dprx);
> +	old_bw = get_current_link_bw(intel_dp);
> 
>  	ret = drm_dp_tunnel_update_state(intel_dp->tunnel);
>  	if (ret < 0) {
> @@ -96,11 +89,10 @@ static int update_tunnel_state(struct intel_dp
> *intel_dp)
> 
>  	intel_dp_update_sink_caps(intel_dp);
> 
> -	new_bw = get_current_link_bw(intel_dp, &new_bw_below_dprx);
> +	new_bw = get_current_link_bw(intel_dp);
> 
>  	/* Suppress the notification if the mode list can't change due to bw. */
> -	if (old_bw_below_dprx == new_bw_below_dprx &&
> -	    !new_bw_below_dprx)
> +	if (old_bw == new_bw)
>  		return 0;
> 
>  	drm_dbg_kms(display->drm,
> --
> 2.49.1

Re: [PATCH 2/5] drm/i915/dp_tunnel: Simplify detection of link BW change

[Imre Deak]

On Mon, Feb 23, 2026 at 06:02:26PM +0200, Murthy, Arun R wrote:
> 
> > -----Original Message-----
> > From: Intel-gfx <intel-gfx-bounces@lists.freedesktop.org> On Behalf Of Imre
> > Deak
> > Sent: Thursday, February 19, 2026 11:58 PM
> > To: intel-gfx@lists.freedesktop.org; intel-xe@lists.freedesktop.org
> > Subject: [PATCH 2/5] drm/i915/dp_tunnel: Simplify detection of link BW change
> > 
> > update_tunnel_state() checks whether a tunnel state change (e.g.
> > available tunnel bandwidth) affects the list of valid modes for the sink
> > connected through the tunnel. If so, its caller sends a hotplug event so
> > userspace can re-enumerate the modes.
> > 
> > A change in tunnel bandwidth does not affect the mode list if the bandwidth
> > was above the sink's DPRX bandwidth both before and after the update, since in
> > that case the effective bandwidth remains limited by the DPRX.
> > 
> > As get_current_link_bw() via intel_dp_max_link_data_rate() already returns
> > bandwidth values clamped to the DPRX limit, the condition for detecting a
> > mode list change can be simplified to:
> > 
> >     old_bw != new_bw
> > 
> > Remove the explicit checks for whether the bandwidth was below the
> > maximum DPRX bandwidth before and after the update, and rely on the
> > clamped bandwidth values instead.
> > 
> > Signed-off-by: Imre Deak <imre.deak@intel.com>
> > ---
> >  drivers/gpu/drm/i915/display/intel_dp_tunnel.c | 18 +++++-------------
> >  1 file changed, 5 insertions(+), 13 deletions(-)
> > 
> > diff --git a/drivers/gpu/drm/i915/display/intel_dp_tunnel.c
> > b/drivers/gpu/drm/i915/display/intel_dp_tunnel.c
> > index eb1eed1c8c7bb..9f3750035f68e 100644
> > --- a/drivers/gpu/drm/i915/display/intel_dp_tunnel.c
> > +++ b/drivers/gpu/drm/i915/display/intel_dp_tunnel.c
> > @@ -54,30 +54,23 @@ static int kbytes_to_mbits(int kbytes)
> >  	return DIV_ROUND_UP(kbytes * 8, 1000);  }
> > 
> > -static int get_current_link_bw(struct intel_dp *intel_dp,
> > -			       bool *below_dprx_bw)
> > +static int get_current_link_bw(struct intel_dp *intel_dp)
> >  {
> >  	int rate = intel_dp_max_common_rate(intel_dp);
> >  	int lane_count = intel_dp_max_common_lane_count(intel_dp);
> > -	int bw;
> > 
> > -	bw = intel_dp_max_link_data_rate(intel_dp, rate, lane_count);
> > -	*below_dprx_bw = bw < drm_dp_max_dprx_data_rate(rate,
> > lane_count);
> > -
> > -	return bw;
> > +	return intel_dp_max_link_data_rate(intel_dp, rate, lane_count);
> >  }
>
> Function name says get the current data rate, but we are returning the
> max data rate here.

It is the current link bandwidth, i.e., the link bandwidth allowed by
the Thunderbolt Connection Manager at the moment. It is not a maximum
(which could refer either to the maximum DPRX bandwidth or the maximum
Thunderbolt bandwidth), but rather the amount allowed by all other
components on the Thunderbolt link sharing the same bandwidth.

> 
> Thanks and Regards,
> Arun R Murthy
> -------------------
> > 
> >  static int update_tunnel_state(struct intel_dp *intel_dp)  {
> >  	struct intel_display *display = to_intel_display(intel_dp);
> >  	struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
> > -	bool old_bw_below_dprx;
> > -	bool new_bw_below_dprx;
> >  	int old_bw;
> >  	int new_bw;
> >  	int ret;
> > 
> > -	old_bw = get_current_link_bw(intel_dp, &old_bw_below_dprx);
> > +	old_bw = get_current_link_bw(intel_dp);
> > 
> >  	ret = drm_dp_tunnel_update_state(intel_dp->tunnel);
> >  	if (ret < 0) {
> > @@ -96,11 +89,10 @@ static int update_tunnel_state(struct intel_dp
> > *intel_dp)
> > 
> >  	intel_dp_update_sink_caps(intel_dp);
> > 
> > -	new_bw = get_current_link_bw(intel_dp, &new_bw_below_dprx);
> > +	new_bw = get_current_link_bw(intel_dp);
> > 
> >  	/* Suppress the notification if the mode list can't change due to bw. */
> > -	if (old_bw_below_dprx == new_bw_below_dprx &&
> > -	    !new_bw_below_dprx)
> > +	if (old_bw == new_bw)
> >  		return 0;
> > 
> >  	drm_dbg_kms(display->drm,
> > --
> > 2.49.1
> 

RE: [PATCH 2/5] drm/i915/dp_tunnel: Simplify detection of link BW change

[Murthy, Arun R]

Reviewed-by: Arun R Murthy <arun.r.murthy@intel.com>

Thanks and Regards,
Arun R Murthy
--------------------

> -----Original Message-----
> From: Deak, Imre <imre.deak@intel.com>
> Sent: Monday, February 23, 2026 10:05 PM
> To: Murthy, Arun R <arun.r.murthy@intel.com>
> Cc: intel-gfx@lists.freedesktop.org; intel-xe@lists.freedesktop.org
> Subject: Re: [PATCH 2/5] drm/i915/dp_tunnel: Simplify detection of link BW
> change
> 
> On Mon, Feb 23, 2026 at 06:02:26PM +0200, Murthy, Arun R wrote:
> >
> > > -----Original Message-----
> > > From: Intel-gfx <intel-gfx-bounces@lists.freedesktop.org> On Behalf
> > > Of Imre Deak
> > > Sent: Thursday, February 19, 2026 11:58 PM
> > > To: intel-gfx@lists.freedesktop.org; intel-xe@lists.freedesktop.org
> > > Subject: [PATCH 2/5] drm/i915/dp_tunnel: Simplify detection of link
> > > BW change
> > >
> > > update_tunnel_state() checks whether a tunnel state change (e.g.
> > > available tunnel bandwidth) affects the list of valid modes for the
> > > sink connected through the tunnel. If so, its caller sends a hotplug
> > > event so userspace can re-enumerate the modes.
> > >
> > > A change in tunnel bandwidth does not affect the mode list if the
> > > bandwidth was above the sink's DPRX bandwidth both before and after
> > > the update, since in that case the effective bandwidth remains limited by
> the DPRX.
> > >
> > > As get_current_link_bw() via intel_dp_max_link_data_rate() already
> > > returns bandwidth values clamped to the DPRX limit, the condition
> > > for detecting a mode list change can be simplified to:
> > >
> > >     old_bw != new_bw
> > >
> > > Remove the explicit checks for whether the bandwidth was below the
> > > maximum DPRX bandwidth before and after the update, and rely on the
> > > clamped bandwidth values instead.
> > >
> > > Signed-off-by: Imre Deak <imre.deak@intel.com>
> > > ---
> > >  drivers/gpu/drm/i915/display/intel_dp_tunnel.c | 18
> > > +++++-------------
> > >  1 file changed, 5 insertions(+), 13 deletions(-)
> > >
> > > diff --git a/drivers/gpu/drm/i915/display/intel_dp_tunnel.c
> > > b/drivers/gpu/drm/i915/display/intel_dp_tunnel.c
> > > index eb1eed1c8c7bb..9f3750035f68e 100644
> > > --- a/drivers/gpu/drm/i915/display/intel_dp_tunnel.c
> > > +++ b/drivers/gpu/drm/i915/display/intel_dp_tunnel.c
> > > @@ -54,30 +54,23 @@ static int kbytes_to_mbits(int kbytes)
> > >  	return DIV_ROUND_UP(kbytes * 8, 1000);  }
> > >
> > > -static int get_current_link_bw(struct intel_dp *intel_dp,
> > > -			       bool *below_dprx_bw)
> > > +static int get_current_link_bw(struct intel_dp *intel_dp)
> > >  {
> > >  	int rate = intel_dp_max_common_rate(intel_dp);
> > >  	int lane_count = intel_dp_max_common_lane_count(intel_dp);
> > > -	int bw;
> > >
> > > -	bw = intel_dp_max_link_data_rate(intel_dp, rate, lane_count);
> > > -	*below_dprx_bw = bw < drm_dp_max_dprx_data_rate(rate,
> > > lane_count);
> > > -
> > > -	return bw;
> > > +	return intel_dp_max_link_data_rate(intel_dp, rate, lane_count);
> > >  }
> >
> > Function name says get the current data rate, but we are returning the
> > max data rate here.
> 
> It is the current link bandwidth, i.e., the link bandwidth allowed by the
> Thunderbolt Connection Manager at the moment. It is not a maximum (which
> could refer either to the maximum DPRX bandwidth or the maximum
> Thunderbolt bandwidth), but rather the amount allowed by all other
> components on the Thunderbolt link sharing the same bandwidth.
> 
> >
> > Thanks and Regards,
> > Arun R Murthy
> > -------------------
> > >
> > >  static int update_tunnel_state(struct intel_dp *intel_dp)  {
> > >  	struct intel_display *display = to_intel_display(intel_dp);
> > >  	struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
> > > -	bool old_bw_below_dprx;
> > > -	bool new_bw_below_dprx;
> > >  	int old_bw;
> > >  	int new_bw;
> > >  	int ret;
> > >
> > > -	old_bw = get_current_link_bw(intel_dp, &old_bw_below_dprx);
> > > +	old_bw = get_current_link_bw(intel_dp);
> > >
> > >  	ret = drm_dp_tunnel_update_state(intel_dp->tunnel);
> > >  	if (ret < 0) {
> > > @@ -96,11 +89,10 @@ static int update_tunnel_state(struct intel_dp
> > > *intel_dp)
> > >
> > >  	intel_dp_update_sink_caps(intel_dp);
> > >
> > > -	new_bw = get_current_link_bw(intel_dp, &new_bw_below_dprx);
> > > +	new_bw = get_current_link_bw(intel_dp);
> > >
> > >  	/* Suppress the notification if the mode list can't change due to bw. */
> > > -	if (old_bw_below_dprx == new_bw_below_dprx &&
> > > -	    !new_bw_below_dprx)
> > > +	if (old_bw == new_bw)
> > >  		return 0;
> > >
> > >  	drm_dbg_kms(display->drm,
> > > --
> > > 2.49.1
> >

[PATCH 3/5] drm/i915/dp_tunnel: Split update_tunnel_state()

[Imre Deak]

Split update_tunnel_state() into two helpers: one that updates the
tunnel state, and another that detects whether the tunnel bandwidth
has changed.

This prepares for a follow-up change that needs to compare the current
bandwidth against the value from before the DP tunnel was detected and
bandwidth allocation mode was enabled.

While at it, document the return value of update_tunnel_state().

Signed-off-by: Imre Deak <imre.deak@intel.com>
---
 .../gpu/drm/i915/display/intel_dp_tunnel.c    | 41 +++++++++++++++----
 1 file changed, 34 insertions(+), 7 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_dp_tunnel.c b/drivers/gpu/drm/i915/display/intel_dp_tunnel.c
index 9f3750035f68e..5840b92dace19 100644
--- a/drivers/gpu/drm/i915/display/intel_dp_tunnel.c
+++ b/drivers/gpu/drm/i915/display/intel_dp_tunnel.c
@@ -62,16 +62,12 @@ static int get_current_link_bw(struct intel_dp *intel_dp)
 	return intel_dp_max_link_data_rate(intel_dp, rate, lane_count);
 }
 
-static int update_tunnel_state(struct intel_dp *intel_dp)
+static int __update_tunnel_state(struct intel_dp *intel_dp)
 {
 	struct intel_display *display = to_intel_display(intel_dp);
 	struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
-	int old_bw;
-	int new_bw;
 	int ret;
 
-	old_bw = get_current_link_bw(intel_dp);
-
 	ret = drm_dp_tunnel_update_state(intel_dp->tunnel);
 	if (ret < 0) {
 		drm_dbg_kms(display->drm,
@@ -89,11 +85,20 @@ static int update_tunnel_state(struct intel_dp *intel_dp)
 
 	intel_dp_update_sink_caps(intel_dp);
 
+	return 0;
+}
+
+static bool has_tunnel_bw_changed(struct intel_dp *intel_dp, int old_bw)
+{
+	struct intel_display *display = to_intel_display(intel_dp);
+	struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
+	int new_bw;
+
 	new_bw = get_current_link_bw(intel_dp);
 
 	/* Suppress the notification if the mode list can't change due to bw. */
 	if (old_bw == new_bw)
-		return 0;
+		return false;
 
 	drm_dbg_kms(display->drm,
 		    "[DPTUN %s][ENCODER:%d:%s] Notify users about BW change: %d -> %d\n",
@@ -101,7 +106,29 @@ static int update_tunnel_state(struct intel_dp *intel_dp)
 		    encoder->base.base.id, encoder->base.name,
 		    kbytes_to_mbits(old_bw), kbytes_to_mbits(new_bw));
 
-	return 1;
+	return true;
+}
+
+/*
+ * Returns:
+ * - 0 in case of success - if there wasn't any change in the tunnel state
+ *   requiring a user notification
+ * - 1 in case of success - if there was a change in the tunnel state
+ *   requiring a user notification
+ * - Negative error code if updating the tunnel state failed
+ */
+static int update_tunnel_state(struct intel_dp *intel_dp)
+{
+	int old_bw;
+	int err;
+
+	old_bw = get_current_link_bw(intel_dp);
+
+	err = __update_tunnel_state(intel_dp);
+	if (err)
+		return err;
+
+	return has_tunnel_bw_changed(intel_dp, old_bw) ? 1 : 0;
 }
 
 /*
-- 
2.49.1

RE: [PATCH 3/5] drm/i915/dp_tunnel: Split update_tunnel_state()

[Murthy, Arun R]

Reviewed-by: Arun R Murthy <arun.r.murthy@intel.com>

Thanks and Regards,
Arun R Murthy
--------------------

> -----Original Message-----
> From: Intel-gfx <intel-gfx-bounces@lists.freedesktop.org> On Behalf Of Imre
> Deak
> Sent: Thursday, February 19, 2026 11:58 PM
> To: intel-gfx@lists.freedesktop.org; intel-xe@lists.freedesktop.org
> Subject: [PATCH 3/5] drm/i915/dp_tunnel: Split update_tunnel_state()
> 
> Split update_tunnel_state() into two helpers: one that updates the tunnel state,
> and another that detects whether the tunnel bandwidth has changed.
> 
> This prepares for a follow-up change that needs to compare the current
> bandwidth against the value from before the DP tunnel was detected and
> bandwidth allocation mode was enabled.
> 
> While at it, document the return value of update_tunnel_state().
> 
> Signed-off-by: Imre Deak <imre.deak@intel.com>
> ---
>  .../gpu/drm/i915/display/intel_dp_tunnel.c    | 41 +++++++++++++++----
>  1 file changed, 34 insertions(+), 7 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_dp_tunnel.c
> b/drivers/gpu/drm/i915/display/intel_dp_tunnel.c
> index 9f3750035f68e..5840b92dace19 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp_tunnel.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp_tunnel.c
> @@ -62,16 +62,12 @@ static int get_current_link_bw(struct intel_dp
> *intel_dp)
>  	return intel_dp_max_link_data_rate(intel_dp, rate, lane_count);  }
> 
> -static int update_tunnel_state(struct intel_dp *intel_dp)
> +static int __update_tunnel_state(struct intel_dp *intel_dp)
>  {
>  	struct intel_display *display = to_intel_display(intel_dp);
>  	struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
> -	int old_bw;
> -	int new_bw;
>  	int ret;
> 
> -	old_bw = get_current_link_bw(intel_dp);
> -
>  	ret = drm_dp_tunnel_update_state(intel_dp->tunnel);
>  	if (ret < 0) {
>  		drm_dbg_kms(display->drm,
> @@ -89,11 +85,20 @@ static int update_tunnel_state(struct intel_dp
> *intel_dp)
> 
>  	intel_dp_update_sink_caps(intel_dp);
> 
> +	return 0;
> +}
> +
> +static bool has_tunnel_bw_changed(struct intel_dp *intel_dp, int
> +old_bw) {
> +	struct intel_display *display = to_intel_display(intel_dp);
> +	struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
> +	int new_bw;
> +
>  	new_bw = get_current_link_bw(intel_dp);
> 
>  	/* Suppress the notification if the mode list can't change due to bw. */
>  	if (old_bw == new_bw)
> -		return 0;
> +		return false;
> 
>  	drm_dbg_kms(display->drm,
>  		    "[DPTUN %s][ENCODER:%d:%s] Notify users about BW
> change: %d -> %d\n", @@ -101,7 +106,29 @@ static int
> update_tunnel_state(struct intel_dp *intel_dp)
>  		    encoder->base.base.id, encoder->base.name,
>  		    kbytes_to_mbits(old_bw), kbytes_to_mbits(new_bw));
> 
> -	return 1;
> +	return true;
> +}
> +
> +/*
> + * Returns:
> + * - 0 in case of success - if there wasn't any change in the tunnel state
> + *   requiring a user notification
> + * - 1 in case of success - if there was a change in the tunnel state
> + *   requiring a user notification
> + * - Negative error code if updating the tunnel state failed  */ static
> +int update_tunnel_state(struct intel_dp *intel_dp) {
> +	int old_bw;
> +	int err;
> +
> +	old_bw = get_current_link_bw(intel_dp);
> +
> +	err = __update_tunnel_state(intel_dp);
> +	if (err)
> +		return err;
> +
> +	return has_tunnel_bw_changed(intel_dp, old_bw) ? 1 : 0;
>  }
> 
>  /*
> --
> 2.49.1

[PATCH 4/5] drm/i915/dp_tunnel: Sanitize documentation of intel_dp_tunnel_detect()

[Imre Deak]

Clarify the documentation of detect_new_tunnel() return values,
including the failure case.

Signed-off-by: Imre Deak <imre.deak@intel.com>
---
 drivers/gpu/drm/i915/display/intel_dp_tunnel.c | 9 ++++++---
 1 file changed, 6 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_dp_tunnel.c b/drivers/gpu/drm/i915/display/intel_dp_tunnel.c
index 5840b92dace19..1c552a7091897 100644
--- a/drivers/gpu/drm/i915/display/intel_dp_tunnel.c
+++ b/drivers/gpu/drm/i915/display/intel_dp_tunnel.c
@@ -241,9 +241,12 @@ static int detect_new_tunnel(struct intel_dp *intel_dp, struct drm_modeset_acqui
  * tunnel. If the tunnel's state change requires this - for instance the
  * tunnel's group ID has changed - the tunnel will be dropped and recreated.
  *
- * Return 0 in case of success - after any tunnel detected and added to
- * @intel_dp - 1 in case the BW on an already existing tunnel has changed in a
- * way that requires notifying user space.
+ * Returns:
+ * - 0 in case of success - after any tunnel detected and added to @intel_dp
+ * - 1 in case the link BW via the new or an already existing tunnel has changed
+ *   in a way that requires notifying user space
+ * - Negative error code, if creating a new tunnel or updating the tunnel
+ *   state failed
  */
 int intel_dp_tunnel_detect(struct intel_dp *intel_dp, struct drm_modeset_acquire_ctx *ctx)
 {
-- 
2.49.1

RE: [PATCH 4/5] drm/i915/dp_tunnel: Sanitize documentation of intel_dp_tunnel_detect()

[Murthy, Arun R]

> -----Original Message-----
> From: Intel-gfx <intel-gfx-bounces@lists.freedesktop.org> On Behalf Of Imre
> Deak
> Sent: Thursday, February 19, 2026 11:58 PM
> To: intel-gfx@lists.freedesktop.org; intel-xe@lists.freedesktop.org
> Subject: [PATCH 4/5] drm/i915/dp_tunnel: Sanitize documentation of
> intel_dp_tunnel_detect()
> 
> Clarify the documentation of detect_new_tunnel() return values, including the
> failure case.
> 
Can this change be merged with the previous patch as the previous patch makes this change.

Thanks and Regards,
Arun R Murthy
-------------------
> Signed-off-by: Imre Deak <imre.deak@intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_dp_tunnel.c | 9 ++++++---
>  1 file changed, 6 insertions(+), 3 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_dp_tunnel.c
> b/drivers/gpu/drm/i915/display/intel_dp_tunnel.c
> index 5840b92dace19..1c552a7091897 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp_tunnel.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp_tunnel.c
> @@ -241,9 +241,12 @@ static int detect_new_tunnel(struct intel_dp
> *intel_dp, struct drm_modeset_acqui
>   * tunnel. If the tunnel's state change requires this - for instance the
>   * tunnel's group ID has changed - the tunnel will be dropped and recreated.
>   *
> - * Return 0 in case of success - after any tunnel detected and added to
> - * @intel_dp - 1 in case the BW on an already existing tunnel has changed in a
> - * way that requires notifying user space.
> + * Returns:
> + * - 0 in case of success - after any tunnel detected and added to
> + @intel_dp
> + * - 1 in case the link BW via the new or an already existing tunnel has
> changed
> + *   in a way that requires notifying user space
> + * - Negative error code, if creating a new tunnel or updating the tunnel
> + *   state failed
>   */
>  int intel_dp_tunnel_detect(struct intel_dp *intel_dp, struct
> drm_modeset_acquire_ctx *ctx)  {
> --
> 2.49.1

Re: [PATCH 4/5] drm/i915/dp_tunnel: Sanitize documentation of intel_dp_tunnel_detect()

[Imre Deak]

On Mon, Feb 23, 2026 at 06:12:23PM +0200, Murthy, Arun R wrote:
> 
> > -----Original Message-----
> > From: Intel-gfx <intel-gfx-bounces@lists.freedesktop.org> On Behalf Of Imre
> > Deak
> > Sent: Thursday, February 19, 2026 11:58 PM
> > To: intel-gfx@lists.freedesktop.org; intel-xe@lists.freedesktop.org
> > Subject: [PATCH 4/5] drm/i915/dp_tunnel: Sanitize documentation of
> > intel_dp_tunnel_detect()
> > 
> > Clarify the documentation of detect_new_tunnel() return values, including the
> > failure case.
> > 
>
> Can this change be merged with the previous patch as the previous
> patch makes this change.

There is no functional change. This patch merely clarifies the
formatting of the return value documentation and documents the failure
case, which was already possible before this patchset. Therefore, I
think this is a separate change that should be submitted as a separate
patch.

> Thanks and Regards,
> Arun R Murthy
> -------------------
> > Signed-off-by: Imre Deak <imre.deak@intel.com>
> > ---
> >  drivers/gpu/drm/i915/display/intel_dp_tunnel.c | 9 ++++++---
> >  1 file changed, 6 insertions(+), 3 deletions(-)
> > 
> > diff --git a/drivers/gpu/drm/i915/display/intel_dp_tunnel.c
> > b/drivers/gpu/drm/i915/display/intel_dp_tunnel.c
> > index 5840b92dace19..1c552a7091897 100644
> > --- a/drivers/gpu/drm/i915/display/intel_dp_tunnel.c
> > +++ b/drivers/gpu/drm/i915/display/intel_dp_tunnel.c
> > @@ -241,9 +241,12 @@ static int detect_new_tunnel(struct intel_dp
> > *intel_dp, struct drm_modeset_acqui
> >   * tunnel. If the tunnel's state change requires this - for instance the
> >   * tunnel's group ID has changed - the tunnel will be dropped and recreated.
> >   *
> > - * Return 0 in case of success - after any tunnel detected and added to
> > - * @intel_dp - 1 in case the BW on an already existing tunnel has changed in a
> > - * way that requires notifying user space.
> > + * Returns:
> > + * - 0 in case of success - after any tunnel detected and added to
> > + @intel_dp
> > + * - 1 in case the link BW via the new or an already existing tunnel has
> > changed
> > + *   in a way that requires notifying user space
> > + * - Negative error code, if creating a new tunnel or updating the tunnel
> > + *   state failed
> >   */
> >  int intel_dp_tunnel_detect(struct intel_dp *intel_dp, struct
> > drm_modeset_acquire_ctx *ctx)  {
> > --
> > 2.49.1
> 

RE: [PATCH 4/5] drm/i915/dp_tunnel: Sanitize documentation of intel_dp_tunnel_detect()

[Murthy, Arun R]

> -----Original Message-----
> From: Deak, Imre <imre.deak@intel.com>
> Sent: Monday, February 23, 2026 10:15 PM
> To: Murthy, Arun R <arun.r.murthy@intel.com>
> Cc: intel-gfx@lists.freedesktop.org; intel-xe@lists.freedesktop.org
> Subject: Re: [PATCH 4/5] drm/i915/dp_tunnel: Sanitize documentation of
> intel_dp_tunnel_detect()
> 
> On Mon, Feb 23, 2026 at 06:12:23PM +0200, Murthy, Arun R wrote:
> >
> > > -----Original Message-----
> > > From: Intel-gfx <intel-gfx-bounces@lists.freedesktop.org> On Behalf
> > > Of Imre Deak
> > > Sent: Thursday, February 19, 2026 11:58 PM
> > > To: intel-gfx@lists.freedesktop.org; intel-xe@lists.freedesktop.org
> > > Subject: [PATCH 4/5] drm/i915/dp_tunnel: Sanitize documentation of
> > > intel_dp_tunnel_detect()
> > >
> > > Clarify the documentation of detect_new_tunnel() return values,
> > > including the failure case.
> > >
> >
> > Can this change be merged with the previous patch as the previous
> > patch makes this change.
> 
> There is no functional change. This patch merely clarifies the formatting of the
> return value documentation and documents the failure case, which was already
> possible before this patchset. Therefore, I think this is a separate change that
> should be submitted as a separate patch.
> 
This change in the return value was introduced in the previous patch, so updating the function header documentation  in the same patch would be better.

Thanks and Regards,
Arun R Murthy
--------------------
> > Thanks and Regards,
> > Arun R Murthy
> > -------------------
> > > Signed-off-by: Imre Deak <imre.deak@intel.com>
> > > ---
> > >  drivers/gpu/drm/i915/display/intel_dp_tunnel.c | 9 ++++++---
> > >  1 file changed, 6 insertions(+), 3 deletions(-)
> > >
> > > diff --git a/drivers/gpu/drm/i915/display/intel_dp_tunnel.c
> > > b/drivers/gpu/drm/i915/display/intel_dp_tunnel.c
> > > index 5840b92dace19..1c552a7091897 100644
> > > --- a/drivers/gpu/drm/i915/display/intel_dp_tunnel.c
> > > +++ b/drivers/gpu/drm/i915/display/intel_dp_tunnel.c
> > > @@ -241,9 +241,12 @@ static int detect_new_tunnel(struct intel_dp
> > > *intel_dp, struct drm_modeset_acqui
> > >   * tunnel. If the tunnel's state change requires this - for instance the
> > >   * tunnel's group ID has changed - the tunnel will be dropped and
> recreated.
> > >   *
> > > - * Return 0 in case of success - after any tunnel detected and
> > > added to
> > > - * @intel_dp - 1 in case the BW on an already existing tunnel has
> > > changed in a
> > > - * way that requires notifying user space.
> > > + * Returns:
> > > + * - 0 in case of success - after any tunnel detected and added to
> > > + @intel_dp
> > > + * - 1 in case the link BW via the new or an already existing
> > > + tunnel has
> > > changed
> > > + *   in a way that requires notifying user space
> > > + * - Negative error code, if creating a new tunnel or updating the tunnel
> > > + *   state failed
> > >   */
> > >  int intel_dp_tunnel_detect(struct intel_dp *intel_dp, struct
> > > drm_modeset_acquire_ctx *ctx)  {
> > > --
> > > 2.49.1
> >

Re: [PATCH 4/5] drm/i915/dp_tunnel: Sanitize documentation of intel_dp_tunnel_detect()

[Imre Deak]

On Tue, Feb 24, 2026 at 04:36:41AM +0200, Murthy, Arun R wrote:
> 
> > -----Original Message-----
> > From: Deak, Imre <imre.deak@intel.com>
> > Sent: Monday, February 23, 2026 10:15 PM
> > To: Murthy, Arun R <arun.r.murthy@intel.com>
> > Cc: intel-gfx@lists.freedesktop.org; intel-xe@lists.freedesktop.org
> > Subject: Re: [PATCH 4/5] drm/i915/dp_tunnel: Sanitize documentation of
> > intel_dp_tunnel_detect()
> > 
> > On Mon, Feb 23, 2026 at 06:12:23PM +0200, Murthy, Arun R wrote:
> > >
> > > > -----Original Message-----
> > > > From: Intel-gfx <intel-gfx-bounces@lists.freedesktop.org> On Behalf
> > > > Of Imre Deak
> > > > Sent: Thursday, February 19, 2026 11:58 PM
> > > > To: intel-gfx@lists.freedesktop.org; intel-xe@lists.freedesktop.org
> > > > Subject: [PATCH 4/5] drm/i915/dp_tunnel: Sanitize documentation of
> > > > intel_dp_tunnel_detect()
> > > >
> > > > Clarify the documentation of detect_new_tunnel() return values,
> > > > including the failure case.
> > > >
> > >
> > > Can this change be merged with the previous patch as the previous
> > > patch makes this change.
> > 
> > There is no functional change. This patch merely clarifies the formatting of the
> > return value documentation and documents the failure case, which was already
> > possible before this patchset. Therefore, I think this is a separate change that
> > should be submitted as a separate patch.
> > 
> This change in the return value was introduced in the previous patch,
> so updating the function header documentation  in the same patch would
> be better.

There is no change in the return value of the function, either in the
previous patch or in any other patch of the patchset; the function's
return value remains the same as it was before the patchset, this change
only clarifies the function documentation.

> Thanks and Regards,
> Arun R Murthy
> --------------------
> > > Thanks and Regards,
> > > Arun R Murthy
> > > -------------------
> > > > Signed-off-by: Imre Deak <imre.deak@intel.com>
> > > > ---
> > > >  drivers/gpu/drm/i915/display/intel_dp_tunnel.c | 9 ++++++---
> > > >  1 file changed, 6 insertions(+), 3 deletions(-)
> > > >
> > > > diff --git a/drivers/gpu/drm/i915/display/intel_dp_tunnel.c
> > > > b/drivers/gpu/drm/i915/display/intel_dp_tunnel.c
> > > > index 5840b92dace19..1c552a7091897 100644
> > > > --- a/drivers/gpu/drm/i915/display/intel_dp_tunnel.c
> > > > +++ b/drivers/gpu/drm/i915/display/intel_dp_tunnel.c
> > > > @@ -241,9 +241,12 @@ static int detect_new_tunnel(struct intel_dp
> > > > *intel_dp, struct drm_modeset_acqui
> > > >   * tunnel. If the tunnel's state change requires this - for instance the
> > > >   * tunnel's group ID has changed - the tunnel will be dropped and
> > recreated.
> > > >   *
> > > > - * Return 0 in case of success - after any tunnel detected and
> > > > added to
> > > > - * @intel_dp - 1 in case the BW on an already existing tunnel has
> > > > changed in a
> > > > - * way that requires notifying user space.
> > > > + * Returns:
> > > > + * - 0 in case of success - after any tunnel detected and added to
> > > > + @intel_dp
> > > > + * - 1 in case the link BW via the new or an already existing
> > > > + tunnel has
> > > > changed
> > > > + *   in a way that requires notifying user space
> > > > + * - Negative error code, if creating a new tunnel or updating the tunnel
> > > > + *   state failed
> > > >   */
> > > >  int intel_dp_tunnel_detect(struct intel_dp *intel_dp, struct
> > > > drm_modeset_acquire_ctx *ctx)  {
> > > > --
> > > > 2.49.1
> > >

RE: [PATCH 4/5] drm/i915/dp_tunnel: Sanitize documentation of intel_dp_tunnel_detect()

[Murthy, Arun R]

Reviewed-by: Arun R Murthy <arun.r.murthy@intel.com>

Thanks and Regards,
Arun R Murthy
--------------------

> -----Original Message-----
> From: Deak, Imre <imre.deak@intel.com>
> Sent: Tuesday, February 24, 2026 1:25 PM
> To: Murthy, Arun R <arun.r.murthy@intel.com>
> Cc: intel-gfx@lists.freedesktop.org; intel-xe@lists.freedesktop.org
> Subject: Re: [PATCH 4/5] drm/i915/dp_tunnel: Sanitize documentation of
> intel_dp_tunnel_detect()
> 
> On Tue, Feb 24, 2026 at 04:36:41AM +0200, Murthy, Arun R wrote:
> >
> > > -----Original Message-----
> > > From: Deak, Imre <imre.deak@intel.com>
> > > Sent: Monday, February 23, 2026 10:15 PM
> > > To: Murthy, Arun R <arun.r.murthy@intel.com>
> > > Cc: intel-gfx@lists.freedesktop.org; intel-xe@lists.freedesktop.org
> > > Subject: Re: [PATCH 4/5] drm/i915/dp_tunnel: Sanitize documentation
> > > of
> > > intel_dp_tunnel_detect()
> > >
> > > On Mon, Feb 23, 2026 at 06:12:23PM +0200, Murthy, Arun R wrote:
> > > >
> > > > > -----Original Message-----
> > > > > From: Intel-gfx <intel-gfx-bounces@lists.freedesktop.org> On
> > > > > Behalf Of Imre Deak
> > > > > Sent: Thursday, February 19, 2026 11:58 PM
> > > > > To: intel-gfx@lists.freedesktop.org;
> > > > > intel-xe@lists.freedesktop.org
> > > > > Subject: [PATCH 4/5] drm/i915/dp_tunnel: Sanitize documentation
> > > > > of
> > > > > intel_dp_tunnel_detect()
> > > > >
> > > > > Clarify the documentation of detect_new_tunnel() return values,
> > > > > including the failure case.
> > > > >
> > > >
> > > > Can this change be merged with the previous patch as the previous
> > > > patch makes this change.
> > >
> > > There is no functional change. This patch merely clarifies the
> > > formatting of the return value documentation and documents the
> > > failure case, which was already possible before this patchset.
> > > Therefore, I think this is a separate change that should be submitted as a
> separate patch.
> > >
> > This change in the return value was introduced in the previous patch,
> > so updating the function header documentation  in the same patch would
> > be better.
> 
> There is no change in the return value of the function, either in the previous
> patch or in any other patch of the patchset; the function's return value remains
> the same as it was before the patchset, this change only clarifies the function
> documentation.
> 
> > Thanks and Regards,
> > Arun R Murthy
> > --------------------
> > > > Thanks and Regards,
> > > > Arun R Murthy
> > > > -------------------
> > > > > Signed-off-by: Imre Deak <imre.deak@intel.com>
> > > > > ---
> > > > >  drivers/gpu/drm/i915/display/intel_dp_tunnel.c | 9 ++++++---
> > > > >  1 file changed, 6 insertions(+), 3 deletions(-)
> > > > >
> > > > > diff --git a/drivers/gpu/drm/i915/display/intel_dp_tunnel.c
> > > > > b/drivers/gpu/drm/i915/display/intel_dp_tunnel.c
> > > > > index 5840b92dace19..1c552a7091897 100644
> > > > > --- a/drivers/gpu/drm/i915/display/intel_dp_tunnel.c
> > > > > +++ b/drivers/gpu/drm/i915/display/intel_dp_tunnel.c
> > > > > @@ -241,9 +241,12 @@ static int detect_new_tunnel(struct
> > > > > intel_dp *intel_dp, struct drm_modeset_acqui
> > > > >   * tunnel. If the tunnel's state change requires this - for instance the
> > > > >   * tunnel's group ID has changed - the tunnel will be dropped
> > > > > and
> > > recreated.
> > > > >   *
> > > > > - * Return 0 in case of success - after any tunnel detected and
> > > > > added to
> > > > > - * @intel_dp - 1 in case the BW on an already existing tunnel
> > > > > has changed in a
> > > > > - * way that requires notifying user space.
> > > > > + * Returns:
> > > > > + * - 0 in case of success - after any tunnel detected and added
> > > > > + to @intel_dp
> > > > > + * - 1 in case the link BW via the new or an already existing
> > > > > + tunnel has
> > > > > changed
> > > > > + *   in a way that requires notifying user space
> > > > > + * - Negative error code, if creating a new tunnel or updating the tunnel
> > > > > + *   state failed
> > > > >   */
> > > > >  int intel_dp_tunnel_detect(struct intel_dp *intel_dp, struct
> > > > > drm_modeset_acquire_ctx *ctx)  {
> > > > > --
> > > > > 2.49.1
> > > >

[PATCH 5/5] drm/i915/dp_tunnel: Send BW change notification after tunnel creation

[Imre Deak]

Detecting a bandwidth change for a sink connected through a DP tunnel
depends on updating the sink's DPRX link rate and lane count.

detect_new_tunnel() -> update_tunnel_state() updates the link
configuration only if the tunnel state changes. However, after the
tunnel is created and bandwidth allocation mode is enabled, the tunnel
state itself may remain unchanged.

Record the sink bandwidth before creating the tunnel and compare it to
the bandwidth after tunnel creation and enabling bandwidth allocation
mode, ensuring that any bandwidth change is detected and userspace is
notified accordingly.

Signed-off-by: Imre Deak <imre.deak@intel.com>
---
 .../gpu/drm/i915/display/intel_dp_tunnel.c    | 25 +++++++++++++++----
 1 file changed, 20 insertions(+), 5 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_dp_tunnel.c b/drivers/gpu/drm/i915/display/intel_dp_tunnel.c
index 1c552a7091897..4b743387b15a6 100644
--- a/drivers/gpu/drm/i915/display/intel_dp_tunnel.c
+++ b/drivers/gpu/drm/i915/display/intel_dp_tunnel.c
@@ -62,7 +62,7 @@ static int get_current_link_bw(struct intel_dp *intel_dp)
 	return intel_dp_max_link_data_rate(intel_dp, rate, lane_count);
 }
 
-static int __update_tunnel_state(struct intel_dp *intel_dp)
+static int __update_tunnel_state(struct intel_dp *intel_dp, bool force_sink_update)
 {
 	struct intel_display *display = to_intel_display(intel_dp);
 	struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
@@ -79,8 +79,8 @@ static int __update_tunnel_state(struct intel_dp *intel_dp)
 		return ret;
 	}
 
-	if (ret == 0 ||
-	    !drm_dp_tunnel_bw_alloc_is_enabled(intel_dp->tunnel))
+	if (!force_sink_update &&
+	    (ret == 0 || !drm_dp_tunnel_bw_alloc_is_enabled(intel_dp->tunnel)))
 		return 0;
 
 	intel_dp_update_sink_caps(intel_dp);
@@ -124,7 +124,7 @@ static int update_tunnel_state(struct intel_dp *intel_dp)
 
 	old_bw = get_current_link_bw(intel_dp);
 
-	err = __update_tunnel_state(intel_dp);
+	err = __update_tunnel_state(intel_dp, false);
 	if (err)
 		return err;
 
@@ -187,13 +187,24 @@ static int allocate_initial_tunnel_bw(struct intel_dp *intel_dp,
 	return allocate_initial_tunnel_bw_for_pipes(intel_dp, pipe_mask);
 }
 
+/*
+ * Returns:
+ * - 0 in case of success - after any tunnel detected and added to @intel_dp
+ * - 1 in case of success - after a tunnel detected and added to @intel_dp,
+ *   where the link BW via the tunnel changed in a way requiring a user
+ *   notification
+ * - Negative error code if the tunnel detection failed
+ */
 static int detect_new_tunnel(struct intel_dp *intel_dp, struct drm_modeset_acquire_ctx *ctx)
 {
 	struct intel_display *display = to_intel_display(intel_dp);
 	struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
 	struct drm_dp_tunnel *tunnel;
+	int old_bw;
 	int ret;
 
+	old_bw = get_current_link_bw(intel_dp);
+
 	tunnel = drm_dp_tunnel_detect(display->dp_tunnel_mgr,
 				      &intel_dp->aux);
 	if (IS_ERR(tunnel))
@@ -223,7 +234,11 @@ static int detect_new_tunnel(struct intel_dp *intel_dp, struct drm_modeset_acqui
 		return ret;
 	}
 
-	return update_tunnel_state(intel_dp);
+	ret = __update_tunnel_state(intel_dp, true);
+	if (ret)
+		return ret;
+
+	return has_tunnel_bw_changed(intel_dp, old_bw) ? 1 : 0;
 }
 
 /**
-- 
2.49.1

RE: [PATCH 5/5] drm/i915/dp_tunnel: Send BW change notification after tunnel creation

[Murthy, Arun R]

Reviewed-by: Arun R Murthy <arun.r.murthy@intel.com>

Thanks and Regards,
Arun R Murthy
--------------------

> -----Original Message-----
> From: Intel-gfx <intel-gfx-bounces@lists.freedesktop.org> On Behalf Of Imre
> Deak
> Sent: Thursday, February 19, 2026 11:58 PM
> To: intel-gfx@lists.freedesktop.org; intel-xe@lists.freedesktop.org
> Subject: [PATCH 5/5] drm/i915/dp_tunnel: Send BW change notification after
> tunnel creation
> 
> Detecting a bandwidth change for a sink connected through a DP tunnel
> depends on updating the sink's DPRX link rate and lane count.
> 
> detect_new_tunnel() -> update_tunnel_state() updates the link configuration
> only if the tunnel state changes. However, after the tunnel is created and
> bandwidth allocation mode is enabled, the tunnel state itself may remain
> unchanged.
> 
> Record the sink bandwidth before creating the tunnel and compare it to the
> bandwidth after tunnel creation and enabling bandwidth allocation mode,
> ensuring that any bandwidth change is detected and userspace is notified
> accordingly.
> 
> Signed-off-by: Imre Deak <imre.deak@intel.com>
> ---
>  .../gpu/drm/i915/display/intel_dp_tunnel.c    | 25 +++++++++++++++----
>  1 file changed, 20 insertions(+), 5 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_dp_tunnel.c
> b/drivers/gpu/drm/i915/display/intel_dp_tunnel.c
> index 1c552a7091897..4b743387b15a6 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp_tunnel.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp_tunnel.c
> @@ -62,7 +62,7 @@ static int get_current_link_bw(struct intel_dp *intel_dp)
>  	return intel_dp_max_link_data_rate(intel_dp, rate, lane_count);  }
> 
> -static int __update_tunnel_state(struct intel_dp *intel_dp)
> +static int __update_tunnel_state(struct intel_dp *intel_dp, bool
> +force_sink_update)
>  {
>  	struct intel_display *display = to_intel_display(intel_dp);
>  	struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base; @@
> -79,8 +79,8 @@ static int __update_tunnel_state(struct intel_dp *intel_dp)
>  		return ret;
>  	}
> 
> -	if (ret == 0 ||
> -	    !drm_dp_tunnel_bw_alloc_is_enabled(intel_dp->tunnel))
> +	if (!force_sink_update &&
> +	    (ret == 0 ||
> +!drm_dp_tunnel_bw_alloc_is_enabled(intel_dp->tunnel)))
>  		return 0;
> 
>  	intel_dp_update_sink_caps(intel_dp);
> @@ -124,7 +124,7 @@ static int update_tunnel_state(struct intel_dp
> *intel_dp)
> 
>  	old_bw = get_current_link_bw(intel_dp);
> 
> -	err = __update_tunnel_state(intel_dp);
> +	err = __update_tunnel_state(intel_dp, false);
>  	if (err)
>  		return err;
> 
> @@ -187,13 +187,24 @@ static int allocate_initial_tunnel_bw(struct intel_dp
> *intel_dp,
>  	return allocate_initial_tunnel_bw_for_pipes(intel_dp, pipe_mask);  }
> 
> +/*
> + * Returns:
> + * - 0 in case of success - after any tunnel detected and added to
> +@intel_dp
> + * - 1 in case of success - after a tunnel detected and added to @intel_dp,
> + *   where the link BW via the tunnel changed in a way requiring a user
> + *   notification
> + * - Negative error code if the tunnel detection failed  */
>  static int detect_new_tunnel(struct intel_dp *intel_dp, struct
> drm_modeset_acquire_ctx *ctx)  {
>  	struct intel_display *display = to_intel_display(intel_dp);
>  	struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
>  	struct drm_dp_tunnel *tunnel;
> +	int old_bw;
>  	int ret;
> 
> +	old_bw = get_current_link_bw(intel_dp);
> +
>  	tunnel = drm_dp_tunnel_detect(display->dp_tunnel_mgr,
>  				      &intel_dp->aux);
>  	if (IS_ERR(tunnel))
> @@ -223,7 +234,11 @@ static int detect_new_tunnel(struct intel_dp
> *intel_dp, struct drm_modeset_acqui
>  		return ret;
>  	}
> 
> -	return update_tunnel_state(intel_dp);
> +	ret = __update_tunnel_state(intel_dp, true);
> +	if (ret)
> +		return ret;
> +
> +	return has_tunnel_bw_changed(intel_dp, old_bw) ? 1 : 0;
>  }
> 
>  /**
> --
> 2.49.1

✓ CI.KUnit: success for drm/i915/dp_tunnel: Preparation for UHBR DP tunnels

[Patchwork]

== Series Details ==

Series: drm/i915/dp_tunnel: Preparation for UHBR DP tunnels
URL   : https://patchwork.freedesktop.org/series/161848/
State : success

== Summary ==

+ trap cleanup EXIT
+ /kernel/tools/testing/kunit/kunit.py run --kunitconfig /kernel/drivers/gpu/drm/xe/.kunitconfig
[19:27:16] Configuring KUnit Kernel ...
Generating .config ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
[19:27:20] Building KUnit Kernel ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
Building with:
$ make all compile_commands.json scripts_gdb ARCH=um O=.kunit --jobs=48
[19:27:52] Starting KUnit Kernel (1/1)...
[19:27:52] ============================================================
Running tests with:
$ .kunit/linux kunit.enable=1 mem=1G console=tty kunit_shutdown=halt
[19:27:52] ================== guc_buf (11 subtests) ===================
[19:27:52] [PASSED] test_smallest
[19:27:52] [PASSED] test_largest
[19:27:52] [PASSED] test_granular
[19:27:52] [PASSED] test_unique
[19:27:52] [PASSED] test_overlap
[19:27:52] [PASSED] test_reusable
[19:27:52] [PASSED] test_too_big
[19:27:52] [PASSED] test_flush
[19:27:52] [PASSED] test_lookup
[19:27:52] [PASSED] test_data
[19:27:52] [PASSED] test_class
[19:27:52] ===================== [PASSED] guc_buf =====================
[19:27:52] =================== guc_dbm (7 subtests) ===================
[19:27:52] [PASSED] test_empty
[19:27:52] [PASSED] test_default
[19:27:52] ======================== test_size  ========================
[19:27:52] [PASSED] 4
[19:27:52] [PASSED] 8
[19:27:52] [PASSED] 32
[19:27:52] [PASSED] 256
[19:27:52] ==================== [PASSED] test_size ====================
[19:27:52] ======================= test_reuse  ========================
[19:27:52] [PASSED] 4
[19:27:52] [PASSED] 8
[19:27:52] [PASSED] 32
[19:27:52] [PASSED] 256
[19:27:52] =================== [PASSED] test_reuse ====================
[19:27:52] =================== test_range_overlap  ====================
[19:27:52] [PASSED] 4
[19:27:52] [PASSED] 8
[19:27:52] [PASSED] 32
[19:27:52] [PASSED] 256
[19:27:52] =============== [PASSED] test_range_overlap ================
[19:27:52] =================== test_range_compact  ====================
[19:27:52] [PASSED] 4
[19:27:52] [PASSED] 8
[19:27:52] [PASSED] 32
[19:27:52] [PASSED] 256
[19:27:52] =============== [PASSED] test_range_compact ================
[19:27:52] ==================== test_range_spare  =====================
[19:27:52] [PASSED] 4
[19:27:52] [PASSED] 8
[19:27:52] [PASSED] 32
[19:27:52] [PASSED] 256
[19:27:52] ================ [PASSED] test_range_spare =================
[19:27:52] ===================== [PASSED] guc_dbm =====================
[19:27:52] =================== guc_idm (6 subtests) ===================
[19:27:52] [PASSED] bad_init
[19:27:52] [PASSED] no_init
[19:27:52] [PASSED] init_fini
[19:27:52] [PASSED] check_used
[19:27:52] [PASSED] check_quota
[19:27:52] [PASSED] check_all
[19:27:52] ===================== [PASSED] guc_idm =====================
[19:27:52] ================== no_relay (3 subtests) ===================
[19:27:52] [PASSED] xe_drops_guc2pf_if_not_ready
[19:27:52] [PASSED] xe_drops_guc2vf_if_not_ready
[19:27:52] [PASSED] xe_rejects_send_if_not_ready
[19:27:52] ==================== [PASSED] no_relay =====================
[19:27:52] ================== pf_relay (14 subtests) ==================
[19:27:52] [PASSED] pf_rejects_guc2pf_too_short
[19:27:52] [PASSED] pf_rejects_guc2pf_too_long
[19:27:52] [PASSED] pf_rejects_guc2pf_no_payload
[19:27:52] [PASSED] pf_fails_no_payload
[19:27:52] [PASSED] pf_fails_bad_origin
[19:27:52] [PASSED] pf_fails_bad_type
[19:27:52] [PASSED] pf_txn_reports_error
[19:27:52] [PASSED] pf_txn_sends_pf2guc
[19:27:52] [PASSED] pf_sends_pf2guc
[19:27:52] [SKIPPED] pf_loopback_nop
[19:27:52] [SKIPPED] pf_loopback_echo
[19:27:52] [SKIPPED] pf_loopback_fail
[19:27:52] [SKIPPED] pf_loopback_busy
[19:27:52] [SKIPPED] pf_loopback_retry
[19:27:52] ==================== [PASSED] pf_relay =====================
[19:27:52] ================== vf_relay (3 subtests) ===================
[19:27:52] [PASSED] vf_rejects_guc2vf_too_short
[19:27:52] [PASSED] vf_rejects_guc2vf_too_long
[19:27:52] [PASSED] vf_rejects_guc2vf_no_payload
[19:27:52] ==================== [PASSED] vf_relay =====================
[19:27:52] ================ pf_gt_config (6 subtests) =================
[19:27:52] [PASSED] fair_contexts_1vf
[19:27:52] [PASSED] fair_doorbells_1vf
[19:27:52] [PASSED] fair_ggtt_1vf
[19:27:52] ====================== fair_contexts  ======================
[19:27:52] [PASSED] 1 VF
[19:27:52] [PASSED] 2 VFs
[19:27:52] [PASSED] 3 VFs
[19:27:52] [PASSED] 4 VFs
[19:27:52] [PASSED] 5 VFs
[19:27:52] [PASSED] 6 VFs
[19:27:52] [PASSED] 7 VFs
[19:27:52] [PASSED] 8 VFs
[19:27:52] [PASSED] 9 VFs
[19:27:52] [PASSED] 10 VFs
[19:27:52] [PASSED] 11 VFs
[19:27:52] [PASSED] 12 VFs
[19:27:52] [PASSED] 13 VFs
[19:27:52] [PASSED] 14 VFs
[19:27:52] [PASSED] 15 VFs
[19:27:52] [PASSED] 16 VFs
[19:27:52] [PASSED] 17 VFs
[19:27:52] [PASSED] 18 VFs
[19:27:52] [PASSED] 19 VFs
[19:27:52] [PASSED] 20 VFs
[19:27:52] [PASSED] 21 VFs
[19:27:52] [PASSED] 22 VFs
[19:27:52] [PASSED] 23 VFs
[19:27:52] [PASSED] 24 VFs
[19:27:52] [PASSED] 25 VFs
[19:27:52] [PASSED] 26 VFs
[19:27:52] [PASSED] 27 VFs
[19:27:52] [PASSED] 28 VFs
[19:27:52] [PASSED] 29 VFs
[19:27:52] [PASSED] 30 VFs
[19:27:52] [PASSED] 31 VFs
[19:27:52] [PASSED] 32 VFs
[19:27:52] [PASSED] 33 VFs
[19:27:52] [PASSED] 34 VFs
[19:27:52] [PASSED] 35 VFs
[19:27:52] [PASSED] 36 VFs
[19:27:52] [PASSED] 37 VFs
[19:27:52] [PASSED] 38 VFs
[19:27:52] [PASSED] 39 VFs
[19:27:52] [PASSED] 40 VFs
[19:27:52] [PASSED] 41 VFs
[19:27:52] [PASSED] 42 VFs
[19:27:52] [PASSED] 43 VFs
[19:27:52] [PASSED] 44 VFs
[19:27:52] [PASSED] 45 VFs
[19:27:52] [PASSED] 46 VFs
[19:27:52] [PASSED] 47 VFs
[19:27:52] [PASSED] 48 VFs
[19:27:52] [PASSED] 49 VFs
[19:27:52] [PASSED] 50 VFs
[19:27:52] [PASSED] 51 VFs
[19:27:52] [PASSED] 52 VFs
[19:27:52] [PASSED] 53 VFs
[19:27:52] [PASSED] 54 VFs
[19:27:52] [PASSED] 55 VFs
[19:27:52] [PASSED] 56 VFs
[19:27:52] [PASSED] 57 VFs
[19:27:52] [PASSED] 58 VFs
[19:27:52] [PASSED] 59 VFs
[19:27:52] [PASSED] 60 VFs
[19:27:52] [PASSED] 61 VFs
[19:27:52] [PASSED] 62 VFs
[19:27:52] [PASSED] 63 VFs
[19:27:52] ================== [PASSED] fair_contexts ==================
[19:27:52] ===================== fair_doorbells  ======================
[19:27:52] [PASSED] 1 VF
[19:27:52] [PASSED] 2 VFs
[19:27:52] [PASSED] 3 VFs
[19:27:52] [PASSED] 4 VFs
[19:27:52] [PASSED] 5 VFs
[19:27:52] [PASSED] 6 VFs
[19:27:52] [PASSED] 7 VFs
[19:27:52] [PASSED] 8 VFs
[19:27:52] [PASSED] 9 VFs
[19:27:52] [PASSED] 10 VFs
[19:27:52] [PASSED] 11 VFs
[19:27:52] [PASSED] 12 VFs
[19:27:52] [PASSED] 13 VFs
[19:27:52] [PASSED] 14 VFs
[19:27:52] [PASSED] 15 VFs
[19:27:52] [PASSED] 16 VFs
[19:27:52] [PASSED] 17 VFs
[19:27:52] [PASSED] 18 VFs
[19:27:52] [PASSED] 19 VFs
[19:27:52] [PASSED] 20 VFs
[19:27:52] [PASSED] 21 VFs
[19:27:52] [PASSED] 22 VFs
[19:27:52] [PASSED] 23 VFs
[19:27:52] [PASSED] 24 VFs
[19:27:52] [PASSED] 25 VFs
[19:27:52] [PASSED] 26 VFs
[19:27:52] [PASSED] 27 VFs
[19:27:52] [PASSED] 28 VFs
[19:27:52] [PASSED] 29 VFs
[19:27:52] [PASSED] 30 VFs
[19:27:52] [PASSED] 31 VFs
[19:27:52] [PASSED] 32 VFs
[19:27:52] [PASSED] 33 VFs
[19:27:52] [PASSED] 34 VFs
[19:27:52] [PASSED] 35 VFs
[19:27:52] [PASSED] 36 VFs
[19:27:52] [PASSED] 37 VFs
[19:27:52] [PASSED] 38 VFs
[19:27:52] [PASSED] 39 VFs
[19:27:52] [PASSED] 40 VFs
[19:27:52] [PASSED] 41 VFs
[19:27:52] [PASSED] 42 VFs
[19:27:52] [PASSED] 43 VFs
[19:27:52] [PASSED] 44 VFs
[19:27:52] [PASSED] 45 VFs
[19:27:52] [PASSED] 46 VFs
[19:27:52] [PASSED] 47 VFs
[19:27:52] [PASSED] 48 VFs
[19:27:52] [PASSED] 49 VFs
[19:27:52] [PASSED] 50 VFs
[19:27:52] [PASSED] 51 VFs
[19:27:52] [PASSED] 52 VFs
[19:27:52] [PASSED] 53 VFs
[19:27:52] [PASSED] 54 VFs
[19:27:52] [PASSED] 55 VFs
[19:27:52] [PASSED] 56 VFs
[19:27:52] [PASSED] 57 VFs
[19:27:52] [PASSED] 58 VFs
[19:27:52] [PASSED] 59 VFs
[19:27:52] [PASSED] 60 VFs
[19:27:52] [PASSED] 61 VFs
[19:27:52] [PASSED] 62 VFs
[19:27:52] [PASSED] 63 VFs
[19:27:52] ================= [PASSED] fair_doorbells ==================
[19:27:52] ======================== fair_ggtt  ========================
[19:27:52] [PASSED] 1 VF
[19:27:52] [PASSED] 2 VFs
[19:27:52] [PASSED] 3 VFs
[19:27:52] [PASSED] 4 VFs
[19:27:52] [PASSED] 5 VFs
[19:27:52] [PASSED] 6 VFs
[19:27:52] [PASSED] 7 VFs
[19:27:52] [PASSED] 8 VFs
[19:27:52] [PASSED] 9 VFs
[19:27:52] [PASSED] 10 VFs
[19:27:52] [PASSED] 11 VFs
[19:27:52] [PASSED] 12 VFs
[19:27:52] [PASSED] 13 VFs
[19:27:52] [PASSED] 14 VFs
[19:27:52] [PASSED] 15 VFs
[19:27:52] [PASSED] 16 VFs
[19:27:52] [PASSED] 17 VFs
[19:27:52] [PASSED] 18 VFs
[19:27:52] [PASSED] 19 VFs
[19:27:52] [PASSED] 20 VFs
[19:27:52] [PASSED] 21 VFs
[19:27:52] [PASSED] 22 VFs
[19:27:52] [PASSED] 23 VFs
[19:27:52] [PASSED] 24 VFs
[19:27:52] [PASSED] 25 VFs
[19:27:52] [PASSED] 26 VFs
[19:27:52] [PASSED] 27 VFs
[19:27:52] [PASSED] 28 VFs
[19:27:52] [PASSED] 29 VFs
[19:27:52] [PASSED] 30 VFs
[19:27:52] [PASSED] 31 VFs
[19:27:52] [PASSED] 32 VFs
[19:27:52] [PASSED] 33 VFs
[19:27:52] [PASSED] 34 VFs
[19:27:52] [PASSED] 35 VFs
[19:27:52] [PASSED] 36 VFs
[19:27:52] [PASSED] 37 VFs
[19:27:52] [PASSED] 38 VFs
[19:27:52] [PASSED] 39 VFs
[19:27:52] [PASSED] 40 VFs
[19:27:52] [PASSED] 41 VFs
[19:27:52] [PASSED] 42 VFs
[19:27:52] [PASSED] 43 VFs
[19:27:52] [PASSED] 44 VFs
[19:27:52] [PASSED] 45 VFs
[19:27:52] [PASSED] 46 VFs
[19:27:52] [PASSED] 47 VFs
[19:27:52] [PASSED] 48 VFs
[19:27:52] [PASSED] 49 VFs
[19:27:52] [PASSED] 50 VFs
[19:27:52] [PASSED] 51 VFs
[19:27:52] [PASSED] 52 VFs
[19:27:52] [PASSED] 53 VFs
[19:27:52] [PASSED] 54 VFs
[19:27:52] [PASSED] 55 VFs
[19:27:52] [PASSED] 56 VFs
[19:27:52] [PASSED] 57 VFs
[19:27:52] [PASSED] 58 VFs
[19:27:52] [PASSED] 59 VFs
[19:27:52] [PASSED] 60 VFs
[19:27:52] [PASSED] 61 VFs
[19:27:52] [PASSED] 62 VFs
[19:27:52] [PASSED] 63 VFs
[19:27:52] ==================== [PASSED] fair_ggtt ====================
[19:27:52] ================== [PASSED] pf_gt_config ===================
[19:27:52] ===================== lmtt (1 subtest) =====================
[19:27:52] ======================== test_ops  =========================
[19:27:52] [PASSED] 2-level
[19:27:52] [PASSED] multi-level
[19:27:52] ==================== [PASSED] test_ops =====================
[19:27:52] ====================== [PASSED] lmtt =======================
[19:27:52] ================= pf_service (11 subtests) =================
[19:27:52] [PASSED] pf_negotiate_any
[19:27:52] [PASSED] pf_negotiate_base_match
[19:27:52] [PASSED] pf_negotiate_base_newer
[19:27:52] [PASSED] pf_negotiate_base_next
[19:27:52] [SKIPPED] pf_negotiate_base_older
[19:27:52] [PASSED] pf_negotiate_base_prev
[19:27:52] [PASSED] pf_negotiate_latest_match
[19:27:52] [PASSED] pf_negotiate_latest_newer
[19:27:52] [PASSED] pf_negotiate_latest_next
[19:27:52] [SKIPPED] pf_negotiate_latest_older
[19:27:52] [SKIPPED] pf_negotiate_latest_prev
[19:27:52] =================== [PASSED] pf_service ====================
[19:27:52] ================= xe_guc_g2g (2 subtests) ==================
[19:27:52] ============== xe_live_guc_g2g_kunit_default  ==============
[19:27:52] ========= [SKIPPED] xe_live_guc_g2g_kunit_default ==========
[19:27:52] ============== xe_live_guc_g2g_kunit_allmem  ===============
[19:27:52] ========== [SKIPPED] xe_live_guc_g2g_kunit_allmem ==========
[19:27:52] =================== [SKIPPED] xe_guc_g2g ===================
[19:27:52] =================== xe_mocs (2 subtests) ===================
[19:27:52] ================ xe_live_mocs_kernel_kunit  ================
[19:27:52] =========== [SKIPPED] xe_live_mocs_kernel_kunit ============
[19:27:52] ================ xe_live_mocs_reset_kunit  =================
[19:27:52] ============ [SKIPPED] xe_live_mocs_reset_kunit ============
[19:27:52] ==================== [SKIPPED] xe_mocs =====================
[19:27:52] ================= xe_migrate (2 subtests) ==================
[19:27:52] ================= xe_migrate_sanity_kunit  =================
[19:27:52] ============ [SKIPPED] xe_migrate_sanity_kunit =============
[19:27:52] ================== xe_validate_ccs_kunit  ==================
[19:27:52] ============= [SKIPPED] xe_validate_ccs_kunit ==============
[19:27:52] =================== [SKIPPED] xe_migrate ===================
[19:27:52] ================== xe_dma_buf (1 subtest) ==================
[19:27:52] ==================== xe_dma_buf_kunit  =====================
[19:27:52] ================ [SKIPPED] xe_dma_buf_kunit ================
[19:27:52] =================== [SKIPPED] xe_dma_buf ===================
[19:27:52] ================= xe_bo_shrink (1 subtest) =================
[19:27:52] =================== xe_bo_shrink_kunit  ====================
[19:27:52] =============== [SKIPPED] xe_bo_shrink_kunit ===============
[19:27:52] ================== [SKIPPED] xe_bo_shrink ==================
[19:27:52] ==================== xe_bo (2 subtests) ====================
[19:27:52] ================== xe_ccs_migrate_kunit  ===================
[19:27:52] ============== [SKIPPED] xe_ccs_migrate_kunit ==============
[19:27:52] ==================== xe_bo_evict_kunit  ====================
[19:27:52] =============== [SKIPPED] xe_bo_evict_kunit ================
[19:27:52] ===================== [SKIPPED] xe_bo ======================
[19:27:52] ==================== args (13 subtests) ====================
[19:27:52] [PASSED] count_args_test
[19:27:52] [PASSED] call_args_example
[19:27:52] [PASSED] call_args_test
[19:27:52] [PASSED] drop_first_arg_example
[19:27:52] [PASSED] drop_first_arg_test
[19:27:52] [PASSED] first_arg_example
[19:27:52] [PASSED] first_arg_test
[19:27:52] [PASSED] last_arg_example
[19:27:52] [PASSED] last_arg_test
[19:27:52] [PASSED] pick_arg_example
[19:27:52] [PASSED] if_args_example
[19:27:52] [PASSED] if_args_test
[19:27:52] [PASSED] sep_comma_example
[19:27:52] ====================== [PASSED] args =======================
[19:27:52] =================== xe_pci (3 subtests) ====================
[19:27:52] ==================== check_graphics_ip  ====================
[19:27:52] [PASSED] 12.00 Xe_LP
[19:27:52] [PASSED] 12.10 Xe_LP+
[19:27:52] [PASSED] 12.55 Xe_HPG
[19:27:52] [PASSED] 12.60 Xe_HPC
[19:27:52] [PASSED] 12.70 Xe_LPG
[19:27:52] [PASSED] 12.71 Xe_LPG
[19:27:52] [PASSED] 12.74 Xe_LPG+
[19:27:52] [PASSED] 20.01 Xe2_HPG
[19:27:52] [PASSED] 20.02 Xe2_HPG
[19:27:52] [PASSED] 20.04 Xe2_LPG
[19:27:52] [PASSED] 30.00 Xe3_LPG
[19:27:52] [PASSED] 30.01 Xe3_LPG
[19:27:52] [PASSED] 30.03 Xe3_LPG
[19:27:52] [PASSED] 30.04 Xe3_LPG
[19:27:52] [PASSED] 30.05 Xe3_LPG
[19:27:52] [PASSED] 35.10 Xe3p_LPG
[19:27:52] [PASSED] 35.11 Xe3p_XPC
[19:27:52] ================ [PASSED] check_graphics_ip ================
[19:27:52] ===================== check_media_ip  ======================
[19:27:52] [PASSED] 12.00 Xe_M
[19:27:52] [PASSED] 12.55 Xe_HPM
[19:27:52] [PASSED] 13.00 Xe_LPM+
[19:27:52] [PASSED] 13.01 Xe2_HPM
[19:27:52] [PASSED] 20.00 Xe2_LPM
[19:27:52] [PASSED] 30.00 Xe3_LPM
[19:27:52] [PASSED] 30.02 Xe3_LPM
[19:27:52] [PASSED] 35.00 Xe3p_LPM
[19:27:52] [PASSED] 35.03 Xe3p_HPM
[19:27:52] ================= [PASSED] check_media_ip ==================
[19:27:52] =================== check_platform_desc  ===================
[19:27:52] [PASSED] 0x9A60 (TIGERLAKE)
[19:27:52] [PASSED] 0x9A68 (TIGERLAKE)
[19:27:52] [PASSED] 0x9A70 (TIGERLAKE)
[19:27:52] [PASSED] 0x9A40 (TIGERLAKE)
[19:27:52] [PASSED] 0x9A49 (TIGERLAKE)
[19:27:52] [PASSED] 0x9A59 (TIGERLAKE)
[19:27:52] [PASSED] 0x9A78 (TIGERLAKE)
[19:27:52] [PASSED] 0x9AC0 (TIGERLAKE)
[19:27:52] [PASSED] 0x9AC9 (TIGERLAKE)
[19:27:52] [PASSED] 0x9AD9 (TIGERLAKE)
[19:27:52] [PASSED] 0x9AF8 (TIGERLAKE)
[19:27:52] [PASSED] 0x4C80 (ROCKETLAKE)
[19:27:52] [PASSED] 0x4C8A (ROCKETLAKE)
[19:27:52] [PASSED] 0x4C8B (ROCKETLAKE)
[19:27:52] [PASSED] 0x4C8C (ROCKETLAKE)
[19:27:52] [PASSED] 0x4C90 (ROCKETLAKE)
[19:27:52] [PASSED] 0x4C9A (ROCKETLAKE)
[19:27:52] [PASSED] 0x4680 (ALDERLAKE_S)
[19:27:52] [PASSED] 0x4682 (ALDERLAKE_S)
[19:27:52] [PASSED] 0x4688 (ALDERLAKE_S)
[19:27:52] [PASSED] 0x468A (ALDERLAKE_S)
[19:27:52] [PASSED] 0x468B (ALDERLAKE_S)
[19:27:52] [PASSED] 0x4690 (ALDERLAKE_S)
[19:27:52] [PASSED] 0x4692 (ALDERLAKE_S)
[19:27:52] [PASSED] 0x4693 (ALDERLAKE_S)
[19:27:52] [PASSED] 0x46A0 (ALDERLAKE_P)
[19:27:52] [PASSED] 0x46A1 (ALDERLAKE_P)
[19:27:52] [PASSED] 0x46A2 (ALDERLAKE_P)
[19:27:52] [PASSED] 0x46A3 (ALDERLAKE_P)
[19:27:52] [PASSED] 0x46A6 (ALDERLAKE_P)
[19:27:52] [PASSED] 0x46A8 (ALDERLAKE_P)
[19:27:52] [PASSED] 0x46AA (ALDERLAKE_P)
[19:27:52] [PASSED] 0x462A (ALDERLAKE_P)
[19:27:52] [PASSED] 0x4626 (ALDERLAKE_P)
stty: 'standard input': Inappropriate ioctl for device
[19:27:52] [PASSED] 0x4628 (ALDERLAKE_P)
[19:27:52] [PASSED] 0x46B0 (ALDERLAKE_P)
[19:27:52] [PASSED] 0x46B1 (ALDERLAKE_P)
[19:27:52] [PASSED] 0x46B2 (ALDERLAKE_P)
[19:27:52] [PASSED] 0x46B3 (ALDERLAKE_P)
[19:27:52] [PASSED] 0x46C0 (ALDERLAKE_P)
[19:27:52] [PASSED] 0x46C1 (ALDERLAKE_P)
[19:27:52] [PASSED] 0x46C2 (ALDERLAKE_P)
[19:27:52] [PASSED] 0x46C3 (ALDERLAKE_P)
[19:27:52] [PASSED] 0x46D0 (ALDERLAKE_N)
[19:27:52] [PASSED] 0x46D1 (ALDERLAKE_N)
[19:27:52] [PASSED] 0x46D2 (ALDERLAKE_N)
[19:27:52] [PASSED] 0x46D3 (ALDERLAKE_N)
[19:27:52] [PASSED] 0x46D4 (ALDERLAKE_N)
[19:27:52] [PASSED] 0xA721 (ALDERLAKE_P)
[19:27:52] [PASSED] 0xA7A1 (ALDERLAKE_P)
[19:27:52] [PASSED] 0xA7A9 (ALDERLAKE_P)
[19:27:52] [PASSED] 0xA7AC (ALDERLAKE_P)
[19:27:52] [PASSED] 0xA7AD (ALDERLAKE_P)
[19:27:52] [PASSED] 0xA720 (ALDERLAKE_P)
[19:27:52] [PASSED] 0xA7A0 (ALDERLAKE_P)
[19:27:52] [PASSED] 0xA7A8 (ALDERLAKE_P)
[19:27:52] [PASSED] 0xA7AA (ALDERLAKE_P)
[19:27:52] [PASSED] 0xA7AB (ALDERLAKE_P)
[19:27:52] [PASSED] 0xA780 (ALDERLAKE_S)
[19:27:52] [PASSED] 0xA781 (ALDERLAKE_S)
[19:27:52] [PASSED] 0xA782 (ALDERLAKE_S)
[19:27:52] [PASSED] 0xA783 (ALDERLAKE_S)
[19:27:52] [PASSED] 0xA788 (ALDERLAKE_S)
[19:27:52] [PASSED] 0xA789 (ALDERLAKE_S)
[19:27:52] [PASSED] 0xA78A (ALDERLAKE_S)
[19:27:52] [PASSED] 0xA78B (ALDERLAKE_S)
[19:27:52] [PASSED] 0x4905 (DG1)
[19:27:52] [PASSED] 0x4906 (DG1)
[19:27:52] [PASSED] 0x4907 (DG1)
[19:27:52] [PASSED] 0x4908 (DG1)
[19:27:52] [PASSED] 0x4909 (DG1)
[19:27:52] [PASSED] 0x56C0 (DG2)
[19:27:52] [PASSED] 0x56C2 (DG2)
[19:27:52] [PASSED] 0x56C1 (DG2)
[19:27:52] [PASSED] 0x7D51 (METEORLAKE)
[19:27:52] [PASSED] 0x7DD1 (METEORLAKE)
[19:27:52] [PASSED] 0x7D41 (METEORLAKE)
[19:27:52] [PASSED] 0x7D67 (METEORLAKE)
[19:27:52] [PASSED] 0xB640 (METEORLAKE)
[19:27:52] [PASSED] 0x56A0 (DG2)
[19:27:52] [PASSED] 0x56A1 (DG2)
[19:27:52] [PASSED] 0x56A2 (DG2)
[19:27:52] [PASSED] 0x56BE (DG2)
[19:27:52] [PASSED] 0x56BF (DG2)
[19:27:52] [PASSED] 0x5690 (DG2)
[19:27:52] [PASSED] 0x5691 (DG2)
[19:27:52] [PASSED] 0x5692 (DG2)
[19:27:52] [PASSED] 0x56A5 (DG2)
[19:27:52] [PASSED] 0x56A6 (DG2)
[19:27:52] [PASSED] 0x56B0 (DG2)
[19:27:52] [PASSED] 0x56B1 (DG2)
[19:27:52] [PASSED] 0x56BA (DG2)
[19:27:52] [PASSED] 0x56BB (DG2)
[19:27:52] [PASSED] 0x56BC (DG2)
[19:27:52] [PASSED] 0x56BD (DG2)
[19:27:52] [PASSED] 0x5693 (DG2)
[19:27:52] [PASSED] 0x5694 (DG2)
[19:27:52] [PASSED] 0x5695 (DG2)
[19:27:52] [PASSED] 0x56A3 (DG2)
[19:27:52] [PASSED] 0x56A4 (DG2)
[19:27:52] [PASSED] 0x56B2 (DG2)
[19:27:52] [PASSED] 0x56B3 (DG2)
[19:27:52] [PASSED] 0x5696 (DG2)
[19:27:52] [PASSED] 0x5697 (DG2)
[19:27:52] [PASSED] 0xB69 (PVC)
[19:27:52] [PASSED] 0xB6E (PVC)
[19:27:52] [PASSED] 0xBD4 (PVC)
[19:27:52] [PASSED] 0xBD5 (PVC)
[19:27:52] [PASSED] 0xBD6 (PVC)
[19:27:52] [PASSED] 0xBD7 (PVC)
[19:27:52] [PASSED] 0xBD8 (PVC)
[19:27:52] [PASSED] 0xBD9 (PVC)
[19:27:52] [PASSED] 0xBDA (PVC)
[19:27:52] [PASSED] 0xBDB (PVC)
[19:27:52] [PASSED] 0xBE0 (PVC)
[19:27:52] [PASSED] 0xBE1 (PVC)
[19:27:52] [PASSED] 0xBE5 (PVC)
[19:27:52] [PASSED] 0x7D40 (METEORLAKE)
[19:27:52] [PASSED] 0x7D45 (METEORLAKE)
[19:27:52] [PASSED] 0x7D55 (METEORLAKE)
[19:27:52] [PASSED] 0x7D60 (METEORLAKE)
[19:27:52] [PASSED] 0x7DD5 (METEORLAKE)
[19:27:52] [PASSED] 0x6420 (LUNARLAKE)
[19:27:52] [PASSED] 0x64A0 (LUNARLAKE)
[19:27:52] [PASSED] 0x64B0 (LUNARLAKE)
[19:27:52] [PASSED] 0xE202 (BATTLEMAGE)
[19:27:52] [PASSED] 0xE209 (BATTLEMAGE)
[19:27:52] [PASSED] 0xE20B (BATTLEMAGE)
[19:27:52] [PASSED] 0xE20C (BATTLEMAGE)
[19:27:52] [PASSED] 0xE20D (BATTLEMAGE)
[19:27:52] [PASSED] 0xE210 (BATTLEMAGE)
[19:27:52] [PASSED] 0xE211 (BATTLEMAGE)
[19:27:52] [PASSED] 0xE212 (BATTLEMAGE)
[19:27:52] [PASSED] 0xE216 (BATTLEMAGE)
[19:27:52] [PASSED] 0xE220 (BATTLEMAGE)
[19:27:52] [PASSED] 0xE221 (BATTLEMAGE)
[19:27:52] [PASSED] 0xE222 (BATTLEMAGE)
[19:27:52] [PASSED] 0xE223 (BATTLEMAGE)
[19:27:52] [PASSED] 0xB080 (PANTHERLAKE)
[19:27:52] [PASSED] 0xB081 (PANTHERLAKE)
[19:27:52] [PASSED] 0xB082 (PANTHERLAKE)
[19:27:52] [PASSED] 0xB083 (PANTHERLAKE)
[19:27:52] [PASSED] 0xB084 (PANTHERLAKE)
[19:27:52] [PASSED] 0xB085 (PANTHERLAKE)
[19:27:52] [PASSED] 0xB086 (PANTHERLAKE)
[19:27:52] [PASSED] 0xB087 (PANTHERLAKE)
[19:27:52] [PASSED] 0xB08F (PANTHERLAKE)
[19:27:52] [PASSED] 0xB090 (PANTHERLAKE)
[19:27:52] [PASSED] 0xB0A0 (PANTHERLAKE)
[19:27:52] [PASSED] 0xB0B0 (PANTHERLAKE)
[19:27:52] [PASSED] 0xFD80 (PANTHERLAKE)
[19:27:52] [PASSED] 0xFD81 (PANTHERLAKE)
[19:27:52] [PASSED] 0xD740 (NOVALAKE_S)
[19:27:52] [PASSED] 0xD741 (NOVALAKE_S)
[19:27:52] [PASSED] 0xD742 (NOVALAKE_S)
[19:27:52] [PASSED] 0xD743 (NOVALAKE_S)
[19:27:52] [PASSED] 0xD744 (NOVALAKE_S)
[19:27:52] [PASSED] 0xD745 (NOVALAKE_S)
[19:27:52] [PASSED] 0x674C (CRESCENTISLAND)
[19:27:52] [PASSED] 0xD750 (NOVALAKE_P)
[19:27:52] [PASSED] 0xD751 (NOVALAKE_P)
[19:27:52] [PASSED] 0xD752 (NOVALAKE_P)
[19:27:52] [PASSED] 0xD753 (NOVALAKE_P)
[19:27:52] [PASSED] 0xD754 (NOVALAKE_P)
[19:27:52] [PASSED] 0xD755 (NOVALAKE_P)
[19:27:52] [PASSED] 0xD756 (NOVALAKE_P)
[19:27:52] [PASSED] 0xD757 (NOVALAKE_P)
[19:27:52] [PASSED] 0xD75F (NOVALAKE_P)
[19:27:52] =============== [PASSED] check_platform_desc ===============
[19:27:52] ===================== [PASSED] xe_pci ======================
[19:27:52] =================== xe_rtp (2 subtests) ====================
[19:27:52] =============== xe_rtp_process_to_sr_tests  ================
[19:27:52] [PASSED] coalesce-same-reg
[19:27:52] [PASSED] no-match-no-add
[19:27:52] [PASSED] match-or
[19:27:52] [PASSED] match-or-xfail
[19:27:52] [PASSED] no-match-no-add-multiple-rules
[19:27:52] [PASSED] two-regs-two-entries
[19:27:52] [PASSED] clr-one-set-other
[19:27:52] [PASSED] set-field
[19:27:52] [PASSED] conflict-duplicate
[19:27:52] [PASSED] conflict-not-disjoint
[19:27:52] [PASSED] conflict-reg-type
[19:27:52] =========== [PASSED] xe_rtp_process_to_sr_tests ============
[19:27:52] ================== xe_rtp_process_tests  ===================
[19:27:52] [PASSED] active1
[19:27:52] [PASSED] active2
[19:27:52] [PASSED] active-inactive
[19:27:52] [PASSED] inactive-active
[19:27:52] [PASSED] inactive-1st_or_active-inactive
[19:27:52] [PASSED] inactive-2nd_or_active-inactive
[19:27:52] [PASSED] inactive-last_or_active-inactive
[19:27:52] [PASSED] inactive-no_or_active-inactive
[19:27:52] ============== [PASSED] xe_rtp_process_tests ===============
[19:27:52] ===================== [PASSED] xe_rtp ======================
[19:27:52] ==================== xe_wa (1 subtest) =====================
[19:27:52] ======================== xe_wa_gt  =========================
[19:27:52] [PASSED] TIGERLAKE B0
[19:27:52] [PASSED] DG1 A0
[19:27:52] [PASSED] DG1 B0
[19:27:52] [PASSED] ALDERLAKE_S A0
[19:27:52] [PASSED] ALDERLAKE_S B0
[19:27:52] [PASSED] ALDERLAKE_S C0
[19:27:52] [PASSED] ALDERLAKE_S D0
[19:27:52] [PASSED] ALDERLAKE_P A0
[19:27:52] [PASSED] ALDERLAKE_P B0
[19:27:52] [PASSED] ALDERLAKE_P C0
[19:27:52] [PASSED] ALDERLAKE_S RPLS D0
[19:27:52] [PASSED] ALDERLAKE_P RPLU E0
[19:27:52] [PASSED] DG2 G10 C0
[19:27:52] [PASSED] DG2 G11 B1
[19:27:52] [PASSED] DG2 G12 A1
[19:27:52] [PASSED] METEORLAKE 12.70(Xe_LPG) A0 13.00(Xe_LPM+) A0
[19:27:52] [PASSED] METEORLAKE 12.71(Xe_LPG) A0 13.00(Xe_LPM+) A0
[19:27:52] [PASSED] METEORLAKE 12.74(Xe_LPG+) A0 13.00(Xe_LPM+) A0
[19:27:52] [PASSED] LUNARLAKE 20.04(Xe2_LPG) A0 20.00(Xe2_LPM) A0
[19:27:52] [PASSED] LUNARLAKE 20.04(Xe2_LPG) B0 20.00(Xe2_LPM) A0
[19:27:52] [PASSED] BATTLEMAGE 20.01(Xe2_HPG) A0 13.01(Xe2_HPM) A1
[19:27:52] [PASSED] PANTHERLAKE 30.00(Xe3_LPG) A0 30.00(Xe3_LPM) A0
[19:27:52] ==================== [PASSED] xe_wa_gt =====================
[19:27:52] ====================== [PASSED] xe_wa ======================
[19:27:52] ============================================================
[19:27:52] Testing complete. Ran 522 tests: passed: 504, skipped: 18
[19:27:52] Elapsed time: 36.337s total, 4.221s configuring, 31.599s building, 0.468s running

+ /kernel/tools/testing/kunit/kunit.py run --kunitconfig /kernel/drivers/gpu/drm/tests/.kunitconfig
[19:27:52] Configuring KUnit Kernel ...
Regenerating .config ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
[19:27:54] Building KUnit Kernel ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
Building with:
$ make all compile_commands.json scripts_gdb ARCH=um O=.kunit --jobs=48
[19:28:20] Starting KUnit Kernel (1/1)...
[19:28:20] ============================================================
Running tests with:
$ .kunit/linux kunit.enable=1 mem=1G console=tty kunit_shutdown=halt
[19:28:20] ============ drm_test_pick_cmdline (2 subtests) ============
[19:28:20] [PASSED] drm_test_pick_cmdline_res_1920_1080_60
[19:28:20] =============== drm_test_pick_cmdline_named  ===============
[19:28:20] [PASSED] NTSC
[19:28:20] [PASSED] NTSC-J
[19:28:20] [PASSED] PAL
[19:28:20] [PASSED] PAL-M
[19:28:20] =========== [PASSED] drm_test_pick_cmdline_named ===========
[19:28:20] ============== [PASSED] drm_test_pick_cmdline ==============
[19:28:20] == drm_test_atomic_get_connector_for_encoder (1 subtest) ===
[19:28:20] [PASSED] drm_test_drm_atomic_get_connector_for_encoder
[19:28:20] ==== [PASSED] drm_test_atomic_get_connector_for_encoder ====
[19:28:20] =========== drm_validate_clone_mode (2 subtests) ===========
[19:28:20] ============== drm_test_check_in_clone_mode  ===============
[19:28:20] [PASSED] in_clone_mode
[19:28:20] [PASSED] not_in_clone_mode
[19:28:20] ========== [PASSED] drm_test_check_in_clone_mode ===========
[19:28:20] =============== drm_test_check_valid_clones  ===============
[19:28:20] [PASSED] not_in_clone_mode
[19:28:20] [PASSED] valid_clone
[19:28:20] [PASSED] invalid_clone
[19:28:20] =========== [PASSED] drm_test_check_valid_clones ===========
[19:28:20] ============= [PASSED] drm_validate_clone_mode =============
[19:28:20] ============= drm_validate_modeset (1 subtest) =============
[19:28:20] [PASSED] drm_test_check_connector_changed_modeset
[19:28:20] ============== [PASSED] drm_validate_modeset ===============
[19:28:20] ====== drm_test_bridge_get_current_state (2 subtests) ======
[19:28:20] [PASSED] drm_test_drm_bridge_get_current_state_atomic
[19:28:20] [PASSED] drm_test_drm_bridge_get_current_state_legacy
[19:28:20] ======== [PASSED] drm_test_bridge_get_current_state ========
[19:28:20] ====== drm_test_bridge_helper_reset_crtc (3 subtests) ======
[19:28:20] [PASSED] drm_test_drm_bridge_helper_reset_crtc_atomic
[19:28:20] [PASSED] drm_test_drm_bridge_helper_reset_crtc_atomic_disabled
[19:28:20] [PASSED] drm_test_drm_bridge_helper_reset_crtc_legacy
[19:28:20] ======== [PASSED] drm_test_bridge_helper_reset_crtc ========
[19:28:20] ============== drm_bridge_alloc (2 subtests) ===============
[19:28:20] [PASSED] drm_test_drm_bridge_alloc_basic
[19:28:20] [PASSED] drm_test_drm_bridge_alloc_get_put
[19:28:20] ================ [PASSED] drm_bridge_alloc =================
[19:28:20] ============= drm_cmdline_parser (40 subtests) =============
[19:28:20] [PASSED] drm_test_cmdline_force_d_only
[19:28:20] [PASSED] drm_test_cmdline_force_D_only_dvi
[19:28:20] [PASSED] drm_test_cmdline_force_D_only_hdmi
[19:28:20] [PASSED] drm_test_cmdline_force_D_only_not_digital
[19:28:20] [PASSED] drm_test_cmdline_force_e_only
[19:28:20] [PASSED] drm_test_cmdline_res
[19:28:20] [PASSED] drm_test_cmdline_res_vesa
[19:28:20] [PASSED] drm_test_cmdline_res_vesa_rblank
[19:28:20] [PASSED] drm_test_cmdline_res_rblank
[19:28:20] [PASSED] drm_test_cmdline_res_bpp
[19:28:20] [PASSED] drm_test_cmdline_res_refresh
[19:28:20] [PASSED] drm_test_cmdline_res_bpp_refresh
[19:28:20] [PASSED] drm_test_cmdline_res_bpp_refresh_interlaced
[19:28:20] [PASSED] drm_test_cmdline_res_bpp_refresh_margins
[19:28:20] [PASSED] drm_test_cmdline_res_bpp_refresh_force_off
[19:28:20] [PASSED] drm_test_cmdline_res_bpp_refresh_force_on
[19:28:20] [PASSED] drm_test_cmdline_res_bpp_refresh_force_on_analog
[19:28:20] [PASSED] drm_test_cmdline_res_bpp_refresh_force_on_digital
[19:28:20] [PASSED] drm_test_cmdline_res_bpp_refresh_interlaced_margins_force_on
[19:28:20] [PASSED] drm_test_cmdline_res_margins_force_on
[19:28:20] [PASSED] drm_test_cmdline_res_vesa_margins
[19:28:20] [PASSED] drm_test_cmdline_name
[19:28:20] [PASSED] drm_test_cmdline_name_bpp
[19:28:20] [PASSED] drm_test_cmdline_name_option
[19:28:20] [PASSED] drm_test_cmdline_name_bpp_option
[19:28:20] [PASSED] drm_test_cmdline_rotate_0
[19:28:20] [PASSED] drm_test_cmdline_rotate_90
[19:28:20] [PASSED] drm_test_cmdline_rotate_180
[19:28:20] [PASSED] drm_test_cmdline_rotate_270
[19:28:20] [PASSED] drm_test_cmdline_hmirror
[19:28:20] [PASSED] drm_test_cmdline_vmirror
[19:28:20] [PASSED] drm_test_cmdline_margin_options
[19:28:20] [PASSED] drm_test_cmdline_multiple_options
[19:28:20] [PASSED] drm_test_cmdline_bpp_extra_and_option
[19:28:20] [PASSED] drm_test_cmdline_extra_and_option
[19:28:20] [PASSED] drm_test_cmdline_freestanding_options
[19:28:20] [PASSED] drm_test_cmdline_freestanding_force_e_and_options
[19:28:20] [PASSED] drm_test_cmdline_panel_orientation
[19:28:20] ================ drm_test_cmdline_invalid  =================
[19:28:20] [PASSED] margin_only
[19:28:20] [PASSED] interlace_only
[19:28:20] [PASSED] res_missing_x
[19:28:20] [PASSED] res_missing_y
[19:28:20] [PASSED] res_bad_y
[19:28:20] [PASSED] res_missing_y_bpp
[19:28:20] [PASSED] res_bad_bpp
[19:28:20] [PASSED] res_bad_refresh
[19:28:20] [PASSED] res_bpp_refresh_force_on_off
[19:28:20] [PASSED] res_invalid_mode
[19:28:20] [PASSED] res_bpp_wrong_place_mode
[19:28:20] [PASSED] name_bpp_refresh
[19:28:20] [PASSED] name_refresh
[19:28:20] [PASSED] name_refresh_wrong_mode
[19:28:20] [PASSED] name_refresh_invalid_mode
[19:28:20] [PASSED] rotate_multiple
[19:28:20] [PASSED] rotate_invalid_val
[19:28:20] [PASSED] rotate_truncated
[19:28:20] [PASSED] invalid_option
[19:28:20] [PASSED] invalid_tv_option
[19:28:20] [PASSED] truncated_tv_option
[19:28:20] ============ [PASSED] drm_test_cmdline_invalid =============
[19:28:20] =============== drm_test_cmdline_tv_options  ===============
[19:28:20] [PASSED] NTSC
[19:28:20] [PASSED] NTSC_443
[19:28:20] [PASSED] NTSC_J
[19:28:20] [PASSED] PAL
[19:28:20] [PASSED] PAL_M
[19:28:20] [PASSED] PAL_N
[19:28:20] [PASSED] SECAM
[19:28:20] [PASSED] MONO_525
[19:28:20] [PASSED] MONO_625
[19:28:20] =========== [PASSED] drm_test_cmdline_tv_options ===========
[19:28:20] =============== [PASSED] drm_cmdline_parser ================
[19:28:20] ========== drmm_connector_hdmi_init (20 subtests) ==========
[19:28:20] [PASSED] drm_test_connector_hdmi_init_valid
[19:28:20] [PASSED] drm_test_connector_hdmi_init_bpc_8
[19:28:20] [PASSED] drm_test_connector_hdmi_init_bpc_10
[19:28:20] [PASSED] drm_test_connector_hdmi_init_bpc_12
[19:28:20] [PASSED] drm_test_connector_hdmi_init_bpc_invalid
[19:28:20] [PASSED] drm_test_connector_hdmi_init_bpc_null
[19:28:20] [PASSED] drm_test_connector_hdmi_init_formats_empty
[19:28:20] [PASSED] drm_test_connector_hdmi_init_formats_no_rgb
[19:28:20] === drm_test_connector_hdmi_init_formats_yuv420_allowed  ===
[19:28:20] [PASSED] supported_formats=0x9 yuv420_allowed=1
[19:28:20] [PASSED] supported_formats=0x9 yuv420_allowed=0
[19:28:20] [PASSED] supported_formats=0x3 yuv420_allowed=1
[19:28:20] [PASSED] supported_formats=0x3 yuv420_allowed=0
[19:28:20] === [PASSED] drm_test_connector_hdmi_init_formats_yuv420_allowed ===
[19:28:20] [PASSED] drm_test_connector_hdmi_init_null_ddc
[19:28:20] [PASSED] drm_test_connector_hdmi_init_null_product
[19:28:20] [PASSED] drm_test_connector_hdmi_init_null_vendor
[19:28:20] [PASSED] drm_test_connector_hdmi_init_product_length_exact
[19:28:20] [PASSED] drm_test_connector_hdmi_init_product_length_too_long
[19:28:20] [PASSED] drm_test_connector_hdmi_init_product_valid
[19:28:20] [PASSED] drm_test_connector_hdmi_init_vendor_length_exact
[19:28:20] [PASSED] drm_test_connector_hdmi_init_vendor_length_too_long
[19:28:20] [PASSED] drm_test_connector_hdmi_init_vendor_valid
[19:28:20] ========= drm_test_connector_hdmi_init_type_valid  =========
[19:28:20] [PASSED] HDMI-A
[19:28:20] [PASSED] HDMI-B
[19:28:20] ===== [PASSED] drm_test_connector_hdmi_init_type_valid =====
[19:28:20] ======== drm_test_connector_hdmi_init_type_invalid  ========
[19:28:20] [PASSED] Unknown
[19:28:20] [PASSED] VGA
[19:28:20] [PASSED] DVI-I
[19:28:20] [PASSED] DVI-D
[19:28:20] [PASSED] DVI-A
[19:28:20] [PASSED] Composite
[19:28:20] [PASSED] SVIDEO
[19:28:20] [PASSED] LVDS
[19:28:20] [PASSED] Component
[19:28:20] [PASSED] DIN
[19:28:20] [PASSED] DP
[19:28:20] [PASSED] TV
[19:28:20] [PASSED] eDP
[19:28:20] [PASSED] Virtual
[19:28:20] [PASSED] DSI
[19:28:20] [PASSED] DPI
[19:28:20] [PASSED] Writeback
[19:28:20] [PASSED] SPI
[19:28:20] [PASSED] USB
[19:28:20] ==== [PASSED] drm_test_connector_hdmi_init_type_invalid ====
[19:28:20] ============ [PASSED] drmm_connector_hdmi_init =============
[19:28:20] ============= drmm_connector_init (3 subtests) =============
[19:28:20] [PASSED] drm_test_drmm_connector_init
[19:28:20] [PASSED] drm_test_drmm_connector_init_null_ddc
[19:28:20] ========= drm_test_drmm_connector_init_type_valid  =========
[19:28:20] [PASSED] Unknown
[19:28:20] [PASSED] VGA
[19:28:20] [PASSED] DVI-I
[19:28:20] [PASSED] DVI-D
[19:28:20] [PASSED] DVI-A
[19:28:20] [PASSED] Composite
[19:28:20] [PASSED] SVIDEO
[19:28:20] [PASSED] LVDS
[19:28:20] [PASSED] Component
[19:28:20] [PASSED] DIN
[19:28:20] [PASSED] DP
[19:28:20] [PASSED] HDMI-A
[19:28:20] [PASSED] HDMI-B
[19:28:20] [PASSED] TV
[19:28:20] [PASSED] eDP
[19:28:20] [PASSED] Virtual
[19:28:20] [PASSED] DSI
[19:28:20] [PASSED] DPI
[19:28:20] [PASSED] Writeback
[19:28:20] [PASSED] SPI
[19:28:20] [PASSED] USB
[19:28:20] ===== [PASSED] drm_test_drmm_connector_init_type_valid =====
[19:28:20] =============== [PASSED] drmm_connector_init ===============
[19:28:20] ========= drm_connector_dynamic_init (6 subtests) ==========
[19:28:20] [PASSED] drm_test_drm_connector_dynamic_init
[19:28:20] [PASSED] drm_test_drm_connector_dynamic_init_null_ddc
[19:28:20] [PASSED] drm_test_drm_connector_dynamic_init_not_added
[19:28:20] [PASSED] drm_test_drm_connector_dynamic_init_properties
[19:28:20] ===== drm_test_drm_connector_dynamic_init_type_valid  ======
[19:28:20] [PASSED] Unknown
[19:28:20] [PASSED] VGA
[19:28:20] [PASSED] DVI-I
[19:28:20] [PASSED] DVI-D
[19:28:20] [PASSED] DVI-A
[19:28:20] [PASSED] Composite
[19:28:20] [PASSED] SVIDEO
[19:28:20] [PASSED] LVDS
[19:28:20] [PASSED] Component
[19:28:20] [PASSED] DIN
[19:28:20] [PASSED] DP
[19:28:20] [PASSED] HDMI-A
[19:28:20] [PASSED] HDMI-B
[19:28:20] [PASSED] TV
[19:28:20] [PASSED] eDP
[19:28:20] [PASSED] Virtual
[19:28:20] [PASSED] DSI
[19:28:20] [PASSED] DPI
[19:28:20] [PASSED] Writeback
[19:28:20] [PASSED] SPI
[19:28:20] [PASSED] USB
[19:28:20] = [PASSED] drm_test_drm_connector_dynamic_init_type_valid ==
[19:28:20] ======== drm_test_drm_connector_dynamic_init_name  =========
[19:28:20] [PASSED] Unknown
[19:28:20] [PASSED] VGA
[19:28:20] [PASSED] DVI-I
[19:28:20] [PASSED] DVI-D
[19:28:20] [PASSED] DVI-A
[19:28:20] [PASSED] Composite
[19:28:20] [PASSED] SVIDEO
[19:28:20] [PASSED] LVDS
[19:28:20] [PASSED] Component
[19:28:20] [PASSED] DIN
[19:28:20] [PASSED] DP
[19:28:20] [PASSED] HDMI-A
[19:28:20] [PASSED] HDMI-B
[19:28:20] [PASSED] TV
[19:28:20] [PASSED] eDP
[19:28:20] [PASSED] Virtual
[19:28:20] [PASSED] DSI
[19:28:20] [PASSED] DPI
[19:28:20] [PASSED] Writeback
[19:28:20] [PASSED] SPI
[19:28:20] [PASSED] USB
[19:28:20] ==== [PASSED] drm_test_drm_connector_dynamic_init_name =====
[19:28:20] =========== [PASSED] drm_connector_dynamic_init ============
[19:28:20] ==== drm_connector_dynamic_register_early (4 subtests) =====
[19:28:20] [PASSED] drm_test_drm_connector_dynamic_register_early_on_list
[19:28:20] [PASSED] drm_test_drm_connector_dynamic_register_early_defer
[19:28:20] [PASSED] drm_test_drm_connector_dynamic_register_early_no_init
[19:28:20] [PASSED] drm_test_drm_connector_dynamic_register_early_no_mode_object
[19:28:20] ====== [PASSED] drm_connector_dynamic_register_early =======
[19:28:20] ======= drm_connector_dynamic_register (7 subtests) ========
[19:28:20] [PASSED] drm_test_drm_connector_dynamic_register_on_list
[19:28:20] [PASSED] drm_test_drm_connector_dynamic_register_no_defer
[19:28:20] [PASSED] drm_test_drm_connector_dynamic_register_no_init
[19:28:20] [PASSED] drm_test_drm_connector_dynamic_register_mode_object
[19:28:20] [PASSED] drm_test_drm_connector_dynamic_register_sysfs
[19:28:20] [PASSED] drm_test_drm_connector_dynamic_register_sysfs_name
[19:28:20] [PASSED] drm_test_drm_connector_dynamic_register_debugfs
[19:28:20] ========= [PASSED] drm_connector_dynamic_register ==========
[19:28:20] = drm_connector_attach_broadcast_rgb_property (2 subtests) =
[19:28:20] [PASSED] drm_test_drm_connector_attach_broadcast_rgb_property
[19:28:20] [PASSED] drm_test_drm_connector_attach_broadcast_rgb_property_hdmi_connector
[19:28:20] === [PASSED] drm_connector_attach_broadcast_rgb_property ===
[19:28:20] ========== drm_get_tv_mode_from_name (2 subtests) ==========
[19:28:20] ========== drm_test_get_tv_mode_from_name_valid  ===========
[19:28:20] [PASSED] NTSC
[19:28:20] [PASSED] NTSC-443
[19:28:20] [PASSED] NTSC-J
[19:28:20] [PASSED] PAL
[19:28:20] [PASSED] PAL-M
[19:28:20] [PASSED] PAL-N
[19:28:20] [PASSED] SECAM
[19:28:20] [PASSED] Mono
[19:28:20] ====== [PASSED] drm_test_get_tv_mode_from_name_valid =======
[19:28:20] [PASSED] drm_test_get_tv_mode_from_name_truncated
[19:28:20] ============ [PASSED] drm_get_tv_mode_from_name ============
[19:28:20] = drm_test_connector_hdmi_compute_mode_clock (12 subtests) =
[19:28:20] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb
[19:28:20] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_10bpc
[19:28:20] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_10bpc_vic_1
[19:28:20] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_12bpc
[19:28:20] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_12bpc_vic_1
[19:28:20] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_double
[19:28:20] = drm_test_connector_hdmi_compute_mode_clock_yuv420_valid  =
[19:28:20] [PASSED] VIC 96
[19:28:20] [PASSED] VIC 97
[19:28:20] [PASSED] VIC 101
[19:28:20] [PASSED] VIC 102
[19:28:20] [PASSED] VIC 106
[19:28:20] [PASSED] VIC 107
[19:28:20] === [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv420_valid ===
[19:28:20] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv420_10_bpc
[19:28:20] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv420_12_bpc
[19:28:20] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv422_8_bpc
[19:28:20] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv422_10_bpc
[19:28:20] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv422_12_bpc
[19:28:20] === [PASSED] drm_test_connector_hdmi_compute_mode_clock ====
[19:28:20] == drm_hdmi_connector_get_broadcast_rgb_name (2 subtests) ==
[19:28:20] === drm_test_drm_hdmi_connector_get_broadcast_rgb_name  ====
[19:28:20] [PASSED] Automatic
[19:28:20] [PASSED] Full
[19:28:20] [PASSED] Limited 16:235
[19:28:20] === [PASSED] drm_test_drm_hdmi_connector_get_broadcast_rgb_name ===
[19:28:20] [PASSED] drm_test_drm_hdmi_connector_get_broadcast_rgb_name_invalid
[19:28:20] ==== [PASSED] drm_hdmi_connector_get_broadcast_rgb_name ====
[19:28:20] == drm_hdmi_connector_get_output_format_name (2 subtests) ==
[19:28:20] === drm_test_drm_hdmi_connector_get_output_format_name  ====
[19:28:20] [PASSED] RGB
[19:28:20] [PASSED] YUV 4:2:0
[19:28:20] [PASSED] YUV 4:2:2
[19:28:20] [PASSED] YUV 4:4:4
[19:28:20] === [PASSED] drm_test_drm_hdmi_connector_get_output_format_name ===
[19:28:20] [PASSED] drm_test_drm_hdmi_connector_get_output_format_name_invalid
[19:28:20] ==== [PASSED] drm_hdmi_connector_get_output_format_name ====
[19:28:20] ============= drm_damage_helper (21 subtests) ==============
[19:28:20] [PASSED] drm_test_damage_iter_no_damage
[19:28:20] [PASSED] drm_test_damage_iter_no_damage_fractional_src
[19:28:20] [PASSED] drm_test_damage_iter_no_damage_src_moved
[19:28:20] [PASSED] drm_test_damage_iter_no_damage_fractional_src_moved
[19:28:20] [PASSED] drm_test_damage_iter_no_damage_not_visible
[19:28:20] [PASSED] drm_test_damage_iter_no_damage_no_crtc
[19:28:20] [PASSED] drm_test_damage_iter_no_damage_no_fb
[19:28:20] [PASSED] drm_test_damage_iter_simple_damage
[19:28:20] [PASSED] drm_test_damage_iter_single_damage
[19:28:20] [PASSED] drm_test_damage_iter_single_damage_intersect_src
[19:28:20] [PASSED] drm_test_damage_iter_single_damage_outside_src
[19:28:20] [PASSED] drm_test_damage_iter_single_damage_fractional_src
[19:28:20] [PASSED] drm_test_damage_iter_single_damage_intersect_fractional_src
[19:28:20] [PASSED] drm_test_damage_iter_single_damage_outside_fractional_src
[19:28:20] [PASSED] drm_test_damage_iter_single_damage_src_moved
[19:28:20] [PASSED] drm_test_damage_iter_single_damage_fractional_src_moved
[19:28:20] [PASSED] drm_test_damage_iter_damage
[19:28:20] [PASSED] drm_test_damage_iter_damage_one_intersect
[19:28:20] [PASSED] drm_test_damage_iter_damage_one_outside
[19:28:20] [PASSED] drm_test_damage_iter_damage_src_moved
[19:28:20] [PASSED] drm_test_damage_iter_damage_not_visible
[19:28:20] ================ [PASSED] drm_damage_helper ================
[19:28:20] ============== drm_dp_mst_helper (3 subtests) ==============
[19:28:20] ============== drm_test_dp_mst_calc_pbn_mode  ==============
[19:28:20] [PASSED] Clock 154000 BPP 30 DSC disabled
[19:28:20] [PASSED] Clock 234000 BPP 30 DSC disabled
[19:28:20] [PASSED] Clock 297000 BPP 24 DSC disabled
[19:28:20] [PASSED] Clock 332880 BPP 24 DSC enabled
[19:28:20] [PASSED] Clock 324540 BPP 24 DSC enabled
[19:28:20] ========== [PASSED] drm_test_dp_mst_calc_pbn_mode ==========
[19:28:20] ============== drm_test_dp_mst_calc_pbn_div  ===============
[19:28:20] [PASSED] Link rate 2000000 lane count 4
[19:28:20] [PASSED] Link rate 2000000 lane count 2
[19:28:20] [PASSED] Link rate 2000000 lane count 1
[19:28:20] [PASSED] Link rate 1350000 lane count 4
[19:28:20] [PASSED] Link rate 1350000 lane count 2
[19:28:20] [PASSED] Link rate 1350000 lane count 1
[19:28:20] [PASSED] Link rate 1000000 lane count 4
[19:28:20] [PASSED] Link rate 1000000 lane count 2
[19:28:20] [PASSED] Link rate 1000000 lane count 1
[19:28:20] [PASSED] Link rate 810000 lane count 4
[19:28:20] [PASSED] Link rate 810000 lane count 2
[19:28:20] [PASSED] Link rate 810000 lane count 1
[19:28:20] [PASSED] Link rate 540000 lane count 4
[19:28:20] [PASSED] Link rate 540000 lane count 2
[19:28:20] [PASSED] Link rate 540000 lane count 1
[19:28:20] [PASSED] Link rate 270000 lane count 4
[19:28:20] [PASSED] Link rate 270000 lane count 2
[19:28:20] [PASSED] Link rate 270000 lane count 1
[19:28:20] [PASSED] Link rate 162000 lane count 4
[19:28:20] [PASSED] Link rate 162000 lane count 2
[19:28:20] [PASSED] Link rate 162000 lane count 1
[19:28:20] ========== [PASSED] drm_test_dp_mst_calc_pbn_div ===========
[19:28:20] ========= drm_test_dp_mst_sideband_msg_req_decode  =========
[19:28:20] [PASSED] DP_ENUM_PATH_RESOURCES with port number
[19:28:20] [PASSED] DP_POWER_UP_PHY with port number
[19:28:20] [PASSED] DP_POWER_DOWN_PHY with port number
[19:28:20] [PASSED] DP_ALLOCATE_PAYLOAD with SDP stream sinks
[19:28:20] [PASSED] DP_ALLOCATE_PAYLOAD with port number
[19:28:20] [PASSED] DP_ALLOCATE_PAYLOAD with VCPI
[19:28:20] [PASSED] DP_ALLOCATE_PAYLOAD with PBN
[19:28:20] [PASSED] DP_QUERY_PAYLOAD with port number
[19:28:20] [PASSED] DP_QUERY_PAYLOAD with VCPI
[19:28:20] [PASSED] DP_REMOTE_DPCD_READ with port number
[19:28:20] [PASSED] DP_REMOTE_DPCD_READ with DPCD address
[19:28:20] [PASSED] DP_REMOTE_DPCD_READ with max number of bytes
[19:28:20] [PASSED] DP_REMOTE_DPCD_WRITE with port number
[19:28:20] [PASSED] DP_REMOTE_DPCD_WRITE with DPCD address
[19:28:20] [PASSED] DP_REMOTE_DPCD_WRITE with data array
[19:28:20] [PASSED] DP_REMOTE_I2C_READ with port number
[19:28:20] [PASSED] DP_REMOTE_I2C_READ with I2C device ID
[19:28:20] [PASSED] DP_REMOTE_I2C_READ with transactions array
[19:28:20] [PASSED] DP_REMOTE_I2C_WRITE with port number
[19:28:20] [PASSED] DP_REMOTE_I2C_WRITE with I2C device ID
[19:28:20] [PASSED] DP_REMOTE_I2C_WRITE with data array
[19:28:20] [PASSED] DP_QUERY_STREAM_ENC_STATUS with stream ID
[19:28:20] [PASSED] DP_QUERY_STREAM_ENC_STATUS with client ID
[19:28:20] [PASSED] DP_QUERY_STREAM_ENC_STATUS with stream event
[19:28:20] [PASSED] DP_QUERY_STREAM_ENC_STATUS with valid stream event
[19:28:20] [PASSED] DP_QUERY_STREAM_ENC_STATUS with stream behavior
[19:28:20] [PASSED] DP_QUERY_STREAM_ENC_STATUS with a valid stream behavior
[19:28:20] ===== [PASSED] drm_test_dp_mst_sideband_msg_req_decode =====
[19:28:20] ================ [PASSED] drm_dp_mst_helper ================
[19:28:20] ================== drm_exec (7 subtests) ===================
[19:28:20] [PASSED] sanitycheck
[19:28:20] [PASSED] test_lock
[19:28:20] [PASSED] test_lock_unlock
[19:28:20] [PASSED] test_duplicates
[19:28:20] [PASSED] test_prepare
[19:28:20] [PASSED] test_prepare_array
[19:28:20] [PASSED] test_multiple_loops
[19:28:20] ==================== [PASSED] drm_exec =====================
[19:28:20] =========== drm_format_helper_test (17 subtests) ===========
[19:28:20] ============== drm_test_fb_xrgb8888_to_gray8  ==============
[19:28:20] [PASSED] single_pixel_source_buffer
[19:28:20] [PASSED] single_pixel_clip_rectangle
[19:28:20] [PASSED] well_known_colors
[19:28:20] [PASSED] destination_pitch
[19:28:20] ========== [PASSED] drm_test_fb_xrgb8888_to_gray8 ==========
[19:28:20] ============= drm_test_fb_xrgb8888_to_rgb332  ==============
[19:28:20] [PASSED] single_pixel_source_buffer
[19:28:20] [PASSED] single_pixel_clip_rectangle
[19:28:20] [PASSED] well_known_colors
[19:28:20] [PASSED] destination_pitch
[19:28:20] ========= [PASSED] drm_test_fb_xrgb8888_to_rgb332 ==========
[19:28:20] ============= drm_test_fb_xrgb8888_to_rgb565  ==============
[19:28:20] [PASSED] single_pixel_source_buffer
[19:28:20] [PASSED] single_pixel_clip_rectangle
[19:28:20] [PASSED] well_known_colors
[19:28:20] [PASSED] destination_pitch
[19:28:20] ========= [PASSED] drm_test_fb_xrgb8888_to_rgb565 ==========
[19:28:20] ============ drm_test_fb_xrgb8888_to_xrgb1555  =============
[19:28:20] [PASSED] single_pixel_source_buffer
[19:28:20] [PASSED] single_pixel_clip_rectangle
[19:28:20] [PASSED] well_known_colors
[19:28:20] [PASSED] destination_pitch
[19:28:20] ======== [PASSED] drm_test_fb_xrgb8888_to_xrgb1555 =========
[19:28:20] ============ drm_test_fb_xrgb8888_to_argb1555  =============
[19:28:20] [PASSED] single_pixel_source_buffer
[19:28:20] [PASSED] single_pixel_clip_rectangle
[19:28:20] [PASSED] well_known_colors
[19:28:20] [PASSED] destination_pitch
[19:28:20] ======== [PASSED] drm_test_fb_xrgb8888_to_argb1555 =========
[19:28:20] ============ drm_test_fb_xrgb8888_to_rgba5551  =============
[19:28:20] [PASSED] single_pixel_source_buffer
[19:28:20] [PASSED] single_pixel_clip_rectangle
[19:28:20] [PASSED] well_known_colors
[19:28:20] [PASSED] destination_pitch
[19:28:20] ======== [PASSED] drm_test_fb_xrgb8888_to_rgba5551 =========
[19:28:20] ============= drm_test_fb_xrgb8888_to_rgb888  ==============
[19:28:20] [PASSED] single_pixel_source_buffer
[19:28:20] [PASSED] single_pixel_clip_rectangle
[19:28:20] [PASSED] well_known_colors
[19:28:20] [PASSED] destination_pitch
[19:28:20] ========= [PASSED] drm_test_fb_xrgb8888_to_rgb888 ==========
[19:28:20] ============= drm_test_fb_xrgb8888_to_bgr888  ==============
[19:28:20] [PASSED] single_pixel_source_buffer
[19:28:20] [PASSED] single_pixel_clip_rectangle
[19:28:20] [PASSED] well_known_colors
[19:28:20] [PASSED] destination_pitch
[19:28:20] ========= [PASSED] drm_test_fb_xrgb8888_to_bgr888 ==========
[19:28:20] ============ drm_test_fb_xrgb8888_to_argb8888  =============
[19:28:20] [PASSED] single_pixel_source_buffer
[19:28:20] [PASSED] single_pixel_clip_rectangle
[19:28:20] [PASSED] well_known_colors
[19:28:20] [PASSED] destination_pitch
[19:28:20] ======== [PASSED] drm_test_fb_xrgb8888_to_argb8888 =========
[19:28:20] =========== drm_test_fb_xrgb8888_to_xrgb2101010  ===========
[19:28:20] [PASSED] single_pixel_source_buffer
[19:28:20] [PASSED] single_pixel_clip_rectangle
[19:28:20] [PASSED] well_known_colors
[19:28:20] [PASSED] destination_pitch
[19:28:20] ======= [PASSED] drm_test_fb_xrgb8888_to_xrgb2101010 =======
[19:28:20] =========== drm_test_fb_xrgb8888_to_argb2101010  ===========
[19:28:20] [PASSED] single_pixel_source_buffer
[19:28:20] [PASSED] single_pixel_clip_rectangle
[19:28:20] [PASSED] well_known_colors
[19:28:20] [PASSED] destination_pitch
[19:28:20] ======= [PASSED] drm_test_fb_xrgb8888_to_argb2101010 =======
[19:28:20] ============== drm_test_fb_xrgb8888_to_mono  ===============
[19:28:20] [PASSED] single_pixel_source_buffer
[19:28:20] [PASSED] single_pixel_clip_rectangle
[19:28:20] [PASSED] well_known_colors
[19:28:20] [PASSED] destination_pitch
[19:28:20] ========== [PASSED] drm_test_fb_xrgb8888_to_mono ===========
[19:28:20] ==================== drm_test_fb_swab  =====================
[19:28:20] [PASSED] single_pixel_source_buffer
[19:28:20] [PASSED] single_pixel_clip_rectangle
[19:28:20] [PASSED] well_known_colors
[19:28:20] [PASSED] destination_pitch
[19:28:20] ================ [PASSED] drm_test_fb_swab =================
[19:28:20] ============ drm_test_fb_xrgb8888_to_xbgr8888  =============
[19:28:20] [PASSED] single_pixel_source_buffer
[19:28:20] [PASSED] single_pixel_clip_rectangle
[19:28:20] [PASSED] well_known_colors
[19:28:20] [PASSED] destination_pitch
[19:28:20] ======== [PASSED] drm_test_fb_xrgb8888_to_xbgr8888 =========
[19:28:20] ============ drm_test_fb_xrgb8888_to_abgr8888  =============
[19:28:20] [PASSED] single_pixel_source_buffer
[19:28:20] [PASSED] single_pixel_clip_rectangle
[19:28:20] [PASSED] well_known_colors
[19:28:20] [PASSED] destination_pitch
[19:28:20] ======== [PASSED] drm_test_fb_xrgb8888_to_abgr8888 =========
[19:28:20] ================= drm_test_fb_clip_offset  =================
[19:28:20] [PASSED] pass through
[19:28:20] [PASSED] horizontal offset
[19:28:20] [PASSED] vertical offset
[19:28:20] [PASSED] horizontal and vertical offset
[19:28:20] [PASSED] horizontal offset (custom pitch)
[19:28:20] [PASSED] vertical offset (custom pitch)
[19:28:20] [PASSED] horizontal and vertical offset (custom pitch)
[19:28:20] ============= [PASSED] drm_test_fb_clip_offset =============
[19:28:20] =================== drm_test_fb_memcpy  ====================
[19:28:20] [PASSED] single_pixel_source_buffer: XR24 little-endian (0x34325258)
[19:28:20] [PASSED] single_pixel_source_buffer: XRA8 little-endian (0x38415258)
[19:28:20] [PASSED] single_pixel_source_buffer: YU24 little-endian (0x34325559)
[19:28:20] [PASSED] single_pixel_clip_rectangle: XB24 little-endian (0x34324258)
[19:28:20] [PASSED] single_pixel_clip_rectangle: XRA8 little-endian (0x38415258)
[19:28:20] [PASSED] single_pixel_clip_rectangle: YU24 little-endian (0x34325559)
[19:28:20] [PASSED] well_known_colors: XB24 little-endian (0x34324258)
[19:28:20] [PASSED] well_known_colors: XRA8 little-endian (0x38415258)
[19:28:20] [PASSED] well_known_colors: YU24 little-endian (0x34325559)
[19:28:20] [PASSED] destination_pitch: XB24 little-endian (0x34324258)
[19:28:20] [PASSED] destination_pitch: XRA8 little-endian (0x38415258)
[19:28:20] [PASSED] destination_pitch: YU24 little-endian (0x34325559)
[19:28:20] =============== [PASSED] drm_test_fb_memcpy ================
[19:28:20] ============= [PASSED] drm_format_helper_test ==============
[19:28:20] ================= drm_format (18 subtests) =================
[19:28:20] [PASSED] drm_test_format_block_width_invalid
[19:28:20] [PASSED] drm_test_format_block_width_one_plane
[19:28:20] [PASSED] drm_test_format_block_width_two_plane
[19:28:20] [PASSED] drm_test_format_block_width_three_plane
[19:28:20] [PASSED] drm_test_format_block_width_tiled
[19:28:20] [PASSED] drm_test_format_block_height_invalid
[19:28:20] [PASSED] drm_test_format_block_height_one_plane
[19:28:20] [PASSED] drm_test_format_block_height_two_plane
[19:28:20] [PASSED] drm_test_format_block_height_three_plane
[19:28:20] [PASSED] drm_test_format_block_height_tiled
[19:28:20] [PASSED] drm_test_format_min_pitch_invalid
[19:28:20] [PASSED] drm_test_format_min_pitch_one_plane_8bpp
[19:28:20] [PASSED] drm_test_format_min_pitch_one_plane_16bpp
[19:28:20] [PASSED] drm_test_format_min_pitch_one_plane_24bpp
[19:28:20] [PASSED] drm_test_format_min_pitch_one_plane_32bpp
[19:28:20] [PASSED] drm_test_format_min_pitch_two_plane
[19:28:20] [PASSED] drm_test_format_min_pitch_three_plane_8bpp
[19:28:20] [PASSED] drm_test_format_min_pitch_tiled
[19:28:20] =================== [PASSED] drm_format ====================
[19:28:20] ============== drm_framebuffer (10 subtests) ===============
[19:28:20] ========== drm_test_framebuffer_check_src_coords  ==========
[19:28:20] [PASSED] Success: source fits into fb
[19:28:20] [PASSED] Fail: overflowing fb with x-axis coordinate
[19:28:20] [PASSED] Fail: overflowing fb with y-axis coordinate
[19:28:20] [PASSED] Fail: overflowing fb with source width
[19:28:20] [PASSED] Fail: overflowing fb with source height
[19:28:20] ====== [PASSED] drm_test_framebuffer_check_src_coords ======
[19:28:20] [PASSED] drm_test_framebuffer_cleanup
[19:28:20] =============== drm_test_framebuffer_create  ===============
[19:28:20] [PASSED] ABGR8888 normal sizes
[19:28:20] [PASSED] ABGR8888 max sizes
[19:28:20] [PASSED] ABGR8888 pitch greater than min required
[19:28:20] [PASSED] ABGR8888 pitch less than min required
[19:28:20] [PASSED] ABGR8888 Invalid width
[19:28:20] [PASSED] ABGR8888 Invalid buffer handle
[19:28:20] [PASSED] No pixel format
[19:28:20] [PASSED] ABGR8888 Width 0
[19:28:20] [PASSED] ABGR8888 Height 0
[19:28:20] [PASSED] ABGR8888 Out of bound height * pitch combination
[19:28:20] [PASSED] ABGR8888 Large buffer offset
[19:28:20] [PASSED] ABGR8888 Buffer offset for inexistent plane
[19:28:20] [PASSED] ABGR8888 Invalid flag
[19:28:20] [PASSED] ABGR8888 Set DRM_MODE_FB_MODIFIERS without modifiers
[19:28:20] [PASSED] ABGR8888 Valid buffer modifier
[19:28:20] [PASSED] ABGR8888 Invalid buffer modifier(DRM_FORMAT_MOD_SAMSUNG_64_32_TILE)
[19:28:20] [PASSED] ABGR8888 Extra pitches without DRM_MODE_FB_MODIFIERS
[19:28:20] [PASSED] ABGR8888 Extra pitches with DRM_MODE_FB_MODIFIERS
[19:28:20] [PASSED] NV12 Normal sizes
[19:28:20] [PASSED] NV12 Max sizes
[19:28:20] [PASSED] NV12 Invalid pitch
[19:28:20] [PASSED] NV12 Invalid modifier/missing DRM_MODE_FB_MODIFIERS flag
[19:28:20] [PASSED] NV12 different  modifier per-plane
[19:28:20] [PASSED] NV12 with DRM_FORMAT_MOD_SAMSUNG_64_32_TILE
[19:28:20] [PASSED] NV12 Valid modifiers without DRM_MODE_FB_MODIFIERS
[19:28:20] [PASSED] NV12 Modifier for inexistent plane
[19:28:20] [PASSED] NV12 Handle for inexistent plane
[19:28:20] [PASSED] NV12 Handle for inexistent plane without DRM_MODE_FB_MODIFIERS
[19:28:20] [PASSED] YVU420 DRM_MODE_FB_MODIFIERS set without modifier
[19:28:20] [PASSED] YVU420 Normal sizes
[19:28:20] [PASSED] YVU420 Max sizes
[19:28:20] [PASSED] YVU420 Invalid pitch
[19:28:20] [PASSED] YVU420 Different pitches
[19:28:20] [PASSED] YVU420 Different buffer offsets/pitches
[19:28:20] [PASSED] YVU420 Modifier set just for plane 0, without DRM_MODE_FB_MODIFIERS
[19:28:20] [PASSED] YVU420 Modifier set just for planes 0, 1, without DRM_MODE_FB_MODIFIERS
[19:28:20] [PASSED] YVU420 Modifier set just for plane 0, 1, with DRM_MODE_FB_MODIFIERS
[19:28:20] [PASSED] YVU420 Valid modifier
[19:28:20] [PASSED] YVU420 Different modifiers per plane
[19:28:20] [PASSED] YVU420 Modifier for inexistent plane
[19:28:20] [PASSED] YUV420_10BIT Invalid modifier(DRM_FORMAT_MOD_LINEAR)
[19:28:20] [PASSED] X0L2 Normal sizes
[19:28:20] [PASSED] X0L2 Max sizes
[19:28:20] [PASSED] X0L2 Invalid pitch
[19:28:20] [PASSED] X0L2 Pitch greater than minimum required
[19:28:20] [PASSED] X0L2 Handle for inexistent plane
[19:28:20] [PASSED] X0L2 Offset for inexistent plane, without DRM_MODE_FB_MODIFIERS set
[19:28:20] [PASSED] X0L2 Modifier without DRM_MODE_FB_MODIFIERS set
[19:28:20] [PASSED] X0L2 Valid modifier
[19:28:20] [PASSED] X0L2 Modifier for inexistent plane
[19:28:20] =========== [PASSED] drm_test_framebuffer_create ===========
[19:28:20] [PASSED] drm_test_framebuffer_free
[19:28:20] [PASSED] drm_test_framebuffer_init
[19:28:20] [PASSED] drm_test_framebuffer_init_bad_format
[19:28:20] [PASSED] drm_test_framebuffer_init_dev_mismatch
[19:28:20] [PASSED] drm_test_framebuffer_lookup
[19:28:20] [PASSED] drm_test_framebuffer_lookup_inexistent
[19:28:20] [PASSED] drm_test_framebuffer_modifiers_not_supported
[19:28:20] ================= [PASSED] drm_framebuffer =================
[19:28:20] ================ drm_gem_shmem (8 subtests) ================
[19:28:20] [PASSED] drm_gem_shmem_test_obj_create
[19:28:20] [PASSED] drm_gem_shmem_test_obj_create_private
[19:28:20] [PASSED] drm_gem_shmem_test_pin_pages
[19:28:20] [PASSED] drm_gem_shmem_test_vmap
[19:28:20] [PASSED] drm_gem_shmem_test_get_sg_table
[19:28:20] [PASSED] drm_gem_shmem_test_get_pages_sgt
[19:28:20] [PASSED] drm_gem_shmem_test_madvise
[19:28:20] [PASSED] drm_gem_shmem_test_purge
[19:28:20] ================== [PASSED] drm_gem_shmem ==================
[19:28:20] === drm_atomic_helper_connector_hdmi_check (27 subtests) ===
[19:28:20] [PASSED] drm_test_check_broadcast_rgb_auto_cea_mode
[19:28:20] [PASSED] drm_test_check_broadcast_rgb_auto_cea_mode_vic_1
[19:28:20] [PASSED] drm_test_check_broadcast_rgb_full_cea_mode
[19:28:20] [PASSED] drm_test_check_broadcast_rgb_full_cea_mode_vic_1
[19:28:20] [PASSED] drm_test_check_broadcast_rgb_limited_cea_mode
[19:28:20] [PASSED] drm_test_check_broadcast_rgb_limited_cea_mode_vic_1
[19:28:20] ====== drm_test_check_broadcast_rgb_cea_mode_yuv420  =======
[19:28:20] [PASSED] Automatic
[19:28:20] [PASSED] Full
[19:28:20] [PASSED] Limited 16:235
[19:28:20] == [PASSED] drm_test_check_broadcast_rgb_cea_mode_yuv420 ===
[19:28:20] [PASSED] drm_test_check_broadcast_rgb_crtc_mode_changed
[19:28:20] [PASSED] drm_test_check_broadcast_rgb_crtc_mode_not_changed
[19:28:20] [PASSED] drm_test_check_disable_connector
[19:28:20] [PASSED] drm_test_check_hdmi_funcs_reject_rate
[19:28:20] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_rgb
[19:28:20] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_yuv420
[19:28:20] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_ignore_yuv422
[19:28:20] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_ignore_yuv420
[19:28:20] [PASSED] drm_test_check_driver_unsupported_fallback_yuv420
[19:28:20] [PASSED] drm_test_check_output_bpc_crtc_mode_changed
[19:28:20] [PASSED] drm_test_check_output_bpc_crtc_mode_not_changed
[19:28:20] [PASSED] drm_test_check_output_bpc_dvi
[19:28:20] [PASSED] drm_test_check_output_bpc_format_vic_1
[19:28:20] [PASSED] drm_test_check_output_bpc_format_display_8bpc_only
[19:28:20] [PASSED] drm_test_check_output_bpc_format_display_rgb_only
[19:28:20] [PASSED] drm_test_check_output_bpc_format_driver_8bpc_only
[19:28:20] [PASSED] drm_test_check_output_bpc_format_driver_rgb_only
[19:28:20] [PASSED] drm_test_check_tmds_char_rate_rgb_8bpc
[19:28:20] [PASSED] drm_test_check_tmds_char_rate_rgb_10bpc
[19:28:20] [PASSED] drm_test_check_tmds_char_rate_rgb_12bpc
[19:28:20] ===== [PASSED] drm_atomic_helper_connector_hdmi_check ======
[19:28:20] === drm_atomic_helper_connector_hdmi_reset (6 subtests) ====
[19:28:20] [PASSED] drm_test_check_broadcast_rgb_value
[19:28:20] [PASSED] drm_test_check_bpc_8_value
[19:28:20] [PASSED] drm_test_check_bpc_10_value
[19:28:20] [PASSED] drm_test_check_bpc_12_value
[19:28:20] [PASSED] drm_test_check_format_value
[19:28:20] [PASSED] drm_test_check_tmds_char_value
[19:28:20] ===== [PASSED] drm_atomic_helper_connector_hdmi_reset ======
[19:28:20] = drm_atomic_helper_connector_hdmi_mode_valid (4 subtests) =
[19:28:20] [PASSED] drm_test_check_mode_valid
[19:28:20] [PASSED] drm_test_check_mode_valid_reject
[19:28:20] [PASSED] drm_test_check_mode_valid_reject_rate
[19:28:20] [PASSED] drm_test_check_mode_valid_reject_max_clock
[19:28:20] === [PASSED] drm_atomic_helper_connector_hdmi_mode_valid ===
[19:28:20] = drm_atomic_helper_connector_hdmi_infoframes (5 subtests) =
[19:28:20] [PASSED] drm_test_check_infoframes
[19:28:20] [PASSED] drm_test_check_reject_avi_infoframe
[19:28:20] [PASSED] drm_test_check_reject_hdr_infoframe_bpc_8
[19:28:20] [PASSED] drm_test_check_reject_hdr_infoframe_bpc_10
[19:28:20] [PASSED] drm_test_check_reject_audio_infoframe
[19:28:20] === [PASSED] drm_atomic_helper_connector_hdmi_infoframes ===
[19:28:20] ================= drm_managed (2 subtests) =================
[19:28:20] [PASSED] drm_test_managed_release_action
[19:28:20] [PASSED] drm_test_managed_run_action
[19:28:20] =================== [PASSED] drm_managed ===================
[19:28:20] =================== drm_mm (6 subtests) ====================
[19:28:20] [PASSED] drm_test_mm_init
[19:28:20] [PASSED] drm_test_mm_debug
[19:28:20] [PASSED] drm_test_mm_align32
[19:28:20] [PASSED] drm_test_mm_align64
[19:28:20] [PASSED] drm_test_mm_lowest
[19:28:20] [PASSED] drm_test_mm_highest
[19:28:20] ===================== [PASSED] drm_mm ======================
[19:28:20] ============= drm_modes_analog_tv (5 subtests) =============
[19:28:20] [PASSED] drm_test_modes_analog_tv_mono_576i
[19:28:20] [PASSED] drm_test_modes_analog_tv_ntsc_480i
[19:28:20] [PASSED] drm_test_modes_analog_tv_ntsc_480i_inlined
[19:28:20] [PASSED] drm_test_modes_analog_tv_pal_576i
[19:28:20] [PASSED] drm_test_modes_analog_tv_pal_576i_inlined
[19:28:20] =============== [PASSED] drm_modes_analog_tv ===============
[19:28:20] ============== drm_plane_helper (2 subtests) ===============
[19:28:20] =============== drm_test_check_plane_state  ================
[19:28:20] [PASSED] clipping_simple
[19:28:20] [PASSED] clipping_rotate_reflect
[19:28:20] [PASSED] positioning_simple
[19:28:20] [PASSED] upscaling
[19:28:20] [PASSED] downscaling
[19:28:20] [PASSED] rounding1
[19:28:20] [PASSED] rounding2
[19:28:20] [PASSED] rounding3
[19:28:20] [PASSED] rounding4
[19:28:20] =========== [PASSED] drm_test_check_plane_state ============
[19:28:20] =========== drm_test_check_invalid_plane_state  ============
[19:28:20] [PASSED] positioning_invalid
[19:28:20] [PASSED] upscaling_invalid
[19:28:20] [PASSED] downscaling_invalid
[19:28:20] ======= [PASSED] drm_test_check_invalid_plane_state ========
[19:28:20] ================ [PASSED] drm_plane_helper =================
[19:28:20] ====== drm_connector_helper_tv_get_modes (1 subtest) =======
[19:28:20] ====== drm_test_connector_helper_tv_get_modes_check  =======
[19:28:20] [PASSED] None
[19:28:20] [PASSED] PAL
[19:28:20] [PASSED] NTSC
[19:28:20] [PASSED] Both, NTSC Default
[19:28:20] [PASSED] Both, PAL Default
[19:28:20] [PASSED] Both, NTSC Default, with PAL on command-line
[19:28:20] [PASSED] Both, PAL Default, with NTSC on command-line
[19:28:20] == [PASSED] drm_test_connector_helper_tv_get_modes_check ===
[19:28:20] ======== [PASSED] drm_connector_helper_tv_get_modes ========
[19:28:20] ================== drm_rect (9 subtests) ===================
[19:28:20] [PASSED] drm_test_rect_clip_scaled_div_by_zero
[19:28:20] [PASSED] drm_test_rect_clip_scaled_not_clipped
[19:28:20] [PASSED] drm_test_rect_clip_scaled_clipped
[19:28:20] [PASSED] drm_test_rect_clip_scaled_signed_vs_unsigned
[19:28:20] ================= drm_test_rect_intersect  =================
[19:28:20] [PASSED] top-left x bottom-right: 2x2+1+1 x 2x2+0+0
[19:28:20] [PASSED] top-right x bottom-left: 2x2+0+0 x 2x2+1-1
[19:28:20] [PASSED] bottom-left x top-right: 2x2+1-1 x 2x2+0+0
[19:28:20] [PASSED] bottom-right x top-left: 2x2+0+0 x 2x2+1+1
[19:28:20] [PASSED] right x left: 2x1+0+0 x 3x1+1+0
[19:28:20] [PASSED] left x right: 3x1+1+0 x 2x1+0+0
[19:28:20] [PASSED] up x bottom: 1x2+0+0 x 1x3+0-1
[19:28:20] [PASSED] bottom x up: 1x3+0-1 x 1x2+0+0
[19:28:20] [PASSED] touching corner: 1x1+0+0 x 2x2+1+1
[19:28:20] [PASSED] touching side: 1x1+0+0 x 1x1+1+0
[19:28:20] [PASSED] equal rects: 2x2+0+0 x 2x2+0+0
[19:28:20] [PASSED] inside another: 2x2+0+0 x 1x1+1+1
[19:28:20] [PASSED] far away: 1x1+0+0 x 1x1+3+6
[19:28:20] [PASSED] points intersecting: 0x0+5+10 x 0x0+5+10
[19:28:20] [PASSED] points not intersecting: 0x0+0+0 x 0x0+5+10
[19:28:20] ============= [PASSED] drm_test_rect_intersect =============
[19:28:20] ================ drm_test_rect_calc_hscale  ================
[19:28:20] [PASSED] normal use
[19:28:20] [PASSED] out of max range
[19:28:20] [PASSED] out of min range
[19:28:20] [PASSED] zero dst
[19:28:20] [PASSED] negative src
[19:28:20] [PASSED] negative dst
[19:28:20] ============ [PASSED] drm_test_rect_calc_hscale ============
[19:28:20] ================ drm_test_rect_calc_vscale  ================
[19:28:20] [PASSED] normal use
[19:28:20] [PASSED] out of max range
[19:28:20] [PASSED] out of min range
[19:28:20] [PASSED] zero dst
[19:28:20] [PASSED] negative src
[19:28:20] [PASSED] negative dst
stty: 'standard input': Inappropriate ioctl for device
[19:28:20] ============ [PASSED] drm_test_rect_calc_vscale ============
[19:28:20] ================== drm_test_rect_rotate  ===================
[19:28:20] [PASSED] reflect-x
[19:28:20] [PASSED] reflect-y
[19:28:20] [PASSED] rotate-0
[19:28:20] [PASSED] rotate-90
[19:28:20] [PASSED] rotate-180
[19:28:20] [PASSED] rotate-270
[19:28:20] ============== [PASSED] drm_test_rect_rotate ===============
[19:28:20] ================ drm_test_rect_rotate_inv  =================
[19:28:20] [PASSED] reflect-x
[19:28:20] [PASSED] reflect-y
[19:28:20] [PASSED] rotate-0
[19:28:20] [PASSED] rotate-90
[19:28:20] [PASSED] rotate-180
[19:28:20] [PASSED] rotate-270
[19:28:20] ============ [PASSED] drm_test_rect_rotate_inv =============
[19:28:20] ==================== [PASSED] drm_rect =====================
[19:28:20] ============ drm_sysfb_modeset_test (1 subtest) ============
[19:28:20] ============ drm_test_sysfb_build_fourcc_list  =============
[19:28:20] [PASSED] no native formats
[19:28:20] [PASSED] XRGB8888 as native format
[19:28:20] [PASSED] remove duplicates
[19:28:20] [PASSED] convert alpha formats
[19:28:20] [PASSED] random formats
[19:28:20] ======== [PASSED] drm_test_sysfb_build_fourcc_list =========
[19:28:20] ============= [PASSED] drm_sysfb_modeset_test ==============
[19:28:20] ================== drm_fixp (2 subtests) ===================
[19:28:20] [PASSED] drm_test_int2fixp
[19:28:20] [PASSED] drm_test_sm2fixp
[19:28:20] ==================== [PASSED] drm_fixp =====================
[19:28:20] ============================================================
[19:28:20] Testing complete. Ran 621 tests: passed: 621
[19:28:20] Elapsed time: 27.386s total, 1.668s configuring, 25.544s building, 0.141s running

+ /kernel/tools/testing/kunit/kunit.py run --kunitconfig /kernel/drivers/gpu/drm/ttm/tests/.kunitconfig
[19:28:20] Configuring KUnit Kernel ...
Regenerating .config ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
[19:28:22] Building KUnit Kernel ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
Building with:
$ make all compile_commands.json scripts_gdb ARCH=um O=.kunit --jobs=48
[19:28:31] Starting KUnit Kernel (1/1)...
[19:28:31] ============================================================
Running tests with:
$ .kunit/linux kunit.enable=1 mem=1G console=tty kunit_shutdown=halt
[19:28:31] ================= ttm_device (5 subtests) ==================
[19:28:31] [PASSED] ttm_device_init_basic
[19:28:31] [PASSED] ttm_device_init_multiple
[19:28:31] [PASSED] ttm_device_fini_basic
[19:28:31] [PASSED] ttm_device_init_no_vma_man
[19:28:31] ================== ttm_device_init_pools  ==================
[19:28:31] [PASSED] No DMA allocations, no DMA32 required
[19:28:31] [PASSED] DMA allocations, DMA32 required
[19:28:31] [PASSED] No DMA allocations, DMA32 required
[19:28:31] [PASSED] DMA allocations, no DMA32 required
[19:28:31] ============== [PASSED] ttm_device_init_pools ==============
[19:28:31] =================== [PASSED] ttm_device ====================
[19:28:31] ================== ttm_pool (8 subtests) ===================
[19:28:31] ================== ttm_pool_alloc_basic  ===================
[19:28:31] [PASSED] One page
[19:28:31] [PASSED] More than one page
[19:28:31] [PASSED] Above the allocation limit
[19:28:31] [PASSED] One page, with coherent DMA mappings enabled
[19:28:31] [PASSED] Above the allocation limit, with coherent DMA mappings enabled
[19:28:31] ============== [PASSED] ttm_pool_alloc_basic ===============
[19:28:31] ============== ttm_pool_alloc_basic_dma_addr  ==============
[19:28:31] [PASSED] One page
[19:28:31] [PASSED] More than one page
[19:28:31] [PASSED] Above the allocation limit
[19:28:31] [PASSED] One page, with coherent DMA mappings enabled
[19:28:31] [PASSED] Above the allocation limit, with coherent DMA mappings enabled
[19:28:31] ========== [PASSED] ttm_pool_alloc_basic_dma_addr ==========
[19:28:31] [PASSED] ttm_pool_alloc_order_caching_match
[19:28:31] [PASSED] ttm_pool_alloc_caching_mismatch
[19:28:31] [PASSED] ttm_pool_alloc_order_mismatch
[19:28:31] [PASSED] ttm_pool_free_dma_alloc
[19:28:31] [PASSED] ttm_pool_free_no_dma_alloc
[19:28:31] [PASSED] ttm_pool_fini_basic
[19:28:31] ==================== [PASSED] ttm_pool =====================
[19:28:31] ================ ttm_resource (8 subtests) =================
[19:28:31] ================= ttm_resource_init_basic  =================
[19:28:31] [PASSED] Init resource in TTM_PL_SYSTEM
[19:28:31] [PASSED] Init resource in TTM_PL_VRAM
[19:28:31] [PASSED] Init resource in a private placement
[19:28:31] [PASSED] Init resource in TTM_PL_SYSTEM, set placement flags
[19:28:31] ============= [PASSED] ttm_resource_init_basic =============
[19:28:31] [PASSED] ttm_resource_init_pinned
[19:28:31] [PASSED] ttm_resource_fini_basic
[19:28:31] [PASSED] ttm_resource_manager_init_basic
[19:28:31] [PASSED] ttm_resource_manager_usage_basic
[19:28:31] [PASSED] ttm_resource_manager_set_used_basic
[19:28:31] [PASSED] ttm_sys_man_alloc_basic
[19:28:31] [PASSED] ttm_sys_man_free_basic
[19:28:31] ================== [PASSED] ttm_resource ===================
[19:28:31] =================== ttm_tt (15 subtests) ===================
[19:28:31] ==================== ttm_tt_init_basic  ====================
[19:28:31] [PASSED] Page-aligned size
[19:28:31] [PASSED] Extra pages requested
[19:28:31] ================ [PASSED] ttm_tt_init_basic ================
[19:28:31] [PASSED] ttm_tt_init_misaligned
[19:28:31] [PASSED] ttm_tt_fini_basic
[19:28:31] [PASSED] ttm_tt_fini_sg
[19:28:31] [PASSED] ttm_tt_fini_shmem
[19:28:31] [PASSED] ttm_tt_create_basic
[19:28:31] [PASSED] ttm_tt_create_invalid_bo_type
[19:28:31] [PASSED] ttm_tt_create_ttm_exists
[19:28:31] [PASSED] ttm_tt_create_failed
[19:28:31] [PASSED] ttm_tt_destroy_basic
[19:28:31] [PASSED] ttm_tt_populate_null_ttm
[19:28:31] [PASSED] ttm_tt_populate_populated_ttm
[19:28:31] [PASSED] ttm_tt_unpopulate_basic
[19:28:31] [PASSED] ttm_tt_unpopulate_empty_ttm
[19:28:31] [PASSED] ttm_tt_swapin_basic
[19:28:31] ===================== [PASSED] ttm_tt ======================
[19:28:31] =================== ttm_bo (14 subtests) ===================
[19:28:31] =========== ttm_bo_reserve_optimistic_no_ticket  ===========
[19:28:31] [PASSED] Cannot be interrupted and sleeps
[19:28:31] [PASSED] Cannot be interrupted, locks straight away
[19:28:31] [PASSED] Can be interrupted, sleeps
[19:28:31] ======= [PASSED] ttm_bo_reserve_optimistic_no_ticket =======
[19:28:31] [PASSED] ttm_bo_reserve_locked_no_sleep
[19:28:31] [PASSED] ttm_bo_reserve_no_wait_ticket
[19:28:31] [PASSED] ttm_bo_reserve_double_resv
[19:28:31] [PASSED] ttm_bo_reserve_interrupted
[19:28:31] [PASSED] ttm_bo_reserve_deadlock
[19:28:31] [PASSED] ttm_bo_unreserve_basic
[19:28:31] [PASSED] ttm_bo_unreserve_pinned
[19:28:31] [PASSED] ttm_bo_unreserve_bulk
[19:28:31] [PASSED] ttm_bo_fini_basic
[19:28:31] [PASSED] ttm_bo_fini_shared_resv
[19:28:31] [PASSED] ttm_bo_pin_basic
[19:28:31] [PASSED] ttm_bo_pin_unpin_resource
[19:28:31] [PASSED] ttm_bo_multiple_pin_one_unpin
[19:28:31] ===================== [PASSED] ttm_bo ======================
[19:28:31] ============== ttm_bo_validate (21 subtests) ===============
[19:28:31] ============== ttm_bo_init_reserved_sys_man  ===============
[19:28:31] [PASSED] Buffer object for userspace
[19:28:31] [PASSED] Kernel buffer object
[19:28:31] [PASSED] Shared buffer object
[19:28:31] ========== [PASSED] ttm_bo_init_reserved_sys_man ===========
[19:28:31] ============== ttm_bo_init_reserved_mock_man  ==============
[19:28:31] [PASSED] Buffer object for userspace
[19:28:31] [PASSED] Kernel buffer object
[19:28:31] [PASSED] Shared buffer object
[19:28:31] ========== [PASSED] ttm_bo_init_reserved_mock_man ==========
[19:28:31] [PASSED] ttm_bo_init_reserved_resv
[19:28:31] ================== ttm_bo_validate_basic  ==================
[19:28:31] [PASSED] Buffer object for userspace
[19:28:31] [PASSED] Kernel buffer object
[19:28:31] [PASSED] Shared buffer object
[19:28:31] ============== [PASSED] ttm_bo_validate_basic ==============
[19:28:31] [PASSED] ttm_bo_validate_invalid_placement
[19:28:31] ============= ttm_bo_validate_same_placement  ==============
[19:28:31] [PASSED] System manager
[19:28:31] [PASSED] VRAM manager
[19:28:31] ========= [PASSED] ttm_bo_validate_same_placement ==========
[19:28:31] [PASSED] ttm_bo_validate_failed_alloc
[19:28:31] [PASSED] ttm_bo_validate_pinned
[19:28:31] [PASSED] ttm_bo_validate_busy_placement
[19:28:31] ================ ttm_bo_validate_multihop  =================
[19:28:31] [PASSED] Buffer object for userspace
[19:28:31] [PASSED] Kernel buffer object
[19:28:31] [PASSED] Shared buffer object
[19:28:31] ============ [PASSED] ttm_bo_validate_multihop =============
[19:28:31] ========== ttm_bo_validate_no_placement_signaled  ==========
[19:28:31] [PASSED] Buffer object in system domain, no page vector
[19:28:31] [PASSED] Buffer object in system domain with an existing page vector
[19:28:31] ====== [PASSED] ttm_bo_validate_no_placement_signaled ======
[19:28:31] ======== ttm_bo_validate_no_placement_not_signaled  ========
[19:28:31] [PASSED] Buffer object for userspace
[19:28:31] [PASSED] Kernel buffer object
[19:28:31] [PASSED] Shared buffer object
[19:28:31] ==== [PASSED] ttm_bo_validate_no_placement_not_signaled ====
[19:28:31] [PASSED] ttm_bo_validate_move_fence_signaled
[19:28:31] ========= ttm_bo_validate_move_fence_not_signaled  =========
[19:28:31] [PASSED] Waits for GPU
[19:28:31] [PASSED] Tries to lock straight away
[19:28:31] ===== [PASSED] ttm_bo_validate_move_fence_not_signaled =====
[19:28:31] [PASSED] ttm_bo_validate_happy_evict
[19:28:31] [PASSED] ttm_bo_validate_all_pinned_evict
[19:28:31] [PASSED] ttm_bo_validate_allowed_only_evict
[19:28:31] [PASSED] ttm_bo_validate_deleted_evict
[19:28:31] [PASSED] ttm_bo_validate_busy_domain_evict
[19:28:31] [PASSED] ttm_bo_validate_evict_gutting
[19:28:31] [PASSED] ttm_bo_validate_recrusive_evict
stty: 'standard input': Inappropriate ioctl for device
[19:28:31] ================= [PASSED] ttm_bo_validate =================
[19:28:31] ============================================================
[19:28:31] Testing complete. Ran 101 tests: passed: 101
[19:28:31] Elapsed time: 11.531s total, 1.700s configuring, 9.615s building, 0.186s running

+ cleanup
++ stat -c %u:%g /kernel
+ chown -R 1003:1003 /kernel

✓ Xe.CI.BAT: success for drm/i915/dp_tunnel: Preparation for UHBR DP tunnels

[Patchwork]

[-- Attachment #1: Type: text/plain, Size: 1478 bytes --]

== Series Details ==

Series: drm/i915/dp_tunnel: Preparation for UHBR DP tunnels
URL   : https://patchwork.freedesktop.org/series/161848/
State : success

== Summary ==

CI Bug Log - changes from xe-4576-cc2c646d39200973cc76d0fa0851d73c9636c27c_BAT -> xe-pw-161848v1_BAT
====================================================

Summary
-------

  **SUCCESS**

  No regressions found.

  

Participating hosts (13 -> 14)
------------------------------

  Additional (1): bat-bmg-3 

Known issues
------------

  Here are the changes found in xe-pw-161848v1_BAT that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@xe_peer2peer@read@read-gpua-vram01-gpub-system-p2p:
    - bat-bmg-3:          NOTRUN -> [SKIP][1] ([Intel XE#6566]) +3 other tests skip
   [1]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161848v1/bat-bmg-3/igt@xe_peer2peer@read@read-gpua-vram01-gpub-system-p2p.html

  
  [Intel XE#6566]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6566


Build changes
-------------

  * IGT: IGT_8762 -> IGT_8763
  * Linux: xe-4576-cc2c646d39200973cc76d0fa0851d73c9636c27c -> xe-pw-161848v1

  IGT_8762: d3c67e0f1fa76ac3d71095825bbc9df0d307e4fc @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
  IGT_8763: 8763
  xe-4576-cc2c646d39200973cc76d0fa0851d73c9636c27c: cc2c646d39200973cc76d0fa0851d73c9636c27c
  xe-pw-161848v1: 161848v1

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161848v1/index.html

[-- Attachment #2: Type: text/html, Size: 2056 bytes --]

✗ Xe.CI.FULL: failure for drm/i915/dp_tunnel: Preparation for UHBR DP tunnels

[Patchwork]

[-- Attachment #1: Type: text/plain, Size: 48431 bytes --]

== Series Details ==

Series: drm/i915/dp_tunnel: Preparation for UHBR DP tunnels
URL   : https://patchwork.freedesktop.org/series/161848/
State : failure

== Summary ==

CI Bug Log - changes from xe-4576-cc2c646d39200973cc76d0fa0851d73c9636c27c_FULL -> xe-pw-161848v1_FULL
====================================================

Summary
-------

  **FAILURE**

  Serious unknown changes coming with xe-pw-161848v1_FULL absolutely need to be
  verified manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in xe-pw-161848v1_FULL, please notify your bug team (I915-ci-infra@lists.freedesktop.org) to allow them
  to document this new failure mode, which will reduce false positives in CI.

  

Participating hosts (2 -> 2)
------------------------------

  No changes in participating hosts

Possible new issues
-------------------

  Here are the unknown changes that may have been introduced in xe-pw-161848v1_FULL:

### IGT changes ###

#### Possible regressions ####

  * igt@kms_pm_dc@dc5-dpms:
    - shard-lnl:          [PASS][1] -> [FAIL][2]
   [1]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4576-cc2c646d39200973cc76d0fa0851d73c9636c27c/shard-lnl-4/igt@kms_pm_dc@dc5-dpms.html
   [2]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161848v1/shard-lnl-4/igt@kms_pm_dc@dc5-dpms.html

  
Known issues
------------

  Here are the changes found in xe-pw-161848v1_FULL that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@kms_big_fb@linear-32bpp-rotate-270:
    - shard-bmg:          NOTRUN -> [SKIP][3] ([Intel XE#2327]) +2 other tests skip
   [3]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161848v1/shard-bmg-9/igt@kms_big_fb@linear-32bpp-rotate-270.html

  * igt@kms_big_fb@x-tiled-64bpp-rotate-270:
    - shard-lnl:          NOTRUN -> [SKIP][4] ([Intel XE#1407]) +1 other test skip
   [4]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161848v1/shard-lnl-2/igt@kms_big_fb@x-tiled-64bpp-rotate-270.html

  * igt@kms_big_fb@y-tiled-64bpp-rotate-90:
    - shard-bmg:          NOTRUN -> [SKIP][5] ([Intel XE#1124]) +10 other tests skip
   [5]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161848v1/shard-bmg-6/igt@kms_big_fb@y-tiled-64bpp-rotate-90.html

  * igt@kms_big_fb@y-tiled-addfb:
    - shard-lnl:          NOTRUN -> [SKIP][6] ([Intel XE#1467])
   [6]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161848v1/shard-lnl-8/igt@kms_big_fb@y-tiled-addfb.html

  * igt@kms_big_fb@yf-tiled-64bpp-rotate-0:
    - shard-lnl:          NOTRUN -> [SKIP][7] ([Intel XE#1124]) +3 other tests skip
   [7]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161848v1/shard-lnl-3/igt@kms_big_fb@yf-tiled-64bpp-rotate-0.html

  * igt@kms_bw@connected-linear-tiling-3-displays-1920x1080p:
    - shard-lnl:          NOTRUN -> [SKIP][8] ([Intel XE#2191])
   [8]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161848v1/shard-lnl-8/igt@kms_bw@connected-linear-tiling-3-displays-1920x1080p.html

  * igt@kms_bw@connected-linear-tiling-4-displays-2560x1440p:
    - shard-bmg:          NOTRUN -> [SKIP][9] ([Intel XE#2314] / [Intel XE#2894]) +2 other tests skip
   [9]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161848v1/shard-bmg-6/igt@kms_bw@connected-linear-tiling-4-displays-2560x1440p.html

  * igt@kms_bw@linear-tiling-1-displays-1920x1080p:
    - shard-bmg:          [PASS][10] -> [SKIP][11] ([Intel XE#367])
   [10]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4576-cc2c646d39200973cc76d0fa0851d73c9636c27c/shard-bmg-5/igt@kms_bw@linear-tiling-1-displays-1920x1080p.html
   [11]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161848v1/shard-bmg-2/igt@kms_bw@linear-tiling-1-displays-1920x1080p.html

  * igt@kms_bw@linear-tiling-2-displays-2160x1440p:
    - shard-lnl:          NOTRUN -> [SKIP][12] ([Intel XE#367])
   [12]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161848v1/shard-lnl-7/igt@kms_bw@linear-tiling-2-displays-2160x1440p.html

  * igt@kms_bw@linear-tiling-4-displays-2160x1440p:
    - shard-bmg:          NOTRUN -> [SKIP][13] ([Intel XE#367]) +2 other tests skip
   [13]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161848v1/shard-bmg-8/igt@kms_bw@linear-tiling-4-displays-2160x1440p.html

  * igt@kms_ccs@crc-primary-rotation-180-y-tiled-gen12-rc-ccs:
    - shard-lnl:          NOTRUN -> [SKIP][14] ([Intel XE#2887]) +4 other tests skip
   [14]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161848v1/shard-lnl-1/igt@kms_ccs@crc-primary-rotation-180-y-tiled-gen12-rc-ccs.html

  * igt@kms_ccs@crc-primary-suspend-4-tiled-bmg-ccs:
    - shard-bmg:          [PASS][15] -> [INCOMPLETE][16] ([Intel XE#7084]) +1 other test incomplete
   [15]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4576-cc2c646d39200973cc76d0fa0851d73c9636c27c/shard-bmg-8/igt@kms_ccs@crc-primary-suspend-4-tiled-bmg-ccs.html
   [16]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161848v1/shard-bmg-8/igt@kms_ccs@crc-primary-suspend-4-tiled-bmg-ccs.html

  * igt@kms_ccs@crc-primary-suspend-4-tiled-dg2-rc-ccs-cc:
    - shard-bmg:          NOTRUN -> [SKIP][17] ([Intel XE#3432]) +1 other test skip
   [17]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161848v1/shard-bmg-5/igt@kms_ccs@crc-primary-suspend-4-tiled-dg2-rc-ccs-cc.html

  * igt@kms_ccs@crc-primary-suspend-4-tiled-mtl-rc-ccs-cc:
    - shard-lnl:          NOTRUN -> [SKIP][18] ([Intel XE#3432])
   [18]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161848v1/shard-lnl-3/igt@kms_ccs@crc-primary-suspend-4-tiled-mtl-rc-ccs-cc.html

  * igt@kms_ccs@crc-sprite-planes-basic-4-tiled-lnl-ccs@pipe-b-dp-2:
    - shard-bmg:          NOTRUN -> [SKIP][19] ([Intel XE#2652]) +3 other tests skip
   [19]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161848v1/shard-bmg-4/igt@kms_ccs@crc-sprite-planes-basic-4-tiled-lnl-ccs@pipe-b-dp-2.html

  * igt@kms_ccs@random-ccs-data-y-tiled-gen12-rc-ccs:
    - shard-bmg:          NOTRUN -> [SKIP][20] ([Intel XE#2887]) +14 other tests skip
   [20]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161848v1/shard-bmg-2/igt@kms_ccs@random-ccs-data-y-tiled-gen12-rc-ccs.html

  * igt@kms_chamelium_color@ctm-max:
    - shard-bmg:          NOTRUN -> [SKIP][21] ([Intel XE#2325]) +1 other test skip
   [21]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161848v1/shard-bmg-9/igt@kms_chamelium_color@ctm-max.html

  * igt@kms_chamelium_color@gamma:
    - shard-lnl:          NOTRUN -> [SKIP][22] ([Intel XE#306])
   [22]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161848v1/shard-lnl-8/igt@kms_chamelium_color@gamma.html

  * igt@kms_chamelium_edid@dp-edid-change-during-suspend:
    - shard-lnl:          NOTRUN -> [SKIP][23] ([Intel XE#373]) +2 other tests skip
   [23]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161848v1/shard-lnl-7/igt@kms_chamelium_edid@dp-edid-change-during-suspend.html

  * igt@kms_chamelium_hpd@common-hpd-after-hibernate:
    - shard-bmg:          NOTRUN -> [SKIP][24] ([Intel XE#2252]) +6 other tests skip
   [24]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161848v1/shard-bmg-7/igt@kms_chamelium_hpd@common-hpd-after-hibernate.html

  * igt@kms_chamelium_sharpness_filter@filter-basic:
    - shard-bmg:          NOTRUN -> [SKIP][25] ([Intel XE#6507])
   [25]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161848v1/shard-bmg-3/igt@kms_chamelium_sharpness_filter@filter-basic.html

  * igt@kms_color_pipeline@plane-lut1d-ctm3x4@pipe-c-edp-1:
    - shard-lnl:          NOTRUN -> [FAIL][26] ([Intel XE#6968]) +3 other tests fail
   [26]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161848v1/shard-lnl-4/igt@kms_color_pipeline@plane-lut1d-ctm3x4@pipe-c-edp-1.html

  * igt@kms_content_protection@atomic-dpms-hdcp14:
    - shard-lnl:          NOTRUN -> [SKIP][27] ([Intel XE#6973])
   [27]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161848v1/shard-lnl-8/igt@kms_content_protection@atomic-dpms-hdcp14.html

  * igt@kms_content_protection@atomic-dpms-hdcp14@pipe-a-dp-2:
    - shard-bmg:          NOTRUN -> [FAIL][28] ([Intel XE#3304]) +1 other test fail
   [28]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161848v1/shard-bmg-8/igt@kms_content_protection@atomic-dpms-hdcp14@pipe-a-dp-2.html

  * igt@kms_content_protection@dp-mst-type-0-suspend-resume:
    - shard-bmg:          NOTRUN -> [SKIP][29] ([Intel XE#6974])
   [29]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161848v1/shard-bmg-3/igt@kms_content_protection@dp-mst-type-0-suspend-resume.html

  * igt@kms_content_protection@mei-interface:
    - shard-bmg:          NOTRUN -> [SKIP][30] ([Intel XE#2341])
   [30]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161848v1/shard-bmg-5/igt@kms_content_protection@mei-interface.html

  * igt@kms_content_protection@uevent:
    - shard-bmg:          NOTRUN -> [FAIL][31] ([Intel XE#6707]) +1 other test fail
   [31]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161848v1/shard-bmg-1/igt@kms_content_protection@uevent.html

  * igt@kms_cursor_crc@cursor-offscreen-512x512:
    - shard-lnl:          NOTRUN -> [SKIP][32] ([Intel XE#2321])
   [32]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161848v1/shard-lnl-8/igt@kms_cursor_crc@cursor-offscreen-512x512.html

  * igt@kms_cursor_crc@cursor-onscreen-32x10:
    - shard-bmg:          NOTRUN -> [SKIP][33] ([Intel XE#2320]) +3 other tests skip
   [33]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161848v1/shard-bmg-6/igt@kms_cursor_crc@cursor-onscreen-32x10.html

  * igt@kms_cursor_crc@cursor-sliding-32x10:
    - shard-lnl:          NOTRUN -> [SKIP][34] ([Intel XE#1424]) +2 other tests skip
   [34]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161848v1/shard-lnl-3/igt@kms_cursor_crc@cursor-sliding-32x10.html

  * igt@kms_cursor_edge_walk@256x256-right-edge:
    - shard-bmg:          NOTRUN -> [FAIL][35] ([Intel XE#6841]) +1 other test fail
   [35]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161848v1/shard-bmg-2/igt@kms_cursor_edge_walk@256x256-right-edge.html

  * igt@kms_cursor_legacy@cursorb-vs-flipa-toggle:
    - shard-lnl:          NOTRUN -> [SKIP][36] ([Intel XE#309])
   [36]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161848v1/shard-lnl-4/igt@kms_cursor_legacy@cursorb-vs-flipa-toggle.html

  * igt@kms_cursor_legacy@flip-vs-cursor-legacy:
    - shard-bmg:          [PASS][37] -> [FAIL][38] ([Intel XE#5299])
   [37]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4576-cc2c646d39200973cc76d0fa0851d73c9636c27c/shard-bmg-8/igt@kms_cursor_legacy@flip-vs-cursor-legacy.html
   [38]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161848v1/shard-bmg-2/igt@kms_cursor_legacy@flip-vs-cursor-legacy.html

  * igt@kms_dirtyfb@psr-dirtyfb-ioctl:
    - shard-bmg:          NOTRUN -> [SKIP][39] ([Intel XE#1508])
   [39]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161848v1/shard-bmg-7/igt@kms_dirtyfb@psr-dirtyfb-ioctl.html

  * igt@kms_dp_linktrain_fallback@dsc-fallback:
    - shard-lnl:          NOTRUN -> [SKIP][40] ([Intel XE#4331])
   [40]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161848v1/shard-lnl-1/igt@kms_dp_linktrain_fallback@dsc-fallback.html

  * igt@kms_dsc@dsc-fractional-bpp-with-bpc:
    - shard-bmg:          NOTRUN -> [SKIP][41] ([Intel XE#2244])
   [41]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161848v1/shard-bmg-5/igt@kms_dsc@dsc-fractional-bpp-with-bpc.html

  * igt@kms_feature_discovery@display-3x:
    - shard-bmg:          NOTRUN -> [SKIP][42] ([Intel XE#2373])
   [42]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161848v1/shard-bmg-9/igt@kms_feature_discovery@display-3x.html

  * igt@kms_flip@2x-flip-vs-rmfb-interruptible:
    - shard-lnl:          NOTRUN -> [SKIP][43] ([Intel XE#1421]) +2 other tests skip
   [43]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161848v1/shard-lnl-8/igt@kms_flip@2x-flip-vs-rmfb-interruptible.html

  * igt@kms_flip@flip-vs-expired-vblank-interruptible@b-edp1:
    - shard-lnl:          [PASS][44] -> [FAIL][45] ([Intel XE#301]) +3 other tests fail
   [44]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4576-cc2c646d39200973cc76d0fa0851d73c9636c27c/shard-lnl-1/igt@kms_flip@flip-vs-expired-vblank-interruptible@b-edp1.html
   [45]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161848v1/shard-lnl-2/igt@kms_flip@flip-vs-expired-vblank-interruptible@b-edp1.html

  * igt@kms_flip@flip-vs-suspend-interruptible:
    - shard-bmg:          [PASS][46] -> [INCOMPLETE][47] ([Intel XE#2049] / [Intel XE#2597]) +1 other test incomplete
   [46]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4576-cc2c646d39200973cc76d0fa0851d73c9636c27c/shard-bmg-4/igt@kms_flip@flip-vs-suspend-interruptible.html
   [47]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161848v1/shard-bmg-5/igt@kms_flip@flip-vs-suspend-interruptible.html

  * igt@kms_flip_scaled_crc@flip-32bpp-yftile-to-64bpp-yftile-downscaling:
    - shard-lnl:          NOTRUN -> [SKIP][48] ([Intel XE#7178]) +1 other test skip
   [48]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161848v1/shard-lnl-2/igt@kms_flip_scaled_crc@flip-32bpp-yftile-to-64bpp-yftile-downscaling.html

  * igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-16bpp-ytile-upscaling:
    - shard-bmg:          NOTRUN -> [SKIP][49] ([Intel XE#7178]) +4 other tests skip
   [49]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161848v1/shard-bmg-2/igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-16bpp-ytile-upscaling.html

  * igt@kms_flip_scaled_crc@flip-nv12-linear-to-nv12-linear-reflect-x:
    - shard-bmg:          NOTRUN -> [SKIP][50] ([Intel XE#7179])
   [50]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161848v1/shard-bmg-2/igt@kms_flip_scaled_crc@flip-nv12-linear-to-nv12-linear-reflect-x.html

  * igt@kms_frontbuffer_tracking@drrs-2p-scndscrn-spr-indfb-fullscreen:
    - shard-lnl:          NOTRUN -> [SKIP][51] ([Intel XE#656]) +12 other tests skip
   [51]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161848v1/shard-lnl-1/igt@kms_frontbuffer_tracking@drrs-2p-scndscrn-spr-indfb-fullscreen.html

  * igt@kms_frontbuffer_tracking@drrs-abgr161616f-draw-mmap-wc:
    - shard-bmg:          NOTRUN -> [SKIP][52] ([Intel XE#7061]) +3 other tests skip
   [52]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161848v1/shard-bmg-7/igt@kms_frontbuffer_tracking@drrs-abgr161616f-draw-mmap-wc.html

  * igt@kms_frontbuffer_tracking@drrs-rgb565-draw-mmap-wc:
    - shard-bmg:          NOTRUN -> [SKIP][53] ([Intel XE#2311]) +23 other tests skip
   [53]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161848v1/shard-bmg-6/igt@kms_frontbuffer_tracking@drrs-rgb565-draw-mmap-wc.html

  * igt@kms_frontbuffer_tracking@fbc-1p-offscreen-pri-shrfb-draw-blt:
    - shard-bmg:          NOTRUN -> [SKIP][54] ([Intel XE#4141]) +18 other tests skip
   [54]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161848v1/shard-bmg-7/igt@kms_frontbuffer_tracking@fbc-1p-offscreen-pri-shrfb-draw-blt.html

  * igt@kms_frontbuffer_tracking@fbc-tiling-y:
    - shard-bmg:          NOTRUN -> [SKIP][55] ([Intel XE#2352])
   [55]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161848v1/shard-bmg-7/igt@kms_frontbuffer_tracking@fbc-tiling-y.html

  * igt@kms_frontbuffer_tracking@fbcdrrs-1p-primscrn-cur-indfb-draw-render:
    - shard-lnl:          NOTRUN -> [SKIP][56] ([Intel XE#651]) +4 other tests skip
   [56]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161848v1/shard-lnl-2/igt@kms_frontbuffer_tracking@fbcdrrs-1p-primscrn-cur-indfb-draw-render.html

  * igt@kms_frontbuffer_tracking@fbcdrrs-abgr161616f-draw-blt:
    - shard-lnl:          NOTRUN -> [SKIP][57] ([Intel XE#7061]) +2 other tests skip
   [57]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161848v1/shard-lnl-3/igt@kms_frontbuffer_tracking@fbcdrrs-abgr161616f-draw-blt.html

  * igt@kms_frontbuffer_tracking@psr-2p-scndscrn-indfb-pgflip-blt:
    - shard-bmg:          NOTRUN -> [SKIP][58] ([Intel XE#2313]) +30 other tests skip
   [58]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161848v1/shard-bmg-4/igt@kms_frontbuffer_tracking@psr-2p-scndscrn-indfb-pgflip-blt.html

  * igt@kms_joiner@basic-big-joiner:
    - shard-lnl:          NOTRUN -> [SKIP][59] ([Intel XE#6901])
   [59]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161848v1/shard-lnl-4/igt@kms_joiner@basic-big-joiner.html

  * igt@kms_pipe_stress@stress-xrgb8888-ytiled:
    - shard-bmg:          NOTRUN -> [SKIP][60] ([Intel XE#4329] / [Intel XE#6912])
   [60]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161848v1/shard-bmg-2/igt@kms_pipe_stress@stress-xrgb8888-ytiled.html

  * igt@kms_plane@pixel-format-x-tiled-modifier@pipe-b-plane-5:
    - shard-bmg:          NOTRUN -> [SKIP][61] ([Intel XE#7130]) +1 other test skip
   [61]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161848v1/shard-bmg-5/igt@kms_plane@pixel-format-x-tiled-modifier@pipe-b-plane-5.html

  * igt@kms_plane@pixel-format-y-tiled-modifier-source-clamping:
    - shard-lnl:          NOTRUN -> [SKIP][62] ([Intel XE#7283]) +1 other test skip
   [62]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161848v1/shard-lnl-4/igt@kms_plane@pixel-format-y-tiled-modifier-source-clamping.html

  * igt@kms_plane@pixel-format-yf-tiled-ccs-modifier-source-clamping:
    - shard-bmg:          NOTRUN -> [SKIP][63] ([Intel XE#7283]) +3 other tests skip
   [63]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161848v1/shard-bmg-3/igt@kms_plane@pixel-format-yf-tiled-ccs-modifier-source-clamping.html

  * igt@kms_plane_lowres@tiling-none@pipe-b-edp-1:
    - shard-lnl:          NOTRUN -> [SKIP][64] ([Intel XE#599]) +3 other tests skip
   [64]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161848v1/shard-lnl-7/igt@kms_plane_lowres@tiling-none@pipe-b-edp-1.html

  * igt@kms_plane_multiple@2x-tiling-yf:
    - shard-lnl:          NOTRUN -> [SKIP][65] ([Intel XE#4596])
   [65]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161848v1/shard-lnl-5/igt@kms_plane_multiple@2x-tiling-yf.html

  * igt@kms_plane_multiple@tiling-yf:
    - shard-bmg:          NOTRUN -> [SKIP][66] ([Intel XE#5020])
   [66]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161848v1/shard-bmg-5/igt@kms_plane_multiple@tiling-yf.html

  * igt@kms_plane_scaling@planes-downscale-factor-0-75@pipe-a:
    - shard-lnl:          NOTRUN -> [SKIP][67] ([Intel XE#2763] / [Intel XE#6886]) +3 other tests skip
   [67]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161848v1/shard-lnl-2/igt@kms_plane_scaling@planes-downscale-factor-0-75@pipe-a.html

  * igt@kms_plane_scaling@planes-upscale-factor-0-25-downscale-factor-0-5:
    - shard-bmg:          NOTRUN -> [SKIP][68] ([Intel XE#2763] / [Intel XE#6886]) +14 other tests skip
   [68]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161848v1/shard-bmg-9/igt@kms_plane_scaling@planes-upscale-factor-0-25-downscale-factor-0-5.html

  * igt@kms_pm_dc@dc3co-vpb-simulation:
    - shard-bmg:          NOTRUN -> [SKIP][69] ([Intel XE#2391])
   [69]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161848v1/shard-bmg-1/igt@kms_pm_dc@dc3co-vpb-simulation.html

  * igt@kms_pm_rpm@dpms-lpsp:
    - shard-bmg:          NOTRUN -> [SKIP][70] ([Intel XE#1439] / [Intel XE#3141] / [Intel XE#836]) +1 other test skip
   [70]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161848v1/shard-bmg-4/igt@kms_pm_rpm@dpms-lpsp.html

  * igt@kms_psr2_sf@fbc-pr-overlay-primary-update-sf-dmg-area:
    - shard-lnl:          NOTRUN -> [SKIP][71] ([Intel XE#1406] / [Intel XE#2893]) +1 other test skip
   [71]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161848v1/shard-lnl-1/igt@kms_psr2_sf@fbc-pr-overlay-primary-update-sf-dmg-area.html

  * igt@kms_psr2_sf@psr2-primary-plane-update-sf-dmg-area-big-fb:
    - shard-bmg:          NOTRUN -> [SKIP][72] ([Intel XE#1406] / [Intel XE#1489]) +7 other tests skip
   [72]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161848v1/shard-bmg-6/igt@kms_psr2_sf@psr2-primary-plane-update-sf-dmg-area-big-fb.html

  * igt@kms_psr2_su@page_flip-nv12:
    - shard-lnl:          NOTRUN -> [SKIP][73] ([Intel XE#1128] / [Intel XE#1406])
   [73]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161848v1/shard-lnl-5/igt@kms_psr2_su@page_flip-nv12.html
    - shard-bmg:          NOTRUN -> [SKIP][74] ([Intel XE#1406] / [Intel XE#2387])
   [74]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161848v1/shard-bmg-7/igt@kms_psr2_su@page_flip-nv12.html

  * igt@kms_psr@fbc-psr2-cursor-plane-move:
    - shard-bmg:          NOTRUN -> [SKIP][75] ([Intel XE#1406] / [Intel XE#2234] / [Intel XE#2850]) +9 other tests skip
   [75]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161848v1/shard-bmg-3/igt@kms_psr@fbc-psr2-cursor-plane-move.html

  * igt@kms_psr@fbc-psr2-sprite-render:
    - shard-lnl:          NOTRUN -> [SKIP][76] ([Intel XE#1406]) +1 other test skip
   [76]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161848v1/shard-lnl-4/igt@kms_psr@fbc-psr2-sprite-render.html

  * igt@kms_psr@fbc-psr2-sprite-render@edp-1:
    - shard-lnl:          NOTRUN -> [SKIP][77] ([Intel XE#1406] / [Intel XE#4609]) +1 other test skip
   [77]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161848v1/shard-lnl-4/igt@kms_psr@fbc-psr2-sprite-render@edp-1.html

  * igt@kms_rotation_crc@primary-y-tiled-reflect-x-90:
    - shard-bmg:          NOTRUN -> [SKIP][78] ([Intel XE#3414] / [Intel XE#3904]) +1 other test skip
   [78]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161848v1/shard-bmg-2/igt@kms_rotation_crc@primary-y-tiled-reflect-x-90.html

  * igt@kms_rotation_crc@primary-yf-tiled-reflect-x-180:
    - shard-bmg:          NOTRUN -> [SKIP][79] ([Intel XE#2330])
   [79]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161848v1/shard-bmg-5/igt@kms_rotation_crc@primary-yf-tiled-reflect-x-180.html

  * igt@kms_rotation_crc@primary-yf-tiled-reflect-x-270:
    - shard-lnl:          NOTRUN -> [SKIP][80] ([Intel XE#3414] / [Intel XE#3904]) +1 other test skip
   [80]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161848v1/shard-lnl-4/igt@kms_rotation_crc@primary-yf-tiled-reflect-x-270.html

  * igt@kms_scaling_modes@scaling-mode-full:
    - shard-bmg:          NOTRUN -> [SKIP][81] ([Intel XE#2413])
   [81]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161848v1/shard-bmg-4/igt@kms_scaling_modes@scaling-mode-full.html

  * igt@kms_setmode@basic-clone-single-crtc:
    - shard-bmg:          NOTRUN -> [SKIP][82] ([Intel XE#1435])
   [82]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161848v1/shard-bmg-5/igt@kms_setmode@basic-clone-single-crtc.html

  * igt@kms_sharpness_filter@invalid-filter-with-scaling-mode:
    - shard-bmg:          NOTRUN -> [SKIP][83] ([Intel XE#6503]) +4 other tests skip
   [83]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161848v1/shard-bmg-1/igt@kms_sharpness_filter@invalid-filter-with-scaling-mode.html

  * igt@kms_tiled_display@basic-test-pattern:
    - shard-bmg:          NOTRUN -> [SKIP][84] ([Intel XE#2426])
   [84]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161848v1/shard-bmg-5/igt@kms_tiled_display@basic-test-pattern.html

  * igt@kms_vrr@seamless-rr-switch-drrs:
    - shard-bmg:          NOTRUN -> [SKIP][85] ([Intel XE#1499]) +1 other test skip
   [85]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161848v1/shard-bmg-5/igt@kms_vrr@seamless-rr-switch-drrs.html

  * igt@kms_vrr@seamless-rr-switch-virtual@pipe-a-edp-1:
    - shard-lnl:          [PASS][86] -> [FAIL][87] ([Intel XE#2142]) +1 other test fail
   [86]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4576-cc2c646d39200973cc76d0fa0851d73c9636c27c/shard-lnl-8/igt@kms_vrr@seamless-rr-switch-virtual@pipe-a-edp-1.html
   [87]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161848v1/shard-lnl-2/igt@kms_vrr@seamless-rr-switch-virtual@pipe-a-edp-1.html

  * igt@xe_compute@ccs-mode-basic:
    - shard-bmg:          NOTRUN -> [SKIP][88] ([Intel XE#6599]) +1 other test skip
   [88]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161848v1/shard-bmg-9/igt@xe_compute@ccs-mode-basic.html

  * igt@xe_compute@ccs-mode-compute-kernel:
    - shard-lnl:          NOTRUN -> [SKIP][89] ([Intel XE#1447])
   [89]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161848v1/shard-lnl-8/igt@xe_compute@ccs-mode-compute-kernel.html

  * igt@xe_compute_preempt@compute-preempt-many-vram-evict:
    - shard-lnl:          NOTRUN -> [SKIP][90] ([Intel XE#5191])
   [90]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161848v1/shard-lnl-2/igt@xe_compute_preempt@compute-preempt-many-vram-evict.html

  * igt@xe_eudebug@basic-vm-access-faultable:
    - shard-lnl:          NOTRUN -> [SKIP][91] ([Intel XE#4837]) +4 other tests skip
   [91]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161848v1/shard-lnl-5/igt@xe_eudebug@basic-vm-access-faultable.html

  * igt@xe_eudebug@vm-bind-clear:
    - shard-bmg:          NOTRUN -> [SKIP][92] ([Intel XE#4837]) +8 other tests skip
   [92]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161848v1/shard-bmg-7/igt@xe_eudebug@vm-bind-clear.html

  * igt@xe_eudebug_online@pagefault-one-of-many:
    - shard-lnl:          NOTRUN -> [SKIP][93] ([Intel XE#6665])
   [93]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161848v1/shard-lnl-8/igt@xe_eudebug_online@pagefault-one-of-many.html
    - shard-bmg:          NOTRUN -> [SKIP][94] ([Intel XE#6665])
   [94]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161848v1/shard-bmg-5/igt@xe_eudebug_online@pagefault-one-of-many.html

  * igt@xe_eudebug_online@set-breakpoint-sigint-debugger:
    - shard-bmg:          NOTRUN -> [SKIP][95] ([Intel XE#4837] / [Intel XE#6665]) +3 other tests skip
   [95]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161848v1/shard-bmg-4/igt@xe_eudebug_online@set-breakpoint-sigint-debugger.html

  * igt@xe_eudebug_online@writes-caching-vram-bb-vram-target-vram:
    - shard-lnl:          NOTRUN -> [SKIP][96] ([Intel XE#4837] / [Intel XE#6665])
   [96]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161848v1/shard-lnl-8/igt@xe_eudebug_online@writes-caching-vram-bb-vram-target-vram.html

  * igt@xe_evict@evict-large-multi-vm:
    - shard-lnl:          NOTRUN -> [SKIP][97] ([Intel XE#6540] / [Intel XE#688]) +4 other tests skip
   [97]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161848v1/shard-lnl-8/igt@xe_evict@evict-large-multi-vm.html

  * igt@xe_exec_basic@multigpu-no-exec-userptr-invalidate:
    - shard-lnl:          NOTRUN -> [SKIP][98] ([Intel XE#1392]) +2 other tests skip
   [98]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161848v1/shard-lnl-8/igt@xe_exec_basic@multigpu-no-exec-userptr-invalidate.html

  * igt@xe_exec_basic@multigpu-once-null-rebind:
    - shard-bmg:          NOTRUN -> [SKIP][99] ([Intel XE#2322]) +8 other tests skip
   [99]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161848v1/shard-bmg-7/igt@xe_exec_basic@multigpu-once-null-rebind.html

  * igt@xe_exec_fault_mode@many-execqueues-multi-queue-prefetch:
    - shard-lnl:          NOTRUN -> [SKIP][100] ([Intel XE#7136]) +4 other tests skip
   [100]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161848v1/shard-lnl-7/igt@xe_exec_fault_mode@many-execqueues-multi-queue-prefetch.html

  * igt@xe_exec_fault_mode@many-multi-queue-userptr-invalidate-race-imm:
    - shard-bmg:          NOTRUN -> [SKIP][101] ([Intel XE#7136]) +13 other tests skip
   [101]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161848v1/shard-bmg-7/igt@xe_exec_fault_mode@many-multi-queue-userptr-invalidate-race-imm.html

  * igt@xe_exec_multi_queue@max-queues-preempt-mode-close-fd:
    - shard-lnl:          NOTRUN -> [SKIP][102] ([Intel XE#6874]) +13 other tests skip
   [102]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161848v1/shard-lnl-7/igt@xe_exec_multi_queue@max-queues-preempt-mode-close-fd.html

  * igt@xe_exec_multi_queue@one-queue-priority-smem:
    - shard-bmg:          NOTRUN -> [SKIP][103] ([Intel XE#6874]) +31 other tests skip
   [103]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161848v1/shard-bmg-5/igt@xe_exec_multi_queue@one-queue-priority-smem.html

  * igt@xe_exec_threads@threads-bal-mixed-fd-userptr:
    - shard-bmg:          [PASS][104] -> [FAIL][105] ([Intel XE#5625])
   [104]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4576-cc2c646d39200973cc76d0fa0851d73c9636c27c/shard-bmg-1/igt@xe_exec_threads@threads-bal-mixed-fd-userptr.html
   [105]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161848v1/shard-bmg-2/igt@xe_exec_threads@threads-bal-mixed-fd-userptr.html

  * igt@xe_exec_threads@threads-many-queues:
    - shard-bmg:          NOTRUN -> [FAIL][106] ([Intel XE#7166])
   [106]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161848v1/shard-bmg-6/igt@xe_exec_threads@threads-many-queues.html

  * igt@xe_exec_threads@threads-multi-queue-mixed-shared-vm-rebind:
    - shard-lnl:          NOTRUN -> [SKIP][107] ([Intel XE#7138]) +3 other tests skip
   [107]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161848v1/shard-lnl-2/igt@xe_exec_threads@threads-multi-queue-mixed-shared-vm-rebind.html
    - shard-bmg:          NOTRUN -> [SKIP][108] ([Intel XE#7138]) +7 other tests skip
   [108]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161848v1/shard-bmg-2/igt@xe_exec_threads@threads-multi-queue-mixed-shared-vm-rebind.html

  * igt@xe_media_fill@media-fill:
    - shard-bmg:          NOTRUN -> [SKIP][109] ([Intel XE#2459] / [Intel XE#2596])
   [109]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161848v1/shard-bmg-8/igt@xe_media_fill@media-fill.html

  * igt@xe_mmap@pci-membarrier-parallel:
    - shard-lnl:          NOTRUN -> [SKIP][110] ([Intel XE#5100]) +1 other test skip
   [110]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161848v1/shard-lnl-4/igt@xe_mmap@pci-membarrier-parallel.html

  * igt@xe_mmap@small-bar:
    - shard-bmg:          NOTRUN -> [SKIP][111] ([Intel XE#586])
   [111]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161848v1/shard-bmg-1/igt@xe_mmap@small-bar.html

  * igt@xe_multigpu_svm@mgpu-coherency-prefetch:
    - shard-lnl:          NOTRUN -> [SKIP][112] ([Intel XE#6964])
   [112]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161848v1/shard-lnl-2/igt@xe_multigpu_svm@mgpu-coherency-prefetch.html
    - shard-bmg:          NOTRUN -> [SKIP][113] ([Intel XE#6964]) +2 other tests skip
   [113]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161848v1/shard-bmg-2/igt@xe_multigpu_svm@mgpu-coherency-prefetch.html

  * igt@xe_peer2peer@write:
    - shard-bmg:          NOTRUN -> [SKIP][114] ([Intel XE#2427] / [Intel XE#6953])
   [114]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161848v1/shard-bmg-6/igt@xe_peer2peer@write.html
    - shard-lnl:          NOTRUN -> [SKIP][115] ([Intel XE#1061])
   [115]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161848v1/shard-lnl-3/igt@xe_peer2peer@write.html

  * igt@xe_pm@d3hot-i2c:
    - shard-lnl:          NOTRUN -> [SKIP][116] ([Intel XE#5742])
   [116]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161848v1/shard-lnl-8/igt@xe_pm@d3hot-i2c.html

  * igt@xe_pm@s3-basic-exec:
    - shard-lnl:          NOTRUN -> [SKIP][117] ([Intel XE#584])
   [117]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161848v1/shard-lnl-4/igt@xe_pm@s3-basic-exec.html

  * igt@xe_pm@vram-d3cold-threshold:
    - shard-lnl:          NOTRUN -> [SKIP][118] ([Intel XE#579])
   [118]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161848v1/shard-lnl-3/igt@xe_pm@vram-d3cold-threshold.html

  * igt@xe_pm_residency@aspm_link_residency:
    - shard-bmg:          [PASS][119] -> [SKIP][120] ([Intel XE#7258])
   [119]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4576-cc2c646d39200973cc76d0fa0851d73c9636c27c/shard-bmg-9/igt@xe_pm_residency@aspm_link_residency.html
   [120]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161848v1/shard-bmg-5/igt@xe_pm_residency@aspm_link_residency.html

  * igt@xe_pxp@regular-src-to-pxp-dest-rendercopy:
    - shard-bmg:          NOTRUN -> [SKIP][121] ([Intel XE#4733])
   [121]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161848v1/shard-bmg-2/igt@xe_pxp@regular-src-to-pxp-dest-rendercopy.html

  * igt@xe_query@multigpu-query-invalid-extension:
    - shard-bmg:          NOTRUN -> [SKIP][122] ([Intel XE#944]) +2 other tests skip
   [122]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161848v1/shard-bmg-7/igt@xe_query@multigpu-query-invalid-extension.html

  * igt@xe_sriov_vram@vf-access-after-resize-down:
    - shard-lnl:          NOTRUN -> [SKIP][123] ([Intel XE#6376])
   [123]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161848v1/shard-lnl-2/igt@xe_sriov_vram@vf-access-after-resize-down.html

  
#### Possible fixes ####

  * igt@kms_async_flips@async-flip-with-page-flip-events-linear:
    - shard-lnl:          [FAIL][124] ([Intel XE#5993]) -> [PASS][125] +3 other tests pass
   [124]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4576-cc2c646d39200973cc76d0fa0851d73c9636c27c/shard-lnl-5/igt@kms_async_flips@async-flip-with-page-flip-events-linear.html
   [125]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161848v1/shard-lnl-8/igt@kms_async_flips@async-flip-with-page-flip-events-linear.html

  * igt@kms_cursor_legacy@flip-vs-cursor-atomic:
    - shard-bmg:          [FAIL][126] ([Intel XE#4633]) -> [PASS][127]
   [126]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4576-cc2c646d39200973cc76d0fa0851d73c9636c27c/shard-bmg-4/igt@kms_cursor_legacy@flip-vs-cursor-atomic.html
   [127]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161848v1/shard-bmg-5/igt@kms_cursor_legacy@flip-vs-cursor-atomic.html

  * igt@kms_flip@flip-vs-expired-vblank@a-edp1:
    - shard-lnl:          [FAIL][128] ([Intel XE#301]) -> [PASS][129]
   [128]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4576-cc2c646d39200973cc76d0fa0851d73c9636c27c/shard-lnl-5/igt@kms_flip@flip-vs-expired-vblank@a-edp1.html
   [129]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161848v1/shard-lnl-4/igt@kms_flip@flip-vs-expired-vblank@a-edp1.html

  * igt@kms_psr_stress_test@flip-primary-invalidate-overlay:
    - shard-lnl:          [SKIP][130] ([Intel XE#1406] / [Intel XE#4692]) -> [PASS][131]
   [130]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4576-cc2c646d39200973cc76d0fa0851d73c9636c27c/shard-lnl-2/igt@kms_psr_stress_test@flip-primary-invalidate-overlay.html
   [131]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161848v1/shard-lnl-3/igt@kms_psr_stress_test@flip-primary-invalidate-overlay.html

  * igt@kms_setmode@basic@pipe-a-edp-1:
    - shard-lnl:          [FAIL][132] ([Intel XE#6361]) -> [PASS][133] +1 other test pass
   [132]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4576-cc2c646d39200973cc76d0fa0851d73c9636c27c/shard-lnl-5/igt@kms_setmode@basic@pipe-a-edp-1.html
   [133]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161848v1/shard-lnl-2/igt@kms_setmode@basic@pipe-a-edp-1.html

  * igt@kms_vrr@flip-basic:
    - shard-lnl:          [FAIL][134] ([Intel XE#4227]) -> [PASS][135] +1 other test pass
   [134]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4576-cc2c646d39200973cc76d0fa0851d73c9636c27c/shard-lnl-2/igt@kms_vrr@flip-basic.html
   [135]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161848v1/shard-lnl-4/igt@kms_vrr@flip-basic.html

  * igt@xe_evict@evict-mixed-many-threads-small:
    - shard-bmg:          [INCOMPLETE][136] ([Intel XE#6321]) -> [PASS][137]
   [136]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4576-cc2c646d39200973cc76d0fa0851d73c9636c27c/shard-bmg-7/igt@xe_evict@evict-mixed-many-threads-small.html
   [137]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161848v1/shard-bmg-1/igt@xe_evict@evict-mixed-many-threads-small.html

  * igt@xe_exec_system_allocator@pat-index-madvise-pat-idx-uc-single-vma:
    - shard-lnl:          [FAIL][138] ([Intel XE#5625]) -> [PASS][139]
   [138]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4576-cc2c646d39200973cc76d0fa0851d73c9636c27c/shard-lnl-5/igt@xe_exec_system_allocator@pat-index-madvise-pat-idx-uc-single-vma.html
   [139]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161848v1/shard-lnl-3/igt@xe_exec_system_allocator@pat-index-madvise-pat-idx-uc-single-vma.html

  * igt@xe_fault_injection@inject-fault-probe-function-xe_device_create:
    - shard-bmg:          [ABORT][140] -> [PASS][141]
   [140]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4576-cc2c646d39200973cc76d0fa0851d73c9636c27c/shard-bmg-8/igt@xe_fault_injection@inject-fault-probe-function-xe_device_create.html
   [141]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161848v1/shard-bmg-8/igt@xe_fault_injection@inject-fault-probe-function-xe_device_create.html

  * igt@xe_sriov_flr@flr-each-isolation:
    - shard-bmg:          [FAIL][142] ([Intel XE#6569]) -> [PASS][143]
   [142]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4576-cc2c646d39200973cc76d0fa0851d73c9636c27c/shard-bmg-6/igt@xe_sriov_flr@flr-each-isolation.html
   [143]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161848v1/shard-bmg-6/igt@xe_sriov_flr@flr-each-isolation.html

  
#### Warnings ####

  * igt@kms_ccs@crc-primary-suspend-4-tiled-lnl-ccs@pipe-d-hdmi-a-3:
    - shard-bmg:          [SKIP][144] ([Intel XE#2652] / [Intel XE#787]) -> [SKIP][145] ([Intel XE#2652]) +49 other tests skip
   [144]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4576-cc2c646d39200973cc76d0fa0851d73c9636c27c/shard-bmg-3/igt@kms_ccs@crc-primary-suspend-4-tiled-lnl-ccs@pipe-d-hdmi-a-3.html
   [145]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161848v1/shard-bmg-1/igt@kms_ccs@crc-primary-suspend-4-tiled-lnl-ccs@pipe-d-hdmi-a-3.html

  * igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-pri-indfb-draw-render:
    - shard-bmg:          [INCOMPLETE][146] ([Intel XE#1727]) -> [SKIP][147] ([Intel XE#4141])
   [146]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4576-cc2c646d39200973cc76d0fa0851d73c9636c27c/shard-bmg-2/igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-pri-indfb-draw-render.html
   [147]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161848v1/shard-bmg-7/igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-pri-indfb-draw-render.html

  * igt@kms_hdr@brightness-with-hdr:
    - shard-bmg:          [SKIP][148] ([Intel XE#3544]) -> [SKIP][149] ([Intel XE#3374] / [Intel XE#3544])
   [148]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4576-cc2c646d39200973cc76d0fa0851d73c9636c27c/shard-bmg-9/igt@kms_hdr@brightness-with-hdr.html
   [149]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161848v1/shard-bmg-5/igt@kms_hdr@brightness-with-hdr.html

  * igt@kms_plane_scaling@plane-downscale-factor-0-5-with-pixel-format@pipe-c:
    - shard-lnl:          [SKIP][150] ([Intel XE#6886]) -> [SKIP][151] ([Intel XE#2763] / [Intel XE#6886]) +45 other tests skip
   [150]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4576-cc2c646d39200973cc76d0fa0851d73c9636c27c/shard-lnl-1/igt@kms_plane_scaling@plane-downscale-factor-0-5-with-pixel-format@pipe-c.html
   [151]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161848v1/shard-lnl-3/igt@kms_plane_scaling@plane-downscale-factor-0-5-with-pixel-format@pipe-c.html

  * igt@kms_plane_scaling@planes-upscale-20x20-downscale-factor-0-5@pipe-b:
    - shard-bmg:          [SKIP][152] ([Intel XE#6886]) -> [SKIP][153] ([Intel XE#2763] / [Intel XE#6886]) +14 other tests skip
   [152]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4576-cc2c646d39200973cc76d0fa0851d73c9636c27c/shard-bmg-4/igt@kms_plane_scaling@planes-upscale-20x20-downscale-factor-0-5@pipe-b.html
   [153]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161848v1/shard-bmg-1/igt@kms_plane_scaling@planes-upscale-20x20-downscale-factor-0-5@pipe-b.html

  
  [Intel XE#1061]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1061
  [Intel XE#1124]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1124
  [Intel XE#1128]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1128
  [Intel XE#1392]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1392
  [Intel XE#1406]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1406
  [Intel XE#1407]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1407
  [Intel XE#1421]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1421
  [Intel XE#1424]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1424
  [Intel XE#1435]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1435
  [Intel XE#1439]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1439
  [Intel XE#1447]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1447
  [Intel XE#1467]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1467
  [Intel XE#1489]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1489
  [Intel XE#1499]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1499
  [Intel XE#1508]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1508
  [Intel XE#1727]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1727
  [Intel XE#2049]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2049
  [Intel XE#2142]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2142
  [Intel XE#2191]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2191
  [Intel XE#2234]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2234
  [Intel XE#2244]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2244
  [Intel XE#2252]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2252
  [Intel XE#2311]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2311
  [Intel XE#2313]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2313
  [Intel XE#2314]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2314
  [Intel XE#2320]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2320
  [Intel XE#2321]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2321
  [Intel XE#2322]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2322
  [Intel XE#2325]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2325
  [Intel XE#2327]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2327
  [Intel XE#2330]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2330
  [Intel XE#2341]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2341
  [Intel XE#2352]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2352
  [Intel XE#2373]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2373
  [Intel XE#2387]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2387
  [Intel XE#2391]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2391
  [Intel XE#2413]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2413
  [Intel XE#2426]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2426
  [Intel XE#2427]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2427
  [Intel XE#2459]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2459
  [Intel XE#2596]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2596
  [Intel XE#2597]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2597
  [Intel XE#2652]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2652
  [Intel XE#2763]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2763
  [Intel XE#2850]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2850
  [Intel XE#2887]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2887
  [Intel XE#2893]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2893
  [Intel XE#2894]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2894
  [Intel XE#301]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/301
  [Intel XE#306]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/306
  [Intel XE#309]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/309
  [Intel XE#3141]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3141
  [Intel XE#3304]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3304
  [Intel XE#3374]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3374
  [Intel XE#3414]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3414
  [Intel XE#3432]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3432
  [Intel XE#3544]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3544
  [Intel XE#367]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/367
  [Intel XE#373]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/373
  [Intel XE#3904]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3904
  [Intel XE#4141]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4141
  [Intel XE#4227]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4227
  [Intel XE#4329]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4329
  [Intel XE#4331]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4331
  [Intel XE#4596]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4596
  [Intel XE#4609]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4609
  [Intel XE#4633]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4633
  [Intel XE#4692]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4692
  [Intel XE#4733]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4733
  [Intel XE#4837]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4837
  [Intel XE#5020]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5020
  [Intel XE#5100]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5100
  [Intel XE#5191]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5191
  [Intel XE#5299]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5299
  [Intel XE#5625]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5625
  [Intel XE#5742]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5742
  [Intel XE#579]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/579
  [Intel XE#584]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/584
  [Intel XE#586]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/586
  [Intel XE#599]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/599
  [Intel XE#5993]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5993
  [Intel XE#6321]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6321
  [Intel XE#6361]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6361
  [Intel XE#6376]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6376
  [Intel XE#6503]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6503
  [Intel XE#6507]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6507
  [Intel XE#651]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/651
  [Intel XE#6540]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6540
  [Intel XE#656]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/656
  [Intel XE#6569]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6569
  [Intel XE#6599]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6599
  [Intel XE#6665]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6665
  [Intel XE#6707]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6707
  [Intel XE#6841]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6841
  [Intel XE#6874]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6874
  [Intel XE#688]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/688
  [Intel XE#6886]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6886
  [Intel XE#6901]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6901
  [Intel XE#6912]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6912
  [Intel XE#6953]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6953
  [Intel XE#6964]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6964
  [Intel XE#6968]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6968
  [Intel XE#6973]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6973
  [Intel XE#6974]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6974
  [Intel XE#7061]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7061
  [Intel XE#7084]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7084
  [Intel XE#7130]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7130
  [Intel XE#7136]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7136
  [Intel XE#7138]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7138
  [Intel XE#7166]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7166
  [Intel XE#7178]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7178
  [Intel XE#7179]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7179
  [Intel XE#7258]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7258
  [Intel XE#7283]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7283
  [Intel XE#787]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/787
  [Intel XE#836]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/836
  [Intel XE#944]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/944


Build changes
-------------

  * IGT: IGT_8762 -> IGT_8763
  * Linux: xe-4576-cc2c646d39200973cc76d0fa0851d73c9636c27c -> xe-pw-161848v1

  IGT_8762: d3c67e0f1fa76ac3d71095825bbc9df0d307e4fc @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
  IGT_8763: 8763
  xe-4576-cc2c646d39200973cc76d0fa0851d73c9636c27c: cc2c646d39200973cc76d0fa0851d73c9636c27c
  xe-pw-161848v1: 161848v1

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161848v1/index.html

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