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From: Matt Roper <matthew.d.roper@intel.com>
To: intel-xe@lists.freedesktop.org
Cc: Matt Roper <matthew.d.roper@intel.com>,
	 Shuicheng Lin <shuicheng.lin@intel.com>
Subject: [PATCH v2 04/10] drm/xe: Move HWSTAM programming to RTP
Date: Fri, 24 Apr 2026 13:48:14 -0700	[thread overview]
Message-ID: <20260424-engine-setup-v2-4-59cc620a25f1@intel.com> (raw)
In-Reply-To: <20260424-engine-setup-v2-0-59cc620a25f1@intel.com>

The write to RING_HWSTAM to disable hardware status page writes on
interrupt was unnecessarily open-coded in xe_hw_engine_enable_ring();
it's preferable to do such programming in the engine_entries[] RTP table
since gets reflected/verified in debugfs, and will also automatically
ensure that the register is properly saved/restored around engine
resets.

In this case the HWSTAM register wasn't explicitly added to the GuC ADS'
save-restore list, so there was the potential for the value to be lost
on engine resets.  This doesn't seem to have happened in practice, so
likely the GuC firmware is automatically saving/restoring this register
on our behalf, but we shouldn't rely on this implicit behavior going
forward.

One other slight change with this patch is that HWSTAM will now be
programmed on the vestigial execlist (non-GuC) initialization path.
Since the register's default value is 0x0 and the documentation
indicates that it's only legal to leave a single bit unmasked at a time,
this likely would have been an illegal situation if the execlist code
were actually usable.

Reviewed-by: Shuicheng Lin <shuicheng.lin@intel.com>
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
---
 drivers/gpu/drm/xe/xe_hw_engine.c | 6 +++++-
 1 file changed, 5 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/xe/xe_hw_engine.c b/drivers/gpu/drm/xe/xe_hw_engine.c
index 0419cd045090..ec47e17b4119 100644
--- a/drivers/gpu/drm/xe/xe_hw_engine.c
+++ b/drivers/gpu/drm/xe/xe_hw_engine.c
@@ -327,7 +327,6 @@ void xe_hw_engine_enable_ring(struct xe_hw_engine *hwe)
 {
 	u32 ring_mode = REG_MASKED_FIELD_ENABLE(GFX_DISABLE_LEGACY_MODE);
 
-	xe_hw_engine_mmio_write32(hwe, RING_HWSTAM(0), ~0x0);
 	xe_hw_engine_mmio_write32(hwe, RING_HWS_PGA(0),
 				  xe_bo_ggtt_addr(hwe->hwsp));
 
@@ -437,6 +436,11 @@ hw_engine_setup_default_state(struct xe_hw_engine *hwe)
 					   ring_cmd_cctl_val,
 					   XE_RTP_ACTION_FLAG(ENGINE_BASE)))
 		},
+		{ XE_RTP_NAME("Disable HW status page updates for interrupts"),
+		  XE_RTP_RULES(FUNC(xe_rtp_match_always)),
+		  XE_RTP_ACTIONS(SET(RING_HWSTAM(0), ~0x0,
+				     XE_RTP_ACTION_FLAG(ENGINE_BASE)))
+		},
 		/*
 		 * To allow the GSC engine to go idle on MTL we need to enable
 		 * idle messaging and set the hysteresis value (we use 0xA=5us

-- 
2.53.0


  parent reply	other threads:[~2026-04-24 20:50 UTC|newest]

Thread overview: 14+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2026-04-24 20:48 [PATCH v2 00/10] Engine initialization cleanup Matt Roper
2026-04-24 20:48 ` [PATCH v2 01/10] drm/xe: Move CCS enablement to engine setup RTP Matt Roper
2026-04-24 20:48 ` [PATCH v2 02/10] drm/xe/rtp: Add "always true" match function Matt Roper
2026-04-24 20:48 ` [PATCH v2 03/10] drm/xe: Stop programming BLIT_CCTL on Xe2 and later platforms Matt Roper
2026-04-24 20:48 ` Matt Roper [this message]
2026-04-24 20:48 ` [PATCH v2 05/10] drm/xe: Fix name and definition of GFX_MODE register Matt Roper
2026-04-24 20:48 ` [PATCH v2 06/10] drm/xe: Const-ify parameters to xe_device_has_* functions Matt Roper
2026-04-24 20:48 ` [PATCH v2 07/10] drm/xe: Move GFX_MODE programming to RTP Matt Roper
2026-04-24 20:48 ` [PATCH v2 08/10] drm/xe: Drop unnecessary STOP_RING clearing Matt Roper
2026-04-24 20:48 ` [PATCH v2 09/10] drm/xe: Drop xe_hw_engine_mmio_write32() Matt Roper
2026-04-24 20:48 ` [PATCH v2 10/10] drm/xe: Mark BCS engines as belonging to the GT forcewake domain Matt Roper
2026-04-24 21:27 ` ✓ CI.KUnit: success for Engine initialization cleanup (rev2) Patchwork
2026-04-24 22:30 ` ✓ Xe.CI.BAT: " Patchwork
2026-04-24 23:15 ` ✗ Xe.CI.FULL: failure " Patchwork

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