From: Gustavo Sousa <gustavo.sousa@intel.com>
To: intel-xe@lists.freedesktop.org
Cc: Gustavo Sousa <gustavo.sousa@intel.com>,
Matt Roper <matthew.d.roper@intel.com>
Subject: [PATCH v2 1/8] drm/xe: Define CACHE_MODE_1 as MCR register
Date: Fri, 08 May 2026 18:42:31 -0300 [thread overview]
Message-ID: <20260508-rtp-mcr-check-v2-1-9897b147a5d2@intel.com> (raw)
In-Reply-To: <20260508-rtp-mcr-check-v2-0-9897b147a5d2@intel.com>
CACHE_MODE_1 is a MCR register for all platforms that currently use it
in the Xe driver. Use XE_REG_MCR() when defining it.
Fixes: 8cd7e9759766 ("drm/xe: Add missing DG2 lrc workarounds")
Fixes: ff063430caa8 ("drm/xe/mtl: Add some initial MTL workarounds")
Bspec: 66534, 67788
Reviewed-by: Matt Roper <matthew.d.roper@intel.com>
Signed-off-by: Gustavo Sousa <gustavo.sousa@intel.com>
---
drivers/gpu/drm/xe/regs/xe_gt_regs.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/xe/regs/xe_gt_regs.h b/drivers/gpu/drm/xe/regs/xe_gt_regs.h
index 16c87ce3f614..408933aee08a 100644
--- a/drivers/gpu/drm/xe/regs/xe_gt_regs.h
+++ b/drivers/gpu/drm/xe/regs/xe_gt_regs.h
@@ -152,7 +152,7 @@
#define XEHPG_INSTDONE_GEOM_SVGUNIT XE_REG_MCR(0x666c)
-#define CACHE_MODE_1 XE_REG(0x7004, XE_REG_OPTION_MASKED)
+#define CACHE_MODE_1 XE_REG_MCR(0x7004, XE_REG_OPTION_MASKED)
#define MSAA_OPTIMIZATION_REDUC_DISABLE REG_BIT(11)
#define COMMON_SLICE_CHICKEN1 XE_REG(0x7010, XE_REG_OPTION_MASKED)
--
2.53.0
next prev parent reply other threads:[~2026-05-08 21:42 UTC|newest]
Thread overview: 24+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-05-08 21:42 [PATCH v2 0/8] Fix MCR inconsistencies in RTP tables Gustavo Sousa
2026-05-08 21:42 ` Gustavo Sousa [this message]
2026-05-08 21:42 ` [PATCH v2 2/8] drm/xe: Define and use MCR version of COMMON_SLICE_CHICKEN1 Gustavo Sousa
2026-05-08 21:42 ` [PATCH v2 3/8] drm/xe: Define and use MCR version of COMMON_SLICE_CHICKEN4 Gustavo Sousa
2026-05-13 22:35 ` Matt Roper
2026-05-08 21:42 ` [PATCH v2 4/8] drm/xe/kunit: Add xe_kunit_helper_is_live_test() Gustavo Sousa
2026-05-11 10:37 ` Jani Nikula
2026-05-11 11:45 ` Gustavo Sousa
2026-05-11 12:03 ` Jani Nikula
2026-05-11 12:30 ` Gustavo Sousa
2026-05-11 20:33 ` Rodrigo Vivi
2026-05-11 21:01 ` Gustavo Sousa
2026-05-12 19:00 ` Rodrigo Vivi
2026-05-12 19:26 ` Michal Wajdeczko
2026-05-13 13:03 ` Gustavo Sousa
2026-05-13 12:58 ` Gustavo Sousa
2026-05-08 21:42 ` [PATCH v2 5/8] drm/xe: Extract xe_hw_engine_setup_reg_lrc() Gustavo Sousa
2026-05-08 21:42 ` [PATCH v2 6/8] drm/xe/kunit: Use KUNIT_EXPECT_EQ() in xe_wa_gt() Gustavo Sousa
2026-05-08 21:42 ` [PATCH v2 7/8] drm/xe/mcr: Extract reg_in_steering_type_ranges() Gustavo Sousa
2026-05-08 21:42 ` [PATCH v2 8/8] drm/xe/reg_sr: Do sanity check for MCR vs non-MCR Gustavo Sousa
2026-05-13 22:49 ` Matt Roper
2026-05-08 21:50 ` ✓ CI.KUnit: success for Fix MCR inconsistencies in RTP tables (rev2) Patchwork
2026-05-08 23:04 ` ✓ Xe.CI.BAT: " Patchwork
2026-05-09 10:54 ` ✗ Xe.CI.FULL: failure " Patchwork
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20260508-rtp-mcr-check-v2-1-9897b147a5d2@intel.com \
--to=gustavo.sousa@intel.com \
--cc=intel-xe@lists.freedesktop.org \
--cc=matthew.d.roper@intel.com \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox