From: Matthew Auld <matthew.auld@intel.com>
To: intel-xe@lists.freedesktop.org
Cc: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
Subject: [PATCH v2 09/10] drm/xe/hw_engine: document top-down paging requirement
Date: Fri, 22 May 2026 13:37:30 +0100 [thread overview]
Message-ID: <20260522123720.39656-21-matthew.auld@intel.com> (raw)
In-Reply-To: <20260522123720.39656-12-matthew.auld@intel.com>
We were doing this anyway, but going forward for paging engines,
agreement is to always reserve BCS instances in top down fashion. This
hopefully future proofs things for VFs, where in some low-level places
it might only have the physical BCS instance from hw pov. If we stick to
a consistent mapping scheme, it should make it possible to determine if
this a special paging engine, or not.
Signed-off-by: Matthew Auld <matthew.auld@intel.com>
Cc: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
---
drivers/gpu/drm/xe/xe_hw_engine.c | 11 ++++++++++-
1 file changed, 10 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/xe/xe_hw_engine.c b/drivers/gpu/drm/xe/xe_hw_engine.c
index c279a7dc62e2..5583fd98b08d 100644
--- a/drivers/gpu/drm/xe/xe_hw_engine.c
+++ b/drivers/gpu/drm/xe/xe_hw_engine.c
@@ -665,7 +665,6 @@ static void hw_engine_setup_logical_and_paging_mapping(struct xe_gt *gt)
if (hwe->class == XE_ENGINE_CLASS_COPY)
num_copy_engines++;
- /* We just reserve the highest BCS instance for USM */
if (num_copy_engines && xe->info.has_usm)
num_paging_engines = 1;
@@ -690,6 +689,16 @@ static void hw_engine_setup_logical_and_paging_mapping(struct xe_gt *gt)
xe_gt_assert(gt, !(num_copy_engines || num_paging_engines) ||
(num_paging_engines < num_copy_engines));
+ /*
+ * On PF, we just reserve the highest BCS instance for USM.
+ *
+ * Note: This is now a requirement going forward. The PF must ALWAYS
+ * reserve BCS instances in top down order, that way the VF has a chance
+ * of discovering the physical BCS instance mappings for paging engines,
+ * in conjunction with vf_num_paging_engines. In some places we might
+ * only have the physical instance, and from hw pov there is no such
+ * thing as a paging engine.
+ */
reserved_logical_bcs_start = num_copy_engines - num_paging_engines;
/* FIXME: Doing a simple logical mapping that works for most hardware */
--
2.54.0
next prev parent reply other threads:[~2026-05-22 12:37 UTC|newest]
Thread overview: 18+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-05-22 12:37 [PATCH v2 00/10] GuC paging engine support Matthew Auld
2026-05-22 12:37 ` [PATCH v2 01/10] drm/xe/guc: refactor ads to use guc_class Matthew Auld
2026-05-23 1:03 ` Daniele Ceraolo Spurio
2026-05-26 9:21 ` Matthew Auld
2026-05-22 12:37 ` [PATCH v2 02/10] drm/xe/guc: refactor to_guc_class() to accept hwe Matthew Auld
2026-05-23 1:07 ` Daniele Ceraolo Spurio
2026-05-22 12:37 ` [PATCH v2 03/10] drm/xe/guc: add the plumbing for GUC_PAGING_CLASS Matthew Auld
2026-05-22 12:37 ` [PATCH v2 04/10] drm/xe/hw_engine: don't open code is_usm_hwe() Matthew Auld
2026-05-23 2:01 ` Daniele Ceraolo Spurio
2026-05-22 12:37 ` [PATCH v2 05/10] drm/xe: refactor the paging engine setup Matthew Auld
2026-05-22 12:37 ` [PATCH v2 06/10] drm/xe/guc: handle guc logical instance for paging engine Matthew Auld
2026-05-22 12:37 ` [PATCH v2 07/10] drm/xe/guc: handle submit mask with " Matthew Auld
2026-05-22 12:37 ` [PATCH v2 08/10] drm/xe/vf: wire up NUM_PAGING_ENGINE_INSTANCES Matthew Auld
2026-05-22 12:37 ` Matthew Auld [this message]
2026-05-22 12:37 ` [PATCH v2 10/10] drm/xe/guc: toggle paging engine support for NVL-S+ Matthew Auld
2026-05-22 13:57 ` ✓ CI.KUnit: success for GuC paging engine support (rev2) Patchwork
2026-05-22 14:35 ` ✓ Xe.CI.BAT: " Patchwork
2026-05-22 20:10 ` ✗ Xe.CI.FULL: failure " Patchwork
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