From: Stuart Summers <stuart.summers@intel.com>
Cc: michal.wajdeczko@intel.com, ilia.levi@intel.com,
x.wang@intel.com, rodrigo.vivi@intel.com,
intel-xe@lists.freedesktop.org,
alan.previn.teres.alexis@intel.com,
Stuart Summers <stuart.summers@intel.com>
Subject: [PATCH 03/12] drm/xe: Cap MSI-X vector count to XE_MSIX_MAX_VECS
Date: Fri, 5 Jun 2026 23:21:10 +0000 [thread overview]
Message-ID: <20260605232108.674580-17-stuart.summers@intel.com> (raw)
In-Reply-To: <20260605232108.674580-14-stuart.summers@intel.com>
Introduce XE_MSIX_MAX_VECS (1024) as a software cap on the total number
of MSI-X vectors the driver will use. We want a way to cap the number
of vectors separately from the PCIe capability. This way we can more
easily manage certain system-wide configurations that might differ
from the per-device level configuration.
Signed-off-by: Stuart Summers <stuart.summers@intel.com>
Assisted-by: Copilot:claude-sonnet-4.6
---
drivers/gpu/drm/xe/xe_irq.c | 2 +-
drivers/gpu/drm/xe/xe_irq.h | 7 +++++++
2 files changed, 8 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/xe/xe_irq.c b/drivers/gpu/drm/xe/xe_irq.c
index 9e49e2241da4..3429bb305293 100644
--- a/drivers/gpu/drm/xe/xe_irq.c
+++ b/drivers/gpu/drm/xe/xe_irq.c
@@ -895,7 +895,7 @@ static int xe_irq_msix_init(struct xe_device *xe)
return nvec;
}
- xe->irq.msix.nvec = nvec;
+ xe->irq.msix.nvec = min_t(int, nvec, XE_MSIX_MAX_VECS);
xa_init_flags(&xe->irq.msix.indexes, XA_FLAGS_ALLOC);
return 0;
}
diff --git a/drivers/gpu/drm/xe/xe_irq.h b/drivers/gpu/drm/xe/xe_irq.h
index a28bd577ba52..5f48249dae8a 100644
--- a/drivers/gpu/drm/xe/xe_irq.h
+++ b/drivers/gpu/drm/xe/xe_irq.h
@@ -10,6 +10,13 @@
#define XE_IRQ_DEFAULT_MSIX 1
+/*
+ * Software cap on the total number of MSI-X vectors the driver will use.
+ * Allows the supported vectors to be managed independent of the PCI
+ * config space report.
+ */
+#define XE_MSIX_MAX_VECS 1024
+
struct xe_device;
struct xe_tile;
struct xe_gt;
--
2.43.0
next prev parent reply other threads:[~2026-06-05 23:21 UTC|newest]
Thread overview: 24+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-06-05 23:21 [PATCH 00/12] Enable per exec queue MSI-X vector assignment Stuart Summers
2026-06-05 23:21 ` [PATCH 01/12] drm/xe: Add kerneldoc to xe_wait_user_fence_ioctl() Stuart Summers
2026-06-05 23:21 ` [PATCH 02/12] drm/xe: Handle NULL in xe_exec_queue_get_unless_zero() Stuart Summers
2026-06-05 23:21 ` Stuart Summers [this message]
2026-06-05 23:21 ` [PATCH 04/12] drm/xe: Assign dedicated MSI-X vectors to exec queues Stuart Summers
2026-06-05 23:21 ` [PATCH 05/12] drm/xe: Add configfs max_msix_vecs attribute Stuart Summers
2026-06-05 23:21 ` [PATCH 06/12] drm/xe: Change MSI-X assignment failure to drm_dbg Stuart Summers
2026-06-06 10:57 ` Michal Wajdeczko
2026-06-08 20:30 ` Summers, Stuart
2026-06-09 19:54 ` Summers, Stuart
2026-06-05 23:21 ` [PATCH 07/12] drm/xe: Remove memirq status and source checks for engine interrupts Stuart Summers
2026-06-06 11:18 ` Michal Wajdeczko
2026-06-09 19:38 ` Summers, Stuart
2026-06-09 21:29 ` Michal Wajdeczko
2026-06-09 22:12 ` Summers, Stuart
2026-06-05 23:21 ` [PATCH 08/12] drm/xe: Add per-exec-queue user fence wait queue Stuart Summers
2026-06-05 23:21 ` [PATCH 09/12] drm/xe: Track all exec queues in a device-level ufence list Stuart Summers
2026-06-05 23:21 ` [PATCH 10/12] drm/xe: Hook up per queue thread wake to the unique MSI-X vector allocation Stuart Summers
2026-06-05 23:21 ` [PATCH 11/12] drm/xe: Enable per-queue ufence wake in ioctl and wake function Stuart Summers
2026-06-05 23:21 ` [PATCH 12/12] drm/xe/memirq: Enable compute walker post-sync interrupt Stuart Summers
2026-06-05 23:47 ` ✗ CI.checkpatch: warning for Enable per exec queue MSI-X vector assignment Patchwork
2026-06-05 23:49 ` ✓ CI.KUnit: success " Patchwork
2026-06-06 0:43 ` ✓ Xe.CI.BAT: " Patchwork
2026-06-06 13:27 ` ✓ Xe.CI.FULL: " Patchwork
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20260605232108.674580-17-stuart.summers@intel.com \
--to=stuart.summers@intel.com \
--cc=alan.previn.teres.alexis@intel.com \
--cc=ilia.levi@intel.com \
--cc=intel-xe@lists.freedesktop.org \
--cc=michal.wajdeczko@intel.com \
--cc=rodrigo.vivi@intel.com \
--cc=x.wang@intel.com \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox