From: Stuart Summers <stuart.summers@intel.com>
Cc: michal.wajdeczko@intel.com, ilia.levi@intel.com,
x.wang@intel.com, rodrigo.vivi@intel.com,
intel-xe@lists.freedesktop.org,
alan.previn.teres.alexis@intel.com,
Stuart Summers <stuart.summers@intel.com>
Subject: [PATCH 10/12] drm/xe: Hook up per queue thread wake to the unique MSI-X vector allocation
Date: Fri, 5 Jun 2026 23:21:17 +0000 [thread overview]
Message-ID: <20260605232108.674580-24-stuart.summers@intel.com> (raw)
In-Reply-To: <20260605232108.674580-14-stuart.summers@intel.com>
When a dedicated MSI-X vector fires for a specific exec queue, the
interrupt handler already has the queue pointer available. Thread it
through the call chain so we can wake the per-queue ufence_wq without
impact any other user threads.
Signed-off-by: Stuart Summers <stuart.summers@intel.com>
Assisted-by: Copilot:claude-sonnet-4.6
---
drivers/gpu/drm/xe/xe_irq.c | 4 ++--
drivers/gpu/drm/xe/xe_memirq.c | 16 +++++++++++-----
drivers/gpu/drm/xe/xe_memirq.h | 4 +++-
3 files changed, 16 insertions(+), 8 deletions(-)
diff --git a/drivers/gpu/drm/xe/xe_irq.c b/drivers/gpu/drm/xe/xe_irq.c
index 935a90719e75..db12e1a371a5 100644
--- a/drivers/gpu/drm/xe/xe_irq.c
+++ b/drivers/gpu/drm/xe/xe_irq.c
@@ -927,7 +927,7 @@ static irqreturn_t xe_irq_msix_default_hwe_handler(int irq, void *arg)
continue;
for_each_hw_engine(hwe, gt, id)
- xe_memirq_hwe_handler(memirq, hwe);
+ xe_memirq_hwe_handler(memirq, hwe, NULL);
}
}
@@ -942,7 +942,7 @@ irqreturn_t xe_irq_msix_hwe_handler(int irq, void *arg)
if (!atomic_read(&tile->xe->irq.enabled))
return IRQ_NONE;
- xe_memirq_hwe_handler(&tile->memirq, q->hwe);
+ xe_memirq_hwe_handler(&tile->memirq, q->hwe, q);
return IRQ_HANDLED;
}
diff --git a/drivers/gpu/drm/xe/xe_memirq.c b/drivers/gpu/drm/xe/xe_memirq.c
index 427a0e13f7aa..f94b75eac80f 100644
--- a/drivers/gpu/drm/xe/xe_memirq.c
+++ b/drivers/gpu/drm/xe/xe_memirq.c
@@ -448,7 +448,8 @@ static void memirq_assume_received(struct xe_memirq *memirq, const char *source,
}
static void memirq_dispatch_engine(struct xe_memirq *memirq,
- struct xe_hw_engine *hwe)
+ struct xe_hw_engine *hwe,
+ struct xe_exec_queue *q)
{
memirq_debug(memirq, "dispatching engine %s\n", hwe->name);
@@ -494,12 +495,17 @@ static void memirq_dispatch_guc(struct xe_memirq *memirq, struct iosys_map *stat
* xe_memirq_hwe_handler - Check and process interrupts for a specific HW engine.
* @memirq: the &xe_memirq
* @hwe: the hw engine to process
+ * @q: the exec queue associated with this interrupt, or NULL
*
- * This function reads and dispatches `Memory Based Interrupts` for the provided HW engine.
+ * This function reads and dispatches `Memory Based Interrupts` for the provided
+ * HW engine. When @q is non-NULL (e.g. called from a dedicated MSI-X vector
+ * handler), it is passed through so the per-queue user fence wait queue is
+ * woken rather than the device-level one.
*/
-void xe_memirq_hwe_handler(struct xe_memirq *memirq, struct xe_hw_engine *hwe)
+void xe_memirq_hwe_handler(struct xe_memirq *memirq, struct xe_hw_engine *hwe,
+ struct xe_exec_queue *q)
{
- memirq_dispatch_engine(memirq, hwe);
+ memirq_dispatch_engine(memirq, hwe, q);
}
/**
@@ -559,7 +565,7 @@ void xe_memirq_handler(struct xe_memirq *memirq)
continue;
for_each_hw_engine(hwe, gt, id)
- xe_memirq_hwe_handler(memirq, hwe);
+ xe_memirq_hwe_handler(memirq, hwe, NULL);
}
/* GuC and media GuC (if present) must be checked separately */
diff --git a/drivers/gpu/drm/xe/xe_memirq.h b/drivers/gpu/drm/xe/xe_memirq.h
index e25d2234ab87..7e2229ad1d38 100644
--- a/drivers/gpu/drm/xe/xe_memirq.h
+++ b/drivers/gpu/drm/xe/xe_memirq.h
@@ -8,6 +8,7 @@
#include <linux/types.h>
+struct xe_exec_queue;
struct xe_guc;
struct xe_hw_engine;
struct xe_memirq;
@@ -20,7 +21,8 @@ u32 xe_memirq_enable_ptr(struct xe_memirq *memirq);
void xe_memirq_reset(struct xe_memirq *memirq);
void xe_memirq_postinstall(struct xe_memirq *memirq);
-void xe_memirq_hwe_handler(struct xe_memirq *memirq, struct xe_hw_engine *hwe);
+void xe_memirq_hwe_handler(struct xe_memirq *memirq, struct xe_hw_engine *hwe,
+ struct xe_exec_queue *q);
void xe_memirq_handler(struct xe_memirq *memirq);
int xe_memirq_init_guc(struct xe_memirq *memirq, struct xe_guc *guc);
--
2.43.0
next prev parent reply other threads:[~2026-06-05 23:21 UTC|newest]
Thread overview: 24+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-06-05 23:21 [PATCH 00/12] Enable per exec queue MSI-X vector assignment Stuart Summers
2026-06-05 23:21 ` [PATCH 01/12] drm/xe: Add kerneldoc to xe_wait_user_fence_ioctl() Stuart Summers
2026-06-05 23:21 ` [PATCH 02/12] drm/xe: Handle NULL in xe_exec_queue_get_unless_zero() Stuart Summers
2026-06-05 23:21 ` [PATCH 03/12] drm/xe: Cap MSI-X vector count to XE_MSIX_MAX_VECS Stuart Summers
2026-06-05 23:21 ` [PATCH 04/12] drm/xe: Assign dedicated MSI-X vectors to exec queues Stuart Summers
2026-06-05 23:21 ` [PATCH 05/12] drm/xe: Add configfs max_msix_vecs attribute Stuart Summers
2026-06-05 23:21 ` [PATCH 06/12] drm/xe: Change MSI-X assignment failure to drm_dbg Stuart Summers
2026-06-06 10:57 ` Michal Wajdeczko
2026-06-08 20:30 ` Summers, Stuart
2026-06-09 19:54 ` Summers, Stuart
2026-06-05 23:21 ` [PATCH 07/12] drm/xe: Remove memirq status and source checks for engine interrupts Stuart Summers
2026-06-06 11:18 ` Michal Wajdeczko
2026-06-09 19:38 ` Summers, Stuart
2026-06-09 21:29 ` Michal Wajdeczko
2026-06-09 22:12 ` Summers, Stuart
2026-06-05 23:21 ` [PATCH 08/12] drm/xe: Add per-exec-queue user fence wait queue Stuart Summers
2026-06-05 23:21 ` [PATCH 09/12] drm/xe: Track all exec queues in a device-level ufence list Stuart Summers
2026-06-05 23:21 ` Stuart Summers [this message]
2026-06-05 23:21 ` [PATCH 11/12] drm/xe: Enable per-queue ufence wake in ioctl and wake function Stuart Summers
2026-06-05 23:21 ` [PATCH 12/12] drm/xe/memirq: Enable compute walker post-sync interrupt Stuart Summers
2026-06-05 23:47 ` ✗ CI.checkpatch: warning for Enable per exec queue MSI-X vector assignment Patchwork
2026-06-05 23:49 ` ✓ CI.KUnit: success " Patchwork
2026-06-06 0:43 ` ✓ Xe.CI.BAT: " Patchwork
2026-06-06 13:27 ` ✓ Xe.CI.FULL: " Patchwork
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