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From: Michal Wajdeczko <michal.wajdeczko@intel.com>
To: Stuart Summers <stuart.summers@intel.com>
Cc: <ilia.levi@intel.com>, <x.wang@intel.com>,
	<rodrigo.vivi@intel.com>, <intel-xe@lists.freedesktop.org>,
	<alan.previn.teres.alexis@intel.com>
Subject: Re: [PATCH 07/12] drm/xe: Remove memirq status and source checks for engine interrupts
Date: Sat, 6 Jun 2026 13:18:30 +0200	[thread overview]
Message-ID: <d0861102-2bd2-4010-90c3-fee01fe0f142@intel.com> (raw)
In-Reply-To: <20260605232108.674580-21-stuart.summers@intel.com>



On 6/6/2026 1:21 AM, Stuart Summers wrote:
> For engine-specific, memory-based interrupts, hardware will not fill in
> the source and status offsets, assuming that software will utilize the
> vector ID to determine the destination for a particular interrupt.
> 
> GuC and VF based interrupts are still handled the same - explicitly
> checking these offsets.
> 
> Bspec: 62316
> 

no empty lines here
> Signed-off-by: Stuart Summers <stuart.summers@intel.com>
> Assisted-by: Copilot:claude-sonnet-4.6
> ---
>  drivers/gpu/drm/xe/xe_memirq.c | 26 ++++++++------------------
>  1 file changed, 8 insertions(+), 18 deletions(-)
> 
> diff --git a/drivers/gpu/drm/xe/xe_memirq.c b/drivers/gpu/drm/xe/xe_memirq.c
> index 9dfe965cb46e..208f44436c66 100644
> --- a/drivers/gpu/drm/xe/xe_memirq.c
> +++ b/drivers/gpu/drm/xe/xe_memirq.c
> @@ -447,18 +447,18 @@ static void memirq_assume_received(struct xe_memirq *memirq, const char *source,
>  	memirq_debug(memirq, "ASSUME %s %s(%u)\n", source, status, offset);
>  }
>  
> -static void memirq_dispatch_engine(struct xe_memirq *memirq, struct iosys_map *status,
> +static void memirq_dispatch_engine(struct xe_memirq *memirq,
>  				   struct xe_hw_engine *hwe)
>  {
> -	memirq_debug(memirq, "STATUS %s %*ph\n", hwe->name, 16, status->vaddr);
> +	memirq_debug(memirq, "dispatching engine %s\n", hwe->name);
>  
>  	/*
> -	 * The programming note says to assume that GT_MI_USER_INTERRUPT is always
> -	 * set. Check and clear related status byte just for a debug.
> +	 * On MSI-X platforms hardware does not fill in the source and status
> +	 * fields for engine-based interrupts (only GuC and VF interrupts have
> +	 * a valid source/status). The dma-fence check for the fence completion
> +	 * is opportunistic, unconditionally pass MI_USER_INTERRUPT to issue
> +	 * that check.
>  	 */
> -	if (IS_ENABLED(CONFIG_DRM_XE_DEBUG_MEMIRQ) &&
> -	    !memirq_received(memirq, status, ilog2(GT_MI_USER_INTERRUPT), hwe->name))
> -		memirq_assume_received(memirq, hwe->name, ilog2(GT_MI_USER_INTERRUPT), "USER");
>  	xe_hw_engine_handle_irq(hwe, GT_MI_USER_INTERRUPT);
>  }
>  
> @@ -499,17 +499,7 @@ static void memirq_dispatch_guc(struct xe_memirq *memirq, struct iosys_map *stat
>   */
>  void xe_memirq_hwe_handler(struct xe_memirq *memirq, struct xe_hw_engine *hwe)
>  {
> -	struct iosys_map source =
> -		IOSYS_MAP_INIT_OFFSET(&memirq->bo->vmap,
> -				      XE_MEMIRQ_SOURCE_OFFSET(hwe->irq_page));
> -
> -	if (memirq_received(memirq, &source, hwe->irq_offset, "SRC")) {
> -		struct iosys_map status =
> -			IOSYS_MAP_INIT_OFFSET(&memirq->bo->vmap,
> -					      XE_MEMIRQ_VECTOR_OFFSET(hwe->irq_page,
> -								      hwe->irq_offset));
> -		memirq_dispatch_engine(memirq, &status, hwe);
> -	}

maybe put the above new comment here (or update the kernel-doc) and call xe_hw_engine_handle_irq() directly?
then the !MSI-X || VF case will still have a status debug dump option available

> +	memirq_dispatch_engine(memirq, hwe);
>  }
>  
>  /**


  reply	other threads:[~2026-06-06 11:18 UTC|newest]

Thread overview: 24+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2026-06-05 23:21 [PATCH 00/12] Enable per exec queue MSI-X vector assignment Stuart Summers
2026-06-05 23:21 ` [PATCH 01/12] drm/xe: Add kerneldoc to xe_wait_user_fence_ioctl() Stuart Summers
2026-06-05 23:21 ` [PATCH 02/12] drm/xe: Handle NULL in xe_exec_queue_get_unless_zero() Stuart Summers
2026-06-05 23:21 ` [PATCH 03/12] drm/xe: Cap MSI-X vector count to XE_MSIX_MAX_VECS Stuart Summers
2026-06-05 23:21 ` [PATCH 04/12] drm/xe: Assign dedicated MSI-X vectors to exec queues Stuart Summers
2026-06-05 23:21 ` [PATCH 05/12] drm/xe: Add configfs max_msix_vecs attribute Stuart Summers
2026-06-05 23:21 ` [PATCH 06/12] drm/xe: Change MSI-X assignment failure to drm_dbg Stuart Summers
2026-06-06 10:57   ` Michal Wajdeczko
2026-06-08 20:30     ` Summers, Stuart
2026-06-09 19:54       ` Summers, Stuart
2026-06-05 23:21 ` [PATCH 07/12] drm/xe: Remove memirq status and source checks for engine interrupts Stuart Summers
2026-06-06 11:18   ` Michal Wajdeczko [this message]
2026-06-09 19:38     ` Summers, Stuart
2026-06-09 21:29       ` Michal Wajdeczko
2026-06-09 22:12         ` Summers, Stuart
2026-06-05 23:21 ` [PATCH 08/12] drm/xe: Add per-exec-queue user fence wait queue Stuart Summers
2026-06-05 23:21 ` [PATCH 09/12] drm/xe: Track all exec queues in a device-level ufence list Stuart Summers
2026-06-05 23:21 ` [PATCH 10/12] drm/xe: Hook up per queue thread wake to the unique MSI-X vector allocation Stuart Summers
2026-06-05 23:21 ` [PATCH 11/12] drm/xe: Enable per-queue ufence wake in ioctl and wake function Stuart Summers
2026-06-05 23:21 ` [PATCH 12/12] drm/xe/memirq: Enable compute walker post-sync interrupt Stuart Summers
2026-06-05 23:47 ` ✗ CI.checkpatch: warning for Enable per exec queue MSI-X vector assignment Patchwork
2026-06-05 23:49 ` ✓ CI.KUnit: success " Patchwork
2026-06-06  0:43 ` ✓ Xe.CI.BAT: " Patchwork
2026-06-06 13:27 ` ✓ Xe.CI.FULL: " Patchwork

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