* [PATCH 0/6] drm/xe: Capture additional HW register state in devcoredump
@ 2026-08-13 13:30 Nareshkumar Gollakoti
2026-08-13 13:30 ` [PATCH 1/6] drm/xe/devcoredump: Capture GT fuse registers " Nareshkumar Gollakoti
` (8 more replies)
0 siblings, 9 replies; 15+ messages in thread
From: Nareshkumar Gollakoti @ 2026-08-13 13:30 UTC (permalink / raw)
To: intel-xe; +Cc: himal.prasad.ghimiray, Nareshkumar Gollakoti
This series extends the Xe devcoredump with additional hardware register
state to improve post-mortem debugging of GPU hangs and faults on Xe3p.
Today the devcoredump captures GuC log/CT, engine and submission state.
When triaging hangs it is often necessary to also know the static HW
configuration (fuses), GuC status/error state, GAM page-fault reporting
and L3 node status at the time of the hang. Collecting these at capture
time makes the dump self-contained and avoids relying on separate
probe-time logging.
To do this, the series adds a small generic MMIO register-dump helper
(descriptor list -> snapshot -> print/free) and uses it for several
register groups. Each group is captured for both the primary GT and,
where applicable, the media GT, and is gated to Xe3p (GRAPHICS_VER >= 35).
Registers requiring MCR steering are read through
xe_gt_mcr_unicast_read_any(); the remaining GAM registers use INSTANCE0
default steering and are read directly.
Snapshots are allocated with GFP_ATOMIC as capture runs inside the
dma_fence signalling section, matching the surrounding captures, and are
freed in the existing devcoredump teardown path.
Patches:
1 Add the generic reg-dump helpers and capture GT/media fuse registers.
2 Capture GT and media GuC status/error registers.
3 Print register offsets alongside names in the GuC engine capture
output (32- and 64-bit), easing cross-reference with the bspec.
4 Capture the GAM page-fault report head/tail registers.
5 Add the TDL gfx registers to the XeHPG extended GuC capture list.
6 Capture L3 node status registers (MCR, read via unicast_read_any()).
Sample devcoredump output gains the following sections:
**** GT Fuse Register Dump ****
**** Media GT Fuse Register Dump ****
**** GT GuC Register Dump ****
**** Media GT GuC Register Dump ****
**** GAM PF Report ****
**** Node Status ****
Nareshkumar Gollakoti (6):
drm/xe/devcoredump: Capture GT fuse registers in devcoredump
drm/xe/devcoredump: Add GuC register snapshot to devcoredump
drm/xe/guc: Print register addresses in capture snapshot output
drm/xe: dump GAM page fault report registers in devcoredump
drm/xe/guc: add TDL gfx registers to capture list
drm/xe: capture L3 node status registers in devcoredump
drivers/gpu/drm/xe/regs/xe_gt_regs.h | 17 ++
drivers/gpu/drm/xe/regs/xe_guc_regs.h | 13 ++
drivers/gpu/drm/xe/xe_devcoredump.c | 266 ++++++++++++++++++++++
drivers/gpu/drm/xe/xe_devcoredump_types.h | 45 ++++
drivers/gpu/drm/xe/xe_device.h | 5 +
drivers/gpu/drm/xe/xe_guc_capture.c | 15 +-
6 files changed, 356 insertions(+), 5 deletions(-)
--
2.43.0
^ permalink raw reply [flat|nested] 15+ messages in thread
* [PATCH 1/6] drm/xe/devcoredump: Capture GT fuse registers in devcoredump
2026-08-13 13:30 [PATCH 0/6] drm/xe: Capture additional HW register state in devcoredump Nareshkumar Gollakoti
@ 2026-08-13 13:30 ` Nareshkumar Gollakoti
2026-08-13 13:52 ` sashiko-bot
2026-08-13 13:30 ` [PATCH 2/6] drm/xe/devcoredump: Add GuC register snapshot to devcoredump Nareshkumar Gollakoti
` (7 subsequent siblings)
8 siblings, 1 reply; 15+ messages in thread
From: Nareshkumar Gollakoti @ 2026-08-13 13:30 UTC (permalink / raw)
To: intel-xe; +Cc: himal.prasad.ghimiray, Nareshkumar Gollakoti
Capture fuse-related GT register state in the Xe devcoredump to preserve
additional hardware configuration information for postmortem debugging.
Add generic register snapshot storage and helpers for capturing,
printing, and freeing MMIO register dumps. Use them to record both
primary GT and media GT fuse register state during devcoredump snapshot
collection and print the captured values in the coredump output.
Also add the required GT register definitions for RPM and mirror
copy-enable state used by the new dump paths.
Signed-off-by: Nareshkumar Gollakoti <naresh.kumar.g@intel.com>
---
drivers/gpu/drm/xe/regs/xe_gt_regs.h | 8 ++
drivers/gpu/drm/xe/xe_devcoredump.c | 146 ++++++++++++++++++++++
drivers/gpu/drm/xe/xe_devcoredump_types.h | 35 ++++++
drivers/gpu/drm/xe/xe_device.h | 5 +
4 files changed, 194 insertions(+)
diff --git a/drivers/gpu/drm/xe/regs/xe_gt_regs.h b/drivers/gpu/drm/xe/regs/xe_gt_regs.h
index 48c515d91882..959b1129fd50 100644
--- a/drivers/gpu/drm/xe/regs/xe_gt_regs.h
+++ b/drivers/gpu/drm/xe/regs/xe_gt_regs.h
@@ -22,6 +22,9 @@
#define MTL_CC_MASK REG_GENMASK(12, 9)
#define MTL_CRST 0xf
+#define RPM_GCD XE_REG(0xc98)
+#define RPM_GCD_MEDIA XE_REG(0x380c98)
+
/* RPM unit config (Gen8+) */
#define RPM_CONFIG0 XE_REG(0xd00)
#define RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_MASK REG_GENMASK(5, 3)
@@ -274,6 +277,11 @@
#define SERVICE_COPY_ENABLE XE_REG(0x9170)
#define FUSE_SERVICE_COPY_ENABLE_MASK REG_GENMASK(7, 0)
+#define COPY_ENABLE_GTFS_GCD XE_REG(0x9174)
+
+#define SERVICE_COPY_ENABLE_MEDIA XE_REG(0x389170)
+#define COPY_ENABLE_GTFS_GCD_MEDIA XE_REG(0x389174)
+
#define GDRST XE_REG(0x941c)
#define GRDOM_GUC REG_BIT(3)
#define GRDOM_FULL REG_BIT(0)
diff --git a/drivers/gpu/drm/xe/xe_devcoredump.c b/drivers/gpu/drm/xe/xe_devcoredump.c
index 5f2b90b18f97..35d8101f2a19 100644
--- a/drivers/gpu/drm/xe/xe_devcoredump.c
+++ b/drivers/gpu/drm/xe/xe_devcoredump.c
@@ -25,6 +25,8 @@
#include "xe_pm.h"
#include "xe_sched_job.h"
#include "xe_vm.h"
+#include "xe_mmio.h"
+#include "regs/xe_gt_regs.h"
/**
* DOC: Xe device coredump
@@ -69,6 +71,136 @@
/* 1 hour timeout */
#define XE_COREDUMP_TIMEOUT_JIFFIES (60 * 60 * HZ)
+/**
+ * struct xe_reg_desc - Register descriptor struct to make reg list
+ *
+ * This struct is used as descriptor containting reg address and name
+ * of the register to dump its value during coredump for debug purpose.
+ */
+struct xe_reg_desc {
+ /** @reg: The register */
+ struct xe_reg reg;
+ /** @name: Name of the register */
+ const char *name;
+};
+
+static const struct xe_reg_desc xe3p_gt_fuse_reglist[] = {
+ { XELP_GT_GEOMETRY_DSS_ENABLE, "GT_GEOMETRY_DSS_ENABLE" },
+ { XEHP_GT_COMPUTE_DSS_ENABLE, "GT_COMPUTE_DSS_ENABLE" },
+ { XELP_EU_ENABLE, "EU_ENABLE" },
+ { MIRROR_FUSE1, "MIRROR_FUSE1" },
+ { GT_VEBOX_VDBOX_DISABLE, "GT_VEBOX_VDBOX_DISABLE" },
+ { SERVICE_COPY_ENABLE, "SERVICE_COPY_ENABLE" },
+ { COPY_ENABLE_GTFS_GCD, "COPY_ENABLE_GTFS_GCD" },
+ { XE2_GT_GEOMETRY_DSS_1, "GT_GEOMETRY_DSS_1" },
+ { XE2_GT_GEOMETRY_DSS_2, "GT_GEOMETRY_DSS_2" },
+ { XE2_GT_COMPUTE_DSS_2, "GT_COMPUTE_DSS_2" },
+ { XEHPC_GT_COMPUTE_DSS_ENABLE_EXT, "GT_COMPUTE_DSS_ENABLE_EXT" },
+ { XE3P_XPC_GT_GEOMETRY_DSS_3, "GT_GEOMETRY_DSS_3" },
+ { XE3P_XPC_GT_COMPUTE_DSS_3, "GT_COMPUTE_DSS_3" },
+ { RPM_GCD, "RPM_GCD" },
+};
+
+static const struct xe_reg_desc xe3p_media_gt_fuse_reglist[] = {
+ { SERVICE_COPY_ENABLE_MEDIA, "SERVICE_COPY_ENABLE_MEDIA" },
+ { COPY_ENABLE_GTFS_GCD_MEDIA, "COPY_ENABLE_GTFS_GCD_MEDIA" },
+ { RPM_GCD_MEDIA, "RPM_GCD_MEDIA" },
+};
+
+/**
+ * struct xe_reg_desc_list - Struct for register descriptor list
+ *
+ * This struct is used to reference the corresponding reglist of
+ * various component
+ */
+struct xe_reg_desc_list {
+ /** @regs: The register discriptor struct pointer*/
+ const struct xe_reg_desc *regs;
+ /** @num_regs: refernce for num regs in reg descriptor*/
+ u32 num_regs;
+};
+
+static void
+xe_capture_reg_desc_list(struct xe_gt *gt,
+ struct xe_reg_dump_snapshot *dst,
+ const struct xe_reg_desc *src,
+ u32 count)
+{
+ u32 i;
+
+ for (i = 0; i < count; i++) {
+ dst[i].reg = src[i].reg;
+ dst[i].value = xe_mmio_read32(>->mmio, src[i].reg);
+ dst[i].name = src[i].name;
+ }
+}
+
+static struct xe_dbg_reg_snapshot *
+xe_dbg_reg_snapshot_capture(struct xe_gt *gt,
+ const struct xe_reg_desc_list *reglist)
+{
+ struct xe_dbg_reg_snapshot *snap;
+
+ if (!reglist->regs || !reglist->num_regs)
+ return NULL;
+
+ snap = kzalloc(struct_size(snap, regs, reglist->num_regs), GFP_ATOMIC);
+ if (!snap)
+ return NULL;
+
+ snap->num_regs = reglist->num_regs;
+
+ xe_capture_reg_desc_list(gt, snap->regs, reglist->regs, reglist->num_regs);
+
+ return snap;
+}
+
+static void xe_dbg_reg_snapshot_print(struct drm_printer *p,
+ const struct xe_dbg_reg_snapshot *snap)
+{
+ u32 i;
+
+ if (!snap)
+ return;
+
+ for (i = 0; i < snap->num_regs; i++)
+ drm_printf(p, " %s [0x%x] = 0x%08x\n",
+ snap->regs[i].name,
+ snap->regs[i].reg.addr,
+ snap->regs[i].value);
+}
+
+static void xe_dbg_reg_snapshot_free(struct xe_dbg_reg_snapshot *snap)
+{
+ kfree(snap);
+}
+
+static struct xe_dbg_reg_snapshot *xe_gt_fuse_snapshot_capture(struct xe_gt *gt)
+{
+ struct xe_reg_desc_list reg_list;
+
+ if (!xe_dbg_reg_snapshot_is_supported(gt_to_xe(gt)))
+ return NULL;
+
+ reg_list.regs = xe3p_gt_fuse_reglist;
+ reg_list.num_regs = ARRAY_SIZE(xe3p_gt_fuse_reglist);
+
+ return xe_dbg_reg_snapshot_capture(gt, ®_list);
+}
+
+static struct xe_dbg_reg_snapshot *xe_media_gt_fuse_snapshot_capture(struct xe_gt *gt)
+{
+ struct xe_reg_desc_list reg_list;
+
+ if (!xe_dbg_reg_snapshot_is_supported(gt_to_xe(gt)))
+ return NULL;
+
+ reg_list.regs = xe3p_media_gt_fuse_reglist;
+ reg_list.num_regs = ARRAY_SIZE(xe3p_media_gt_fuse_reglist);
+
+ return xe_dbg_reg_snapshot_capture(gt, ®_list);
+}
+
static struct xe_device *coredump_to_xe(const struct xe_devcoredump *coredump)
{
return container_of(coredump, struct xe_device, devcoredump);
@@ -114,6 +246,11 @@ static ssize_t __xe_devcoredump_read(char *buffer, ssize_t count,
drm_printf(&p, "\n**** GT #%d ****\n", ss->gt->info.id);
drm_printf(&p, "\tTile: %d\n", ss->gt->tile->id);
+ drm_printf(&p, "\n**** GT Fuse Register Dump ****\n");
+ xe_dbg_reg_snapshot_print(&p, ss->gt_fuse);
+ drm_printf(&p, "\n**** Media GT Fuse Register Dump ****\n");
+ xe_dbg_reg_snapshot_print(&p, ss->media_fuse);
+
drm_puts(&p, "\n**** GuC Log ****\n");
xe_guc_log_snapshot_print(ss->guc.log, &p);
drm_puts(&p, "\n**** GuC CT ****\n");
@@ -149,6 +286,12 @@ static void xe_devcoredump_snapshot_free(struct xe_devcoredump_snapshot *ss)
xe_guc_ct_snapshot_free(ss->guc.ct);
ss->guc.ct = NULL;
+ xe_dbg_reg_snapshot_free(ss->gt_fuse);
+ ss->gt_fuse = NULL;
+
+ xe_dbg_reg_snapshot_free(ss->media_fuse);
+ ss->media_fuse = NULL;
+
if (!IS_ERR_OR_NULL(ss->gt))
xe_guc_capture_put_matched_nodes(&ss->gt->uc.guc);
ss->matched_node = NULL;
@@ -349,6 +492,9 @@ static void devcoredump_snapshot(struct xe_devcoredump *coredump,
cookie = dma_fence_begin_signalling();
+ ss->gt_fuse = xe_gt_fuse_snapshot_capture(q->gt);
+ ss->media_fuse = xe_media_gt_fuse_snapshot_capture(q->gt);
+
ss->guc.log = xe_guc_log_snapshot_capture(&guc->log, true);
ss->guc.ct = xe_guc_ct_snapshot_capture(&guc->ct);
ss->ge = xe_guc_exec_queue_snapshot_capture(q);
diff --git a/drivers/gpu/drm/xe/xe_devcoredump_types.h b/drivers/gpu/drm/xe/xe_devcoredump_types.h
index a174385a6d83..14490b61a56f 100644
--- a/drivers/gpu/drm/xe/xe_devcoredump_types.h
+++ b/drivers/gpu/drm/xe/xe_devcoredump_types.h
@@ -14,6 +14,35 @@
struct xe_device;
struct xe_gt;
+/**
+ * struct xe_reg_dump_snapshot - dump register snapshot
+ *
+ * This struct used as generic reg dump snapshot in the format of
+ * register, its value and its name for human readable format.
+ */
+struct xe_reg_dump_snapshot {
+ /** @reg: xe register structure*/
+ struct xe_reg reg;
+ /** @value: Value of the register*/
+ u32 value;
+ /** @name: Name of the register */
+ const char *name;
+};
+
+/**
+ * struct xe_dbg_reg_snapshot - Register snapshot
+ *
+ * This struct contains the register values captured at the time of the crash.
+ * It is used to store the register values in a human-readable format for
+ * debugging purposes.
+ */
+struct xe_dbg_reg_snapshot {
+ /** @num_regs: Number of registers need for capture. */
+ u32 num_regs;
+ /** @regs: Array of fuse register snapshots. */
+ struct xe_reg_dump_snapshot regs[];
+};
+
/**
* struct xe_devcoredump_snapshot - Crash snapshot
*
@@ -35,6 +64,12 @@ struct xe_devcoredump_snapshot {
/** @gt: Affected GT, used by forcewake for delayed capture */
struct xe_gt *gt;
+
+ /** @gt_fuse: Fuse snapshot */
+ struct xe_dbg_reg_snapshot *gt_fuse;
+ /** @media_fuse: Media Fuse snapshot */
+ struct xe_dbg_reg_snapshot *media_fuse;
+
/** @work: Workqueue for deferred capture outside of signaling context */
struct work_struct work;
diff --git a/drivers/gpu/drm/xe/xe_device.h b/drivers/gpu/drm/xe/xe_device.h
index 6c4cfaebc44a..d199a674675b 100644
--- a/drivers/gpu/drm/xe/xe_device.h
+++ b/drivers/gpu/drm/xe/xe_device.h
@@ -260,6 +260,11 @@ static inline bool xe_debug_page_size_mode_is_mixed(struct xe_device *xe)
}
#endif
+static inline bool xe_dbg_reg_snapshot_is_supported(struct xe_device *xe)
+{
+ return (GRAPHICS_VER(xe) >= 35) ? true : false;
+}
+
void xe_device_set_wedged_method(struct xe_device *xe, unsigned long method);
void xe_device_declare_wedged(struct xe_device *xe);
int xe_device_validate_wedged_mode(struct xe_device *xe, unsigned int mode);
--
2.43.0
^ permalink raw reply related [flat|nested] 15+ messages in thread
* [PATCH 2/6] drm/xe/devcoredump: Add GuC register snapshot to devcoredump
2026-08-13 13:30 [PATCH 0/6] drm/xe: Capture additional HW register state in devcoredump Nareshkumar Gollakoti
2026-08-13 13:30 ` [PATCH 1/6] drm/xe/devcoredump: Capture GT fuse registers " Nareshkumar Gollakoti
@ 2026-08-13 13:30 ` Nareshkumar Gollakoti
2026-08-13 14:04 ` sashiko-bot
2026-08-13 13:30 ` [PATCH 3/6] drm/xe/guc: Print register addresses in capture snapshot output Nareshkumar Gollakoti
` (6 subsequent siblings)
8 siblings, 1 reply; 15+ messages in thread
From: Nareshkumar Gollakoti @ 2026-08-13 13:30 UTC (permalink / raw)
To: intel-xe; +Cc: himal.prasad.ghimiray, Nareshkumar Gollakoti
Add support for capturing GuC register state as part of the xe
devcoredump snapshot.
Define a dedicated GuC register snapshot structure, record selected
GT and media GuC status/error registers during devcoredump capture,
and free the snapshot during teardown.
Keeping these register values in the devcoredump helps with
post-mortem analysis of GuC-related failures.
Signed-off-by: Nareshkumar Gollakoti <naresh.kumar.g@intel.com>
---
drivers/gpu/drm/xe/regs/xe_guc_regs.h | 13 +++++
drivers/gpu/drm/xe/xe_devcoredump.c | 60 +++++++++++++++++++++++
drivers/gpu/drm/xe/xe_devcoredump_types.h | 5 ++
3 files changed, 78 insertions(+)
diff --git a/drivers/gpu/drm/xe/regs/xe_guc_regs.h b/drivers/gpu/drm/xe/regs/xe_guc_regs.h
index 5faac8316b66..99487abbbc62 100644
--- a/drivers/gpu/drm/xe/regs/xe_guc_regs.h
+++ b/drivers/gpu/drm/xe/regs/xe_guc_regs.h
@@ -150,6 +150,19 @@
#define GUC_INTR_SW_INT_1 REG_BIT(1)
#define GUC_INTR_SW_INT_0 REG_BIT(0)
+#define GUC_DEVICEID XE_REG(0xc008)
+#define GUC_SHIM_ERR_TRAP XE_REG(0xc070)
+#define GUC_HW_FATL_ERR XE_REG(0xc598)
+#define GUC_HW_NOTIFY_ERR XE_REG(0xc59c)
+
+#define GUC_STATUS_M XE_REG(0x38c000)
+#define GUC_WOPCM_SIZE_M XE_REG(0x38c050)
+#define GUC_DEVICEID_M XE_REG(0x38c008)
+#define DMA_CTRL_M XE_REG(0x38c314)
+#define GUC_HW_FATL_ERR_M XE_REG(0x38c598)
+#define GUC_HW_NOTIFY_ERR_M XE_REG(0x38c59c)
+#define GUC_SHIM_ERR_TRAP_M XE_REG(0x38c070)
+
#define GUC_NUM_DOORBELLS 256
/* format of the HW-monitored doorbell cacheline */
diff --git a/drivers/gpu/drm/xe/xe_devcoredump.c b/drivers/gpu/drm/xe/xe_devcoredump.c
index 35d8101f2a19..b339d4035628 100644
--- a/drivers/gpu/drm/xe/xe_devcoredump.c
+++ b/drivers/gpu/drm/xe/xe_devcoredump.c
@@ -27,6 +27,7 @@
#include "xe_vm.h"
#include "xe_mmio.h"
#include "regs/xe_gt_regs.h"
+#include "regs/xe_guc_regs.h"
/**
* DOC: Xe device coredump
@@ -84,6 +85,26 @@ struct xe_reg_desc {
const char *name;
};
+static const struct xe_reg_desc xe_gt_guc_reg_list[] = {
+ {GUC_STATUS, "GUC_STATUS"},
+ {GUC_WOPCM_SIZE, "GUC_WOPCM_SIZE"},
+ {GUC_DEVICEID, "GUC_DEVICEID"},
+ {DMA_CTRL, "DMA_CTRL"},
+ {GUC_HW_FATL_ERR, "GUC_HW_FATL_ERR"},
+ {GUC_HW_NOTIFY_ERR, "GUC_HW_NOTIFY_ERR"},
+ {GUC_SHIM_ERR_TRAP, "GUC_SHIM_ERR_TRAP"},
+};
+
+static const struct xe_reg_desc xe_media_gt_guc_reg_list[] = {
+ {GUC_STATUS_M, "GUC_STATUS_M"},
+ {GUC_WOPCM_SIZE_M, "GUC_WOPCM_SIZE_M"},
+ {GUC_DEVICEID_M, "GUC_DEVICEID_M"},
+ {DMA_CTRL_M, "DMA_CTRL_M"},
+ {GUC_HW_FATL_ERR_M, "GUC_HW_FATL_ERR_M"},
+ {GUC_HW_NOTIFY_ERR_M, "GUC_HW_NOTIFY_ERR_M"},
+ {GUC_SHIM_ERR_TRAP_M, "GUC_SHIM_ERR_TRAP_M"}
+};
+
static const struct xe_reg_desc xe3p_gt_fuse_reglist[] = {
{ XELP_GT_GEOMETRY_DSS_ENABLE, "GT_GEOMETRY_DSS_ENABLE" },
{ XEHP_GT_COMPUTE_DSS_ENABLE, "GT_COMPUTE_DSS_ENABLE" },
@@ -201,6 +222,32 @@ static struct xe_dbg_reg_snapshot *xe_media_gt_fuse_snapshot_capture(struct xe_g
return xe_dbg_reg_snapshot_capture(gt, ®_list);
}
+static struct xe_dbg_reg_snapshot *xe_gt_guc_reg_snapshot_capture(struct xe_gt *gt)
+{
+ struct xe_reg_desc_list reg_list;
+
+ if (!xe_dbg_reg_snapshot_is_supported(gt_to_xe(gt)))
+ return NULL;
+
+ reg_list.regs = xe_gt_guc_reg_list;
+ reg_list.num_regs = ARRAY_SIZE(xe_gt_guc_reg_list);
+
+ return xe_dbg_reg_snapshot_capture(gt, ®_list);
+}
+
+static struct xe_dbg_reg_snapshot *xe_media_gt_guc_reg_snapshot_capture(struct xe_gt *gt)
+{
+ struct xe_reg_desc_list reg_list;
+
+ if (!xe_dbg_reg_snapshot_is_supported(gt_to_xe(gt)))
+ return NULL;
+
+ reg_list.regs = xe_media_gt_guc_reg_list;
+ reg_list.num_regs = ARRAY_SIZE(xe_media_gt_guc_reg_list);
+
+ return xe_dbg_reg_snapshot_capture(gt, ®_list);
+}
+
static struct xe_device *coredump_to_xe(const struct xe_devcoredump *coredump)
{
return container_of(coredump, struct xe_device, devcoredump);
@@ -251,6 +298,11 @@ static ssize_t __xe_devcoredump_read(char *buffer, ssize_t count,
drm_printf(&p, "\n**** Media GT Fuse Register Dump ****\n");
xe_dbg_reg_snapshot_print(&p, ss->media_fuse);
+ drm_printf(&p, "\n**** GT GuC Register Dump ****\n");
+ xe_dbg_reg_snapshot_print(&p, ss->gt_guc_reg);
+ drm_printf(&p, "\n**** Media GT GuC Register Dump ****\n");
+ xe_dbg_reg_snapshot_print(&p, ss->media_gt_guc_reg);
+
drm_puts(&p, "\n**** GuC Log ****\n");
xe_guc_log_snapshot_print(ss->guc.log, &p);
drm_puts(&p, "\n**** GuC CT ****\n");
@@ -292,6 +344,12 @@ static void xe_devcoredump_snapshot_free(struct xe_devcoredump_snapshot *ss)
xe_dbg_reg_snapshot_free(ss->media_fuse);
ss->media_fuse = NULL;
+ xe_dbg_reg_snapshot_free(ss->gt_guc_reg);
+ ss->gt_guc_reg = NULL;
+
+ xe_dbg_reg_snapshot_free(ss->media_gt_guc_reg);
+ ss->media_gt_guc_reg = NULL;
+
if (!IS_ERR_OR_NULL(ss->gt))
xe_guc_capture_put_matched_nodes(&ss->gt->uc.guc);
ss->matched_node = NULL;
@@ -495,6 +553,8 @@ static void devcoredump_snapshot(struct xe_devcoredump *coredump,
ss->gt_fuse = xe_gt_fuse_snapshot_capture(q->gt);
ss->media_fuse = xe_media_gt_fuse_snapshot_capture(q->gt);
+ ss->gt_guc_reg = xe_gt_guc_reg_snapshot_capture(q->gt);
+ ss->media_gt_guc_reg = xe_media_gt_guc_reg_snapshot_capture(q->gt);
ss->guc.log = xe_guc_log_snapshot_capture(&guc->log, true);
ss->guc.ct = xe_guc_ct_snapshot_capture(&guc->ct);
ss->ge = xe_guc_exec_queue_snapshot_capture(q);
diff --git a/drivers/gpu/drm/xe/xe_devcoredump_types.h b/drivers/gpu/drm/xe/xe_devcoredump_types.h
index 14490b61a56f..28b505176657 100644
--- a/drivers/gpu/drm/xe/xe_devcoredump_types.h
+++ b/drivers/gpu/drm/xe/xe_devcoredump_types.h
@@ -70,6 +70,11 @@ struct xe_devcoredump_snapshot {
/** @media_fuse: Media Fuse snapshot */
struct xe_dbg_reg_snapshot *media_fuse;
+ /** @gt_guc_reg: gt guc reg snapshot */
+ struct xe_dbg_reg_snapshot *gt_guc_reg;
+ /** @media_gt_guc_reg: media gt guc reg snapshot */
+ struct xe_dbg_reg_snapshot *media_gt_guc_reg;
+
/** @work: Workqueue for deferred capture outside of signaling context */
struct work_struct work;
--
2.43.0
^ permalink raw reply related [flat|nested] 15+ messages in thread
* [PATCH 3/6] drm/xe/guc: Print register addresses in capture snapshot output
2026-08-13 13:30 [PATCH 0/6] drm/xe: Capture additional HW register state in devcoredump Nareshkumar Gollakoti
2026-08-13 13:30 ` [PATCH 1/6] drm/xe/devcoredump: Capture GT fuse registers " Nareshkumar Gollakoti
2026-08-13 13:30 ` [PATCH 2/6] drm/xe/devcoredump: Add GuC register snapshot to devcoredump Nareshkumar Gollakoti
@ 2026-08-13 13:30 ` Nareshkumar Gollakoti
2026-08-13 14:11 ` sashiko-bot
2026-08-13 13:30 ` [PATCH 4/6] drm/xe: dump GAM page fault report registers in devcoredump Nareshkumar Gollakoti
` (5 subsequent siblings)
8 siblings, 1 reply; 15+ messages in thread
From: Nareshkumar Gollakoti @ 2026-08-13 13:30 UTC (permalink / raw)
To: intel-xe; +Cc: himal.prasad.ghimiray, Nareshkumar Gollakoti
Include register offsets in GuC capture snapshot print output for both
32-bit and 64-bit registers.
When dumping captured engine register state, print each register name
alongside its MMIO offset to make the snapshot output easier to
cross-reference with register definitions and hardware debug
documentation.
This improves postmortem analysis without changing capture contents.
Signed-off-by: Nareshkumar Gollakoti <naresh.kumar.g@intel.com>
---
drivers/gpu/drm/xe/xe_guc_capture.c | 11 +++++++----
1 file changed, 7 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/xe/xe_guc_capture.c b/drivers/gpu/drm/xe/xe_guc_capture.c
index 82df19b304e1..368769857c9b 100644
--- a/drivers/gpu/drm/xe/xe_guc_capture.c
+++ b/drivers/gpu/drm/xe/xe_guc_capture.c
@@ -1774,7 +1774,9 @@ snapshot_print_by_list_order(struct xe_hw_engine_snapshot *snapshot, struct drm_
XE_WARN_ON(!low32_ready);
low32_ready = false;
- drm_printf(p, "\t%s: 0x%016llx\n", reg_desc->regname, value_qw);
+ drm_printf(p, "\t%s (0x%x): 0x%016llx\n", reg_desc->regname,
+ reg_desc->reg.addr,
+ value_qw);
break;
}
@@ -1788,10 +1790,11 @@ snapshot_print_by_list_order(struct xe_hw_engine_snapshot *snapshot, struct drm_
XE_WARN_ON(low32_ready);
if (FIELD_GET(GUC_REGSET_STEERING_NEEDED, reg_desc->flags))
- drm_printf(p, "\t%s[%u]: 0x%08x\n", reg_desc->regname,
- reg_desc->dss_id, value);
+ drm_printf(p, "\t%s[%u] (0x%x): 0x%08x\n", reg_desc->regname,
+ reg_desc->dss_id, reg_desc->reg.addr, value);
else
- drm_printf(p, "\t%s: 0x%08x\n", reg_desc->regname, value);
+ drm_printf(p, "\t%s (0x%x): 0x%08x\n", reg_desc->regname,
+ reg_desc->reg.addr, value);
break;
}
--
2.43.0
^ permalink raw reply related [flat|nested] 15+ messages in thread
* [PATCH 4/6] drm/xe: dump GAM page fault report registers in devcoredump
2026-08-13 13:30 [PATCH 0/6] drm/xe: Capture additional HW register state in devcoredump Nareshkumar Gollakoti
` (2 preceding siblings ...)
2026-08-13 13:30 ` [PATCH 3/6] drm/xe/guc: Print register addresses in capture snapshot output Nareshkumar Gollakoti
@ 2026-08-13 13:30 ` Nareshkumar Gollakoti
2026-08-13 13:30 ` [PATCH 5/6] drm/xe/guc: add TDL gfx registers to capture list Nareshkumar Gollakoti
` (4 subsequent siblings)
8 siblings, 0 replies; 15+ messages in thread
From: Nareshkumar Gollakoti @ 2026-08-13 13:30 UTC (permalink / raw)
To: intel-xe; +Cc: himal.prasad.ghimiray, Nareshkumar Gollakoti
Add PAGE_FLTRPTQ_HEAD_GAMCTRL and PAGE_FLTRPTQ_TAIL_GAMCTRL to the Xe
register definitions and capture them as part of the devcoredump
snapshot.
Include the register dump in the devcoredump output and release the
snapshot during cleanup so page fault report state is available for
post-mortem debugging.
Signed-off-by: Nareshkumar Gollakoti <naresh.kumar.g@intel.com>
---
drivers/gpu/drm/xe/regs/xe_gt_regs.h | 3 +++
drivers/gpu/drm/xe/xe_devcoredump.c | 25 +++++++++++++++++++++++
drivers/gpu/drm/xe/xe_devcoredump_types.h | 3 +++
3 files changed, 31 insertions(+)
diff --git a/drivers/gpu/drm/xe/regs/xe_gt_regs.h b/drivers/gpu/drm/xe/regs/xe_gt_regs.h
index 959b1129fd50..25014bccd3a6 100644
--- a/drivers/gpu/drm/xe/regs/xe_gt_regs.h
+++ b/drivers/gpu/drm/xe/regs/xe_gt_regs.h
@@ -505,6 +505,9 @@
#define LMEM_EN REG_BIT(31)
#define LMTT_DIR_PTR REG_GENMASK(30, 0) /* in multiples of 64KB */
+#define PAGE_FLTRPTQ_HEAD_GAMCTRL XE_REG(0xcf90)
+#define PAGE_FLTRPTQ_TAIL_GAMCTRL XE_REG(0xcf94)
+
#define HALF_SLICE_CHICKEN5 XE_REG_MCR(0xe188, XE_REG_OPTION_MASKED)
#define DISABLE_SAMPLE_G_PERFORMANCE REG_BIT(0)
diff --git a/drivers/gpu/drm/xe/xe_devcoredump.c b/drivers/gpu/drm/xe/xe_devcoredump.c
index b339d4035628..6cc4e3969417 100644
--- a/drivers/gpu/drm/xe/xe_devcoredump.c
+++ b/drivers/gpu/drm/xe/xe_devcoredump.c
@@ -128,6 +128,11 @@ static const struct xe_reg_desc xe3p_media_gt_fuse_reglist[] = {
{ RPM_GCD_MEDIA, "RPM_GCD_MEDIA" },
};
+static const struct xe_reg_desc xe3p_gam_pf_reglist[] = {
+ { PAGE_FLTRPTQ_HEAD_GAMCTRL, "PAGE_FLTRPTQ_HEAD_GAMCTRL"},
+ { PAGE_FLTRPTQ_TAIL_GAMCTRL, "PAGE_FLTRPTQ_TAIL_GAMCTRL"},
+};
+
/**
* struct xe_reg_desc_list - Struct for register descriptor list
*
@@ -248,6 +253,19 @@ static struct xe_dbg_reg_snapshot *xe_media_gt_guc_reg_snapshot_capture(struct x
return xe_dbg_reg_snapshot_capture(gt, ®_list);
}
+static struct xe_dbg_reg_snapshot *xe_gam_pf_report_capture(struct xe_gt *gt)
+{
+ struct xe_reg_desc_list reg_list;
+
+ if (!xe_dbg_reg_snapshot_is_supported(gt_to_xe(gt)))
+ return NULL;
+
+ reg_list.regs = xe3p_gam_pf_reglist;
+ reg_list.num_regs = ARRAY_SIZE(xe3p_gam_pf_reglist);
+
+ return xe_dbg_reg_snapshot_capture(gt, ®_list);
+}
+
static struct xe_device *coredump_to_xe(const struct xe_devcoredump *coredump)
{
return container_of(coredump, struct xe_device, devcoredump);
@@ -308,6 +326,9 @@ static ssize_t __xe_devcoredump_read(char *buffer, ssize_t count,
drm_puts(&p, "\n**** GuC CT ****\n");
xe_guc_ct_snapshot_print(ss->guc.ct, &p);
+ drm_printf(&p, "\n**** GAM PF Report ****\n");
+ xe_dbg_reg_snapshot_print(&p, ss->gam_pf_report);
+
drm_puts(&p, "\n**** Contexts ****\n");
xe_guc_exec_queue_snapshot_print(ss->ge, &p);
@@ -354,6 +375,9 @@ static void xe_devcoredump_snapshot_free(struct xe_devcoredump_snapshot *ss)
xe_guc_capture_put_matched_nodes(&ss->gt->uc.guc);
ss->matched_node = NULL;
+ xe_dbg_reg_snapshot_free(ss->gam_pf_report);
+ ss->gam_pf_report = NULL;
+
xe_guc_exec_queue_snapshot_free(ss->ge);
ss->ge = NULL;
@@ -557,6 +581,7 @@ static void devcoredump_snapshot(struct xe_devcoredump *coredump,
ss->media_gt_guc_reg = xe_media_gt_guc_reg_snapshot_capture(q->gt);
ss->guc.log = xe_guc_log_snapshot_capture(&guc->log, true);
ss->guc.ct = xe_guc_ct_snapshot_capture(&guc->ct);
+ ss->gam_pf_report = xe_gam_pf_report_capture(q->gt);
ss->ge = xe_guc_exec_queue_snapshot_capture(q);
if (job)
ss->job = xe_sched_job_snapshot_capture(job);
diff --git a/drivers/gpu/drm/xe/xe_devcoredump_types.h b/drivers/gpu/drm/xe/xe_devcoredump_types.h
index 28b505176657..893eadd68a3d 100644
--- a/drivers/gpu/drm/xe/xe_devcoredump_types.h
+++ b/drivers/gpu/drm/xe/xe_devcoredump_types.h
@@ -86,6 +86,9 @@ struct xe_devcoredump_snapshot {
struct xe_guc_log_snapshot *log;
} guc;
+ /** @gam_pf_report: GAM PF report snapshot */
+ struct xe_dbg_reg_snapshot *gam_pf_report;
+
/** @ge: GuC Submission Engine snapshot */
struct xe_guc_submit_exec_queue_snapshot *ge;
--
2.43.0
^ permalink raw reply related [flat|nested] 15+ messages in thread
* [PATCH 5/6] drm/xe/guc: add TDL gfx registers to capture list
2026-08-13 13:30 [PATCH 0/6] drm/xe: Capture additional HW register state in devcoredump Nareshkumar Gollakoti
` (3 preceding siblings ...)
2026-08-13 13:30 ` [PATCH 4/6] drm/xe: dump GAM page fault report registers in devcoredump Nareshkumar Gollakoti
@ 2026-08-13 13:30 ` Nareshkumar Gollakoti
2026-08-13 14:25 ` sashiko-bot
2026-08-13 13:30 ` [PATCH 6/6] drm/xe: capture L3 node status registers in devcoredump Nareshkumar Gollakoti
` (3 subsequent siblings)
8 siblings, 1 reply; 15+ messages in thread
From: Nareshkumar Gollakoti @ 2026-08-13 13:30 UTC (permalink / raw)
To: intel-xe; +Cc: himal.prasad.ghimiray, Nareshkumar Gollakoti
Add ROW_INSDONE_TDL_GFX and SS_LSC_HDC_IDLE_TDL_GFX register
definitions and include them in the XeHPG extended GuC capture register
list.
This makes the TDL gfx state available in GuC error captures for
debugging hang and fault scenarios.
Signed-off-by: Nareshkumar Gollakoti <naresh.kumar.g@intel.com>
---
drivers/gpu/drm/xe/regs/xe_gt_regs.h | 3 +++
drivers/gpu/drm/xe/xe_guc_capture.c | 4 +++-
2 files changed, 6 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/xe/regs/xe_gt_regs.h b/drivers/gpu/drm/xe/regs/xe_gt_regs.h
index 25014bccd3a6..8c55d766a5a6 100644
--- a/drivers/gpu/drm/xe/regs/xe_gt_regs.h
+++ b/drivers/gpu/drm/xe/regs/xe_gt_regs.h
@@ -572,6 +572,9 @@
#define EU_SYSTOLIC_LIC_THROTTLE_CTL_WITH_LOCK XE_REG_MCR(0xe534)
#define EU_SYSTOLIC_LIC_THROTTLE_CTL_LOCK_BIT REG_BIT(31)
+#define ROW_INSDONE_TDL_GFX XE_REG_MCR(0xe580)
+#define SS_LSC_HDC_IDLE_TDL_GFX XE_REG_MCR(0xe584)
+
#define XEHP_HDC_CHICKEN0 XE_REG_MCR(0xe5f0, XE_REG_OPTION_MASKED)
#define LSC_L1_FLUSH_CTL_3D_DATAPORT_FLUSH_EVENTS_MASK REG_GENMASK(13, 11)
#define DIS_ATOMIC_CHAINING_TYPED_WRITES REG_BIT(3)
diff --git a/drivers/gpu/drm/xe/xe_guc_capture.c b/drivers/gpu/drm/xe/xe_guc_capture.c
index 368769857c9b..a6052da71787 100644
--- a/drivers/gpu/drm/xe/xe_guc_capture.c
+++ b/drivers/gpu/drm/xe/xe_guc_capture.c
@@ -376,7 +376,9 @@ static const struct __ext_steer_reg xehpg_extregs[] = {
{"SC_INSTDONE", XEHPG_SC_INSTDONE},
{"SC_INSTDONE_EXTRA", XEHPG_SC_INSTDONE_EXTRA},
{"SC_INSTDONE_EXTRA2", XEHPG_SC_INSTDONE_EXTRA2},
- {"INSTDONE_GEOM_SVGUNIT", XEHPG_INSTDONE_GEOM_SVGUNIT}
+ {"INSTDONE_GEOM_SVGUNIT", XEHPG_INSTDONE_GEOM_SVGUNIT},
+ {"ROW_INSDONE_TDL_GFX", ROW_INSDONE_TDL_GFX},
+ {"SS_LSC_HDC_IDLE_TDL_GFX", SS_LSC_HDC_IDLE_TDL_GFX}
};
static void __fill_ext_reg(struct __guc_mmio_reg_descr *ext,
--
2.43.0
^ permalink raw reply related [flat|nested] 15+ messages in thread
* [PATCH 6/6] drm/xe: capture L3 node status registers in devcoredump
2026-08-13 13:30 [PATCH 0/6] drm/xe: Capture additional HW register state in devcoredump Nareshkumar Gollakoti
` (4 preceding siblings ...)
2026-08-13 13:30 ` [PATCH 5/6] drm/xe/guc: add TDL gfx registers to capture list Nareshkumar Gollakoti
@ 2026-08-13 13:30 ` Nareshkumar Gollakoti
2026-08-13 14:37 ` sashiko-bot
2026-08-13 13:39 ` ✓ CI.KUnit: success for drm/xe: Capture additional HW register state " Patchwork
` (2 subsequent siblings)
8 siblings, 1 reply; 15+ messages in thread
From: Nareshkumar Gollakoti @ 2026-08-13 13:30 UTC (permalink / raw)
To: intel-xe; +Cc: himal.prasad.ghimiray, Nareshkumar Gollakoti
Add L3_NODE_IDLE and L3STAT_LBCF_GFX register definitions and include
them in the devcoredump snapshot as a node status section.
Extend the register descriptor to mark MCR registers so the snapshot
code can read them through xe_gt_mcr_unicast_read_any(), then print and
free the captured node status registers alongside the existing dump
sections.
Signed-off-by: Nareshkumar Gollakoti <naresh.kumar.g@intel.com>
---
drivers/gpu/drm/xe/regs/xe_gt_regs.h | 3 ++
drivers/gpu/drm/xe/xe_devcoredump.c | 37 ++++++++++++++++++++++-
drivers/gpu/drm/xe/xe_devcoredump_types.h | 2 ++
3 files changed, 41 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/xe/regs/xe_gt_regs.h b/drivers/gpu/drm/xe/regs/xe_gt_regs.h
index 8c55d766a5a6..fdd081791961 100644
--- a/drivers/gpu/drm/xe/regs/xe_gt_regs.h
+++ b/drivers/gpu/drm/xe/regs/xe_gt_regs.h
@@ -430,6 +430,9 @@
#define L3_ESC_MASK REG_BIT(0)
#define L3_ESC(value) REG_FIELD_PREP(L3_ESC_MASK, value)
+#define L3_NODE_IDLE XE_REG(0xb0b0)
+#define L3STAT_LBCF_GFX XE_REG(0xb128)
+
#define XEHP_L3NODEARBCFG XE_REG_MCR(0xb0b4)
#define XEHP_LNESPARE REG_BIT(19)
diff --git a/drivers/gpu/drm/xe/xe_devcoredump.c b/drivers/gpu/drm/xe/xe_devcoredump.c
index 6cc4e3969417..ab8cd7d58964 100644
--- a/drivers/gpu/drm/xe/xe_devcoredump.c
+++ b/drivers/gpu/drm/xe/xe_devcoredump.c
@@ -28,6 +28,7 @@
#include "xe_mmio.h"
#include "regs/xe_gt_regs.h"
#include "regs/xe_guc_regs.h"
+#include "xe_gt_mcr.h"
/**
* DOC: Xe device coredump
@@ -83,6 +84,8 @@ struct xe_reg_desc {
struct xe_reg reg;
/** @name: Name of the register */
const char *name;
+ /** @mcr: mcr type registers */
+ bool mcr;
};
static const struct xe_reg_desc xe_gt_guc_reg_list[] = {
@@ -133,6 +136,11 @@ static const struct xe_reg_desc xe3p_gam_pf_reglist[] = {
{ PAGE_FLTRPTQ_TAIL_GAMCTRL, "PAGE_FLTRPTQ_TAIL_GAMCTRL"},
};
+static const struct xe_reg_desc xe3p_l3_node_reglist[] = {
+ { L3_NODE_IDLE, "L3_NODE_IDLE", .mcr = true },
+ { L3STAT_LBCF_GFX, "L3STAT_LBCF_GFX", .mcr = true },
+};
+
/**
* struct xe_reg_desc_list - Struct for register descriptor list
*
@@ -156,7 +164,12 @@ xe_capture_reg_desc_list(struct xe_gt *gt,
for (i = 0; i < count; i++) {
dst[i].reg = src[i].reg;
- dst[i].value = xe_mmio_read32(>->mmio, src[i].reg);
+ if (src[i].mcr)
+ dst[i].value = xe_gt_mcr_unicast_read_any(gt,
+ XE_REG_MCR
+ (src[i].reg.addr));
+ else
+ dst[i].value = xe_mmio_read32(>->mmio, src[i].reg);
dst[i].name = src[i].name;
}
}
@@ -266,6 +279,19 @@ static struct xe_dbg_reg_snapshot *xe_gam_pf_report_capture(struct xe_gt *gt)
return xe_dbg_reg_snapshot_capture(gt, ®_list);
}
+static struct xe_dbg_reg_snapshot *xe_node_status_capture(struct xe_gt *gt)
+{
+ struct xe_reg_desc_list reg_list;
+
+ if (!xe_dbg_reg_snapshot_is_supported(gt_to_xe(gt)))
+ return NULL;
+
+ reg_list.regs = xe3p_l3_node_reglist;
+ reg_list.num_regs = ARRAY_SIZE(xe3p_l3_node_reglist);
+
+ return xe_dbg_reg_snapshot_capture(gt, ®_list);
+}
+
static struct xe_device *coredump_to_xe(const struct xe_devcoredump *coredump)
{
return container_of(coredump, struct xe_device, devcoredump);
@@ -329,6 +355,9 @@ static ssize_t __xe_devcoredump_read(char *buffer, ssize_t count,
drm_printf(&p, "\n**** GAM PF Report ****\n");
xe_dbg_reg_snapshot_print(&p, ss->gam_pf_report);
+ drm_printf(&p, "\n**** Node Status ****\n");
+ xe_dbg_reg_snapshot_print(&p, ss->ns);
+
drm_puts(&p, "\n**** Contexts ****\n");
xe_guc_exec_queue_snapshot_print(ss->ge, &p);
@@ -378,6 +407,9 @@ static void xe_devcoredump_snapshot_free(struct xe_devcoredump_snapshot *ss)
xe_dbg_reg_snapshot_free(ss->gam_pf_report);
ss->gam_pf_report = NULL;
+ xe_dbg_reg_snapshot_free(ss->ns);
+ ss->ns = NULL;
+
xe_guc_exec_queue_snapshot_free(ss->ge);
ss->ge = NULL;
@@ -582,6 +614,9 @@ static void devcoredump_snapshot(struct xe_devcoredump *coredump,
ss->guc.log = xe_guc_log_snapshot_capture(&guc->log, true);
ss->guc.ct = xe_guc_ct_snapshot_capture(&guc->ct);
ss->gam_pf_report = xe_gam_pf_report_capture(q->gt);
+
+ ss->ns = xe_node_status_capture(q->gt);
+
ss->ge = xe_guc_exec_queue_snapshot_capture(q);
if (job)
ss->job = xe_sched_job_snapshot_capture(job);
diff --git a/drivers/gpu/drm/xe/xe_devcoredump_types.h b/drivers/gpu/drm/xe/xe_devcoredump_types.h
index 893eadd68a3d..e6554aa02429 100644
--- a/drivers/gpu/drm/xe/xe_devcoredump_types.h
+++ b/drivers/gpu/drm/xe/xe_devcoredump_types.h
@@ -88,6 +88,8 @@ struct xe_devcoredump_snapshot {
/** @gam_pf_report: GAM PF report snapshot */
struct xe_dbg_reg_snapshot *gam_pf_report;
+ /** @ns: Node status snapshot */
+ struct xe_dbg_reg_snapshot *ns;
/** @ge: GuC Submission Engine snapshot */
struct xe_guc_submit_exec_queue_snapshot *ge;
--
2.43.0
^ permalink raw reply related [flat|nested] 15+ messages in thread
* ✓ CI.KUnit: success for drm/xe: Capture additional HW register state in devcoredump
2026-08-13 13:30 [PATCH 0/6] drm/xe: Capture additional HW register state in devcoredump Nareshkumar Gollakoti
` (5 preceding siblings ...)
2026-08-13 13:30 ` [PATCH 6/6] drm/xe: capture L3 node status registers in devcoredump Nareshkumar Gollakoti
@ 2026-08-13 13:39 ` Patchwork
2026-08-13 14:27 ` ✓ Xe.CI.BAT: " Patchwork
2026-08-13 15:58 ` ✗ Xe.CI.FULL: failure " Patchwork
8 siblings, 0 replies; 15+ messages in thread
From: Patchwork @ 2026-08-13 13:39 UTC (permalink / raw)
To: Nareshkumar Gollakoti; +Cc: intel-xe
== Series Details ==
Series: drm/xe: Capture additional HW register state in devcoredump
URL : https://patchwork.freedesktop.org/series/172150/
State : success
== Summary ==
+ trap cleanup EXIT
+ /kernel/tools/testing/kunit/kunit.py run --kunitconfig /kernel/drivers/gpu/tests/.kunitconfig
[13:37:18] Configuring KUnit Kernel ...
Generating .config ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
[13:37:22] Building KUnit Kernel ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
Building with:
$ make all compile_commands.json scripts_gdb ARCH=um O=.kunit --jobs=48
[13:37:42] Starting KUnit Kernel (1/1)...
[13:37:42] ============================================================
Running tests with:
$ .kunit/linux kunit.enable=1 mem=1G console=tty kunit_shutdown=halt
[13:37:42] ================= gpu_buddy (13 subtests) ==================
[13:37:42] [PASSED] gpu_test_buddy_alloc_limit
[13:37:42] [PASSED] gpu_test_buddy_alloc_optimistic
[13:37:42] [PASSED] gpu_test_buddy_alloc_pessimistic
[13:37:42] [PASSED] gpu_test_buddy_alloc_pathological
[13:37:42] [PASSED] gpu_test_buddy_alloc_contiguous
[13:37:42] [PASSED] gpu_test_buddy_alloc_clear
[13:37:42] [PASSED] gpu_test_buddy_alloc_range
[13:37:42] [PASSED] gpu_test_buddy_alloc_range_bias
[13:37:42] [PASSED] gpu_test_buddy_fragmentation_performance
[13:37:42] [PASSED] gpu_test_buddy_alloc_exceeds_max_order
[13:37:42] [PASSED] gpu_test_buddy_offset_aligned_allocation
[13:37:42] [PASSED] gpu_test_buddy_subtree_offset_alignment_stress
[13:37:42] [PASSED] gpu_test_buddy_addr_to_block
[13:37:42] ==================== [PASSED] gpu_buddy ====================
[13:37:42] ============================================================
[13:37:42] Testing complete. Ran 13 tests: passed: 13
[13:37:42] Elapsed time: 24.823s total, 4.440s configuring, 19.918s building, 0.442s running
+ /kernel/tools/testing/kunit/kunit.py run --kunitconfig /kernel/drivers/gpu/drm/xe/.kunitconfig
[13:37:43] Configuring KUnit Kernel ...
Regenerating .config ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
[13:37:44] Building KUnit Kernel ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
Building with:
$ make all compile_commands.json scripts_gdb ARCH=um O=.kunit --jobs=48
[13:38:18] Starting KUnit Kernel (1/1)...
[13:38:18] ============================================================
Running tests with:
$ .kunit/linux kunit.enable=1 mem=1G console=tty kunit_shutdown=halt
[13:38:18] ================== guc_buf (11 subtests) ===================
[13:38:18] [PASSED] test_smallest
[13:38:18] [PASSED] test_largest
[13:38:18] [PASSED] test_granular
[13:38:18] [PASSED] test_unique
[13:38:18] [PASSED] test_overlap
[13:38:18] [PASSED] test_reusable
[13:38:18] [PASSED] test_too_big
[13:38:18] [PASSED] test_flush
[13:38:18] [PASSED] test_lookup
[13:38:18] [PASSED] test_data
[13:38:18] [PASSED] test_class
[13:38:18] ===================== [PASSED] guc_buf =====================
[13:38:18] =================== guc_dbm (7 subtests) ===================
[13:38:18] [PASSED] test_empty
[13:38:18] [PASSED] test_default
[13:38:18] ======================== test_size ========================
[13:38:18] [PASSED] 4
[13:38:18] [PASSED] 8
[13:38:18] [PASSED] 32
[13:38:18] [PASSED] 256
[13:38:18] ==================== [PASSED] test_size ====================
[13:38:18] ======================= test_reuse ========================
[13:38:18] [PASSED] 4
[13:38:18] [PASSED] 8
[13:38:18] [PASSED] 32
[13:38:18] [PASSED] 256
[13:38:18] =================== [PASSED] test_reuse ====================
[13:38:18] =================== test_range_overlap ====================
[13:38:18] [PASSED] 4
[13:38:18] [PASSED] 8
[13:38:18] [PASSED] 32
[13:38:18] [PASSED] 256
[13:38:18] =============== [PASSED] test_range_overlap ================
[13:38:18] =================== test_range_compact ====================
[13:38:18] [PASSED] 4
[13:38:18] [PASSED] 8
[13:38:18] [PASSED] 32
[13:38:18] [PASSED] 256
[13:38:18] =============== [PASSED] test_range_compact ================
[13:38:18] ==================== test_range_spare =====================
[13:38:18] [PASSED] 4
[13:38:18] [PASSED] 8
[13:38:18] [PASSED] 32
[13:38:18] [PASSED] 256
[13:38:18] ================ [PASSED] test_range_spare =================
[13:38:18] ===================== [PASSED] guc_dbm =====================
[13:38:18] =================== guc_idm (6 subtests) ===================
[13:38:18] [PASSED] bad_init
[13:38:18] [PASSED] no_init
[13:38:18] [PASSED] init_fini
[13:38:18] [PASSED] check_used
[13:38:18] [PASSED] check_quota
[13:38:18] [PASSED] check_all
[13:38:18] ===================== [PASSED] guc_idm =====================
[13:38:18] =============== guc_klv_helpers (9 subtests) ===============
[13:38:18] [PASSED] test_count
[13:38:18] [PASSED] test_encode_u32
[13:38:18] [PASSED] test_encode_u64
[13:38:18] [PASSED] test_encode_string
[13:38:18] [PASSED] test_encode_object_raw
[13:38:18] [PASSED] test_encode_object_klv
[13:38:18] [PASSED] test_encode_object_nested
[13:38:18] [PASSED] test_encode_object_basic
[13:38:18] [PASSED] test_print
[13:38:18] ================= [PASSED] guc_klv_helpers =================
[13:38:18] ================== no_relay (3 subtests) ===================
[13:38:18] [PASSED] xe_drops_guc2pf_if_not_ready
[13:38:18] [PASSED] xe_drops_guc2vf_if_not_ready
[13:38:18] [PASSED] xe_rejects_send_if_not_ready
[13:38:18] ==================== [PASSED] no_relay =====================
[13:38:18] ================== pf_relay (14 subtests) ==================
[13:38:18] [PASSED] pf_rejects_guc2pf_too_short
[13:38:18] [PASSED] pf_rejects_guc2pf_too_long
[13:38:18] [PASSED] pf_rejects_guc2pf_no_payload
[13:38:18] [PASSED] pf_fails_no_payload
[13:38:18] [PASSED] pf_fails_bad_origin
[13:38:18] [PASSED] pf_fails_bad_type
[13:38:18] [PASSED] pf_txn_reports_error
[13:38:18] [PASSED] pf_txn_sends_pf2guc
[13:38:18] [PASSED] pf_sends_pf2guc
[13:38:18] [SKIPPED] pf_loopback_nop (requires CONFIG_DRM_XE_DEBUG_SRIOV)
[13:38:18] [SKIPPED] pf_loopback_echo (requires CONFIG_DRM_XE_DEBUG_SRIOV)
[13:38:18] [SKIPPED] pf_loopback_fail (requires CONFIG_DRM_XE_DEBUG_SRIOV)
[13:38:18] [SKIPPED] pf_loopback_busy (requires CONFIG_DRM_XE_DEBUG_SRIOV)
[13:38:18] [SKIPPED] pf_loopback_retry (requires CONFIG_DRM_XE_DEBUG_SRIOV)
[13:38:18] ==================== [PASSED] pf_relay =====================
[13:38:18] ================== vf_relay (3 subtests) ===================
[13:38:18] [PASSED] vf_rejects_guc2vf_too_short
[13:38:18] [PASSED] vf_rejects_guc2vf_too_long
[13:38:18] [PASSED] vf_rejects_guc2vf_no_payload
[13:38:18] ==================== [PASSED] vf_relay =====================
[13:38:18] ================ pf_gt_config (9 subtests) =================
[13:38:18] [PASSED] fair_contexts_1vf
[13:38:18] [PASSED] fair_doorbells_1vf
[13:38:18] [PASSED] fair_ggtt_1vf
[13:38:18] ====================== fair_vram_1vf ======================
[13:38:18] [PASSED] 3.50 GiB
[13:38:18] [PASSED] 11.5 GiB
[13:38:18] [PASSED] 15.5 GiB
[13:38:18] [PASSED] 31.5 GiB
[13:38:18] [PASSED] 63.5 GiB
[13:38:18] [PASSED] 1.91 GiB
[13:38:18] ================== [PASSED] fair_vram_1vf ==================
[13:38:18] ================ fair_vram_1vf_admin_only =================
[13:38:18] [PASSED] 3.50 GiB
[13:38:18] [PASSED] 11.5 GiB
[13:38:18] [PASSED] 15.5 GiB
[13:38:18] [PASSED] 31.5 GiB
[13:38:18] [PASSED] 63.5 GiB
[13:38:18] [PASSED] 1.91 GiB
[13:38:18] ============ [PASSED] fair_vram_1vf_admin_only =============
[13:38:18] ====================== fair_contexts ======================
[13:38:18] [PASSED] 1 VF
[13:38:18] [PASSED] 2 VFs
[13:38:18] [PASSED] 3 VFs
[13:38:18] [PASSED] 4 VFs
[13:38:18] [PASSED] 5 VFs
[13:38:18] [PASSED] 6 VFs
[13:38:18] [PASSED] 7 VFs
[13:38:18] [PASSED] 8 VFs
[13:38:18] [PASSED] 9 VFs
[13:38:18] [PASSED] 10 VFs
[13:38:18] [PASSED] 11 VFs
[13:38:18] [PASSED] 12 VFs
[13:38:18] [PASSED] 13 VFs
[13:38:18] [PASSED] 14 VFs
[13:38:18] [PASSED] 15 VFs
[13:38:18] [PASSED] 16 VFs
[13:38:18] [PASSED] 17 VFs
[13:38:18] [PASSED] 18 VFs
[13:38:18] [PASSED] 19 VFs
[13:38:18] [PASSED] 20 VFs
[13:38:18] [PASSED] 21 VFs
[13:38:18] [PASSED] 22 VFs
[13:38:18] [PASSED] 23 VFs
[13:38:18] [PASSED] 24 VFs
[13:38:18] [PASSED] 25 VFs
[13:38:18] [PASSED] 26 VFs
[13:38:18] [PASSED] 27 VFs
[13:38:18] [PASSED] 28 VFs
[13:38:18] [PASSED] 29 VFs
[13:38:18] [PASSED] 30 VFs
[13:38:18] [PASSED] 31 VFs
[13:38:18] [PASSED] 32 VFs
[13:38:18] [PASSED] 33 VFs
[13:38:18] [PASSED] 34 VFs
[13:38:18] [PASSED] 35 VFs
[13:38:18] [PASSED] 36 VFs
[13:38:18] [PASSED] 37 VFs
[13:38:18] [PASSED] 38 VFs
[13:38:18] [PASSED] 39 VFs
[13:38:18] [PASSED] 40 VFs
[13:38:18] [PASSED] 41 VFs
[13:38:18] [PASSED] 42 VFs
[13:38:18] [PASSED] 43 VFs
[13:38:18] [PASSED] 44 VFs
[13:38:18] [PASSED] 45 VFs
[13:38:18] [PASSED] 46 VFs
[13:38:18] [PASSED] 47 VFs
[13:38:18] [PASSED] 48 VFs
[13:38:18] [PASSED] 49 VFs
[13:38:18] [PASSED] 50 VFs
[13:38:18] [PASSED] 51 VFs
[13:38:18] [PASSED] 52 VFs
[13:38:18] [PASSED] 53 VFs
[13:38:18] [PASSED] 54 VFs
[13:38:18] [PASSED] 55 VFs
[13:38:18] [PASSED] 56 VFs
[13:38:18] [PASSED] 57 VFs
[13:38:18] [PASSED] 58 VFs
[13:38:18] [PASSED] 59 VFs
[13:38:18] [PASSED] 60 VFs
[13:38:18] [PASSED] 61 VFs
[13:38:18] [PASSED] 62 VFs
[13:38:18] [PASSED] 63 VFs
[13:38:18] ================== [PASSED] fair_contexts ==================
[13:38:18] ===================== fair_doorbells ======================
[13:38:18] [PASSED] 1 VF
[13:38:18] [PASSED] 2 VFs
[13:38:18] [PASSED] 3 VFs
[13:38:18] [PASSED] 4 VFs
[13:38:18] [PASSED] 5 VFs
[13:38:18] [PASSED] 6 VFs
[13:38:18] [PASSED] 7 VFs
[13:38:18] [PASSED] 8 VFs
[13:38:18] [PASSED] 9 VFs
[13:38:18] [PASSED] 10 VFs
[13:38:18] [PASSED] 11 VFs
[13:38:18] [PASSED] 12 VFs
[13:38:18] [PASSED] 13 VFs
[13:38:18] [PASSED] 14 VFs
[13:38:18] [PASSED] 15 VFs
[13:38:18] [PASSED] 16 VFs
[13:38:18] [PASSED] 17 VFs
[13:38:18] [PASSED] 18 VFs
[13:38:18] [PASSED] 19 VFs
[13:38:18] [PASSED] 20 VFs
[13:38:18] [PASSED] 21 VFs
[13:38:18] [PASSED] 22 VFs
[13:38:18] [PASSED] 23 VFs
[13:38:18] [PASSED] 24 VFs
[13:38:18] [PASSED] 25 VFs
[13:38:18] [PASSED] 26 VFs
[13:38:18] [PASSED] 27 VFs
[13:38:18] [PASSED] 28 VFs
[13:38:18] [PASSED] 29 VFs
[13:38:18] [PASSED] 30 VFs
[13:38:18] [PASSED] 31 VFs
[13:38:18] [PASSED] 32 VFs
[13:38:18] [PASSED] 33 VFs
[13:38:18] [PASSED] 34 VFs
[13:38:18] [PASSED] 35 VFs
[13:38:18] [PASSED] 36 VFs
[13:38:18] [PASSED] 37 VFs
[13:38:18] [PASSED] 38 VFs
[13:38:18] [PASSED] 39 VFs
[13:38:18] [PASSED] 40 VFs
[13:38:18] [PASSED] 41 VFs
[13:38:18] [PASSED] 42 VFs
[13:38:18] [PASSED] 43 VFs
[13:38:18] [PASSED] 44 VFs
[13:38:18] [PASSED] 45 VFs
[13:38:18] [PASSED] 46 VFs
[13:38:18] [PASSED] 47 VFs
[13:38:18] [PASSED] 48 VFs
[13:38:18] [PASSED] 49 VFs
[13:38:18] [PASSED] 50 VFs
[13:38:18] [PASSED] 51 VFs
[13:38:18] [PASSED] 52 VFs
[13:38:18] [PASSED] 53 VFs
[13:38:18] [PASSED] 54 VFs
[13:38:18] [PASSED] 55 VFs
[13:38:18] [PASSED] 56 VFs
[13:38:18] [PASSED] 57 VFs
[13:38:18] [PASSED] 58 VFs
[13:38:18] [PASSED] 59 VFs
[13:38:18] [PASSED] 60 VFs
[13:38:18] [PASSED] 61 VFs
[13:38:18] [PASSED] 62 VFs
[13:38:18] [PASSED] 63 VFs
[13:38:18] ================= [PASSED] fair_doorbells ==================
[13:38:18] ======================== fair_ggtt ========================
[13:38:18] [PASSED] 1 VF
[13:38:18] [PASSED] 2 VFs
[13:38:18] [PASSED] 3 VFs
[13:38:18] [PASSED] 4 VFs
[13:38:18] [PASSED] 5 VFs
[13:38:18] [PASSED] 6 VFs
[13:38:18] [PASSED] 7 VFs
[13:38:18] [PASSED] 8 VFs
[13:38:18] [PASSED] 9 VFs
[13:38:18] [PASSED] 10 VFs
[13:38:18] [PASSED] 11 VFs
[13:38:18] [PASSED] 12 VFs
[13:38:18] [PASSED] 13 VFs
[13:38:18] [PASSED] 14 VFs
[13:38:18] [PASSED] 15 VFs
[13:38:18] [PASSED] 16 VFs
[13:38:18] [PASSED] 17 VFs
[13:38:18] [PASSED] 18 VFs
[13:38:18] [PASSED] 19 VFs
[13:38:18] [PASSED] 20 VFs
[13:38:18] [PASSED] 21 VFs
[13:38:18] [PASSED] 22 VFs
[13:38:18] [PASSED] 23 VFs
[13:38:18] [PASSED] 24 VFs
[13:38:18] [PASSED] 25 VFs
[13:38:18] [PASSED] 26 VFs
[13:38:18] [PASSED] 27 VFs
[13:38:18] [PASSED] 28 VFs
[13:38:18] [PASSED] 29 VFs
[13:38:18] [PASSED] 30 VFs
[13:38:18] [PASSED] 31 VFs
[13:38:18] [PASSED] 32 VFs
[13:38:18] [PASSED] 33 VFs
[13:38:18] [PASSED] 34 VFs
[13:38:18] [PASSED] 35 VFs
[13:38:18] [PASSED] 36 VFs
[13:38:18] [PASSED] 37 VFs
[13:38:18] [PASSED] 38 VFs
[13:38:18] [PASSED] 39 VFs
[13:38:18] [PASSED] 40 VFs
[13:38:18] [PASSED] 41 VFs
[13:38:18] [PASSED] 42 VFs
[13:38:18] [PASSED] 43 VFs
[13:38:18] [PASSED] 44 VFs
[13:38:18] [PASSED] 45 VFs
[13:38:18] [PASSED] 46 VFs
[13:38:18] [PASSED] 47 VFs
[13:38:18] [PASSED] 48 VFs
[13:38:18] [PASSED] 49 VFs
[13:38:18] [PASSED] 50 VFs
[13:38:18] [PASSED] 51 VFs
[13:38:18] [PASSED] 52 VFs
[13:38:18] [PASSED] 53 VFs
[13:38:18] [PASSED] 54 VFs
[13:38:18] [PASSED] 55 VFs
[13:38:18] [PASSED] 56 VFs
[13:38:18] [PASSED] 57 VFs
[13:38:18] [PASSED] 58 VFs
[13:38:18] [PASSED] 59 VFs
[13:38:18] [PASSED] 60 VFs
[13:38:18] [PASSED] 61 VFs
[13:38:18] [PASSED] 62 VFs
[13:38:18] [PASSED] 63 VFs
[13:38:18] ==================== [PASSED] fair_ggtt ====================
[13:38:18] ======================== fair_vram ========================
[13:38:18] [PASSED] 1 VF
[13:38:18] [PASSED] 2 VFs
[13:38:18] [PASSED] 3 VFs
[13:38:18] [PASSED] 4 VFs
[13:38:18] [PASSED] 5 VFs
[13:38:18] [PASSED] 6 VFs
[13:38:18] [PASSED] 7 VFs
[13:38:18] [PASSED] 8 VFs
[13:38:18] [PASSED] 9 VFs
[13:38:18] [PASSED] 10 VFs
[13:38:18] [PASSED] 11 VFs
[13:38:18] [PASSED] 12 VFs
[13:38:18] [PASSED] 13 VFs
[13:38:18] [PASSED] 14 VFs
[13:38:18] [PASSED] 15 VFs
[13:38:18] [PASSED] 16 VFs
[13:38:18] [PASSED] 17 VFs
[13:38:18] [PASSED] 18 VFs
[13:38:18] [PASSED] 19 VFs
[13:38:18] [PASSED] 20 VFs
[13:38:18] [PASSED] 21 VFs
[13:38:18] [PASSED] 22 VFs
[13:38:18] [PASSED] 23 VFs
[13:38:18] [PASSED] 24 VFs
[13:38:18] [PASSED] 25 VFs
[13:38:18] [PASSED] 26 VFs
[13:38:18] [PASSED] 27 VFs
[13:38:18] [PASSED] 28 VFs
[13:38:18] [PASSED] 29 VFs
[13:38:18] [PASSED] 30 VFs
[13:38:18] [PASSED] 31 VFs
[13:38:18] [PASSED] 32 VFs
[13:38:18] [PASSED] 33 VFs
[13:38:18] [PASSED] 34 VFs
[13:38:18] [PASSED] 35 VFs
[13:38:18] [PASSED] 36 VFs
[13:38:18] [PASSED] 37 VFs
[13:38:18] [PASSED] 38 VFs
[13:38:18] [PASSED] 39 VFs
[13:38:18] [PASSED] 40 VFs
[13:38:18] [PASSED] 41 VFs
[13:38:18] [PASSED] 42 VFs
[13:38:18] [PASSED] 43 VFs
[13:38:18] [PASSED] 44 VFs
[13:38:18] [PASSED] 45 VFs
[13:38:18] [PASSED] 46 VFs
[13:38:18] [PASSED] 47 VFs
[13:38:18] [PASSED] 48 VFs
[13:38:18] [PASSED] 49 VFs
[13:38:18] [PASSED] 50 VFs
[13:38:18] [PASSED] 51 VFs
[13:38:18] [PASSED] 52 VFs
[13:38:18] [PASSED] 53 VFs
[13:38:18] [PASSED] 54 VFs
[13:38:18] [PASSED] 55 VFs
[13:38:18] [PASSED] 56 VFs
[13:38:18] [PASSED] 57 VFs
[13:38:18] [PASSED] 58 VFs
[13:38:18] [PASSED] 59 VFs
[13:38:18] [PASSED] 60 VFs
[13:38:18] [PASSED] 61 VFs
[13:38:18] [PASSED] 62 VFs
[13:38:18] [PASSED] 63 VFs
[13:38:18] ==================== [PASSED] fair_vram ====================
[13:38:18] ================== [PASSED] pf_gt_config ===================
[13:38:18] ===================== lmtt (1 subtest) =====================
[13:38:18] ======================== test_ops =========================
[13:38:18] [PASSED] 2-level
[13:38:18] [PASSED] multi-level
[13:38:18] ==================== [PASSED] test_ops =====================
[13:38:18] ====================== [PASSED] lmtt =======================
[13:38:18] ================= sriov_packet (1 subtest) =================
[13:38:18] [PASSED] test_descriptor_init
[13:38:18] ================== [PASSED] sriov_packet ===================
[13:38:18] ================= pf_service (11 subtests) =================
[13:38:18] [PASSED] pf_negotiate_any
[13:38:18] [PASSED] pf_negotiate_base_match
[13:38:18] [PASSED] pf_negotiate_base_newer
[13:38:18] [PASSED] pf_negotiate_base_next
[13:38:18] [SKIPPED] pf_negotiate_base_older (no older minor)
[13:38:18] [PASSED] pf_negotiate_base_prev
[13:38:18] [PASSED] pf_negotiate_latest_match
[13:38:18] [PASSED] pf_negotiate_latest_newer
[13:38:18] [PASSED] pf_negotiate_latest_next
[13:38:18] [SKIPPED] pf_negotiate_latest_older (no older minor)
[13:38:18] [SKIPPED] pf_negotiate_latest_prev (no prev major)
[13:38:18] =================== [PASSED] pf_service ====================
[13:38:18] ================= xe_guc_g2g (2 subtests) ==================
[13:38:18] ============== xe_live_guc_g2g_kunit_default ==============
[13:38:18] ========= [SKIPPED] xe_live_guc_g2g_kunit_default ==========
[13:38:18] ============== xe_live_guc_g2g_kunit_allmem ===============
[13:38:18] ========== [SKIPPED] xe_live_guc_g2g_kunit_allmem ==========
[13:38:18] =================== [SKIPPED] xe_guc_g2g ===================
[13:38:18] =================== xe_mocs (2 subtests) ===================
[13:38:18] ================ xe_live_mocs_kernel_kunit ================
[13:38:18] =========== [SKIPPED] xe_live_mocs_kernel_kunit ============
[13:38:18] ================ xe_live_mocs_reset_kunit =================
[13:38:18] ============ [SKIPPED] xe_live_mocs_reset_kunit ============
[13:38:18] ==================== [SKIPPED] xe_mocs =====================
[13:38:18] ================= xe_migrate (2 subtests) ==================
[13:38:18] ================= xe_migrate_sanity_kunit =================
[13:38:18] ============ [SKIPPED] xe_migrate_sanity_kunit =============
[13:38:18] ================== xe_validate_ccs_kunit ==================
[13:38:18] ============= [SKIPPED] xe_validate_ccs_kunit ==============
[13:38:18] =================== [SKIPPED] xe_migrate ===================
[13:38:18] ================== xe_dma_buf (1 subtest) ==================
[13:38:18] ==================== xe_dma_buf_kunit =====================
[13:38:18] ================ [SKIPPED] xe_dma_buf_kunit ================
[13:38:18] =================== [SKIPPED] xe_dma_buf ===================
[13:38:18] ================= xe_bo_shrink (1 subtest) =================
[13:38:18] =================== xe_bo_shrink_kunit ====================
[13:38:18] =============== [SKIPPED] xe_bo_shrink_kunit ===============
[13:38:18] ================== [SKIPPED] xe_bo_shrink ==================
[13:38:18] ==================== xe_bo (2 subtests) ====================
[13:38:18] ================== xe_ccs_migrate_kunit ===================
[13:38:18] ============== [SKIPPED] xe_ccs_migrate_kunit ==============
[13:38:18] ==================== xe_bo_evict_kunit ====================
[13:38:18] =============== [SKIPPED] xe_bo_evict_kunit ================
[13:38:18] ===================== [SKIPPED] xe_bo ======================
[13:38:18] ==================== args (13 subtests) ====================
[13:38:18] [PASSED] count_args_test
[13:38:18] [PASSED] call_args_example
[13:38:18] [PASSED] call_args_test
[13:38:18] [PASSED] drop_first_arg_example
[13:38:18] [PASSED] drop_first_arg_test
[13:38:18] [PASSED] first_arg_example
[13:38:18] [PASSED] first_arg_test
[13:38:18] [PASSED] last_arg_example
[13:38:18] [PASSED] last_arg_test
[13:38:18] [PASSED] pick_arg_example
[13:38:18] [PASSED] if_args_example
[13:38:18] [PASSED] if_args_test
[13:38:18] [PASSED] sep_comma_example
[13:38:18] ====================== [PASSED] args =======================
[13:38:18] =================== xe_pci (3 subtests) ====================
[13:38:18] ==================== check_graphics_ip ====================
[13:38:18] [PASSED] 12.00 Xe_LP
[13:38:18] [PASSED] 12.10 Xe_LP+
[13:38:18] [PASSED] 12.55 Xe_HPG
[13:38:18] [PASSED] 12.60 Xe_HPC
[13:38:18] [PASSED] 12.70 Xe_LPG
[13:38:18] [PASSED] 12.71 Xe_LPG
[13:38:18] [PASSED] 12.74 Xe_LPG+
[13:38:18] [PASSED] 20.01 Xe2_HPG
[13:38:18] [PASSED] 20.02 Xe2_HPG
[13:38:18] [PASSED] 20.04 Xe2_LPG
[13:38:18] [PASSED] 30.00 Xe3_LPG
[13:38:18] [PASSED] 30.01 Xe3_LPG
[13:38:18] [PASSED] 30.03 Xe3_LPG
[13:38:18] [PASSED] 30.04 Xe3_LPG
[13:38:18] [PASSED] 30.05 Xe3_LPG
[13:38:18] [PASSED] 35.10 Xe3p_LPG
[13:38:18] [PASSED] 35.11 Xe3p_XPC
[13:38:18] ================ [PASSED] check_graphics_ip ================
[13:38:18] ===================== check_media_ip ======================
[13:38:18] [PASSED] 12.00 Xe_M
[13:38:18] [PASSED] 12.55 Xe_HPM
[13:38:18] [PASSED] 13.00 Xe_LPM+
[13:38:18] [PASSED] 13.01 Xe2_HPM
[13:38:18] [PASSED] 20.00 Xe2_LPM
[13:38:18] [PASSED] 30.00 Xe3_LPM
[13:38:18] [PASSED] 30.02 Xe3_LPM
[13:38:18] [PASSED] 35.00 Xe3p_LPM
[13:38:18] [PASSED] 35.03 Xe3p_HPM
[13:38:18] ================= [PASSED] check_media_ip ==================
[13:38:18] =================== check_platform_desc ===================
[13:38:18] [PASSED] 0x9A60 (TIGERLAKE)
[13:38:18] [PASSED] 0x9A68 (TIGERLAKE)
[13:38:18] [PASSED] 0x9A70 (TIGERLAKE)
[13:38:18] [PASSED] 0x9A40 (TIGERLAKE)
[13:38:18] [PASSED] 0x9A49 (TIGERLAKE)
[13:38:18] [PASSED] 0x9A59 (TIGERLAKE)
[13:38:18] [PASSED] 0x9A78 (TIGERLAKE)
[13:38:18] [PASSED] 0x9AC0 (TIGERLAKE)
[13:38:18] [PASSED] 0x9AC9 (TIGERLAKE)
[13:38:18] [PASSED] 0x9AD9 (TIGERLAKE)
[13:38:18] [PASSED] 0x9AF8 (TIGERLAKE)
[13:38:18] [PASSED] 0x4C80 (ROCKETLAKE)
[13:38:18] [PASSED] 0x4C8A (ROCKETLAKE)
[13:38:18] [PASSED] 0x4C8B (ROCKETLAKE)
[13:38:18] [PASSED] 0x4C8C (ROCKETLAKE)
[13:38:18] [PASSED] 0x4C90 (ROCKETLAKE)
[13:38:18] [PASSED] 0x4C9A (ROCKETLAKE)
[13:38:18] [PASSED] 0x4680 (ALDERLAKE_S)
[13:38:18] [PASSED] 0x4682 (ALDERLAKE_S)
[13:38:18] [PASSED] 0x4688 (ALDERLAKE_S)
[13:38:18] [PASSED] 0x468A (ALDERLAKE_S)
[13:38:18] [PASSED] 0x468B (ALDERLAKE_S)
[13:38:18] [PASSED] 0x4690 (ALDERLAKE_S)
[13:38:18] [PASSED] 0x4692 (ALDERLAKE_S)
[13:38:18] [PASSED] 0x4693 (ALDERLAKE_S)
[13:38:18] [PASSED] 0x46A0 (ALDERLAKE_P)
[13:38:18] [PASSED] 0x46A1 (ALDERLAKE_P)
[13:38:18] [PASSED] 0x46A2 (ALDERLAKE_P)
[13:38:18] [PASSED] 0x46A3 (ALDERLAKE_P)
[13:38:18] [PASSED] 0x46A6 (ALDERLAKE_P)
[13:38:18] [PASSED] 0x46A8 (ALDERLAKE_P)
[13:38:18] [PASSED] 0x46AA (ALDERLAKE_P)
[13:38:18] [PASSED] 0x462A (ALDERLAKE_P)
[13:38:18] [PASSED] 0x4626 (ALDERLAKE_P)
[13:38:18] [PASSED] 0x4628 (ALDERLAKE_P)
[13:38:18] [PASSED] 0x46B0 (ALDERLAKE_P)
[13:38:18] [PASSED] 0x46B1 (ALDERLAKE_P)
[13:38:18] [PASSED] 0x46B2 (ALDERLAKE_P)
[13:38:18] [PASSED] 0x46B3 (ALDERLAKE_P)
[13:38:18] [PASSED] 0x46C0 (ALDERLAKE_P)
[13:38:18] [PASSED] 0x46C1 (ALDERLAKE_P)
[13:38:18] [PASSED] 0x46C2 (ALDERLAKE_P)
[13:38:18] [PASSED] 0x46C3 (ALDERLAKE_P)
[13:38:18] [PASSED] 0x46D0 (ALDERLAKE_N)
[13:38:18] [PASSED] 0x46D1 (ALDERLAKE_N)
[13:38:18] [PASSED] 0x46D2 (ALDERLAKE_N)
[13:38:18] [PASSED] 0x46D3 (ALDERLAKE_N)
[13:38:18] [PASSED] 0x46D4 (ALDERLAKE_N)
[13:38:18] [PASSED] 0xA721 (ALDERLAKE_P)
[13:38:18] [PASSED] 0xA7A1 (ALDERLAKE_P)
[13:38:18] [PASSED] 0xA7A9 (ALDERLAKE_P)
[13:38:18] [PASSED] 0xA7AC (ALDERLAKE_P)
[13:38:18] [PASSED] 0xA7AD (ALDERLAKE_P)
[13:38:18] [PASSED] 0xA720 (ALDERLAKE_P)
[13:38:18] [PASSED] 0xA7A0 (ALDERLAKE_P)
[13:38:18] [PASSED] 0xA7A8 (ALDERLAKE_P)
[13:38:18] [PASSED] 0xA7AA (ALDERLAKE_P)
[13:38:18] [PASSED] 0xA7AB (ALDERLAKE_P)
[13:38:18] [PASSED] 0xA780 (ALDERLAKE_S)
[13:38:18] [PASSED] 0xA781 (ALDERLAKE_S)
[13:38:18] [PASSED] 0xA782 (ALDERLAKE_S)
[13:38:18] [PASSED] 0xA783 (ALDERLAKE_S)
[13:38:18] [PASSED] 0xA788 (ALDERLAKE_S)
[13:38:18] [PASSED] 0xA789 (ALDERLAKE_S)
[13:38:18] [PASSED] 0xA78A (ALDERLAKE_S)
[13:38:18] [PASSED] 0xA78B (ALDERLAKE_S)
[13:38:18] [PASSED] 0x4905 (DG1)
[13:38:18] [PASSED] 0x4906 (DG1)
[13:38:18] [PASSED] 0x4907 (DG1)
[13:38:18] [PASSED] 0x4908 (DG1)
[13:38:18] [PASSED] 0x4909 (DG1)
[13:38:18] [PASSED] 0x56C0 (DG2)
[13:38:18] [PASSED] 0x56C2 (DG2)
[13:38:18] [PASSED] 0x56C1 (DG2)
[13:38:18] [PASSED] 0x7D51 (METEORLAKE)
[13:38:18] [PASSED] 0x7DD1 (METEORLAKE)
[13:38:18] [PASSED] 0x7D41 (METEORLAKE)
[13:38:18] [PASSED] 0x7D67 (METEORLAKE)
[13:38:18] [PASSED] 0xB640 (METEORLAKE)
[13:38:18] [PASSED] 0x56A0 (DG2)
[13:38:18] [PASSED] 0x56A1 (DG2)
[13:38:18] [PASSED] 0x56A2 (DG2)
[13:38:18] [PASSED] 0x56BE (DG2)
[13:38:18] [PASSED] 0x56BF (DG2)
[13:38:18] [PASSED] 0x5690 (DG2)
[13:38:18] [PASSED] 0x5691 (DG2)
[13:38:18] [PASSED] 0x5692 (DG2)
[13:38:18] [PASSED] 0x56A5 (DG2)
[13:38:18] [PASSED] 0x56A6 (DG2)
[13:38:18] [PASSED] 0x56B0 (DG2)
[13:38:18] [PASSED] 0x56B1 (DG2)
[13:38:18] [PASSED] 0x56BA (DG2)
[13:38:18] [PASSED] 0x56BB (DG2)
[13:38:18] [PASSED] 0x56BC (DG2)
[13:38:18] [PASSED] 0x56BD (DG2)
[13:38:18] [PASSED] 0x5693 (DG2)
[13:38:18] [PASSED] 0x5694 (DG2)
[13:38:18] [PASSED] 0x5695 (DG2)
[13:38:18] [PASSED] 0x56A3 (DG2)
[13:38:18] [PASSED] 0x56A4 (DG2)
[13:38:18] [PASSED] 0x56B2 (DG2)
[13:38:18] [PASSED] 0x56B3 (DG2)
[13:38:18] [PASSED] 0x5696 (DG2)
[13:38:18] [PASSED] 0x5697 (DG2)
[13:38:18] [PASSED] 0xB69 (PVC)
[13:38:18] [PASSED] 0xB6E (PVC)
[13:38:18] [PASSED] 0xBD4 (PVC)
[13:38:18] [PASSED] 0xBD5 (PVC)
[13:38:18] [PASSED] 0xBD6 (PVC)
[13:38:18] [PASSED] 0xBD7 (PVC)
[13:38:18] [PASSED] 0xBD8 (PVC)
[13:38:18] [PASSED] 0xBD9 (PVC)
[13:38:18] [PASSED] 0xBDA (PVC)
[13:38:18] [PASSED] 0xBDB (PVC)
[13:38:18] [PASSED] 0xBE0 (PVC)
[13:38:18] [PASSED] 0xBE1 (PVC)
[13:38:18] [PASSED] 0xBE5 (PVC)
[13:38:18] [PASSED] 0x7D40 (METEORLAKE)
[13:38:18] [PASSED] 0x7D45 (METEORLAKE)
[13:38:18] [PASSED] 0x7D55 (METEORLAKE)
[13:38:18] [PASSED] 0x7D60 (METEORLAKE)
[13:38:18] [PASSED] 0x7DD5 (METEORLAKE)
[13:38:18] [PASSED] 0x6420 (LUNARLAKE)
[13:38:18] [PASSED] 0x64A0 (LUNARLAKE)
[13:38:18] [PASSED] 0x64B0 (LUNARLAKE)
[13:38:18] [PASSED] 0xE202 (BATTLEMAGE)
[13:38:18] [PASSED] 0xE209 (BATTLEMAGE)
[13:38:18] [PASSED] 0xE20B (BATTLEMAGE)
[13:38:18] [PASSED] 0xE20C (BATTLEMAGE)
[13:38:18] [PASSED] 0xE20D (BATTLEMAGE)
[13:38:18] [PASSED] 0xE210 (BATTLEMAGE)
[13:38:18] [PASSED] 0xE211 (BATTLEMAGE)
[13:38:18] [PASSED] 0xE212 (BATTLEMAGE)
[13:38:18] [PASSED] 0xE216 (BATTLEMAGE)
[13:38:18] [PASSED] 0xE220 (BATTLEMAGE)
[13:38:18] [PASSED] 0xE221 (BATTLEMAGE)
[13:38:18] [PASSED] 0xE222 (BATTLEMAGE)
[13:38:18] [PASSED] 0xE223 (BATTLEMAGE)
[13:38:18] [PASSED] 0xB080 (PANTHERLAKE)
[13:38:18] [PASSED] 0xB081 (PANTHERLAKE)
[13:38:18] [PASSED] 0xB082 (PANTHERLAKE)
[13:38:18] [PASSED] 0xB083 (PANTHERLAKE)
[13:38:18] [PASSED] 0xB084 (PANTHERLAKE)
[13:38:18] [PASSED] 0xB085 (PANTHERLAKE)
[13:38:18] [PASSED] 0xB086 (PANTHERLAKE)
[13:38:18] [PASSED] 0xB087 (PANTHERLAKE)
[13:38:18] [PASSED] 0xB08F (PANTHERLAKE)
[13:38:18] [PASSED] 0xB090 (PANTHERLAKE)
[13:38:18] [PASSED] 0xB0A0 (PANTHERLAKE)
[13:38:18] [PASSED] 0xB0B0 (PANTHERLAKE)
[13:38:18] [PASSED] 0xFD80 (PANTHERLAKE)
[13:38:18] [PASSED] 0xFD81 (PANTHERLAKE)
[13:38:18] [PASSED] 0xD740 (NOVALAKE_S)
[13:38:18] [PASSED] 0xD741 (NOVALAKE_S)
[13:38:18] [PASSED] 0xD742 (NOVALAKE_S)
[13:38:18] [PASSED] 0xD743 (NOVALAKE_S)
[13:38:18] [PASSED] 0xD745 (NOVALAKE_S)
[13:38:18] [PASSED] 0xD74A (NOVALAKE_S)
[13:38:18] [PASSED] 0xD74B (NOVALAKE_S)
[13:38:18] [PASSED] 0x674C (CRESCENTISLAND)
[13:38:18] [PASSED] 0x674D (CRESCENTISLAND)
[13:38:18] [PASSED] 0x674E (CRESCENTISLAND)
[13:38:18] [PASSED] 0x674F (CRESCENTISLAND)
[13:38:18] [PASSED] 0x6750 (CRESCENTISLAND)
[13:38:18] [PASSED] 0xD750 (NOVALAKE_P)
[13:38:18] [PASSED] 0xD751 (NOVALAKE_P)
[13:38:18] [PASSED] 0xD752 (NOVALAKE_P)
[13:38:18] [PASSED] 0xD753 (NOVALAKE_P)
[13:38:18] [PASSED] 0xD754 (NOVALAKE_P)
[13:38:18] [PASSED] 0xD755 (NOVALAKE_P)
[13:38:18] [PASSED] 0xD756 (NOVALAKE_P)
[13:38:18] [PASSED] 0xD757 (NOVALAKE_P)
[13:38:18] [PASSED] 0xD75F (NOVALAKE_P)
[13:38:18] =============== [PASSED] check_platform_desc ===============
[13:38:18] ===================== [PASSED] xe_pci ======================
[13:38:18] ============= xe_rtp_tables_test (5 subtests) ==============
[13:38:18] ================== xe_rtp_table_gt_test ===================
[13:38:18] [PASSED] gt_was/14011060649
[13:38:18] [PASSED] gt_was/14011059788
[13:38:18] [PASSED] gt_was/14015795083
[13:38:18] [PASSED] gt_was/16021867713
[13:38:18] [PASSED] gt_was/14019449301
[13:38:18] [PASSED] gt_was/16028005424
[13:38:18] [PASSED] gt_was/14026578760
[13:38:18] [PASSED] gt_was/1409420604
[13:38:18] [PASSED] gt_was/1408615072
[13:38:18] [PASSED] gt_was/22010523718
[13:38:18] [PASSED] gt_was/14011006942
[13:38:18] [PASSED] gt_was/14014830051
[13:38:18] [PASSED] gt_was/18018781329
[13:38:18] [PASSED] gt_was/1509235366
[13:38:18] [PASSED] gt_was/18018781329
[13:38:18] [PASSED] gt_was/16016694945
[13:38:18] [PASSED] gt_was/14018575942
[13:38:18] [PASSED] gt_was/22016670082
[13:38:18] [PASSED] gt_was/22016670082
[13:38:18] [PASSED] gt_was/14017421178
[13:38:18] [PASSED] gt_was/16025250150
[13:38:18] [PASSED] gt_was/14021871409
[13:38:18] [PASSED] gt_was/16021865536
[13:38:18] [PASSED] gt_was/14021486841
[13:38:18] [PASSED] gt_was/14025160223
[13:38:18] [PASSED] gt_was/14026144927, 16029437861, 14026127056
[13:38:18] [PASSED] gt_was/14025635424
[13:38:18] [PASSED] gt_was/16028005424
[13:38:18] ============== [PASSED] xe_rtp_table_gt_test ===============
[13:38:18] ================== xe_rtp_table_gt_test ===================
[13:38:18] [PASSED] gt_tunings/Tuning: Blend Fill Caching Optimization Disable
[13:38:18] [PASSED] gt_tunings/Tuning: 32B Access Enable
[13:38:18] [PASSED] gt_tunings/Tuning: L3 cache
[13:38:18] [PASSED] gt_tunings/Tuning: L3 cache - media
[13:38:18] [PASSED] gt_tunings/Tuning: Compression Overfetch
[13:38:18] [PASSED] gt_tunings/Tuning: Compression Overfetch - media
[13:38:18] [PASSED] gt_tunings/Tuning: Enable compressible partial write overfetch in L3
[13:38:18] [PASSED] gt_tunings/Tuning: Enable compressible partial write overfetch in L3 - media
[13:38:18] [PASSED] gt_tunings/Tuning: L2 Overfetch Compressible Only
[13:38:18] [PASSED] gt_tunings/Tuning: L2 Overfetch Compressible Only - media
[13:38:18] [PASSED] gt_tunings/Tuning: Stateless compression control
[13:38:18] [PASSED] gt_tunings/Tuning: Stateless compression control - media
[13:38:18] [PASSED] gt_tunings/Tuning: L3 RW flush all Cache
[13:38:18] [PASSED] gt_tunings/Tuning: L3 RW flush all cache - media
[13:38:18] [PASSED] gt_tunings/Tuning: Set STLB Bank Hash Mode to 4KB
[13:38:18] ============== [PASSED] xe_rtp_table_gt_test ===============
[13:38:18] ================== xe_rtp_table_oob_test ==================
[13:38:18] [PASSED] oob_was/1607983814
[13:38:18] [PASSED] oob_was/16010904313
[13:38:18] [PASSED] oob_was/18022495364
[13:38:18] [PASSED] oob_was/22012773006
[13:38:18] [PASSED] oob_was/14014475959
[13:38:18] [PASSED] oob_was/22011391025
[13:38:18] [PASSED] oob_was/22012727170
[13:38:18] [PASSED] oob_was/22012727685
[13:38:18] [PASSED] oob_was/22016596838
[13:38:18] [PASSED] oob_was/18020744125
[13:38:18] [PASSED] oob_was/1409600907
[13:38:18] [PASSED] oob_was/22014953428
[13:38:18] [PASSED] oob_was/16017236439
[13:38:18] [PASSED] oob_was/14019821291
[13:38:18] [PASSED] oob_was/14015076503
[13:38:18] [PASSED] oob_was/14018913170
[13:38:18] [PASSED] oob_was/14018094691
[13:38:18] [PASSED] oob_was/18024947630
[13:38:18] [PASSED] oob_was/16022287689
[13:38:18] [PASSED] oob_was/13011645652
[13:38:18] [PASSED] oob_was/14022293748
[13:38:18] [PASSED] oob_was/22019794406
[13:38:18] [PASSED] oob_was/22019338487
[13:38:18] [PASSED] oob_was/16023588340
[13:38:18] [PASSED] oob_was/14019789679
[13:38:18] [PASSED] oob_was/14022866841
[13:38:18] [PASSED] oob_was/16021333562
[13:38:18] [PASSED] oob_was/14016712196
[13:38:18] [PASSED] oob_was/14015568240
[13:38:18] [PASSED] oob_was/18013179988
[13:38:18] [PASSED] oob_was/1508761755
[13:38:18] [PASSED] oob_was/16023105232
[13:38:18] [PASSED] oob_was/16026508708
[13:38:18] [PASSED] oob_was/14020001231
[13:38:18] [PASSED] oob_was/16023683509
[13:38:18] [PASSED] oob_was/14025515070
[13:38:18] [PASSED] oob_was/15015404425_disable
[13:38:18] [PASSED] oob_was/16026007364
[13:38:18] [PASSED] oob_was/14020316580
[13:38:18] [PASSED] oob_was/14025883347
[13:38:18] [PASSED] oob_was/16029380221
[13:38:18] [PASSED] oob_was/22022079272
[13:38:18] [PASSED] oob_was/16029897822
[13:38:18] [PASSED] oob_was/14027054324
[13:38:18] ============== [PASSED] xe_rtp_table_oob_test ==============
[13:38:18] ================ xe_rtp_table_dev_oob_test ================
[13:38:18] [PASSED] device_oob_was/22010954014
[13:38:18] [PASSED] device_oob_was/15015404425
[13:38:18] [PASSED] device_oob_was/22019338487_display
[13:38:18] [PASSED] device_oob_was/14022085890
[13:38:18] [PASSED] device_oob_was/14026539277
[13:38:18] [PASSED] device_oob_was/14026633728
[13:38:18] [PASSED] device_oob_was/14026746987
[13:38:18] [PASSED] device_oob_was/14026779378
[13:38:18] ============ [PASSED] xe_rtp_table_dev_oob_test ============
[13:38:18] ========== xe_rtp_table_missing_upper_bound_test ==========
[13:38:18] [PASSED] register_whitelist/WaAllowPMDepthAndInvocationCountAccessFromUMD, 1408556865
[13:38:18] [PASSED] register_whitelist/1508744258, 14012131227, 1808121037
[13:38:18] [PASSED] register_whitelist/1806527549
[13:38:18] [PASSED] register_whitelist/allow_read_ctx_timestamp
[13:38:18] [PASSED] register_whitelist/allow_read_queue_timestamp
[13:38:18] [PASSED] register_whitelist/16014440446
[13:38:18] [PASSED] register_whitelist/16017236439
[13:38:18] [PASSED] register_whitelist/16020183090
[13:38:18] [PASSED] register_whitelist/14024997852
[13:38:18] [PASSED] register_whitelist/14024997852
[13:38:18] ====== [PASSED] xe_rtp_table_missing_upper_bound_test ======
[13:38:18] =============== [PASSED] xe_rtp_tables_test ================
[13:38:18] =================== xe_rtp (3 subtests) ====================
[13:38:18] =================== xe_rtp_rules_tests ====================
[13:38:18] [PASSED] no
[13:38:18] [PASSED] yes
[13:38:18] [PASSED] no-and-no
[13:38:18] [PASSED] no-and-yes
[13:38:18] [PASSED] yes-and-no
[13:38:18] [PASSED] yes-and-yes
[13:38:18] [PASSED] no-or-no
[13:38:18] [PASSED] no-or-yes
[13:38:18] [PASSED] yes-or-no
[13:38:18] [PASSED] yes-or-yes
[13:38:18] [PASSED] no-yes-or-yes-no
[13:38:18] [PASSED] no-yes-or-yes-yes
[13:38:18] [PASSED] yes-yes-or-no-yes
[13:38:18] [PASSED] yes-yes-or-yes-yes
[13:38:18] [PASSED] no-no-or-yes-or-no
[13:38:18] [PASSED] or
[13:38:18] [PASSED] or-yes
[13:38:18] [PASSED] or-no
[13:38:18] [PASSED] yes-or
[13:38:18] [PASSED] no-or
[13:38:18] [PASSED] no-or-or-yes
[13:38:18] [PASSED] yes-or-or-no
[13:38:18] [PASSED] no-or-or-no
[13:38:18] [PASSED] missing-context-engine-class
[13:38:18] [PASSED] missing-context-engine-class-or-yes
[13:38:18] [PASSED] missing-context-engine-class-or-or-yes
[13:38:18] =============== [PASSED] xe_rtp_rules_tests ================
[13:38:18] =============== xe_rtp_process_to_sr_tests ================
[13:38:18] [PASSED] coalesce-same-reg
[13:38:18] [PASSED] coalesce-same-reg-literal-and-func
[13:38:18] [PASSED] no-match-no-add
[13:38:18] [PASSED] two-regs-two-entries
[13:38:18] [PASSED] clr-one-set-other
[13:38:18] [PASSED] set-field
[13:38:18] [PASSED] conflict-duplicate
[13:38:18] [PASSED] conflict-not-disjoint
[13:38:18] [PASSED] conflict-not-disjoint-literal-and-func
[13:38:18] [PASSED] conflict-reg-type
[13:38:18] [PASSED] bad-mcr-reg-forced-to-regular
[13:38:18] [PASSED] bad-regular-reg-forced-to-mcr
[13:38:18] =========== [PASSED] xe_rtp_process_to_sr_tests ============
[13:38:18] ================== xe_rtp_process_tests ===================
[13:38:18] [PASSED] active1
[13:38:18] [PASSED] active2
[13:38:18] [PASSED] active-inactive
[13:38:18] [PASSED] inactive-active
[13:38:18] [PASSED] inactive-active-inactive
[13:38:18] [PASSED] inactive-inactive-inactive
[13:38:18] ============== [PASSED] xe_rtp_process_tests ===============
[13:38:18] ===================== [PASSED] xe_rtp ======================
[13:38:18] ==================== xe_wa (1 subtest) =====================
[13:38:18] ======================== xe_wa_gt =========================
[13:38:18] [PASSED] TIGERLAKE B0
[13:38:18] [PASSED] DG1 A0
[13:38:18] [PASSED] DG1 B0
[13:38:18] [PASSED] ALDERLAKE_S A0
[13:38:18] [PASSED] ALDERLAKE_S B0
[13:38:18] [PASSED] ALDERLAKE_S C0
[13:38:18] [PASSED] ALDERLAKE_S D0
[13:38:18] [PASSED] ALDERLAKE_P A0
[13:38:18] [PASSED] ALDERLAKE_P B0
[13:38:18] [PASSED] ALDERLAKE_P C0
[13:38:18] [PASSED] ALDERLAKE_S RPLS D0
[13:38:18] [PASSED] ALDERLAKE_P RPLU E0
[13:38:18] [PASSED] DG2 G10 C0
[13:38:18] [PASSED] DG2 G11 B1
[13:38:18] [PASSED] DG2 G12 A1
[13:38:18] [PASSED] METEORLAKE 12.70(Xe_LPG) A0 13.00(Xe_LPM+) A0
[13:38:18] [PASSED] METEORLAKE 12.71(Xe_LPG) A0 13.00(Xe_LPM+) A0
[13:38:18] [PASSED] METEORLAKE 12.74(Xe_LPG+) A0 13.00(Xe_LPM+) A0
[13:38:18] [PASSED] LUNARLAKE 20.04(Xe2_LPG) A0 20.00(Xe2_LPM) A0
[13:38:18] [PASSED] LUNARLAKE 20.04(Xe2_LPG) B0 20.00(Xe2_LPM) A0
[13:38:18] [PASSED] BATTLEMAGE 20.01(Xe2_HPG) A0 13.01(Xe2_HPM) A1
[13:38:18] [PASSED] PANTHERLAKE 30.00(Xe3_LPG) A0 30.00(Xe3_LPM) A0
[13:38:18] ==================== [PASSED] xe_wa_gt =====================
[13:38:18] ====================== [PASSED] xe_wa ======================
[13:38:18] ============================================================
[13:38:18] Testing complete. Ran 742 tests: passed: 724, skipped: 18
[13:38:18] Elapsed time: 35.822s total, 1.851s configuring, 33.306s building, 0.632s running
+ /kernel/tools/testing/kunit/kunit.py run --kunitconfig /kernel/drivers/gpu/drm/tests/.kunitconfig
[13:38:18] Configuring KUnit Kernel ...
Regenerating .config ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
[13:38:20] Building KUnit Kernel ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
Building with:
$ make all compile_commands.json scripts_gdb ARCH=um O=.kunit --jobs=48
[13:38:45] Starting KUnit Kernel (1/1)...
[13:38:45] ============================================================
Running tests with:
$ .kunit/linux kunit.enable=1 mem=1G console=tty kunit_shutdown=halt
[13:38:45] ============ drm_test_pick_cmdline (2 subtests) ============
[13:38:45] [PASSED] drm_test_pick_cmdline_res_1920_1080_60
[13:38:45] =============== drm_test_pick_cmdline_named ===============
[13:38:45] [PASSED] NTSC
[13:38:45] [PASSED] NTSC-J
[13:38:45] [PASSED] PAL
[13:38:45] [PASSED] PAL-M
[13:38:45] =========== [PASSED] drm_test_pick_cmdline_named ===========
[13:38:45] ============== [PASSED] drm_test_pick_cmdline ==============
[13:38:45] == drm_test_atomic_get_connector_for_encoder (1 subtest) ===
[13:38:45] [PASSED] drm_test_drm_atomic_get_connector_for_encoder
[13:38:45] ==== [PASSED] drm_test_atomic_get_connector_for_encoder ====
[13:38:45] =========== drm_validate_clone_mode (2 subtests) ===========
[13:38:45] ============== drm_test_check_in_clone_mode ===============
[13:38:45] [PASSED] in_clone_mode
[13:38:45] [PASSED] not_in_clone_mode
[13:38:45] ========== [PASSED] drm_test_check_in_clone_mode ===========
[13:38:45] =============== drm_test_check_valid_clones ===============
[13:38:45] [PASSED] not_in_clone_mode
[13:38:45] [PASSED] valid_clone
[13:38:45] [PASSED] invalid_clone
[13:38:45] =========== [PASSED] drm_test_check_valid_clones ===========
[13:38:45] ============= [PASSED] drm_validate_clone_mode =============
[13:38:45] ============= drm_validate_modeset (1 subtest) =============
[13:38:45] [PASSED] drm_test_check_connector_changed_modeset
[13:38:45] ============== [PASSED] drm_validate_modeset ===============
[13:38:45] ====== drm_test_bridge_get_current_state (1 subtest) =======
[13:38:45] [PASSED] drm_test_drm_bridge_get_current_state_atomic
[13:38:45] ======== [PASSED] drm_test_bridge_get_current_state ========
[13:38:45] ====== drm_test_bridge_helper_reset_crtc (3 subtests) ======
[13:38:45] [PASSED] drm_test_drm_bridge_helper_reset_crtc_atomic
[13:38:45] [PASSED] drm_test_drm_bridge_helper_reset_crtc_atomic_disabled
[13:38:45] [PASSED] drm_test_drm_bridge_helper_hdmi_output_bus_fmts
[13:38:45] ======== [PASSED] drm_test_bridge_helper_reset_crtc ========
[13:38:45] ============== drm_bridge_alloc (2 subtests) ===============
[13:38:45] [PASSED] drm_test_drm_bridge_alloc_basic
[13:38:45] [PASSED] drm_test_drm_bridge_alloc_get_put
[13:38:45] ================ [PASSED] drm_bridge_alloc =================
[13:38:45] ============= drm_bridge_bus_fmt (5 subtests) ==============
[13:38:45] [PASSED] drm_test_bridge_rgb_yuv_rgb
[13:38:45] [PASSED] drm_test_bridge_must_convert_to_yuv444
[13:38:45] [PASSED] drm_test_bridge_hdmi_auto_rgb
[13:38:45] [PASSED] drm_test_bridge_auto_first
[13:38:45] [PASSED] drm_test_bridge_rgb_yuv_no_path
[13:38:45] =============== [PASSED] drm_bridge_bus_fmt ================
[13:38:45] ============= drm_cmdline_parser (40 subtests) =============
[13:38:45] [PASSED] drm_test_cmdline_force_d_only
[13:38:45] [PASSED] drm_test_cmdline_force_D_only_dvi
[13:38:45] [PASSED] drm_test_cmdline_force_D_only_hdmi
[13:38:45] [PASSED] drm_test_cmdline_force_D_only_not_digital
[13:38:45] [PASSED] drm_test_cmdline_force_e_only
[13:38:45] [PASSED] drm_test_cmdline_res
[13:38:45] [PASSED] drm_test_cmdline_res_vesa
[13:38:45] [PASSED] drm_test_cmdline_res_vesa_rblank
[13:38:45] [PASSED] drm_test_cmdline_res_rblank
[13:38:45] [PASSED] drm_test_cmdline_res_bpp
[13:38:45] [PASSED] drm_test_cmdline_res_refresh
[13:38:45] [PASSED] drm_test_cmdline_res_bpp_refresh
[13:38:45] [PASSED] drm_test_cmdline_res_bpp_refresh_interlaced
[13:38:45] [PASSED] drm_test_cmdline_res_bpp_refresh_margins
[13:38:45] [PASSED] drm_test_cmdline_res_bpp_refresh_force_off
[13:38:45] [PASSED] drm_test_cmdline_res_bpp_refresh_force_on
[13:38:45] [PASSED] drm_test_cmdline_res_bpp_refresh_force_on_analog
[13:38:45] [PASSED] drm_test_cmdline_res_bpp_refresh_force_on_digital
[13:38:45] [PASSED] drm_test_cmdline_res_bpp_refresh_interlaced_margins_force_on
[13:38:45] [PASSED] drm_test_cmdline_res_margins_force_on
[13:38:45] [PASSED] drm_test_cmdline_res_vesa_margins
[13:38:45] [PASSED] drm_test_cmdline_name
[13:38:45] [PASSED] drm_test_cmdline_name_bpp
[13:38:45] [PASSED] drm_test_cmdline_name_option
[13:38:45] [PASSED] drm_test_cmdline_name_bpp_option
[13:38:45] [PASSED] drm_test_cmdline_rotate_0
[13:38:45] [PASSED] drm_test_cmdline_rotate_90
[13:38:45] [PASSED] drm_test_cmdline_rotate_180
[13:38:45] [PASSED] drm_test_cmdline_rotate_270
[13:38:45] [PASSED] drm_test_cmdline_hmirror
[13:38:45] [PASSED] drm_test_cmdline_vmirror
[13:38:45] [PASSED] drm_test_cmdline_margin_options
[13:38:45] [PASSED] drm_test_cmdline_multiple_options
[13:38:45] [PASSED] drm_test_cmdline_bpp_extra_and_option
[13:38:45] [PASSED] drm_test_cmdline_extra_and_option
[13:38:45] [PASSED] drm_test_cmdline_freestanding_options
[13:38:45] [PASSED] drm_test_cmdline_freestanding_force_e_and_options
[13:38:45] [PASSED] drm_test_cmdline_panel_orientation
[13:38:45] ================ drm_test_cmdline_invalid =================
[13:38:45] [PASSED] margin_only
[13:38:45] [PASSED] interlace_only
[13:38:45] [PASSED] res_missing_x
[13:38:45] [PASSED] res_missing_y
[13:38:45] [PASSED] res_bad_y
[13:38:45] [PASSED] res_missing_y_bpp
[13:38:45] [PASSED] res_bad_bpp
[13:38:45] [PASSED] res_bad_refresh
[13:38:45] [PASSED] res_bpp_refresh_force_on_off
[13:38:45] [PASSED] res_invalid_mode
[13:38:45] [PASSED] res_bpp_wrong_place_mode
[13:38:45] [PASSED] name_bpp_refresh
[13:38:45] [PASSED] name_refresh
[13:38:45] [PASSED] name_refresh_wrong_mode
[13:38:45] [PASSED] name_refresh_invalid_mode
[13:38:45] [PASSED] rotate_multiple
[13:38:45] [PASSED] rotate_invalid_val
[13:38:45] [PASSED] rotate_truncated
[13:38:45] [PASSED] invalid_option
[13:38:45] [PASSED] invalid_tv_option
[13:38:45] [PASSED] truncated_tv_option
[13:38:45] ============ [PASSED] drm_test_cmdline_invalid =============
[13:38:45] =============== drm_test_cmdline_tv_options ===============
[13:38:45] [PASSED] NTSC
[13:38:45] [PASSED] NTSC_443
[13:38:45] [PASSED] NTSC_J
[13:38:45] [PASSED] PAL
[13:38:45] [PASSED] PAL_M
[13:38:45] [PASSED] PAL_N
[13:38:45] [PASSED] SECAM
[13:38:45] [PASSED] MONO_525
[13:38:45] [PASSED] MONO_625
[13:38:45] =========== [PASSED] drm_test_cmdline_tv_options ===========
[13:38:45] =============== [PASSED] drm_cmdline_parser ================
[13:38:45] ========== drmm_connector_hdmi_init (20 subtests) ==========
[13:38:45] [PASSED] drm_test_connector_hdmi_init_valid
[13:38:45] [PASSED] drm_test_connector_hdmi_init_bpc_8
[13:38:45] [PASSED] drm_test_connector_hdmi_init_bpc_10
[13:38:45] [PASSED] drm_test_connector_hdmi_init_bpc_12
[13:38:45] [PASSED] drm_test_connector_hdmi_init_bpc_invalid
[13:38:45] [PASSED] drm_test_connector_hdmi_init_bpc_null
[13:38:45] [PASSED] drm_test_connector_hdmi_init_formats_empty
[13:38:45] [PASSED] drm_test_connector_hdmi_init_formats_no_rgb
[13:38:45] === drm_test_connector_hdmi_init_formats_yuv420_allowed ===
[13:38:45] [PASSED] supported_formats=0x9 yuv420_allowed=1
[13:38:45] [PASSED] supported_formats=0x9 yuv420_allowed=0
[13:38:45] [PASSED] supported_formats=0x5 yuv420_allowed=1
[13:38:45] [PASSED] supported_formats=0x5 yuv420_allowed=0
[13:38:45] === [PASSED] drm_test_connector_hdmi_init_formats_yuv420_allowed ===
[13:38:45] [PASSED] drm_test_connector_hdmi_init_null_ddc
[13:38:45] [PASSED] drm_test_connector_hdmi_init_null_product
[13:38:45] [PASSED] drm_test_connector_hdmi_init_null_vendor
[13:38:45] [PASSED] drm_test_connector_hdmi_init_product_length_exact
[13:38:45] [PASSED] drm_test_connector_hdmi_init_product_length_too_long
[13:38:45] [PASSED] drm_test_connector_hdmi_init_product_valid
[13:38:45] [PASSED] drm_test_connector_hdmi_init_vendor_length_exact
[13:38:45] [PASSED] drm_test_connector_hdmi_init_vendor_length_too_long
[13:38:45] [PASSED] drm_test_connector_hdmi_init_vendor_valid
[13:38:45] ========= drm_test_connector_hdmi_init_type_valid =========
[13:38:45] [PASSED] HDMI-A
[13:38:45] [PASSED] HDMI-B
[13:38:45] ===== [PASSED] drm_test_connector_hdmi_init_type_valid =====
[13:38:45] ======== drm_test_connector_hdmi_init_type_invalid ========
[13:38:45] [PASSED] Unknown
[13:38:45] [PASSED] VGA
[13:38:45] [PASSED] DVI-I
[13:38:45] [PASSED] DVI-D
[13:38:45] [PASSED] DVI-A
[13:38:45] [PASSED] Composite
[13:38:45] [PASSED] SVIDEO
[13:38:45] [PASSED] LVDS
[13:38:45] [PASSED] Component
[13:38:45] [PASSED] DIN
[13:38:45] [PASSED] DP
[13:38:45] [PASSED] TV
[13:38:45] [PASSED] eDP
[13:38:45] [PASSED] Virtual
[13:38:45] [PASSED] DSI
[13:38:45] [PASSED] DPI
[13:38:45] [PASSED] Writeback
[13:38:45] [PASSED] SPI
[13:38:45] [PASSED] USB
[13:38:45] ==== [PASSED] drm_test_connector_hdmi_init_type_invalid ====
[13:38:45] ============ [PASSED] drmm_connector_hdmi_init =============
[13:38:45] ============= drmm_connector_init (3 subtests) =============
[13:38:45] [PASSED] drm_test_drmm_connector_init
[13:38:45] [PASSED] drm_test_drmm_connector_init_null_ddc
[13:38:45] ========= drm_test_drmm_connector_init_type_valid =========
[13:38:45] [PASSED] Unknown
[13:38:45] [PASSED] VGA
[13:38:45] [PASSED] DVI-I
[13:38:45] [PASSED] DVI-D
[13:38:45] [PASSED] DVI-A
[13:38:45] [PASSED] Composite
[13:38:45] [PASSED] SVIDEO
[13:38:45] [PASSED] LVDS
[13:38:45] [PASSED] Component
[13:38:45] [PASSED] DIN
[13:38:45] [PASSED] DP
[13:38:45] [PASSED] HDMI-A
[13:38:45] [PASSED] HDMI-B
[13:38:45] [PASSED] TV
[13:38:45] [PASSED] eDP
[13:38:45] [PASSED] Virtual
[13:38:45] [PASSED] DSI
[13:38:45] [PASSED] DPI
[13:38:45] [PASSED] Writeback
[13:38:45] [PASSED] SPI
[13:38:45] [PASSED] USB
[13:38:45] ===== [PASSED] drm_test_drmm_connector_init_type_valid =====
[13:38:45] =============== [PASSED] drmm_connector_init ===============
[13:38:45] ========= drm_connector_dynamic_init (6 subtests) ==========
[13:38:45] [PASSED] drm_test_drm_connector_dynamic_init
[13:38:45] [PASSED] drm_test_drm_connector_dynamic_init_null_ddc
[13:38:45] [PASSED] drm_test_drm_connector_dynamic_init_not_added
[13:38:45] [PASSED] drm_test_drm_connector_dynamic_init_properties
[13:38:45] ===== drm_test_drm_connector_dynamic_init_type_valid ======
[13:38:45] [PASSED] Unknown
[13:38:45] [PASSED] VGA
[13:38:45] [PASSED] DVI-I
[13:38:45] [PASSED] DVI-D
[13:38:45] [PASSED] DVI-A
[13:38:45] [PASSED] Composite
[13:38:45] [PASSED] SVIDEO
[13:38:45] [PASSED] LVDS
[13:38:45] [PASSED] Component
[13:38:45] [PASSED] DIN
[13:38:45] [PASSED] DP
[13:38:45] [PASSED] HDMI-A
[13:38:45] [PASSED] HDMI-B
[13:38:45] [PASSED] TV
[13:38:45] [PASSED] eDP
[13:38:45] [PASSED] Virtual
[13:38:45] [PASSED] DSI
[13:38:45] [PASSED] DPI
[13:38:45] [PASSED] Writeback
[13:38:45] [PASSED] SPI
[13:38:45] [PASSED] USB
[13:38:45] = [PASSED] drm_test_drm_connector_dynamic_init_type_valid ==
[13:38:45] ======== drm_test_drm_connector_dynamic_init_name =========
[13:38:45] [PASSED] Unknown
[13:38:45] [PASSED] VGA
[13:38:45] [PASSED] DVI-I
[13:38:45] [PASSED] DVI-D
[13:38:45] [PASSED] DVI-A
[13:38:45] [PASSED] Composite
[13:38:45] [PASSED] SVIDEO
[13:38:45] [PASSED] LVDS
[13:38:45] [PASSED] Component
[13:38:45] [PASSED] DIN
[13:38:45] [PASSED] DP
[13:38:45] [PASSED] HDMI-A
[13:38:45] [PASSED] HDMI-B
[13:38:45] [PASSED] TV
[13:38:45] [PASSED] eDP
[13:38:45] [PASSED] Virtual
[13:38:45] [PASSED] DSI
[13:38:45] [PASSED] DPI
[13:38:45] [PASSED] Writeback
[13:38:45] [PASSED] SPI
[13:38:45] [PASSED] USB
[13:38:45] ==== [PASSED] drm_test_drm_connector_dynamic_init_name =====
[13:38:45] =========== [PASSED] drm_connector_dynamic_init ============
[13:38:45] ==== drm_connector_dynamic_register_early (4 subtests) =====
[13:38:45] [PASSED] drm_test_drm_connector_dynamic_register_early_on_list
[13:38:45] [PASSED] drm_test_drm_connector_dynamic_register_early_defer
[13:38:45] [PASSED] drm_test_drm_connector_dynamic_register_early_no_init
[13:38:45] [PASSED] drm_test_drm_connector_dynamic_register_early_no_mode_object
[13:38:45] ====== [PASSED] drm_connector_dynamic_register_early =======
[13:38:45] ======= drm_connector_dynamic_register (7 subtests) ========
[13:38:45] [PASSED] drm_test_drm_connector_dynamic_register_on_list
[13:38:45] [PASSED] drm_test_drm_connector_dynamic_register_no_defer
[13:38:45] [PASSED] drm_test_drm_connector_dynamic_register_no_init
[13:38:45] [PASSED] drm_test_drm_connector_dynamic_register_mode_object
[13:38:45] [PASSED] drm_test_drm_connector_dynamic_register_sysfs
[13:38:45] [PASSED] drm_test_drm_connector_dynamic_register_sysfs_name
[13:38:45] [PASSED] drm_test_drm_connector_dynamic_register_debugfs
[13:38:45] ========= [PASSED] drm_connector_dynamic_register ==========
[13:38:45] = drm_connector_attach_broadcast_rgb_property (2 subtests) =
[13:38:45] [PASSED] drm_test_drm_connector_attach_broadcast_rgb_property
[13:38:45] [PASSED] drm_test_drm_connector_attach_broadcast_rgb_property_hdmi_connector
[13:38:45] === [PASSED] drm_connector_attach_broadcast_rgb_property ===
[13:38:45] ========== drm_get_tv_mode_from_name (2 subtests) ==========
[13:38:45] ========== drm_test_get_tv_mode_from_name_valid ===========
[13:38:45] [PASSED] NTSC
[13:38:45] [PASSED] NTSC-443
[13:38:45] [PASSED] NTSC-J
[13:38:45] [PASSED] PAL
[13:38:45] [PASSED] PAL-M
[13:38:45] [PASSED] PAL-N
[13:38:45] [PASSED] SECAM
[13:38:45] [PASSED] Mono
[13:38:45] ====== [PASSED] drm_test_get_tv_mode_from_name_valid =======
[13:38:45] [PASSED] drm_test_get_tv_mode_from_name_truncated
[13:38:45] ============ [PASSED] drm_get_tv_mode_from_name ============
[13:38:45] = drm_test_connector_hdmi_compute_mode_clock (12 subtests) =
[13:38:45] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb
[13:38:45] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_10bpc
[13:38:45] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_10bpc_vic_1
[13:38:45] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_12bpc
[13:38:45] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_12bpc_vic_1
[13:38:45] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_double
[13:38:45] = drm_test_connector_hdmi_compute_mode_clock_yuv420_valid =
[13:38:45] [PASSED] VIC 96
[13:38:45] [PASSED] VIC 97
[13:38:45] [PASSED] VIC 101
[13:38:45] [PASSED] VIC 102
[13:38:45] [PASSED] VIC 106
[13:38:45] [PASSED] VIC 107
[13:38:45] === [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv420_valid ===
[13:38:45] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv420_10_bpc
[13:38:45] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv420_12_bpc
[13:38:45] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv422_8_bpc
[13:38:45] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv422_10_bpc
[13:38:45] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv422_12_bpc
[13:38:45] === [PASSED] drm_test_connector_hdmi_compute_mode_clock ====
[13:38:45] == drm_hdmi_connector_get_broadcast_rgb_name (2 subtests) ==
[13:38:45] === drm_test_drm_hdmi_connector_get_broadcast_rgb_name ====
[13:38:45] [PASSED] Automatic
[13:38:45] [PASSED] Full
[13:38:45] [PASSED] Limited 16:235
[13:38:45] === [PASSED] drm_test_drm_hdmi_connector_get_broadcast_rgb_name ===
[13:38:45] [PASSED] drm_test_drm_hdmi_connector_get_broadcast_rgb_name_invalid
[13:38:45] ==== [PASSED] drm_hdmi_connector_get_broadcast_rgb_name ====
[13:38:45] == drm_hdmi_connector_get_output_format_name (2 subtests) ==
[13:38:45] === drm_test_drm_hdmi_connector_get_output_format_name ====
[13:38:45] [PASSED] RGB
[13:38:45] [PASSED] YUV 4:2:0
[13:38:45] [PASSED] YUV 4:2:2
[13:38:45] [PASSED] YUV 4:4:4
[13:38:45] === [PASSED] drm_test_drm_hdmi_connector_get_output_format_name ===
[13:38:45] [PASSED] drm_test_drm_hdmi_connector_get_output_format_name_invalid
[13:38:45] ==== [PASSED] drm_hdmi_connector_get_output_format_name ====
[13:38:45] ============= drm_damage_helper (21 subtests) ==============
[13:38:45] [PASSED] drm_test_damage_iter_no_damage
[13:38:45] [PASSED] drm_test_damage_iter_no_damage_fractional_src
[13:38:45] [PASSED] drm_test_damage_iter_no_damage_src_moved
[13:38:45] [PASSED] drm_test_damage_iter_no_damage_fractional_src_moved
[13:38:45] [PASSED] drm_test_damage_iter_no_damage_not_visible
[13:38:45] [PASSED] drm_test_damage_iter_no_damage_no_crtc
[13:38:45] [PASSED] drm_test_damage_iter_no_damage_no_fb
[13:38:45] [PASSED] drm_test_damage_iter_simple_damage
[13:38:45] [PASSED] drm_test_damage_iter_single_damage
[13:38:45] [PASSED] drm_test_damage_iter_single_damage_intersect_src
[13:38:45] [PASSED] drm_test_damage_iter_single_damage_outside_src
[13:38:45] [PASSED] drm_test_damage_iter_single_damage_fractional_src
[13:38:45] [PASSED] drm_test_damage_iter_single_damage_intersect_fractional_src
[13:38:45] [PASSED] drm_test_damage_iter_single_damage_outside_fractional_src
[13:38:45] [PASSED] drm_test_damage_iter_single_damage_src_moved
[13:38:45] [PASSED] drm_test_damage_iter_single_damage_fractional_src_moved
[13:38:45] [PASSED] drm_test_damage_iter_damage
[13:38:45] [PASSED] drm_test_damage_iter_damage_one_intersect
[13:38:45] [PASSED] drm_test_damage_iter_damage_one_outside
[13:38:45] [PASSED] drm_test_damage_iter_damage_src_moved
[13:38:45] [PASSED] drm_test_damage_iter_damage_not_visible
[13:38:45] ================ [PASSED] drm_damage_helper ================
[13:38:45] ============== drm_dp_mst_helper (3 subtests) ==============
[13:38:45] ============== drm_test_dp_mst_calc_pbn_mode ==============
[13:38:45] [PASSED] Clock 154000 BPP 30 DSC disabled
[13:38:45] [PASSED] Clock 234000 BPP 30 DSC disabled
[13:38:45] [PASSED] Clock 297000 BPP 24 DSC disabled
[13:38:45] [PASSED] Clock 332880 BPP 24 DSC enabled
[13:38:45] [PASSED] Clock 324540 BPP 24 DSC enabled
[13:38:45] ========== [PASSED] drm_test_dp_mst_calc_pbn_mode ==========
[13:38:45] ============== drm_test_dp_mst_calc_pbn_div ===============
[13:38:45] [PASSED] Link rate 2000000 lane count 4
[13:38:45] [PASSED] Link rate 2000000 lane count 2
[13:38:45] [PASSED] Link rate 2000000 lane count 1
[13:38:45] [PASSED] Link rate 1350000 lane count 4
[13:38:45] [PASSED] Link rate 1350000 lane count 2
[13:38:45] [PASSED] Link rate 1350000 lane count 1
[13:38:45] [PASSED] Link rate 1000000 lane count 4
[13:38:45] [PASSED] Link rate 1000000 lane count 2
[13:38:45] [PASSED] Link rate 1000000 lane count 1
[13:38:45] [PASSED] Link rate 810000 lane count 4
[13:38:45] [PASSED] Link rate 810000 lane count 2
[13:38:45] [PASSED] Link rate 810000 lane count 1
[13:38:45] [PASSED] Link rate 540000 lane count 4
[13:38:45] [PASSED] Link rate 540000 lane count 2
[13:38:45] [PASSED] Link rate 540000 lane count 1
[13:38:45] [PASSED] Link rate 270000 lane count 4
[13:38:45] [PASSED] Link rate 270000 lane count 2
[13:38:45] [PASSED] Link rate 270000 lane count 1
[13:38:45] [PASSED] Link rate 162000 lane count 4
[13:38:45] [PASSED] Link rate 162000 lane count 2
[13:38:45] [PASSED] Link rate 162000 lane count 1
[13:38:45] ========== [PASSED] drm_test_dp_mst_calc_pbn_div ===========
[13:38:45] ========= drm_test_dp_mst_sideband_msg_req_decode =========
[13:38:45] [PASSED] DP_ENUM_PATH_RESOURCES with port number
[13:38:45] [PASSED] DP_POWER_UP_PHY with port number
[13:38:45] [PASSED] DP_POWER_DOWN_PHY with port number
[13:38:45] [PASSED] DP_ALLOCATE_PAYLOAD with SDP stream sinks
[13:38:45] [PASSED] DP_ALLOCATE_PAYLOAD with port number
[13:38:45] [PASSED] DP_ALLOCATE_PAYLOAD with VCPI
[13:38:45] [PASSED] DP_ALLOCATE_PAYLOAD with PBN
[13:38:45] [PASSED] DP_QUERY_PAYLOAD with port number
[13:38:45] [PASSED] DP_QUERY_PAYLOAD with VCPI
[13:38:45] [PASSED] DP_REMOTE_DPCD_READ with port number
[13:38:45] [PASSED] DP_REMOTE_DPCD_READ with DPCD address
[13:38:45] [PASSED] DP_REMOTE_DPCD_READ with max number of bytes
[13:38:45] [PASSED] DP_REMOTE_DPCD_WRITE with port number
[13:38:45] [PASSED] DP_REMOTE_DPCD_WRITE with DPCD address
[13:38:45] [PASSED] DP_REMOTE_DPCD_WRITE with data array
[13:38:45] [PASSED] DP_REMOTE_I2C_READ with port number
[13:38:45] [PASSED] DP_REMOTE_I2C_READ with I2C device ID
[13:38:45] [PASSED] DP_REMOTE_I2C_READ with transactions array
[13:38:45] [PASSED] DP_REMOTE_I2C_WRITE with port number
[13:38:45] [PASSED] DP_REMOTE_I2C_WRITE with I2C device ID
[13:38:45] [PASSED] DP_REMOTE_I2C_WRITE with data array
[13:38:45] [PASSED] DP_QUERY_STREAM_ENC_STATUS with stream ID
[13:38:45] [PASSED] DP_QUERY_STREAM_ENC_STATUS with client ID
[13:38:45] [PASSED] DP_QUERY_STREAM_ENC_STATUS with stream event
[13:38:45] [PASSED] DP_QUERY_STREAM_ENC_STATUS with valid stream event
[13:38:45] [PASSED] DP_QUERY_STREAM_ENC_STATUS with stream behavior
[13:38:45] [PASSED] DP_QUERY_STREAM_ENC_STATUS with a valid stream behavior
[13:38:45] ===== [PASSED] drm_test_dp_mst_sideband_msg_req_decode =====
[13:38:45] ================ [PASSED] drm_dp_mst_helper ================
[13:38:45] ================== drm_exec (7 subtests) ===================
[13:38:45] [PASSED] sanitycheck
[13:38:45] [PASSED] test_lock
[13:38:45] [PASSED] test_lock_unlock
[13:38:45] [PASSED] test_duplicates
[13:38:45] [PASSED] test_prepare
[13:38:45] [PASSED] test_prepare_array
[13:38:45] [PASSED] test_multiple_loops
[13:38:45] ==================== [PASSED] drm_exec =====================
[13:38:45] =========== drm_format_helper_test (17 subtests) ===========
[13:38:45] ============== drm_test_fb_xrgb8888_to_gray8 ==============
[13:38:45] [PASSED] single_pixel_source_buffer
[13:38:45] [PASSED] single_pixel_clip_rectangle
[13:38:45] [PASSED] well_known_colors
[13:38:45] [PASSED] destination_pitch
[13:38:45] ========== [PASSED] drm_test_fb_xrgb8888_to_gray8 ==========
[13:38:45] ============= drm_test_fb_xrgb8888_to_rgb332 ==============
[13:38:45] [PASSED] single_pixel_source_buffer
[13:38:45] [PASSED] single_pixel_clip_rectangle
[13:38:45] [PASSED] well_known_colors
[13:38:45] [PASSED] destination_pitch
[13:38:45] ========= [PASSED] drm_test_fb_xrgb8888_to_rgb332 ==========
[13:38:45] ============= drm_test_fb_xrgb8888_to_rgb565 ==============
[13:38:45] [PASSED] single_pixel_source_buffer
[13:38:45] [PASSED] single_pixel_clip_rectangle
[13:38:45] [PASSED] well_known_colors
[13:38:45] [PASSED] destination_pitch
[13:38:45] ========= [PASSED] drm_test_fb_xrgb8888_to_rgb565 ==========
[13:38:45] ============ drm_test_fb_xrgb8888_to_xrgb1555 =============
[13:38:45] [PASSED] single_pixel_source_buffer
[13:38:45] [PASSED] single_pixel_clip_rectangle
[13:38:45] [PASSED] well_known_colors
[13:38:45] [PASSED] destination_pitch
[13:38:45] ======== [PASSED] drm_test_fb_xrgb8888_to_xrgb1555 =========
[13:38:45] ============ drm_test_fb_xrgb8888_to_argb1555 =============
[13:38:45] [PASSED] single_pixel_source_buffer
[13:38:45] [PASSED] single_pixel_clip_rectangle
[13:38:45] [PASSED] well_known_colors
[13:38:45] [PASSED] destination_pitch
[13:38:45] ======== [PASSED] drm_test_fb_xrgb8888_to_argb1555 =========
[13:38:45] ============ drm_test_fb_xrgb8888_to_rgba5551 =============
[13:38:45] [PASSED] single_pixel_source_buffer
[13:38:45] [PASSED] single_pixel_clip_rectangle
[13:38:45] [PASSED] well_known_colors
[13:38:45] [PASSED] destination_pitch
[13:38:45] ======== [PASSED] drm_test_fb_xrgb8888_to_rgba5551 =========
[13:38:45] ============= drm_test_fb_xrgb8888_to_rgb888 ==============
[13:38:45] [PASSED] single_pixel_source_buffer
[13:38:45] [PASSED] single_pixel_clip_rectangle
[13:38:45] [PASSED] well_known_colors
[13:38:45] [PASSED] destination_pitch
[13:38:45] ========= [PASSED] drm_test_fb_xrgb8888_to_rgb888 ==========
[13:38:45] ============= drm_test_fb_xrgb8888_to_bgr888 ==============
[13:38:45] [PASSED] single_pixel_source_buffer
[13:38:45] [PASSED] single_pixel_clip_rectangle
[13:38:45] [PASSED] well_known_colors
[13:38:45] [PASSED] destination_pitch
[13:38:45] ========= [PASSED] drm_test_fb_xrgb8888_to_bgr888 ==========
[13:38:45] ============ drm_test_fb_xrgb8888_to_argb8888 =============
[13:38:45] [PASSED] single_pixel_source_buffer
[13:38:45] [PASSED] single_pixel_clip_rectangle
[13:38:45] [PASSED] well_known_colors
[13:38:45] [PASSED] destination_pitch
[13:38:45] ======== [PASSED] drm_test_fb_xrgb8888_to_argb8888 =========
[13:38:45] =========== drm_test_fb_xrgb8888_to_xrgb2101010 ===========
[13:38:45] [PASSED] single_pixel_source_buffer
[13:38:45] [PASSED] single_pixel_clip_rectangle
[13:38:45] [PASSED] well_known_colors
[13:38:45] [PASSED] destination_pitch
[13:38:45] ======= [PASSED] drm_test_fb_xrgb8888_to_xrgb2101010 =======
[13:38:45] =========== drm_test_fb_xrgb8888_to_argb2101010 ===========
[13:38:45] [PASSED] single_pixel_source_buffer
[13:38:45] [PASSED] single_pixel_clip_rectangle
[13:38:45] [PASSED] well_known_colors
[13:38:45] [PASSED] destination_pitch
[13:38:45] ======= [PASSED] drm_test_fb_xrgb8888_to_argb2101010 =======
[13:38:45] ============== drm_test_fb_xrgb8888_to_mono ===============
[13:38:45] [PASSED] single_pixel_source_buffer
[13:38:45] [PASSED] single_pixel_clip_rectangle
[13:38:45] [PASSED] well_known_colors
[13:38:45] [PASSED] destination_pitch
[13:38:45] ========== [PASSED] drm_test_fb_xrgb8888_to_mono ===========
[13:38:45] ==================== drm_test_fb_swab =====================
[13:38:45] [PASSED] single_pixel_source_buffer
[13:38:45] [PASSED] single_pixel_clip_rectangle
[13:38:45] [PASSED] well_known_colors
[13:38:45] [PASSED] destination_pitch
[13:38:45] ================ [PASSED] drm_test_fb_swab =================
[13:38:45] ============ drm_test_fb_xrgb8888_to_xbgr8888 =============
[13:38:45] [PASSED] single_pixel_source_buffer
[13:38:45] [PASSED] single_pixel_clip_rectangle
[13:38:45] [PASSED] well_known_colors
[13:38:45] [PASSED] destination_pitch
[13:38:45] ======== [PASSED] drm_test_fb_xrgb8888_to_xbgr8888 =========
[13:38:45] ============ drm_test_fb_xrgb8888_to_abgr8888 =============
[13:38:45] [PASSED] single_pixel_source_buffer
[13:38:45] [PASSED] single_pixel_clip_rectangle
[13:38:45] [PASSED] well_known_colors
[13:38:45] [PASSED] destination_pitch
[13:38:45] ======== [PASSED] drm_test_fb_xrgb8888_to_abgr8888 =========
[13:38:45] ================= drm_test_fb_clip_offset =================
[13:38:45] [PASSED] pass through
[13:38:45] [PASSED] horizontal offset
[13:38:45] [PASSED] vertical offset
[13:38:45] [PASSED] horizontal and vertical offset
[13:38:45] [PASSED] horizontal offset (custom pitch)
[13:38:45] [PASSED] vertical offset (custom pitch)
[13:38:45] [PASSED] horizontal and vertical offset (custom pitch)
[13:38:45] ============= [PASSED] drm_test_fb_clip_offset =============
[13:38:45] =================== drm_test_fb_memcpy ====================
[13:38:45] [PASSED] single_pixel_source_buffer: XR24 little-endian (0x34325258)
[13:38:45] [PASSED] single_pixel_source_buffer: XRA8 little-endian (0x38415258)
[13:38:45] [PASSED] single_pixel_source_buffer: YU24 little-endian (0x34325559)
[13:38:45] [PASSED] single_pixel_clip_rectangle: XB24 little-endian (0x34324258)
[13:38:45] [PASSED] single_pixel_clip_rectangle: XRA8 little-endian (0x38415258)
[13:38:45] [PASSED] single_pixel_clip_rectangle: YU24 little-endian (0x34325559)
[13:38:45] [PASSED] well_known_colors: XB24 little-endian (0x34324258)
[13:38:45] [PASSED] well_known_colors: XRA8 little-endian (0x38415258)
[13:38:45] [PASSED] well_known_colors: YU24 little-endian (0x34325559)
[13:38:45] [PASSED] destination_pitch: XB24 little-endian (0x34324258)
[13:38:45] [PASSED] destination_pitch: XRA8 little-endian (0x38415258)
[13:38:45] [PASSED] destination_pitch: YU24 little-endian (0x34325559)
[13:38:45] =============== [PASSED] drm_test_fb_memcpy ================
[13:38:45] ============= [PASSED] drm_format_helper_test ==============
[13:38:45] ================= drm_format (18 subtests) =================
[13:38:45] [PASSED] drm_test_format_block_width_invalid
[13:38:45] [PASSED] drm_test_format_block_width_one_plane
[13:38:45] [PASSED] drm_test_format_block_width_two_plane
[13:38:45] [PASSED] drm_test_format_block_width_three_plane
[13:38:45] [PASSED] drm_test_format_block_width_tiled
[13:38:45] [PASSED] drm_test_format_block_height_invalid
[13:38:45] [PASSED] drm_test_format_block_height_one_plane
[13:38:45] [PASSED] drm_test_format_block_height_two_plane
[13:38:45] [PASSED] drm_test_format_block_height_three_plane
[13:38:45] [PASSED] drm_test_format_block_height_tiled
[13:38:45] [PASSED] drm_test_format_min_pitch_invalid
[13:38:45] [PASSED] drm_test_format_min_pitch_one_plane_8bpp
[13:38:45] [PASSED] drm_test_format_min_pitch_one_plane_16bpp
[13:38:45] [PASSED] drm_test_format_min_pitch_one_plane_24bpp
[13:38:45] [PASSED] drm_test_format_min_pitch_one_plane_32bpp
[13:38:45] [PASSED] drm_test_format_min_pitch_two_plane
[13:38:45] [PASSED] drm_test_format_min_pitch_three_plane_8bpp
[13:38:45] [PASSED] drm_test_format_min_pitch_tiled
[13:38:45] =================== [PASSED] drm_format ====================
[13:38:45] ============== drm_framebuffer (10 subtests) ===============
[13:38:45] ========== drm_test_framebuffer_check_src_coords ==========
[13:38:45] [PASSED] Success: source fits into fb
[13:38:45] [PASSED] Fail: overflowing fb with x-axis coordinate
[13:38:45] [PASSED] Fail: overflowing fb with y-axis coordinate
[13:38:45] [PASSED] Fail: overflowing fb with source width
[13:38:45] [PASSED] Fail: overflowing fb with source height
[13:38:45] ====== [PASSED] drm_test_framebuffer_check_src_coords ======
[13:38:45] [PASSED] drm_test_framebuffer_cleanup
[13:38:45] =============== drm_test_framebuffer_create ===============
[13:38:45] [PASSED] ABGR8888 normal sizes
[13:38:45] [PASSED] ABGR8888 max sizes
[13:38:45] [PASSED] ABGR8888 pitch greater than min required
[13:38:45] [PASSED] ABGR8888 pitch less than min required
[13:38:45] [PASSED] ABGR8888 Invalid width
[13:38:45] [PASSED] ABGR8888 Invalid buffer handle
[13:38:45] [PASSED] No pixel format
[13:38:45] [PASSED] ABGR8888 Width 0
[13:38:45] [PASSED] ABGR8888 Height 0
[13:38:45] [PASSED] ABGR8888 Out of bound height * pitch combination
[13:38:45] [PASSED] ABGR8888 Large buffer offset
[13:38:45] [PASSED] ABGR8888 Buffer offset for inexistent plane
[13:38:45] [PASSED] ABGR8888 Invalid flag
[13:38:45] [PASSED] ABGR8888 Set DRM_MODE_FB_MODIFIERS without modifiers
[13:38:45] [PASSED] ABGR8888 Valid buffer modifier
[13:38:45] [PASSED] ABGR8888 Invalid buffer modifier(DRM_FORMAT_MOD_SAMSUNG_64_32_TILE)
[13:38:45] [PASSED] ABGR8888 Extra pitches without DRM_MODE_FB_MODIFIERS
[13:38:45] [PASSED] ABGR8888 Extra pitches with DRM_MODE_FB_MODIFIERS
[13:38:45] [PASSED] NV12 Normal sizes
[13:38:45] [PASSED] NV12 Max sizes
[13:38:45] [PASSED] NV12 Invalid pitch
[13:38:45] [PASSED] NV12 Invalid modifier/missing DRM_MODE_FB_MODIFIERS flag
[13:38:45] [PASSED] NV12 different modifier per-plane
[13:38:45] [PASSED] NV12 with DRM_FORMAT_MOD_SAMSUNG_64_32_TILE
[13:38:45] [PASSED] NV12 Valid modifiers without DRM_MODE_FB_MODIFIERS
[13:38:45] [PASSED] NV12 Modifier for inexistent plane
[13:38:45] [PASSED] NV12 Handle for inexistent plane
[13:38:45] [PASSED] NV12 Handle for inexistent plane without DRM_MODE_FB_MODIFIERS
[13:38:45] [PASSED] YVU420 DRM_MODE_FB_MODIFIERS set without modifier
[13:38:45] [PASSED] YVU420 Normal sizes
[13:38:45] [PASSED] YVU420 Max sizes
[13:38:45] [PASSED] YVU420 Invalid pitch
[13:38:45] [PASSED] YVU420 Different pitches
[13:38:45] [PASSED] YVU420 Different buffer offsets/pitches
[13:38:45] [PASSED] YVU420 Modifier set just for plane 0, without DRM_MODE_FB_MODIFIERS
[13:38:45] [PASSED] YVU420 Modifier set just for planes 0, 1, without DRM_MODE_FB_MODIFIERS
[13:38:45] [PASSED] YVU420 Modifier set just for plane 0, 1, with DRM_MODE_FB_MODIFIERS
[13:38:45] [PASSED] YVU420 Valid modifier
[13:38:45] [PASSED] YVU420 Different modifiers per plane
[13:38:45] [PASSED] YVU420 Modifier for inexistent plane
[13:38:45] [PASSED] YUV420_10BIT Invalid modifier(DRM_FORMAT_MOD_LINEAR)
[13:38:45] [PASSED] X0L2 Normal sizes
[13:38:45] [PASSED] X0L2 Max sizes
[13:38:45] [PASSED] X0L2 Invalid pitch
[13:38:45] [PASSED] X0L2 Pitch greater than minimum required
[13:38:45] [PASSED] X0L2 Handle for inexistent plane
[13:38:45] [PASSED] X0L2 Offset for inexistent plane, without DRM_MODE_FB_MODIFIERS set
[13:38:45] [PASSED] X0L2 Modifier without DRM_MODE_FB_MODIFIERS set
[13:38:45] [PASSED] X0L2 Valid modifier
[13:38:45] [PASSED] X0L2 Modifier for inexistent plane
[13:38:45] =========== [PASSED] drm_test_framebuffer_create ===========
[13:38:45] [PASSED] drm_test_framebuffer_free
[13:38:45] [PASSED] drm_test_framebuffer_init
[13:38:45] [PASSED] drm_test_framebuffer_init_bad_format
[13:38:45] [PASSED] drm_test_framebuffer_init_dev_mismatch
[13:38:45] [PASSED] drm_test_framebuffer_lookup
[13:38:45] [PASSED] drm_test_framebuffer_lookup_inexistent
[13:38:45] [PASSED] drm_test_framebuffer_modifiers_not_supported
[13:38:45] ================= [PASSED] drm_framebuffer =================
[13:38:45] ================ drm_gem_shmem (8 subtests) ================
[13:38:45] [PASSED] drm_gem_shmem_test_obj_create
[13:38:45] [PASSED] drm_gem_shmem_test_obj_create_private
[13:38:45] [PASSED] drm_gem_shmem_test_pin_pages
[13:38:45] [PASSED] drm_gem_shmem_test_vmap
[13:38:45] [PASSED] drm_gem_shmem_test_get_sg_table
[13:38:45] [PASSED] drm_gem_shmem_test_get_pages_sgt
[13:38:45] [PASSED] drm_gem_shmem_test_madvise
[13:38:45] [PASSED] drm_gem_shmem_test_purge
[13:38:45] ================== [PASSED] drm_gem_shmem ==================
[13:38:45] === drm_atomic_helper_connector_hdmi_check (29 subtests) ===
[13:38:45] [PASSED] drm_test_check_broadcast_rgb_auto_cea_mode
[13:38:45] [PASSED] drm_test_check_broadcast_rgb_auto_cea_mode_vic_1
[13:38:45] [PASSED] drm_test_check_broadcast_rgb_full_cea_mode
[13:38:45] [PASSED] drm_test_check_broadcast_rgb_full_cea_mode_vic_1
[13:38:45] [PASSED] drm_test_check_broadcast_rgb_limited_cea_mode
[13:38:45] [PASSED] drm_test_check_broadcast_rgb_limited_cea_mode_vic_1
[13:38:45] ====== drm_test_check_broadcast_rgb_cea_mode_yuv420 =======
[13:38:45] [PASSED] Automatic
[13:38:45] [PASSED] Full
[13:38:45] [PASSED] Limited 16:235
[13:38:45] == [PASSED] drm_test_check_broadcast_rgb_cea_mode_yuv420 ===
[13:38:45] [PASSED] drm_test_check_broadcast_rgb_crtc_mode_changed
[13:38:45] [PASSED] drm_test_check_broadcast_rgb_crtc_mode_not_changed
[13:38:45] [PASSED] drm_test_check_disable_connector
[13:38:45] [PASSED] drm_test_check_hdmi_funcs_reject_rate
[13:38:45] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_rgb
[13:38:45] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_yuv420
[13:38:45] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_ignore_yuv422
[13:38:45] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_ignore_yuv420
[13:38:45] [PASSED] drm_test_check_driver_unsupported_fallback_yuv420
[13:38:45] [PASSED] drm_test_check_output_bpc_crtc_mode_changed
[13:38:45] [PASSED] drm_test_check_output_bpc_crtc_mode_not_changed
[13:38:45] [PASSED] drm_test_check_output_bpc_dvi
[13:38:45] [PASSED] drm_test_check_output_bpc_format_vic_1
[13:38:45] [PASSED] drm_test_check_output_bpc_format_display_8bpc_only
[13:38:45] [PASSED] drm_test_check_output_bpc_format_display_rgb_only
[13:38:45] [PASSED] drm_test_check_output_bpc_format_driver_8bpc_only
[13:38:45] [PASSED] drm_test_check_output_bpc_format_driver_rgb_only
[13:38:45] [PASSED] drm_test_check_tmds_char_rate_rgb_8bpc
[13:38:45] [PASSED] drm_test_check_tmds_char_rate_rgb_10bpc
[13:38:45] [PASSED] drm_test_check_tmds_char_rate_rgb_12bpc
[13:38:45] ============ drm_test_check_hdmi_color_format =============
[13:38:45] [PASSED] AUTO -> RGB
[13:38:45] [PASSED] YCBCR422 -> YUV422
[13:38:45] [PASSED] YCBCR420 -> YUV420
[13:38:45] [PASSED] YCBCR444 -> YUV444
[13:38:45] [PASSED] RGB -> RGB
[13:38:45] ======== [PASSED] drm_test_check_hdmi_color_format =========
[13:38:45] ======== drm_test_check_hdmi_color_format_420_only ========
[13:38:45] [PASSED] RGB should fail
[13:38:45] [PASSED] YUV444 should fail
[13:38:45] [PASSED] YUV422 should fail
[13:38:45] [PASSED] YUV420 should work
[13:38:45] ==== [PASSED] drm_test_check_hdmi_color_format_420_only ====
[13:38:45] ===== [PASSED] drm_atomic_helper_connector_hdmi_check ======
[13:38:45] === drm_atomic_helper_connector_hdmi_reset (6 subtests) ====
[13:38:45] [PASSED] drm_test_check_broadcast_rgb_value
[13:38:45] [PASSED] drm_test_check_bpc_8_value
[13:38:45] [PASSED] drm_test_check_bpc_10_value
[13:38:45] [PASSED] drm_test_check_bpc_12_value
[13:38:45] [PASSED] drm_test_check_format_value
[13:38:45] [PASSED] drm_test_check_tmds_char_value
[13:38:45] ===== [PASSED] drm_atomic_helper_connector_hdmi_reset ======
[13:38:45] = drm_atomic_helper_connector_hdmi_mode_valid (7 subtests) =
[13:38:45] [PASSED] drm_test_check_mode_valid
[13:38:45] [PASSED] drm_test_check_mode_valid_reject
[13:38:45] [PASSED] drm_test_check_mode_valid_reject_rate
[13:38:45] [PASSED] drm_test_check_mode_valid_reject_max_clock
[13:38:45] [PASSED] drm_test_check_mode_valid_yuv420_only_max_clock
[13:38:45] [PASSED] drm_test_check_mode_valid_reject_yuv420_only_connector
[13:38:45] [PASSED] drm_test_check_mode_valid_accept_yuv420_also_connector_rgb
[13:38:45] === [PASSED] drm_atomic_helper_connector_hdmi_mode_valid ===
[13:38:45] = drm_atomic_helper_connector_hdmi_infoframes (5 subtests) =
[13:38:45] [PASSED] drm_test_check_infoframes
[13:38:45] [PASSED] drm_test_check_reject_avi_infoframe
[13:38:45] [PASSED] drm_test_check_reject_hdr_infoframe_bpc_8
[13:38:45] [PASSED] drm_test_check_reject_hdr_infoframe_bpc_10
[13:38:45] [PASSED] drm_test_check_reject_audio_infoframe
[13:38:45] === [PASSED] drm_atomic_helper_connector_hdmi_infoframes ===
[13:38:45] ================= drm_managed (2 subtests) =================
[13:38:45] [PASSED] drm_test_managed_release_action
[13:38:45] [PASSED] drm_test_managed_run_action
[13:38:45] =================== [PASSED] drm_managed ===================
[13:38:45] =================== drm_mm (6 subtests) ====================
[13:38:45] [PASSED] drm_test_mm_init
[13:38:45] [PASSED] drm_test_mm_debug
[13:38:45] [PASSED] drm_test_mm_align32
[13:38:45] [PASSED] drm_test_mm_align64
[13:38:45] [PASSED] drm_test_mm_lowest
[13:38:45] [PASSED] drm_test_mm_highest
[13:38:45] ===================== [PASSED] drm_mm ======================
[13:38:45] ============= drm_modes_analog_tv (5 subtests) =============
[13:38:45] [PASSED] drm_test_modes_analog_tv_mono_576i
[13:38:45] [PASSED] drm_test_modes_analog_tv_ntsc_480i
[13:38:45] [PASSED] drm_test_modes_analog_tv_ntsc_480i_inlined
[13:38:45] [PASSED] drm_test_modes_analog_tv_pal_576i
[13:38:45] [PASSED] drm_test_modes_analog_tv_pal_576i_inlined
[13:38:45] =============== [PASSED] drm_modes_analog_tv ===============
[13:38:45] ============== drm_plane_helper (2 subtests) ===============
[13:38:45] =============== drm_test_check_plane_state ================
[13:38:45] [PASSED] clipping_simple
[13:38:45] [PASSED] clipping_rotate_reflect
[13:38:45] [PASSED] positioning_simple
[13:38:45] [PASSED] upscaling
[13:38:45] [PASSED] downscaling
[13:38:45] [PASSED] rounding1
[13:38:45] [PASSED] rounding2
[13:38:45] [PASSED] rounding3
[13:38:45] [PASSED] rounding4
[13:38:45] =========== [PASSED] drm_test_check_plane_state ============
[13:38:45] =========== drm_test_check_invalid_plane_state ============
[13:38:45] [PASSED] positioning_invalid
[13:38:45] [PASSED] upscaling_invalid
[13:38:45] [PASSED] downscaling_invalid
[13:38:45] ======= [PASSED] drm_test_check_invalid_plane_state ========
[13:38:45] ================ [PASSED] drm_plane_helper =================
[13:38:45] ====== drm_connector_helper_tv_get_modes (1 subtest) =======
[13:38:45] ====== drm_test_connector_helper_tv_get_modes_check =======
[13:38:45] [PASSED] None
[13:38:45] [PASSED] PAL
[13:38:45] [PASSED] NTSC
[13:38:45] [PASSED] Both, NTSC Default
[13:38:45] [PASSED] Both, PAL Default
[13:38:45] [PASSED] Both, NTSC Default, with PAL on command-line
[13:38:45] [PASSED] Both, PAL Default, with NTSC on command-line
[13:38:45] == [PASSED] drm_test_connector_helper_tv_get_modes_check ===
[13:38:45] ======== [PASSED] drm_connector_helper_tv_get_modes ========
[13:38:45] ================== drm_rect (9 subtests) ===================
[13:38:45] [PASSED] drm_test_rect_clip_scaled_div_by_zero
[13:38:45] [PASSED] drm_test_rect_clip_scaled_not_clipped
[13:38:45] [PASSED] drm_test_rect_clip_scaled_clipped
[13:38:45] [PASSED] drm_test_rect_clip_scaled_signed_vs_unsigned
[13:38:45] ================= drm_test_rect_intersect =================
[13:38:45] [PASSED] top-left x bottom-right: 2x2+1+1 x 2x2+0+0
[13:38:45] [PASSED] top-right x bottom-left: 2x2+0+0 x 2x2+1-1
[13:38:45] [PASSED] bottom-left x top-right: 2x2+1-1 x 2x2+0+0
[13:38:45] [PASSED] bottom-right x top-left: 2x2+0+0 x 2x2+1+1
[13:38:45] [PASSED] right x left: 2x1+0+0 x 3x1+1+0
[13:38:45] [PASSED] left x right: 3x1+1+0 x 2x1+0+0
[13:38:45] [PASSED] up x bottom: 1x2+0+0 x 1x3+0-1
[13:38:45] [PASSED] bottom x up: 1x3+0-1 x 1x2+0+0
[13:38:45] [PASSED] touching corner: 1x1+0+0 x 2x2+1+1
[13:38:45] [PASSED] touching side: 1x1+0+0 x 1x1+1+0
[13:38:45] [PASSED] equal rects: 2x2+0+0 x 2x2+0+0
[13:38:45] [PASSED] inside another: 2x2+0+0 x 1x1+1+1
[13:38:45] [PASSED] far away: 1x1+0+0 x 1x1+3+6
[13:38:45] [PASSED] points intersecting: 0x0+5+10 x 0x0+5+10
[13:38:45] [PASSED] points not intersecting: 0x0+0+0 x 0x0+5+10
[13:38:45] ============= [PASSED] drm_test_rect_intersect =============
[13:38:45] ================ drm_test_rect_calc_hscale ================
[13:38:45] [PASSED] normal use
[13:38:45] [PASSED] out of max range
[13:38:45] [PASSED] out of min range
[13:38:45] [PASSED] zero dst
[13:38:45] [PASSED] negative src
[13:38:45] [PASSED] negative dst
[13:38:45] ============ [PASSED] drm_test_rect_calc_hscale ============
[13:38:45] ================ drm_test_rect_calc_vscale ================
[13:38:45] [PASSED] normal use
[13:38:45] [PASSED] out of max range
[13:38:45] [PASSED] out of min range
[13:38:45] [PASSED] zero dst
[13:38:45] [PASSED] negative src
[13:38:45] [PASSED] negative dst
[13:38:45] ============ [PASSED] drm_test_rect_calc_vscale ============
[13:38:45] ================== drm_test_rect_rotate ===================
[13:38:45] [PASSED] reflect-x
[13:38:45] [PASSED] reflect-y
[13:38:45] [PASSED] rotate-0
[13:38:45] [PASSED] rotate-90
[13:38:45] [PASSED] rotate-180
[13:38:45] [PASSED] rotate-270
[13:38:45] ============== [PASSED] drm_test_rect_rotate ===============
[13:38:45] ================ drm_test_rect_rotate_inv =================
[13:38:45] [PASSED] reflect-x
[13:38:45] [PASSED] reflect-y
[13:38:45] [PASSED] rotate-0
[13:38:45] [PASSED] rotate-90
[13:38:45] [PASSED] rotate-180
[13:38:45] [PASSED] rotate-270
[13:38:45] ============ [PASSED] drm_test_rect_rotate_inv =============
[13:38:45] ==================== [PASSED] drm_rect =====================
[13:38:45] ============ drm_sysfb_modeset_test (1 subtest) ============
[13:38:45] ============ drm_test_sysfb_build_fourcc_list =============
[13:38:45] [PASSED] no native formats
[13:38:45] [PASSED] XRGB8888 as native format
[13:38:45] [PASSED] remove duplicates
[13:38:45] [PASSED] convert alpha formats
[13:38:45] [PASSED] random formats
[13:38:45] ======== [PASSED] drm_test_sysfb_build_fourcc_list =========
[13:38:45] ============= [PASSED] drm_sysfb_modeset_test ==============
[13:38:45] ================== drm_fixp (2 subtests) ===================
[13:38:45] [PASSED] drm_test_int2fixp
[13:38:45] [PASSED] drm_test_sm2fixp
[13:38:45] ==================== [PASSED] drm_fixp =====================
[13:38:45] ============================================================
[13:38:45] Testing complete. Ran 637 tests: passed: 637
[13:38:45] Elapsed time: 26.734s total, 1.828s configuring, 24.738s building, 0.149s running
+ /kernel/tools/testing/kunit/kunit.py run --kunitconfig /kernel/drivers/gpu/drm/ttm/tests/.kunitconfig
[13:38:45] Configuring KUnit Kernel ...
Regenerating .config ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
[13:38:47] Building KUnit Kernel ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
Building with:
$ make all compile_commands.json scripts_gdb ARCH=um O=.kunit --jobs=48
[13:38:57] Starting KUnit Kernel (1/1)...
[13:38:57] ============================================================
Running tests with:
$ .kunit/linux kunit.enable=1 mem=1G console=tty kunit_shutdown=halt
[13:38:57] ================= ttm_device (5 subtests) ==================
[13:38:57] [PASSED] ttm_device_init_basic
[13:38:57] [PASSED] ttm_device_init_multiple
[13:38:57] [PASSED] ttm_device_fini_basic
[13:38:57] [PASSED] ttm_device_init_no_vma_man
[13:38:57] ================== ttm_device_init_pools ==================
[13:38:57] [PASSED] No DMA allocations, no DMA32 required
[13:38:57] [PASSED] DMA allocations, DMA32 required
[13:38:57] [PASSED] No DMA allocations, DMA32 required
[13:38:57] [PASSED] DMA allocations, no DMA32 required
[13:38:57] ============== [PASSED] ttm_device_init_pools ==============
[13:38:57] =================== [PASSED] ttm_device ====================
[13:38:57] ================== ttm_pool (8 subtests) ===================
[13:38:57] ================== ttm_pool_alloc_basic ===================
[13:38:57] [PASSED] One page
[13:38:57] [PASSED] More than one page
[13:38:57] [PASSED] Above the allocation limit
[13:38:57] [PASSED] One page, with coherent DMA mappings enabled
[13:38:57] [PASSED] Above the allocation limit, with coherent DMA mappings enabled
[13:38:57] ============== [PASSED] ttm_pool_alloc_basic ===============
[13:38:57] ============== ttm_pool_alloc_basic_dma_addr ==============
[13:38:57] [PASSED] One page
[13:38:57] [PASSED] More than one page
[13:38:57] [PASSED] Above the allocation limit
[13:38:57] [PASSED] One page, with coherent DMA mappings enabled
[13:38:57] [PASSED] Above the allocation limit, with coherent DMA mappings enabled
[13:38:57] ========== [PASSED] ttm_pool_alloc_basic_dma_addr ==========
[13:38:57] [PASSED] ttm_pool_alloc_order_caching_match
[13:38:57] [PASSED] ttm_pool_alloc_caching_mismatch
[13:38:57] [PASSED] ttm_pool_alloc_order_mismatch
[13:38:57] [PASSED] ttm_pool_free_dma_alloc
[13:38:57] [PASSED] ttm_pool_free_no_dma_alloc
[13:38:57] [PASSED] ttm_pool_fini_basic
[13:38:57] ==================== [PASSED] ttm_pool =====================
[13:38:57] ================ ttm_resource (8 subtests) =================
[13:38:57] ================= ttm_resource_init_basic =================
[13:38:57] [PASSED] Init resource in TTM_PL_SYSTEM
[13:38:57] [PASSED] Init resource in TTM_PL_VRAM
[13:38:57] [PASSED] Init resource in a private placement
[13:38:57] [PASSED] Init resource in TTM_PL_SYSTEM, set placement flags
[13:38:57] ============= [PASSED] ttm_resource_init_basic =============
[13:38:57] [PASSED] ttm_resource_init_pinned
[13:38:57] [PASSED] ttm_resource_fini_basic
[13:38:57] [PASSED] ttm_resource_manager_init_basic
[13:38:57] [PASSED] ttm_resource_manager_usage_basic
[13:38:57] [PASSED] ttm_resource_manager_set_used_basic
[13:38:57] [PASSED] ttm_sys_man_alloc_basic
[13:38:57] [PASSED] ttm_sys_man_free_basic
[13:38:57] ================== [PASSED] ttm_resource ===================
[13:38:57] =================== ttm_tt (15 subtests) ===================
[13:38:57] ==================== ttm_tt_init_basic ====================
[13:38:57] [PASSED] Page-aligned size
[13:38:57] [PASSED] Extra pages requested
[13:38:57] ================ [PASSED] ttm_tt_init_basic ================
[13:38:57] [PASSED] ttm_tt_init_misaligned
[13:38:57] [PASSED] ttm_tt_fini_basic
[13:38:57] [PASSED] ttm_tt_fini_sg
[13:38:57] [PASSED] ttm_tt_fini_shmem
[13:38:57] [PASSED] ttm_tt_create_basic
[13:38:57] [PASSED] ttm_tt_create_invalid_bo_type
[13:38:57] [PASSED] ttm_tt_create_ttm_exists
[13:38:57] [PASSED] ttm_tt_create_failed
[13:38:57] [PASSED] ttm_tt_destroy_basic
[13:38:57] [PASSED] ttm_tt_populate_null_ttm
[13:38:57] [PASSED] ttm_tt_populate_populated_ttm
[13:38:57] [PASSED] ttm_tt_unpopulate_basic
[13:38:57] [PASSED] ttm_tt_unpopulate_empty_ttm
[13:38:57] [PASSED] ttm_tt_swapin_basic
[13:38:57] ===================== [PASSED] ttm_tt ======================
[13:38:57] =================== ttm_bo (14 subtests) ===================
[13:38:57] =========== ttm_bo_reserve_optimistic_no_ticket ===========
[13:38:57] [PASSED] Cannot be interrupted and sleeps
[13:38:57] [PASSED] Cannot be interrupted, locks straight away
[13:38:57] [PASSED] Can be interrupted, sleeps
[13:38:57] ======= [PASSED] ttm_bo_reserve_optimistic_no_ticket =======
[13:38:57] [PASSED] ttm_bo_reserve_locked_no_sleep
[13:38:57] [PASSED] ttm_bo_reserve_no_wait_ticket
[13:38:57] [PASSED] ttm_bo_reserve_double_resv
[13:38:57] [PASSED] ttm_bo_reserve_interrupted
[13:38:57] [PASSED] ttm_bo_reserve_deadlock
[13:38:57] [PASSED] ttm_bo_unreserve_basic
[13:38:57] [PASSED] ttm_bo_unreserve_pinned
[13:38:57] [PASSED] ttm_bo_unreserve_bulk
[13:38:57] [PASSED] ttm_bo_fini_basic
[13:38:57] [PASSED] ttm_bo_fini_shared_resv
[13:38:57] [PASSED] ttm_bo_pin_basic
[13:38:57] [PASSED] ttm_bo_pin_unpin_resource
[13:38:57] [PASSED] ttm_bo_multiple_pin_one_unpin
[13:38:57] ===================== [PASSED] ttm_bo ======================
[13:38:57] ============== ttm_bo_validate (22 subtests) ===============
[13:38:57] ============== ttm_bo_init_reserved_sys_man ===============
[13:38:57] [PASSED] Buffer object for userspace
[13:38:57] [PASSED] Kernel buffer object
[13:38:57] [PASSED] Shared buffer object
[13:38:57] ========== [PASSED] ttm_bo_init_reserved_sys_man ===========
[13:38:57] ============== ttm_bo_init_reserved_mock_man ==============
[13:38:57] [PASSED] Buffer object for userspace
[13:38:57] [PASSED] Kernel buffer object
[13:38:57] [PASSED] Shared buffer object
[13:38:57] ========== [PASSED] ttm_bo_init_reserved_mock_man ==========
[13:38:57] [PASSED] ttm_bo_init_reserved_resv
[13:38:57] ================== ttm_bo_validate_basic ==================
[13:38:57] [PASSED] Buffer object for userspace
[13:38:57] [PASSED] Kernel buffer object
[13:38:57] [PASSED] Shared buffer object
[13:38:57] ============== [PASSED] ttm_bo_validate_basic ==============
[13:38:57] [PASSED] ttm_bo_validate_invalid_placement
[13:38:57] ============= ttm_bo_validate_same_placement ==============
[13:38:57] [PASSED] System manager
[13:38:57] [PASSED] VRAM manager
[13:38:57] ========= [PASSED] ttm_bo_validate_same_placement ==========
[13:38:57] [PASSED] ttm_bo_validate_failed_alloc
[13:38:57] [PASSED] ttm_bo_validate_pinned
[13:38:57] [PASSED] ttm_bo_validate_busy_placement
[13:38:57] ================ ttm_bo_validate_multihop =================
[13:38:57] [PASSED] Buffer object for userspace
[13:38:57] [PASSED] Kernel buffer object
[13:38:57] [PASSED] Shared buffer object
[13:38:57] ============ [PASSED] ttm_bo_validate_multihop =============
[13:38:57] ========== ttm_bo_validate_no_placement_signaled ==========
[13:38:57] [PASSED] Buffer object in system domain, no page vector
[13:38:57] [PASSED] Buffer object in system domain with an existing page vector
[13:38:57] ====== [PASSED] ttm_bo_validate_no_placement_signaled ======
[13:38:57] ======== ttm_bo_validate_no_placement_not_signaled ========
[13:38:57] [PASSED] Buffer object for userspace
[13:38:57] [PASSED] Kernel buffer object
[13:38:57] [PASSED] Shared buffer object
[13:38:57] ==== [PASSED] ttm_bo_validate_no_placement_not_signaled ====
[13:38:57] [PASSED] ttm_bo_validate_move_fence_signaled
[13:38:57] ========= ttm_bo_validate_move_fence_not_signaled =========
[13:38:57] [PASSED] Waits for GPU
[13:38:57] [PASSED] Tries to lock straight away
[13:38:57] ===== [PASSED] ttm_bo_validate_move_fence_not_signaled =====
[13:38:57] [PASSED] ttm_bo_validate_swapout
[13:38:57] [PASSED] ttm_bo_validate_happy_evict
[13:38:57] [PASSED] ttm_bo_validate_all_pinned_evict
[13:38:57] [PASSED] ttm_bo_validate_allowed_only_evict
[13:38:57] [PASSED] ttm_bo_validate_deleted_evict
[13:38:57] [PASSED] ttm_bo_validate_busy_domain_evict
[13:38:57] [PASSED] ttm_bo_validate_evict_gutting
[13:38:57] [PASSED] ttm_bo_validate_recrusive_evict
[13:38:57] ================= [PASSED] ttm_bo_validate =================
[13:38:57] ============================================================
[13:38:57] Testing complete. Ran 102 tests: passed: 102
[13:38:57] Elapsed time: 12.062s total, 1.812s configuring, 10.034s building, 0.182s running
+ /kernel/tools/testing/kunit/kunit.py run --kunitconfig /kernel/drivers/dma-buf/.kunitconfig
[13:38:58] Configuring KUnit Kernel ...
Regenerating .config ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
[13:38:59] Building KUnit Kernel ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
Building with:
$ make all compile_commands.json scripts_gdb ARCH=um O=.kunit --jobs=48
[13:39:08] Starting KUnit Kernel (1/1)...
[13:39:08] ============================================================
Running tests with:
$ .kunit/linux kunit.enable=1 mem=1G console=tty kunit_shutdown=halt
[13:39:08] =============== dma-buf-fence (12 subtests) ================
[13:39:08] [PASSED] test_sanitycheck
[13:39:08] [PASSED] test_signaling
[13:39:08] [PASSED] test_add_callback
[13:39:08] [PASSED] test_late_add_callback
[13:39:08] [PASSED] test_rm_callback
[13:39:08] [PASSED] test_late_rm_callback
[13:39:08] [PASSED] test_status
[13:39:08] [PASSED] test_error
[13:39:08] [PASSED] test_wait
[13:39:08] [PASSED] test_wait_timeout
[13:39:08] [PASSED] test_stub
[13:39:08] [SKIPPED] test_race_signal_callback (requires at least 2 CPUs)
[13:39:08] ================== [PASSED] dma-buf-fence ==================
[13:39:08] ============ dma-buf-fence-chain (11 subtests) =============
[13:39:08] [PASSED] test_sanitycheck
[13:39:08] [PASSED] test_find_seqno
[13:39:08] [PASSED] test_find_signaled
[13:39:08] [PASSED] test_find_out_of_order
[13:39:13] [PASSED] test_find_gap
[13:39:13] [PASSED] test_find_race
[13:39:13] [PASSED] test_signal_forward
[13:39:13] [PASSED] test_signal_backward
[13:39:13] [PASSED] test_wait_forward
[13:39:13] [PASSED] test_wait_backward
[13:39:13] [PASSED] test_wait_random
[13:39:13] =============== [PASSED] dma-buf-fence-chain ===============
[13:39:13] ============ dma-buf-fence-unwrap (10 subtests) ============
[13:39:13] [PASSED] test_sanitycheck
[13:39:13] [PASSED] test_unwrap_array
[13:39:13] [PASSED] test_unwrap_chain
[13:39:13] [PASSED] test_unwrap_chain_array
[13:39:13] [PASSED] test_unwrap_merge
[13:39:13] [PASSED] test_unwrap_merge_duplicate
[13:39:13] [PASSED] test_unwrap_merge_seqno
[13:39:13] [PASSED] test_unwrap_merge_order
[13:39:13] [PASSED] test_unwrap_merge_complex
[13:39:13] [PASSED] test_unwrap_merge_complex_seqno
[13:39:13] ============== [PASSED] dma-buf-fence-unwrap ===============
[13:39:13] ================ dma-buf-resv (5 subtests) =================
[13:39:13] [PASSED] test_sanitycheck
[13:39:13] ===================== test_signaling ======================
[13:39:13] [PASSED] kernel
[13:39:13] [PASSED] write
[13:39:13] [PASSED] read
[13:39:13] [PASSED] bookkeep
[13:39:13] ================= [PASSED] test_signaling ==================
[13:39:13] ====================== test_for_each ======================
[13:39:13] [PASSED] kernel
[13:39:13] [PASSED] write
[13:39:13] [PASSED] read
[13:39:13] [PASSED] bookkeep
[13:39:13] ================== [PASSED] test_for_each ==================
[13:39:13] ================= test_for_each_unlocked ==================
[13:39:13] [PASSED] kernel
[13:39:13] [PASSED] write
[13:39:13] [PASSED] read
[13:39:13] [PASSED] bookkeep
[13:39:13] ============= [PASSED] test_for_each_unlocked ==============
[13:39:13] ===================== test_get_fences =====================
[13:39:13] [PASSED] kernel
[13:39:13] [PASSED] write
[13:39:13] [PASSED] read
[13:39:13] [PASSED] bookkeep
[13:39:13] ================= [PASSED] test_get_fences =================
[13:39:13] ================== [PASSED] dma-buf-resv ===================
[13:39:13] ============================================================
[13:39:13] Testing complete. Ran 50 tests: passed: 49, skipped: 1
[13:39:13] Elapsed time: 15.743s total, 1.821s configuring, 8.651s building, 5.266s running
+ cleanup
++ stat -c %u:%g /kernel
+ chown -R 1003:1003 /kernel
^ permalink raw reply [flat|nested] 15+ messages in thread
* Re: [PATCH 1/6] drm/xe/devcoredump: Capture GT fuse registers in devcoredump
2026-08-13 13:30 ` [PATCH 1/6] drm/xe/devcoredump: Capture GT fuse registers " Nareshkumar Gollakoti
@ 2026-08-13 13:52 ` sashiko-bot
0 siblings, 0 replies; 15+ messages in thread
From: sashiko-bot @ 2026-08-13 13:52 UTC (permalink / raw)
To: Nareshkumar Gollakoti; +Cc: intel-xe
Thank you for your contribution! Sashiko AI review found 3 potential issue(s) to consider:
- [High] Incorrect GT context passed to fuse capture functions causes MMIO offset corruption and missing forcewake.
- [Medium] Attempting to read PF-only physical fuse registers from a Virtual Function (VF) causes kernel warnings.
- [Medium] Unconditional capture of Media GT fuse registers without verifying if the hardware actually possesses a Media GT.
--
--- Patch [1]: [PATCH 1/6] drm/xe/devcoredump: Capture GT fuse registers in devcoredump ---
commit 83b02d67e48ca9a916843ba3c9656f4f78b755ae
Author: Nareshkumar Gollakoti <naresh.kumar.g@intel.com>
drm/xe/devcoredump: Capture GT fuse registers in devcoredump
This commit captures fuse-related GT register state in the Xe devcoredump to
preserve additional hardware configuration information. It adds generic
register snapshot storage and helpers for capturing and printing MMIO dumps.
> diff --git a/drivers/gpu/drm/xe/xe_devcoredump.c b/drivers/gpu/drm/xe/xe_devcoredump.c
> index 5f2b90b18f97b..35d8101f2a192 100644
> --- a/drivers/gpu/drm/xe/xe_devcoredump.c
> +++ b/drivers/gpu/drm/xe/xe_devcoredump.c
[ ... ]
> +static struct xe_dbg_reg_snapshot *xe_gt_fuse_snapshot_capture(struct xe_gt *gt)
> +{
> + struct xe_reg_desc_list reg_list;
> +
> + if (!xe_dbg_reg_snapshot_is_supported(gt_to_xe(gt)))
> + return NULL;
> +
> + reg_list.regs = xe3p_gt_fuse_reglist;
> + reg_list.num_regs = ARRAY_SIZE(xe3p_gt_fuse_reglist);
> +
> + return xe_dbg_reg_snapshot_capture(gt, ®_list);
> +}
[Severity: Medium]
Will this trigger kernel warnings when running as a Virtual Function (VF)?
If a GPU hang occurs in an SR-IOV VF environment,
xe_gt_fuse_snapshot_capture() calls xe_mmio_read32(), which routes to
xe_gt_sriov_vf_read32(). Since physical fuse registers like RPM_GCD are
PF-only and not on the VF MMIO whitelist, the access is rejected,
potentially polluting the kernel log with warnings for every register.
Should there be an IS_SRIOV_VF() guard before attempting to read PF-only
physical fuse registers?
[ ... ]
> @@ -349,6 +492,9 @@ static void devcoredump_snapshot(struct xe_devcoredump *coredump,
>
> cookie = dma_fence_begin_signalling();
>
> + ss->gt_fuse = xe_gt_fuse_snapshot_capture(q->gt);
> + ss->media_fuse = xe_media_gt_fuse_snapshot_capture(q->gt);
[Severity: High]
Does this pass the wrong GT context to the capture functions when the fault is
on the Media GT?
The faulting q->gt is passed unconditionally to both captures. xe_mmio_read32()
automatically adds a 0x380000 offset to register addresses when invoked on the
Media GT. If q->gt is the Media GT, xe_gt_fuse_snapshot_capture() will
erroneously capture Media GT registers instead of Primary GT registers.
Additionally, devcoredump only holds forcewake for the faulting q->gt. If
q->gt is the Primary GT, xe_media_gt_fuse_snapshot_capture() will attempt
to read Media GT registers while the Media GT is asleep, causing Unclaimed
Register errors and returning garbage data.
Should it capture using the specific primary and media GTs with appropriate
forcewake?
[Severity: Medium]
What happens on hardware configurations that do not possess a Media GT?
The unconditional call to xe_media_gt_fuse_snapshot_capture() attempts to
read registers at offset 0x380000. If the Media GT is physically absent or
fused off on the SKU, would this result in Unclaimed Register hardware errors
and system log spam?
Should there be a check for the existence of a Media GT before attempting
the capture?
> +
> ss->guc.log = xe_guc_log_snapshot_capture(&guc->log, true);
> ss->guc.ct = xe_guc_ct_snapshot_capture(&guc->ct);
--
Sashiko AI review · https://sashiko.dev/#/patchset/20260813133037.2912699-1-naresh.kumar.g@intel.com?part=1
^ permalink raw reply [flat|nested] 15+ messages in thread
* Re: [PATCH 2/6] drm/xe/devcoredump: Add GuC register snapshot to devcoredump
2026-08-13 13:30 ` [PATCH 2/6] drm/xe/devcoredump: Add GuC register snapshot to devcoredump Nareshkumar Gollakoti
@ 2026-08-13 14:04 ` sashiko-bot
0 siblings, 0 replies; 15+ messages in thread
From: sashiko-bot @ 2026-08-13 14:04 UTC (permalink / raw)
To: Nareshkumar Gollakoti; +Cc: intel-xe
Thank you for your contribution! Sashiko AI review found 3 potential issue(s) to consider:
- [High] Devcoredump captures GuC registers using the wrong GT's MMIO and forcewake context, leading to duplicated media GT captures, missing primary GT captures, and potential hardware timeouts.
- [High] Unconditional reading of restricted GuC registers during devcoredump capture can cause MMIO timeouts or hardware failures on SR-IOV Virtual Functions.
- [High] Devcoredump fails to capture the primary GT fuse registers when a hang occurs on the media GT, and accesses media fuses without forcewake when a hang occurs on the primary GT.
--
--- Patch [2]: [PATCH 2/6] drm/xe/devcoredump: Add GuC register snapshot to devcoredump ---
commit ec31bf15e0d277f5f7b46d37e62dd0788024eecc
Author: Nareshkumar Gollakoti <naresh.kumar.g@intel.com>
drm/xe/devcoredump: Add GuC register snapshot to devcoredump
Add support for capturing GuC register state as part of the xe
devcoredump snapshot.
> diff --git a/drivers/gpu/drm/xe/regs/xe_guc_regs.h b/drivers/gpu/drm/xe/regs/xe_guc_regs.h
> --- a/drivers/gpu/drm/xe/regs/xe_guc_regs.h
> +++ b/drivers/gpu/drm/xe/regs/xe_guc_regs.h
> @@ -150,6 +150,19 @@
> #define GUC_INTR_SW_INT_1 REG_BIT(1)
> #define GUC_INTR_SW_INT_0 REG_BIT(0)
>
> +#define GUC_DEVICEID XE_REG(0xc008)
> +#define GUC_SHIM_ERR_TRAP XE_REG(0xc070)
> +#define GUC_HW_FATL_ERR XE_REG(0xc598)
> +#define GUC_HW_NOTIFY_ERR XE_REG(0xc59c)
> +
> +#define GUC_STATUS_M XE_REG(0x38c000)
[Severity: High]
By defining hardcoded media GT register addresses like GUC_STATUS_M above
the adj_limit, won't they bypass MMIO adjustment? This could cause them
to behave differently than primary registers when passed a media GT.
> +#define GUC_WOPCM_SIZE_M XE_REG(0x38c050)
> +#define GUC_DEVICEID_M XE_REG(0x38c008)
> +#define DMA_CTRL_M XE_REG(0x38c314)
> +#define GUC_HW_FATL_ERR_M XE_REG(0x38c598)
> +#define GUC_HW_NOTIFY_ERR_M XE_REG(0x38c59c)
> +#define GUC_SHIM_ERR_TRAP_M XE_REG(0x38c070)
> +
> diff --git a/drivers/gpu/drm/xe/xe_devcoredump.c b/drivers/gpu/drm/xe/xe_devcoredump.c
> --- a/drivers/gpu/drm/xe/xe_devcoredump.c
> +++ b/drivers/gpu/drm/xe/xe_devcoredump.c
[ ... ]
> @@ -201,6 +222,32 @@ static struct xe_dbg_reg_snapshot *xe_media_gt_fuse_snapshot_capture(struct xe_g
> return xe_dbg_reg_snapshot_capture(gt, ®_list);
> }
>
> +static struct xe_dbg_reg_snapshot *xe_gt_guc_reg_snapshot_capture(struct xe_gt *gt)
> +{
> + struct xe_reg_desc_list reg_list;
> +
> + if (!xe_dbg_reg_snapshot_is_supported(gt_to_xe(gt)))
> + return NULL;
[Severity: High]
Does this code need an IS_SRIOV_VF() check before capturing GuC registers?
According to the driver pattern for other hardware controllers, accessing
PF-only hardware resources from an SR-IOV Virtual Function causes MMIO
timeouts. If a GPU hang on an SR-IOV VF triggers devcoredump_snapshot(),
this unconditional read might cause a timeout.
> +
> + reg_list.regs = xe_gt_guc_reg_list;
> + reg_list.num_regs = ARRAY_SIZE(xe_gt_guc_reg_list);
> +
> + return xe_dbg_reg_snapshot_capture(gt, ®_list);
> +}
> +
> +static struct xe_dbg_reg_snapshot *xe_media_gt_guc_reg_snapshot_capture(struct xe_gt *gt)
> +{
> + struct xe_reg_desc_list reg_list;
> +
> + if (!xe_dbg_reg_snapshot_is_supported(gt_to_xe(gt)))
> + return NULL;
[Severity: High]
Does the media GT GuC capture also need a VF check to prevent MMIO timeouts
when running as a guest VM user?
> +
> + reg_list.regs = xe_media_gt_guc_reg_list;
> + reg_list.num_regs = ARRAY_SIZE(xe_media_gt_guc_reg_list);
> +
> + return xe_dbg_reg_snapshot_capture(gt, ®_list);
> +}
[ ... ]
> @@ -495,6 +553,8 @@ static void devcoredump_snapshot(struct xe_devcoredump *coredump,
> ss->gt_fuse = xe_gt_fuse_snapshot_capture(q->gt);
> ss->media_fuse = xe_media_gt_fuse_snapshot_capture(q->gt);
[Severity: High]
This isn't a bug introduced by this patch, but does capturing both primary
and media GT fuses using the same faulting queue GT (q->gt) cause MMIO
aliasing and missing forcewake?
When the hang is on the primary GT, reading media fuses could happen without
holding the media GT's forcewake domain, risking an MMIO timeout. When on
the media GT, primary fuse reads might be translated by the media GT's
adj_offset, failing to capture the primary GT fuses.
> +
> + ss->gt_guc_reg = xe_gt_guc_reg_snapshot_capture(q->gt);
> + ss->media_gt_guc_reg = xe_media_gt_guc_reg_snapshot_capture(q->gt);
[Severity: High]
Will passing the faulting queue's GT (q->gt) to both primary and media GuC
captures cause similar MMIO aliasing and missing forcewake issues?
If the hang is on the primary GT, reading media GuC registers could occur
without acquiring the media GT's forcewake domain, which may trigger MMIO
timeouts. If the hang is on the media GT, reading primary GuC registers
would be shifted by the media GT's adj_offset (0x380000), causing it to
erroneously read the media GuC registers again and completely lose the
primary GuC state.
> ss->guc.log = xe_guc_log_snapshot_capture(&guc->log, true);
> ss->guc.ct = xe_guc_ct_snapshot_capture(&guc->ct);
> ss->ge = xe_guc_exec_queue_snapshot_capture(q);
--
Sashiko AI review · https://sashiko.dev/#/patchset/20260813133037.2912699-1-naresh.kumar.g@intel.com?part=2
^ permalink raw reply [flat|nested] 15+ messages in thread
* Re: [PATCH 3/6] drm/xe/guc: Print register addresses in capture snapshot output
2026-08-13 13:30 ` [PATCH 3/6] drm/xe/guc: Print register addresses in capture snapshot output Nareshkumar Gollakoti
@ 2026-08-13 14:11 ` sashiko-bot
0 siblings, 0 replies; 15+ messages in thread
From: sashiko-bot @ 2026-08-13 14:11 UTC (permalink / raw)
To: Nareshkumar Gollakoti; +Cc: intel-xe
Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [Medium] Mismatched MMIO offset printed for 64-bit registers.
--
--- Patch [3]: [PATCH 3/6] drm/xe/guc: Print register addresses in capture snapshot output ---
commit 4cd73ae81306dc6a8f6e5245b976fc6aed0e2134
Author: Nareshkumar Gollakoti <naresh.kumar.g@intel.com>
drm/xe/guc: Print register addresses in capture snapshot output
This commit updates the GuC capture snapshot printing logic to include the
register's MMIO offset alongside its name and value. This makes the output
easier to cross-reference with hardware debug documentation.
> diff --git a/drivers/gpu/drm/xe/xe_guc_capture.c b/drivers/gpu/drm/xe/xe_guc_capture.c
> index 82df19b304e17..368769857c9b8 100644
> --- a/drivers/gpu/drm/xe/xe_guc_capture.c
> +++ b/drivers/gpu/drm/xe/xe_guc_capture.c
> @@ -1774,7 +1774,9 @@ snapshot_print_by_list_order(struct xe_hw_engine_snapshot *snapshot, struct drm_
> XE_WARN_ON(!low32_ready);
> low32_ready = false;
>
> - drm_printf(p, "\t%s: 0x%016llx\n", reg_desc->regname, value_qw);
> + drm_printf(p, "\t%s (0x%x): 0x%016llx\n", reg_desc->regname,
> + reg_desc->reg.addr,
> + value_qw);
[Severity: Medium]
Will this print the MMIO offset of the upper 32-bit register (HI_DW) instead
of the base address (LOW_DW)?
In snapshot_print_by_list_order() in drivers/gpu/drm/xe/xe_guc_capture.c,
the REG_64BIT_HI_DW case is processing the second entry of a 64-bit register
pair. Because it uses reg_desc->reg.addr from the HI_DW descriptor, the
printed output pairs the combined 64-bit value with the offset of the upper
32-bit register.
Could this regression cause confusion when cross-referencing the offset with
hardware documentation, which typically expects the base offset for a 64-bit
register?
--
Sashiko AI review · https://sashiko.dev/#/patchset/20260813133037.2912699-1-naresh.kumar.g@intel.com?part=3
^ permalink raw reply [flat|nested] 15+ messages in thread
* Re: [PATCH 5/6] drm/xe/guc: add TDL gfx registers to capture list
2026-08-13 13:30 ` [PATCH 5/6] drm/xe/guc: add TDL gfx registers to capture list Nareshkumar Gollakoti
@ 2026-08-13 14:25 ` sashiko-bot
0 siblings, 0 replies; 15+ messages in thread
From: sashiko-bot @ 2026-08-13 14:25 UTC (permalink / raw)
To: Nareshkumar Gollakoti; +Cc: intel-xe
Thank you for your contribution! Sashiko AI review found 2 potential issue(s) to consider:
- [Medium] Typographical error in register name 'ROW_INSDONE_TDL_GFX' (missing 'T' in 'INSTDONE').
- [Low] Improper indentation using spaces instead of tabs.
--
--- Patch [5]: [PATCH 5/6] drm/xe/guc: add TDL gfx registers to capture list ---
commit 3c0be61d6ad550502777320cdeb9da502f084893
Author: Nareshkumar Gollakoti <naresh.kumar.g@intel.com>
drm/xe/guc: add TDL gfx registers to capture list
Add ROW_INSDONE_TDL_GFX and SS_LSC_HDC_IDLE_TDL_GFX register
definitions and include them in the XeHPG extended GuC capture register
list.
> diff --git a/drivers/gpu/drm/xe/regs/xe_gt_regs.h b/drivers/gpu/drm/xe/regs/xe_gt_regs.h
> index 25014bccd3a69..8c55d766a5a63 100644
> --- a/drivers/gpu/drm/xe/regs/xe_gt_regs.h
> +++ b/drivers/gpu/drm/xe/regs/xe_gt_regs.h
> @@ -572,6 +572,9 @@
> #define EU_SYSTOLIC_LIC_THROTTLE_CTL_WITH_LOCK XE_REG_MCR(0xe534)
> #define EU_SYSTOLIC_LIC_THROTTLE_CTL_LOCK_BIT REG_BIT(31)
>
> +#define ROW_INSDONE_TDL_GFX XE_REG_MCR(0xe580)
^^^^^^^^^^^^^^^^^^^
[Severity: Medium]
This isn't a bug, but there seems to be a typo in the register name.
Should this be ROW_INSTDONE_TDL_GFX (missing 'T' in INSTDONE)? If userspace
telemetry and GPU hang analysis tools rely on substring matching for
'INSTDONE', they will silently miss this register.
> +#define SS_LSC_HDC_IDLE_TDL_GFX XE_REG_MCR(0xe584)
[Severity: Low]
This isn't a bug, but it looks like these definitions use spaces instead of
tabs for alignment, unlike the surrounding macros.
[ ... ]
> diff --git a/drivers/gpu/drm/xe/xe_guc_capture.c b/drivers/gpu/drm/xe/xe_guc_capture.c
> index 368769857c9b8..a6052da717878 100644
> --- a/drivers/gpu/drm/xe/xe_guc_capture.c
> +++ b/drivers/gpu/drm/xe/xe_guc_capture.c
> @@ -376,7 +376,9 @@ static const struct __ext_steer_reg xehpg_extregs[] = {
> {"SC_INSTDONE", XEHPG_SC_INSTDONE},
> {"SC_INSTDONE_EXTRA", XEHPG_SC_INSTDONE_EXTRA},
> {"SC_INSTDONE_EXTRA2", XEHPG_SC_INSTDONE_EXTRA2},
> - {"INSTDONE_GEOM_SVGUNIT", XEHPG_INSTDONE_GEOM_SVGUNIT}
> + {"INSTDONE_GEOM_SVGUNIT", XEHPG_INSTDONE_GEOM_SVGUNIT},
> + {"ROW_INSDONE_TDL_GFX", ROW_INSDONE_TDL_GFX},
^^^^^^^^^^^^^^^^^^^^^
[Severity: Medium]
Since this string name is exported to userspace and GuC capture tools, will
the misspelled "INSDONE" break tooling expectations that look for "INSTDONE"?
> + {"SS_LSC_HDC_IDLE_TDL_GFX", SS_LSC_HDC_IDLE_TDL_GFX}
> };
>
--
Sashiko AI review · https://sashiko.dev/#/patchset/20260813133037.2912699-1-naresh.kumar.g@intel.com?part=5
^ permalink raw reply [flat|nested] 15+ messages in thread
* ✓ Xe.CI.BAT: success for drm/xe: Capture additional HW register state in devcoredump
2026-08-13 13:30 [PATCH 0/6] drm/xe: Capture additional HW register state in devcoredump Nareshkumar Gollakoti
` (6 preceding siblings ...)
2026-08-13 13:39 ` ✓ CI.KUnit: success for drm/xe: Capture additional HW register state " Patchwork
@ 2026-08-13 14:27 ` Patchwork
2026-08-13 15:58 ` ✗ Xe.CI.FULL: failure " Patchwork
8 siblings, 0 replies; 15+ messages in thread
From: Patchwork @ 2026-08-13 14:27 UTC (permalink / raw)
To: Nareshkumar Gollakoti; +Cc: intel-xe
[-- Attachment #1: Type: text/plain, Size: 973 bytes --]
== Series Details ==
Series: drm/xe: Capture additional HW register state in devcoredump
URL : https://patchwork.freedesktop.org/series/172150/
State : success
== Summary ==
CI Bug Log - changes from xe-5589-c194081ec71ea95135c7f9ddbc7d02e9c8cad19a_BAT -> xe-pw-172150v1_BAT
====================================================
Summary
-------
**SUCCESS**
No regressions found.
Participating hosts (13 -> 13)
------------------------------
No changes in participating hosts
Changes
-------
No changes found
Build changes
-------------
* Linux: xe-5589-c194081ec71ea95135c7f9ddbc7d02e9c8cad19a -> xe-pw-172150v1
IGT_9054: 3d819a8f511b2bcd844647bcf7e433b9407d058e @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
xe-5589-c194081ec71ea95135c7f9ddbc7d02e9c8cad19a: c194081ec71ea95135c7f9ddbc7d02e9c8cad19a
xe-pw-172150v1: 172150v1
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-172150v1/index.html
[-- Attachment #2: Type: text/html, Size: 1521 bytes --]
^ permalink raw reply [flat|nested] 15+ messages in thread
* Re: [PATCH 6/6] drm/xe: capture L3 node status registers in devcoredump
2026-08-13 13:30 ` [PATCH 6/6] drm/xe: capture L3 node status registers in devcoredump Nareshkumar Gollakoti
@ 2026-08-13 14:37 ` sashiko-bot
0 siblings, 0 replies; 15+ messages in thread
From: sashiko-bot @ 2026-08-13 14:37 UTC (permalink / raw)
To: Nareshkumar Gollakoti; +Cc: intel-xe
Thank you for your contribution! Sashiko AI review found 2 potential issue(s) to consider:
- [High] Capturing MCR registers in the devcoredump snapshot triggers a kernel assertion failure (BUG/WARN) when executed in an SR-IOV Virtual Function (VF) environment.
- [Medium] MCR registers are incorrectly defined as regular `XE_REG` instead of `XE_REG_MCR`, bypassing the subsystem's compile-time type safety.
--
--- Patch [6]: [PATCH 6/6] drm/xe: capture L3 node status registers in devcoredump ---
commit a45fb5f7ed9065191b925af139e27c7fca72cb39
Author: Nareshkumar Gollakoti <naresh.kumar.g@intel.com>
drm/xe: capture L3 node status registers in devcoredump
This commit adds L3_NODE_IDLE and L3STAT_LBCF_GFX register definitions
and includes them in the devcoredump node status section. It also
extends the register descriptor to mark MCR registers, allowing the
snapshot code to read them using xe_gt_mcr_unicast_read_any().
> diff --git a/drivers/gpu/drm/xe/regs/xe_gt_regs.h b/drivers/gpu/drm/xe/regs/xe_gt_regs.h
> index 8c55d766a5a63..fdd0817919617 100644
> --- a/drivers/gpu/drm/xe/regs/xe_gt_regs.h
> +++ b/drivers/gpu/drm/xe/regs/xe_gt_regs.h
> @@ -430,6 +430,9 @@
> #define L3_ESC_MASK REG_BIT(0)
> #define L3_ESC(value) REG_FIELD_PREP(L3_ESC_MASK, value)
>
> +#define L3_NODE_IDLE XE_REG(0xb0b0)
> +#define L3STAT_LBCF_GFX XE_REG(0xb128)
> +
[Severity: Medium]
Should these registers be defined using XE_REG_MCR instead of XE_REG?
Defining them with XE_REG bypasses the compile-time type safety intended
for multicast/replicated registers.
> #define XEHP_L3NODEARBCFG XE_REG_MCR(0xb0b4)
> #define XEHP_LNESPARE REG_BIT(19)
[ ... ]
> diff --git a/drivers/gpu/drm/xe/xe_devcoredump.c b/drivers/gpu/drm/xe/xe_devcoredump.c
> index 6cc4e3969417e..ab8cd7d589646 100644
> --- a/drivers/gpu/drm/xe/xe_devcoredump.c
> +++ b/drivers/gpu/drm/xe/xe_devcoredump.c
[ ... ]
> @@ -83,6 +84,8 @@ struct xe_reg_desc {
> struct xe_reg reg;
> /** @name: Name of the register */
> const char *name;
> + /** @mcr: mcr type registers */
> + bool mcr;
> };
[Severity: Medium]
Does adding this boolean flag subvert the existing type safety architecture?
The struct xe_reg already contains an mcr bitfield which is automatically
populated when registers are correctly defined with XE_REG_MCR. Adding a
separate flag forces the code to manually cast the address back into an MCR
register at runtime, losing the intended compiler type checks.
[ ... ]
> @@ -156,7 +164,12 @@ xe_capture_reg_desc_list(struct xe_gt *gt,
>
> for (i = 0; i < count; i++) {
> dst[i].reg = src[i].reg;
> - dst[i].value = xe_mmio_read32(>->mmio, src[i].reg);
> + if (src[i].mcr)
> + dst[i].value = xe_gt_mcr_unicast_read_any(gt,
> + XE_REG_MCR
> + (src[i].reg.addr));
> + else
> + dst[i].value = xe_mmio_read32(>->mmio, src[i].reg);
> dst[i].name = src[i].name;
> }
> }
[Severity: High]
Can this path trigger a kernel assertion failure in an SR-IOV Virtual Function
environment?
Looking at xe_gt_mcr_unicast_read_any, it contains an explicit guard against
execution in a VF:
xe_gt_mcr_unicast_read_any(struct xe_gt *gt, struct xe_reg_mcr reg_mcr)
{
...
xe_gt_assert(gt, !IS_SRIOV_VF(gt_to_xe(gt)));
...
}
Because devcoredumps can be triggered by unprivileged VF workloads causing a
GPU hang, executing this read could lead to unauthorized attempts to access
privileged steering registers, potentially causing MMIO timeouts and undefined
driver behavior.
[ ... ]
> @@ -266,6 +279,19 @@ static struct xe_dbg_reg_snapshot *xe_gam_pf_report_capture(struct xe_gt *gt)
> return xe_dbg_reg_snapshot_capture(gt, ®_list);
> }
>
> +static struct xe_dbg_reg_snapshot *xe_node_status_capture(struct xe_gt *gt)
> +{
> + struct xe_reg_desc_list reg_list;
> +
> + if (!xe_dbg_reg_snapshot_is_supported(gt_to_xe(gt)))
> + return NULL;
> +
> + reg_list.regs = xe3p_l3_node_reglist;
> + reg_list.num_regs = ARRAY_SIZE(xe3p_l3_node_reglist);
> +
> + return xe_dbg_reg_snapshot_capture(gt, ®_list);
> +}
[Severity: High]
Should this capture function include an early return guard for VFs?
Since capturing MCR registers is a PF-only operation, omitting an
IS_SRIOV_VF check here allows the snapshot code to unconditionally attempt
MCR reads, leading to the assertion failure mentioned above.
--
Sashiko AI review · https://sashiko.dev/#/patchset/20260813133037.2912699-1-naresh.kumar.g@intel.com?part=6
^ permalink raw reply [flat|nested] 15+ messages in thread
* ✗ Xe.CI.FULL: failure for drm/xe: Capture additional HW register state in devcoredump
2026-08-13 13:30 [PATCH 0/6] drm/xe: Capture additional HW register state in devcoredump Nareshkumar Gollakoti
` (7 preceding siblings ...)
2026-08-13 14:27 ` ✓ Xe.CI.BAT: " Patchwork
@ 2026-08-13 15:58 ` Patchwork
8 siblings, 0 replies; 15+ messages in thread
From: Patchwork @ 2026-08-13 15:58 UTC (permalink / raw)
To: Nareshkumar Gollakoti; +Cc: intel-xe
[-- Attachment #1: Type: text/plain, Size: 18730 bytes --]
== Series Details ==
Series: drm/xe: Capture additional HW register state in devcoredump
URL : https://patchwork.freedesktop.org/series/172150/
State : failure
== Summary ==
CI Bug Log - changes from xe-5589-c194081ec71ea95135c7f9ddbc7d02e9c8cad19a_FULL -> xe-pw-172150v1_FULL
====================================================
Summary
-------
**FAILURE**
Serious unknown changes coming with xe-pw-172150v1_FULL absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in xe-pw-172150v1_FULL, please notify your bug team (I915-ci-infra@lists.freedesktop.org) to allow them
to document this new failure mode, which will reduce false positives in CI.
Participating hosts (2 -> 2)
------------------------------
No changes in participating hosts
Possible new issues
-------------------
Here are the unknown changes that may have been introduced in xe-pw-172150v1_FULL:
### IGT changes ###
#### Possible regressions ####
* igt@xe_exec_capture@reset:
- shard-lnl: [PASS][1] -> [FAIL][2]
[1]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5589-c194081ec71ea95135c7f9ddbc7d02e9c8cad19a/shard-lnl-4/igt@xe_exec_capture@reset.html
[2]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-172150v1/shard-lnl-4/igt@xe_exec_capture@reset.html
- shard-bmg: [PASS][3] -> [FAIL][4]
[3]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5589-c194081ec71ea95135c7f9ddbc7d02e9c8cad19a/shard-bmg-10/igt@xe_exec_capture@reset.html
[4]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-172150v1/shard-bmg-8/igt@xe_exec_capture@reset.html
#### Warnings ####
* igt@kms_pm_rpm@modeset-lpsp-stress:
- shard-bmg: [SKIP][5] ([Intel XE#1439] / [Intel XE#3141] / [Intel XE#7383] / [Intel XE#836]) -> [SKIP][6]
[5]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5589-c194081ec71ea95135c7f9ddbc7d02e9c8cad19a/shard-bmg-9/igt@kms_pm_rpm@modeset-lpsp-stress.html
[6]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-172150v1/shard-bmg-5/igt@kms_pm_rpm@modeset-lpsp-stress.html
Known issues
------------
Here are the changes found in xe-pw-172150v1_FULL that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@kms_ccs@crc-primary-suspend-4-tiled-bmg-ccs:
- shard-bmg: [PASS][7] -> [INCOMPLETE][8] ([Intel XE#7084] / [Intel XE#8150]) +1 other test incomplete
[7]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5589-c194081ec71ea95135c7f9ddbc7d02e9c8cad19a/shard-bmg-5/igt@kms_ccs@crc-primary-suspend-4-tiled-bmg-ccs.html
[8]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-172150v1/shard-bmg-3/igt@kms_ccs@crc-primary-suspend-4-tiled-bmg-ccs.html
* igt@kms_flip@flip-vs-expired-vblank@a-edp1:
- shard-lnl: [PASS][9] -> [FAIL][10] ([Intel XE#301]) +2 other tests fail
[9]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5589-c194081ec71ea95135c7f9ddbc7d02e9c8cad19a/shard-lnl-7/igt@kms_flip@flip-vs-expired-vblank@a-edp1.html
[10]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-172150v1/shard-lnl-4/igt@kms_flip@flip-vs-expired-vblank@a-edp1.html
* igt@xe_evict@evict-mixed-many-threads-small:
- shard-bmg: [PASS][11] -> [INCOMPLETE][12] ([Intel XE#6321] / [Intel XE#8355])
[11]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5589-c194081ec71ea95135c7f9ddbc7d02e9c8cad19a/shard-bmg-4/igt@xe_evict@evict-mixed-many-threads-small.html
[12]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-172150v1/shard-bmg-9/igt@xe_evict@evict-mixed-many-threads-small.html
* igt@xe_exec_system_allocator@process-many-large-execqueues-malloc-race:
- shard-bmg: [PASS][13] -> [SKIP][14] ([Intel XE#8589]) +99 other tests skip
[13]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5589-c194081ec71ea95135c7f9ddbc7d02e9c8cad19a/shard-bmg-9/igt@xe_exec_system_allocator@process-many-large-execqueues-malloc-race.html
[14]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-172150v1/shard-bmg-5/igt@xe_exec_system_allocator@process-many-large-execqueues-malloc-race.html
* igt@xe_exec_system_allocator@process-many-mmap-new-huge-nomemset:
- shard-bmg: [PASS][15] -> [DMESG-FAIL][16] ([Intel XE#6652] / [Intel XE#7774])
[15]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5589-c194081ec71ea95135c7f9ddbc7d02e9c8cad19a/shard-bmg-9/igt@xe_exec_system_allocator@process-many-mmap-new-huge-nomemset.html
[16]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-172150v1/shard-bmg-5/igt@xe_exec_system_allocator@process-many-mmap-new-huge-nomemset.html
* igt@xe_pmu@engine-activity-accuracy-90@engine-drm_xe_engine_class_render0:
- shard-bmg: [PASS][17] -> [FAIL][18] ([Intel XE#8555]) +1 other test fail
[17]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5589-c194081ec71ea95135c7f9ddbc7d02e9c8cad19a/shard-bmg-6/igt@xe_pmu@engine-activity-accuracy-90@engine-drm_xe_engine_class_render0.html
[18]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-172150v1/shard-bmg-2/igt@xe_pmu@engine-activity-accuracy-90@engine-drm_xe_engine_class_render0.html
#### Possible fixes ####
* igt@kms_hdr@invalid-hdr:
- shard-bmg: [SKIP][19] ([Intel XE#1503]) -> [PASS][20]
[19]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5589-c194081ec71ea95135c7f9ddbc7d02e9c8cad19a/shard-bmg-5/igt@kms_hdr@invalid-hdr.html
[20]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-172150v1/shard-bmg-8/igt@kms_hdr@invalid-hdr.html
#### Warnings ####
* igt@kms_big_fb@y-tiled-8bpp-rotate-0:
- shard-bmg: [SKIP][21] ([Intel XE#1124]) -> [SKIP][22] ([Intel XE#8589])
[21]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5589-c194081ec71ea95135c7f9ddbc7d02e9c8cad19a/shard-bmg-9/igt@kms_big_fb@y-tiled-8bpp-rotate-0.html
[22]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-172150v1/shard-bmg-5/igt@kms_big_fb@y-tiled-8bpp-rotate-0.html
* igt@kms_bw@connected-linear-tiling-3-displays-target-1920x1080p:
- shard-bmg: [SKIP][23] ([Intel XE#7679]) -> [SKIP][24] ([Intel XE#8589])
[23]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5589-c194081ec71ea95135c7f9ddbc7d02e9c8cad19a/shard-bmg-9/igt@kms_bw@connected-linear-tiling-3-displays-target-1920x1080p.html
[24]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-172150v1/shard-bmg-5/igt@kms_bw@connected-linear-tiling-3-displays-target-1920x1080p.html
* igt@kms_ccs@crc-primary-rotation-180-y-tiled-gen12-rc-ccs:
- shard-bmg: [SKIP][25] ([Intel XE#2887]) -> [SKIP][26] ([Intel XE#8589]) +1 other test skip
[25]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5589-c194081ec71ea95135c7f9ddbc7d02e9c8cad19a/shard-bmg-9/igt@kms_ccs@crc-primary-rotation-180-y-tiled-gen12-rc-ccs.html
[26]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-172150v1/shard-bmg-5/igt@kms_ccs@crc-primary-rotation-180-y-tiled-gen12-rc-ccs.html
* igt@kms_chamelium_color@ctm-0-50:
- shard-bmg: [SKIP][27] ([Intel XE#2325] / [Intel XE#7358]) -> [SKIP][28] ([Intel XE#8589])
[27]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5589-c194081ec71ea95135c7f9ddbc7d02e9c8cad19a/shard-bmg-9/igt@kms_chamelium_color@ctm-0-50.html
[28]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-172150v1/shard-bmg-5/igt@kms_chamelium_color@ctm-0-50.html
* igt@kms_chamelium_edid@hdmi-mode-timings:
- shard-bmg: [SKIP][29] ([Intel XE#2252]) -> [SKIP][30] ([Intel XE#8589])
[29]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5589-c194081ec71ea95135c7f9ddbc7d02e9c8cad19a/shard-bmg-9/igt@kms_chamelium_edid@hdmi-mode-timings.html
[30]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-172150v1/shard-bmg-5/igt@kms_chamelium_edid@hdmi-mode-timings.html
* igt@kms_content_protection@atomic-dpms-hdcp14:
- shard-bmg: [FAIL][31] ([Intel XE#3304] / [Intel XE#7374]) -> [SKIP][32] ([Intel XE#8589])
[31]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5589-c194081ec71ea95135c7f9ddbc7d02e9c8cad19a/shard-bmg-9/igt@kms_content_protection@atomic-dpms-hdcp14.html
[32]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-172150v1/shard-bmg-5/igt@kms_content_protection@atomic-dpms-hdcp14.html
* igt@kms_cursor_crc@cursor-sliding-32x10:
- shard-bmg: [SKIP][33] ([Intel XE#2320]) -> [SKIP][34] ([Intel XE#8589]) +1 other test skip
[33]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5589-c194081ec71ea95135c7f9ddbc7d02e9c8cad19a/shard-bmg-9/igt@kms_cursor_crc@cursor-sliding-32x10.html
[34]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-172150v1/shard-bmg-5/igt@kms_cursor_crc@cursor-sliding-32x10.html
* igt@kms_feature_discovery@dp-mst:
- shard-bmg: [SKIP][35] ([Intel XE#2375]) -> [SKIP][36] ([Intel XE#8589])
[35]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5589-c194081ec71ea95135c7f9ddbc7d02e9c8cad19a/shard-bmg-9/igt@kms_feature_discovery@dp-mst.html
[36]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-172150v1/shard-bmg-5/igt@kms_feature_discovery@dp-mst.html
* igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-indfb-plflip-blt:
- shard-bmg: [SKIP][37] ([Intel XE#4141]) -> [SKIP][38] ([Intel XE#8589]) +2 other tests skip
[37]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5589-c194081ec71ea95135c7f9ddbc7d02e9c8cad19a/shard-bmg-9/igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-indfb-plflip-blt.html
[38]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-172150v1/shard-bmg-5/igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-indfb-plflip-blt.html
* igt@kms_frontbuffer_tracking@fbcdrrs-2p-primscrn-spr-indfb-draw-render:
- shard-bmg: [SKIP][39] ([Intel XE#2311]) -> [SKIP][40] ([Intel XE#8589]) +8 other tests skip
[39]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5589-c194081ec71ea95135c7f9ddbc7d02e9c8cad19a/shard-bmg-9/igt@kms_frontbuffer_tracking@fbcdrrs-2p-primscrn-spr-indfb-draw-render.html
[40]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-172150v1/shard-bmg-5/igt@kms_frontbuffer_tracking@fbcdrrs-2p-primscrn-spr-indfb-draw-render.html
* igt@kms_frontbuffer_tracking@psrhdr-1p-offscreen-pri-indfb-draw-mmap-wc:
- shard-bmg: [SKIP][41] ([Intel XE#2313]) -> [SKIP][42] ([Intel XE#8589]) +6 other tests skip
[41]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5589-c194081ec71ea95135c7f9ddbc7d02e9c8cad19a/shard-bmg-9/igt@kms_frontbuffer_tracking@psrhdr-1p-offscreen-pri-indfb-draw-mmap-wc.html
[42]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-172150v1/shard-bmg-5/igt@kms_frontbuffer_tracking@psrhdr-1p-offscreen-pri-indfb-draw-mmap-wc.html
* igt@kms_joiner@invalid-modeset-big-joiner:
- shard-bmg: [SKIP][43] ([Intel XE#6901]) -> [SKIP][44] ([Intel XE#8589])
[43]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5589-c194081ec71ea95135c7f9ddbc7d02e9c8cad19a/shard-bmg-9/igt@kms_joiner@invalid-modeset-big-joiner.html
[44]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-172150v1/shard-bmg-5/igt@kms_joiner@invalid-modeset-big-joiner.html
* igt@kms_psr2_su@frontbuffer-xrgb8888:
- shard-bmg: [SKIP][45] ([Intel XE#2387] / [Intel XE#7429]) -> [SKIP][46] ([Intel XE#8589])
[45]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5589-c194081ec71ea95135c7f9ddbc7d02e9c8cad19a/shard-bmg-9/igt@kms_psr2_su@frontbuffer-xrgb8888.html
[46]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-172150v1/shard-bmg-5/igt@kms_psr2_su@frontbuffer-xrgb8888.html
* igt@kms_psr@psr2-primary-blt:
- shard-bmg: [SKIP][47] ([Intel XE#2234] / [Intel XE#2850]) -> [SKIP][48] ([Intel XE#8589])
[47]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5589-c194081ec71ea95135c7f9ddbc7d02e9c8cad19a/shard-bmg-9/igt@kms_psr@psr2-primary-blt.html
[48]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-172150v1/shard-bmg-5/igt@kms_psr@psr2-primary-blt.html
* igt@kms_vrr@seamless-rr-switch-vrr:
- shard-bmg: [SKIP][49] ([Intel XE#1499]) -> [SKIP][50] ([Intel XE#8589])
[49]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5589-c194081ec71ea95135c7f9ddbc7d02e9c8cad19a/shard-bmg-9/igt@kms_vrr@seamless-rr-switch-vrr.html
[50]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-172150v1/shard-bmg-5/igt@kms_vrr@seamless-rr-switch-vrr.html
* igt@xe_exec_fault_mode@many-execqueues-multi-queue-userptr-rebind-prefetch:
- shard-bmg: [SKIP][51] ([Intel XE#8374]) -> [SKIP][52] ([Intel XE#8589])
[51]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5589-c194081ec71ea95135c7f9ddbc7d02e9c8cad19a/shard-bmg-9/igt@xe_exec_fault_mode@many-execqueues-multi-queue-userptr-rebind-prefetch.html
[52]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-172150v1/shard-bmg-5/igt@xe_exec_fault_mode@many-execqueues-multi-queue-userptr-rebind-prefetch.html
* igt@xe_exec_multi_queue@few-execs-preempt-mode-fault-priority:
- shard-bmg: [SKIP][53] ([Intel XE#8364]) -> [SKIP][54] ([Intel XE#8589]) +2 other tests skip
[53]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5589-c194081ec71ea95135c7f9ddbc7d02e9c8cad19a/shard-bmg-9/igt@xe_exec_multi_queue@few-execs-preempt-mode-fault-priority.html
[54]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-172150v1/shard-bmg-5/igt@xe_exec_multi_queue@few-execs-preempt-mode-fault-priority.html
* igt@xe_page_reclaim@boundary-split:
- shard-bmg: [SKIP][55] ([Intel XE#7793]) -> [SKIP][56] ([Intel XE#8589])
[55]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5589-c194081ec71ea95135c7f9ddbc7d02e9c8cad19a/shard-bmg-9/igt@xe_page_reclaim@boundary-split.html
[56]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-172150v1/shard-bmg-5/igt@xe_page_reclaim@boundary-split.html
* igt@xe_peer2peer@write:
- shard-bmg: [SKIP][57] ([Intel XE#2427] / [Intel XE#6953] / [Intel XE#7326] / [Intel XE#7353]) -> [SKIP][58] ([Intel XE#6953] / [Intel XE#7326] / [Intel XE#7353])
[57]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5589-c194081ec71ea95135c7f9ddbc7d02e9c8cad19a/shard-bmg-9/igt@xe_peer2peer@write.html
[58]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-172150v1/shard-bmg-5/igt@xe_peer2peer@write.html
* igt@xe_pxp@pxp-stale-queue-post-termination-irq:
- shard-bmg: [SKIP][59] ([Intel XE#4733] / [Intel XE#7417]) -> [SKIP][60] ([Intel XE#8589]) +1 other test skip
[59]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5589-c194081ec71ea95135c7f9ddbc7d02e9c8cad19a/shard-bmg-9/igt@xe_pxp@pxp-stale-queue-post-termination-irq.html
[60]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-172150v1/shard-bmg-5/igt@xe_pxp@pxp-stale-queue-post-termination-irq.html
* igt@xe_survivability@runtime-survivability:
- shard-bmg: [DMESG-WARN][61] ([Intel XE#6627] / [Intel XE#7419]) -> [SKIP][62] ([Intel XE#8589])
[61]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5589-c194081ec71ea95135c7f9ddbc7d02e9c8cad19a/shard-bmg-9/igt@xe_survivability@runtime-survivability.html
[62]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-172150v1/shard-bmg-5/igt@xe_survivability@runtime-survivability.html
[Intel XE#1124]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1124
[Intel XE#1439]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1439
[Intel XE#1499]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1499
[Intel XE#1503]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1503
[Intel XE#2234]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2234
[Intel XE#2252]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2252
[Intel XE#2311]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2311
[Intel XE#2313]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2313
[Intel XE#2320]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2320
[Intel XE#2325]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2325
[Intel XE#2375]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2375
[Intel XE#2387]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2387
[Intel XE#2427]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2427
[Intel XE#2850]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2850
[Intel XE#2887]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2887
[Intel XE#301]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/301
[Intel XE#3141]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3141
[Intel XE#3304]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3304
[Intel XE#4141]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4141
[Intel XE#4733]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4733
[Intel XE#6321]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6321
[Intel XE#6627]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6627
[Intel XE#6652]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6652
[Intel XE#6901]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6901
[Intel XE#6953]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6953
[Intel XE#7084]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7084
[Intel XE#7326]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7326
[Intel XE#7353]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7353
[Intel XE#7358]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7358
[Intel XE#7374]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7374
[Intel XE#7383]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7383
[Intel XE#7417]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7417
[Intel XE#7419]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7419
[Intel XE#7429]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7429
[Intel XE#7679]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7679
[Intel XE#7774]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7774
[Intel XE#7793]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7793
[Intel XE#8150]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/8150
[Intel XE#8355]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/8355
[Intel XE#836]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/836
[Intel XE#8364]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/8364
[Intel XE#8374]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/8374
[Intel XE#8555]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/8555
[Intel XE#8589]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/8589
Build changes
-------------
* Linux: xe-5589-c194081ec71ea95135c7f9ddbc7d02e9c8cad19a -> xe-pw-172150v1
IGT_9054: 3d819a8f511b2bcd844647bcf7e433b9407d058e @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
xe-5589-c194081ec71ea95135c7f9ddbc7d02e9c8cad19a: c194081ec71ea95135c7f9ddbc7d02e9c8cad19a
xe-pw-172150v1: 172150v1
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-172150v1/index.html
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^ permalink raw reply [flat|nested] 15+ messages in thread
end of thread, other threads:[~2026-08-13 15:58 UTC | newest]
Thread overview: 15+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2026-08-13 13:30 [PATCH 0/6] drm/xe: Capture additional HW register state in devcoredump Nareshkumar Gollakoti
2026-08-13 13:30 ` [PATCH 1/6] drm/xe/devcoredump: Capture GT fuse registers " Nareshkumar Gollakoti
2026-08-13 13:52 ` sashiko-bot
2026-08-13 13:30 ` [PATCH 2/6] drm/xe/devcoredump: Add GuC register snapshot to devcoredump Nareshkumar Gollakoti
2026-08-13 14:04 ` sashiko-bot
2026-08-13 13:30 ` [PATCH 3/6] drm/xe/guc: Print register addresses in capture snapshot output Nareshkumar Gollakoti
2026-08-13 14:11 ` sashiko-bot
2026-08-13 13:30 ` [PATCH 4/6] drm/xe: dump GAM page fault report registers in devcoredump Nareshkumar Gollakoti
2026-08-13 13:30 ` [PATCH 5/6] drm/xe/guc: add TDL gfx registers to capture list Nareshkumar Gollakoti
2026-08-13 14:25 ` sashiko-bot
2026-08-13 13:30 ` [PATCH 6/6] drm/xe: capture L3 node status registers in devcoredump Nareshkumar Gollakoti
2026-08-13 14:37 ` sashiko-bot
2026-08-13 13:39 ` ✓ CI.KUnit: success for drm/xe: Capture additional HW register state " Patchwork
2026-08-13 14:27 ` ✓ Xe.CI.BAT: " Patchwork
2026-08-13 15:58 ` ✗ Xe.CI.FULL: failure " Patchwork
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