[PATCH v2 0/7] drm/xe: Capture additional HW register state in devcoredump

[PATCH v2 0/7] drm/xe: Capture additional HW register state in devcoredump

[Nareshkumar Gollakoti]

This series extends the Xe devcoredump with additional hardware register
state to improve post-mortem debugging of GPU hangs and faults on Xe3p.

Today the devcoredump captures GuC log/CT, engine and submission state.
When triaging hangs it is often necessary to also know the static HW
configuration (fuses), GuC status/error state, GAM page-fault reporting
and L3 node status at the time of the hang. Collecting these at capture
time makes the dump self-contained and avoids relying on separate
probe-time logging.

To do this, the series adds a small generic MMIO register-dump helper
(descriptor list -> snapshot -> print/free) and uses it for several
register groups. Each group is captured for both the primary GT and,
where applicable, the media GT, and is gated to Xe3p (GRAPHICS_VER >= 35).
Registers requiring MCR steering are read through
xe_gt_mcr_unicast_read_any(); the remaining GAM registers use INSTANCE0
default steering and are read directly.

Snapshots are allocated with GFP_ATOMIC as capture runs inside the
dma_fence signalling section, matching the surrounding captures, and are
freed in the existing devcoredump teardown path.

Patches:
  1  Add the generic reg-dump helpers and capture GT/media fuse registers.
  2  Capture GT and media GuC status/error registers.
  3  Print register offsets alongside names in the GuC engine capture
     output (32- and 64-bit), easing cross-reference with the bspec.
  4  Capture the GAM page-fault report head/tail registers.
  5  Add the TDL gfx registers to the XeHPG extended GuC capture list.
  6  Capture L3 node status registers (MCR, read via unicast_read_any()).

Sample devcoredump output gains the following sections:
  **** GT Fuse Register Dump ****
  **** Media GT Fuse Register Dump ****
  **** GT GuC Register Dump ****
  **** Media GT GuC Register Dump ****
  **** GAM PF Report ****
  **** Node Status ****
  ****  Additional engine state registers ****

Nareshkumar Gollakoti (7):
  drm/xe/devcoredump: Capture GT fuse registers in devcoredump
  drm/xe/devcoredump: Add GuC register snapshot to devcoredump
  drm/xe/guc: Print register addresses in capture snapshot output
  drm/xe: dump GAM page fault report registers in devcoredump
  drm/xe/guc: add TDL,SLICE gfx registers to capture list
  drm/xe: capture L3 node status registers in devcoredump
  drm/xe/guc: capture additional engine state registers

 drivers/gpu/drm/xe/regs/xe_engine_regs.h  |  22 ++
 drivers/gpu/drm/xe/regs/xe_gt_regs.h      |  15 +
 drivers/gpu/drm/xe/regs/xe_guc_regs.h     |   5 +
 drivers/gpu/drm/xe/xe_devcoredump.c       | 391 ++++++++++++++++++++++
 drivers/gpu/drm/xe/xe_devcoredump_types.h |  49 +++
 drivers/gpu/drm/xe/xe_device.h            |   5 +
 drivers/gpu/drm/xe/xe_guc_capture.c       |  36 +-
 7 files changed, 517 insertions(+), 6 deletions(-)

-- 
2.43.0

[PATCH v2 1/7] drm/xe/devcoredump: Capture GT fuse registers in devcoredump

[Nareshkumar Gollakoti]

Capture fuse-related GT register state in the Xe devcoredump to preserve
additional hardware configuration information for postmortem debugging.

Add generic register snapshot storage and helpers for capturing,
printing, and freeing MMIO register dumps. Use them to record both
primary GT and media GT fuse register state during devcoredump snapshot
collection and print the captured values in the coredump output.

Also add the required GT register definitions for RPM and mirror
copy-enable state used by the new dump paths.

v2:(Sashiko)
- Fix GT/media fuse snapshot capture to use the correct GT context.
- Add non-fault GT force wake for cross-GT register capture.
- Skip reading registers when SR-IOV VF.
- Skip media GT capture when media GT is absent.
- Add RPM snapshot print/free handling explicitly.
- Add POWERGATE_ENABLE register to get render awake status

Signed-off-by: Nareshkumar Gollakoti <naresh.kumar.g@intel.com>
---
 drivers/gpu/drm/xe/regs/xe_gt_regs.h      |   4 +
 drivers/gpu/drm/xe/xe_devcoredump.c       | 254 ++++++++++++++++++++++
 drivers/gpu/drm/xe/xe_devcoredump_types.h |  39 ++++
 drivers/gpu/drm/xe/xe_device.h            |   5 +
 4 files changed, 302 insertions(+)

diff --git a/drivers/gpu/drm/xe/regs/xe_gt_regs.h b/drivers/gpu/drm/xe/regs/xe_gt_regs.h
index 48c515d91882..19f0a65cc3d2 100644
--- a/drivers/gpu/drm/xe/regs/xe_gt_regs.h
+++ b/drivers/gpu/drm/xe/regs/xe_gt_regs.h
@@ -22,6 +22,8 @@
 #define   MTL_CC_MASK					REG_GENMASK(12, 9)
 #define   MTL_CRST					0xf
 
+#define RPM_GCD						XE_REG(0xc98)
+
 /* RPM unit config (Gen8+) */
 #define RPM_CONFIG0					XE_REG(0xd00)
 #define   RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_MASK		REG_GENMASK(5, 3)
@@ -274,6 +276,8 @@
 #define SERVICE_COPY_ENABLE			XE_REG(0x9170)
 #define   FUSE_SERVICE_COPY_ENABLE_MASK		REG_GENMASK(7, 0)
 
+#define COPY_ENABLE_GTFS_GCD			XE_REG(0x9174)
+
 #define GDRST					XE_REG(0x941c)
 #define   GRDOM_GUC				REG_BIT(3)
 #define   GRDOM_FULL				REG_BIT(0)
diff --git a/drivers/gpu/drm/xe/xe_devcoredump.c b/drivers/gpu/drm/xe/xe_devcoredump.c
index 5f2b90b18f97..e5c33bc94103 100644
--- a/drivers/gpu/drm/xe/xe_devcoredump.c
+++ b/drivers/gpu/drm/xe/xe_devcoredump.c
@@ -25,6 +25,8 @@
 #include "xe_pm.h"
 #include "xe_sched_job.h"
 #include "xe_vm.h"
+#include "xe_mmio.h"
+#include "regs/xe_gt_regs.h"
 
 /**
  * DOC: Xe device coredump
@@ -69,6 +71,232 @@
 /* 1 hour timeout */
 #define XE_COREDUMP_TIMEOUT_JIFFIES (60 * 60 * HZ)
 
+/**
+ * struct xe_reg_desc - Register descriptor struct to make reg list
+ *
+ * This struct is used as descriptor containting reg address and name
+ * of the register to dump its value during coredump for debug purpose.
+ */
+struct xe_reg_desc {
+	/** @reg: The register */
+	struct xe_reg reg;
+	/** @name: Name of the register */
+	const char *name;
+};
+
+#define XE_REG_DESC(_reg, _name)	{ .reg = (_reg), .name = (_name) }
+
+static const struct xe_reg_desc xe3p_gt_fuse_reglist[] = {
+	XE_REG_DESC(XELP_GT_GEOMETRY_DSS_ENABLE, "GT_GEOMETRY_DSS_ENABLE"),
+	XE_REG_DESC(XEHP_GT_COMPUTE_DSS_ENABLE, "GT_COMPUTE_DSS_ENABLE"),
+	XE_REG_DESC(XELP_EU_ENABLE, "EU_ENABLE"),
+	XE_REG_DESC(MIRROR_FUSE1, "MIRROR_FUSE1"),
+	XE_REG_DESC(GT_VEBOX_VDBOX_DISABLE, "GT_VEBOX_VDBOX_DISABLE"),
+	XE_REG_DESC(SERVICE_COPY_ENABLE, "SERVICE_COPY_ENABLE"),
+	XE_REG_DESC(COPY_ENABLE_GTFS_GCD, "COPY_ENABLE_GTFS_GCD"),
+	XE_REG_DESC(XE2_GT_GEOMETRY_DSS_1, "GT_GEOMETRY_DSS_1"),
+	XE_REG_DESC(XE2_GT_GEOMETRY_DSS_2, "GT_GEOMETRY_DSS_2"),
+	XE_REG_DESC(XE2_GT_COMPUTE_DSS_2, "GT_COMPUTE_DSS_2"),
+	XE_REG_DESC(XEHPC_GT_COMPUTE_DSS_ENABLE_EXT, "GT_COMPUTE_DSS_ENABLE_EXT"),
+	XE_REG_DESC(XE3P_XPC_GT_GEOMETRY_DSS_3, "GT_GEOMETRY_DSS_3"),
+	XE_REG_DESC(XE3P_XPC_GT_COMPUTE_DSS_3, "GT_COMPUTE_DSS_3"),
+};
+
+static const struct xe_reg_desc xe3p_media_gt_fuse_reglist[] = {
+	XE_REG_DESC(SERVICE_COPY_ENABLE, "SERVICE_COPY_ENABLE"),
+	XE_REG_DESC(COPY_ENABLE_GTFS_GCD, "COPY_ENABLE_GTFS_GCD"),
+};
+
+static const struct xe_reg_desc xe3p_gt_rpm_reglist[] = {
+	XE_REG_DESC(RPM_GCD, "RPM_GCD"),
+	XE_REG_DESC(POWERGATE_ENABLE, "POWERGATE_ENABLE"),
+};
+
+static const struct xe_reg_desc xe3p_media_gt_rpm_reglist[] = {
+	XE_REG_DESC(RPM_GCD, "RPM_GCD"),
+};
+
+/**
+ * struct xe_reg_desc_list - Struct for register descriptor list
+ *
+ * This struct is used to reference the corresponding reglist of
+ * various component
+ */
+struct xe_reg_desc_list {
+	/** @regs: Pointer to an array of register descriptors. */
+	const struct xe_reg_desc *regs;
+	/** @num_regs: refernce for num regs in reg descriptor*/
+	u32 num_regs;
+};
+
+/**
+ * struct xe_gt_regset - Struct for register descriptor list for GT
+ *
+ * This struct is used to reference the corresponding reglist of
+ * GT and media GT
+ */
+struct xe_gt_regset {
+	struct xe_reg_desc_list gt[XE_MAX_GT_PER_TILE + 1];
+};
+
+static const struct xe_gt_regset xe_fuse_regset = {
+	.gt[XE_GT_TYPE_MAIN] = {
+		.regs = xe3p_gt_fuse_reglist,
+		.num_regs = ARRAY_SIZE(xe3p_gt_fuse_reglist),
+	},
+	.gt[XE_GT_TYPE_MEDIA] = {
+		.regs = xe3p_media_gt_fuse_reglist,
+		.num_regs = ARRAY_SIZE(xe3p_media_gt_fuse_reglist),
+	},
+};
+
+static const struct xe_gt_regset xe_rpm_regset = {
+	.gt[XE_GT_TYPE_MAIN] = {
+		.regs = xe3p_gt_rpm_reglist,
+		.num_regs = ARRAY_SIZE(xe3p_gt_rpm_reglist),
+	},
+	.gt[XE_GT_TYPE_MEDIA] = {
+		.regs = xe3p_media_gt_rpm_reglist,
+		.num_regs = ARRAY_SIZE(xe3p_media_gt_rpm_reglist),
+	},
+};
+
+#define XE_GT_REG_LIST(_type, _gt_type) \
+	(&xe_##_type##_regset.gt[XE_GT_TYPE_##_gt_type])
+
+static void
+xe_capture_reg_desc_list(struct xe_gt *gt,
+			 struct xe_reg_dump_snapshot *dst,
+			 const struct xe_reg_desc *src,
+			 u32 count)
+{
+	u32 i;
+
+	for (i = 0; i < count; i++) {
+		dst[i].reg = src[i].reg;
+		dst[i].value = xe_mmio_read32(&gt->mmio, src[i].reg);
+		dst[i].name = src[i].name;
+	}
+}
+
+static struct xe_dbg_reg_snapshot *
+xe_dbg_reg_snapshot_capture(struct xe_gt *gt,
+			    const struct xe_reg_desc_list *reglist)
+{
+	struct xe_dbg_reg_snapshot *snap;
+
+	if (!gt || !xe_dbg_reg_snapshot_is_supported(gt_to_xe(gt)))
+		return NULL;
+
+	if (IS_SRIOV_VF(gt_to_xe(gt)))
+		return NULL;
+
+	if (!reglist->regs || !reglist->num_regs)
+		return NULL;
+
+	snap = kzalloc(struct_size(snap, regs, reglist->num_regs), GFP_ATOMIC);
+	if (!snap)
+		return NULL;
+
+	snap->num_regs = reglist->num_regs;
+
+	xe_capture_reg_desc_list(gt, snap->regs, reglist->regs, reglist->num_regs);
+
+	return snap;
+}
+
+static void xe_dbg_reg_snapshot_print(struct drm_printer *p,
+				      const struct xe_dbg_reg_snapshot *snap)
+{
+	u32 i;
+
+	if (!snap)
+		return;
+
+	for (i = 0; i < snap->num_regs; i++)
+		drm_printf(p, " %s [0x%x] = 0x%08x\n",
+			   snap->regs[i].name,
+			   snap->regs[i].reg.addr,
+			   snap->regs[i].value);
+}
+
+static void xe_dbg_reg_snapshot_free(struct xe_dbg_reg_snapshot *snap)
+{
+	kfree(snap);
+}
+
+static void xe_gt_rpm_snapshot_print(struct drm_printer *p,
+				     const struct xe_dbg_reg_snapshot *snap)
+{
+	xe_dbg_reg_snapshot_print(p, snap);
+
+	if (snap && snap->num_regs >= 2 && !(snap->regs[1].value & 0x2))
+		drm_puts(p, "render is not awake\n");
+}
+
+static struct xe_dbg_reg_snapshot *
+xe_dbg_reg_snapshot_capture_target(struct xe_gt *fault_gt,
+				   struct xe_gt *target_gt,
+				   const struct xe_reg_desc_list *reglist)
+{
+	if (!fault_gt || !target_gt)
+		return NULL;
+
+	if (target_gt != fault_gt) {
+		CLASS(xe_force_wake, fw_ref)(gt_to_fw(target_gt),
+					     XE_FORCEWAKE_ALL);
+		if (!xe_force_wake_ref_has_domain(fw_ref.domains, XE_FORCEWAKE_ALL))
+			return NULL;
+
+		return xe_dbg_reg_snapshot_capture(target_gt, reglist);
+	}
+
+	return xe_dbg_reg_snapshot_capture(target_gt, reglist);
+}
+
+static struct xe_dbg_reg_snapshot *
+xe_gt_fuse_snapshot_capture(struct xe_gt *gt)
+{
+	if (!gt || !gt->tile || !gt->tile->primary_gt)
+		return NULL;
+
+	return xe_dbg_reg_snapshot_capture_target(gt,
+						  gt->tile->primary_gt,
+						  XE_GT_REG_LIST(fuse, MAIN));
+}
+
+static struct xe_dbg_reg_snapshot *
+xe_media_gt_fuse_snapshot_capture(struct xe_gt *gt)
+{
+	if (!gt || !gt->tile || !gt->tile->media_gt)
+		return NULL;
+
+	return xe_dbg_reg_snapshot_capture_target(gt,
+						  gt->tile->media_gt,
+						  XE_GT_REG_LIST(fuse, MEDIA));
+}
+
+static struct xe_dbg_reg_snapshot *xe_gt_rpm_snapshot_capture(struct xe_gt *gt)
+{
+	if (!gt || !gt->tile || !gt->tile->primary_gt)
+		return NULL;
+
+	return xe_dbg_reg_snapshot_capture_target(gt,
+						  gt->tile->primary_gt,
+						  XE_GT_REG_LIST(rpm, MAIN));
+}
+
+static struct xe_dbg_reg_snapshot *
+xe_media_gt_rpm_snapshot_capture(struct xe_gt *gt)
+{
+	if (!gt || !gt->tile || !gt->tile->media_gt)
+		return NULL;
+
+	return xe_dbg_reg_snapshot_capture_target(gt,
+						  gt->tile->media_gt,
+						  XE_GT_REG_LIST(rpm, MEDIA));
+}
+
 static struct xe_device *coredump_to_xe(const struct xe_devcoredump *coredump)
 {
 	return container_of(coredump, struct xe_device, devcoredump);
@@ -114,6 +342,15 @@ static ssize_t __xe_devcoredump_read(char *buffer, ssize_t count,
 	drm_printf(&p, "\n**** GT #%d ****\n", ss->gt->info.id);
 	drm_printf(&p, "\tTile: %d\n", ss->gt->tile->id);
 
+	drm_printf(&p, "\n**** GT Fuse Register Dump ****\n");
+	xe_dbg_reg_snapshot_print(&p, ss->gt_fuse);
+	drm_printf(&p, "\n**** Media GT Fuse Register Dump ****\n");
+	xe_dbg_reg_snapshot_print(&p, ss->media_fuse);
+	drm_printf(&p, "\n**** GT RPM Register Dump ****\n");
+	xe_gt_rpm_snapshot_print(&p, ss->gt_rpm);
+	drm_printf(&p, "\n**** Media GT RPM Register Dump ****\n");
+	xe_dbg_reg_snapshot_print(&p, ss->media_gt_rpm);
+
 	drm_puts(&p, "\n**** GuC Log ****\n");
 	xe_guc_log_snapshot_print(ss->guc.log, &p);
 	drm_puts(&p, "\n**** GuC CT ****\n");
@@ -149,6 +386,18 @@ static void xe_devcoredump_snapshot_free(struct xe_devcoredump_snapshot *ss)
 	xe_guc_ct_snapshot_free(ss->guc.ct);
 	ss->guc.ct = NULL;
 
+	xe_dbg_reg_snapshot_free(ss->gt_fuse);
+	ss->gt_fuse = NULL;
+
+	xe_dbg_reg_snapshot_free(ss->media_fuse);
+	ss->media_fuse = NULL;
+
+	xe_dbg_reg_snapshot_free(ss->gt_rpm);
+	ss->gt_rpm = NULL;
+
+	xe_dbg_reg_snapshot_free(ss->media_gt_rpm);
+	ss->media_gt_rpm = NULL;
+
 	if (!IS_ERR_OR_NULL(ss->gt))
 		xe_guc_capture_put_matched_nodes(&ss->gt->uc.guc);
 	ss->matched_node = NULL;
@@ -349,6 +598,11 @@ static void devcoredump_snapshot(struct xe_devcoredump *coredump,
 
 	cookie = dma_fence_begin_signalling();
 
+	ss->gt_fuse = xe_gt_fuse_snapshot_capture(q->gt);
+	ss->media_fuse = xe_media_gt_fuse_snapshot_capture(q->gt);
+	ss->gt_rpm = xe_gt_rpm_snapshot_capture(q->gt);
+	ss->media_gt_rpm = xe_media_gt_rpm_snapshot_capture(q->gt);
+
 	ss->guc.log = xe_guc_log_snapshot_capture(&guc->log, true);
 	ss->guc.ct = xe_guc_ct_snapshot_capture(&guc->ct);
 	ss->ge = xe_guc_exec_queue_snapshot_capture(q);
diff --git a/drivers/gpu/drm/xe/xe_devcoredump_types.h b/drivers/gpu/drm/xe/xe_devcoredump_types.h
index a174385a6d83..75f317a5fe36 100644
--- a/drivers/gpu/drm/xe/xe_devcoredump_types.h
+++ b/drivers/gpu/drm/xe/xe_devcoredump_types.h
@@ -14,6 +14,35 @@
 struct xe_device;
 struct xe_gt;
 
+/**
+ * struct xe_reg_dump_snapshot - dump register snapshot
+ *
+ * This struct is used as generic reg dump snapshot in the format of
+ * register, its value and its name for human readable format.
+ */
+struct xe_reg_dump_snapshot {
+	/** @reg: xe register structure*/
+	struct xe_reg reg;
+	/** @value: Value of the register*/
+	u32 value;
+	/** @name: Name of the register */
+	const char *name;
+};
+
+/**
+ * struct xe_dbg_reg_snapshot - Register snapshot
+ *
+ * This struct contains the register values captured at the time of the crash.
+ * It is used to store the register values in a human-readable format for
+ * debugging purposes.
+ */
+struct xe_dbg_reg_snapshot {
+	/** @num_regs: Number of registers needed for capture. */
+	u32 num_regs;
+	/** @regs: Pointer to an array of register dump snapshot. */
+	struct xe_reg_dump_snapshot regs[];
+};
+
 /**
  * struct xe_devcoredump_snapshot - Crash snapshot
  *
@@ -35,6 +64,16 @@ struct xe_devcoredump_snapshot {
 
 	/** @gt: Affected GT, used by forcewake for delayed capture */
 	struct xe_gt *gt;
+
+	/** @gt_fuse: Fuse snapshot */
+	struct xe_dbg_reg_snapshot *gt_fuse;
+	/** @media_fuse: Media Fuse snapshot */
+	struct xe_dbg_reg_snapshot *media_fuse;
+	/** @gt_rpm: GT RPM snapshot */
+	struct xe_dbg_reg_snapshot *gt_rpm;
+	/** @media_gt_rpm: Media GT RPM snapshot */
+	struct xe_dbg_reg_snapshot *media_gt_rpm;
+
 	/** @work: Workqueue for deferred capture outside of signaling context */
 	struct work_struct work;
 
diff --git a/drivers/gpu/drm/xe/xe_device.h b/drivers/gpu/drm/xe/xe_device.h
index 6c4cfaebc44a..e05951b6988b 100644
--- a/drivers/gpu/drm/xe/xe_device.h
+++ b/drivers/gpu/drm/xe/xe_device.h
@@ -260,6 +260,11 @@ static inline bool xe_debug_page_size_mode_is_mixed(struct xe_device *xe)
 }
 #endif
 
+static inline bool xe_dbg_reg_snapshot_is_supported(struct xe_device *xe)
+{
+	return (GRAPHICS_VER(xe) >= 35);
+}
+
 void xe_device_set_wedged_method(struct xe_device *xe, unsigned long method);
 void xe_device_declare_wedged(struct xe_device *xe);
 int xe_device_validate_wedged_mode(struct xe_device *xe, unsigned int mode);
-- 
2.43.0

[PATCH v2 2/7] drm/xe/devcoredump: Add GuC register snapshot to devcoredump

[Nareshkumar Gollakoti]

Add support for capturing GuC register state as part of the xe
devcoredump snapshot.

Define a dedicated GuC register snapshot structure, record selected
GT and media GuC status/error registers during devcoredump capture,
and free the snapshot during teardown.

Keeping these register values in the devcoredump helps with
post-mortem analysis of GuC-related failures.

v2:(Sashiko)
- Reuse the generic target GT snapshot helper for GuC register capture
- Capture primary and media GuC registers using correct GT MMIO context
- Avoid reading the same on SR-IOV VF
- skip reading media GT GuC registers when media is not present
- drop hardcoded media register address macros

Signed-off-by: Nareshkumar Gollakoti <naresh.kumar.g@intel.com>
---
 drivers/gpu/drm/xe/regs/xe_guc_regs.h     |  5 ++
 drivers/gpu/drm/xe/xe_devcoredump.c       | 58 +++++++++++++++++++++++
 drivers/gpu/drm/xe/xe_devcoredump_types.h |  5 ++
 3 files changed, 68 insertions(+)

diff --git a/drivers/gpu/drm/xe/regs/xe_guc_regs.h b/drivers/gpu/drm/xe/regs/xe_guc_regs.h
index 5faac8316b66..c13ee6e21e37 100644
--- a/drivers/gpu/drm/xe/regs/xe_guc_regs.h
+++ b/drivers/gpu/drm/xe/regs/xe_guc_regs.h
@@ -150,6 +150,11 @@
 #define GUC_INTR_SW_INT_1			REG_BIT(1)
 #define GUC_INTR_SW_INT_0			REG_BIT(0)
 
+#define GUC_DEVICEID				XE_REG(0xc008)
+#define GUC_SHIM_ERR_TRAP			XE_REG(0xc070)
+#define GUC_HW_FATL_ERR				XE_REG(0xc598)
+#define GUC_HW_NOTIFY_ERR			XE_REG(0xc59c)
+
 #define GUC_NUM_DOORBELLS			256
 
 /* format of the HW-monitored doorbell cacheline */
diff --git a/drivers/gpu/drm/xe/xe_devcoredump.c b/drivers/gpu/drm/xe/xe_devcoredump.c
index e5c33bc94103..62b1158b89a5 100644
--- a/drivers/gpu/drm/xe/xe_devcoredump.c
+++ b/drivers/gpu/drm/xe/xe_devcoredump.c
@@ -27,6 +27,7 @@
 #include "xe_vm.h"
 #include "xe_mmio.h"
 #include "regs/xe_gt_regs.h"
+#include "regs/xe_guc_regs.h"
 
 /**
  * DOC: Xe device coredump
@@ -86,6 +87,16 @@ struct xe_reg_desc {
 
 #define XE_REG_DESC(_reg, _name)	{ .reg = (_reg), .name = (_name) }
 
+static const struct xe_reg_desc xe3p_gt_guc_reglist[] = {
+	XE_REG_DESC(GUC_STATUS,	"GUC_STATUS"),
+	XE_REG_DESC(GUC_WOPCM_SIZE,	"GUC_WOPCM_SIZE"),
+	XE_REG_DESC(GUC_DEVICEID,	"GUC_DEVICEID"),
+	XE_REG_DESC(DMA_CTRL,	"DMA_CTRL"),
+	XE_REG_DESC(GUC_HW_FATL_ERR,	"GUC_HW_FATL_ERR"),
+	XE_REG_DESC(GUC_HW_NOTIFY_ERR,	"GUC_HW_NOTIFY_ERR"),
+	XE_REG_DESC(GUC_SHIM_ERR_TRAP,	"GUC_SHIM_ERR_TRAP"),
+};
+
 static const struct xe_reg_desc xe3p_gt_fuse_reglist[] = {
 	XE_REG_DESC(XELP_GT_GEOMETRY_DSS_ENABLE, "GT_GEOMETRY_DSS_ENABLE"),
 	XE_REG_DESC(XEHP_GT_COMPUTE_DSS_ENABLE, "GT_COMPUTE_DSS_ENABLE"),
@@ -161,6 +172,17 @@ static const struct xe_gt_regset xe_rpm_regset = {
 	},
 };
 
+static const struct xe_gt_regset xe_guc_regset = {
+	.gt[XE_GT_TYPE_MAIN] = {
+		.regs = xe3p_gt_guc_reglist,
+		.num_regs = ARRAY_SIZE(xe3p_gt_guc_reglist),
+	},
+	.gt[XE_GT_TYPE_MEDIA] = {
+		.regs = xe3p_gt_guc_reglist,
+		.num_regs = ARRAY_SIZE(xe3p_gt_guc_reglist),
+	},
+};
+
 #define XE_GT_REG_LIST(_type, _gt_type) \
 	(&xe_##_type##_regset.gt[XE_GT_TYPE_##_gt_type])
 
@@ -297,6 +319,28 @@ xe_media_gt_rpm_snapshot_capture(struct xe_gt *gt)
 						  XE_GT_REG_LIST(rpm, MEDIA));
 }
 
+static struct xe_dbg_reg_snapshot *
+xe_gt_guc_reg_snapshot_capture(struct xe_gt *gt)
+{
+	if (!gt || !gt->tile || !gt->tile->primary_gt)
+		return NULL;
+
+	return xe_dbg_reg_snapshot_capture_target(gt,
+						  gt->tile->primary_gt,
+						  XE_GT_REG_LIST(guc, MAIN));
+}
+
+static struct xe_dbg_reg_snapshot *
+xe_media_gt_guc_reg_snapshot_capture(struct xe_gt *gt)
+{
+	if (!gt || !gt->tile || !gt->tile->media_gt)
+		return NULL;
+
+	return xe_dbg_reg_snapshot_capture_target(gt,
+						  gt->tile->media_gt,
+						  XE_GT_REG_LIST(guc, MEDIA));
+}
+
 static struct xe_device *coredump_to_xe(const struct xe_devcoredump *coredump)
 {
 	return container_of(coredump, struct xe_device, devcoredump);
@@ -351,6 +395,11 @@ static ssize_t __xe_devcoredump_read(char *buffer, ssize_t count,
 	drm_printf(&p, "\n**** Media GT RPM Register Dump ****\n");
 	xe_dbg_reg_snapshot_print(&p, ss->media_gt_rpm);
 
+	drm_printf(&p, "\n**** GT GuC Register Dump ****\n");
+	xe_dbg_reg_snapshot_print(&p, ss->gt_guc_reg);
+	drm_printf(&p, "\n**** Media GT GuC Register Dump ****\n");
+	xe_dbg_reg_snapshot_print(&p, ss->media_gt_guc_reg);
+
 	drm_puts(&p, "\n**** GuC Log ****\n");
 	xe_guc_log_snapshot_print(ss->guc.log, &p);
 	drm_puts(&p, "\n**** GuC CT ****\n");
@@ -398,6 +447,12 @@ static void xe_devcoredump_snapshot_free(struct xe_devcoredump_snapshot *ss)
 	xe_dbg_reg_snapshot_free(ss->media_gt_rpm);
 	ss->media_gt_rpm = NULL;
 
+	xe_dbg_reg_snapshot_free(ss->gt_guc_reg);
+	ss->gt_guc_reg = NULL;
+
+	xe_dbg_reg_snapshot_free(ss->media_gt_guc_reg);
+	ss->media_gt_guc_reg = NULL;
+
 	if (!IS_ERR_OR_NULL(ss->gt))
 		xe_guc_capture_put_matched_nodes(&ss->gt->uc.guc);
 	ss->matched_node = NULL;
@@ -603,6 +658,9 @@ static void devcoredump_snapshot(struct xe_devcoredump *coredump,
 	ss->gt_rpm = xe_gt_rpm_snapshot_capture(q->gt);
 	ss->media_gt_rpm = xe_media_gt_rpm_snapshot_capture(q->gt);
 
+	ss->gt_guc_reg = xe_gt_guc_reg_snapshot_capture(q->gt);
+	ss->media_gt_guc_reg = xe_media_gt_guc_reg_snapshot_capture(q->gt);
+
 	ss->guc.log = xe_guc_log_snapshot_capture(&guc->log, true);
 	ss->guc.ct = xe_guc_ct_snapshot_capture(&guc->ct);
 	ss->ge = xe_guc_exec_queue_snapshot_capture(q);
diff --git a/drivers/gpu/drm/xe/xe_devcoredump_types.h b/drivers/gpu/drm/xe/xe_devcoredump_types.h
index 75f317a5fe36..4671e00558db 100644
--- a/drivers/gpu/drm/xe/xe_devcoredump_types.h
+++ b/drivers/gpu/drm/xe/xe_devcoredump_types.h
@@ -74,6 +74,11 @@ struct xe_devcoredump_snapshot {
 	/** @media_gt_rpm: Media GT RPM snapshot */
 	struct xe_dbg_reg_snapshot *media_gt_rpm;
 
+	/** @gt_guc_reg: gt guc reg snapshot */
+	struct xe_dbg_reg_snapshot *gt_guc_reg;
+	/** @media_gt_guc_reg: media gt guc reg snapshot */
+	struct xe_dbg_reg_snapshot *media_gt_guc_reg;
+
 	/** @work: Workqueue for deferred capture outside of signaling context */
 	struct work_struct work;
 
-- 
2.43.0

[PATCH v2 3/7] drm/xe/guc: Print register addresses in capture snapshot output

[Nareshkumar Gollakoti]

Include register offsets in GuC capture snapshot print output for both
32-bit and 64-bit registers.

When dumping captured engine register state, print each register name
alongside its MMIO offset to make the snapshot output easier to
cross-reference with register definitions and hardware debug
documentation.

This improves postmortem analysis without changing capture contents.

v2:(Sashiko)
- Ensure lower DWORD prints

Signed-off-by: Nareshkumar Gollakoti <naresh.kumar.g@intel.com>
---
 drivers/gpu/drm/xe/xe_guc_capture.c | 11 +++++++----
 1 file changed, 7 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/xe/xe_guc_capture.c b/drivers/gpu/drm/xe/xe_guc_capture.c
index 82df19b304e1..324f25af3b0d 100644
--- a/drivers/gpu/drm/xe/xe_guc_capture.c
+++ b/drivers/gpu/drm/xe/xe_guc_capture.c
@@ -1774,7 +1774,9 @@ snapshot_print_by_list_order(struct xe_hw_engine_snapshot *snapshot, struct drm_
 			XE_WARN_ON(!low32_ready);
 			low32_ready = false;
 
-			drm_printf(p, "\t%s: 0x%016llx\n", reg_desc->regname, value_qw);
+			drm_printf(p, "\t%s (0x%lx): 0x%016llx\n", reg_desc->regname,
+				   reg_desc->reg.addr - sizeof(u32),
+				   value_qw);
 			break;
 		}
 
@@ -1788,10 +1790,11 @@ snapshot_print_by_list_order(struct xe_hw_engine_snapshot *snapshot, struct drm_
 			XE_WARN_ON(low32_ready);
 
 			if (FIELD_GET(GUC_REGSET_STEERING_NEEDED, reg_desc->flags))
-				drm_printf(p, "\t%s[%u]: 0x%08x\n", reg_desc->regname,
-					   reg_desc->dss_id, value);
+				drm_printf(p, "\t%s[%u] (0x%x): 0x%08x\n", reg_desc->regname,
+					   reg_desc->dss_id, reg_desc->reg.addr, value);
 			else
-				drm_printf(p, "\t%s: 0x%08x\n", reg_desc->regname, value);
+				drm_printf(p, "\t%s (0x%x): 0x%08x\n", reg_desc->regname,
+					   reg_desc->reg.addr, value);
 
 			break;
 		}
-- 
2.43.0

[PATCH v2 4/7] drm/xe: dump GAM page fault report registers in devcoredump

[Nareshkumar Gollakoti]

Add PAGE_FLTRPTQ_HEAD_GAMCTRL and PAGE_FLTRPTQ_TAIL_GAMCTRL to the Xe
register definitions and capture them as part of the devcoredump
snapshot.

Include the register dump in the devcoredump output and release the
snapshot during cleanup so page fault report state is available for
post-mortem debugging.

v2:
- As design change made for previous patches. refactored this patch
  as well to accommodate those changes.
- Add PF occurred print when the two register values are not equal

Signed-off-by: Nareshkumar Gollakoti <naresh.kumar.g@intel.com>
---
 drivers/gpu/drm/xe/regs/xe_gt_regs.h      |  3 ++
 drivers/gpu/drm/xe/xe_devcoredump.c       | 39 +++++++++++++++++++++++
 drivers/gpu/drm/xe/xe_devcoredump_types.h |  3 ++
 3 files changed, 45 insertions(+)

diff --git a/drivers/gpu/drm/xe/regs/xe_gt_regs.h b/drivers/gpu/drm/xe/regs/xe_gt_regs.h
index 19f0a65cc3d2..05542f20c7b5 100644
--- a/drivers/gpu/drm/xe/regs/xe_gt_regs.h
+++ b/drivers/gpu/drm/xe/regs/xe_gt_regs.h
@@ -501,6 +501,9 @@
 #define   LMEM_EN				REG_BIT(31)
 #define   LMTT_DIR_PTR				REG_GENMASK(30, 0) /* in multiples of 64KB */
 
+#define PAGE_FLTRPTQ_HEAD_GAMCTRL		XE_REG(0xcf90)
+#define PAGE_FLTRPTQ_TAIL_GAMCTRL		XE_REG(0xcf94)
+
 #define HALF_SLICE_CHICKEN5			XE_REG_MCR(0xe188, XE_REG_OPTION_MASKED)
 #define   DISABLE_SAMPLE_G_PERFORMANCE		REG_BIT(0)
 
diff --git a/drivers/gpu/drm/xe/xe_devcoredump.c b/drivers/gpu/drm/xe/xe_devcoredump.c
index 62b1158b89a5..37893d09d05e 100644
--- a/drivers/gpu/drm/xe/xe_devcoredump.c
+++ b/drivers/gpu/drm/xe/xe_devcoredump.c
@@ -127,6 +127,11 @@ static const struct xe_reg_desc xe3p_media_gt_rpm_reglist[] = {
 	XE_REG_DESC(RPM_GCD, "RPM_GCD"),
 };
 
+static const struct xe_reg_desc xe3p_gam_pf_reglist[] = {
+	XE_REG_DESC(PAGE_FLTRPTQ_HEAD_GAMCTRL, "PAGE_FLTRPTQ_HEAD_GAMCTRL"),
+	XE_REG_DESC(PAGE_FLTRPTQ_TAIL_GAMCTRL, "PAGE_FLTRPTQ_TAIL_GAMCTRL"),
+};
+
 /**
  * struct xe_reg_desc_list - Struct for register descriptor list
  *
@@ -183,6 +188,13 @@ static const struct xe_gt_regset xe_guc_regset = {
 	},
 };
 
+static const struct xe_gt_regset xe_gam_pf_regset = {
+	.gt[XE_GT_TYPE_MAIN] = {
+		.regs = xe3p_gam_pf_reglist,
+		.num_regs = ARRAY_SIZE(xe3p_gam_pf_reglist),
+	},
+};
+
 #define XE_GT_REG_LIST(_type, _gt_type) \
 	(&xe_##_type##_regset.gt[XE_GT_TYPE_##_gt_type])
 
@@ -256,6 +268,16 @@ static void xe_gt_rpm_snapshot_print(struct drm_printer *p,
 		drm_puts(p, "render is not awake\n");
 }
 
+static void xe_gam_pf_snapshot_print(struct drm_printer *p,
+				     const struct xe_dbg_reg_snapshot *snap)
+{
+	xe_dbg_reg_snapshot_print(p, snap);
+
+	if (snap && snap->num_regs >= 2 &&
+	    snap->regs[0].value != snap->regs[1].value)
+		drm_printf(p, "PF occurred, refer to dmesg log for PF info\n");
+}
+
 static struct xe_dbg_reg_snapshot *
 xe_dbg_reg_snapshot_capture_target(struct xe_gt *fault_gt,
 				   struct xe_gt *target_gt,
@@ -341,6 +363,16 @@ xe_media_gt_guc_reg_snapshot_capture(struct xe_gt *gt)
 						  XE_GT_REG_LIST(guc, MEDIA));
 }
 
+static struct xe_dbg_reg_snapshot *xe_gam_pf_report_capture(struct xe_gt *gt)
+{
+	if (!gt || !gt->tile || !gt->tile->primary_gt)
+		return NULL;
+
+	return xe_dbg_reg_snapshot_capture_target(gt,
+						  gt->tile->primary_gt,
+						  XE_GT_REG_LIST(gam_pf, MAIN));
+}
+
 static struct xe_device *coredump_to_xe(const struct xe_devcoredump *coredump)
 {
 	return container_of(coredump, struct xe_device, devcoredump);
@@ -405,6 +437,9 @@ static ssize_t __xe_devcoredump_read(char *buffer, ssize_t count,
 	drm_puts(&p, "\n**** GuC CT ****\n");
 	xe_guc_ct_snapshot_print(ss->guc.ct, &p);
 
+	drm_printf(&p, "\n**** GAM PF Report ****\n");
+	xe_gam_pf_snapshot_print(&p, ss->gam_pf_report);
+
 	drm_puts(&p, "\n**** Contexts ****\n");
 	xe_guc_exec_queue_snapshot_print(ss->ge, &p);
 
@@ -457,6 +492,9 @@ static void xe_devcoredump_snapshot_free(struct xe_devcoredump_snapshot *ss)
 		xe_guc_capture_put_matched_nodes(&ss->gt->uc.guc);
 	ss->matched_node = NULL;
 
+	xe_dbg_reg_snapshot_free(ss->gam_pf_report);
+	ss->gam_pf_report = NULL;
+
 	xe_guc_exec_queue_snapshot_free(ss->ge);
 	ss->ge = NULL;
 
@@ -663,6 +701,7 @@ static void devcoredump_snapshot(struct xe_devcoredump *coredump,
 
 	ss->guc.log = xe_guc_log_snapshot_capture(&guc->log, true);
 	ss->guc.ct = xe_guc_ct_snapshot_capture(&guc->ct);
+	ss->gam_pf_report = xe_gam_pf_report_capture(q->gt);
 	ss->ge = xe_guc_exec_queue_snapshot_capture(q);
 	if (job)
 		ss->job = xe_sched_job_snapshot_capture(job);
diff --git a/drivers/gpu/drm/xe/xe_devcoredump_types.h b/drivers/gpu/drm/xe/xe_devcoredump_types.h
index 4671e00558db..ea7638d0a7a2 100644
--- a/drivers/gpu/drm/xe/xe_devcoredump_types.h
+++ b/drivers/gpu/drm/xe/xe_devcoredump_types.h
@@ -90,6 +90,9 @@ struct xe_devcoredump_snapshot {
 		struct xe_guc_log_snapshot *log;
 	} guc;
 
+	/** @gam_pf_report: GAM PF report snapshot */
+	struct xe_dbg_reg_snapshot *gam_pf_report;
+
 	/** @ge: GuC Submission Engine snapshot */
 	struct xe_guc_submit_exec_queue_snapshot *ge;
 
-- 
2.43.0

[PATCH v2 5/7] drm/xe/guc: add TDL, SLICE gfx registers to capture list

[Nareshkumar Gollakoti]

Add ROW_INSTDONE_TDL_GFX, SS_LSC_HDC_IDLE_TDL_GFX and SLICE_ARB_STATUS
register definitions and include them in the XeHPG extended GuC capture
register list.

v2:(Sashiko)
- Refactored ROW_INSTDONE_TDL_GFX to ROW_INSTDONE_TDL_GFX
- Add SLICE_ARB_STATUS register to xeHP register list
- Refactor commit message

Signed-off-by: Nareshkumar Gollakoti <naresh.kumar.g@intel.com>
---
 drivers/gpu/drm/xe/regs/xe_gt_regs.h | 5 +++++
 drivers/gpu/drm/xe/xe_guc_capture.c  | 5 ++++-
 2 files changed, 9 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/xe/regs/xe_gt_regs.h b/drivers/gpu/drm/xe/regs/xe_gt_regs.h
index 05542f20c7b5..b3ce7074f7d7 100644
--- a/drivers/gpu/drm/xe/regs/xe_gt_regs.h
+++ b/drivers/gpu/drm/xe/regs/xe_gt_regs.h
@@ -504,6 +504,8 @@
 #define PAGE_FLTRPTQ_HEAD_GAMCTRL		XE_REG(0xcf90)
 #define PAGE_FLTRPTQ_TAIL_GAMCTRL		XE_REG(0xcf94)
 
+#define SLICE_ARB_STATUS			XE_REG_MCR(0xd814)
+
 #define HALF_SLICE_CHICKEN5			XE_REG_MCR(0xe188, XE_REG_OPTION_MASKED)
 #define   DISABLE_SAMPLE_G_PERFORMANCE		REG_BIT(0)
 
@@ -568,6 +570,9 @@
 #define EU_SYSTOLIC_LIC_THROTTLE_CTL_WITH_LOCK	XE_REG_MCR(0xe534)
 #define   EU_SYSTOLIC_LIC_THROTTLE_CTL_LOCK_BIT	REG_BIT(31)
 
+#define ROW_INSTDONE_TDL_GFX			XE_REG_MCR(0xe580)
+#define SS_LSC_HDC_IDLE_TDL_GFX			XE_REG_MCR(0xe584)
+
 #define XEHP_HDC_CHICKEN0					XE_REG_MCR(0xe5f0, XE_REG_OPTION_MASKED)
 #define   LSC_L1_FLUSH_CTL_3D_DATAPORT_FLUSH_EVENTS_MASK	REG_GENMASK(13, 11)
 #define   DIS_ATOMIC_CHAINING_TYPED_WRITES	REG_BIT(3)
diff --git a/drivers/gpu/drm/xe/xe_guc_capture.c b/drivers/gpu/drm/xe/xe_guc_capture.c
index 324f25af3b0d..62832bd4af78 100644
--- a/drivers/gpu/drm/xe/xe_guc_capture.c
+++ b/drivers/gpu/drm/xe/xe_guc_capture.c
@@ -376,7 +376,10 @@ static const struct __ext_steer_reg xehpg_extregs[] = {
 	{"SC_INSTDONE",			XEHPG_SC_INSTDONE},
 	{"SC_INSTDONE_EXTRA",		XEHPG_SC_INSTDONE_EXTRA},
 	{"SC_INSTDONE_EXTRA2",		XEHPG_SC_INSTDONE_EXTRA2},
-	{"INSTDONE_GEOM_SVGUNIT",	XEHPG_INSTDONE_GEOM_SVGUNIT}
+	{"INSTDONE_GEOM_SVGUNIT",	XEHPG_INSTDONE_GEOM_SVGUNIT},
+	{"ROW_INSTDONE_TDL_GFX",	ROW_INSTDONE_TDL_GFX},
+	{"SS_LSC_HDC_IDLE_TDL_GFX",	SS_LSC_HDC_IDLE_TDL_GFX},
+	{"SLICE_ARB_STATUS",		SLICE_ARB_STATUS}
 };
 
 static void __fill_ext_reg(struct __guc_mmio_reg_descr *ext,
-- 
2.43.0

[PATCH v2 6/7] drm/xe: capture L3 node status registers in devcoredump

[Nareshkumar Gollakoti]

Add L3_NODE_IDLE and L3STAT_LBCF_GFX register definitions and include
them in the devcoredump snapshot as a node status section.

Extend the register descriptor to mark MCR registers so the snapshot
code can read them through xe_gt_mcr_unicast_read_any(), then print and
free the captured node status registers alongside the existing dump
sections.

v2:(Sashiko)
- change L3 node registers as XE_REG_MCR type
- identify mcr register type from reg.mcr
- As generic capture function ensure VF check this will not execute
  on VF Mode.

Signed-off-by: Nareshkumar Gollakoti <naresh.kumar.g@intel.com>
---
 drivers/gpu/drm/xe/regs/xe_gt_regs.h      |  3 ++
 drivers/gpu/drm/xe/xe_devcoredump.c       | 46 +++++++++++++++++++++--
 drivers/gpu/drm/xe/xe_devcoredump_types.h |  2 +
 3 files changed, 48 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/xe/regs/xe_gt_regs.h b/drivers/gpu/drm/xe/regs/xe_gt_regs.h
index b3ce7074f7d7..213422063de3 100644
--- a/drivers/gpu/drm/xe/regs/xe_gt_regs.h
+++ b/drivers/gpu/drm/xe/regs/xe_gt_regs.h
@@ -426,6 +426,9 @@
 #define   L3_ESC_MASK				REG_BIT(0)
 #define   L3_ESC(value)				REG_FIELD_PREP(L3_ESC_MASK, value)
 
+#define L3_NODE_IDLE				XE_REG_MCR(0xb0b0)
+#define L3STAT_LBCF_GFX				XE_REG_MCR(0xb128)
+
 #define XEHP_L3NODEARBCFG			XE_REG_MCR(0xb0b4)
 #define   XEHP_LNESPARE				REG_BIT(19)
 
diff --git a/drivers/gpu/drm/xe/xe_devcoredump.c b/drivers/gpu/drm/xe/xe_devcoredump.c
index 37893d09d05e..5099d545726e 100644
--- a/drivers/gpu/drm/xe/xe_devcoredump.c
+++ b/drivers/gpu/drm/xe/xe_devcoredump.c
@@ -28,6 +28,7 @@
 #include "xe_mmio.h"
 #include "regs/xe_gt_regs.h"
 #include "regs/xe_guc_regs.h"
+#include "xe_gt_mcr.h"
 
 /**
  * DOC: Xe device coredump
@@ -79,13 +80,18 @@
  * of the register to dump its value during coredump for debug purpose.
  */
 struct xe_reg_desc {
-	/** @reg: The register */
-	struct xe_reg reg;
+	union {
+		/** @reg: The register */
+		struct xe_reg reg;
+		/** @mcr_reg: The mcr register */
+		struct xe_reg_mcr mcr_reg;
+	};
 	/** @name: Name of the register */
 	const char *name;
 };
 
 #define XE_REG_DESC(_reg, _name)	{ .reg = (_reg), .name = (_name) }
+#define XE_REG_DESC_MCR(_reg, _name)	{ .mcr_reg = (_reg), .name = (_name) }
 
 static const struct xe_reg_desc xe3p_gt_guc_reglist[] = {
 	XE_REG_DESC(GUC_STATUS,	"GUC_STATUS"),
@@ -132,6 +138,11 @@ static const struct xe_reg_desc xe3p_gam_pf_reglist[] = {
 	XE_REG_DESC(PAGE_FLTRPTQ_TAIL_GAMCTRL, "PAGE_FLTRPTQ_TAIL_GAMCTRL"),
 };
 
+static const struct xe_reg_desc xe3p_l3_node_reglist[] = {
+	XE_REG_DESC_MCR(L3_NODE_IDLE, "L3_NODE_IDLE"),
+	XE_REG_DESC_MCR(L3STAT_LBCF_GFX, "L3STAT_LBCF_GFX"),
+};
+
 /**
  * struct xe_reg_desc_list - Struct for register descriptor list
  *
@@ -195,6 +206,13 @@ static const struct xe_gt_regset xe_gam_pf_regset = {
 	},
 };
 
+static const struct xe_gt_regset xe_l3_node_regset = {
+	.gt[XE_GT_TYPE_MAIN] = {
+		.regs = xe3p_l3_node_reglist,
+		.num_regs = ARRAY_SIZE(xe3p_l3_node_reglist),
+	},
+};
+
 #define XE_GT_REG_LIST(_type, _gt_type) \
 	(&xe_##_type##_regset.gt[XE_GT_TYPE_##_gt_type])
 
@@ -208,7 +226,10 @@ xe_capture_reg_desc_list(struct xe_gt *gt,
 
 	for (i = 0; i < count; i++) {
 		dst[i].reg = src[i].reg;
-		dst[i].value = xe_mmio_read32(&gt->mmio, src[i].reg);
+		if (src[i].reg.mcr)
+			dst[i].value = xe_gt_mcr_unicast_read_any(gt, src[i].mcr_reg);
+		else
+			dst[i].value = xe_mmio_read32(&gt->mmio, src[i].reg);
 		dst[i].name = src[i].name;
 	}
 }
@@ -373,6 +394,16 @@ static struct xe_dbg_reg_snapshot *xe_gam_pf_report_capture(struct xe_gt *gt)
 						  XE_GT_REG_LIST(gam_pf, MAIN));
 }
 
+static struct xe_dbg_reg_snapshot *xe_node_status_capture(struct xe_gt *gt)
+{
+	if (!gt || !gt->tile || !gt->tile->primary_gt)
+		return NULL;
+
+	return xe_dbg_reg_snapshot_capture_target(gt,
+						  gt->tile->primary_gt,
+						  XE_GT_REG_LIST(l3_node, MAIN));
+}
+
 static struct xe_device *coredump_to_xe(const struct xe_devcoredump *coredump)
 {
 	return container_of(coredump, struct xe_device, devcoredump);
@@ -440,6 +471,9 @@ static ssize_t __xe_devcoredump_read(char *buffer, ssize_t count,
 	drm_printf(&p, "\n**** GAM PF Report ****\n");
 	xe_gam_pf_snapshot_print(&p, ss->gam_pf_report);
 
+	drm_printf(&p, "\n**** Node Status ****\n");
+	xe_dbg_reg_snapshot_print(&p, ss->ns);
+
 	drm_puts(&p, "\n**** Contexts ****\n");
 	xe_guc_exec_queue_snapshot_print(ss->ge, &p);
 
@@ -495,6 +529,9 @@ static void xe_devcoredump_snapshot_free(struct xe_devcoredump_snapshot *ss)
 	xe_dbg_reg_snapshot_free(ss->gam_pf_report);
 	ss->gam_pf_report = NULL;
 
+	xe_dbg_reg_snapshot_free(ss->ns);
+	ss->ns = NULL;
+
 	xe_guc_exec_queue_snapshot_free(ss->ge);
 	ss->ge = NULL;
 
@@ -702,6 +739,9 @@ static void devcoredump_snapshot(struct xe_devcoredump *coredump,
 	ss->guc.log = xe_guc_log_snapshot_capture(&guc->log, true);
 	ss->guc.ct = xe_guc_ct_snapshot_capture(&guc->ct);
 	ss->gam_pf_report = xe_gam_pf_report_capture(q->gt);
+
+	ss->ns = xe_node_status_capture(q->gt);
+
 	ss->ge = xe_guc_exec_queue_snapshot_capture(q);
 	if (job)
 		ss->job = xe_sched_job_snapshot_capture(job);
diff --git a/drivers/gpu/drm/xe/xe_devcoredump_types.h b/drivers/gpu/drm/xe/xe_devcoredump_types.h
index ea7638d0a7a2..6f6d1a80dbb6 100644
--- a/drivers/gpu/drm/xe/xe_devcoredump_types.h
+++ b/drivers/gpu/drm/xe/xe_devcoredump_types.h
@@ -92,6 +92,8 @@ struct xe_devcoredump_snapshot {
 
 	/** @gam_pf_report: GAM PF report snapshot */
 	struct xe_dbg_reg_snapshot *gam_pf_report;
+	/** @ns: Node status snapshot */
+	struct xe_dbg_reg_snapshot *ns;
 
 	/** @ge: GuC Submission Engine snapshot */
 	struct xe_guc_submit_exec_queue_snapshot *ge;
-- 
2.43.0

[PATCH v2 7/7] drm/xe/guc: capture additional engine state registers

[Nareshkumar Gollakoti]

Add a wider set of engine state registers to GuC error capture to improve
post-mortem debugging of engine hangs and reset-related failures.

Define the missing register offsets in xe_engine_regs.h and include them in
the GuC capture list. The additional registers cover reset state, front-end
and back-end FSM state, power state, batch buffer state, instruction state,
preemption status, and related chicken/debug controls.

This provides more complete engine context in capture dumps, which should
help root-cause analysis when investigating GuC-reported engine failures.

Signed-off-by: Nareshkumar Gollakoti <naresh.kumar.g@intel.com>
---
 drivers/gpu/drm/xe/regs/xe_engine_regs.h | 22 ++++++++++++++++++++++
 drivers/gpu/drm/xe/xe_guc_capture.c      | 20 +++++++++++++++++++-
 2 files changed, 41 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/xe/regs/xe_engine_regs.h b/drivers/gpu/drm/xe/regs/xe_engine_regs.h
index 94033982e694..c661abf69249 100644
--- a/drivers/gpu/drm/xe/regs/xe_engine_regs.h
+++ b/drivers/gpu/drm/xe/regs/xe_engine_regs.h
@@ -60,6 +60,8 @@
 
 #define RING_START_UDW(base)			XE_REG((base) + 0x48)
 
+#define RING_CSFE_GLB_CHICKEN3(base)		XE_REG((base) + 0x4c)
+
 #define RING_PSMI_CTL(base)			XE_REG((base) + 0x50, XE_REG_OPTION_MASKED)
 #define   RC_SEMA_IDLE_MSG_DISABLE		REG_BIT(12)
 #define   WAIT_FOR_EVENT_POWER_DOWN_DISABLE	REG_BIT(7)
@@ -72,6 +74,7 @@
 #define RING_DMA_FADD_UDW(base)			XE_REG((base) + 0x60)
 #define RING_IPEHR(base)			XE_REG((base) + 0x68)
 #define RING_INSTDONE(base)			XE_REG((base) + 0x6c)
+#define RING_INSTPS(base)			XE_REG((base) + 0x70)
 #define RING_ACTHD(base)			XE_REG((base) + 0x74)
 #define RING_DMA_FADD(base)			XE_REG((base) + 0x78)
 #define RING_HWS_PGA(base)			XE_REG((base) + 0x80)
@@ -102,6 +105,8 @@
 #define   SELECTIVE_READ_GROUP			REG_GENMASK(29, 23)
 #define   SELECTIVE_READ_INSTANCE		REG_GENMASK(22, 16)
 
+#define RESET_CTRL(base)			XE_REG((base) + 0xd0)
+
 /*
  * CMD_CCTL read/write fields take a MOCS value and _not_ a table index.
  * The lsb of each can be considered a separate enabling bit for encryption.
@@ -123,15 +128,21 @@
 #define FF_SLICE_CS_CHICKEN1(base)		XE_REG((base) + 0xe0, XE_REG_OPTION_MASKED)
 #define   FFSC_PERCTX_PREEMPT_CTRL		REG_BIT(14)
 
+#define FF_SLICE_CS_CHICKEN2(base)		XE_REG((base) + 0xe4, XE_REG_OPTION_MASKED)
+
 #define CS_DEBUG_MODE1(base)			XE_REG((base) + 0xec, XE_REG_OPTION_MASKED)
 #define   FF_DOP_CLOCK_GATE_DISABLE		REG_BIT(1)
 #define   REPLAY_MODE_GRANULARITY		REG_BIT(0)
 
 #define INDIRECT_RING_STATE(base)		XE_REG((base) + 0x108)
 
+#define RING_BB_STATE(base)				XE_REG((base) + 0x110)
+
 #define RING_BBADDR(base)			XE_REG((base) + 0x140)
 #define RING_BBADDR_UDW(base)			XE_REG((base) + 0x168)
 
+#define RING_BB_ADDR_DIFF(base)			XE_REG((base) + 0x154)
+
 #define PR_CTR_CTRL(base)			XE_REG((base) + 0x178)
 #define   CTR_COUNT_SELECT_FF			REG_BIT(31)
 #define   CTR_LOGIC_OP_MASK			REG_GENMASK(30, 0)
@@ -148,6 +159,8 @@
 #define   BLIT_CCTL_DST_MOCS_MASK		REG_GENMASK(14, 9)
 #define   BLIT_CCTL_SRC_MOCS_MASK		REG_GENMASK(6, 1)
 
+#define RING_CSBEFSM3(base)			XE_REG((base) + 0x224)
+
 #define RING_EXECLIST_STATUS_LO(base)		XE_REG((base) + 0x234)
 #define RING_EXECLIST_STATUS_HI(base)		XE_REG((base) + 0x234 + 4)
 
@@ -169,9 +182,16 @@
 #define   GFX_MSIX_INTERRUPT_ENABLE		REG_BIT(13)
 #define   GFX_DISABLE_LEGACY_MODE		REG_BIT(3)
 
+#define RING_CSFESM(base)			XE_REG((base) + 0x2a0)
+#define RING_CSFESM2(base)			XE_REG((base) + 0x2a4)
+#define RING_CSFESM3(base)			XE_REG((base) + 0x2a8)
+#define RING_CSPWRFSM(base)			XE_REG((base) + 0x2ac)
+
 #define RING_CSMQDEBUG(base)			XE_REG((base) + 0x2b0)
 #define   CURRENT_ACTIVE_QUEUE_ID_MASK		REG_GENMASK(7, 0)
 
+#define RING_CSBEFSM(base)			XE_REG((base) + 0x2bc)
+
 #define RING_QUEUE_TIMESTAMP(base)		XE_REG((base) + 0x4c0)
 #define RING_QUEUE_TIMESTAMP_UDW(base)		XE_REG((base) + 0x4c0 + 4)
 
@@ -217,6 +237,8 @@
 #define   PREEMPT_GPGPU_LEVEL_MASK		PREEMPT_GPGPU_LEVEL(1, 1)
 #define   PREEMPT_3D_OBJECT_LEVEL		REG_BIT(0)
 
+#define CS_PREEMPTION_STATUS(base)		XE_REG((base) + 0x5ac)
+
 #define CS_GPR_DATA(base, n)			XE_REG((base) + 0x600 + (n) * 4)
 #define CS_GPR_REG(base, n)			CS_GPR_DATA((base), (n) * 2)
 #define CS_GPR_REG_UDW(base, n)			CS_GPR_DATA((base), (n) * 2 + 1)
diff --git a/drivers/gpu/drm/xe/xe_guc_capture.c b/drivers/gpu/drm/xe/xe_guc_capture.c
index 62832bd4af78..37e7e3d92bfc 100644
--- a/drivers/gpu/drm/xe/xe_guc_capture.c
+++ b/drivers/gpu/drm/xe/xe_guc_capture.c
@@ -131,7 +131,25 @@ struct __guc_capture_parsed_output {
 	{ RING_EXECLIST_STATUS_LO(0),	REG_64BIT_LOW_DW, 0,	0,	0,	NULL}, \
 	{ RING_EXECLIST_STATUS_HI(0),	REG_64BIT_HI_DW, 0,	0,	0,	"RING_EXECLIST_STATUS"}, \
 	{ RING_EXECLIST_SQ_CONTENTS_LO(0), REG_64BIT_LOW_DW, 0,	0,	0,	NULL}, \
-	{ RING_EXECLIST_SQ_CONTENTS_HI(0), REG_64BIT_HI_DW, 0,	0,	0,	"RING_EXECLIST_SQ_CONTENTS"}
+	{ RING_EXECLIST_SQ_CONTENTS_HI(0), REG_64BIT_HI_DW, 0, 0, 0, "RING_EXECLIST_SQ_CONTENTS"}, \
+	{ RESET_CTRL(0),	REG_32BIT, 0, 0, 0,	"RESET_CTRL"}, \
+	{ RING_CSBEFSM3(0),	REG_32BIT,	0,	0,	0,	"RING_CSBEFSM3"}, \
+	{ RING_CSFESM(0),	REG_32BIT,	0,	0,	0,	"RING_CSFESM"}, \
+	{ RING_CSFESM2(0),	REG_32BIT,	0,	0,	0,	"RING_CSFESM2"}, \
+	{ RING_CSFESM3(0),	REG_32BIT,	0,	0,	0,	"RING_CSFESM3"}, \
+	{ RING_CSPWRFSM(0),	REG_32BIT,	0,	0,	0,	"RING_CSPWRFSM"}, \
+	{ RING_CSBEFSM(0),	REG_32BIT,	0,	0,	0,	"RING_CSBEFSM1"}, \
+	{ BCS_SWCTRL(0),	REG_32BIT,	0,	0,	0,	"BCS_SWCTRL"}, \
+	{ RING_CSFE_GLB_CHICKEN3(0), REG_32BIT, 0, 0, 0, "RING_CSFE_GLB_CHICKEN3" }, \
+	{ RING_PSMI_CTL(0),	REG_32BIT,	0,	0,	0,	"RING_PSMI_CTL"}, \
+	{ RING_INSTPS(0),	REG_32BIT,	0,	0,	0,	"RING_INSTPS"}, \
+	{ RING_BB_ADDR_DIFF(0),	REG_32BIT,	0,	0,	0,	"RING_BB_ADDR_DIFF"}, \
+	{ RING_BB_STATE(0),	REG_32BIT,	0,	0,	0,	"RING_BB_STATE"}, \
+	{ FF_SLICE_CS_CHICKEN1(0), REG_32BIT, 0, 0, 0, "FF_SLICE_CS_CHICKEN1" }, \
+	{ CS_DEBUG_MODE1(0),	REG_32BIT,	0,	0,	0,	"CS_DEBUG_MODE1"}, \
+	{ CS_CHICKEN1(0),	REG_32BIT,	0,	0,	0,	"CS_CHICKEN1"}, \
+	{ CS_PREEMPTION_STATUS(0), REG_32BIT, 0, 0, 0, "CS_PREEMPTION_STATUS" }, \
+	{ FF_SLICE_CS_CHICKEN2(0), REG_32BIT, 0, 0, 0, "FF_SLICE_CS_CHICKEN2" }
 
 #define COMMON_XELP_RC_CLASS \
 	{ RCU_MODE,			REG_32BIT,	0,	0,	0,	"RCU_MODE"}
-- 
2.43.0

Re: [PATCH v2 1/7] drm/xe/devcoredump: Capture GT fuse registers in devcoredump

[sashiko-bot]

Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [Medium] Incorrect register and bitmask used to determine render awake status in devcoredump.
--

--- Patch [1]: [PATCH v2 1/7] drm/xe/devcoredump: Capture GT fuse registers in devcoredump ---
commit 963c6786cf6616eea5a69f2bd77da1dc93b6d6ff
Author: Nareshkumar Gollakoti <naresh.kumar.g@intel.com>

drm/xe/devcoredump: Capture GT fuse registers in devcoredump
    
Capture fuse-related GT register state in the Xe devcoredump to preserve
additional hardware configuration information for postmortem debugging.

> diff --git a/drivers/gpu/drm/xe/xe_devcoredump.c b/drivers/gpu/drm/xe/xe_devcoredump.c
> index 5f2b90b18f97b..e5c33bc941030 100644
> --- a/drivers/gpu/drm/xe/xe_devcoredump.c
> +++ b/drivers/gpu/drm/xe/xe_devcoredump.c
[ ... ]
> @@ -69,6 +71,232 @@
>  /* 1 hour timeout */
>  #define XE_COREDUMP_TIMEOUT_JIFFIES (60 * 60 * HZ)
>  
[ ... ]
> +static const struct xe_reg_desc xe3p_gt_rpm_reglist[] = {
> +	XE_REG_DESC(RPM_GCD, "RPM_GCD"),
> +	XE_REG_DESC(POWERGATE_ENABLE, "POWERGATE_ENABLE"),
> +};
[ ... ]
> +static void xe_gt_rpm_snapshot_print(struct drm_printer *p,
> +				     const struct xe_dbg_reg_snapshot *snap)
> +{
> +	xe_dbg_reg_snapshot_print(p, snap);
> +
> +	if (snap && snap->num_regs >= 2 && !(snap->regs[1].value & 0x2))
> +		drm_puts(p, "render is not awake\n");
> +}

[Severity: Medium]
Are we checking the correct register and bit for the render awake status here?

It looks like xe3p_gt_rpm_reglist captures POWERGATE_ENABLE at index 1,
instead of POWERGATE_DOMAIN_STATUS. If so, evaluating
!(snap->regs[1].value & 0x2) would check the media powergate enable status
(bit 0x2 of POWERGATE_ENABLE) rather than the actual render awake status.

This could result in incorrect diagnostic information being printed in the
devcoredump.

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20260824184356.1960708-1-naresh.kumar.g@intel.com?part=1

Re: [PATCH v2 3/7] drm/xe/guc: Print register addresses in capture snapshot output

[sashiko-bot]

Thank you for your contribution! Sashiko AI review found 2 potential issue(s) to consider:
- [Medium] Incorrect register address calculation for 64-bit registers
- [Low] Format string type mismatch for size_t
--

--- Patch [3]: [PATCH v2 3/7] drm/xe/guc: Print register addresses in capture snapshot output ---
commit baf33cc78a6f2c33ba405aaad2eb334575f207ed
Author: Nareshkumar Gollakoti <naresh.kumar.g@intel.com>

drm/xe/guc: Print register addresses in capture snapshot output
    
This commit modifies the GuC capture snapshot output to include register
offsets alongside their names for both 32-bit and 64-bit registers.

> diff --git a/drivers/gpu/drm/xe/xe_guc_capture.c b/drivers/gpu/drm/xe/xe_guc_capture.c
> index 82df19b304e17..324f25af3b0d0 100644
> --- a/drivers/gpu/drm/xe/xe_guc_capture.c
> +++ b/drivers/gpu/drm/xe/xe_guc_capture.c
> @@ -1774,7 +1774,9 @@ snapshot_print_by_list_order(struct xe_hw_engine_snapshot *snapshot, struct drm_
>  			XE_WARN_ON(!low32_ready);
>  			low32_ready = false;
>  
> -			drm_printf(p, "\t%s: 0x%016llx\n", reg_desc->regname, value_qw);
> +			drm_printf(p, "\t%s (0x%lx): 0x%016llx\n", reg_desc->regname,
> +				   reg_desc->reg.addr - sizeof(u32),
> +				   value_qw);

[Severity: Medium]
Does this correctly calculate the base address for all 64-bit registers?

In the Intel Xe engine MMIO layout, the upper and lower 32-bit registers are
not always exactly 4 bytes apart.

For example, RING_ACTHD (lower 32-bit) is located at offset 0x74, while
RING_ACTHD_UDW (upper 32-bit) is at 0x5c. RING_BBADDR is at 0x140 and
RING_BBADDR_UDW is at 0x168.

By subtracting 4 from 0x5c, the output would incorrectly print 0x58 for ACTHD,
which is actually the address of RING_HWSTAM.

[Severity: Low]
Will this format string trigger a compiler warning on 32-bit platforms?

The expression reg_desc->reg.addr - sizeof(u32) subtracts a size_t from a u32,
promoting the result to size_t. The format string uses %lx, which expects an
unsigned long.

On 32-bit platforms (where the driver can be compile-tested), size_t is
typically unsigned int. Passing an unsigned int to %lx triggers a -Wformat
compiler warning, which could break builds using -Werror.

Should this use %zx for size_t, or explicitly cast the result to u32 and
use %x?

>  			break;
>  		}

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20260824184356.1960708-1-naresh.kumar.g@intel.com?part=3

Re: [PATCH v2 7/7] drm/xe/guc: capture additional engine state registers

[sashiko-bot]

Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [Medium] Engine-specific state registers (e.g., BCS_SWCTRL, FF_SLICE_CS_CHICKEN1) are incorrectly added to the `COMMON_BASE_ENGINE_INSTANCE` macro, causing GuC to attempt invalid MMIO reads on non-matching engine classes.
--

--- Patch [7]: [PATCH v2 7/7] drm/xe/guc: capture additional engine state registers ---
commit a1d512f9f15bd162d8a7f22264dfc3c44b0fa414
Author: Nareshkumar Gollakoti <naresh.kumar.g@intel.com>

drm/xe/guc: capture additional engine state registers

This commit adds a wider set of engine state registers to GuC error capture
to improve post-mortem debugging of engine hangs and reset-related
failures. It defines the missing register offsets and includes them in the
GuC capture list.

> diff --git a/drivers/gpu/drm/xe/xe_guc_capture.c b/drivers/gpu/drm/xe/xe_guc_capture.c
> index 62832bd4af78d..37e7e3d92bfcc 100644
> --- a/drivers/gpu/drm/xe/xe_guc_capture.c
> +++ b/drivers/gpu/drm/xe/xe_guc_capture.c
[ ... ]
> @@ -131,7 +131,25 @@ struct __guc_capture_parsed_output {
>  	{ RING_EXECLIST_STATUS_LO(0),	REG_64BIT_LOW_DW, 0,	0,	0,	NULL}, \
>  	{ RING_EXECLIST_STATUS_HI(0),	REG_64BIT_HI_DW, 0,	0,	0,	"RING_EXECLIST_STATUS"}, \
>  	{ RING_EXECLIST_SQ_CONTENTS_LO(0), REG_64BIT_LOW_DW, 0,	0,	0,	NULL}, \
> -	{ RING_EXECLIST_SQ_CONTENTS_HI(0), REG_64BIT_HI_DW, 0,	0,	0,	"RING_EXECLIST_SQ_CONTENTS"}
> +	{ RING_EXECLIST_SQ_CONTENTS_HI(0), REG_64BIT_HI_DW, 0, 0, 0, "RING_EXECLIST_SQ_CONTENTS"}, \
> +	{ RESET_CTRL(0),	REG_32BIT, 0, 0, 0,	"RESET_CTRL"}, \
> +	{ RING_CSBEFSM3(0),	REG_32BIT,	0,	0,	0,	"RING_CSBEFSM3"}, \
> +	{ RING_CSFESM(0),	REG_32BIT,	0,	0,	0,	"RING_CSFESM"}, \
> +	{ RING_CSFESM2(0),	REG_32BIT,	0,	0,	0,	"RING_CSFESM2"}, \
> +	{ RING_CSFESM3(0),	REG_32BIT,	0,	0,	0,	"RING_CSFESM3"}, \
> +	{ RING_CSPWRFSM(0),	REG_32BIT,	0,	0,	0,	"RING_CSPWRFSM"}, \
> +	{ RING_CSBEFSM(0),	REG_32BIT,	0,	0,	0,	"RING_CSBEFSM1"}, \
> +	{ BCS_SWCTRL(0),	REG_32BIT,	0,	0,	0,	"BCS_SWCTRL"}, \
> +	{ RING_CSFE_GLB_CHICKEN3(0), REG_32BIT, 0, 0, 0, "RING_CSFE_GLB_CHICKEN3" }, \

[Severity: Medium]
Does adding class-specific state registers like BCS_SWCTRL to the
COMMON_BASE_ENGINE_INSTANCE macro cause the GuC to attempt invalid MMIO reads
on non-matching engine classes?

Reading class-specific registers on all hardware engines could lead to
unclaimed register errors during an error capture on a Video or GSC engine,
which may flood the system logs with warnings.

> +	{ RING_PSMI_CTL(0),	REG_32BIT,	0,	0,	0,	"RING_PSMI_CTL"}, \
> +	{ RING_INSTPS(0),	REG_32BIT,	0,	0,	0,	"RING_INSTPS"}, \
> +	{ RING_BB_ADDR_DIFF(0),	REG_32BIT,	0,	0,	0,	"RING_BB_ADDR_DIFF"}, \
> +	{ RING_BB_STATE(0),	REG_32BIT,	0,	0,	0,	"RING_BB_STATE"}, \
> +	{ FF_SLICE_CS_CHICKEN1(0), REG_32BIT, 0, 0, 0, "FF_SLICE_CS_CHICKEN1" }, \
> +	{ CS_DEBUG_MODE1(0),	REG_32BIT,	0,	0,	0,	"CS_DEBUG_MODE1"}, \
> +	{ CS_CHICKEN1(0),	REG_32BIT,	0,	0,	0,	"CS_CHICKEN1"}, \
> +	{ CS_PREEMPTION_STATUS(0), REG_32BIT, 0, 0, 0, "CS_PREEMPTION_STATUS" }, \
> +	{ FF_SLICE_CS_CHICKEN2(0), REG_32BIT, 0, 0, 0, "FF_SLICE_CS_CHICKEN2" }

[Severity: Medium]
Are these render-specific registers (FF_SLICE_*) being appended to the common
base macro?

This might pollute the register list for all engine classes. Should these be
placed in a class-specific list instead to avoid invalid hardware accesses
when non-matching engines hang?

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20260824184356.1960708-1-naresh.kumar.g@intel.com?part=7

✓ CI.KUnit: success for drm/xe: Capture additional HW register state in devcoredump (rev2)

[Patchwork]

== Series Details ==

Series: drm/xe: Capture additional HW register state in devcoredump (rev2)
URL   : https://patchwork.freedesktop.org/series/172150/
State : success

== Summary ==

+ trap cleanup EXIT
+ /kernel/tools/testing/kunit/kunit.py run --kunitconfig /kernel/drivers/gpu/drm/xe/.kunitconfig
[23:48:43] Configuring KUnit Kernel ...
Generating .config ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
[23:48:48] Building KUnit Kernel ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
Building with:
$ make all compile_commands.json scripts_gdb ARCH=um O=.kunit --jobs=48
[23:49:20] Starting KUnit Kernel (1/1)...
[23:49:20] ============================================================
Running tests with:
$ .kunit/linux kunit.enable=1 mem=1G console=tty kunit_shutdown=halt
[23:49:20] ================== guc_buf (11 subtests) ===================
[23:49:20] [PASSED] test_smallest
[23:49:20] [PASSED] test_largest
[23:49:20] [PASSED] test_granular
[23:49:20] [PASSED] test_unique
[23:49:20] [PASSED] test_overlap
[23:49:20] [PASSED] test_reusable
[23:49:20] [PASSED] test_too_big
[23:49:20] [PASSED] test_flush
[23:49:20] [PASSED] test_lookup
[23:49:20] [PASSED] test_data
[23:49:20] [PASSED] test_class
[23:49:20] ===================== [PASSED] guc_buf =====================
[23:49:20] =================== guc_dbm (7 subtests) ===================
[23:49:20] [PASSED] test_empty
[23:49:20] [PASSED] test_default
[23:49:20] ======================== test_size  ========================
[23:49:20] [PASSED] 4
[23:49:20] [PASSED] 8
[23:49:20] [PASSED] 32
[23:49:20] [PASSED] 256
[23:49:20] ==================== [PASSED] test_size ====================
[23:49:20] ======================= test_reuse  ========================
[23:49:20] [PASSED] 4
[23:49:20] [PASSED] 8
[23:49:20] [PASSED] 32
[23:49:20] [PASSED] 256
[23:49:20] =================== [PASSED] test_reuse ====================
[23:49:20] =================== test_range_overlap  ====================
[23:49:20] [PASSED] 4
[23:49:20] [PASSED] 8
[23:49:20] [PASSED] 32
[23:49:20] [PASSED] 256
[23:49:20] =============== [PASSED] test_range_overlap ================
[23:49:20] =================== test_range_compact  ====================
[23:49:20] [PASSED] 4
[23:49:20] [PASSED] 8
[23:49:20] [PASSED] 32
[23:49:20] [PASSED] 256
[23:49:20] =============== [PASSED] test_range_compact ================
[23:49:20] ==================== test_range_spare  =====================
[23:49:20] [PASSED] 4
[23:49:20] [PASSED] 8
[23:49:20] [PASSED] 32
[23:49:20] [PASSED] 256
[23:49:20] ================ [PASSED] test_range_spare =================
[23:49:20] ===================== [PASSED] guc_dbm =====================
[23:49:20] =================== guc_idm (6 subtests) ===================
[23:49:20] [PASSED] bad_init
[23:49:20] [PASSED] no_init
[23:49:20] [PASSED] init_fini
[23:49:20] [PASSED] check_used
[23:49:20] [PASSED] check_quota
[23:49:20] [PASSED] check_all
[23:49:20] ===================== [PASSED] guc_idm =====================
[23:49:20] =============== guc_klv_helpers (9 subtests) ===============
[23:49:20] [PASSED] test_count
[23:49:20] [PASSED] test_encode_u32
[23:49:20] [PASSED] test_encode_u64
[23:49:20] [PASSED] test_encode_string
[23:49:20] [PASSED] test_encode_object_raw
[23:49:20] [PASSED] test_encode_object_klv
[23:49:20] [PASSED] test_encode_object_nested
[23:49:20] [PASSED] test_encode_object_basic
[23:49:20] [PASSED] test_print
[23:49:20] ================= [PASSED] guc_klv_helpers =================
[23:49:20] =================== xe_log (4 subtests) ====================
[23:49:20] [PASSED] demo_cper
[23:49:20] [PASSED] demo_dmesg
[23:49:20] ======================= test_dmesg  ========================
[23:49:20] [PASSED] test_fatal
[23:49:20] [PASSED] test_fatal_tile
[23:49:20] [PASSED] test_fatal_gt
[23:49:20] [PASSED] test_fatal_comp
[23:49:20] [PASSED] test_fatal_comp_tile
[23:49:20] [PASSED] test_fatal_comp_gt
[23:49:20] [PASSED] test_fatal_all
[23:49:20] [PASSED] test_recoverable
[23:49:20] [PASSED] test_recoverable_tile
[23:49:20] [PASSED] test_recoverable_gt
[23:49:20] [PASSED] test_recoverable_comp
[23:49:20] [PASSED] test_recoverable_comp_tile
[23:49:20] [PASSED] test_recoverable_comp_gt
[23:49:20] [PASSED] test_recoverable_all
[23:49:20] [PASSED] test_info
[23:49:20] [PASSED] test_info_tile
[23:49:20] [PASSED] test_info_gt
[23:49:20] [PASSED] test_info_err
[23:49:20] [PASSED] test_info_comp
[23:49:20] [PASSED] test_info_comp_tile
[23:49:20] [PASSED] test_info_comp_gt
[23:49:20] [PASSED] test_info_all
[23:49:20] [PASSED] test_hw_fatal
[23:49:20] [PASSED] test_hw_recoverable
[23:49:20] [PASSED] test_hw_corrected
[23:49:20] [PASSED] test_hw_informational
[23:49:20] =================== [PASSED] test_dmesg ====================
[23:49:20] ====================== test_invalid  =======================
[23:49:20] [SKIPPED] no-component no-location no-warn (requires CONFIG_DRM_XE_DEBUG)
[23:49:20] [SKIPPED] reserved location (requires CONFIG_DRM_XE_DEBUG)
[23:49:20] [SKIPPED] unknown location (requires CONFIG_DRM_XE_DEBUG)
[23:49:20] [SKIPPED] nonzero-device-id location (requires CONFIG_DRM_XE_DEBUG)
[23:49:20] [SKIPPED] invalid-tile-id location (requires CONFIG_DRM_XE_DEBUG)
[23:49:20] [SKIPPED] invalid-gt-id location (requires CONFIG_DRM_XE_DEBUG)
[23:49:20] [SKIPPED] unknown component class (requires CONFIG_DRM_XE_DEBUG)
[23:49:20] [SKIPPED] unknown system component (requires CONFIG_DRM_XE_DEBUG)
[23:49:20] [SKIPPED] unknown hardware component (requires CONFIG_DRM_XE_DEBUG)
[23:49:20] [SKIPPED] unknown component and location (requires CONFIG_DRM_XE_DEBUG)
[23:49:20] ================== [SKIPPED] test_invalid ==================
[23:49:20] ===================== [PASSED] xe_log ======================
[23:49:20] ================== no_relay (3 subtests) ===================
[23:49:20] [PASSED] xe_drops_guc2pf_if_not_ready
[23:49:20] [PASSED] xe_drops_guc2vf_if_not_ready
[23:49:20] [PASSED] xe_rejects_send_if_not_ready
[23:49:20] ==================== [PASSED] no_relay =====================
[23:49:20] ================== pf_relay (14 subtests) ==================
[23:49:20] [PASSED] pf_rejects_guc2pf_too_short
[23:49:20] [PASSED] pf_rejects_guc2pf_too_long
[23:49:20] [PASSED] pf_rejects_guc2pf_no_payload
[23:49:20] [PASSED] pf_fails_no_payload
[23:49:20] [PASSED] pf_fails_bad_origin
[23:49:20] [PASSED] pf_fails_bad_type
[23:49:20] [PASSED] pf_txn_reports_error
[23:49:20] [PASSED] pf_txn_sends_pf2guc
[23:49:20] [PASSED] pf_sends_pf2guc
[23:49:20] [SKIPPED] pf_loopback_nop (requires CONFIG_DRM_XE_DEBUG_SRIOV)
[23:49:20] [SKIPPED] pf_loopback_echo (requires CONFIG_DRM_XE_DEBUG_SRIOV)
[23:49:20] [SKIPPED] pf_loopback_fail (requires CONFIG_DRM_XE_DEBUG_SRIOV)
[23:49:20] [SKIPPED] pf_loopback_busy (requires CONFIG_DRM_XE_DEBUG_SRIOV)
[23:49:20] [SKIPPED] pf_loopback_retry (requires CONFIG_DRM_XE_DEBUG_SRIOV)
[23:49:20] ==================== [PASSED] pf_relay =====================
[23:49:20] ================== vf_relay (3 subtests) ===================
[23:49:20] [PASSED] vf_rejects_guc2vf_too_short
[23:49:20] [PASSED] vf_rejects_guc2vf_too_long
[23:49:20] [PASSED] vf_rejects_guc2vf_no_payload
[23:49:20] ==================== [PASSED] vf_relay =====================
[23:49:20] ================ pf_gt_config (9 subtests) =================
[23:49:20] [PASSED] fair_contexts_1vf
[23:49:20] [PASSED] fair_doorbells_1vf
[23:49:20] [PASSED] fair_ggtt_1vf
[23:49:20] ====================== fair_vram_1vf  ======================
[23:49:20] [PASSED] 3.50 GiB
[23:49:20] [PASSED] 11.5 GiB
[23:49:20] [PASSED] 15.5 GiB
[23:49:20] [PASSED] 31.5 GiB
[23:49:20] [PASSED] 63.5 GiB
[23:49:20] [PASSED] 1.91 GiB
[23:49:20] ================== [PASSED] fair_vram_1vf ==================
[23:49:20] ================ fair_vram_1vf_admin_only  =================
[23:49:20] [PASSED] 3.50 GiB
[23:49:20] [PASSED] 11.5 GiB
[23:49:20] [PASSED] 15.5 GiB
[23:49:20] [PASSED] 31.5 GiB
[23:49:20] [PASSED] 63.5 GiB
[23:49:20] [PASSED] 1.91 GiB
[23:49:20] ============ [PASSED] fair_vram_1vf_admin_only =============
[23:49:20] ====================== fair_contexts  ======================
[23:49:20] [PASSED] 1 VF
[23:49:20] [PASSED] 2 VFs
[23:49:20] [PASSED] 3 VFs
[23:49:20] [PASSED] 4 VFs
[23:49:20] [PASSED] 5 VFs
[23:49:20] [PASSED] 6 VFs
[23:49:20] [PASSED] 7 VFs
[23:49:20] [PASSED] 8 VFs
[23:49:20] [PASSED] 9 VFs
[23:49:20] [PASSED] 10 VFs
[23:49:20] [PASSED] 11 VFs
[23:49:20] [PASSED] 12 VFs
[23:49:20] [PASSED] 13 VFs
[23:49:20] [PASSED] 14 VFs
[23:49:20] [PASSED] 15 VFs
[23:49:20] [PASSED] 16 VFs
[23:49:20] [PASSED] 17 VFs
[23:49:20] [PASSED] 18 VFs
[23:49:20] [PASSED] 19 VFs
[23:49:20] [PASSED] 20 VFs
[23:49:20] [PASSED] 21 VFs
[23:49:20] [PASSED] 22 VFs
[23:49:20] [PASSED] 23 VFs
[23:49:20] [PASSED] 24 VFs
[23:49:20] [PASSED] 25 VFs
[23:49:20] [PASSED] 26 VFs
[23:49:20] [PASSED] 27 VFs
[23:49:20] [PASSED] 28 VFs
[23:49:20] [PASSED] 29 VFs
[23:49:20] [PASSED] 30 VFs
[23:49:20] [PASSED] 31 VFs
[23:49:20] [PASSED] 32 VFs
[23:49:20] [PASSED] 33 VFs
[23:49:20] [PASSED] 34 VFs
[23:49:20] [PASSED] 35 VFs
[23:49:20] [PASSED] 36 VFs
[23:49:20] [PASSED] 37 VFs
[23:49:20] [PASSED] 38 VFs
[23:49:20] [PASSED] 39 VFs
[23:49:20] [PASSED] 40 VFs
[23:49:20] [PASSED] 41 VFs
[23:49:20] [PASSED] 42 VFs
[23:49:20] [PASSED] 43 VFs
[23:49:20] [PASSED] 44 VFs
[23:49:20] [PASSED] 45 VFs
[23:49:20] [PASSED] 46 VFs
[23:49:20] [PASSED] 47 VFs
[23:49:20] [PASSED] 48 VFs
[23:49:20] [PASSED] 49 VFs
[23:49:20] [PASSED] 50 VFs
[23:49:20] [PASSED] 51 VFs
[23:49:20] [PASSED] 52 VFs
[23:49:20] [PASSED] 53 VFs
[23:49:20] [PASSED] 54 VFs
[23:49:20] [PASSED] 55 VFs
[23:49:20] [PASSED] 56 VFs
[23:49:20] [PASSED] 57 VFs
[23:49:20] [PASSED] 58 VFs
[23:49:20] [PASSED] 59 VFs
[23:49:20] [PASSED] 60 VFs
[23:49:20] [PASSED] 61 VFs
[23:49:20] [PASSED] 62 VFs
[23:49:20] [PASSED] 63 VFs
[23:49:20] ================== [PASSED] fair_contexts ==================
[23:49:20] ===================== fair_doorbells  ======================
[23:49:20] [PASSED] 1 VF
[23:49:20] [PASSED] 2 VFs
[23:49:20] [PASSED] 3 VFs
[23:49:20] [PASSED] 4 VFs
[23:49:20] [PASSED] 5 VFs
[23:49:20] [PASSED] 6 VFs
[23:49:20] [PASSED] 7 VFs
[23:49:20] [PASSED] 8 VFs
[23:49:20] [PASSED] 9 VFs
[23:49:20] [PASSED] 10 VFs
[23:49:20] [PASSED] 11 VFs
[23:49:20] [PASSED] 12 VFs
[23:49:20] [PASSED] 13 VFs
[23:49:20] [PASSED] 14 VFs
[23:49:20] [PASSED] 15 VFs
[23:49:20] [PASSED] 16 VFs
[23:49:20] [PASSED] 17 VFs
[23:49:20] [PASSED] 18 VFs
[23:49:20] [PASSED] 19 VFs
[23:49:20] [PASSED] 20 VFs
[23:49:20] [PASSED] 21 VFs
[23:49:20] [PASSED] 22 VFs
[23:49:20] [PASSED] 23 VFs
[23:49:20] [PASSED] 24 VFs
[23:49:20] [PASSED] 25 VFs
[23:49:20] [PASSED] 26 VFs
[23:49:20] [PASSED] 27 VFs
[23:49:20] [PASSED] 28 VFs
[23:49:20] [PASSED] 29 VFs
[23:49:20] [PASSED] 30 VFs
[23:49:20] [PASSED] 31 VFs
[23:49:20] [PASSED] 32 VFs
[23:49:20] [PASSED] 33 VFs
[23:49:20] [PASSED] 34 VFs
[23:49:20] [PASSED] 35 VFs
[23:49:20] [PASSED] 36 VFs
[23:49:20] [PASSED] 37 VFs
[23:49:20] [PASSED] 38 VFs
[23:49:20] [PASSED] 39 VFs
[23:49:20] [PASSED] 40 VFs
[23:49:20] [PASSED] 41 VFs
[23:49:20] [PASSED] 42 VFs
[23:49:20] [PASSED] 43 VFs
[23:49:20] [PASSED] 44 VFs
[23:49:20] [PASSED] 45 VFs
[23:49:20] [PASSED] 46 VFs
[23:49:20] [PASSED] 47 VFs
[23:49:20] [PASSED] 48 VFs
[23:49:20] [PASSED] 49 VFs
[23:49:20] [PASSED] 50 VFs
[23:49:20] [PASSED] 51 VFs
[23:49:20] [PASSED] 52 VFs
[23:49:20] [PASSED] 53 VFs
[23:49:20] [PASSED] 54 VFs
[23:49:20] [PASSED] 55 VFs
[23:49:20] [PASSED] 56 VFs
[23:49:20] [PASSED] 57 VFs
[23:49:20] [PASSED] 58 VFs
[23:49:20] [PASSED] 59 VFs
[23:49:20] [PASSED] 60 VFs
[23:49:20] [PASSED] 61 VFs
[23:49:20] [PASSED] 62 VFs
[23:49:20] [PASSED] 63 VFs
[23:49:20] ================= [PASSED] fair_doorbells ==================
[23:49:20] ======================== fair_ggtt  ========================
[23:49:20] [PASSED] 1 VF
[23:49:20] [PASSED] 2 VFs
[23:49:20] [PASSED] 3 VFs
[23:49:20] [PASSED] 4 VFs
[23:49:20] [PASSED] 5 VFs
[23:49:20] [PASSED] 6 VFs
[23:49:20] [PASSED] 7 VFs
[23:49:20] [PASSED] 8 VFs
[23:49:20] [PASSED] 9 VFs
[23:49:20] [PASSED] 10 VFs
[23:49:20] [PASSED] 11 VFs
[23:49:20] [PASSED] 12 VFs
[23:49:20] [PASSED] 13 VFs
[23:49:20] [PASSED] 14 VFs
[23:49:20] [PASSED] 15 VFs
[23:49:20] [PASSED] 16 VFs
[23:49:20] [PASSED] 17 VFs
[23:49:20] [PASSED] 18 VFs
[23:49:20] [PASSED] 19 VFs
[23:49:20] [PASSED] 20 VFs
[23:49:20] [PASSED] 21 VFs
[23:49:20] [PASSED] 22 VFs
[23:49:20] [PASSED] 23 VFs
[23:49:20] [PASSED] 24 VFs
[23:49:20] [PASSED] 25 VFs
[23:49:20] [PASSED] 26 VFs
[23:49:20] [PASSED] 27 VFs
[23:49:20] [PASSED] 28 VFs
[23:49:20] [PASSED] 29 VFs
[23:49:20] [PASSED] 30 VFs
[23:49:20] [PASSED] 31 VFs
[23:49:20] [PASSED] 32 VFs
[23:49:20] [PASSED] 33 VFs
[23:49:20] [PASSED] 34 VFs
[23:49:20] [PASSED] 35 VFs
[23:49:20] [PASSED] 36 VFs
[23:49:20] [PASSED] 37 VFs
[23:49:20] [PASSED] 38 VFs
[23:49:20] [PASSED] 39 VFs
[23:49:20] [PASSED] 40 VFs
[23:49:20] [PASSED] 41 VFs
[23:49:20] [PASSED] 42 VFs
[23:49:20] [PASSED] 43 VFs
[23:49:20] [PASSED] 44 VFs
[23:49:20] [PASSED] 45 VFs
[23:49:20] [PASSED] 46 VFs
[23:49:20] [PASSED] 47 VFs
[23:49:20] [PASSED] 48 VFs
[23:49:20] [PASSED] 49 VFs
[23:49:20] [PASSED] 50 VFs
[23:49:20] [PASSED] 51 VFs
[23:49:20] [PASSED] 52 VFs
[23:49:20] [PASSED] 53 VFs
[23:49:20] [PASSED] 54 VFs
[23:49:20] [PASSED] 55 VFs
[23:49:20] [PASSED] 56 VFs
[23:49:20] [PASSED] 57 VFs
[23:49:20] [PASSED] 58 VFs
[23:49:20] [PASSED] 59 VFs
[23:49:20] [PASSED] 60 VFs
[23:49:20] [PASSED] 61 VFs
[23:49:20] [PASSED] 62 VFs
[23:49:20] [PASSED] 63 VFs
[23:49:20] ==================== [PASSED] fair_ggtt ====================
[23:49:20] ======================== fair_vram  ========================
[23:49:20] [PASSED] 1 VF
[23:49:20] [PASSED] 2 VFs
[23:49:20] [PASSED] 3 VFs
[23:49:20] [PASSED] 4 VFs
[23:49:20] [PASSED] 5 VFs
[23:49:20] [PASSED] 6 VFs
[23:49:20] [PASSED] 7 VFs
[23:49:20] [PASSED] 8 VFs
[23:49:20] [PASSED] 9 VFs
[23:49:20] [PASSED] 10 VFs
[23:49:20] [PASSED] 11 VFs
[23:49:20] [PASSED] 12 VFs
[23:49:20] [PASSED] 13 VFs
[23:49:20] [PASSED] 14 VFs
[23:49:20] [PASSED] 15 VFs
[23:49:20] [PASSED] 16 VFs
[23:49:20] [PASSED] 17 VFs
[23:49:20] [PASSED] 18 VFs
[23:49:20] [PASSED] 19 VFs
[23:49:20] [PASSED] 20 VFs
[23:49:20] [PASSED] 21 VFs
[23:49:20] [PASSED] 22 VFs
[23:49:20] [PASSED] 23 VFs
[23:49:20] [PASSED] 24 VFs
[23:49:20] [PASSED] 25 VFs
[23:49:20] [PASSED] 26 VFs
[23:49:20] [PASSED] 27 VFs
[23:49:20] [PASSED] 28 VFs
[23:49:20] [PASSED] 29 VFs
[23:49:20] [PASSED] 30 VFs
[23:49:20] [PASSED] 31 VFs
[23:49:20] [PASSED] 32 VFs
[23:49:20] [PASSED] 33 VFs
[23:49:20] [PASSED] 34 VFs
[23:49:20] [PASSED] 35 VFs
[23:49:20] [PASSED] 36 VFs
[23:49:20] [PASSED] 37 VFs
[23:49:20] [PASSED] 38 VFs
[23:49:20] [PASSED] 39 VFs
[23:49:20] [PASSED] 40 VFs
[23:49:20] [PASSED] 41 VFs
[23:49:20] [PASSED] 42 VFs
[23:49:20] [PASSED] 43 VFs
[23:49:20] [PASSED] 44 VFs
[23:49:20] [PASSED] 45 VFs
[23:49:20] [PASSED] 46 VFs
[23:49:20] [PASSED] 47 VFs
[23:49:20] [PASSED] 48 VFs
[23:49:20] [PASSED] 49 VFs
[23:49:20] [PASSED] 50 VFs
[23:49:20] [PASSED] 51 VFs
[23:49:20] [PASSED] 52 VFs
[23:49:20] [PASSED] 53 VFs
[23:49:20] [PASSED] 54 VFs
[23:49:20] [PASSED] 55 VFs
[23:49:20] [PASSED] 56 VFs
[23:49:20] [PASSED] 57 VFs
[23:49:20] [PASSED] 58 VFs
[23:49:20] [PASSED] 59 VFs
[23:49:20] [PASSED] 60 VFs
[23:49:20] [PASSED] 61 VFs
[23:49:20] [PASSED] 62 VFs
[23:49:20] [PASSED] 63 VFs
[23:49:20] ==================== [PASSED] fair_vram ====================
[23:49:20] ================== [PASSED] pf_gt_config ===================
[23:49:20] ===================== lmtt (1 subtest) =====================
[23:49:20] ======================== test_ops  =========================
[23:49:20] [PASSED] 2-level
[23:49:20] [PASSED] multi-level
[23:49:20] ==================== [PASSED] test_ops =====================
[23:49:20] ====================== [PASSED] lmtt =======================
[23:49:20] ================= sriov_packet (1 subtest) =================
[23:49:20] [PASSED] test_descriptor_init
[23:49:20] ================== [PASSED] sriov_packet ===================
[23:49:20] ================= pf_service (11 subtests) =================
[23:49:20] [PASSED] pf_negotiate_any
[23:49:20] [PASSED] pf_negotiate_base_match
[23:49:20] [PASSED] pf_negotiate_base_newer
[23:49:20] [PASSED] pf_negotiate_base_next
[23:49:20] [SKIPPED] pf_negotiate_base_older (no older minor)
[23:49:20] [PASSED] pf_negotiate_base_prev
[23:49:20] [PASSED] pf_negotiate_latest_match
[23:49:20] [PASSED] pf_negotiate_latest_newer
[23:49:20] [PASSED] pf_negotiate_latest_next
[23:49:20] [SKIPPED] pf_negotiate_latest_older (no older minor)
[23:49:20] [SKIPPED] pf_negotiate_latest_prev (no prev major)
[23:49:20] =================== [PASSED] pf_service ====================
[23:49:20] ================= xe_guc_g2g (2 subtests) ==================
[23:49:20] ============== xe_live_guc_g2g_kunit_default  ==============
[23:49:20] ========= [SKIPPED] xe_live_guc_g2g_kunit_default ==========
[23:49:20] ============== xe_live_guc_g2g_kunit_allmem  ===============
[23:49:20] ========== [SKIPPED] xe_live_guc_g2g_kunit_allmem ==========
[23:49:20] =================== [SKIPPED] xe_guc_g2g ===================
[23:49:20] =================== xe_mocs (2 subtests) ===================
[23:49:20] ================ xe_live_mocs_kernel_kunit  ================
[23:49:20] =========== [SKIPPED] xe_live_mocs_kernel_kunit ============
[23:49:20] ================ xe_live_mocs_reset_kunit  =================
[23:49:20] ============ [SKIPPED] xe_live_mocs_reset_kunit ============
[23:49:20] ==================== [SKIPPED] xe_mocs =====================
[23:49:20] ================= xe_migrate (2 subtests) ==================
[23:49:20] ================= xe_migrate_sanity_kunit  =================
[23:49:20] ============ [SKIPPED] xe_migrate_sanity_kunit =============
[23:49:20] ================== xe_validate_ccs_kunit  ==================
[23:49:20] ============= [SKIPPED] xe_validate_ccs_kunit ==============
[23:49:20] =================== [SKIPPED] xe_migrate ===================
[23:49:20] ================== xe_dma_buf (1 subtest) ==================
[23:49:20] ==================== xe_dma_buf_kunit  =====================
[23:49:20] ================ [SKIPPED] xe_dma_buf_kunit ================
[23:49:20] =================== [SKIPPED] xe_dma_buf ===================
[23:49:20] ================= xe_bo_shrink (1 subtest) =================
[23:49:20] =================== xe_bo_shrink_kunit  ====================
[23:49:20] =============== [SKIPPED] xe_bo_shrink_kunit ===============
[23:49:20] ================== [SKIPPED] xe_bo_shrink ==================
[23:49:20] ==================== xe_bo (2 subtests) ====================
[23:49:20] ================== xe_ccs_migrate_kunit  ===================
[23:49:20] ============== [SKIPPED] xe_ccs_migrate_kunit ==============
[23:49:20] ==================== xe_bo_evict_kunit  ====================
[23:49:20] =============== [SKIPPED] xe_bo_evict_kunit ================
[23:49:20] ===================== [SKIPPED] xe_bo ======================
[23:49:20] =================== xe_any (9 subtests) ====================
[23:49:20] [PASSED] test_to_xe
[23:49:20] [PASSED] test_to_dev
[23:49:20] [PASSED] test_to_pdev
[23:49:20] [PASSED] test_to_drm
[23:49:20] [PASSED] test_if_pdev
[23:49:20] [PASSED] test_if_xe
[23:49:20] [PASSED] test_if_tile
[23:49:20] [PASSED] test_if_gt
[23:49:20] [PASSED] test_to_id
[23:49:20] ===================== [PASSED] xe_any ======================
[23:49:20] ==================== args (13 subtests) ====================
[23:49:20] [PASSED] count_args_test
[23:49:20] [PASSED] call_args_example
[23:49:20] [PASSED] call_args_test
[23:49:20] [PASSED] drop_first_arg_example
[23:49:20] [PASSED] drop_first_arg_test
[23:49:20] [PASSED] first_arg_example
[23:49:20] [PASSED] first_arg_test
[23:49:20] [PASSED] last_arg_example
[23:49:20] [PASSED] last_arg_test
[23:49:20] [PASSED] pick_arg_example
[23:49:20] [PASSED] if_args_example
[23:49:20] [PASSED] if_args_test
[23:49:20] [PASSED] sep_comma_example
[23:49:20] ====================== [PASSED] args =======================
[23:49:20] =================== xe_pci (3 subtests) ====================
[23:49:20] ==================== check_graphics_ip  ====================
[23:49:20] [PASSED] 12.00 Xe_LP
[23:49:20] [PASSED] 12.10 Xe_LP+
[23:49:20] [PASSED] 12.55 Xe_HPG
[23:49:20] [PASSED] 12.60 Xe_HPC
[23:49:20] [PASSED] 12.70 Xe_LPG
[23:49:20] [PASSED] 12.71 Xe_LPG
[23:49:20] [PASSED] 12.74 Xe_LPG+
[23:49:20] [PASSED] 20.01 Xe2_HPG
[23:49:20] [PASSED] 20.02 Xe2_HPG
[23:49:20] [PASSED] 20.04 Xe2_LPG
[23:49:20] [PASSED] 30.00 Xe3_LPG
[23:49:20] [PASSED] 30.01 Xe3_LPG
[23:49:20] [PASSED] 30.03 Xe3_LPG
[23:49:20] [PASSED] 30.04 Xe3_LPG
[23:49:20] [PASSED] 30.05 Xe3_LPG
[23:49:20] [PASSED] 35.10 Xe3p_LPG
[23:49:20] [PASSED] 35.11 Xe3p_XPC
[23:49:20] ================ [PASSED] check_graphics_ip ================
[23:49:20] ===================== check_media_ip  ======================
[23:49:20] [PASSED] 12.00 Xe_M
[23:49:20] [PASSED] 12.55 Xe_HPM
[23:49:20] [PASSED] 13.00 Xe_LPM+
[23:49:20] [PASSED] 13.01 Xe2_HPM
[23:49:20] [PASSED] 20.00 Xe2_LPM
[23:49:20] [PASSED] 30.00 Xe3_LPM
[23:49:20] [PASSED] 30.02 Xe3_LPM
[23:49:20] [PASSED] 35.00 Xe3p_LPM
[23:49:20] [PASSED] 35.03 Xe3p_HPM
[23:49:20] ================= [PASSED] check_media_ip ==================
[23:49:20] =================== check_platform_desc  ===================
[23:49:20] [PASSED] 0x9A60 (TIGERLAKE)
[23:49:20] [PASSED] 0x9A68 (TIGERLAKE)
[23:49:20] [PASSED] 0x9A70 (TIGERLAKE)
[23:49:20] [PASSED] 0x9A40 (TIGERLAKE)
[23:49:20] [PASSED] 0x9A49 (TIGERLAKE)
[23:49:20] [PASSED] 0x9A59 (TIGERLAKE)
[23:49:20] [PASSED] 0x9A78 (TIGERLAKE)
[23:49:20] [PASSED] 0x9AC0 (TIGERLAKE)
[23:49:20] [PASSED] 0x9AC9 (TIGERLAKE)
[23:49:20] [PASSED] 0x9AD9 (TIGERLAKE)
[23:49:20] [PASSED] 0x9AF8 (TIGERLAKE)
[23:49:20] [PASSED] 0x4C80 (ROCKETLAKE)
[23:49:20] [PASSED] 0x4C8A (ROCKETLAKE)
[23:49:20] [PASSED] 0x4C8B (ROCKETLAKE)
[23:49:20] [PASSED] 0x4C8C (ROCKETLAKE)
[23:49:20] [PASSED] 0x4C90 (ROCKETLAKE)
[23:49:20] [PASSED] 0x4C9A (ROCKETLAKE)
[23:49:20] [PASSED] 0x4680 (ALDERLAKE_S)
[23:49:20] [PASSED] 0x4682 (ALDERLAKE_S)
[23:49:20] [PASSED] 0x4688 (ALDERLAKE_S)
[23:49:20] [PASSED] 0x468A (ALDERLAKE_S)
[23:49:20] [PASSED] 0x468B (ALDERLAKE_S)
[23:49:20] [PASSED] 0x4690 (ALDERLAKE_S)
[23:49:20] [PASSED] 0x4692 (ALDERLAKE_S)
[23:49:20] [PASSED] 0x4693 (ALDERLAKE_S)
[23:49:20] [PASSED] 0x46A0 (ALDERLAKE_P)
[23:49:20] [PASSED] 0x46A1 (ALDERLAKE_P)
[23:49:20] [PASSED] 0x46A2 (ALDERLAKE_P)
[23:49:20] [PASSED] 0x46A3 (ALDERLAKE_P)
[23:49:20] [PASSED] 0x46A6 (ALDERLAKE_P)
[23:49:20] [PASSED] 0x46A8 (ALDERLAKE_P)
[23:49:20] [PASSED] 0x46AA (ALDERLAKE_P)
[23:49:20] [PASSED] 0x462A (ALDERLAKE_P)
[23:49:20] [PASSED] 0x4626 (ALDERLAKE_P)
[23:49:20] [PASSED] 0x4628 (ALDERLAKE_P)
[23:49:20] [PASSED] 0x46B0 (ALDERLAKE_P)
[23:49:20] [PASSED] 0x46B1 (ALDERLAKE_P)
[23:49:20] [PASSED] 0x46B2 (ALDERLAKE_P)
[23:49:20] [PASSED] 0x46B3 (ALDERLAKE_P)
[23:49:20] [PASSED] 0x46C0 (ALDERLAKE_P)
[23:49:20] [PASSED] 0x46C1 (ALDERLAKE_P)
[23:49:20] [PASSED] 0x46C2 (ALDERLAKE_P)
[23:49:20] [PASSED] 0x46C3 (ALDERLAKE_P)
[23:49:20] [PASSED] 0x46D0 (ALDERLAKE_N)
[23:49:20] [PASSED] 0x46D1 (ALDERLAKE_N)
[23:49:20] [PASSED] 0x46D2 (ALDERLAKE_N)
[23:49:20] [PASSED] 0x46D3 (ALDERLAKE_N)
[23:49:20] [PASSED] 0x46D4 (ALDERLAKE_N)
[23:49:20] [PASSED] 0xA721 (ALDERLAKE_P)
[23:49:20] [PASSED] 0xA7A1 (ALDERLAKE_P)
[23:49:20] [PASSED] 0xA7A9 (ALDERLAKE_P)
[23:49:20] [PASSED] 0xA7AC (ALDERLAKE_P)
[23:49:20] [PASSED] 0xA7AD (ALDERLAKE_P)
[23:49:20] [PASSED] 0xA720 (ALDERLAKE_P)
[23:49:20] [PASSED] 0xA7A0 (ALDERLAKE_P)
[23:49:20] [PASSED] 0xA7A8 (ALDERLAKE_P)
[23:49:20] [PASSED] 0xA7AA (ALDERLAKE_P)
[23:49:20] [PASSED] 0xA7AB (ALDERLAKE_P)
[23:49:20] [PASSED] 0xA780 (ALDERLAKE_S)
[23:49:20] [PASSED] 0xA781 (ALDERLAKE_S)
[23:49:20] [PASSED] 0xA782 (ALDERLAKE_S)
[23:49:20] [PASSED] 0xA783 (ALDERLAKE_S)
[23:49:20] [PASSED] 0xA788 (ALDERLAKE_S)
[23:49:20] [PASSED] 0xA789 (ALDERLAKE_S)
[23:49:20] [PASSED] 0xA78A (ALDERLAKE_S)
[23:49:20] [PASSED] 0xA78B (ALDERLAKE_S)
[23:49:20] [PASSED] 0x4905 (DG1)
[23:49:20] [PASSED] 0x4906 (DG1)
[23:49:20] [PASSED] 0x4907 (DG1)
[23:49:20] [PASSED] 0x4908 (DG1)
[23:49:20] [PASSED] 0x4909 (DG1)
[23:49:20] [PASSED] 0x56C0 (DG2)
[23:49:20] [PASSED] 0x56C2 (DG2)
[23:49:20] [PASSED] 0x56C1 (DG2)
[23:49:20] [PASSED] 0x7D51 (METEORLAKE)
[23:49:20] [PASSED] 0x7DD1 (METEORLAKE)
[23:49:20] [PASSED] 0x7D41 (METEORLAKE)
[23:49:20] [PASSED] 0x7D67 (METEORLAKE)
[23:49:20] [PASSED] 0xB640 (METEORLAKE)
[23:49:20] [PASSED] 0x56A0 (DG2)
[23:49:20] [PASSED] 0x56A1 (DG2)
[23:49:20] [PASSED] 0x56A2 (DG2)
[23:49:20] [PASSED] 0x56BE (DG2)
[23:49:20] [PASSED] 0x56BF (DG2)
[23:49:20] [PASSED] 0x5690 (DG2)
[23:49:20] [PASSED] 0x5691 (DG2)
[23:49:20] [PASSED] 0x5692 (DG2)
[23:49:20] [PASSED] 0x56A5 (DG2)
[23:49:20] [PASSED] 0x56A6 (DG2)
[23:49:20] [PASSED] 0x56B0 (DG2)
[23:49:20] [PASSED] 0x56B1 (DG2)
[23:49:20] [PASSED] 0x56BA (DG2)
[23:49:20] [PASSED] 0x56BB (DG2)
[23:49:20] [PASSED] 0x56BC (DG2)
[23:49:20] [PASSED] 0x56BD (DG2)
[23:49:20] [PASSED] 0x5693 (DG2)
[23:49:20] [PASSED] 0x5694 (DG2)
[23:49:20] [PASSED] 0x5695 (DG2)
[23:49:20] [PASSED] 0x56A3 (DG2)
[23:49:20] [PASSED] 0x56A4 (DG2)
[23:49:20] [PASSED] 0x56B2 (DG2)
[23:49:20] [PASSED] 0x56B3 (DG2)
[23:49:20] [PASSED] 0x5696 (DG2)
[23:49:20] [PASSED] 0x5697 (DG2)
[23:49:20] [PASSED] 0xB69 (PVC)
[23:49:20] [PASSED] 0xB6E (PVC)
[23:49:20] [PASSED] 0xBD4 (PVC)
[23:49:20] [PASSED] 0xBD5 (PVC)
[23:49:20] [PASSED] 0xBD6 (PVC)
[23:49:20] [PASSED] 0xBD7 (PVC)
[23:49:20] [PASSED] 0xBD8 (PVC)
[23:49:20] [PASSED] 0xBD9 (PVC)
[23:49:20] [PASSED] 0xBDA (PVC)
[23:49:20] [PASSED] 0xBDB (PVC)
[23:49:20] [PASSED] 0xBE0 (PVC)
[23:49:20] [PASSED] 0xBE1 (PVC)
[23:49:20] [PASSED] 0xBE5 (PVC)
[23:49:20] [PASSED] 0x7D40 (METEORLAKE)
[23:49:20] [PASSED] 0x7D45 (METEORLAKE)
[23:49:20] [PASSED] 0x7D55 (METEORLAKE)
[23:49:20] [PASSED] 0x7D60 (METEORLAKE)
[23:49:20] [PASSED] 0x7DD5 (METEORLAKE)
[23:49:20] [PASSED] 0x6420 (LUNARLAKE)
[23:49:20] [PASSED] 0x64A0 (LUNARLAKE)
[23:49:20] [PASSED] 0x64B0 (LUNARLAKE)
[23:49:20] [PASSED] 0xE202 (BATTLEMAGE)
[23:49:20] [PASSED] 0xE209 (BATTLEMAGE)
[23:49:20] [PASSED] 0xE20B (BATTLEMAGE)
[23:49:20] [PASSED] 0xE20C (BATTLEMAGE)
[23:49:20] [PASSED] 0xE20D (BATTLEMAGE)
[23:49:20] [PASSED] 0xE210 (BATTLEMAGE)
[23:49:20] [PASSED] 0xE211 (BATTLEMAGE)
[23:49:20] [PASSED] 0xE212 (BATTLEMAGE)
[23:49:20] [PASSED] 0xE216 (BATTLEMAGE)
[23:49:20] [PASSED] 0xE220 (BATTLEMAGE)
[23:49:20] [PASSED] 0xE221 (BATTLEMAGE)
[23:49:20] [PASSED] 0xE222 (BATTLEMAGE)
[23:49:20] [PASSED] 0xE223 (BATTLEMAGE)
[23:49:20] [PASSED] 0xB080 (PANTHERLAKE)
[23:49:20] [PASSED] 0xB081 (PANTHERLAKE)
[23:49:20] [PASSED] 0xB082 (PANTHERLAKE)
[23:49:20] [PASSED] 0xB083 (PANTHERLAKE)
[23:49:20] [PASSED] 0xB084 (PANTHERLAKE)
[23:49:20] [PASSED] 0xB085 (PANTHERLAKE)
[23:49:20] [PASSED] 0xB086 (PANTHERLAKE)
[23:49:20] [PASSED] 0xB087 (PANTHERLAKE)
[23:49:20] [PASSED] 0xB08F (PANTHERLAKE)
[23:49:20] [PASSED] 0xB090 (PANTHERLAKE)
[23:49:20] [PASSED] 0xB0A0 (PANTHERLAKE)
[23:49:20] [PASSED] 0xB0B0 (PANTHERLAKE)
[23:49:20] [PASSED] 0xFD80 (PANTHERLAKE)
[23:49:20] [PASSED] 0xFD81 (PANTHERLAKE)
[23:49:20] [PASSED] 0xD740 (NOVALAKE_S)
[23:49:20] [PASSED] 0xD741 (NOVALAKE_S)
[23:49:20] [PASSED] 0xD742 (NOVALAKE_S)
[23:49:20] [PASSED] 0xD743 (NOVALAKE_S)
[23:49:20] [PASSED] 0xD745 (NOVALAKE_S)
[23:49:20] [PASSED] 0xD74A (NOVALAKE_S)
[23:49:20] [PASSED] 0xD74B (NOVALAKE_S)
[23:49:20] [PASSED] 0x674C (CRESCENTISLAND)
[23:49:20] [PASSED] 0x674D (CRESCENTISLAND)
[23:49:20] [PASSED] 0x674E (CRESCENTISLAND)
[23:49:20] [PASSED] 0x674F (CRESCENTISLAND)
[23:49:20] [PASSED] 0x6750 (CRESCENTISLAND)
[23:49:20] [PASSED] 0xD750 (NOVALAKE_P)
[23:49:20] [PASSED] 0xD751 (NOVALAKE_P)
[23:49:20] [PASSED] 0xD752 (NOVALAKE_P)
[23:49:20] [PASSED] 0xD753 (NOVALAKE_P)
[23:49:20] [PASSED] 0xD754 (NOVALAKE_P)
[23:49:20] [PASSED] 0xD755 (NOVALAKE_P)
[23:49:20] [PASSED] 0xD756 (NOVALAKE_P)
[23:49:20] [PASSED] 0xD757 (NOVALAKE_P)
[23:49:20] [PASSED] 0xD75F (NOVALAKE_P)
[23:49:20] =============== [PASSED] check_platform_desc ===============
[23:49:20] ===================== [PASSED] xe_pci ======================
[23:49:20] ============= xe_rtp_tables_test (5 subtests) ==============
[23:49:20] ================== xe_rtp_table_gt_test  ===================
[23:49:20] [PASSED] gt_was/14011060649
[23:49:20] [PASSED] gt_was/14011059788
[23:49:20] [PASSED] gt_was/14015795083
[23:49:20] [PASSED] gt_was/16021867713
[23:49:20] [PASSED] gt_was/14019449301
[23:49:20] [PASSED] gt_was/16028005424
[23:49:20] [PASSED] gt_was/14026578760
[23:49:20] [PASSED] gt_was/1409420604
[23:49:20] [PASSED] gt_was/1408615072
[23:49:20] [PASSED] gt_was/22010523718
[23:49:20] [PASSED] gt_was/14011006942
[23:49:20] [PASSED] gt_was/14014830051
[23:49:20] [PASSED] gt_was/18018781329
[23:49:20] [PASSED] gt_was/1509235366
[23:49:20] [PASSED] gt_was/18018781329
[23:49:20] [PASSED] gt_was/16016694945
[23:49:20] [PASSED] gt_was/14018575942
[23:49:20] [PASSED] gt_was/22016670082
[23:49:20] [PASSED] gt_was/22016670082
[23:49:20] [PASSED] gt_was/14017421178
[23:49:20] [PASSED] gt_was/16025250150
[23:49:20] [PASSED] gt_was/14021871409
[23:49:20] [PASSED] gt_was/16021865536
[23:49:20] [PASSED] gt_was/14021486841
[23:49:20] [PASSED] gt_was/14025160223
[23:49:20] [PASSED] gt_was/14026144927, 16029437861, 14026127056
[23:49:20] [PASSED] gt_was/14025635424
[23:49:20] [PASSED] gt_was/16028005424
[23:49:20] ============== [PASSED] xe_rtp_table_gt_test ===============
[23:49:20] ================== xe_rtp_table_gt_test  ===================
[23:49:20] [PASSED] gt_tunings/Tuning: Blend Fill Caching Optimization Disable
[23:49:20] [PASSED] gt_tunings/Tuning: 32B Access Enable
[23:49:20] [PASSED] gt_tunings/Tuning: L3 cache
[23:49:20] [PASSED] gt_tunings/Tuning: L3 cache - media
[23:49:20] [PASSED] gt_tunings/Tuning: Compression Overfetch
[23:49:20] [PASSED] gt_tunings/Tuning: Compression Overfetch - media
[23:49:20] [PASSED] gt_tunings/Tuning: Enable compressible partial write overfetch in L3
[23:49:20] [PASSED] gt_tunings/Tuning: Enable compressible partial write overfetch in L3 - media
[23:49:20] [PASSED] gt_tunings/Tuning: L2 Overfetch Compressible Only
[23:49:20] [PASSED] gt_tunings/Tuning: L2 Overfetch Compressible Only - media
[23:49:20] [PASSED] gt_tunings/Tuning: Stateless compression control
[23:49:20] [PASSED] gt_tunings/Tuning: Stateless compression control - media
[23:49:20] [PASSED] gt_tunings/Tuning: L3 RW flush all Cache
[23:49:20] [PASSED] gt_tunings/Tuning: L3 RW flush all cache - media
[23:49:20] [PASSED] gt_tunings/Tuning: Set STLB Bank Hash Mode to 4KB
[23:49:20] ============== [PASSED] xe_rtp_table_gt_test ===============
[23:49:20] ================== xe_rtp_table_oob_test  ==================
[23:49:20] [PASSED] oob_was/1607983814
[23:49:20] [PASSED] oob_was/16010904313
[23:49:20] [PASSED] oob_was/18022495364
[23:49:20] [PASSED] oob_was/22012773006
[23:49:20] [PASSED] oob_was/14014475959
[23:49:20] [PASSED] oob_was/22011391025
[23:49:20] [PASSED] oob_was/22012727170
[23:49:20] [PASSED] oob_was/22012727685
[23:49:20] [PASSED] oob_was/22016596838
[23:49:20] [PASSED] oob_was/18020744125
[23:49:20] [PASSED] oob_was/1409600907
[23:49:20] [PASSED] oob_was/22014953428
[23:49:20] [PASSED] oob_was/16017236439
[23:49:20] [PASSED] oob_was/14019821291
[23:49:20] [PASSED] oob_was/14015076503
[23:49:20] [PASSED] oob_was/14018913170
[23:49:20] [PASSED] oob_was/14018094691
[23:49:20] [PASSED] oob_was/18024947630
[23:49:20] [PASSED] oob_was/16022287689
[23:49:20] [PASSED] oob_was/13011645652
[23:49:20] [PASSED] oob_was/14022293748
[23:49:20] [PASSED] oob_was/22019794406
[23:49:20] [PASSED] oob_was/22019338487
[23:49:20] [PASSED] oob_was/16023588340
[23:49:20] [PASSED] oob_was/14019789679
[23:49:20] [PASSED] oob_was/14022866841
[23:49:20] [PASSED] oob_was/16021333562
[23:49:20] [PASSED] oob_was/14016712196
[23:49:20] [PASSED] oob_was/14015568240
[23:49:20] [PASSED] oob_was/18013179988
[23:49:20] [PASSED] oob_was/1508761755
[23:49:20] [PASSED] oob_was/16023105232
[23:49:20] [PASSED] oob_was/16026508708
[23:49:20] [PASSED] oob_was/14020001231
[23:49:20] [PASSED] oob_was/16023683509
[23:49:20] [PASSED] oob_was/14025515070
[23:49:20] [PASSED] oob_was/15015404425_disable
[23:49:20] [PASSED] oob_was/16026007364
[23:49:20] [PASSED] oob_was/14020316580
[23:49:20] [PASSED] oob_was/14025883347
[23:49:20] [PASSED] oob_was/16029380221
[23:49:20] [PASSED] oob_was/22022079272
[23:49:20] [PASSED] oob_was/16029897822
[23:49:20] [PASSED] oob_was/14027054324
[23:49:20] ============== [PASSED] xe_rtp_table_oob_test ==============
[23:49:20] ================ xe_rtp_table_dev_oob_test  ================
[23:49:20] [PASSED] device_oob_was/22010954014
[23:49:20] [PASSED] device_oob_was/15015404425
[23:49:20] [PASSED] device_oob_was/22019338487_display
[23:49:20] [PASSED] device_oob_was/14022085890
[23:49:20] [PASSED] device_oob_was/14026539277
[23:49:20] [PASSED] device_oob_was/14026633728
[23:49:20] [PASSED] device_oob_was/14026746987
[23:49:20] [PASSED] device_oob_was/14026779378
[23:49:20] ============ [PASSED] xe_rtp_table_dev_oob_test ============
[23:49:20] ========== xe_rtp_table_missing_upper_bound_test  ==========
[23:49:20] [PASSED] register_whitelist/WaAllowPMDepthAndInvocationCountAccessFromUMD, 1408556865
[23:49:20] [PASSED] register_whitelist/1508744258, 14012131227, 1808121037
[23:49:20] [PASSED] register_whitelist/1806527549
[23:49:20] [PASSED] register_whitelist/allow_read_ctx_timestamp
[23:49:20] [PASSED] register_whitelist/allow_read_queue_timestamp
[23:49:20] [PASSED] register_whitelist/16014440446
[23:49:20] [PASSED] register_whitelist/16017236439
[23:49:20] [PASSED] register_whitelist/16020183090
[23:49:20] [PASSED] register_whitelist/14024997852
[23:49:20] [PASSED] register_whitelist/14024997852
[23:49:20] ====== [PASSED] xe_rtp_table_missing_upper_bound_test ======
[23:49:20] =============== [PASSED] xe_rtp_tables_test ================
[23:49:20] =================== xe_rtp (3 subtests) ====================
[23:49:20] =================== xe_rtp_rules_tests  ====================
[23:49:20] [PASSED] no
[23:49:20] [PASSED] yes
[23:49:20] [PASSED] no-and-no
[23:49:20] [PASSED] no-and-yes
[23:49:20] [PASSED] yes-and-no
[23:49:20] [PASSED] yes-and-yes
[23:49:20] [PASSED] no-or-no
[23:49:20] [PASSED] no-or-yes
[23:49:20] [PASSED] yes-or-no
[23:49:20] [PASSED] yes-or-yes
[23:49:20] [PASSED] no-yes-or-yes-no
[23:49:20] [PASSED] no-yes-or-yes-yes
[23:49:20] [PASSED] yes-yes-or-no-yes
[23:49:20] [PASSED] yes-yes-or-yes-yes
[23:49:20] [PASSED] no-no-or-yes-or-no
[23:49:20] [PASSED] or
[23:49:20] [PASSED] or-yes
[23:49:20] [PASSED] or-no
[23:49:20] [PASSED] yes-or
[23:49:20] [PASSED] no-or
[23:49:20] [PASSED] no-or-or-yes
[23:49:20] [PASSED] yes-or-or-no
[23:49:20] [PASSED] no-or-or-no
[23:49:20] [PASSED] missing-context-engine-class
[23:49:20] [PASSED] missing-context-engine-class-or-yes
[23:49:20] [PASSED] missing-context-engine-class-or-or-yes
[23:49:20] =============== [PASSED] xe_rtp_rules_tests ================
[23:49:20] =============== xe_rtp_process_to_sr_tests  ================
[23:49:20] [PASSED] coalesce-same-reg
[23:49:20] [PASSED] coalesce-same-reg-literal-and-func
[23:49:20] [PASSED] no-match-no-add
[23:49:20] [PASSED] two-regs-two-entries
[23:49:20] [PASSED] clr-one-set-other
[23:49:20] [PASSED] set-field
[23:49:20] [PASSED] conflict-duplicate
[23:49:20] [PASSED] conflict-not-disjoint
[23:49:20] [PASSED] conflict-not-disjoint-literal-and-func
[23:49:20] [PASSED] conflict-reg-type
[23:49:20] [PASSED] bad-mcr-reg-forced-to-regular
[23:49:20] [PASSED] bad-regular-reg-forced-to-mcr
[23:49:20] =========== [PASSED] xe_rtp_process_to_sr_tests ============
[23:49:20] ================== xe_rtp_process_tests  ===================
[23:49:20] [PASSED] active1
[23:49:20] [PASSED] active2
[23:49:20] [PASSED] active-inactive
[23:49:20] [PASSED] inactive-active
[23:49:20] [PASSED] inactive-active-inactive
[23:49:20] [PASSED] inactive-inactive-inactive
[23:49:20] ============== [PASSED] xe_rtp_process_tests ===============
[23:49:20] ===================== [PASSED] xe_rtp ======================
[23:49:20] ==================== xe_wa (1 subtest) =====================
[23:49:20] ======================== xe_wa_gt  =========================
[23:49:20] [PASSED] TIGERLAKE B0
[23:49:20] [PASSED] DG1 A0
[23:49:20] [PASSED] DG1 B0
[23:49:20] [PASSED] ALDERLAKE_S A0
[23:49:20] [PASSED] ALDERLAKE_S B0
[23:49:20] [PASSED] ALDERLAKE_S C0
[23:49:20] [PASSED] ALDERLAKE_S D0
[23:49:20] [PASSED] ALDERLAKE_P A0
[23:49:20] [PASSED] ALDERLAKE_P B0
[23:49:20] [PASSED] ALDERLAKE_P C0
[23:49:20] [PASSED] ALDERLAKE_S RPLS D0
[23:49:20] [PASSED] ALDERLAKE_P RPLU E0
[23:49:20] [PASSED] DG2 G10 C0
[23:49:20] [PASSED] DG2 G11 B1
[23:49:20] [PASSED] DG2 G12 A1
[23:49:20] [PASSED] METEORLAKE 12.70(Xe_LPG) A0 13.00(Xe_LPM+) A0
[23:49:20] [PASSED] METEORLAKE 12.71(Xe_LPG) A0 13.00(Xe_LPM+) A0
[23:49:20] [PASSED] METEORLAKE 12.74(Xe_LPG+) A0 13.00(Xe_LPM+) A0
[23:49:20] [PASSED] LUNARLAKE 20.04(Xe2_LPG) A0 20.00(Xe2_LPM) A0
[23:49:20] [PASSED] LUNARLAKE 20.04(Xe2_LPG) B0 20.00(Xe2_LPM) A0
[23:49:20] [PASSED] BATTLEMAGE 20.01(Xe2_HPG) A0 13.01(Xe2_HPM) A1
[23:49:20] [PASSED] PANTHERLAKE 30.00(Xe3_LPG) A0 30.00(Xe3_LPM) A0
[23:49:20] ==================== [PASSED] xe_wa_gt =====================
[23:49:20] ====================== [PASSED] xe_wa ======================
[23:49:20] ============================================================
[23:49:20] Testing complete. Ran 789 tests: passed: 761, skipped: 28
[23:49:20] Elapsed time: 36.953s total, 4.347s configuring, 31.889s building, 0.678s running

+ /kernel/tools/testing/kunit/kunit.py run --kunitconfig /kernel/drivers/gpu/drm/tests/.kunitconfig
[23:49:20] Configuring KUnit Kernel ...
Regenerating .config ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
[23:49:22] Building KUnit Kernel ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
Building with:
$ make all compile_commands.json scripts_gdb ARCH=um O=.kunit --jobs=48
[23:49:47] Starting KUnit Kernel (1/1)...
[23:49:47] ============================================================
Running tests with:
$ .kunit/linux kunit.enable=1 mem=1G console=tty kunit_shutdown=halt
[23:49:47] ============ drm_test_pick_cmdline (2 subtests) ============
[23:49:47] [PASSED] drm_test_pick_cmdline_res_1920_1080_60
[23:49:47] =============== drm_test_pick_cmdline_named  ===============
[23:49:47] [PASSED] NTSC
[23:49:47] [PASSED] NTSC-J
[23:49:47] [PASSED] PAL
[23:49:47] [PASSED] PAL-M
[23:49:47] =========== [PASSED] drm_test_pick_cmdline_named ===========
[23:49:47] ============== [PASSED] drm_test_pick_cmdline ==============
[23:49:47] == drm_test_atomic_get_connector_for_encoder (1 subtest) ===
[23:49:47] [PASSED] drm_test_drm_atomic_get_connector_for_encoder
[23:49:47] ==== [PASSED] drm_test_atomic_get_connector_for_encoder ====
[23:49:47] =========== drm_validate_clone_mode (2 subtests) ===========
[23:49:47] ============== drm_test_check_in_clone_mode  ===============
[23:49:47] [PASSED] in_clone_mode
[23:49:47] [PASSED] not_in_clone_mode
[23:49:47] ========== [PASSED] drm_test_check_in_clone_mode ===========
[23:49:47] =============== drm_test_check_valid_clones  ===============
[23:49:47] [PASSED] not_in_clone_mode
[23:49:47] [PASSED] valid_clone
[23:49:47] [PASSED] invalid_clone
[23:49:47] =========== [PASSED] drm_test_check_valid_clones ===========
[23:49:47] ============= [PASSED] drm_validate_clone_mode =============
[23:49:47] ============= drm_validate_modeset (1 subtest) =============
[23:49:47] [PASSED] drm_test_check_connector_changed_modeset
[23:49:47] ============== [PASSED] drm_validate_modeset ===============
[23:49:47] ====== drm_test_bridge_get_current_state (1 subtest) =======
[23:49:47] [PASSED] drm_test_drm_bridge_get_current_state_atomic
[23:49:47] ======== [PASSED] drm_test_bridge_get_current_state ========
[23:49:47] ====== drm_test_bridge_helper_reset_crtc (3 subtests) ======
[23:49:47] [PASSED] drm_test_drm_bridge_helper_reset_crtc_atomic
[23:49:47] [PASSED] drm_test_drm_bridge_helper_reset_crtc_atomic_disabled
[23:49:47] [PASSED] drm_test_drm_bridge_helper_hdmi_output_bus_fmts
[23:49:47] ======== [PASSED] drm_test_bridge_helper_reset_crtc ========
[23:49:47] ============== drm_bridge_alloc (2 subtests) ===============
[23:49:47] [PASSED] drm_test_drm_bridge_alloc_basic
[23:49:47] [PASSED] drm_test_drm_bridge_alloc_get_put
[23:49:47] ================ [PASSED] drm_bridge_alloc =================
[23:49:47] ============= drm_bridge_bus_fmt (5 subtests) ==============
[23:49:47] [PASSED] drm_test_bridge_rgb_yuv_rgb
[23:49:47] [PASSED] drm_test_bridge_must_convert_to_yuv444
[23:49:47] [PASSED] drm_test_bridge_hdmi_auto_rgb
[23:49:47] [PASSED] drm_test_bridge_auto_first
[23:49:47] [PASSED] drm_test_bridge_rgb_yuv_no_path
[23:49:47] =============== [PASSED] drm_bridge_bus_fmt ================
[23:49:47] ============= drm_cmdline_parser (40 subtests) =============
[23:49:47] [PASSED] drm_test_cmdline_force_d_only
[23:49:47] [PASSED] drm_test_cmdline_force_D_only_dvi
[23:49:47] [PASSED] drm_test_cmdline_force_D_only_hdmi
[23:49:47] [PASSED] drm_test_cmdline_force_D_only_not_digital
[23:49:47] [PASSED] drm_test_cmdline_force_e_only
[23:49:47] [PASSED] drm_test_cmdline_res
[23:49:47] [PASSED] drm_test_cmdline_res_vesa
[23:49:47] [PASSED] drm_test_cmdline_res_vesa_rblank
[23:49:47] [PASSED] drm_test_cmdline_res_rblank
[23:49:47] [PASSED] drm_test_cmdline_res_bpp
[23:49:47] [PASSED] drm_test_cmdline_res_refresh
[23:49:47] [PASSED] drm_test_cmdline_res_bpp_refresh
[23:49:47] [PASSED] drm_test_cmdline_res_bpp_refresh_interlaced
[23:49:47] [PASSED] drm_test_cmdline_res_bpp_refresh_margins
[23:49:47] [PASSED] drm_test_cmdline_res_bpp_refresh_force_off
[23:49:47] [PASSED] drm_test_cmdline_res_bpp_refresh_force_on
[23:49:47] [PASSED] drm_test_cmdline_res_bpp_refresh_force_on_analog
[23:49:47] [PASSED] drm_test_cmdline_res_bpp_refresh_force_on_digital
[23:49:47] [PASSED] drm_test_cmdline_res_bpp_refresh_interlaced_margins_force_on
[23:49:47] [PASSED] drm_test_cmdline_res_margins_force_on
[23:49:47] [PASSED] drm_test_cmdline_res_vesa_margins
[23:49:47] [PASSED] drm_test_cmdline_name
[23:49:47] [PASSED] drm_test_cmdline_name_bpp
[23:49:47] [PASSED] drm_test_cmdline_name_option
[23:49:47] [PASSED] drm_test_cmdline_name_bpp_option
[23:49:47] [PASSED] drm_test_cmdline_rotate_0
[23:49:47] [PASSED] drm_test_cmdline_rotate_90
[23:49:47] [PASSED] drm_test_cmdline_rotate_180
[23:49:47] [PASSED] drm_test_cmdline_rotate_270
[23:49:47] [PASSED] drm_test_cmdline_hmirror
[23:49:47] [PASSED] drm_test_cmdline_vmirror
[23:49:47] [PASSED] drm_test_cmdline_margin_options
[23:49:47] [PASSED] drm_test_cmdline_multiple_options
[23:49:47] [PASSED] drm_test_cmdline_bpp_extra_and_option
[23:49:47] [PASSED] drm_test_cmdline_extra_and_option
[23:49:47] [PASSED] drm_test_cmdline_freestanding_options
[23:49:47] [PASSED] drm_test_cmdline_freestanding_force_e_and_options
[23:49:47] [PASSED] drm_test_cmdline_panel_orientation
[23:49:47] ================ drm_test_cmdline_invalid  =================
[23:49:47] [PASSED] margin_only
[23:49:47] [PASSED] interlace_only
[23:49:47] [PASSED] res_missing_x
[23:49:47] [PASSED] res_missing_y
[23:49:47] [PASSED] res_bad_y
[23:49:47] [PASSED] res_missing_y_bpp
[23:49:47] [PASSED] res_bad_bpp
[23:49:47] [PASSED] res_bad_refresh
[23:49:47] [PASSED] res_bpp_refresh_force_on_off
[23:49:47] [PASSED] res_invalid_mode
[23:49:47] [PASSED] res_bpp_wrong_place_mode
[23:49:47] [PASSED] name_bpp_refresh
[23:49:47] [PASSED] name_refresh
[23:49:47] [PASSED] name_refresh_wrong_mode
[23:49:47] [PASSED] name_refresh_invalid_mode
[23:49:47] [PASSED] rotate_multiple
[23:49:47] [PASSED] rotate_invalid_val
[23:49:47] [PASSED] rotate_truncated
[23:49:47] [PASSED] invalid_option
[23:49:47] [PASSED] invalid_tv_option
[23:49:47] [PASSED] truncated_tv_option
[23:49:47] ============ [PASSED] drm_test_cmdline_invalid =============
[23:49:47] =============== drm_test_cmdline_tv_options  ===============
[23:49:47] [PASSED] NTSC
[23:49:47] [PASSED] NTSC_443
[23:49:47] [PASSED] NTSC_J
[23:49:47] [PASSED] PAL
[23:49:47] [PASSED] PAL_M
[23:49:47] [PASSED] PAL_N
[23:49:47] [PASSED] SECAM
[23:49:47] [PASSED] MONO_525
[23:49:47] [PASSED] MONO_625
[23:49:47] =========== [PASSED] drm_test_cmdline_tv_options ===========
[23:49:47] =============== [PASSED] drm_cmdline_parser ================
[23:49:47] ========== drmm_connector_hdmi_init (20 subtests) ==========
[23:49:47] [PASSED] drm_test_connector_hdmi_init_valid
[23:49:47] [PASSED] drm_test_connector_hdmi_init_bpc_8
[23:49:47] [PASSED] drm_test_connector_hdmi_init_bpc_10
[23:49:47] [PASSED] drm_test_connector_hdmi_init_bpc_12
[23:49:47] [PASSED] drm_test_connector_hdmi_init_bpc_invalid
[23:49:47] [PASSED] drm_test_connector_hdmi_init_bpc_null
[23:49:47] [PASSED] drm_test_connector_hdmi_init_formats_empty
[23:49:47] [PASSED] drm_test_connector_hdmi_init_formats_no_rgb
[23:49:47] === drm_test_connector_hdmi_init_formats_yuv420_allowed  ===
[23:49:47] [PASSED] supported_formats=0x9 yuv420_allowed=1
[23:49:47] [PASSED] supported_formats=0x9 yuv420_allowed=0
[23:49:47] [PASSED] supported_formats=0x5 yuv420_allowed=1
[23:49:47] [PASSED] supported_formats=0x5 yuv420_allowed=0
[23:49:47] === [PASSED] drm_test_connector_hdmi_init_formats_yuv420_allowed ===
[23:49:47] [PASSED] drm_test_connector_hdmi_init_null_ddc
[23:49:47] [PASSED] drm_test_connector_hdmi_init_null_product
[23:49:47] [PASSED] drm_test_connector_hdmi_init_null_vendor
[23:49:47] [PASSED] drm_test_connector_hdmi_init_product_length_exact
[23:49:47] [PASSED] drm_test_connector_hdmi_init_product_length_too_long
[23:49:47] [PASSED] drm_test_connector_hdmi_init_product_valid
[23:49:47] [PASSED] drm_test_connector_hdmi_init_vendor_length_exact
[23:49:47] [PASSED] drm_test_connector_hdmi_init_vendor_length_too_long
[23:49:47] [PASSED] drm_test_connector_hdmi_init_vendor_valid
[23:49:47] ========= drm_test_connector_hdmi_init_type_valid  =========
[23:49:47] [PASSED] HDMI-A
[23:49:47] [PASSED] HDMI-B
[23:49:47] ===== [PASSED] drm_test_connector_hdmi_init_type_valid =====
[23:49:47] ======== drm_test_connector_hdmi_init_type_invalid  ========
[23:49:47] [PASSED] Unknown
[23:49:47] [PASSED] VGA
[23:49:47] [PASSED] DVI-I
[23:49:47] [PASSED] DVI-D
[23:49:47] [PASSED] DVI-A
[23:49:47] [PASSED] Composite
[23:49:47] [PASSED] SVIDEO
[23:49:47] [PASSED] LVDS
[23:49:47] [PASSED] Component
[23:49:47] [PASSED] DIN
[23:49:47] [PASSED] DP
[23:49:47] [PASSED] TV
[23:49:47] [PASSED] eDP
[23:49:47] [PASSED] Virtual
[23:49:47] [PASSED] DSI
[23:49:47] [PASSED] DPI
[23:49:47] [PASSED] Writeback
[23:49:47] [PASSED] SPI
[23:49:47] [PASSED] USB
[23:49:47] ==== [PASSED] drm_test_connector_hdmi_init_type_invalid ====
[23:49:47] ============ [PASSED] drmm_connector_hdmi_init =============
[23:49:47] ============= drmm_connector_init (3 subtests) =============
[23:49:47] [PASSED] drm_test_drmm_connector_init
[23:49:47] [PASSED] drm_test_drmm_connector_init_null_ddc
[23:49:47] ========= drm_test_drmm_connector_init_type_valid  =========
[23:49:47] [PASSED] Unknown
[23:49:47] [PASSED] VGA
[23:49:47] [PASSED] DVI-I
[23:49:47] [PASSED] DVI-D
[23:49:47] [PASSED] DVI-A
[23:49:47] [PASSED] Composite
[23:49:47] [PASSED] SVIDEO
[23:49:47] [PASSED] LVDS
[23:49:47] [PASSED] Component
[23:49:47] [PASSED] DIN
[23:49:47] [PASSED] DP
[23:49:47] [PASSED] HDMI-A
[23:49:47] [PASSED] HDMI-B
[23:49:47] [PASSED] TV
[23:49:47] [PASSED] eDP
[23:49:47] [PASSED] Virtual
[23:49:47] [PASSED] DSI
[23:49:47] [PASSED] DPI
[23:49:47] [PASSED] Writeback
[23:49:47] [PASSED] SPI
[23:49:47] [PASSED] USB
[23:49:47] ===== [PASSED] drm_test_drmm_connector_init_type_valid =====
[23:49:47] =============== [PASSED] drmm_connector_init ===============
[23:49:47] ========= drm_connector_dynamic_init (6 subtests) ==========
[23:49:47] [PASSED] drm_test_drm_connector_dynamic_init
[23:49:47] [PASSED] drm_test_drm_connector_dynamic_init_null_ddc
[23:49:47] [PASSED] drm_test_drm_connector_dynamic_init_not_added
[23:49:47] [PASSED] drm_test_drm_connector_dynamic_init_properties
[23:49:47] ===== drm_test_drm_connector_dynamic_init_type_valid  ======
[23:49:47] [PASSED] Unknown
[23:49:47] [PASSED] VGA
[23:49:47] [PASSED] DVI-I
[23:49:47] [PASSED] DVI-D
[23:49:47] [PASSED] DVI-A
[23:49:47] [PASSED] Composite
[23:49:47] [PASSED] SVIDEO
[23:49:47] [PASSED] LVDS
[23:49:47] [PASSED] Component
[23:49:47] [PASSED] DIN
[23:49:47] [PASSED] DP
[23:49:47] [PASSED] HDMI-A
[23:49:47] [PASSED] HDMI-B
[23:49:47] [PASSED] TV
[23:49:47] [PASSED] eDP
[23:49:47] [PASSED] Virtual
[23:49:47] [PASSED] DSI
[23:49:47] [PASSED] DPI
[23:49:47] [PASSED] Writeback
[23:49:47] [PASSED] SPI
[23:49:47] [PASSED] USB
[23:49:47] = [PASSED] drm_test_drm_connector_dynamic_init_type_valid ==
[23:49:47] ======== drm_test_drm_connector_dynamic_init_name  =========
[23:49:47] [PASSED] Unknown
[23:49:47] [PASSED] VGA
[23:49:47] [PASSED] DVI-I
[23:49:47] [PASSED] DVI-D
[23:49:47] [PASSED] DVI-A
[23:49:47] [PASSED] Composite
[23:49:47] [PASSED] SVIDEO
[23:49:47] [PASSED] LVDS
[23:49:47] [PASSED] Component
[23:49:47] [PASSED] DIN
[23:49:47] [PASSED] DP
[23:49:47] [PASSED] HDMI-A
[23:49:47] [PASSED] HDMI-B
[23:49:47] [PASSED] TV
[23:49:47] [PASSED] eDP
[23:49:47] [PASSED] Virtual
[23:49:47] [PASSED] DSI
[23:49:47] [PASSED] DPI
[23:49:47] [PASSED] Writeback
[23:49:47] [PASSED] SPI
[23:49:47] [PASSED] USB
[23:49:47] ==== [PASSED] drm_test_drm_connector_dynamic_init_name =====
[23:49:47] =========== [PASSED] drm_connector_dynamic_init ============
[23:49:47] ==== drm_connector_dynamic_register_early (4 subtests) =====
[23:49:47] [PASSED] drm_test_drm_connector_dynamic_register_early_on_list
[23:49:47] [PASSED] drm_test_drm_connector_dynamic_register_early_defer
[23:49:47] [PASSED] drm_test_drm_connector_dynamic_register_early_no_init
[23:49:47] [PASSED] drm_test_drm_connector_dynamic_register_early_no_mode_object
[23:49:47] ====== [PASSED] drm_connector_dynamic_register_early =======
[23:49:47] ======= drm_connector_dynamic_register (7 subtests) ========
[23:49:47] [PASSED] drm_test_drm_connector_dynamic_register_on_list
[23:49:47] [PASSED] drm_test_drm_connector_dynamic_register_no_defer
[23:49:47] [PASSED] drm_test_drm_connector_dynamic_register_no_init
[23:49:47] [PASSED] drm_test_drm_connector_dynamic_register_mode_object
[23:49:47] [PASSED] drm_test_drm_connector_dynamic_register_sysfs
[23:49:47] [PASSED] drm_test_drm_connector_dynamic_register_sysfs_name
[23:49:47] [PASSED] drm_test_drm_connector_dynamic_register_debugfs
[23:49:47] ========= [PASSED] drm_connector_dynamic_register ==========
[23:49:47] = drm_connector_attach_broadcast_rgb_property (2 subtests) =
[23:49:47] [PASSED] drm_test_drm_connector_attach_broadcast_rgb_property
[23:49:47] [PASSED] drm_test_drm_connector_attach_broadcast_rgb_property_hdmi_connector
[23:49:47] === [PASSED] drm_connector_attach_broadcast_rgb_property ===
[23:49:47] ========== drm_get_tv_mode_from_name (2 subtests) ==========
[23:49:47] ========== drm_test_get_tv_mode_from_name_valid  ===========
[23:49:47] [PASSED] NTSC
[23:49:47] [PASSED] NTSC-443
[23:49:47] [PASSED] NTSC-J
[23:49:47] [PASSED] PAL
[23:49:47] [PASSED] PAL-M
[23:49:47] [PASSED] PAL-N
[23:49:47] [PASSED] SECAM
[23:49:47] [PASSED] Mono
[23:49:47] ====== [PASSED] drm_test_get_tv_mode_from_name_valid =======
[23:49:47] [PASSED] drm_test_get_tv_mode_from_name_truncated
[23:49:47] ============ [PASSED] drm_get_tv_mode_from_name ============
[23:49:47] = drm_test_connector_hdmi_compute_mode_clock (12 subtests) =
[23:49:47] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb
[23:49:47] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_10bpc
[23:49:47] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_10bpc_vic_1
[23:49:47] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_12bpc
[23:49:47] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_12bpc_vic_1
[23:49:47] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_double
[23:49:47] = drm_test_connector_hdmi_compute_mode_clock_yuv420_valid  =
[23:49:47] [PASSED] VIC 96
[23:49:47] [PASSED] VIC 97
[23:49:47] [PASSED] VIC 101
[23:49:47] [PASSED] VIC 102
[23:49:47] [PASSED] VIC 106
[23:49:47] [PASSED] VIC 107
[23:49:47] === [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv420_valid ===
[23:49:47] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv420_10_bpc
[23:49:47] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv420_12_bpc
[23:49:47] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv422_8_bpc
[23:49:47] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv422_10_bpc
[23:49:47] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv422_12_bpc
[23:49:47] === [PASSED] drm_test_connector_hdmi_compute_mode_clock ====
[23:49:47] == drm_hdmi_connector_get_broadcast_rgb_name (2 subtests) ==
[23:49:47] === drm_test_drm_hdmi_connector_get_broadcast_rgb_name  ====
[23:49:47] [PASSED] Automatic
[23:49:47] [PASSED] Full
[23:49:47] [PASSED] Limited 16:235
[23:49:47] === [PASSED] drm_test_drm_hdmi_connector_get_broadcast_rgb_name ===
[23:49:47] [PASSED] drm_test_drm_hdmi_connector_get_broadcast_rgb_name_invalid
[23:49:47] ==== [PASSED] drm_hdmi_connector_get_broadcast_rgb_name ====
[23:49:47] == drm_hdmi_connector_get_output_format_name (2 subtests) ==
[23:49:47] === drm_test_drm_hdmi_connector_get_output_format_name  ====
[23:49:47] [PASSED] RGB
[23:49:47] [PASSED] YUV 4:2:0
[23:49:47] [PASSED] YUV 4:2:2
[23:49:47] [PASSED] YUV 4:4:4
[23:49:47] === [PASSED] drm_test_drm_hdmi_connector_get_output_format_name ===
[23:49:47] [PASSED] drm_test_drm_hdmi_connector_get_output_format_name_invalid
[23:49:47] ==== [PASSED] drm_hdmi_connector_get_output_format_name ====
[23:49:47] ============= drm_damage_helper (21 subtests) ==============
[23:49:47] [PASSED] drm_test_damage_iter_no_damage
[23:49:47] [PASSED] drm_test_damage_iter_no_damage_fractional_src
[23:49:47] [PASSED] drm_test_damage_iter_no_damage_src_moved
[23:49:47] [PASSED] drm_test_damage_iter_no_damage_fractional_src_moved
[23:49:47] [PASSED] drm_test_damage_iter_no_damage_not_visible
[23:49:47] [PASSED] drm_test_damage_iter_no_damage_no_crtc
[23:49:47] [PASSED] drm_test_damage_iter_no_damage_no_fb
[23:49:47] [PASSED] drm_test_damage_iter_simple_damage
[23:49:47] [PASSED] drm_test_damage_iter_single_damage
[23:49:47] [PASSED] drm_test_damage_iter_single_damage_intersect_src
[23:49:47] [PASSED] drm_test_damage_iter_single_damage_outside_src
[23:49:47] [PASSED] drm_test_damage_iter_single_damage_fractional_src
[23:49:47] [PASSED] drm_test_damage_iter_single_damage_intersect_fractional_src
[23:49:47] [PASSED] drm_test_damage_iter_single_damage_outside_fractional_src
[23:49:47] [PASSED] drm_test_damage_iter_single_damage_src_moved
[23:49:47] [PASSED] drm_test_damage_iter_single_damage_fractional_src_moved
[23:49:47] [PASSED] drm_test_damage_iter_damage
[23:49:47] [PASSED] drm_test_damage_iter_damage_one_intersect
[23:49:47] [PASSED] drm_test_damage_iter_damage_one_outside
[23:49:47] [PASSED] drm_test_damage_iter_damage_src_moved
[23:49:47] [PASSED] drm_test_damage_iter_damage_not_visible
[23:49:47] ================ [PASSED] drm_damage_helper ================
[23:49:47] ============== drm_dp_mst_helper (3 subtests) ==============
[23:49:47] ============== drm_test_dp_mst_calc_pbn_mode  ==============
[23:49:47] [PASSED] Clock 154000 BPP 30 DSC disabled
[23:49:47] [PASSED] Clock 234000 BPP 30 DSC disabled
[23:49:47] [PASSED] Clock 297000 BPP 24 DSC disabled
[23:49:47] [PASSED] Clock 332880 BPP 24 DSC enabled
[23:49:47] [PASSED] Clock 324540 BPP 24 DSC enabled
[23:49:47] ========== [PASSED] drm_test_dp_mst_calc_pbn_mode ==========
[23:49:47] ============== drm_test_dp_mst_calc_pbn_div  ===============
[23:49:47] [PASSED] Link rate 2000000 lane count 4
[23:49:47] [PASSED] Link rate 2000000 lane count 2
[23:49:47] [PASSED] Link rate 2000000 lane count 1
[23:49:47] [PASSED] Link rate 1350000 lane count 4
[23:49:47] [PASSED] Link rate 1350000 lane count 2
[23:49:47] [PASSED] Link rate 1350000 lane count 1
[23:49:47] [PASSED] Link rate 1000000 lane count 4
[23:49:47] [PASSED] Link rate 1000000 lane count 2
[23:49:47] [PASSED] Link rate 1000000 lane count 1
[23:49:47] [PASSED] Link rate 810000 lane count 4
[23:49:47] [PASSED] Link rate 810000 lane count 2
[23:49:47] [PASSED] Link rate 810000 lane count 1
[23:49:47] [PASSED] Link rate 540000 lane count 4
[23:49:47] [PASSED] Link rate 540000 lane count 2
[23:49:47] [PASSED] Link rate 540000 lane count 1
[23:49:47] [PASSED] Link rate 270000 lane count 4
[23:49:47] [PASSED] Link rate 270000 lane count 2
[23:49:47] [PASSED] Link rate 270000 lane count 1
[23:49:47] [PASSED] Link rate 162000 lane count 4
[23:49:47] [PASSED] Link rate 162000 lane count 2
[23:49:47] [PASSED] Link rate 162000 lane count 1
[23:49:47] ========== [PASSED] drm_test_dp_mst_calc_pbn_div ===========
[23:49:47] ========= drm_test_dp_mst_sideband_msg_req_decode  =========
[23:49:47] [PASSED] DP_ENUM_PATH_RESOURCES with port number
[23:49:47] [PASSED] DP_POWER_UP_PHY with port number
[23:49:47] [PASSED] DP_POWER_DOWN_PHY with port number
[23:49:47] [PASSED] DP_ALLOCATE_PAYLOAD with SDP stream sinks
[23:49:47] [PASSED] DP_ALLOCATE_PAYLOAD with port number
[23:49:47] [PASSED] DP_ALLOCATE_PAYLOAD with VCPI
[23:49:47] [PASSED] DP_ALLOCATE_PAYLOAD with PBN
[23:49:47] [PASSED] DP_QUERY_PAYLOAD with port number
[23:49:47] [PASSED] DP_QUERY_PAYLOAD with VCPI
[23:49:47] [PASSED] DP_REMOTE_DPCD_READ with port number
[23:49:47] [PASSED] DP_REMOTE_DPCD_READ with DPCD address
[23:49:47] [PASSED] DP_REMOTE_DPCD_READ with max number of bytes
[23:49:47] [PASSED] DP_REMOTE_DPCD_WRITE with port number
[23:49:47] [PASSED] DP_REMOTE_DPCD_WRITE with DPCD address
[23:49:47] [PASSED] DP_REMOTE_DPCD_WRITE with data array
[23:49:47] [PASSED] DP_REMOTE_I2C_READ with port number
[23:49:47] [PASSED] DP_REMOTE_I2C_READ with I2C device ID
[23:49:47] [PASSED] DP_REMOTE_I2C_READ with transactions array
[23:49:47] [PASSED] DP_REMOTE_I2C_WRITE with port number
[23:49:47] [PASSED] DP_REMOTE_I2C_WRITE with I2C device ID
[23:49:47] [PASSED] DP_REMOTE_I2C_WRITE with data array
[23:49:47] [PASSED] DP_QUERY_STREAM_ENC_STATUS with stream ID
[23:49:47] [PASSED] DP_QUERY_STREAM_ENC_STATUS with client ID
[23:49:47] [PASSED] DP_QUERY_STREAM_ENC_STATUS with stream event
[23:49:47] [PASSED] DP_QUERY_STREAM_ENC_STATUS with valid stream event
[23:49:47] [PASSED] DP_QUERY_STREAM_ENC_STATUS with stream behavior
[23:49:47] [PASSED] DP_QUERY_STREAM_ENC_STATUS with a valid stream behavior
[23:49:47] ===== [PASSED] drm_test_dp_mst_sideband_msg_req_decode =====
[23:49:47] ================ [PASSED] drm_dp_mst_helper ================
[23:49:47] ================== drm_exec (7 subtests) ===================
[23:49:47] [PASSED] sanitycheck
[23:49:47] [PASSED] test_lock
[23:49:47] [PASSED] test_lock_unlock
[23:49:47] [PASSED] test_duplicates
[23:49:47] [PASSED] test_prepare
[23:49:47] [PASSED] test_prepare_array
[23:49:47] [PASSED] test_multiple_loops
[23:49:47] ==================== [PASSED] drm_exec =====================
[23:49:47] =========== drm_format_helper_test (17 subtests) ===========
[23:49:47] ============== drm_test_fb_xrgb8888_to_gray8  ==============
[23:49:47] [PASSED] single_pixel_source_buffer
[23:49:47] [PASSED] single_pixel_clip_rectangle
[23:49:47] [PASSED] well_known_colors
[23:49:47] [PASSED] destination_pitch
[23:49:47] ========== [PASSED] drm_test_fb_xrgb8888_to_gray8 ==========
[23:49:47] ============= drm_test_fb_xrgb8888_to_rgb332  ==============
[23:49:47] [PASSED] single_pixel_source_buffer
[23:49:47] [PASSED] single_pixel_clip_rectangle
[23:49:47] [PASSED] well_known_colors
[23:49:47] [PASSED] destination_pitch
[23:49:47] ========= [PASSED] drm_test_fb_xrgb8888_to_rgb332 ==========
[23:49:47] ============= drm_test_fb_xrgb8888_to_rgb565  ==============
[23:49:47] [PASSED] single_pixel_source_buffer
[23:49:47] [PASSED] single_pixel_clip_rectangle
[23:49:47] [PASSED] well_known_colors
[23:49:47] [PASSED] destination_pitch
[23:49:47] ========= [PASSED] drm_test_fb_xrgb8888_to_rgb565 ==========
[23:49:47] ============ drm_test_fb_xrgb8888_to_xrgb1555  =============
[23:49:47] [PASSED] single_pixel_source_buffer
[23:49:47] [PASSED] single_pixel_clip_rectangle
[23:49:47] [PASSED] well_known_colors
[23:49:47] [PASSED] destination_pitch
[23:49:47] ======== [PASSED] drm_test_fb_xrgb8888_to_xrgb1555 =========
[23:49:47] ============ drm_test_fb_xrgb8888_to_argb1555  =============
[23:49:47] [PASSED] single_pixel_source_buffer
[23:49:47] [PASSED] single_pixel_clip_rectangle
[23:49:47] [PASSED] well_known_colors
[23:49:47] [PASSED] destination_pitch
[23:49:47] ======== [PASSED] drm_test_fb_xrgb8888_to_argb1555 =========
[23:49:47] ============ drm_test_fb_xrgb8888_to_rgba5551  =============
[23:49:47] [PASSED] single_pixel_source_buffer
[23:49:47] [PASSED] single_pixel_clip_rectangle
[23:49:47] [PASSED] well_known_colors
[23:49:47] [PASSED] destination_pitch
[23:49:47] ======== [PASSED] drm_test_fb_xrgb8888_to_rgba5551 =========
[23:49:47] ============= drm_test_fb_xrgb8888_to_rgb888  ==============
[23:49:47] [PASSED] single_pixel_source_buffer
[23:49:47] [PASSED] single_pixel_clip_rectangle
[23:49:47] [PASSED] well_known_colors
[23:49:47] [PASSED] destination_pitch
[23:49:47] ========= [PASSED] drm_test_fb_xrgb8888_to_rgb888 ==========
[23:49:47] ============= drm_test_fb_xrgb8888_to_bgr888  ==============
[23:49:47] [PASSED] single_pixel_source_buffer
[23:49:47] [PASSED] single_pixel_clip_rectangle
[23:49:47] [PASSED] well_known_colors
[23:49:47] [PASSED] destination_pitch
[23:49:47] ========= [PASSED] drm_test_fb_xrgb8888_to_bgr888 ==========
[23:49:47] ============ drm_test_fb_xrgb8888_to_argb8888  =============
[23:49:47] [PASSED] single_pixel_source_buffer
[23:49:47] [PASSED] single_pixel_clip_rectangle
[23:49:47] [PASSED] well_known_colors
[23:49:47] [PASSED] destination_pitch
[23:49:47] ======== [PASSED] drm_test_fb_xrgb8888_to_argb8888 =========
[23:49:47] =========== drm_test_fb_xrgb8888_to_xrgb2101010  ===========
[23:49:47] [PASSED] single_pixel_source_buffer
[23:49:47] [PASSED] single_pixel_clip_rectangle
[23:49:47] [PASSED] well_known_colors
[23:49:47] [PASSED] destination_pitch
[23:49:47] ======= [PASSED] drm_test_fb_xrgb8888_to_xrgb2101010 =======
[23:49:47] =========== drm_test_fb_xrgb8888_to_argb2101010  ===========
[23:49:47] [PASSED] single_pixel_source_buffer
[23:49:47] [PASSED] single_pixel_clip_rectangle
[23:49:47] [PASSED] well_known_colors
[23:49:47] [PASSED] destination_pitch
[23:49:47] ======= [PASSED] drm_test_fb_xrgb8888_to_argb2101010 =======
[23:49:47] ============== drm_test_fb_xrgb8888_to_mono  ===============
[23:49:47] [PASSED] single_pixel_source_buffer
[23:49:47] [PASSED] single_pixel_clip_rectangle
[23:49:47] [PASSED] well_known_colors
[23:49:47] [PASSED] destination_pitch
[23:49:47] ========== [PASSED] drm_test_fb_xrgb8888_to_mono ===========
[23:49:47] ==================== drm_test_fb_swab  =====================
[23:49:47] [PASSED] single_pixel_source_buffer
[23:49:47] [PASSED] single_pixel_clip_rectangle
[23:49:47] [PASSED] well_known_colors
[23:49:47] [PASSED] destination_pitch
[23:49:47] ================ [PASSED] drm_test_fb_swab =================
[23:49:47] ============ drm_test_fb_xrgb8888_to_xbgr8888  =============
[23:49:47] [PASSED] single_pixel_source_buffer
[23:49:47] [PASSED] single_pixel_clip_rectangle
[23:49:47] [PASSED] well_known_colors
[23:49:47] [PASSED] destination_pitch
[23:49:47] ======== [PASSED] drm_test_fb_xrgb8888_to_xbgr8888 =========
[23:49:47] ============ drm_test_fb_xrgb8888_to_abgr8888  =============
[23:49:47] [PASSED] single_pixel_source_buffer
[23:49:47] [PASSED] single_pixel_clip_rectangle
[23:49:47] [PASSED] well_known_colors
[23:49:47] [PASSED] destination_pitch
[23:49:47] ======== [PASSED] drm_test_fb_xrgb8888_to_abgr8888 =========
[23:49:47] ================= drm_test_fb_clip_offset  =================
[23:49:47] [PASSED] pass through
[23:49:47] [PASSED] horizontal offset
[23:49:47] [PASSED] vertical offset
[23:49:47] [PASSED] horizontal and vertical offset
[23:49:47] [PASSED] horizontal offset (custom pitch)
[23:49:47] [PASSED] vertical offset (custom pitch)
[23:49:47] [PASSED] horizontal and vertical offset (custom pitch)
[23:49:47] ============= [PASSED] drm_test_fb_clip_offset =============
[23:49:47] =================== drm_test_fb_memcpy  ====================
[23:49:47] [PASSED] single_pixel_source_buffer: XR24 little-endian (0x34325258)
[23:49:47] [PASSED] single_pixel_source_buffer: XRA8 little-endian (0x38415258)
[23:49:47] [PASSED] single_pixel_source_buffer: YU24 little-endian (0x34325559)
[23:49:47] [PASSED] single_pixel_clip_rectangle: XB24 little-endian (0x34324258)
[23:49:47] [PASSED] single_pixel_clip_rectangle: XRA8 little-endian (0x38415258)
[23:49:47] [PASSED] single_pixel_clip_rectangle: YU24 little-endian (0x34325559)
[23:49:47] [PASSED] well_known_colors: XB24 little-endian (0x34324258)
[23:49:47] [PASSED] well_known_colors: XRA8 little-endian (0x38415258)
[23:49:47] [PASSED] well_known_colors: YU24 little-endian (0x34325559)
[23:49:47] [PASSED] destination_pitch: XB24 little-endian (0x34324258)
[23:49:47] [PASSED] destination_pitch: XRA8 little-endian (0x38415258)
[23:49:47] [PASSED] destination_pitch: YU24 little-endian (0x34325559)
[23:49:47] =============== [PASSED] drm_test_fb_memcpy ================
[23:49:47] ============= [PASSED] drm_format_helper_test ==============
[23:49:47] ================= drm_format (18 subtests) =================
[23:49:47] [PASSED] drm_test_format_block_width_invalid
[23:49:47] [PASSED] drm_test_format_block_width_one_plane
[23:49:47] [PASSED] drm_test_format_block_width_two_plane
[23:49:47] [PASSED] drm_test_format_block_width_three_plane
[23:49:47] [PASSED] drm_test_format_block_width_tiled
[23:49:47] [PASSED] drm_test_format_block_height_invalid
[23:49:47] [PASSED] drm_test_format_block_height_one_plane
[23:49:47] [PASSED] drm_test_format_block_height_two_plane
[23:49:47] [PASSED] drm_test_format_block_height_three_plane
[23:49:47] [PASSED] drm_test_format_block_height_tiled
[23:49:47] [PASSED] drm_test_format_min_pitch_invalid
[23:49:47] [PASSED] drm_test_format_min_pitch_one_plane_8bpp
[23:49:47] [PASSED] drm_test_format_min_pitch_one_plane_16bpp
[23:49:47] [PASSED] drm_test_format_min_pitch_one_plane_24bpp
[23:49:47] [PASSED] drm_test_format_min_pitch_one_plane_32bpp
[23:49:47] [PASSED] drm_test_format_min_pitch_two_plane
[23:49:47] [PASSED] drm_test_format_min_pitch_three_plane_8bpp
[23:49:47] [PASSED] drm_test_format_min_pitch_tiled
[23:49:47] =================== [PASSED] drm_format ====================
[23:49:47] ============== drm_framebuffer (10 subtests) ===============
[23:49:47] ========== drm_test_framebuffer_check_src_coords  ==========
[23:49:47] [PASSED] Success: source fits into fb
[23:49:47] [PASSED] Fail: overflowing fb with x-axis coordinate
[23:49:47] [PASSED] Fail: overflowing fb with y-axis coordinate
[23:49:47] [PASSED] Fail: overflowing fb with source width
[23:49:47] [PASSED] Fail: overflowing fb with source height
[23:49:47] ====== [PASSED] drm_test_framebuffer_check_src_coords ======
[23:49:47] [PASSED] drm_test_framebuffer_cleanup
[23:49:47] =============== drm_test_framebuffer_create  ===============
[23:49:47] [PASSED] ABGR8888 normal sizes
[23:49:47] [PASSED] ABGR8888 max sizes
[23:49:47] [PASSED] ABGR8888 pitch greater than min required
[23:49:47] [PASSED] ABGR8888 pitch less than min required
[23:49:47] [PASSED] ABGR8888 Invalid width
[23:49:47] [PASSED] ABGR8888 Invalid buffer handle
[23:49:47] [PASSED] No pixel format
[23:49:47] [PASSED] ABGR8888 Width 0
[23:49:47] [PASSED] ABGR8888 Height 0
[23:49:47] [PASSED] ABGR8888 Out of bound height * pitch combination
[23:49:47] [PASSED] ABGR8888 Large buffer offset
[23:49:47] [PASSED] ABGR8888 Buffer offset for inexistent plane
[23:49:47] [PASSED] ABGR8888 Invalid flag
[23:49:47] [PASSED] ABGR8888 Set DRM_MODE_FB_MODIFIERS without modifiers
[23:49:47] [PASSED] ABGR8888 Valid buffer modifier
[23:49:47] [PASSED] ABGR8888 Invalid buffer modifier(DRM_FORMAT_MOD_SAMSUNG_64_32_TILE)
[23:49:47] [PASSED] ABGR8888 Extra pitches without DRM_MODE_FB_MODIFIERS
[23:49:47] [PASSED] ABGR8888 Extra pitches with DRM_MODE_FB_MODIFIERS
[23:49:47] [PASSED] NV12 Normal sizes
[23:49:47] [PASSED] NV12 Max sizes
[23:49:47] [PASSED] NV12 Invalid pitch
[23:49:47] [PASSED] NV12 Invalid modifier/missing DRM_MODE_FB_MODIFIERS flag
[23:49:47] [PASSED] NV12 different  modifier per-plane
[23:49:47] [PASSED] NV12 with DRM_FORMAT_MOD_SAMSUNG_64_32_TILE
[23:49:47] [PASSED] NV12 Valid modifiers without DRM_MODE_FB_MODIFIERS
[23:49:47] [PASSED] NV12 Modifier for inexistent plane
[23:49:47] [PASSED] NV12 Handle for inexistent plane
[23:49:47] [PASSED] NV12 Handle for inexistent plane without DRM_MODE_FB_MODIFIERS
[23:49:47] [PASSED] YVU420 DRM_MODE_FB_MODIFIERS set without modifier
[23:49:47] [PASSED] YVU420 Normal sizes
[23:49:47] [PASSED] YVU420 Max sizes
[23:49:47] [PASSED] YVU420 Invalid pitch
[23:49:47] [PASSED] YVU420 Different pitches
[23:49:47] [PASSED] YVU420 Different buffer offsets/pitches
[23:49:47] [PASSED] YVU420 Modifier set just for plane 0, without DRM_MODE_FB_MODIFIERS
[23:49:47] [PASSED] YVU420 Modifier set just for planes 0, 1, without DRM_MODE_FB_MODIFIERS
[23:49:47] [PASSED] YVU420 Modifier set just for plane 0, 1, with DRM_MODE_FB_MODIFIERS
[23:49:47] [PASSED] YVU420 Valid modifier
[23:49:47] [PASSED] YVU420 Different modifiers per plane
[23:49:47] [PASSED] YVU420 Modifier for inexistent plane
[23:49:47] [PASSED] YUV420_10BIT Invalid modifier(DRM_FORMAT_MOD_LINEAR)
[23:49:47] [PASSED] X0L2 Normal sizes
[23:49:47] [PASSED] X0L2 Max sizes
[23:49:47] [PASSED] X0L2 Invalid pitch
[23:49:47] [PASSED] X0L2 Pitch greater than minimum required
[23:49:47] [PASSED] X0L2 Handle for inexistent plane
[23:49:47] [PASSED] X0L2 Offset for inexistent plane, without DRM_MODE_FB_MODIFIERS set
[23:49:47] [PASSED] X0L2 Modifier without DRM_MODE_FB_MODIFIERS set
[23:49:47] [PASSED] X0L2 Valid modifier
[23:49:47] [PASSED] X0L2 Modifier for inexistent plane
[23:49:47] =========== [PASSED] drm_test_framebuffer_create ===========
[23:49:47] [PASSED] drm_test_framebuffer_free
[23:49:47] [PASSED] drm_test_framebuffer_init
[23:49:47] [PASSED] drm_test_framebuffer_init_bad_format
[23:49:47] [PASSED] drm_test_framebuffer_init_dev_mismatch
[23:49:47] [PASSED] drm_test_framebuffer_lookup
[23:49:47] [PASSED] drm_test_framebuffer_lookup_inexistent
[23:49:47] [PASSED] drm_test_framebuffer_modifiers_not_supported
[23:49:47] ================= [PASSED] drm_framebuffer =================
[23:49:47] ================ drm_gem_shmem (8 subtests) ================
[23:49:47] [PASSED] drm_gem_shmem_test_obj_create
[23:49:47] [PASSED] drm_gem_shmem_test_obj_create_private
[23:49:47] [PASSED] drm_gem_shmem_test_pin_pages
[23:49:47] [PASSED] drm_gem_shmem_test_vmap
[23:49:47] [PASSED] drm_gem_shmem_test_get_sg_table
[23:49:47] [PASSED] drm_gem_shmem_test_get_pages_sgt
[23:49:47] [PASSED] drm_gem_shmem_test_madvise
[23:49:47] [PASSED] drm_gem_shmem_test_purge
[23:49:47] ================== [PASSED] drm_gem_shmem ==================
[23:49:47] === drm_atomic_helper_connector_hdmi_check (29 subtests) ===
[23:49:47] [PASSED] drm_test_check_broadcast_rgb_auto_cea_mode
[23:49:47] [PASSED] drm_test_check_broadcast_rgb_auto_cea_mode_vic_1
[23:49:47] [PASSED] drm_test_check_broadcast_rgb_full_cea_mode
[23:49:47] [PASSED] drm_test_check_broadcast_rgb_full_cea_mode_vic_1
[23:49:47] [PASSED] drm_test_check_broadcast_rgb_limited_cea_mode
[23:49:47] [PASSED] drm_test_check_broadcast_rgb_limited_cea_mode_vic_1
[23:49:47] ====== drm_test_check_broadcast_rgb_cea_mode_yuv420  =======
[23:49:47] [PASSED] Automatic
[23:49:47] [PASSED] Full
[23:49:47] [PASSED] Limited 16:235
[23:49:47] == [PASSED] drm_test_check_broadcast_rgb_cea_mode_yuv420 ===
[23:49:47] [PASSED] drm_test_check_broadcast_rgb_crtc_mode_changed
[23:49:47] [PASSED] drm_test_check_broadcast_rgb_crtc_mode_not_changed
[23:49:47] [PASSED] drm_test_check_disable_connector
[23:49:47] [PASSED] drm_test_check_hdmi_funcs_reject_rate
[23:49:47] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_rgb
[23:49:47] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_yuv420
[23:49:47] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_ignore_yuv422
[23:49:47] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_ignore_yuv420
[23:49:47] [PASSED] drm_test_check_driver_unsupported_fallback_yuv420
[23:49:47] [PASSED] drm_test_check_output_bpc_crtc_mode_changed
[23:49:47] [PASSED] drm_test_check_output_bpc_crtc_mode_not_changed
[23:49:47] [PASSED] drm_test_check_output_bpc_dvi
[23:49:47] [PASSED] drm_test_check_output_bpc_format_vic_1
[23:49:47] [PASSED] drm_test_check_output_bpc_format_display_8bpc_only
[23:49:47] [PASSED] drm_test_check_output_bpc_format_display_rgb_only
[23:49:47] [PASSED] drm_test_check_output_bpc_format_driver_8bpc_only
[23:49:47] [PASSED] drm_test_check_output_bpc_format_driver_rgb_only
[23:49:47] [PASSED] drm_test_check_tmds_char_rate_rgb_8bpc
[23:49:47] [PASSED] drm_test_check_tmds_char_rate_rgb_10bpc
[23:49:47] [PASSED] drm_test_check_tmds_char_rate_rgb_12bpc
[23:49:47] ============ drm_test_check_hdmi_color_format  =============
[23:49:47] [PASSED] AUTO -> RGB
[23:49:47] [PASSED] YCBCR422 -> YUV422
[23:49:47] [PASSED] YCBCR420 -> YUV420
[23:49:47] [PASSED] YCBCR444 -> YUV444
[23:49:47] [PASSED] RGB -> RGB
[23:49:47] ======== [PASSED] drm_test_check_hdmi_color_format =========
[23:49:47] ======== drm_test_check_hdmi_color_format_420_only  ========
[23:49:47] [PASSED] RGB should fail
[23:49:47] [PASSED] YUV444 should fail
[23:49:47] [PASSED] YUV422 should fail
[23:49:47] [PASSED] YUV420 should work
[23:49:47] ==== [PASSED] drm_test_check_hdmi_color_format_420_only ====
[23:49:47] ===== [PASSED] drm_atomic_helper_connector_hdmi_check ======
[23:49:47] === drm_atomic_helper_connector_hdmi_reset (6 subtests) ====
[23:49:47] [PASSED] drm_test_check_broadcast_rgb_value
[23:49:47] [PASSED] drm_test_check_bpc_8_value
[23:49:47] [PASSED] drm_test_check_bpc_10_value
[23:49:47] [PASSED] drm_test_check_bpc_12_value
[23:49:47] [PASSED] drm_test_check_format_value
[23:49:47] [PASSED] drm_test_check_tmds_char_value
[23:49:47] ===== [PASSED] drm_atomic_helper_connector_hdmi_reset ======
[23:49:47] = drm_atomic_helper_connector_hdmi_mode_valid (7 subtests) =
[23:49:47] [PASSED] drm_test_check_mode_valid
[23:49:47] [PASSED] drm_test_check_mode_valid_reject
[23:49:47] [PASSED] drm_test_check_mode_valid_reject_rate
[23:49:47] [PASSED] drm_test_check_mode_valid_reject_max_clock
[23:49:47] [PASSED] drm_test_check_mode_valid_yuv420_only_max_clock
[23:49:47] [PASSED] drm_test_check_mode_valid_reject_yuv420_only_connector
[23:49:47] [PASSED] drm_test_check_mode_valid_accept_yuv420_also_connector_rgb
[23:49:47] === [PASSED] drm_atomic_helper_connector_hdmi_mode_valid ===
[23:49:47] = drm_atomic_helper_connector_hdmi_infoframes (5 subtests) =
[23:49:47] [PASSED] drm_test_check_infoframes
[23:49:47] [PASSED] drm_test_check_reject_avi_infoframe
[23:49:47] [PASSED] drm_test_check_reject_hdr_infoframe_bpc_8
[23:49:47] [PASSED] drm_test_check_reject_hdr_infoframe_bpc_10
[23:49:47] [PASSED] drm_test_check_reject_audio_infoframe
[23:49:47] === [PASSED] drm_atomic_helper_connector_hdmi_infoframes ===
[23:49:47] ================= drm_managed (2 subtests) =================
[23:49:47] [PASSED] drm_test_managed_release_action
[23:49:47] [PASSED] drm_test_managed_run_action
[23:49:47] =================== [PASSED] drm_managed ===================
[23:49:47] =================== drm_mm (6 subtests) ====================
[23:49:47] [PASSED] drm_test_mm_init
[23:49:47] [PASSED] drm_test_mm_debug
[23:49:47] [PASSED] drm_test_mm_align32
[23:49:47] [PASSED] drm_test_mm_align64
[23:49:47] [PASSED] drm_test_mm_lowest
[23:49:47] [PASSED] drm_test_mm_highest
[23:49:47] ===================== [PASSED] drm_mm ======================
[23:49:47] ============= drm_modes_analog_tv (5 subtests) =============
[23:49:47] [PASSED] drm_test_modes_analog_tv_mono_576i
[23:49:47] [PASSED] drm_test_modes_analog_tv_ntsc_480i
[23:49:47] [PASSED] drm_test_modes_analog_tv_ntsc_480i_inlined
[23:49:47] [PASSED] drm_test_modes_analog_tv_pal_576i
[23:49:47] [PASSED] drm_test_modes_analog_tv_pal_576i_inlined
[23:49:47] =============== [PASSED] drm_modes_analog_tv ===============
[23:49:47] ============== drm_plane_helper (2 subtests) ===============
[23:49:47] =============== drm_test_check_plane_state  ================
[23:49:47] [PASSED] clipping_simple
[23:49:47] [PASSED] clipping_rotate_reflect
[23:49:47] [PASSED] positioning_simple
[23:49:47] [PASSED] upscaling
[23:49:47] [PASSED] downscaling
[23:49:47] [PASSED] rounding1
[23:49:47] [PASSED] rounding2
[23:49:47] [PASSED] rounding3
[23:49:47] [PASSED] rounding4
[23:49:47] =========== [PASSED] drm_test_check_plane_state ============
[23:49:47] =========== drm_test_check_invalid_plane_state  ============
[23:49:47] [PASSED] positioning_invalid
[23:49:47] [PASSED] upscaling_invalid
[23:49:47] [PASSED] downscaling_invalid
[23:49:47] ======= [PASSED] drm_test_check_invalid_plane_state ========
[23:49:47] ================ [PASSED] drm_plane_helper =================
[23:49:47] ====== drm_connector_helper_tv_get_modes (1 subtest) =======
[23:49:47] ====== drm_test_connector_helper_tv_get_modes_check  =======
[23:49:47] [PASSED] None
[23:49:47] [PASSED] PAL
[23:49:47] [PASSED] NTSC
[23:49:47] [PASSED] Both, NTSC Default
[23:49:47] [PASSED] Both, PAL Default
[23:49:47] [PASSED] Both, NTSC Default, with PAL on command-line
[23:49:47] [PASSED] Both, PAL Default, with NTSC on command-line
[23:49:47] == [PASSED] drm_test_connector_helper_tv_get_modes_check ===
[23:49:47] ======== [PASSED] drm_connector_helper_tv_get_modes ========
[23:49:47] ================== drm_rect (9 subtests) ===================
[23:49:47] [PASSED] drm_test_rect_clip_scaled_div_by_zero
[23:49:47] [PASSED] drm_test_rect_clip_scaled_not_clipped
[23:49:47] [PASSED] drm_test_rect_clip_scaled_clipped
[23:49:47] [PASSED] drm_test_rect_clip_scaled_signed_vs_unsigned
[23:49:47] ================= drm_test_rect_intersect  =================
[23:49:47] [PASSED] top-left x bottom-right: 2x2+1+1 x 2x2+0+0
[23:49:47] [PASSED] top-right x bottom-left: 2x2+0+0 x 2x2+1-1
[23:49:47] [PASSED] bottom-left x top-right: 2x2+1-1 x 2x2+0+0
[23:49:47] [PASSED] bottom-right x top-left: 2x2+0+0 x 2x2+1+1
[23:49:47] [PASSED] right x left: 2x1+0+0 x 3x1+1+0
[23:49:47] [PASSED] left x right: 3x1+1+0 x 2x1+0+0
[23:49:47] [PASSED] up x bottom: 1x2+0+0 x 1x3+0-1
[23:49:47] [PASSED] bottom x up: 1x3+0-1 x 1x2+0+0
[23:49:47] [PASSED] touching corner: 1x1+0+0 x 2x2+1+1
[23:49:47] [PASSED] touching side: 1x1+0+0 x 1x1+1+0
[23:49:47] [PASSED] equal rects: 2x2+0+0 x 2x2+0+0
[23:49:47] [PASSED] inside another: 2x2+0+0 x 1x1+1+1
[23:49:47] [PASSED] far away: 1x1+0+0 x 1x1+3+6
[23:49:47] [PASSED] points intersecting: 0x0+5+10 x 0x0+5+10
[23:49:47] [PASSED] points not intersecting: 0x0+0+0 x 0x0+5+10
[23:49:47] ============= [PASSED] drm_test_rect_intersect =============
[23:49:47] ================ drm_test_rect_calc_hscale  ================
[23:49:47] [PASSED] normal use
[23:49:47] [PASSED] out of max range
[23:49:47] [PASSED] out of min range
[23:49:47] [PASSED] zero dst
[23:49:47] [PASSED] negative src
[23:49:47] [PASSED] negative dst
[23:49:47] ============ [PASSED] drm_test_rect_calc_hscale ============
[23:49:47] ================ drm_test_rect_calc_vscale  ================
[23:49:47] [PASSED] normal use
[23:49:47] [PASSED] out of max range
[23:49:47] [PASSED] out of min range
[23:49:47] [PASSED] zero dst
[23:49:47] [PASSED] negative src
[23:49:47] [PASSED] negative dst
[23:49:47] ============ [PASSED] drm_test_rect_calc_vscale ============
[23:49:47] ================== drm_test_rect_rotate  ===================
[23:49:47] [PASSED] reflect-x
[23:49:47] [PASSED] reflect-y
[23:49:47] [PASSED] rotate-0
[23:49:47] [PASSED] rotate-90
[23:49:47] [PASSED] rotate-180
[23:49:47] [PASSED] rotate-270
[23:49:47] ============== [PASSED] drm_test_rect_rotate ===============
[23:49:47] ================ drm_test_rect_rotate_inv  =================
[23:49:47] [PASSED] reflect-x
[23:49:47] [PASSED] reflect-y
[23:49:47] [PASSED] rotate-0
[23:49:47] [PASSED] rotate-90
[23:49:47] [PASSED] rotate-180
[23:49:47] [PASSED] rotate-270
[23:49:47] ============ [PASSED] drm_test_rect_rotate_inv =============
[23:49:47] ==================== [PASSED] drm_rect =====================
[23:49:47] ============ drm_sysfb_modeset_test (1 subtest) ============
[23:49:47] ============ drm_test_sysfb_build_fourcc_list  =============
[23:49:47] [PASSED] no native formats
[23:49:47] [PASSED] XRGB8888 as native format
[23:49:47] [PASSED] remove duplicates
[23:49:47] [PASSED] convert alpha formats
[23:49:47] [PASSED] random formats
[23:49:47] ======== [PASSED] drm_test_sysfb_build_fourcc_list =========
[23:49:47] ============= [PASSED] drm_sysfb_modeset_test ==============
[23:49:47] ================== drm_fixp (2 subtests) ===================
[23:49:47] [PASSED] drm_test_int2fixp
[23:49:47] [PASSED] drm_test_sm2fixp
[23:49:47] ==================== [PASSED] drm_fixp =====================
[23:49:47] ============================================================
[23:49:47] Testing complete. Ran 637 tests: passed: 637
[23:49:47] Elapsed time: 26.768s total, 1.776s configuring, 24.778s building, 0.191s running

+ /kernel/tools/testing/kunit/kunit.py run --kunitconfig /kernel/drivers/gpu/drm/ttm/tests/.kunitconfig
[23:49:47] Configuring KUnit Kernel ...
Regenerating .config ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
[23:49:49] Building KUnit Kernel ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
Building with:
$ make all compile_commands.json scripts_gdb ARCH=um O=.kunit --jobs=48
[23:49:59] Starting KUnit Kernel (1/1)...
[23:49:59] ============================================================
Running tests with:
$ .kunit/linux kunit.enable=1 mem=1G console=tty kunit_shutdown=halt
[23:49:59] ================= ttm_device (5 subtests) ==================
[23:49:59] [PASSED] ttm_device_init_basic
[23:49:59] [PASSED] ttm_device_init_multiple
[23:49:59] [PASSED] ttm_device_fini_basic
[23:49:59] [PASSED] ttm_device_init_no_vma_man
[23:49:59] ================== ttm_device_init_pools  ==================
[23:49:59] [PASSED] No DMA allocations, no DMA32 required
[23:49:59] [PASSED] DMA allocations, DMA32 required
[23:49:59] [PASSED] No DMA allocations, DMA32 required
[23:49:59] [PASSED] DMA allocations, no DMA32 required
[23:49:59] ============== [PASSED] ttm_device_init_pools ==============
[23:49:59] =================== [PASSED] ttm_device ====================
[23:49:59] ================== ttm_pool (8 subtests) ===================
[23:49:59] ================== ttm_pool_alloc_basic  ===================
[23:49:59] [PASSED] One page
[23:49:59] [PASSED] More than one page
[23:49:59] [PASSED] Above the allocation limit
[23:49:59] [PASSED] One page, with coherent DMA mappings enabled
[23:49:59] [PASSED] Above the allocation limit, with coherent DMA mappings enabled
[23:49:59] ============== [PASSED] ttm_pool_alloc_basic ===============
[23:49:59] ============== ttm_pool_alloc_basic_dma_addr  ==============
[23:49:59] [PASSED] One page
[23:49:59] [PASSED] More than one page
[23:49:59] [PASSED] Above the allocation limit
[23:49:59] [PASSED] One page, with coherent DMA mappings enabled
[23:49:59] [PASSED] Above the allocation limit, with coherent DMA mappings enabled
[23:49:59] ========== [PASSED] ttm_pool_alloc_basic_dma_addr ==========
[23:49:59] [PASSED] ttm_pool_alloc_order_caching_match
[23:49:59] [PASSED] ttm_pool_alloc_caching_mismatch
[23:49:59] [PASSED] ttm_pool_alloc_order_mismatch
[23:49:59] [PASSED] ttm_pool_free_dma_alloc
[23:49:59] [PASSED] ttm_pool_free_no_dma_alloc
[23:49:59] [PASSED] ttm_pool_fini_basic
[23:49:59] ==================== [PASSED] ttm_pool =====================
[23:49:59] ================ ttm_resource (8 subtests) =================
[23:49:59] ================= ttm_resource_init_basic  =================
[23:49:59] [PASSED] Init resource in TTM_PL_SYSTEM
[23:49:59] [PASSED] Init resource in TTM_PL_VRAM
[23:49:59] [PASSED] Init resource in a private placement
[23:49:59] [PASSED] Init resource in TTM_PL_SYSTEM, set placement flags
[23:49:59] ============= [PASSED] ttm_resource_init_basic =============
[23:49:59] [PASSED] ttm_resource_init_pinned
[23:49:59] [PASSED] ttm_resource_fini_basic
[23:49:59] [PASSED] ttm_resource_manager_init_basic
[23:49:59] [PASSED] ttm_resource_manager_usage_basic
[23:49:59] [PASSED] ttm_resource_manager_set_used_basic
[23:49:59] [PASSED] ttm_sys_man_alloc_basic
[23:49:59] [PASSED] ttm_sys_man_free_basic
[23:49:59] ================== [PASSED] ttm_resource ===================
[23:49:59] =================== ttm_tt (15 subtests) ===================
[23:49:59] ==================== ttm_tt_init_basic  ====================
[23:49:59] [PASSED] Page-aligned size
[23:49:59] [PASSED] Extra pages requested
[23:49:59] ================ [PASSED] ttm_tt_init_basic ================
[23:49:59] [PASSED] ttm_tt_init_misaligned
[23:49:59] [PASSED] ttm_tt_fini_basic
[23:49:59] [PASSED] ttm_tt_fini_sg
[23:49:59] [PASSED] ttm_tt_fini_shmem
[23:49:59] [PASSED] ttm_tt_create_basic
[23:49:59] [PASSED] ttm_tt_create_invalid_bo_type
[23:49:59] [PASSED] ttm_tt_create_ttm_exists
[23:49:59] [PASSED] ttm_tt_create_failed
[23:49:59] [PASSED] ttm_tt_destroy_basic
[23:49:59] [PASSED] ttm_tt_populate_null_ttm
[23:49:59] [PASSED] ttm_tt_populate_populated_ttm
[23:49:59] [PASSED] ttm_tt_unpopulate_basic
[23:49:59] [PASSED] ttm_tt_unpopulate_empty_ttm
[23:49:59] [PASSED] ttm_tt_swapin_basic
[23:49:59] ===================== [PASSED] ttm_tt ======================
[23:49:59] =================== ttm_bo (14 subtests) ===================
[23:49:59] =========== ttm_bo_reserve_optimistic_no_ticket  ===========
[23:49:59] [PASSED] Cannot be interrupted and sleeps
[23:49:59] [PASSED] Cannot be interrupted, locks straight away
[23:49:59] [PASSED] Can be interrupted, sleeps
[23:49:59] ======= [PASSED] ttm_bo_reserve_optimistic_no_ticket =======
[23:49:59] [PASSED] ttm_bo_reserve_locked_no_sleep
[23:49:59] [PASSED] ttm_bo_reserve_no_wait_ticket
[23:49:59] [PASSED] ttm_bo_reserve_double_resv
[23:49:59] [PASSED] ttm_bo_reserve_interrupted
[23:49:59] [PASSED] ttm_bo_reserve_deadlock
[23:49:59] [PASSED] ttm_bo_unreserve_basic
[23:49:59] [PASSED] ttm_bo_unreserve_pinned
[23:49:59] [PASSED] ttm_bo_unreserve_bulk
[23:49:59] [PASSED] ttm_bo_fini_basic
[23:49:59] [PASSED] ttm_bo_fini_shared_resv
[23:49:59] [PASSED] ttm_bo_pin_basic
[23:49:59] [PASSED] ttm_bo_pin_unpin_resource
[23:49:59] [PASSED] ttm_bo_multiple_pin_one_unpin
[23:49:59] ===================== [PASSED] ttm_bo ======================
[23:49:59] ============== ttm_bo_validate (22 subtests) ===============
[23:49:59] ============== ttm_bo_init_reserved_sys_man  ===============
[23:49:59] [PASSED] Buffer object for userspace
[23:49:59] [PASSED] Kernel buffer object
[23:49:59] [PASSED] Shared buffer object
[23:49:59] ========== [PASSED] ttm_bo_init_reserved_sys_man ===========
[23:49:59] ============== ttm_bo_init_reserved_mock_man  ==============
[23:49:59] [PASSED] Buffer object for userspace
[23:49:59] [PASSED] Kernel buffer object
[23:49:59] [PASSED] Shared buffer object
[23:49:59] ========== [PASSED] ttm_bo_init_reserved_mock_man ==========
[23:49:59] [PASSED] ttm_bo_init_reserved_resv
[23:49:59] ================== ttm_bo_validate_basic  ==================
[23:49:59] [PASSED] Buffer object for userspace
[23:49:59] [PASSED] Kernel buffer object
[23:49:59] [PASSED] Shared buffer object
[23:49:59] ============== [PASSED] ttm_bo_validate_basic ==============
[23:49:59] [PASSED] ttm_bo_validate_invalid_placement
[23:49:59] ============= ttm_bo_validate_same_placement  ==============
[23:49:59] [PASSED] System manager
[23:49:59] [PASSED] VRAM manager
[23:49:59] ========= [PASSED] ttm_bo_validate_same_placement ==========
[23:49:59] [PASSED] ttm_bo_validate_failed_alloc
[23:49:59] [PASSED] ttm_bo_validate_pinned
[23:49:59] [PASSED] ttm_bo_validate_busy_placement
[23:49:59] ================ ttm_bo_validate_multihop  =================
[23:49:59] [PASSED] Buffer object for userspace
[23:49:59] [PASSED] Kernel buffer object
[23:49:59] [PASSED] Shared buffer object
[23:49:59] ============ [PASSED] ttm_bo_validate_multihop =============
[23:49:59] ========== ttm_bo_validate_no_placement_signaled  ==========
[23:49:59] [PASSED] Buffer object in system domain, no page vector
[23:49:59] [PASSED] Buffer object in system domain with an existing page vector
[23:49:59] ====== [PASSED] ttm_bo_validate_no_placement_signaled ======
[23:49:59] ======== ttm_bo_validate_no_placement_not_signaled  ========
[23:49:59] [PASSED] Buffer object for userspace
[23:49:59] [PASSED] Kernel buffer object
[23:49:59] [PASSED] Shared buffer object
[23:49:59] ==== [PASSED] ttm_bo_validate_no_placement_not_signaled ====
[23:49:59] [PASSED] ttm_bo_validate_move_fence_signaled
[23:49:59] ========= ttm_bo_validate_move_fence_not_signaled  =========
[23:49:59] [PASSED] Waits for GPU
[23:49:59] [PASSED] Tries to lock straight away
[23:49:59] ===== [PASSED] ttm_bo_validate_move_fence_not_signaled =====
[23:49:59] [PASSED] ttm_bo_validate_swapout
[23:49:59] [PASSED] ttm_bo_validate_happy_evict
[23:49:59] [PASSED] ttm_bo_validate_all_pinned_evict
[23:49:59] [PASSED] ttm_bo_validate_allowed_only_evict
[23:49:59] [PASSED] ttm_bo_validate_deleted_evict
[23:49:59] [PASSED] ttm_bo_validate_busy_domain_evict
[23:49:59] [PASSED] ttm_bo_validate_evict_gutting
[23:49:59] [PASSED] ttm_bo_validate_recrusive_evict
[23:49:59] ================= [PASSED] ttm_bo_validate =================
[23:49:59] ============================================================
[23:49:59] Testing complete. Ran 102 tests: passed: 102
[23:49:59] Elapsed time: 11.971s total, 1.797s configuring, 9.959s building, 0.178s running

+ /kernel/tools/testing/kunit/kunit.py run --kunitconfig /kernel/drivers/dma-buf/.kunitconfig
[23:49:59] Configuring KUnit Kernel ...
Regenerating .config ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
[23:50:01] Building KUnit Kernel ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
Building with:
$ make all compile_commands.json scripts_gdb ARCH=um O=.kunit --jobs=48
[23:50:10] Starting KUnit Kernel (1/1)...
[23:50:10] ============================================================
Running tests with:
$ .kunit/linux kunit.enable=1 mem=1G console=tty kunit_shutdown=halt
[23:50:10] =============== dma-buf-fence (12 subtests) ================
[23:50:10] [PASSED] test_sanitycheck
[23:50:10] [PASSED] test_signaling
[23:50:10] [PASSED] test_add_callback
[23:50:10] [PASSED] test_late_add_callback
[23:50:10] [PASSED] test_rm_callback
[23:50:10] [PASSED] test_late_rm_callback
[23:50:10] [PASSED] test_status
[23:50:10] [PASSED] test_error
[23:50:10] [PASSED] test_wait
[23:50:10] [PASSED] test_wait_timeout
[23:50:10] [PASSED] test_stub
[23:50:10] [SKIPPED] test_race_signal_callback (requires at least 2 CPUs)
[23:50:10] ================== [PASSED] dma-buf-fence ==================
[23:50:10] ============ dma-buf-fence-chain (11 subtests) =============
[23:50:10] [PASSED] test_sanitycheck
[23:50:10] [PASSED] test_find_seqno
[23:50:10] [PASSED] test_find_signaled
[23:50:10] [PASSED] test_find_out_of_order
[23:50:15] [PASSED] test_find_gap
[23:50:15] [PASSED] test_find_race
[23:50:15] [PASSED] test_signal_forward
[23:50:15] [PASSED] test_signal_backward
[23:50:15] [PASSED] test_wait_forward
[23:50:15] [PASSED] test_wait_backward
[23:50:15] [PASSED] test_wait_random
[23:50:15] =============== [PASSED] dma-buf-fence-chain ===============
[23:50:15] ============ dma-buf-fence-unwrap (10 subtests) ============
[23:50:15] [PASSED] test_sanitycheck
[23:50:15] [PASSED] test_unwrap_array
[23:50:15] [PASSED] test_unwrap_chain
[23:50:15] [PASSED] test_unwrap_chain_array
[23:50:15] [PASSED] test_unwrap_merge
[23:50:15] [PASSED] test_unwrap_merge_duplicate
[23:50:15] [PASSED] test_unwrap_merge_seqno
[23:50:15] [PASSED] test_unwrap_merge_order
[23:50:15] [PASSED] test_unwrap_merge_complex
[23:50:15] [PASSED] test_unwrap_merge_complex_seqno
[23:50:15] ============== [PASSED] dma-buf-fence-unwrap ===============
[23:50:15] ================ dma-buf-resv (5 subtests) =================
[23:50:15] [PASSED] test_sanitycheck
[23:50:15] ===================== test_signaling  ======================
[23:50:15] [PASSED] kernel
[23:50:15] [PASSED] write
[23:50:15] [PASSED] read
[23:50:15] [PASSED] bookkeep
[23:50:15] ================= [PASSED] test_signaling ==================
[23:50:15] ====================== test_for_each  ======================
[23:50:15] [PASSED] kernel
[23:50:15] [PASSED] write
[23:50:15] [PASSED] read
[23:50:15] [PASSED] bookkeep
[23:50:15] ================== [PASSED] test_for_each ==================
[23:50:15] ================= test_for_each_unlocked  ==================
[23:50:15] [PASSED] kernel
[23:50:15] [PASSED] write
[23:50:15] [PASSED] read
[23:50:15] [PASSED] bookkeep
[23:50:15] ============= [PASSED] test_for_each_unlocked ==============
[23:50:15] ===================== test_get_fences  =====================
[23:50:15] [PASSED] kernel
[23:50:15] [PASSED] write
[23:50:15] [PASSED] read
[23:50:15] [PASSED] bookkeep
[23:50:15] ================= [PASSED] test_get_fences =================
[23:50:15] ================== [PASSED] dma-buf-resv ===================
[23:50:15] ============================================================
[23:50:15] Testing complete. Ran 50 tests: passed: 49, skipped: 1
[23:50:15] Elapsed time: 15.781s total, 1.794s configuring, 8.615s building, 5.355s running

+ cleanup
++ stat -c %u:%g /kernel
+ chown -R 1003:1003 /kernel

✓ Xe.CI.BAT: success for drm/xe: Capture additional HW register state in devcoredump (rev2)

[Patchwork]

[-- Attachment #1: Type: text/plain, Size: 883 bytes --]

== Series Details ==

Series: drm/xe: Capture additional HW register state in devcoredump (rev2)
URL   : https://patchwork.freedesktop.org/series/172150/
State : success

== Summary ==

CI Bug Log - changes from xe-5642-15e2ba2fb6d25c03d89519aec46f8d5be3e118ad_BAT -> xe-pw-172150v2_BAT
====================================================

Summary
-------

  **SUCCESS**

  No regressions found.

  

Participating hosts (13 -> 12)
------------------------------

  Missing    (1): bat-nvls-1 


Changes
-------

  No changes found


Build changes
-------------

  * Linux: xe-5642-15e2ba2fb6d25c03d89519aec46f8d5be3e118ad -> xe-pw-172150v2

  IGT_9071: 9071
  xe-5642-15e2ba2fb6d25c03d89519aec46f8d5be3e118ad: 15e2ba2fb6d25c03d89519aec46f8d5be3e118ad
  xe-pw-172150v2: 172150v2

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-172150v2/index.html

[-- Attachment #2: Type: text/html, Size: 1431 bytes --]

✗ Xe.CI.FULL: failure for drm/xe: Capture additional HW register state in devcoredump (rev2)

[Patchwork]

[-- Attachment #1: Type: text/plain, Size: 21767 bytes --]

== Series Details ==

Series: drm/xe: Capture additional HW register state in devcoredump (rev2)
URL   : https://patchwork.freedesktop.org/series/172150/
State : failure

== Summary ==

CI Bug Log - changes from xe-5642-15e2ba2fb6d25c03d89519aec46f8d5be3e118ad_FULL -> xe-pw-172150v2_FULL
====================================================

Summary
-------

  **FAILURE**

  Serious unknown changes coming with xe-pw-172150v2_FULL absolutely need to be
  verified manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in xe-pw-172150v2_FULL, please notify your bug team (I915-ci-infra@lists.freedesktop.org) to allow them
  to document this new failure mode, which will reduce false positives in CI.

  

Participating hosts (2 -> 2)
------------------------------

  No changes in participating hosts

Possible new issues
-------------------

  Here are the unknown changes that may have been introduced in xe-pw-172150v2_FULL:

### IGT changes ###

#### Possible regressions ####

  * igt@xe_exec_capture@reset:
    - shard-lnl:          [PASS][1] -> [FAIL][2]
   [1]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5642-15e2ba2fb6d25c03d89519aec46f8d5be3e118ad/shard-lnl-8/igt@xe_exec_capture@reset.html
   [2]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-172150v2/shard-lnl-4/igt@xe_exec_capture@reset.html
    - shard-bmg:          [PASS][3] -> [FAIL][4]
   [3]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5642-15e2ba2fb6d25c03d89519aec46f8d5be3e118ad/shard-bmg-2/igt@xe_exec_capture@reset.html
   [4]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-172150v2/shard-bmg-9/igt@xe_exec_capture@reset.html

  
Known issues
------------

  Here are the changes found in xe-pw-172150v2_FULL that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@kms_addfb_basic@addfb25-y-tiled-small-legacy:
    - shard-bmg:          NOTRUN -> [SKIP][5] ([Intel XE#2233])
   [5]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-172150v2/shard-bmg-10/igt@kms_addfb_basic@addfb25-y-tiled-small-legacy.html

  * igt@kms_big_fb@linear-32bpp-rotate-270:
    - shard-bmg:          NOTRUN -> [SKIP][6] ([Intel XE#2327])
   [6]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-172150v2/shard-bmg-10/igt@kms_big_fb@linear-32bpp-rotate-270.html

  * igt@kms_big_fb@y-tiled-max-hw-stride-32bpp-rotate-180-async-flip:
    - shard-bmg:          NOTRUN -> [SKIP][7] ([Intel XE#1124]) +3 other tests skip
   [7]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-172150v2/shard-bmg-8/igt@kms_big_fb@y-tiled-max-hw-stride-32bpp-rotate-180-async-flip.html

  * igt@kms_bw@linear-tiling-2-displays-target-3840x2160p:
    - shard-bmg:          NOTRUN -> [SKIP][8] ([Intel XE#367])
   [8]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-172150v2/shard-bmg-4/igt@kms_bw@linear-tiling-2-displays-target-3840x2160p.html

  * igt@kms_ccs@bad-pixel-format-4-tiled-mtl-rc-ccs-cc:
    - shard-bmg:          NOTRUN -> [SKIP][9] ([Intel XE#2887]) +6 other tests skip
   [9]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-172150v2/shard-bmg-10/igt@kms_ccs@bad-pixel-format-4-tiled-mtl-rc-ccs-cc.html

  * igt@kms_cdclk@plane-scaling:
    - shard-bmg:          NOTRUN -> [SKIP][10] ([Intel XE#2724] / [Intel XE#7449])
   [10]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-172150v2/shard-bmg-10/igt@kms_cdclk@plane-scaling.html

  * igt@kms_chamelium_color@ctm-red-to-blue:
    - shard-bmg:          NOTRUN -> [SKIP][11] ([Intel XE#2325] / [Intel XE#7358])
   [11]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-172150v2/shard-bmg-10/igt@kms_chamelium_color@ctm-red-to-blue.html

  * igt@kms_chamelium_hpd@hdmi-hpd-storm-disable:
    - shard-bmg:          NOTRUN -> [SKIP][12] ([Intel XE#2252]) +2 other tests skip
   [12]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-172150v2/shard-bmg-10/igt@kms_chamelium_hpd@hdmi-hpd-storm-disable.html

  * igt@kms_cursor_crc@cursor-offscreen-512x170:
    - shard-bmg:          NOTRUN -> [SKIP][13] ([Intel XE#2321] / [Intel XE#7355])
   [13]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-172150v2/shard-bmg-8/igt@kms_cursor_crc@cursor-offscreen-512x170.html

  * igt@kms_cursor_crc@cursor-offscreen-max-size:
    - shard-bmg:          NOTRUN -> [SKIP][14] ([Intel XE#2320]) +3 other tests skip
   [14]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-172150v2/shard-bmg-10/igt@kms_cursor_crc@cursor-offscreen-max-size.html

  * igt@kms_dsc@dsc-fractional-bpp-with-bpc:
    - shard-bmg:          NOTRUN -> [SKIP][15] ([Intel XE#8265]) +1 other test skip
   [15]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-172150v2/shard-bmg-10/igt@kms_dsc@dsc-fractional-bpp-with-bpc.html

  * igt@kms_feature_discovery@display-4x:
    - shard-bmg:          NOTRUN -> [SKIP][16] ([Intel XE#1138] / [Intel XE#7344])
   [16]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-172150v2/shard-bmg-4/igt@kms_feature_discovery@display-4x.html

  * igt@kms_flip@flip-vs-expired-vblank@b-edp1:
    - shard-lnl:          [PASS][17] -> [FAIL][18] ([Intel XE#301]) +1 other test fail
   [17]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5642-15e2ba2fb6d25c03d89519aec46f8d5be3e118ad/shard-lnl-6/igt@kms_flip@flip-vs-expired-vblank@b-edp1.html
   [18]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-172150v2/shard-lnl-6/igt@kms_flip@flip-vs-expired-vblank@b-edp1.html

  * igt@kms_flip_scaled_crc@flip-32bpp-4tile-to-32bpp-4tiledg2rcccs-upscaling:
    - shard-bmg:          NOTRUN -> [SKIP][19] ([Intel XE#7178] / [Intel XE#7349]) +1 other test skip
   [19]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-172150v2/shard-bmg-8/igt@kms_flip_scaled_crc@flip-32bpp-4tile-to-32bpp-4tiledg2rcccs-upscaling.html

  * igt@kms_frontbuffer_tracking@drrs-2p-pri-indfb-multidraw:
    - shard-bmg:          NOTRUN -> [SKIP][20] ([Intel XE#2311]) +18 other tests skip
   [20]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-172150v2/shard-bmg-8/igt@kms_frontbuffer_tracking@drrs-2p-pri-indfb-multidraw.html

  * igt@kms_frontbuffer_tracking@fbc-1p-offscreen-pri-indfb-draw-render:
    - shard-bmg:          NOTRUN -> [SKIP][21] ([Intel XE#4141]) +3 other tests skip
   [21]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-172150v2/shard-bmg-8/igt@kms_frontbuffer_tracking@fbc-1p-offscreen-pri-indfb-draw-render.html

  * igt@kms_frontbuffer_tracking@fbchdr-abgr161616f-draw-render:
    - shard-bmg:          NOTRUN -> [SKIP][22] ([Intel XE#7061])
   [22]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-172150v2/shard-bmg-4/igt@kms_frontbuffer_tracking@fbchdr-abgr161616f-draw-render.html

  * igt@kms_frontbuffer_tracking@fbcpsr-abgr161616f-draw-blt:
    - shard-bmg:          NOTRUN -> [SKIP][23] ([Intel XE#7061] / [Intel XE#7356]) +2 other tests skip
   [23]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-172150v2/shard-bmg-10/igt@kms_frontbuffer_tracking@fbcpsr-abgr161616f-draw-blt.html

  * igt@kms_frontbuffer_tracking@psrhdr-2p-primscrn-cur-indfb-draw-mmap-wc:
    - shard-bmg:          NOTRUN -> [SKIP][24] ([Intel XE#2313]) +24 other tests skip
   [24]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-172150v2/shard-bmg-10/igt@kms_frontbuffer_tracking@psrhdr-2p-primscrn-cur-indfb-draw-mmap-wc.html

  * igt@kms_joiner@basic-ultra-joiner:
    - shard-bmg:          NOTRUN -> [SKIP][25] ([Intel XE#6911] / [Intel XE#7378])
   [25]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-172150v2/shard-bmg-10/igt@kms_joiner@basic-ultra-joiner.html

  * igt@kms_plane@pixel-format-y-tiled-modifier:
    - shard-bmg:          NOTRUN -> [SKIP][26] ([Intel XE#7283])
   [26]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-172150v2/shard-bmg-8/igt@kms_plane@pixel-format-y-tiled-modifier.html

  * igt@kms_plane_lowres@tiling-yf:
    - shard-bmg:          NOTRUN -> [SKIP][27] ([Intel XE#2393])
   [27]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-172150v2/shard-bmg-10/igt@kms_plane_lowres@tiling-yf.html

  * igt@kms_plane_multiple@tiling-y:
    - shard-bmg:          NOTRUN -> [SKIP][28] ([Intel XE#5020] / [Intel XE#7348])
   [28]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-172150v2/shard-bmg-8/igt@kms_plane_multiple@tiling-y.html

  * igt@kms_plane_scaling@planes-upscale-factor-0-25-downscale-factor-0-75:
    - shard-bmg:          NOTRUN -> [SKIP][29] ([Intel XE#2763] / [Intel XE#6886]) +4 other tests skip
   [29]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-172150v2/shard-bmg-4/igt@kms_plane_scaling@planes-upscale-factor-0-25-downscale-factor-0-75.html

  * igt@kms_pm_backlight@fade-with-dpms:
    - shard-bmg:          NOTRUN -> [SKIP][30] ([Intel XE#7376] / [Intel XE#7760] / [Intel XE#870])
   [30]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-172150v2/shard-bmg-10/igt@kms_pm_backlight@fade-with-dpms.html

  * igt@kms_pm_dc@dc5-pageflip-negative:
    - shard-bmg:          NOTRUN -> [SKIP][31] ([Intel XE#6927])
   [31]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-172150v2/shard-bmg-10/igt@kms_pm_dc@dc5-pageflip-negative.html

  * igt@kms_pm_rpm@package-g7:
    - shard-bmg:          NOTRUN -> [SKIP][32] ([Intel XE#6814] / [Intel XE#7428])
   [32]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-172150v2/shard-bmg-10/igt@kms_pm_rpm@package-g7.html

  * igt@kms_psr2_sf@psr2-cursor-plane-move-continuous-exceed-fully-sf:
    - shard-bmg:          NOTRUN -> [SKIP][33] ([Intel XE#1489]) +2 other tests skip
   [33]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-172150v2/shard-bmg-8/igt@kms_psr2_sf@psr2-cursor-plane-move-continuous-exceed-fully-sf.html

  * igt@kms_psr@psr-sprite-plane-move:
    - shard-bmg:          NOTRUN -> [SKIP][34] ([Intel XE#2234] / [Intel XE#2850]) +5 other tests skip
   [34]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-172150v2/shard-bmg-4/igt@kms_psr@psr-sprite-plane-move.html

  * igt@kms_sharpness_filter@filter-scaler-downscale:
    - shard-bmg:          NOTRUN -> [SKIP][35] ([Intel XE#6503])
   [35]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-172150v2/shard-bmg-10/igt@kms_sharpness_filter@filter-scaler-downscale.html

  * igt@kms_vrr@flip-suspend:
    - shard-bmg:          NOTRUN -> [SKIP][36] ([Intel XE#1499]) +1 other test skip
   [36]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-172150v2/shard-bmg-10/igt@kms_vrr@flip-suspend.html

  * igt@xe_evict@evict-small-multi-queue-cm:
    - shard-bmg:          NOTRUN -> [SKIP][37] ([Intel XE#8370])
   [37]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-172150v2/shard-bmg-8/igt@xe_evict@evict-small-multi-queue-cm.html

  * igt@xe_exec_basic@multigpu-once-bindexecqueue-userptr-invalidate:
    - shard-bmg:          NOTRUN -> [SKIP][38] ([Intel XE#2322] / [Intel XE#7372]) +2 other tests skip
   [38]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-172150v2/shard-bmg-10/igt@xe_exec_basic@multigpu-once-bindexecqueue-userptr-invalidate.html

  * igt@xe_exec_fault_mode@once-multi-queue-userptr-rebind-imm:
    - shard-bmg:          NOTRUN -> [SKIP][39] ([Intel XE#8374]) +4 other tests skip
   [39]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-172150v2/shard-bmg-10/igt@xe_exec_fault_mode@once-multi-queue-userptr-rebind-imm.html

  * igt@xe_exec_multi_queue@few-execs-preempt-mode-fault-basic:
    - shard-bmg:          NOTRUN -> [SKIP][40] ([Intel XE#8364]) +13 other tests skip
   [40]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-172150v2/shard-bmg-4/igt@xe_exec_multi_queue@few-execs-preempt-mode-fault-basic.html

  * igt@xe_exec_threads@threads-multi-queue-cm-fd-userptr:
    - shard-bmg:          NOTRUN -> [SKIP][41] ([Intel XE#8378]) +2 other tests skip
   [41]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-172150v2/shard-bmg-4/igt@xe_exec_threads@threads-multi-queue-cm-fd-userptr.html

  * igt@xe_live_ktest@xe_bo@xe_ccs_migrate_kunit:
    - shard-bmg:          NOTRUN -> [SKIP][42] ([Intel XE#2229])
   [42]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-172150v2/shard-bmg-10/igt@xe_live_ktest@xe_bo@xe_ccs_migrate_kunit.html

  * igt@xe_live_ktest@xe_eudebug:
    - shard-bmg:          NOTRUN -> [SKIP][43] ([Intel XE#2833])
   [43]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-172150v2/shard-bmg-8/igt@xe_live_ktest@xe_eudebug.html

  * igt@xe_multigpu_svm@mgpu-concurrent-access-basic:
    - shard-bmg:          NOTRUN -> [SKIP][44] ([Intel XE#6964])
   [44]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-172150v2/shard-bmg-10/igt@xe_multigpu_svm@mgpu-concurrent-access-basic.html

  * igt@xe_page_reclaim@prl-invalidate-full:
    - shard-bmg:          NOTRUN -> [SKIP][45] ([Intel XE#7793])
   [45]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-172150v2/shard-bmg-4/igt@xe_page_reclaim@prl-invalidate-full.html

  * igt@xe_pat@l2-flush-opt-svm-pat-restrict:
    - shard-bmg:          NOTRUN -> [SKIP][46] ([Intel XE#7590])
   [46]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-172150v2/shard-bmg-10/igt@xe_pat@l2-flush-opt-svm-pat-restrict.html

  * igt@xe_pat@pat-index-xelp:
    - shard-bmg:          NOTRUN -> [SKIP][47] ([Intel XE#2245] / [Intel XE#7590])
   [47]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-172150v2/shard-bmg-10/igt@xe_pat@pat-index-xelp.html

  * igt@xe_pm@d3cold-mocs:
    - shard-bmg:          NOTRUN -> [SKIP][48] ([Intel XE#2284] / [Intel XE#7370])
   [48]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-172150v2/shard-bmg-4/igt@xe_pm@d3cold-mocs.html

  * igt@xe_pxp@pxp-stale-bo-exec-post-rpm:
    - shard-bmg:          NOTRUN -> [SKIP][49] ([Intel XE#4733] / [Intel XE#7417])
   [49]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-172150v2/shard-bmg-4/igt@xe_pxp@pxp-stale-bo-exec-post-rpm.html

  * igt@xe_query@multigpu-query-invalid-extension:
    - shard-bmg:          NOTRUN -> [SKIP][50] ([Intel XE#944]) +1 other test skip
   [50]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-172150v2/shard-bmg-8/igt@xe_query@multigpu-query-invalid-extension.html

  
#### Possible fixes ####

  * igt@core_hotunplug@hotrebind-with-load:
    - shard-bmg:          [ABORT][51] ([Intel XE#8007]) -> [PASS][52] +1 other test pass
   [51]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5642-15e2ba2fb6d25c03d89519aec46f8d5be3e118ad/shard-bmg-1/igt@core_hotunplug@hotrebind-with-load.html
   [52]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-172150v2/shard-bmg-4/igt@core_hotunplug@hotrebind-with-load.html

  * igt@kms_ccs@crc-primary-suspend-4-tiled-bmg-ccs:
    - shard-bmg:          [INCOMPLETE][53] ([Intel XE#7084] / [Intel XE#8150]) -> [PASS][54] +1 other test pass
   [53]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5642-15e2ba2fb6d25c03d89519aec46f8d5be3e118ad/shard-bmg-9/igt@kms_ccs@crc-primary-suspend-4-tiled-bmg-ccs.html
   [54]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-172150v2/shard-bmg-8/igt@kms_ccs@crc-primary-suspend-4-tiled-bmg-ccs.html

  * igt@kms_flip@flip-vs-expired-vblank-interruptible@b-edp1:
    - shard-lnl:          [FAIL][55] ([Intel XE#301]) -> [PASS][56]
   [55]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5642-15e2ba2fb6d25c03d89519aec46f8d5be3e118ad/shard-lnl-3/igt@kms_flip@flip-vs-expired-vblank-interruptible@b-edp1.html
   [56]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-172150v2/shard-lnl-7/igt@kms_flip@flip-vs-expired-vblank-interruptible@b-edp1.html

  * igt@kms_flip@flip-vs-expired-vblank@c-edp1:
    - shard-lnl:          [FAIL][57] ([Intel XE#301] / [Intel XE#3149]) -> [PASS][58] +1 other test pass
   [57]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5642-15e2ba2fb6d25c03d89519aec46f8d5be3e118ad/shard-lnl-6/igt@kms_flip@flip-vs-expired-vblank@c-edp1.html
   [58]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-172150v2/shard-lnl-6/igt@kms_flip@flip-vs-expired-vblank@c-edp1.html

  * igt@kms_flip@modeset-vs-vblank-race-interruptible:
    - shard-bmg:          [FAIL][59] ([Intel XE#3098]) -> [PASS][60] +1 other test pass
   [59]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5642-15e2ba2fb6d25c03d89519aec46f8d5be3e118ad/shard-bmg-2/igt@kms_flip@modeset-vs-vblank-race-interruptible.html
   [60]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-172150v2/shard-bmg-9/igt@kms_flip@modeset-vs-vblank-race-interruptible.html

  
#### Warnings ####

  * igt@kms_flip@flip-vs-expired-vblank-interruptible:
    - shard-lnl:          [FAIL][61] ([Intel XE#301] / [Intel XE#3149]) -> [FAIL][62] ([Intel XE#301]) +1 other test fail
   [61]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5642-15e2ba2fb6d25c03d89519aec46f8d5be3e118ad/shard-lnl-3/igt@kms_flip@flip-vs-expired-vblank-interruptible.html
   [62]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-172150v2/shard-lnl-7/igt@kms_flip@flip-vs-expired-vblank-interruptible.html

  
  [Intel XE#1124]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1124
  [Intel XE#1138]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1138
  [Intel XE#1489]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1489
  [Intel XE#1499]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1499
  [Intel XE#2229]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2229
  [Intel XE#2233]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2233
  [Intel XE#2234]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2234
  [Intel XE#2245]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2245
  [Intel XE#2252]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2252
  [Intel XE#2284]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2284
  [Intel XE#2311]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2311
  [Intel XE#2313]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2313
  [Intel XE#2320]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2320
  [Intel XE#2321]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2321
  [Intel XE#2322]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2322
  [Intel XE#2325]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2325
  [Intel XE#2327]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2327
  [Intel XE#2393]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2393
  [Intel XE#2724]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2724
  [Intel XE#2763]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2763
  [Intel XE#2833]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2833
  [Intel XE#2850]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2850
  [Intel XE#2887]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2887
  [Intel XE#301]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/301
  [Intel XE#3098]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3098
  [Intel XE#3149]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3149
  [Intel XE#367]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/367
  [Intel XE#4141]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4141
  [Intel XE#4733]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4733
  [Intel XE#5020]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5020
  [Intel XE#6503]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6503
  [Intel XE#6814]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6814
  [Intel XE#6886]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6886
  [Intel XE#6911]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6911
  [Intel XE#6927]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6927
  [Intel XE#6964]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6964
  [Intel XE#7061]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7061
  [Intel XE#7084]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7084
  [Intel XE#7178]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7178
  [Intel XE#7283]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7283
  [Intel XE#7344]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7344
  [Intel XE#7348]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7348
  [Intel XE#7349]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7349
  [Intel XE#7355]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7355
  [Intel XE#7356]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7356
  [Intel XE#7358]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7358
  [Intel XE#7370]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7370
  [Intel XE#7372]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7372
  [Intel XE#7376]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7376
  [Intel XE#7378]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7378
  [Intel XE#7417]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7417
  [Intel XE#7428]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7428
  [Intel XE#7449]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7449
  [Intel XE#7590]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7590
  [Intel XE#7760]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7760
  [Intel XE#7793]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7793
  [Intel XE#8007]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/8007
  [Intel XE#8150]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/8150
  [Intel XE#8265]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/8265
  [Intel XE#8364]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/8364
  [Intel XE#8370]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/8370
  [Intel XE#8374]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/8374
  [Intel XE#8378]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/8378
  [Intel XE#870]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/870
  [Intel XE#944]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/944


Build changes
-------------

  * Linux: xe-5642-15e2ba2fb6d25c03d89519aec46f8d5be3e118ad -> xe-pw-172150v2

  IGT_9071: 9071
  xe-5642-15e2ba2fb6d25c03d89519aec46f8d5be3e118ad: 15e2ba2fb6d25c03d89519aec46f8d5be3e118ad
  xe-pw-172150v2: 172150v2

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-172150v2/index.html

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