[PATCH v5 00/15] Enable DP2.1 alpm

[PATCH v5 00/15] Enable DP2.1 alpm

[Animesh Manna]

ALPM support added on DP2.1 and xe3p will support DP2.1 alpm.
This patch series extending alpm supoort for DP2.1.

Cc: Jouni Högander <jouni.hogander@intel.com>
Signed-off-by: Animesh Manna <animesh.manna@intel.com>

Animesh Manna (15):
  drm/i915/alpm: Add DPCD definition for DP2.1 ALPM capability
  drm/i915/alpm: Move alpm sink capabality readout in separate function
  drm/i915/alpm: alpm_init() for DP2.1
  drm/i915/alpm: Enable debugfs for DP2.1
  drm/i915/alpm: Refactor Auxless wake time calculation
  drm/i915/alpm: Auxless wake time calculation for Xe3p
  drm/i915/alpm: table based establishment period
  drm/i915/alpm: Half LFPS cycle calculation
  drm/i915/alpm: Modify LFPS cycle count for DP ALPM
  drm/i915/alpm: Program LTTPR count for DP 2.1 ALPM
  drm/i915/alpm: Enable MAC Transmitting LFPS for LT PHY
  drm/i915/alpm: Replace is_edp() with alpm_is_possible()
  drm/i915/alpm: Introduce has_alpm to decouple from pr/psr2/lobf
  drm/i915/alpm: Compute and program switch to active latency
  drm/i915/alpm: Program zero-based LFPS half cycle duration

 drivers/gpu/drm/i915/display/intel_alpm.c     | 324 +++++++++++++++---
 drivers/gpu/drm/i915/display/intel_alpm.h     |   5 +-
 drivers/gpu/drm/i915/display/intel_cx0_phy.c  |   6 +-
 drivers/gpu/drm/i915/display/intel_ddi.c      |   5 +-
 .../drm/i915/display/intel_display_types.h    |   2 +
 drivers/gpu/drm/i915/display/intel_dp.c       |  15 +-
 .../drm/i915/display/intel_dp_link_training.c |  16 +
 drivers/gpu/drm/i915/display/intel_lt_phy.c   |  27 ++
 drivers/gpu/drm/i915/display/intel_lt_phy.h   |   2 +
 .../gpu/drm/i915/display/intel_lt_phy_regs.h  |   3 +
 drivers/gpu/drm/i915/display/intel_psr.c      |  39 +--
 drivers/gpu/drm/i915/display/intel_psr.h      |   1 -
 drivers/gpu/drm/i915/display/intel_psr_regs.h |   4 +
 include/drm/display/drm_dp.h                  |   4 +-
 14 files changed, 375 insertions(+), 78 deletions(-)

-- 
2.29.0

[PATCH v5 01/15] drm/i915/alpm: Add DPCD definition for DP2.1 ALPM capability

[Animesh Manna]

Add required DPCD address which will be needed to enable DP2.1 ALPM.

Cc: Jouni Högander <jouni.hogander@intel.com>
Reviewed-by: Suraj Kandpal <suraj.kandpal@intel.com>
Signed-off-by: Animesh Manna <animesh.manna@intel.com>
---
 include/drm/display/drm_dp.h | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/include/drm/display/drm_dp.h b/include/drm/display/drm_dp.h
index e63c7f075f54..9f1e9ef5cdb6 100644
--- a/include/drm/display/drm_dp.h
+++ b/include/drm/display/drm_dp.h
@@ -1541,6 +1541,8 @@
 /* See DP_128B132B_SUPPORTED_LINK_RATES for values */
 #define DP_PHY_REPEATER_128B132B_RATES			    0xf0007 /* 2.0 */
 #define DP_PHY_REPEATER_EQ_DONE                             0xf0008 /* 2.0 E11 */
+#define DP_LTTPR_ALPM_CAPABILITIES                          0xf0009 /* 2.1 */
+#define DP_TOTAL_LTTPR_CNT                                  0xf000a /* 2.1 */
 
 enum drm_dp_phy {
 	DP_PHY_DPRX,
@@ -1720,7 +1722,7 @@ enum drm_dp_phy {
 #define DP_DSC_BRANCH_CAP_SIZE		3
 #define EDP_PSR_RECEIVER_CAP_SIZE	2
 #define EDP_DISPLAY_CTL_CAP_SIZE	5
-#define DP_LTTPR_COMMON_CAP_SIZE	8
+#define DP_LTTPR_COMMON_CAP_SIZE	10
 #define DP_LTTPR_PHY_CAP_SIZE		3
 
 #define DP_SDP_AUDIO_TIMESTAMP		0x01
-- 
2.29.0

RE: [PATCH v5 01/15] drm/i915/alpm: Add DPCD definition for DP2.1 ALPM capability

[Kandpal, Suraj]

> Subject: [PATCH v5 01/15] drm/i915/alpm: Add DPCD definition for DP2.1 ALPM
> capability
> 
> Add required DPCD address which will be needed to enable DP2.1 ALPM.
> 
> Cc: Jouni Högander <jouni.hogander@intel.com>
> Reviewed-by: Suraj Kandpal <suraj.kandpal@intel.com>
> Signed-off-by: Animesh Manna <animesh.manna@intel.com>

FYI,
Needs to be sent to dri-devel too

Regards,
Suraj Kandpal

> ---
>  include/drm/display/drm_dp.h | 4 +++-
>  1 file changed, 3 insertions(+), 1 deletion(-)
> 
> diff --git a/include/drm/display/drm_dp.h b/include/drm/display/drm_dp.h
> index e63c7f075f54..9f1e9ef5cdb6 100644
> --- a/include/drm/display/drm_dp.h
> +++ b/include/drm/display/drm_dp.h
> @@ -1541,6 +1541,8 @@
>  /* See DP_128B132B_SUPPORTED_LINK_RATES for values */
>  #define DP_PHY_REPEATER_128B132B_RATES			    0xf0007 /*
> 2.0 */
>  #define DP_PHY_REPEATER_EQ_DONE                             0xf0008 /* 2.0 E11 */
> +#define DP_LTTPR_ALPM_CAPABILITIES                          0xf0009 /* 2.1 */
> +#define DP_TOTAL_LTTPR_CNT                                  0xf000a /* 2.1 */
> 
>  enum drm_dp_phy {
>  	DP_PHY_DPRX,
> @@ -1720,7 +1722,7 @@ enum drm_dp_phy {
>  #define DP_DSC_BRANCH_CAP_SIZE		3
>  #define EDP_PSR_RECEIVER_CAP_SIZE	2
>  #define EDP_DISPLAY_CTL_CAP_SIZE	5
> -#define DP_LTTPR_COMMON_CAP_SIZE	8
> +#define DP_LTTPR_COMMON_CAP_SIZE	10
>  #define DP_LTTPR_PHY_CAP_SIZE		3
> 
>  #define DP_SDP_AUDIO_TIMESTAMP		0x01
> --
> 2.29.0

RE: [PATCH v5 01/15] drm/i915/alpm: Add DPCD definition for DP2.1 ALPM capability

[Manna, Animesh]

> -----Original Message-----
> From: Kandpal, Suraj <suraj.kandpal@intel.com>
> Sent: Tuesday, August 25, 2026 1:25 PM
> To: Manna, Animesh <animesh.manna@intel.com>; intel-
> gfx@lists.freedesktop.org; intel-xe@lists.freedesktop.org
> Cc: Hogander, Jouni <jouni.hogander@intel.com>; Nikula, Jani
> <jani.nikula@intel.com>
> Subject: RE: [PATCH v5 01/15] drm/i915/alpm: Add DPCD definition for DP2.1
> ALPM capability
> 
> > Subject: [PATCH v5 01/15] drm/i915/alpm: Add DPCD definition for DP2.1
> > ALPM capability
> >
> > Add required DPCD address which will be needed to enable DP2.1 ALPM.
> >
> > Cc: Jouni Högander <jouni.hogander@intel.com>
> > Reviewed-by: Suraj Kandpal <suraj.kandpal@intel.com>
> > Signed-off-by: Animesh Manna <animesh.manna@intel.com>
> 
> FYI,
> Needs to be sent to dri-devel too

Yes, right. Will take care in next version.

Regards,
Animesh

> 
> Regards,
> Suraj Kandpal
> 
> > ---
> >  include/drm/display/drm_dp.h | 4 +++-
> >  1 file changed, 3 insertions(+), 1 deletion(-)
> >
> > diff --git a/include/drm/display/drm_dp.h
> > b/include/drm/display/drm_dp.h index e63c7f075f54..9f1e9ef5cdb6
> 100644
> > --- a/include/drm/display/drm_dp.h
> > +++ b/include/drm/display/drm_dp.h
> > @@ -1541,6 +1541,8 @@
> >  /* See DP_128B132B_SUPPORTED_LINK_RATES for values */
> >  #define DP_PHY_REPEATER_128B132B_RATES
> 0xf0007 /*
> > 2.0 */
> >  #define DP_PHY_REPEATER_EQ_DONE                             0xf0008 /* 2.0 E11
> */
> > +#define DP_LTTPR_ALPM_CAPABILITIES                          0xf0009 /* 2.1 */
> > +#define DP_TOTAL_LTTPR_CNT                                  0xf000a /* 2.1 */
> >
> >  enum drm_dp_phy {
> >  	DP_PHY_DPRX,
> > @@ -1720,7 +1722,7 @@ enum drm_dp_phy {
> >  #define DP_DSC_BRANCH_CAP_SIZE		3
> >  #define EDP_PSR_RECEIVER_CAP_SIZE	2
> >  #define EDP_DISPLAY_CTL_CAP_SIZE	5
> > -#define DP_LTTPR_COMMON_CAP_SIZE	8
> > +#define DP_LTTPR_COMMON_CAP_SIZE	10
> >  #define DP_LTTPR_PHY_CAP_SIZE		3
> >
> >  #define DP_SDP_AUDIO_TIMESTAMP		0x01
> > --
> > 2.29.0

[PATCH v5 02/15] drm/i915/alpm: Move alpm sink capabality readout in separate function

[Animesh Manna]

Non functional change.

Signed-off-by: Animesh Manna <animesh.manna@intel.com>
---
 drivers/gpu/drm/i915/display/intel_alpm.c | 10 ++++++++++
 drivers/gpu/drm/i915/display/intel_alpm.h |  1 +
 drivers/gpu/drm/i915/display/intel_dp.c   |  7 +------
 3 files changed, 12 insertions(+), 6 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_alpm.c b/drivers/gpu/drm/i915/display/intel_alpm.c
index f1383764b702..542900e29a01 100644
--- a/drivers/gpu/drm/i915/display/intel_alpm.c
+++ b/drivers/gpu/drm/i915/display/intel_alpm.c
@@ -43,6 +43,16 @@ bool intel_alpm_is_alpm_aux_less(struct intel_dp *intel_dp,
 		(crtc_state->has_lobf && intel_alpm_aux_less_wake_supported(intel_dp));
 }
 
+void intel_alpm_init_dpcd(struct intel_dp *intel_dp)
+{
+	u8 dpcd;
+
+	if (drm_dp_dpcd_readb(&intel_dp->aux, DP_RECEIVER_ALPM_CAP, &dpcd) < 0)
+		return;
+
+	intel_dp->alpm_dpcd = dpcd;
+}
+
 void intel_alpm_init(struct intel_dp *intel_dp)
 {
 	mutex_init(&intel_dp->alpm.lock);
diff --git a/drivers/gpu/drm/i915/display/intel_alpm.h b/drivers/gpu/drm/i915/display/intel_alpm.h
index 1cf70668ab1b..fae68d557960 100644
--- a/drivers/gpu/drm/i915/display/intel_alpm.h
+++ b/drivers/gpu/drm/i915/display/intel_alpm.h
@@ -15,6 +15,7 @@ struct intel_connector;
 struct intel_atomic_state;
 struct intel_crtc;
 
+void intel_alpm_init_dpcd(struct intel_dp *intel_dp);
 void intel_alpm_init(struct intel_dp *intel_dp);
 bool intel_alpm_compute_params(struct intel_dp *intel_dp,
 			       struct intel_crtc_state *crtc_state);
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index 6b60e0a1c8ee..77d516f0bd07 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -4764,7 +4764,6 @@ static bool
 intel_edp_init_dpcd(struct intel_dp *intel_dp, struct intel_connector *connector)
 {
 	struct intel_display *display = to_intel_display(intel_dp);
-	int ret;
 
 	/* this function is meant to be called only once */
 	drm_WARN_ON(display->drm, intel_dp->dpcd[DP_DPCD_REV] != 0);
@@ -4804,11 +4803,7 @@ intel_edp_init_dpcd(struct intel_dp *intel_dp, struct intel_connector *connector
 	 */
 	intel_dp_init_source_oui(intel_dp);
 
-	/* Read the ALPM DPCD caps */
-	ret = drm_dp_dpcd_read_byte(&intel_dp->aux, DP_RECEIVER_ALPM_CAP,
-				    &intel_dp->alpm_dpcd);
-	if (ret < 0)
-		return false;
+	intel_alpm_init_dpcd(intel_dp);
 
 	/*
 	 * This has to be called after intel_dp->edp_dpcd is filled, PSR checks
-- 
2.29.0

Re: [PATCH v5 02/15] drm/i915/alpm: Move alpm sink capabality readout in separate function

[sashiko-bot]

Thank you for your contribution! Sashiko AI review found 2 potential issue(s) to consider:
- [Medium] The refactoring silently drops error propagation when reading the ALPM DPCD capability, altering eDP initialization failure behavior despite the 'Non functional change' claim.
- [Medium] The uninitialized stack variable `dpcd` can be assigned to `intel_dp->alpm_dpcd` if `drm_dp_dpcd_readb()` returns 0.
--

--- Patch [2]: [PATCH v5 02/15] drm/i915/alpm: Move alpm sink capabality readout in separate function ---
commit 7a8fa9f136849fe0967523fc134415ba1067f31f
Author: Animesh Manna <animesh.manna@intel.com>

drm/i915/alpm: Move alpm sink capabality readout in separate function

This commit refactors the ALPM sink capability readout logic into a new
standalone function, intel_alpm_init_dpcd().

> diff --git a/drivers/gpu/drm/i915/display/intel_alpm.c b/drivers/gpu/drm/i915/display/intel_alpm.c
> index f1383764b7028..542900e29a014 100644
> --- a/drivers/gpu/drm/i915/display/intel_alpm.c
> +++ b/drivers/gpu/drm/i915/display/intel_alpm.c
[ ... ]
> @@ -43,6 +43,16 @@ bool intel_alpm_is_alpm_aux_less(struct intel_dp *intel_dp,
>  		(crtc_state->has_lobf && intel_alpm_aux_less_wake_supported(intel_dp));
>  }
>  
> +void intel_alpm_init_dpcd(struct intel_dp *intel_dp)
> +{
> +	u8 dpcd;
> +
> +	if (drm_dp_dpcd_readb(&intel_dp->aux, DP_RECEIVER_ALPM_CAP, &dpcd) < 0)
> +		return;
> +
> +	intel_dp->alpm_dpcd = dpcd;

[Severity: Medium]
If drm_dp_dpcd_readb() performs a short read and returns 0, the error check
will evaluate to false. Does this result in assigning uninitialized stack 
memory from dpcd to intel_dp->alpm_dpcd?

The previous API used here (drm_dp_dpcd_read_byte) explicitly checked for
short reads and returned a negative error, which avoided this scenario.

> +}
> +
[ ... ]
> diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
> index 113d767e62e9c..bf626a1e189b1 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp.c
[ ... ]
> @@ -4810,11 +4809,7 @@ intel_edp_init_dpcd(struct intel_dp *intel_dp, struct intel_connector *connector
>  	 */
>  	intel_dp_init_source_oui(intel_dp);
>  
> -	/* Read the ALPM DPCD caps */
> -	ret = drm_dp_dpcd_read_byte(&intel_dp->aux, DP_RECEIVER_ALPM_CAP,
> -				    &intel_dp->alpm_dpcd);
> -	if (ret < 0)
> -		return false;
> +	intel_alpm_init_dpcd(intel_dp);

[Severity: Medium]
The commit message states this is a non-functional change, but the previous
code returned false and aborted eDP initialization if the AUX read failed.

Since the new intel_alpm_init_dpcd() function returns void, does this 
inadvertently swallow the error and change the initialization failure behavior
for eDP?

>  
>  	/*
>  	 * This has to be called after intel_dp->edp_dpcd is filled, PSR checks

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20260825054536.3455704-1-animesh.manna@intel.com?part=2

RE: [PATCH v5 02/15] drm/i915/alpm: Move alpm sink capabality readout in separate function

[Kandpal, Suraj]

> Subject: [PATCH v5 02/15] drm/i915/alpm: Move alpm sink capabality readout
> in separate function
> 
> Non functional change.

Please add a definition as to what the patch is doing something like "Abstract ALPM DPCD initiailization into its own function"

Regards,
Suraj Kandpal

> 
> Signed-off-by: Animesh Manna <animesh.manna@intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_alpm.c | 10 ++++++++++
> drivers/gpu/drm/i915/display/intel_alpm.h |  1 +
>  drivers/gpu/drm/i915/display/intel_dp.c   |  7 +------
>  3 files changed, 12 insertions(+), 6 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_alpm.c
> b/drivers/gpu/drm/i915/display/intel_alpm.c
> index f1383764b702..542900e29a01 100644
> --- a/drivers/gpu/drm/i915/display/intel_alpm.c
> +++ b/drivers/gpu/drm/i915/display/intel_alpm.c
> @@ -43,6 +43,16 @@ bool intel_alpm_is_alpm_aux_less(struct intel_dp
> *intel_dp,
>  		(crtc_state->has_lobf &&
> intel_alpm_aux_less_wake_supported(intel_dp));
>  }
> 
> +void intel_alpm_init_dpcd(struct intel_dp *intel_dp) {
> +	u8 dpcd;
> +
> +	if (drm_dp_dpcd_readb(&intel_dp->aux, DP_RECEIVER_ALPM_CAP,
> &dpcd) < 0)
> +		return;
> +
> +	intel_dp->alpm_dpcd = dpcd;
> +}
> +
>  void intel_alpm_init(struct intel_dp *intel_dp)  {
>  	mutex_init(&intel_dp->alpm.lock);
> diff --git a/drivers/gpu/drm/i915/display/intel_alpm.h
> b/drivers/gpu/drm/i915/display/intel_alpm.h
> index 1cf70668ab1b..fae68d557960 100644
> --- a/drivers/gpu/drm/i915/display/intel_alpm.h
> +++ b/drivers/gpu/drm/i915/display/intel_alpm.h
> @@ -15,6 +15,7 @@ struct intel_connector;  struct intel_atomic_state;  struct
> intel_crtc;
> 
> +void intel_alpm_init_dpcd(struct intel_dp *intel_dp);
>  void intel_alpm_init(struct intel_dp *intel_dp);  bool
> intel_alpm_compute_params(struct intel_dp *intel_dp,
>  			       struct intel_crtc_state *crtc_state); diff --git
> a/drivers/gpu/drm/i915/display/intel_dp.c
> b/drivers/gpu/drm/i915/display/intel_dp.c
> index 6b60e0a1c8ee..77d516f0bd07 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> @@ -4764,7 +4764,6 @@ static bool
>  intel_edp_init_dpcd(struct intel_dp *intel_dp, struct intel_connector
> *connector)  {
>  	struct intel_display *display = to_intel_display(intel_dp);
> -	int ret;
> 
>  	/* this function is meant to be called only once */
>  	drm_WARN_ON(display->drm, intel_dp->dpcd[DP_DPCD_REV] != 0);
> @@ -4804,11 +4803,7 @@ intel_edp_init_dpcd(struct intel_dp *intel_dp,
> struct intel_connector *connector
>  	 */
>  	intel_dp_init_source_oui(intel_dp);
> 
> -	/* Read the ALPM DPCD caps */
> -	ret = drm_dp_dpcd_read_byte(&intel_dp->aux,
> DP_RECEIVER_ALPM_CAP,
> -				    &intel_dp->alpm_dpcd);
> -	if (ret < 0)
> -		return false;
> +	intel_alpm_init_dpcd(intel_dp);
> 
>  	/*
>  	 * This has to be called after intel_dp->edp_dpcd is filled, PSR checks
> --
> 2.29.0

[PATCH v5 03/15] drm/i915/alpm: alpm_init() for DP2.1

[Animesh Manna]

Initialize ALPM for DP2.1 and separate out ALPM mutex-init
from alpm-init.

v2: Separate out mutex-init. [Jani]
v3: Refactor further to avoid DISPLAY_VER check in multiple places. [Jani]
V4: Cosmetic changes. [Suraj]

Cc: Jouni Högander <jouni.hogander@intel.com>
Reviewed-by: Suraj Kandpal <suraj.kandpal@intel.com>
Signed-off-by: Animesh Manna <animesh.manna@intel.com>
---
 drivers/gpu/drm/i915/display/intel_alpm.c | 13 +++++++++++++
 drivers/gpu/drm/i915/display/intel_alpm.h |  1 +
 drivers/gpu/drm/i915/display/intel_dp.c   |  8 ++++++--
 3 files changed, 20 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_alpm.c b/drivers/gpu/drm/i915/display/intel_alpm.c
index 542900e29a01..08ad77cd32f8 100644
--- a/drivers/gpu/drm/i915/display/intel_alpm.c
+++ b/drivers/gpu/drm/i915/display/intel_alpm.c
@@ -43,6 +43,19 @@ bool intel_alpm_is_alpm_aux_less(struct intel_dp *intel_dp,
 		(crtc_state->has_lobf && intel_alpm_aux_less_wake_supported(intel_dp));
 }
 
+bool intel_alpm_source_supported(struct intel_connector *connector)
+{
+	struct intel_display *display = to_intel_display(connector);
+
+	if (!((connector->base.connector_type == DRM_MODE_CONNECTOR_DisplayPort &&
+	       DISPLAY_VER(display) >= 35) ||
+	    (connector->base.connector_type == DRM_MODE_CONNECTOR_eDP &&
+	     DISPLAY_VER(display) >= 20)))
+		return false;
+
+	return true;
+}
+
 void intel_alpm_init_dpcd(struct intel_dp *intel_dp)
 {
 	u8 dpcd;
diff --git a/drivers/gpu/drm/i915/display/intel_alpm.h b/drivers/gpu/drm/i915/display/intel_alpm.h
index fae68d557960..7280865ed5f0 100644
--- a/drivers/gpu/drm/i915/display/intel_alpm.h
+++ b/drivers/gpu/drm/i915/display/intel_alpm.h
@@ -15,6 +15,7 @@ struct intel_connector;
 struct intel_atomic_state;
 struct intel_crtc;
 
+bool intel_alpm_source_supported(struct intel_connector *connector);
 void intel_alpm_init_dpcd(struct intel_dp *intel_dp);
 void intel_alpm_init(struct intel_dp *intel_dp);
 bool intel_alpm_compute_params(struct intel_dp *intel_dp,
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index 77d516f0bd07..042c6e8b8e60 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -6343,6 +6343,9 @@ intel_dp_detect(struct drm_connector *_connector,
 	if (ret == 1)
 		connector->base.epoch_counter++;
 
+	if (intel_alpm_source_supported(connector))
+		intel_alpm_init_dpcd(intel_dp);
+
 	if (!intel_dp_is_edp(intel_dp))
 		intel_psr_init_dpcd(intel_dp, connector);
 
@@ -6986,8 +6989,6 @@ static bool intel_edp_init_connector(struct intel_dp *intel_dp,
 	 */
 	intel_hpd_enable_detection(encoder);
 
-	intel_alpm_init(intel_dp);
-
 	/* Cache DPCD and EDID for edp. */
 	has_dpcd = intel_edp_init_dpcd(intel_dp, connector);
 
@@ -7202,6 +7203,9 @@ intel_dp_init_connector(struct intel_digital_port *dig_port,
 
 	intel_psr_init(intel_dp);
 
+	if (intel_alpm_source_supported(connector))
+		intel_alpm_init(intel_dp);
+
 	return true;
 
 fail:
-- 
2.29.0

Re: [PATCH v5 03/15] drm/i915/alpm: alpm_init() for DP2.1

[sashiko-bot]

Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [Medium] Stale ALPM capability retained across hotplugs due to missing state cleanup
--

--- Patch [3]: [PATCH v5 03/15] drm/i915/alpm: alpm_init() for DP2.1 ---
commit aaac88b9e7cd98f5bc53a3e1137528cc3fb4f5d2
Author: Animesh Manna <animesh.manna@intel.com>

drm/i915/alpm: alpm_init() for DP2.1

Initialize ALPM for DP2.1 and separate out ALPM mutex-init from alpm-init.

> diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
> index bf626a1e189b1..b63c19589cd21 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> @@ -6349,6 +6349,9 @@ intel_dp_detect(struct drm_connector *_connector,
>  	if (ret == 1)
>  		connector->base.epoch_counter++;
>  
> +	if (intel_alpm_source_supported(connector))
> +		intel_alpm_init_dpcd(intel_dp);
> +

[Severity: Medium]
Since this patch now initializes ALPM DPCD capabilities in the hotplug detect
path, does intel_dp->alpm_dpcd need to be cleared when a monitor is
disconnected?

Looking earlier in intel_dp_detect(), when the status is disconnected,
capabilities like DSC and panel replay are explicitly cleared:

	if (status == connector_status_disconnected) {
		intel_dp_test_reset(intel_dp);
		...
		memset(connector->dp.dsc_dpcd, 0, sizeof(connector->dp.dsc_dpcd));
		memset(connector->dp.panel_replay_caps.dpcd, 0,
		       sizeof(connector->dp.panel_replay_caps.dpcd));

If an ALPM-capable monitor is replaced with one that does not support ALPM,
and the DPCD read fails (for example, if the sink NACKs the unsupported
address), intel_alpm_init_dpcd() returns early without clearing the stale
value:

drivers/gpu/drm/i915/display/intel_alpm.c:intel_alpm_init_dpcd() {
	...
	if (drm_dp_dpcd_readb(&intel_dp->aux, DP_RECEIVER_ALPM_CAP, &dpcd) < 0)
		return;

	intel_dp->alpm_dpcd = dpcd;
}

Could this result in the driver incorrectly trying to enable ALPM on a sink
that doesn't actually support it?

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20260825054536.3455704-1-animesh.manna@intel.com?part=3

[PATCH v5 04/15] drm/i915/alpm: Enable debugfs for DP2.1

[Animesh Manna]

Enable ALPM debug info through lobf debug info.

v2: cosmetic change. [Suraj]
v3: Use common api instead of DISPLAY_VER check in multiple places. [Jani]

Cc: Jouni Högander <jouni.hogander@intel.com>
Reviewed-by: Suraj Kandpal <suraj.kandpal@intel.com>
Signed-off-by: Animesh Manna <animesh.manna@intel.com>
---
 drivers/gpu/drm/i915/display/intel_alpm.c | 4 +---
 1 file changed, 1 insertion(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_alpm.c b/drivers/gpu/drm/i915/display/intel_alpm.c
index 08ad77cd32f8..8cfcda97cf58 100644
--- a/drivers/gpu/drm/i915/display/intel_alpm.c
+++ b/drivers/gpu/drm/i915/display/intel_alpm.c
@@ -617,11 +617,9 @@ DEFINE_SIMPLE_ATTRIBUTE(i915_edp_lobf_debug_fops,
 
 void intel_alpm_lobf_debugfs_add(struct intel_connector *connector)
 {
-	struct intel_display *display = to_intel_display(connector);
 	struct dentry *root = connector->base.debugfs_entry;
 
-	if (DISPLAY_VER(display) < 20 ||
-	    connector->base.connector_type != DRM_MODE_CONNECTOR_eDP)
+	if (!intel_alpm_source_supported(connector))
 		return;
 
 	debugfs_create_file("i915_edp_lobf_debug", 0644, root,
-- 
2.29.0

Re: [PATCH v5 04/15] drm/i915/alpm: Enable debugfs for DP2.1

[sashiko-bot]

Thank you for your contribution! Sashiko AI review found 2 potential issue(s) to consider:

New issues:
- [Critical] Unconditional dereference of `connector->encoder` in ALPM debugfs operations leads to a kernel crash on inactive DP MST connectors.

Pre-existing issues:
- [High] Use-After-Free of CRTC state and unsafe hardware register access in `i915_edp_lobf_info_show`.
--

--- Patch [4]: [PATCH v5 04/15] drm/i915/alpm: Enable debugfs for DP2.1 ---
commit 92b26450255b1614cb8fb75394a055699100a23e
Author: Animesh Manna <animesh.manna@intel.com>

drm/i915/alpm: Enable debugfs for DP2.1

The commit enables ALPM debug information through LOBF debug info.
It replaces the DISPLAY_VER and DRM_MODE_CONNECTOR_eDP checks with a
common api check instead.

> diff --git a/drivers/gpu/drm/i915/display/intel_alpm.c b/drivers/gpu/drm/i915/display/intel_alpm.c
> index 08ad77cd32f8c..8cfcda97cf588 100644
> --- a/drivers/gpu/drm/i915/display/intel_alpm.c
> +++ b/drivers/gpu/drm/i915/display/intel_alpm.c
> @@ -617,11 +617,9 @@ DEFINE_SIMPLE_ATTRIBUTE(i915_edp_lobf_debug_fops,
>  
>  void intel_alpm_lobf_debugfs_add(struct intel_connector *connector)
>  {
> -	struct intel_display *display = to_intel_display(connector);
>  	struct dentry *root = connector->base.debugfs_entry;
>  
> -	if (DISPLAY_VER(display) < 20 ||
> -	    connector->base.connector_type != DRM_MODE_CONNECTOR_eDP)
> +	if (!intel_alpm_source_supported(connector))
>  		return;
>  

[Severity: Critical]
Does relaxing this condition allow debugfs files to be created for dynamic MST
connectors?

If so, could this lead to a NULL pointer dereference in
i915_edp_lobf_debug_get() and i915_edp_lobf_debug_set()?

For MST connectors, connector->encoder is NULL until a mode is set. If the
debugfs files are accessed on an inactive MST connector, the unconditional
dereference:

drivers/gpu/drm/i915/display/intel_alpm.c:i915_edp_lobf_debug_get() {
    ...
    struct intel_dp *intel_dp = enc_to_intel_dp(connector->encoder);
    ...
}

would crash the kernel.

[Severity: High]
This is a pre-existing issue, but I noticed a potential use-after-free and
unsafe hardware register access in i915_edp_lobf_info_show().

When reading the debugfs file, i915_edp_lobf_info_show() accesses
crtc->base.state and ALPM_CTL:

drivers/gpu/drm/i915/display/intel_alpm.c:i915_edp_lobf_info_show() {
    ...
    crtc_state = to_intel_crtc_state(crtc->base.state);
    cpu_transcoder = crtc_state->cpu_transcoder;
    alpm_ctl = intel_de_read(display, ALPM_CTL(display, cpu_transcoder));
    ...
}

If this is read concurrently with a non-routing atomic commit (which can swap
and free crtc->state without connection_mutex), could this result in a
use-after-free?

Additionally, is it safe to read from the ALPM_CTL register without first
checking if the CRTC is active and acquiring a display power domain wakeref?

>  	debugfs_create_file("i915_edp_lobf_debug", 0644, root,

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20260825054536.3455704-1-animesh.manna@intel.com?part=4

[PATCH v5 05/15] drm/i915/alpm: Refactor Auxless wake time calculation

[Animesh Manna]

Divide the auxless wake time calculation in parts which will
help later to add Xe3p related modification.

v2: Refactor first existing calculation. [Jani]
v3: Cosmetic changes. [Jani, Suraj]

Bspec: 71477
Cc: Jouni Högander <jouni.hogander@intel.com>
Reviewed-by: Suraj Kandpal <suraj.kandpal@intel.com>
Signed-off-by: Animesh Manna <animesh.manna@intel.com>
---
 drivers/gpu/drm/i915/display/intel_alpm.c | 31 ++++++++++++++++-------
 1 file changed, 22 insertions(+), 9 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_alpm.c b/drivers/gpu/drm/i915/display/intel_alpm.c
index 8cfcda97cf58..4b15d96d0ad7 100644
--- a/drivers/gpu/drm/i915/display/intel_alpm.c
+++ b/drivers/gpu/drm/i915/display/intel_alpm.c
@@ -105,6 +105,25 @@ static int get_lfps_half_cycle_clocks(const struct intel_crtc_state *crtc_state)
 		1000 / (2 * LFPS_CYCLE_COUNT);
 }
 
+static int get_tphy2_p2_to_p0(const struct intel_crtc_state *crtc_state)
+{
+	return 12 * 1000;
+}
+
+static int get_establishment_period(const struct intel_crtc_state *crtc_state)
+{
+	int t1 = 50 * 1000;
+	int tps4 = 252;
+	/* port_clock is link rate in 10kbit/s units */
+	int tml_phy_lock = 1000 * 1000 * tps4 / crtc_state->port_clock;
+	int tcds, establishment_period;
+
+	tcds = (7 + DIV_ROUND_UP(6500, tml_phy_lock) + 1) * tml_phy_lock;
+	establishment_period = (SILENCE_PERIOD_TIME + t1 + tcds);
+
+	return establishment_period;
+}
+
 /*
  * AUX-Less Wake Time = CEILING( ((PHY P2 to P0) + tLFPS_Period, Max+
  * tSilence, Max+ tPHY Establishment + tCDS) / tline)
@@ -126,17 +145,11 @@ static int get_lfps_half_cycle_clocks(const struct intel_crtc_state *crtc_state)
  */
 static int _lnl_compute_aux_less_wake_time(const struct intel_crtc_state *crtc_state)
 {
-	int tphy2_p2_to_p0 = 12 * 1000;
-	int t1 = 50 * 1000;
-	int tps4 = 252;
-	/* port_clock is link rate in 10kbit/s units */
-	int tml_phy_lock = 1000 * 1000 * tps4 / crtc_state->port_clock;
-	int num_ml_phy_lock = 7 + DIV_ROUND_UP(6500, tml_phy_lock) + 1;
-	int t2 = num_ml_phy_lock * tml_phy_lock;
-	int tcds = 1 * t2;
+	int tphy2_p2_to_p0 = get_tphy2_p2_to_p0(crtc_state);
+	int establishment_period = get_establishment_period(crtc_state);
 
 	return DIV_ROUND_UP(tphy2_p2_to_p0 + get_lfps_cycle_time(crtc_state) +
-			    SILENCE_PERIOD_TIME + t1 + tcds, 1000);
+			    establishment_period, 1000);
 }
 
 static int
-- 
2.29.0

[PATCH v5 06/15] drm/i915/alpm: Auxless wake time calculation for Xe3p

[Animesh Manna]

Add support for auxless waketime calculation for DP2.1 ALPM
as dependent parameter got changed.

v1: Initial version.
v2: Use intel_dp_is_uhbr(). [Jani]
v3:
- Separate out switch to active latency calculation.
- Use macro definition for ML_PHY_LOCK length. [Suraj]
- Modify AUX_LESS_WAKE_TIME bitfield for xe3lpd. [Suraj]

Bspec: 71477
Cc: Jouni Högander <jouni.hogander@intel.com>
Signed-off-by: Animesh Manna <animesh.manna@intel.com>
---
 drivers/gpu/drm/i915/display/intel_alpm.c     | 61 +++++++++++++++----
 drivers/gpu/drm/i915/display/intel_psr_regs.h |  2 +
 2 files changed, 51 insertions(+), 12 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_alpm.c b/drivers/gpu/drm/i915/display/intel_alpm.c
index 4b15d96d0ad7..af2733805505 100644
--- a/drivers/gpu/drm/i915/display/intel_alpm.c
+++ b/drivers/gpu/drm/i915/display/intel_alpm.c
@@ -105,21 +105,50 @@ static int get_lfps_half_cycle_clocks(const struct intel_crtc_state *crtc_state)
 		1000 / (2 * LFPS_CYCLE_COUNT);
 }
 
+#define ML_PHY_LOCK_LEN		252
+#define ML_PHY_LOCK_LEN_UHBR	396
+
 static int get_tphy2_p2_to_p0(const struct intel_crtc_state *crtc_state)
 {
-	return 12 * 1000;
+	struct intel_display *display = to_intel_display(crtc_state);
+
+	return DISPLAY_VER(display) >= 35 ? (20 * 1000) : (12 * 1000);
 }
 
-static int get_establishment_period(const struct intel_crtc_state *crtc_state)
+static int get_establishment_period(struct intel_dp *intel_dp,
+				    const struct intel_crtc_state *crtc_state)
 {
 	int t1 = 50 * 1000;
-	int tps4 = 252;
+	int tps4 = intel_dp_is_uhbr(crtc_state) ? (ML_PHY_LOCK_LEN_UHBR * 32) :
+		   (ML_PHY_LOCK_LEN * 10);
 	/* port_clock is link rate in 10kbit/s units */
-	int tml_phy_lock = 1000 * 1000 * tps4 / crtc_state->port_clock;
+	int tml_phy_lock = 1000 * 1000 * tps4 / crtc_state->port_clock / 10;
+	int lttpr_count = 0;
 	int tcds, establishment_period;
 
-	tcds = (7 + DIV_ROUND_UP(6500, tml_phy_lock) + 1) * tml_phy_lock;
-	establishment_period = (SILENCE_PERIOD_TIME + t1 + tcds);
+	if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP)) {
+		tcds = (7 + DIV_ROUND_UP(6500, tml_phy_lock) + 1) * tml_phy_lock;
+	} else {
+		tcds = 7 * tml_phy_lock;
+		lttpr_count = drm_dp_lttpr_count(intel_dp->lttpr_common_caps);
+	}
+
+	if (lttpr_count) {
+		int tlw = 13000;
+		int tcs = 10000;
+		int tlfps_period = get_lfps_cycle_time(crtc_state);
+		int tdcs = (SILENCE_PERIOD_TIME + t1 + tcs +
+			    (lttpr_count - 1) * (tlw + tlfps_period));
+		int tacds = 70000;
+		int tds = (lttpr_count - 1) * 7 * tml_phy_lock;
+
+		/* tdrl is same as tcds*/
+		establishment_period = tlw + tlfps_period + tdcs + tacds + tds + tcds;
+	} else {
+		/* TODO: Add a check for data realign by DPCD 0x116[3] */
+
+		establishment_period = (SILENCE_PERIOD_TIME + t1 + tcds);
+	}
 
 	return establishment_period;
 }
@@ -141,12 +170,16 @@ static int get_establishment_period(const struct intel_crtc_state *crtc_state)
  * within the CDS period complete within the CDS period regardless of
  * entry into the period
  * tML_PHY_LOCK = TPS4 Length * ( 10 / (Link Rate in MHz) )
- * TPS4 Length = 252 Symbols
+ * ML_PHY_LOCK Length (8b/10b): 252
+ * ML_PHY_LOCK Length (128b/132b): 396
+ * TPS4 Length = ML_PHY_LOCK * Rate Div
+ * Rate Div = 32 for 128b/132b and 10 for 8b/10b.
  */
-static int _lnl_compute_aux_less_wake_time(const struct intel_crtc_state *crtc_state)
+static int _lnl_compute_aux_less_wake_time(struct intel_dp *intel_dp,
+					   const struct intel_crtc_state *crtc_state)
 {
 	int tphy2_p2_to_p0 = get_tphy2_p2_to_p0(crtc_state);
-	int establishment_period = get_establishment_period(crtc_state);
+	int establishment_period = get_establishment_period(intel_dp, crtc_state);
 
 	return DIV_ROUND_UP(tphy2_p2_to_p0 + get_lfps_cycle_time(crtc_state) +
 			    establishment_period, 1000);
@@ -161,7 +194,7 @@ _lnl_compute_aux_less_alpm_params(struct intel_dp *intel_dp,
 		lfps_half_cycle;
 
 	aux_less_wake_time =
-		_lnl_compute_aux_less_wake_time(crtc_state);
+		_lnl_compute_aux_less_wake_time(intel_dp, crtc_state);
 	aux_less_wake_lines = intel_usecs_to_scanlines(&crtc_state->hw.adjusted_mode,
 						       aux_less_wake_time);
 	silence_period = get_silence_period_symbols(crtc_state);
@@ -430,8 +463,12 @@ static void lnl_alpm_configure(struct intel_dp *intel_dp,
 	if (intel_alpm_is_alpm_aux_less(intel_dp, crtc_state)) {
 		alpm_ctl = ALPM_CTL_ALPM_ENABLE |
 			ALPM_CTL_ALPM_AUX_LESS_ENABLE |
-			ALPM_CTL_AUX_LESS_SLEEP_HOLD_TIME_50_SYMBOLS |
-			ALPM_CTL_AUX_LESS_WAKE_TIME(crtc_state->alpm_state.aux_less_wake_lines);
+			ALPM_CTL_AUX_LESS_SLEEP_HOLD_TIME_50_SYMBOLS;
+
+		if (DISPLAY_VER(display) < 35)
+			alpm_ctl |= ALPM_CTL_AUX_LESS_WAKE_TIME(crtc_state->alpm_state.aux_less_wake_lines);
+		else
+			alpm_ctl |= ALPM_CTL_AUX_LESS_WAKE_TIME_XE3LPD(crtc_state->alpm_state.aux_less_wake_lines);
 
 		if (intel_dp->as_sdp_supported) {
 			u32 pr_alpm_ctl = get_pr_alpm_as_sdp_transmission_time(crtc_state);
diff --git a/drivers/gpu/drm/i915/display/intel_psr_regs.h b/drivers/gpu/drm/i915/display/intel_psr_regs.h
index 16a9e3af198d..8ec99bbd84b6 100644
--- a/drivers/gpu/drm/i915/display/intel_psr_regs.h
+++ b/drivers/gpu/drm/i915/display/intel_psr_regs.h
@@ -299,7 +299,9 @@
 #define  ALPM_CTL_EXTENDED_FAST_WAKE_MIN_LINES		5
 #define  ALPM_CTL_EXTENDED_FAST_WAKE_TIME(lines)	REG_FIELD_PREP(ALPM_CTL_EXTENDED_FAST_WAKE_TIME_MASK, (lines) - ALPM_CTL_EXTENDED_FAST_WAKE_MIN_LINES)
 #define  ALPM_CTL_AUX_LESS_WAKE_TIME_MASK		REG_GENMASK(5, 0)
+#define  ALPM_CTL_AUX_LESS_WAKE_TIME_MASK_XE3LPD	REG_GENMASK(7, 0)
 #define  ALPM_CTL_AUX_LESS_WAKE_TIME(val)		REG_FIELD_PREP(ALPM_CTL_AUX_LESS_WAKE_TIME_MASK, val)
+#define  ALPM_CTL_AUX_LESS_WAKE_TIME_XE3LPD(val)	REG_FIELD_PREP(ALPM_CTL_AUX_LESS_WAKE_TIME_MASK_XE3LPD, val)
 
 #define _ALPM_CTL2_A	0x60954
 #define ALPM_CTL2(dev_priv, tran)	_MMIO_TRANS2(dev_priv, tran, _ALPM_CTL2_A)
-- 
2.29.0

Re: [PATCH v5 06/15] drm/i915/alpm: Auxless wake time calculation for Xe3p

[sashiko-bot]

Thank you for your contribution! Sashiko AI review found 3 potential issue(s) to consider:
- [High] Severe 32-bit signed integer overflow in `tml_phy_lock` calculation results in negative time values.
- [Medium] Missing error check on `drm_dp_lttpr_count()` return value allows negative error codes to corrupt ALPM time calculations.
- [Medium] The bounds check for `aux_less_wake_lines` does not use the expanded Xe3LPD mask, artificially limiting the maximum wake lines and potentially disabling ALPM on newer hardware.
--

--- Patch [6]: [PATCH v5 06/15] drm/i915/alpm: Auxless wake time calculation for Xe3p ---
commit d691d0d2ce1f7d50c7d92a8c206ccf76b71ba2ce
Author: Animesh Manna <animesh.manna@intel.com>
Subject: drm/i915/alpm: Auxless wake time calculation for Xe3p

This commit adds support for auxless waketime calculation for DP2.1 ALPM,
updating dependent parameters.

> diff --git a/drivers/gpu/drm/i915/display/intel_alpm.c b/drivers/gpu/drm/i915/display/intel_alpm.c
> index 4b15d96d0ad79..af2733805505e 100644
> --- a/drivers/gpu/drm/i915/display/intel_alpm.c
> +++ b/drivers/gpu/drm/i915/display/intel_alpm.c
> @@ -105,21 +105,50 @@ static int get_lfps_half_cycle_clocks(const struct intel_crtc_state *crtc_state)
>  		1000 / (2 * LFPS_CYCLE_COUNT);
>  }
>  
> +#define ML_PHY_LOCK_LEN		252
> +#define ML_PHY_LOCK_LEN_UHBR	396
> +
>  static int get_tphy2_p2_to_p0(const struct intel_crtc_state *crtc_state)
>  {
> -	return 12 * 1000;
> +	struct intel_display *display = to_intel_display(crtc_state);
> +
> +	return DISPLAY_VER(display) >= 35 ? (20 * 1000) : (12 * 1000);
>  }
>  
> -static int get_establishment_period(const struct intel_crtc_state *crtc_state)
> +static int get_establishment_period(struct intel_dp *intel_dp,
> +				    const struct intel_crtc_state *crtc_state)
>  {
>  	int t1 = 50 * 1000;
> -	int tps4 = 252;
> +	int tps4 = intel_dp_is_uhbr(crtc_state) ? (ML_PHY_LOCK_LEN_UHBR * 32) :
> +		   (ML_PHY_LOCK_LEN * 10);
>  	/* port_clock is link rate in 10kbit/s units */
> -	int tml_phy_lock = 1000 * 1000 * tps4 / crtc_state->port_clock;
> +	int tml_phy_lock = 1000 * 1000 * tps4 / crtc_state->port_clock / 10;

[Severity: High]
Does 1000 * 1000 * tps4 overflow the 32-bit signed integer before division?

For DP 2.1 UHBR, tps4 evaluates to 396 * 32 = 12672, yielding a product of
12,672,000,000. This exceeds the maximum 32-bit signed integer (2,147,483,647)
and results in a negative intermediate value.

This negative value will propagate through the division and subsequent time
formulas, corrupting the wake times programmed into the hardware.

> +	int lttpr_count = 0;
>  	int tcds, establishment_period;
>  
> -	tcds = (7 + DIV_ROUND_UP(6500, tml_phy_lock) + 1) * tml_phy_lock;
> -	establishment_period = (SILENCE_PERIOD_TIME + t1 + tcds);
> +	if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP)) {
> +		tcds = (7 + DIV_ROUND_UP(6500, tml_phy_lock) + 1) * tml_phy_lock;
> +	} else {
> +		tcds = 7 * tml_phy_lock;
> +		lttpr_count = drm_dp_lttpr_count(intel_dp->lttpr_common_caps);
> +	}
> +
> +	if (lttpr_count) {

[Severity: Medium]
Can drm_dp_lttpr_count() return a negative error code here?

If drm_dp_lttpr_count() returns a negative error code (e.g., -EINVAL or
-ERANGE), lttpr_count will evaluate to true in this check.

The code will then proceed into this block and use the negative value in
arithmetic like (lttpr_count - 1), causing a massive underflow in the
calculation of tdcs, tds, and establishment_period.

Should this explicitly check if (lttpr_count > 0)?

> +		int tlw = 13000;
> +		int tcs = 10000;
> +		int tlfps_period = get_lfps_cycle_time(crtc_state);
> +		int tdcs = (SILENCE_PERIOD_TIME + t1 + tcs +
> +			    (lttpr_count - 1) * (tlw + tlfps_period));
> +		int tacds = 70000;
> +		int tds = (lttpr_count - 1) * 7 * tml_phy_lock;
> +
> +		/* tdrl is same as tcds*/
> +		establishment_period = tlw + tlfps_period + tdcs + tacds + tds + tcds;
> +	} else {
> +		/* TODO: Add a check for data realign by DPCD 0x116[3] */
> +
> +		establishment_period = (SILENCE_PERIOD_TIME + t1 + tcds);
> +	}
>  
>  	return establishment_period;
>  }

[ ... ]

> @@ -161,7 +194,7 @@ _lnl_compute_aux_less_alpm_params(struct intel_dp *intel_dp,
>  		lfps_half_cycle;
>  
>  	aux_less_wake_time =
> -		_lnl_compute_aux_less_wake_time(crtc_state);
> +		_lnl_compute_aux_less_wake_time(intel_dp, crtc_state);
>  	aux_less_wake_lines = intel_usecs_to_scanlines(&crtc_state->hw.adjusted_mode,
>  						       aux_less_wake_time);
>  	silence_period = get_silence_period_symbols(crtc_state);

[Severity: Medium]
Does the bounds check further down in this function still use the legacy mask?

Looking at the rest of _lnl_compute_aux_less_alpm_params():

    if (aux_less_wake_lines > ALPM_CTL_AUX_LESS_WAKE_TIME_MASK ||
        ...
        return false;

    if (display->params.psr_safest_params)
        aux_less_wake_lines = ALPM_CTL_AUX_LESS_WAKE_TIME_MASK;

Since this patch introduces ALPM_CTL_AUX_LESS_WAKE_TIME_MASK_XE3LPD for
platforms with DISPLAY_VER >= 35, will these checks artificially limit the
maximum wake lines to the older 6-bit mask (63) and potentially disable ALPM
on newer hardware?

[ ... ]

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20260825054536.3455704-1-animesh.manna@intel.com?part=6

[PATCH v5 07/15] drm/i915/alpm: table based establishment period

[Animesh Manna]

Only use the table when the link rate is listed (idx valid)
and the LTTPR count is within the table bounds. A zero entry
means the rate has no tabulated value, so fall back to the
computed establishment period below.

Signed-off-by: Animesh Manna <animesh.manna@intel.com>
---
 drivers/gpu/drm/i915/display/intel_alpm.c | 95 +++++++++++++++++++++++
 1 file changed, 95 insertions(+)

diff --git a/drivers/gpu/drm/i915/display/intel_alpm.c b/drivers/gpu/drm/i915/display/intel_alpm.c
index af2733805505..078e04bb69d2 100644
--- a/drivers/gpu/drm/i915/display/intel_alpm.c
+++ b/drivers/gpu/drm/i915/display/intel_alpm.c
@@ -115,6 +115,92 @@ static int get_tphy2_p2_to_p0(const struct intel_crtc_state *crtc_state)
 	return DISPLAY_VER(display) >= 35 ? (20 * 1000) : (12 * 1000);
 }
 
+#define DEFAULT_MAX_LTTPR_COUNT 7
+#define MAX_SUPPORTED_DP_LINK_RATES 12
+
+static const u32 establishment_periods[DEFAULT_MAX_LTTPR_COUNT][MAX_SUPPORTED_DP_LINK_RATES] = {
+	/* 1620, 2160, 2430, 2700, 3240, 4320, 5400, 6750, 8100, 10000, 13500, 20000 */
+	/* No Retimers */
+	{ 61070, 0, 0, 56710, 0, 0, 53450, 0, 52360, 59050, 56750, 54620 },
+	/*  1 Retimer  */
+	{ 155670, 0, 0, 151310, 0, 0, 148050, 0, 146960, 153650, 151350, 149220 },
+	/*  2 Retimers */
+	{ 181160, 0, 0, 172450, 0, 0, 165910, 0, 163740, 177120, 172520, 168220 },
+	/*  3 Retimers */
+	{ 206650, 0, 0, 193580, 0, 0, 183780, 0, 180510, 200590, 193690, 187290 },
+	/*  4 Retimers */
+	{ 232140, 0, 0, 214710, 0, 0, 201650, 0, 197290, 224060, 214860, 206320 },
+	/*  5 Retimers */
+	{ 257620, 0, 0, 235850, 0, 0, 219510, 0, 214070, 247530, 236030, 225360 },
+	/*  6 Retimers */
+	{ 283110, 0, 0, 256980, 0, 0, 237380, 0, 230850, 271000, 257200, 244390 },
+};
+
+enum link_rate_idx {
+	LINK_RATE_INVALID = -1,
+	LINK_RATE_1,
+	LINK_RATE_2,
+	LINK_RATE_3,
+	LINK_RATE_4,
+	LINK_RATE_5,
+	LINK_RATE_6,
+	LINK_RATE_7,
+	LINK_RATE_8,
+	LINK_RATE_9,
+	LINK_RATE_10,
+	LINK_RATE_11,
+	LINK_RATE_12
+};
+
+static int get_link_rate_index(int port_clock)
+{
+	int link_rate_index;
+
+	switch (port_clock) {
+	case 162000:
+		link_rate_index = LINK_RATE_1;	// Rate_1 (RBR) - 1.62 Gbps/Lane
+		break;
+	case 216000:
+		link_rate_index = LINK_RATE_2;	// Rate_2       - 2.16 Gbps/Lane
+		break;
+	case 243000:
+		link_rate_index = LINK_RATE_3;	// Rate_3       - 2.43 Gbps/Lane
+		break;
+	case 270000:
+		link_rate_index = LINK_RATE_4;	// Rate_4 (HBR) - 2.70 Gbps/Lane
+		break;
+	case 324000:
+		link_rate_index = LINK_RATE_5;	// Rate_5 (RBR2)- 3.24 Gbps/Lane
+		break;
+	case 432000:
+		link_rate_index = LINK_RATE_6;	// Rate_6       - 4.32 Gbps/Lane
+		break;
+	case 540000:
+		link_rate_index = LINK_RATE_7;	// Rate_7 (HBR2)- 5.40 Gbps/Lane
+		break;
+	case 675000:
+		link_rate_index = LINK_RATE_8;	// Rate_8       - 6.75 Gbps/Lane
+		break;
+	case 810000:
+		link_rate_index = LINK_RATE_9;	// Rate_9 (HBR3)- 8.10 Gbps/Lane
+		break;
+	case 1000000:
+		link_rate_index = LINK_RATE_10;	// Rate_10 (UHBR10) - 10.0 Gbps/Lane
+		break;
+	case 1350000:
+		link_rate_index = LINK_RATE_11;	// Rate_11 (UHBR13.5) - 13.5 Gbps/Lane
+		break;
+	case 2000000:
+		link_rate_index = LINK_RATE_12;	// Rate_12 (UHBR20) - 20.0 Gbps/Lane
+		break;
+	default:
+		link_rate_index = -1;
+		break;
+	}
+
+	return link_rate_index;
+}
+
 static int get_establishment_period(struct intel_dp *intel_dp,
 				    const struct intel_crtc_state *crtc_state)
 {
@@ -129,8 +215,17 @@ static int get_establishment_period(struct intel_dp *intel_dp,
 	if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP)) {
 		tcds = (7 + DIV_ROUND_UP(6500, tml_phy_lock) + 1) * tml_phy_lock;
 	} else {
+		int idx = get_link_rate_index(crtc_state->port_clock);
+
 		tcds = 7 * tml_phy_lock;
 		lttpr_count = drm_dp_lttpr_count(intel_dp->lttpr_common_caps);
+
+		if (idx != LINK_RATE_INVALID &&
+		    lttpr_count < DEFAULT_MAX_LTTPR_COUNT &&
+		    establishment_periods[lttpr_count][idx]) {
+			establishment_period = establishment_periods[lttpr_count][idx];
+			return establishment_period;
+		}
 	}
 
 	if (lttpr_count) {
-- 
2.29.0

Re: [PATCH v5 07/15] drm/i915/alpm: table based establishment period

[sashiko-bot]

Thank you for your contribution! Sashiko AI review found 2 potential issue(s) to consider:

New issues:
- [High] Unchecked negative error codes from drm_dp_lttpr_count() cause an out-of-bounds array read and integer underflow.

Pre-existing issues:
- [High] 32-bit signed integer overflow in `tml_phy_lock` calculation corrupts ALPM wake time.
--

--- Patch [7]: [PATCH v5 07/15] drm/i915/alpm: table based establishment period ---
commit 39688e03d0da05abea5d53e9441ff2410c77a69c
Author: Animesh Manna <animesh.manna@intel.com>
Subject: drm/i915/alpm: table based establishment period

This patch introduces a table-based lookup for the establishment period
in intel_alpm.c. It uses the link rate and LTTPR count to find the period
from a 2D array, falling back to a computed value if not found.

> diff --git a/drivers/gpu/drm/i915/display/intel_alpm.c b/drivers/gpu/drm/i915/display/intel_alpm.c
> index af2733805505e..078e04bb69d29 100644
> --- a/drivers/gpu/drm/i915/display/intel_alpm.c
> +++ b/drivers/gpu/drm/i915/display/intel_alpm.c

[ ... ]

> @@ -129,8 +215,17 @@ static int get_establishment_period(struct intel_dp *intel_dp,
>  	if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP)) {
>  		tcds = (7 + DIV_ROUND_UP(6500, tml_phy_lock) + 1) * tml_phy_lock;

[Severity: High]
This isn't a bug introduced by this patch, but does the calculation for
tml_phy_lock suffer from a 32-bit signed integer overflow?

Looking earlier in get_establishment_period():

int tml_phy_lock = 1000 * 1000 * tps4 / crtc_state->port_clock / 10;

The expression 1000 * 1000 * tps4 evaluates using 32-bit signed integer
math. For both DP (tps4 = 2520) and UHBR (tps4 = 12672), the intermediate
result exceeds INT_MAX (2,147,483,647) and overflows (to -212643840 for
UHBR). This negative value propagates into tml_phy_lock and causes tcds to
subtract time instead of adding it, which could corrupt the ALPM wake time.

>  	} else {
> +		int idx = get_link_rate_index(crtc_state->port_clock);
> +
>  		tcds = 7 * tml_phy_lock;
>  		lttpr_count = drm_dp_lttpr_count(intel_dp->lttpr_common_caps);
> +
> +		if (idx != LINK_RATE_INVALID &&
> +		    lttpr_count < DEFAULT_MAX_LTTPR_COUNT &&

[Severity: High]
If a buggy or malicious DP sink returns an invalid LTTPR configuration,
drm_dp_lttpr_count() can return a negative error code (e.g., -ERANGE
or -EINVAL). Since lttpr_count is signed, will it incorrectly pass this
lttpr_count < DEFAULT_MAX_LTTPR_COUNT check?

> +		    establishment_periods[lttpr_count][idx]) {
> +			establishment_period = establishment_periods[lttpr_count][idx];

Could this negative lttpr_count then be used as an array index on this
line, causing an out-of-bounds memory read? If the out-of-bounds read
accesses an unmapped page it could trigger a kernel oops.

Furthermore, if the lookup is bypassed, the negative lttpr_count could cause
severe integer underflow in the fallback calculation later in this function:

int tdcs = (SILENCE_PERIOD_TIME + t1 + tcs +
            (lttpr_count - 1) * (tlw + tlfps_period));

> +			return establishment_period;
> +		}
>  	}
>  
>  	if (lttpr_count) {

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20260825054536.3455704-1-animesh.manna@intel.com?part=7

[PATCH v5 08/15] drm/i915/alpm: Half LFPS cycle calculation

[Animesh Manna]

Add support for half LFPS cycle calculation for DP2.1 ALPM as dependent
parameters got changed.

v1: Initial version.
v2: Avoid returning early. [Jani]
v3: Use intel_crtc_has_type(). [Suraj]

Cc: Jouni Högander <jouni.hogander@intel.com>
Signed-off-by: Animesh Manna <animesh.manna@intel.com>
---
 drivers/gpu/drm/i915/display/intel_alpm.c | 18 ++++++++++++------
 1 file changed, 12 insertions(+), 6 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_alpm.c b/drivers/gpu/drm/i915/display/intel_alpm.c
index 078e04bb69d2..98aa418a6ff7 100644
--- a/drivers/gpu/drm/i915/display/intel_alpm.c
+++ b/drivers/gpu/drm/i915/display/intel_alpm.c
@@ -80,12 +80,18 @@ static int get_silence_period_symbols(const struct intel_crtc_state *crtc_state)
 static void get_lfps_cycle_min_max_time(const struct intel_crtc_state *crtc_state,
 					int *min, int *max)
 {
-	if (crtc_state->port_clock < 540000) {
-		*min = 65 * LFPS_CYCLE_COUNT;
-		*max = 75 * LFPS_CYCLE_COUNT;
-	} else {
-		*min = 140;
-		*max = 800;
+	struct intel_display *display = to_intel_display(crtc_state);
+
+	*min = 320;
+	*max = 1600;
+	if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP)) {
+		if (crtc_state->port_clock < 540000 && DISPLAY_VER(display) < 35) {
+			*min = 65 * LFPS_CYCLE_COUNT;
+			*max = 75 * LFPS_CYCLE_COUNT;
+		} else {
+			*min = 140;
+			*max = 800;
+		}
 	}
 }
 
-- 
2.29.0

Re: [PATCH v5 08/15] drm/i915/alpm: Half LFPS cycle calculation

[sashiko-bot]

Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:

Pre-existing issues:
- [High] `get_lfps_half_cycle_clocks()` incorrectly uses the DP port clock (link rate) instead of the symbol clock, which inflates the cycle count and causes it to exceed the 5-bit register mask for DP 2.1 UHBR rates, completely breaking ALPM.
--

--- Patch [8]: [PATCH v5 08/15] drm/i915/alpm: Half LFPS cycle calculation ---
commit 3b44d7e9f6ce14c0e3f4bb3319784906c402099b
Author: Animesh Manna <animesh.manna@intel.com>

drm/i915/alpm: Half LFPS cycle calculation

Add support for half LFPS cycle calculation for DP2.1 ALPM as dependent
parameters got changed.

> diff --git a/drivers/gpu/drm/i915/display/intel_alpm.c b/drivers/gpu/drm/i915/display/intel_alpm.c
> index 078e04bb69d29..98aa418a6ff77 100644
> --- a/drivers/gpu/drm/i915/display/intel_alpm.c
> +++ b/drivers/gpu/drm/i915/display/intel_alpm.c
> @@ -80,12 +80,18 @@ static int get_silence_period_symbols(const struct intel_crtc_state *crtc_state)

[Severity: High]
This isn't a bug introduced by this patch, but since this patch series
enables DP 2.1 ALPM, it exposes an issue in get_lfps_half_cycle_clocks()
(which is located nearby in this file).

Does get_lfps_half_cycle_clocks() incorrectly use the DP port clock
(link rate) instead of the symbol clock?

For legacy 8b/10b encoding, the link rate in 10 kbps is numerically equal
to the symbol clock in kHz. However, for 128b/132b (UHBR) rates introduced
in DP 2.1, the link rate is 3.2x the symbol clock. This inflates the symbol
count calculation by a factor of 3.2.

When this inflated value is checked against the 5-bit mask
(PORT_ALPM_LFPS_CTL_LAST_LFPS_HALF_CYCLE_DURATION_MASK) in
_lnl_compute_aux_less_alpm_params(), it unconditionally fails because it
exceeds the maximum value of 31. This causes ALPM configuration to abort for
any DP 2.1 UHBR display.

Other ALPM functions like get_silence_period_symbols() correctly use
intel_dp_link_symbol_clock(crtc_state->port_clock). Should
get_lfps_half_cycle_clocks() also be updated to use the symbol clock?

>  static void get_lfps_cycle_min_max_time(const struct intel_crtc_state *crtc_state,
>  					int *min, int *max)
>  {
> -	if (crtc_state->port_clock < 540000) {
> -		*min = 65 * LFPS_CYCLE_COUNT;
> -		*max = 75 * LFPS_CYCLE_COUNT;
> -	} else {
> -		*min = 140;
> -		*max = 800;
> +	struct intel_display *display = to_intel_display(crtc_state);
> +
> +	*min = 320;
> +	*max = 1600;
> +	if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP)) {
> +		if (crtc_state->port_clock < 540000 && DISPLAY_VER(display) < 35) {
> +			*min = 65 * LFPS_CYCLE_COUNT;
> +			*max = 75 * LFPS_CYCLE_COUNT;
> +		} else {
> +			*min = 140;
> +			*max = 800;
> +		}
>  	}
>  }

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20260825054536.3455704-1-animesh.manna@intel.com?part=8

[PATCH v5 09/15] drm/i915/alpm: Modify LFPS cycle count for DP ALPM

[Animesh Manna]

For DP minimum LFPS count is set to minimum 16.

Signed-off-by: Animesh Manna <animesh.manna@intel.com>
---
 drivers/gpu/drm/i915/display/intel_alpm.c     | 28 +++++++++++++++++--
 drivers/gpu/drm/i915/display/intel_psr_regs.h |  2 ++
 2 files changed, 27 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_alpm.c b/drivers/gpu/drm/i915/display/intel_alpm.c
index 98aa418a6ff7..890bf2488554 100644
--- a/drivers/gpu/drm/i915/display/intel_alpm.c
+++ b/drivers/gpu/drm/i915/display/intel_alpm.c
@@ -24,7 +24,8 @@
 				(SILENCE_PERIOD_MAX_TIME -	\
 				 SILENCE_PERIOD_MIN_TIME) / 2)
 
-#define LFPS_CYCLE_COUNT 10
+#define LFPS_CYCLE_COUNT	10
+#define LFPS_CYCLE_COUNT_DP	16
 
 bool intel_alpm_aux_wake_supported(struct intel_dp *intel_dp)
 {
@@ -105,10 +106,22 @@ static int get_lfps_cycle_time(const struct intel_crtc_state *crtc_state)
 	return tlfps_cycle_min +  (tlfps_cycle_max - tlfps_cycle_min) / 2;
 }
 
+static int get_lfps_cycle_count(const struct intel_crtc_state *crtc_state)
+{
+	struct intel_display *display = to_intel_display(crtc_state);
+
+	/* External DP on Xe3lpd+ uses a minimum of 16 LFPS cycles. */
+	if (!intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP) &&
+	    DISPLAY_VER(display) >= 35)
+		return LFPS_CYCLE_COUNT_DP;
+
+	return LFPS_CYCLE_COUNT;
+}
+
 static int get_lfps_half_cycle_clocks(const struct intel_crtc_state *crtc_state)
 {
 	return get_lfps_cycle_time(crtc_state) * crtc_state->port_clock / 1000 /
-		1000 / (2 * LFPS_CYCLE_COUNT);
+		1000 / (2 * get_lfps_cycle_count(crtc_state));
 }
 
 #define ML_PHY_LOCK_LEN		252
@@ -622,12 +635,21 @@ void intel_alpm_port_configure(struct intel_dp *intel_dp,
 		return;
 
 	if (intel_alpm_is_alpm_aux_less(intel_dp, crtc_state)) {
+		int lfps_cycle = get_lfps_cycle_count(crtc_state);
+		u32 lfps_cycle_val;
+
+		if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP))
+			lfps_cycle_val = PORT_ALPM_LFPS_CTL_LFPS_CYCLE_COUNT(lfps_cycle);
+		else
+			lfps_cycle_val = PORT_ALPM_LFPS_CTL_LFPS_CYCLE_COUNT_XE3LPD(lfps_cycle);
+
 		alpm_ctl_val = PORT_ALPM_CTL_ALPM_AUX_LESS_ENABLE |
 			PORT_ALPM_CTL_MAX_PHY_SWING_SETUP(15) |
 			PORT_ALPM_CTL_MAX_PHY_SWING_HOLD(0) |
 			PORT_ALPM_CTL_SILENCE_PERIOD(
 				crtc_state->alpm_state.silence_period_sym_clocks);
-		lfps_ctl_val = PORT_ALPM_LFPS_CTL_LFPS_CYCLE_COUNT(LFPS_CYCLE_COUNT) |
+
+		lfps_ctl_val = lfps_cycle_val |
 			PORT_ALPM_LFPS_CTL_LFPS_HALF_CYCLE_DURATION(
 				crtc_state->alpm_state.lfps_half_cycle_num_of_syms) |
 			PORT_ALPM_LFPS_CTL_FIRST_LFPS_HALF_CYCLE_DURATION(
diff --git a/drivers/gpu/drm/i915/display/intel_psr_regs.h b/drivers/gpu/drm/i915/display/intel_psr_regs.h
index 8ec99bbd84b6..d33e9b0a81d7 100644
--- a/drivers/gpu/drm/i915/display/intel_psr_regs.h
+++ b/drivers/gpu/drm/i915/display/intel_psr_regs.h
@@ -333,8 +333,10 @@
 #define PORT_ALPM_LFPS_CTL(port)				_MMIO_PORT(port, _PORT_ALPM_LFPS_CTL_A, _PORT_ALPM_LFPS_CTL_B)
 #define  PORT_ALPM_LFPS_CTL_LFPS_START_POLARITY			REG_BIT(31)
 #define  PORT_ALPM_LFPS_CTL_LFPS_CYCLE_COUNT_MASK		REG_GENMASK(27, 24)
+#define  PORT_ALPM_LFPS_CTL_LFPS_CYCLE_COUNT_MASK_XE3LPD	REG_GENMASK(30, 24)
 #define  PORT_ALPM_LFPS_CTL_LFPS_CYCLE_COUNT_MIN		7
 #define  PORT_ALPM_LFPS_CTL_LFPS_CYCLE_COUNT(val)		REG_FIELD_PREP(PORT_ALPM_LFPS_CTL_LFPS_CYCLE_COUNT_MASK, (val) - PORT_ALPM_LFPS_CTL_LFPS_CYCLE_COUNT_MIN)
+#define  PORT_ALPM_LFPS_CTL_LFPS_CYCLE_COUNT_XE3LPD(val)	REG_FIELD_PREP(PORT_ALPM_LFPS_CTL_LFPS_CYCLE_COUNT_MASK_XE3LPD, (val) - PORT_ALPM_LFPS_CTL_LFPS_CYCLE_COUNT_MIN)
 #define  PORT_ALPM_LFPS_CTL_LFPS_HALF_CYCLE_DURATION_MASK	REG_GENMASK(20, 16)
 #define  PORT_ALPM_LFPS_CTL_LFPS_HALF_CYCLE_DURATION(val)	REG_FIELD_PREP(PORT_ALPM_LFPS_CTL_LFPS_HALF_CYCLE_DURATION_MASK, val)
 #define  PORT_ALPM_LFPS_CTL_FIRST_LFPS_HALF_CYCLE_DURATION_MASK	REG_GENMASK(12, 8)
-- 
2.29.0

Re: [PATCH v5 09/15] drm/i915/alpm: Modify LFPS cycle count for DP ALPM

[sashiko-bot]

Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [Medium] Incorrect register bit mask selection for LFPS cycle count based on connector type instead of hardware IP version.
--

--- Patch [9]: [PATCH v5 09/15] drm/i915/alpm: Modify LFPS cycle count for DP ALPM ---
commit f40607bd1107960e9e7fba56539c2f142247127f
Author: Animesh Manna <animesh.manna@intel.com>

drm/i915/alpm: Modify LFPS cycle count for DP ALPM
    
This commit modifies the display driver to set a minimum LFPS cycle
count of 16 for external DP on newer display IPs.

> diff --git a/drivers/gpu/drm/i915/display/intel_alpm.c b/drivers/gpu/drm/i915/display/intel_alpm.c
> index 98aa418a6ff77..890bf24885547 100644
> --- a/drivers/gpu/drm/i915/display/intel_alpm.c
> +++ b/drivers/gpu/drm/i915/display/intel_alpm.c
[ ... ]
> @@ -622,12 +635,21 @@ void intel_alpm_port_configure(struct intel_dp *intel_dp,
>  		return;
>  
>  	if (intel_alpm_is_alpm_aux_less(intel_dp, crtc_state)) {
> +		int lfps_cycle = get_lfps_cycle_count(crtc_state);
> +		u32 lfps_cycle_val;
> +
> +		if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP))
> +			lfps_cycle_val = PORT_ALPM_LFPS_CTL_LFPS_CYCLE_COUNT(lfps_cycle);
> +		else
> +			lfps_cycle_val = PORT_ALPM_LFPS_CTL_LFPS_CYCLE_COUNT_XE3LPD(lfps_cycle);
                ^^^^

[Severity: Medium]
Does this code incorrectly conflate the sink type with the display IP version?

In intel_alpm_port_configure(), branching on the connector type
(INTEL_OUTPUT_EDP) rather than the hardware IP version causes eDP panels on
Xe3LPD to be programmed using the legacy 4-bit register mask instead of the
expanded 7-bit Xe3LPD mask.

While the current default value for eDP (10 cycles) happens to fit within the
lower 4 bits, if the eDP LFPS cycle count is ever tuned to a value > 22, the
legacy 4-bit mask will truncate it and could corrupt the hardware configuration.

Should this logic check the display version instead of the output type?

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20260825054536.3455704-1-animesh.manna@intel.com?part=9

[PATCH v5 10/15] drm/i915/alpm: Program LTTPR count for DP 2.1 ALPM

[Animesh Manna]

Issue a AUX write transaction to DPCD DP_TOTAL_LTTPR_CNT (0xf000a)
with total number of LTTPR before link training.

v2: Cosmetic changes. [Suraj]

Cc: Jouni Högander <jouni.hogander@intel.com>
Signed-off-by: Animesh Manna <animesh.manna@intel.com>
---
 drivers/gpu/drm/i915/display/intel_alpm.c        |  9 ++++++++-
 .../drm/i915/display/intel_dp_link_training.c    | 16 ++++++++++++++++
 2 files changed, 24 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/display/intel_alpm.c b/drivers/gpu/drm/i915/display/intel_alpm.c
index 890bf2488554..d23f3bdf1339 100644
--- a/drivers/gpu/drm/i915/display/intel_alpm.c
+++ b/drivers/gpu/drm/i915/display/intel_alpm.c
@@ -563,7 +563,7 @@ static void lnl_alpm_configure(struct intel_dp *intel_dp,
 {
 	struct intel_display *display = to_intel_display(intel_dp);
 	enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
-	u32 alpm_ctl;
+	u32 alpm_ctl, alpm_ctl2, lttpr_count;
 
 	if (DISPLAY_VER(display) < 20 || (!intel_psr_needs_alpm(intel_dp, crtc_state) &&
 					  !crtc_state->has_lobf))
@@ -613,6 +613,13 @@ static void lnl_alpm_configure(struct intel_dp *intel_dp,
 
 	alpm_ctl |= ALPM_CTL_ALPM_ENTRY_CHECK(crtc_state->alpm_state.check_entry_lines);
 
+	lttpr_count = drm_dp_lttpr_count(intel_dp->lttpr_common_caps);
+
+	alpm_ctl2 = intel_de_read(display, ALPM_CTL2(display, cpu_transcoder));
+	alpm_ctl2 &= ~ALPM_CTL2_NUMBER_OF_LTTPR_MASK;
+	alpm_ctl2 |= ALPM_CTL2_NUMBER_OF_LTTPR(lttpr_count);
+
+	intel_de_write(display, ALPM_CTL2(display, cpu_transcoder), alpm_ctl2);
 	intel_de_write(display, ALPM_CTL(display, cpu_transcoder), alpm_ctl);
 	mutex_unlock(&intel_dp->alpm.lock);
 }
diff --git a/drivers/gpu/drm/i915/display/intel_dp_link_training.c b/drivers/gpu/drm/i915/display/intel_dp_link_training.c
index cb92cff90614..1d5873cb64f5 100644
--- a/drivers/gpu/drm/i915/display/intel_dp_link_training.c
+++ b/drivers/gpu/drm/i915/display/intel_dp_link_training.c
@@ -2265,6 +2265,20 @@ intel_dp_128b132b_link_train(struct intel_dp *intel_dp,
 	return passed;
 }
 
+static void intel_dp_update_lttpr_count(struct intel_dp *intel_dp,
+					int lttpr_count)
+{
+	/*
+	 * Program only for DP2.1 and return if LTTPR revison is less than 0x20
+	 * where 0:3 represents minor rev and 4:7 represent major rev
+	 */
+	if (!intel_dp_is_edp(intel_dp) ||
+	    intel_dp->lttpr_common_caps[0] <= 0x20)
+		return;
+
+	drm_dp_dpcd_writeb(&intel_dp->aux, DP_TOTAL_LTTPR_CNT, lttpr_count);
+}
+
 /**
  * intel_dp_start_link_train - start link training
  * @state: Atomic state
@@ -2304,6 +2318,8 @@ void intel_dp_start_link_train(struct intel_atomic_state *state,
 
 	intel_dp_prepare_link_train(intel_dp, crtc_state);
 
+	intel_dp_update_lttpr_count(intel_dp, lttpr_count);
+
 	if (intel_dp_is_uhbr(crtc_state))
 		passed = intel_dp_128b132b_link_train(intel_dp, crtc_state, lttpr_count);
 	else
-- 
2.29.0

Re: [PATCH v5 10/15] drm/i915/alpm: Program LTTPR count for DP 2.1 ALPM

[sashiko-bot]

Thank you for your contribution! Sashiko AI review found 2 potential issue(s) to consider:
- [High] Logical inversion in the early return condition causes `intel_dp_update_lttpr_count` to unconditionally return for all display types, rendering the new feature completely inactive.
- [Medium] Mismatch between comment and code for LTTPR revision check.
--

--- Patch [10]: [PATCH v5 10/15] drm/i915/alpm: Program LTTPR count for DP 2.1 ALPM ---
commit 2590778ff6f9e6755fe0231710bcb90018b982c4
Author: Animesh Manna <animesh.manna@intel.com>

drm/i915/alpm: Program LTTPR count for DP 2.1 ALPM

This commit adds an AUX write transaction to DP_TOTAL_LTTPR_CNT (0xf000a)
with the total number of LTTPRs before link training for DP 2.1 ALPM.

> diff --git a/drivers/gpu/drm/i915/display/intel_dp_link_training.c b/drivers/gpu/drm/i915/display/intel_dp_link_training.c
> index cb92cff906146..1d5873cb64f55 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp_link_training.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp_link_training.c
[ ... ]
> @@ -2265,6 +2265,20 @@ intel_dp_128b132b_link_train(struct intel_dp *intel_dp,
>  	return passed;
>  }
>  
> +static void intel_dp_update_lttpr_count(struct intel_dp *intel_dp,
> +					int lttpr_count)
> +{
> +	/*
> +	 * Program only for DP2.1 and return if LTTPR revison is less than 0x20
> +	 * where 0:3 represents minor rev and 4:7 represent major rev
> +	 */

[Severity: Medium]
Does this comment contradict the logic implemented below? 

The comment states the function should return if the revision is "less
than 0x20", while the code correctly checks for less than or equal to 0x20
to filter out DP 2.0.

> +	if (!intel_dp_is_edp(intel_dp) ||
> +	    intel_dp->lttpr_common_caps[0] <= 0x20)
> +		return;

[Severity: High]
Does this logic inadvertently cause an unconditional early return for all
display types?

For external DP displays where LTTPRs are used, !intel_dp_is_edp(intel_dp)
evaluates to true, triggering the early return immediately.

For eDP displays, !intel_dp_is_edp(intel_dp) evaluates to false, but since
eDP bypasses LTTPR initialization in intel_dp_init_lttpr_and_dprx_caps(),
intel_dp->lttpr_common_caps remains zero-initialized. 

This causes intel_dp->lttpr_common_caps[0] <= 0x20 to evaluate to true
(since 0 is less than 0x20), which also triggers the early return.

Was the intention to check intel_dp_is_edp(intel_dp) without the logical
inversion to properly bypass eDP?

> +
> +	drm_dp_dpcd_writeb(&intel_dp->aux, DP_TOTAL_LTTPR_CNT, lttpr_count);
> +}

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20260825054536.3455704-1-animesh.manna@intel.com?part=10

[PATCH v5 11/15] drm/i915/alpm: Enable MAC Transmitting LFPS for LT PHY

[Animesh Manna]

Enable MAC to transmit LFPS via LT PHY during aux-less alpm.

v2:
- Correct commit description. [Suraj]
- Remove loop as no dependency on the transmitter LT_PHY_CMN_CTL0. [Suraj]
v3: Cosmetic changes. [Suraj]

Cc: Jouni Högander <jouni.hogander@intel.com>
Reviewed-by: Suraj Kandpal <suraj.kandpal@intel.com>
Signed-off-by: Animesh Manna <animesh.manna@intel.com>
---
 drivers/gpu/drm/i915/display/intel_ddi.c      |  5 +++-
 drivers/gpu/drm/i915/display/intel_lt_phy.c   | 27 +++++++++++++++++++
 drivers/gpu/drm/i915/display/intel_lt_phy.h   |  2 ++
 .../gpu/drm/i915/display/intel_lt_phy_regs.h  |  3 +++
 4 files changed, 36 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
index 9b3b526e5e55..5244218132aa 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -3796,7 +3796,10 @@ static void mtl_ddi_prepare_link_retrain(struct intel_dp *intel_dp,
 	 *     ii. Enable MAC Transmits LFPS in the "PHY Common Control 0" PIPE
 	 *         register
 	 */
-	intel_lnl_mac_transmit_lfps(encoder, crtc_state);
+	if (HAS_LT_PHY(display))
+		intel_xe3plpd_mac_transmit_lfps(encoder, crtc_state);
+	else
+		intel_lnl_mac_transmit_lfps(encoder, crtc_state);
 }
 
 static void intel_ddi_prepare_link_retrain(struct intel_dp *intel_dp,
diff --git a/drivers/gpu/drm/i915/display/intel_lt_phy.c b/drivers/gpu/drm/i915/display/intel_lt_phy.c
index 86492651b01d..4fe010df20be 100644
--- a/drivers/gpu/drm/i915/display/intel_lt_phy.c
+++ b/drivers/gpu/drm/i915/display/intel_lt_phy.c
@@ -5,6 +5,7 @@
 
 #include <drm/drm_print.h>
 
+#include "intel_alpm.h"
 #include "intel_cx0_phy.h"
 #include "intel_cx0_phy_regs.h"
 #include "intel_ddi.h"
@@ -2357,3 +2358,29 @@ void intel_lt_phy_verify_plls(struct intel_display *display)
 	intel_lt_phy_pll_verify_tables(display, xe3plpd_lt_edp_tables);
 	intel_lt_phy_pll_verify_tables(display, xe3plpd_lt_hdmi_tables);
 }
+
+/*
+ * According to HAS we need to enable MAC Transmitting LFPS in the "PHY Common
+ * Control 0" PIPE register in case of AUX Less ALPM is going to be used. This
+ * function is doing that and is called by link retrain sequence.
+ */
+void intel_xe3plpd_mac_transmit_lfps(struct intel_encoder *encoder,
+				     const struct intel_crtc_state *crtc_state)
+{
+	struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
+	struct ref_tracker *wakeref;
+	u8 owned_lane_mask;
+
+	if (!intel_alpm_is_alpm_aux_less(intel_dp, crtc_state))
+		return;
+
+	wakeref = intel_lt_phy_transaction_begin(encoder);
+
+	owned_lane_mask = intel_lt_phy_get_owned_lane_mask(encoder);
+
+	intel_lt_phy_rmw(encoder, owned_lane_mask, LT_PHY_CMN_CTL_0,
+			 LT_PHY_CMN_LFPS_ENABLE,
+			 LT_PHY_CMN_LFPS_ENABLE, MB_WRITE_COMMITTED);
+
+	intel_lt_phy_transaction_end(encoder, wakeref);
+}
diff --git a/drivers/gpu/drm/i915/display/intel_lt_phy.h b/drivers/gpu/drm/i915/display/intel_lt_phy.h
index 16de39484779..c76c97b90946 100644
--- a/drivers/gpu/drm/i915/display/intel_lt_phy.h
+++ b/drivers/gpu/drm/i915/display/intel_lt_phy.h
@@ -49,5 +49,7 @@ void intel_xe3plpd_pll_enable(struct intel_encoder *encoder,
 			      const struct intel_dpll_hw_state *dpll_hw_state);
 void intel_xe3plpd_pll_disable(struct intel_encoder *encoder);
 void intel_lt_phy_verify_plls(struct intel_display *display);
+void intel_xe3plpd_mac_transmit_lfps(struct intel_encoder *encoder,
+				     const struct intel_crtc_state *crtc_state);
 
 #endif /* __INTEL_LT_PHY_H__ */
diff --git a/drivers/gpu/drm/i915/display/intel_lt_phy_regs.h b/drivers/gpu/drm/i915/display/intel_lt_phy_regs.h
index ff6d7829dbb9..b64ff57e0c09 100644
--- a/drivers/gpu/drm/i915/display/intel_lt_phy_regs.h
+++ b/drivers/gpu/drm/i915/display/intel_lt_phy_regs.h
@@ -35,6 +35,9 @@
 #define LT_PHY_TXY_CTL10_MAC(idx)	_MMIO(LT_PHY_TXY_CTL10(idx))
 #define  LT_PHY_TX_LANE_ENABLE		REG_BIT8(0)
 
+#define LT_PHY_CMN_CTL_0		(0x800)
+#define  LT_PHY_CMN_LFPS_ENABLE		REG_BIT8(1)
+
 /* LT Phy Vendor Register */
 #define LT_PHY_VDR_0_CONFIG	0xC02
 #define  LT_PHY_VDR_DP_PLL_ENABLE	REG_BIT(7)
-- 
2.29.0

[PATCH v5 12/15] drm/i915/alpm: Replace is_edp() with alpm_is_possible()

[Animesh Manna]

Add a separate alpm_is_possible() which will check for both edp and dp.

Cc: Jouni Högander <jouni.hogander@intel.com>
Signed-off-by: Animesh Manna <animesh.manna@intel.com>
---
 drivers/gpu/drm/i915/display/intel_alpm.c | 16 +++++++++++++---
 drivers/gpu/drm/i915/display/intel_alpm.h |  1 +
 2 files changed, 14 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_alpm.c b/drivers/gpu/drm/i915/display/intel_alpm.c
index d23f3bdf1339..f3f6f40f9624 100644
--- a/drivers/gpu/drm/i915/display/intel_alpm.c
+++ b/drivers/gpu/drm/i915/display/intel_alpm.c
@@ -72,6 +72,16 @@ void intel_alpm_init(struct intel_dp *intel_dp)
 	mutex_init(&intel_dp->alpm.lock);
 }
 
+bool intel_alpm_is_possible(struct intel_dp *intel_dp)
+{
+	struct intel_display *display = to_intel_display(intel_dp);
+
+	return (DISPLAY_VER(display) >= 12 && intel_dp->alpm_dpcd) ||
+		(DISPLAY_VER(display) >= 35 &&
+		intel_dp->lttpr_common_caps[DP_LTTPR_ALPM_CAPABILITIES -
+					    DP_LT_TUNABLE_PHY_REPEATER_FIELD_DATA_STRUCTURE_REV]);
+}
+
 static int get_silence_period_symbols(const struct intel_crtc_state *crtc_state)
 {
 	return SILENCE_PERIOD_TIME * intel_dp_link_symbol_clock(crtc_state->port_clock) /
@@ -519,7 +529,7 @@ void intel_alpm_lobf_compute_config(struct intel_dp *intel_dp,
 	if (intel_dp->alpm.sink_alpm_error)
 		return;
 
-	if (!intel_dp_is_edp(intel_dp))
+	if (!intel_alpm_is_possible(intel_dp))
 		return;
 
 	if (DISPLAY_VER(display) < 20)
@@ -685,7 +695,7 @@ void intel_alpm_lobf_disable(const struct intel_crtc_state *new_crtc_state)
 
 		intel_dp = enc_to_intel_dp(encoder);
 
-		if (!intel_dp_is_edp(intel_dp))
+		if (!intel_alpm_is_possible(intel_dp))
 			continue;
 
 		mutex_lock(&intel_dp->alpm.lock);
@@ -726,7 +736,7 @@ void intel_alpm_lobf_enable(const struct intel_crtc_state *new_crtc_state)
 
 		intel_dp = enc_to_intel_dp(encoder);
 
-		if (intel_dp_is_edp(intel_dp)) {
+		if (intel_alpm_is_possible(intel_dp)) {
 			intel_alpm_enable_sink(intel_dp, new_crtc_state);
 			intel_alpm_configure(intel_dp, new_crtc_state);
 		}
diff --git a/drivers/gpu/drm/i915/display/intel_alpm.h b/drivers/gpu/drm/i915/display/intel_alpm.h
index 7280865ed5f0..b0f6e2a9eede 100644
--- a/drivers/gpu/drm/i915/display/intel_alpm.h
+++ b/drivers/gpu/drm/i915/display/intel_alpm.h
@@ -18,6 +18,7 @@ struct intel_crtc;
 bool intel_alpm_source_supported(struct intel_connector *connector);
 void intel_alpm_init_dpcd(struct intel_dp *intel_dp);
 void intel_alpm_init(struct intel_dp *intel_dp);
+bool intel_alpm_is_possible(struct intel_dp *intel_dp);
 bool intel_alpm_compute_params(struct intel_dp *intel_dp,
 			       struct intel_crtc_state *crtc_state);
 void intel_alpm_lobf_compute_config(struct intel_dp *intel_dp,
-- 
2.29.0

Re: [PATCH v5 12/15] drm/i915/alpm: Replace is_edp() with alpm_is_possible()

[sashiko-bot]

Thank you for your contribution! Sashiko AI review found 2 potential issue(s) to consider:
- [High] Flawed logical OR (||) for LTTPR ALPM capabilities and incomplete feature integration.
- [Medium] DPCD capability registers are evaluated without applying capability bitmasks.
--

--- Patch [12]: [PATCH v5 12/15] drm/i915/alpm: Replace is_edp() with alpm_is_possible() ---
commit 7013cc56cbeba3729d838fd8bd915ecee9e1de24
Author: Animesh Manna <animesh.manna@intel.com>

drm/i915/alpm: Replace is_edp() with alpm_is_possible()

Add a separate alpm_is_possible() which will check for both edp and dp.

Cc: Jouni Högander <jouni.hogander@intel.com>

> diff --git a/drivers/gpu/drm/i915/display/intel_alpm.c b/drivers/gpu/drm/i915/display/intel_alpm.c
> index d23f3bdf13399..f3f6f40f96244 100644
> --- a/drivers/gpu/drm/i915/display/intel_alpm.c
> +++ b/drivers/gpu/drm/i915/display/intel_alpm.c

[ ... ]

> @@ -72,6 +72,16 @@ void intel_alpm_init(struct intel_dp *intel_dp)
>  	mutex_init(&intel_dp->alpm.lock);
>  }
>  
> +bool intel_alpm_is_possible(struct intel_dp *intel_dp)
> +{
> +	struct intel_display *display = to_intel_display(intel_dp);
> +
> +	return (DISPLAY_VER(display) >= 12 && intel_dp->alpm_dpcd) ||
> +		(DISPLAY_VER(display) >= 35 &&
> +		intel_dp->lttpr_common_caps[DP_LTTPR_ALPM_CAPABILITIES -
> +					    DP_LT_TUNABLE_PHY_REPEATER_FIELD_DATA_STRUCTURE_REV]);
> +}

[Severity: High]
Should this logical OR (||) be an AND (&&) for LTTPR capabilities? By using
OR, if the LTTPR supports ALPM but the sink does not (or vice versa), this
function will return true.

Could this lead to mismatched configurations? For example, if the LTTPR
supports ALPM but the sink doesn't, intel_alpm_enable_sink() will write
DP_ALPM_MODE_AUX_LESS to the sink's DP_RECEIVER_ALPM_CONFIG register even
though the sink lacks support.

Additionally, downstream functions like intel_alpm_lobf_compute_config()
exclusively check the sink's capability. Does using a logical OR here
effectively render the LTTPR check dead code in those paths?

[Severity: Medium]
Is it safe to evaluate the raw DPCD capability bytes (intel_dp->alpm_dpcd
and lttpr_common_caps) directly as booleans?

Since DPCD 0x02e is a bitfield containing multiple distinct bits (like
DP_ALPM_PM_STATE_2A_SUPPORT), a non-zero value doesn't necessarily mean
basic ALPM capability is supported.

Should this use existing helpers like intel_alpm_aux_wake_supported() or
explicitly apply the DP_ALPM_CAP bitmasks to prevent falsely detecting ALPM
support on reserved bits?

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20260825054536.3455704-1-animesh.manna@intel.com?part=12

[PATCH v5 13/15] drm/i915/alpm: Introduce has_alpm to decouple from pr/psr2/lobf

[Animesh Manna]

For DP2.1, ALPM is optional and there can be scenario where panel replay
will be supported without ALPM. So decouple ALPM feature by has_alpm flag
from related display features.

Cc: Jouni Högander <jouni.hogander@intel.com>
Signed-off-by: Animesh Manna <animesh.manna@intel.com>
---
 drivers/gpu/drm/i915/display/intel_alpm.c     | 19 +++------
 drivers/gpu/drm/i915/display/intel_alpm.h     |  2 -
 drivers/gpu/drm/i915/display/intel_cx0_phy.c  |  6 ++-
 .../drm/i915/display/intel_display_types.h    |  1 +
 drivers/gpu/drm/i915/display/intel_lt_phy.c   |  2 +-
 drivers/gpu/drm/i915/display/intel_psr.c      | 39 +++++++++----------
 drivers/gpu/drm/i915/display/intel_psr.h      |  1 -
 7 files changed, 30 insertions(+), 40 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_alpm.c b/drivers/gpu/drm/i915/display/intel_alpm.c
index f3f6f40f9624..8c17da9883d6 100644
--- a/drivers/gpu/drm/i915/display/intel_alpm.c
+++ b/drivers/gpu/drm/i915/display/intel_alpm.c
@@ -37,13 +37,6 @@ bool intel_alpm_aux_less_wake_supported(struct intel_dp *intel_dp)
 	return intel_dp->alpm_dpcd & DP_ALPM_AUX_LESS_CAP;
 }
 
-bool intel_alpm_is_alpm_aux_less(struct intel_dp *intel_dp,
-				 const struct intel_crtc_state *crtc_state)
-{
-	return intel_psr_needs_alpm_aux_less(intel_dp, crtc_state) ||
-		(crtc_state->has_lobf && intel_alpm_aux_less_wake_supported(intel_dp));
-}
-
 bool intel_alpm_source_supported(struct intel_connector *connector)
 {
 	struct intel_display *display = to_intel_display(connector);
@@ -513,6 +506,7 @@ void intel_alpm_lobf_compute_config_late(struct intel_dp *intel_dp,
 
 	crtc_state->has_lobf = (crtc_state->set_context_latency + crtc_state->vrr.guardband) >
 			       (first_sdp_position + waketime_in_lines);
+	crtc_state->has_alpm = crtc_state->has_lobf;
 }
 
 void intel_alpm_lobf_compute_config(struct intel_dp *intel_dp,
@@ -575,8 +569,7 @@ static void lnl_alpm_configure(struct intel_dp *intel_dp,
 	enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
 	u32 alpm_ctl, alpm_ctl2, lttpr_count;
 
-	if (DISPLAY_VER(display) < 20 || (!intel_psr_needs_alpm(intel_dp, crtc_state) &&
-					  !crtc_state->has_lobf))
+	if (DISPLAY_VER(display) < 20 || !crtc_state->has_alpm)
 		return;
 
 	mutex_lock(&intel_dp->alpm.lock);
@@ -584,7 +577,7 @@ static void lnl_alpm_configure(struct intel_dp *intel_dp,
 	 * Panel Replay on eDP is always using ALPM aux less. I.e. no need to
 	 * check panel support at this point.
 	 */
-	if (intel_alpm_is_alpm_aux_less(intel_dp, crtc_state)) {
+	if (intel_alpm_aux_less_wake_supported(intel_dp)) {
 		alpm_ctl = ALPM_CTL_ALPM_ENABLE |
 			ALPM_CTL_ALPM_AUX_LESS_ENABLE |
 			ALPM_CTL_AUX_LESS_SLEEP_HOLD_TIME_50_SYMBOLS;
@@ -648,10 +641,10 @@ void intel_alpm_port_configure(struct intel_dp *intel_dp,
 	enum port port = dp_to_dig_port(intel_dp)->base.port;
 	u32 alpm_ctl_val = 0, lfps_ctl_val = 0;
 
-	if (DISPLAY_VER(display) < 20)
+	if (DISPLAY_VER(display) < 20 || !crtc_state->has_alpm)
 		return;
 
-	if (intel_alpm_is_alpm_aux_less(intel_dp, crtc_state)) {
+	if (intel_alpm_aux_less_wake_supported(intel_dp)) {
 		int lfps_cycle = get_lfps_cycle_count(crtc_state);
 		u32 lfps_cycle_val;
 
@@ -710,7 +703,7 @@ void intel_alpm_enable_sink(struct intel_dp *intel_dp,
 {
 	u8 val;
 
-	if (!intel_psr_needs_alpm(intel_dp, crtc_state) && !crtc_state->has_lobf)
+	if (!crtc_state->has_alpm)
 		return;
 
 	val = DP_ALPM_ENABLE | DP_ALPM_LOCK_ERROR_IRQ_HPD_ENABLE;
diff --git a/drivers/gpu/drm/i915/display/intel_alpm.h b/drivers/gpu/drm/i915/display/intel_alpm.h
index b0f6e2a9eede..bca746d88da3 100644
--- a/drivers/gpu/drm/i915/display/intel_alpm.h
+++ b/drivers/gpu/drm/i915/display/intel_alpm.h
@@ -35,8 +35,6 @@ void intel_alpm_lobf_enable(const struct intel_crtc_state *new_crtc_state);
 void intel_alpm_lobf_debugfs_add(struct intel_connector *connector);
 bool intel_alpm_aux_wake_supported(struct intel_dp *intel_dp);
 bool intel_alpm_aux_less_wake_supported(struct intel_dp *intel_dp);
-bool intel_alpm_is_alpm_aux_less(struct intel_dp *intel_dp,
-				 const struct intel_crtc_state *crtc_state);
 void intel_alpm_disable(struct intel_dp *intel_dp);
 bool intel_alpm_get_error(struct intel_dp *intel_dp);
 void intel_alpm_lobf_compute_config_late(struct intel_dp *intel_dp,
diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy.c b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
index dbebd7210848..4ad09a894eb2 100644
--- a/drivers/gpu/drm/i915/display/intel_cx0_phy.c
+++ b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
@@ -3449,8 +3449,10 @@ void intel_lnl_mac_transmit_lfps(struct intel_encoder *encoder,
 	int i;
 	u8 owned_lane_mask;
 
-	if (DISPLAY_VER(display) < 20 ||
-	    !intel_alpm_is_alpm_aux_less(enc_to_intel_dp(encoder), crtc_state))
+	if (DISPLAY_VER(display) < 20 || !crtc_state->has_alpm)
+		return;
+
+	if (!intel_alpm_aux_less_wake_supported(enc_to_intel_dp(encoder)))
 		return;
 
 	owned_lane_mask = intel_cx0_get_owned_lane_mask(encoder);
diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
index 20a07ea06b5e..f8ac98ff8a87 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -1442,6 +1442,7 @@ struct intel_crtc_state {
 		u8 silence_period_sym_clocks;
 		u8 lfps_half_cycle_num_of_syms;
 	} alpm_state;
+	bool has_alpm;
 
 	/* to track changes in plane color blocks */
 	bool plane_color_changed;
diff --git a/drivers/gpu/drm/i915/display/intel_lt_phy.c b/drivers/gpu/drm/i915/display/intel_lt_phy.c
index 4fe010df20be..62607284c350 100644
--- a/drivers/gpu/drm/i915/display/intel_lt_phy.c
+++ b/drivers/gpu/drm/i915/display/intel_lt_phy.c
@@ -2371,7 +2371,7 @@ void intel_xe3plpd_mac_transmit_lfps(struct intel_encoder *encoder,
 	struct ref_tracker *wakeref;
 	u8 owned_lane_mask;
 
-	if (!intel_alpm_is_alpm_aux_less(intel_dp, crtc_state))
+	if (!crtc_state->has_alpm || !intel_alpm_aux_less_wake_supported(intel_dp))
 		return;
 
 	wakeref = intel_lt_phy_transaction_begin(encoder);
diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c
index 52836496040f..6a03bc624108 100644
--- a/drivers/gpu/drm/i915/display/intel_psr.c
+++ b/drivers/gpu/drm/i915/display/intel_psr.c
@@ -1648,6 +1648,8 @@ static bool intel_sel_update_config_valid(struct intel_crtc_state *crtc_state,
 	crtc_state->enable_psr2_su_region_et = psr2_su_region_et_valid(connector,
 								       crtc_state->has_panel_replay);
 
+	crtc_state->has_alpm = intel_alpm_is_possible(intel_dp);
+
 	return true;
 
 unsupported:
@@ -1735,11 +1737,17 @@ static bool _panel_replay_compute_config(struct intel_crtc_state *crtc_state,
 	crtc_state->link_off_after_as_sdp_when_pr_active = compute_link_off_after_as_sdp_when_pr_active(connector);
 	crtc_state->disable_as_sdp_when_pr_active = compute_disable_as_sdp_when_pr_active(connector);
 
+	if (intel_alpm_is_possible(intel_dp))
+		crtc_state->has_alpm = alpm_config_valid(intel_dp, crtc_state, true, true, false);
+
 	if (!intel_dp_is_edp(intel_dp))
 		return true;
 
 	/* Remaining checks are for eDP only */
 
+	if (!crtc_state->has_alpm)
+		return false;
+
 	if (to_intel_crtc(crtc_state->uapi.crtc)->pipe != PIPE_A &&
 	    to_intel_crtc(crtc_state->uapi.crtc)->pipe != PIPE_B)
 		return false;
@@ -1762,9 +1770,6 @@ static bool _panel_replay_compute_config(struct intel_crtc_state *crtc_state,
 		return false;
 	}
 
-	if (!alpm_config_valid(intel_dp, crtc_state, true, true, false))
-		return false;
-
 	return true;
 }
 
@@ -4530,16 +4535,6 @@ void intel_psr_connector_debugfs_add(struct intel_connector *connector)
 				    connector, &i915_psr_status_fops);
 }
 
-bool intel_psr_needs_alpm(struct intel_dp *intel_dp, const struct intel_crtc_state *crtc_state)
-{
-	/*
-	 * eDP Panel Replay uses always ALPM
-	 * PSR2 uses ALPM but PSR1 doesn't
-	 */
-	return intel_dp_is_edp(intel_dp) && (crtc_state->has_sel_update ||
-					     crtc_state->has_panel_replay);
-}
-
 bool intel_psr_needs_alpm_aux_less(struct intel_dp *intel_dp,
 				   const struct intel_crtc_state *crtc_state)
 {
@@ -4553,15 +4548,17 @@ void intel_psr_compute_config_late(struct intel_dp *intel_dp,
 	int vblank = intel_crtc_vblank_length(crtc_state);
 	int wake_lines;
 
-	if (intel_psr_needs_alpm_aux_less(intel_dp, crtc_state))
-		wake_lines = crtc_state->alpm_state.aux_less_wake_lines;
-	else if (intel_psr_needs_alpm(intel_dp, crtc_state))
-		wake_lines = DISPLAY_VER(display) < 20 ?
-			     psr2_block_count_lines(crtc_state->alpm_state.io_wake_lines,
-						    crtc_state->alpm_state.fast_wake_lines) :
-			     crtc_state->alpm_state.io_wake_lines;
-	else
+	if (crtc_state->has_alpm) {
+		if (intel_alpm_aux_less_wake_supported(intel_dp))
+			wake_lines = crtc_state->alpm_state.aux_less_wake_lines;
+		else
+			wake_lines = DISPLAY_VER(display) < 20 ?
+				     psr2_block_count_lines(crtc_state->alpm_state.io_wake_lines,
+							    crtc_state->alpm_state.fast_wake_lines) :
+				     crtc_state->alpm_state.io_wake_lines;
+	} else {
 		wake_lines = 0;
+	}
 
 	/*
 	 * Disable the PSR features if wake lines exceed the available vblank.
diff --git a/drivers/gpu/drm/i915/display/intel_psr.h b/drivers/gpu/drm/i915/display/intel_psr.h
index d545fdaa0de7..4905ba4da4b8 100644
--- a/drivers/gpu/drm/i915/display/intel_psr.h
+++ b/drivers/gpu/drm/i915/display/intel_psr.h
@@ -79,7 +79,6 @@ void intel_psr_trigger_frame_change_event(struct intel_dsb *dsb,
 int intel_psr_min_set_context_latency(const struct intel_crtc_state *crtc_state);
 void intel_psr_connector_debugfs_add(struct intel_connector *connector);
 void intel_psr_debugfs_register(struct intel_display *display);
-bool intel_psr_needs_alpm(struct intel_dp *intel_dp, const struct intel_crtc_state *crtc_state);
 bool intel_psr_needs_alpm_aux_less(struct intel_dp *intel_dp,
 				   const struct intel_crtc_state *crtc_state);
 void intel_psr_compute_config_late(struct intel_dp *intel_dp,
-- 
2.29.0

Re: [PATCH v5 13/15] drm/i915/alpm: Introduce has_alpm to decouple from pr/psr2/lobf

[sashiko-bot]

Thank you for your contribution! Sashiko AI review found 3 potential issue(s) to consider:
- [High] Source/sink protocol mismatch for PSR2 panels with AUX-less capability.
- [High] State leakage of the `has_alpm` flag forces ALPM on unsupported PSR1 fallbacks.
- [High] Inconsistent ALPM wake line validation causes unsafe late atomic state downgrades.
--

--- Patch [13]: [PATCH v5 13/15] drm/i915/alpm: Introduce has_alpm to decouple from pr/psr2/lobf ---
commit dd0c0bc3be20db88d8488b6083be9663dc32cc6d
Author: Animesh Manna <animesh.manna@intel.com>
Subject: drm/i915/alpm: Introduce has_alpm to decouple from pr/psr2/lobf

For DP2.1, ALPM is optional and there can be scenario where panel replay
will be supported without ALPM. So decouple ALPM feature by has_alpm flag
from related display features.

> diff --git a/drivers/gpu/drm/i915/display/intel_alpm.c b/drivers/gpu/drm/i915/display/intel_alpm.c
> index f3f6f40f96244..8c17da9883d6d 100644
> --- a/drivers/gpu/drm/i915/display/intel_alpm.c
> +++ b/drivers/gpu/drm/i915/display/intel_alpm.c

[ ... ]

> @@ -575,8 +569,7 @@ static void lnl_alpm_configure(struct intel_dp *intel_dp,
>  	enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
>  	u32 alpm_ctl, alpm_ctl2, lttpr_count;
>  
> -	if (DISPLAY_VER(display) < 20 || (!intel_psr_needs_alpm(intel_dp, crtc_state) &&
> -					  !crtc_state->has_lobf))
> +	if (DISPLAY_VER(display) < 20 || !crtc_state->has_alpm)
>  		return;
>  
>  	mutex_lock(&intel_dp->alpm.lock);
> @@ -584,7 +577,7 @@ static void lnl_alpm_configure(struct intel_dp *intel_dp,
>  	 * Panel Replay on eDP is always using ALPM aux less. I.e. no need to
>  	 * check panel support at this point.
>  	 */
> -	if (intel_alpm_is_alpm_aux_less(intel_dp, crtc_state)) {
> +	if (intel_alpm_aux_less_wake_supported(intel_dp)) {
>  		alpm_ctl = ALPM_CTL_ALPM_ENABLE |
>  			ALPM_CTL_ALPM_AUX_LESS_ENABLE |
>  			ALPM_CTL_AUX_LESS_SLEEP_HOLD_TIME_50_SYMBOLS;

[Severity: High]
Does this create a protocol mismatch between the source and the sink?

By changing this to rely on intel_alpm_aux_less_wake_supported(), the source
is now programmed for AUX-less ALPM (ALPM_CTL_ALPM_AUX_LESS_ENABLE) for PSR2
panels that advertise DP_ALPM_AUX_LESS_CAP.

However, intel_alpm_enable_sink() still requires Panel Replay or LOBF to
enable AUX-less mode on the sink. Because neither is true for PSR2, the sink
will be expecting fast-wake ALPM, which conflicts with how the source is
now programmed here.

[ ... ]

> diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c
> index 40e3d70959965..8c6aa4e948894 100644
> --- a/drivers/gpu/drm/i915/display/intel_psr.c
> +++ b/drivers/gpu/drm/i915/display/intel_psr.c

[ ... ]

> @@ -1729,11 +1731,17 @@ static bool _panel_replay_compute_config(struct intel_crtc_state *crtc_state,
>  	crtc_state->link_off_after_as_sdp_when_pr_active = compute_link_off_after_as_sdp_when_pr_active(connector);
>  	crtc_state->disable_as_sdp_when_pr_active = compute_disable_as_sdp_when_pr_active(connector);
>  
> +	if (intel_alpm_is_possible(intel_dp))
> +		crtc_state->has_alpm = alpm_config_valid(intel_dp, crtc_state, true, true, false);
> +
>  	if (!intel_dp_is_edp(intel_dp))
>  		return true;
>  
>  	/* Remaining checks are for eDP only */
>  
> +	if (!crtc_state->has_alpm)
> +		return false;
> +
>  	if (to_intel_crtc(crtc_state->uapi.crtc)->pipe != PIPE_A &&
>  	    to_intel_crtc(crtc_state->uapi.crtc)->pipe != PIPE_B)
>  		return false;

[Severity: High]
Can this leak the has_alpm state if the panel replay config is aborted?

If alpm_config_valid() succeeds, crtc_state->has_alpm is set to true.
However, if a subsequent check in _panel_replay_compute_config() returns
false (such as the PIPE_A/B check or a later HDCP check), has_alpm remains
set to true.

When the driver then falls back to computing PSR1, has_alpm stays true and
bypasses the previous protections that prevented ALPM from being enabled
on PSR1. This forces ALPM on for PSR1 fallbacks where it is not supported.

[ ... ]

> @@ -4547,15 +4542,17 @@ void intel_psr_compute_config_late(struct intel_dp *intel_dp,
>  	int vblank = intel_crtc_vblank_length(crtc_state);
>  	int wake_lines;
>  
> -	if (intel_psr_needs_alpm_aux_less(intel_dp, crtc_state))
> -		wake_lines = crtc_state->alpm_state.aux_less_wake_lines;
> -	else if (intel_psr_needs_alpm(intel_dp, crtc_state))
> -		wake_lines = DISPLAY_VER(display) < 20 ?
> -			     psr2_block_count_lines(crtc_state->alpm_state.io_wake_lines,
> -						    crtc_state->alpm_state.fast_wake_lines) :
> -			     crtc_state->alpm_state.io_wake_lines;
> -	else
> +	if (crtc_state->has_alpm) {
> +		if (intel_alpm_aux_less_wake_supported(intel_dp))
> +			wake_lines = crtc_state->alpm_state.aux_less_wake_lines;
> +		else
> +			wake_lines = DISPLAY_VER(display) < 20 ?
> +				     psr2_block_count_lines(crtc_state->alpm_state.io_wake_lines,
> +							    crtc_state->alpm_state.fast_wake_lines) :
> +				     crtc_state->alpm_state.io_wake_lines;
> +	} else {
>  		wake_lines = 0;
> +	}
>  
>  	/*
>  	 * Disable the PSR features if wake lines exceed the available vblank.

[Severity: High]
Does this late selection of aux_less_wake_lines conflict with the early
validation performed for PSR2?

During early validation, intel_psr2_config_valid() hardcodes the aux_less
parameter to false when calling alpm_config_valid(), so it validates
against the smaller io_wake_lines.

If intel_alpm_aux_less_wake_supported() evaluates to true here in late
compute, it will dynamically select the larger aux_less_wake_lines instead. 
This mismatch can cause the subsequent _wake_lines_fit_into_vblank() check
to fail, triggering a late teardown of has_sel_update after watermarks and
DDB allocations have already been computed assuming PSR/SU was active.

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20260825054536.3455704-1-animesh.manna@intel.com?part=13

[PATCH v5 14/15] drm/i915/alpm: Compute and program switch to active latency

[Animesh Manna]

Program the ALPM switch to active latency into ALPM_CTL2. For UHBR link
rates the latency is derived from the link symbol clock and converted to
scanlines, for non-UHBR rates it is zero.

Cc: Jouni Högander <jouni.hogander@intel.com>
Signed-off-by: Animesh Manna <animesh.manna@intel.com>
---
 drivers/gpu/drm/i915/display/intel_alpm.c     | 32 +++++++++++++++++--
 .../drm/i915/display/intel_display_types.h    |  1 +
 2 files changed, 31 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_alpm.c b/drivers/gpu/drm/i915/display/intel_alpm.c
index 8c17da9883d6..5d2ac7561567 100644
--- a/drivers/gpu/drm/i915/display/intel_alpm.c
+++ b/drivers/gpu/drm/i915/display/intel_alpm.c
@@ -270,6 +270,31 @@ static int get_establishment_period(struct intel_dp *intel_dp,
 	return establishment_period;
 }
 
+
+static int get_switch_to_active(const struct intel_crtc_state *crtc_state)
+{
+	int port_clock = crtc_state->port_clock;
+	int switch_to_active;
+
+	if (intel_dp_is_uhbr(crtc_state)) {
+		/* symbol_clock (fLink) in MHz */
+		int symbol_clock = port_clock / intel_dp_link_symbol_size(port_clock) / 100;
+
+		/*
+		 * tSwitch to Active = 32 * (ML_PHY_LOCK Length + 3 + 64) / fLink
+		 *
+		 * The "+ 3" term is the trailing zero padding after the
+		 * POST_LT_SCRAMBLER_RESET, the "+ 64" term represents the MTP
+		 * time slots. The result is in microseconds.
+		 */
+		switch_to_active = 32 * ((396 + 3 + 64) / symbol_clock);
+	} else {
+		switch_to_active = 0;
+	}
+
+	return switch_to_active;
+}
+
 /*
  * AUX-Less Wake Time = CEILING( ((PHY P2 to P0) + tLFPS_Period, Max+
  * tSilence, Max+ tPHY Establishment + tCDS) / tline)
@@ -329,7 +354,8 @@ _lnl_compute_aux_less_alpm_params(struct intel_dp *intel_dp,
 	crtc_state->alpm_state.aux_less_wake_lines = aux_less_wake_lines;
 	crtc_state->alpm_state.silence_period_sym_clocks = silence_period;
 	crtc_state->alpm_state.lfps_half_cycle_num_of_syms = lfps_half_cycle;
-
+	crtc_state->alpm_state.switch_to_active = intel_usecs_to_scanlines(&crtc_state->hw.adjusted_mode,
+									   get_switch_to_active(crtc_state));
 	return true;
 }
 
@@ -619,8 +645,10 @@ static void lnl_alpm_configure(struct intel_dp *intel_dp,
 	lttpr_count = drm_dp_lttpr_count(intel_dp->lttpr_common_caps);
 
 	alpm_ctl2 = intel_de_read(display, ALPM_CTL2(display, cpu_transcoder));
-	alpm_ctl2 &= ~ALPM_CTL2_NUMBER_OF_LTTPR_MASK;
+	alpm_ctl2 &= ~(ALPM_CTL2_NUMBER_OF_LTTPR_MASK |
+		       ALPM_CTL2_SWITCH_TO_ACTIVE_LATENCY_MASK);
 	alpm_ctl2 |= ALPM_CTL2_NUMBER_OF_LTTPR(lttpr_count);
+	alpm_ctl2 |= ALPM_CTL2_SWITCH_TO_ACTIVE_LATENCY(crtc_state->alpm_state.switch_to_active);
 
 	intel_de_write(display, ALPM_CTL2(display, cpu_transcoder), alpm_ctl2);
 	intel_de_write(display, ALPM_CTL(display, cpu_transcoder), alpm_ctl);
diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
index f8ac98ff8a87..4cbf56a9195f 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -1441,6 +1441,7 @@ struct intel_crtc_state {
 		u8 aux_less_wake_lines;
 		u8 silence_period_sym_clocks;
 		u8 lfps_half_cycle_num_of_syms;
+		int switch_to_active;
 	} alpm_state;
 	bool has_alpm;
 
-- 
2.29.0

Re: [PATCH v5 14/15] drm/i915/alpm: Compute and program switch to active latency

[sashiko-bot]

Thank you for your contribution! Sashiko AI review found 2 potential issue(s) to consider:
- [High] Severe integer arithmetic precision loss in `get_switch_to_active` calculates a latency of 0 for UHBR20 links and incorrect values for other UHBR links.
- [Medium] Missing bounds validation for the computed `switch_to_active` scanline value.
--

--- Patch [14]: [PATCH v5 14/15] drm/i915/alpm: Compute and program switch to active latency ---
commit c70c27fb353539a13b15cf08616e266e5b7146a1
Author: Animesh Manna <animesh.manna@intel.com>

drm/i915/alpm: Compute and program switch to active latency

This commit programs the ALPM switch-to-active latency into ALPM_CTL2. For
UHBR link rates, the latency is derived from the link symbol clock and
converted to scanlines. For non-UHBR rates, the latency is zero.

> diff --git a/drivers/gpu/drm/i915/display/intel_alpm.c b/drivers/gpu/drm/i915/display/intel_alpm.c
> index 8c17da9883d6d..5d2ac75615670 100644
> --- a/drivers/gpu/drm/i915/display/intel_alpm.c
> +++ b/drivers/gpu/drm/i915/display/intel_alpm.c

[ ... ]

> @@ -270,6 +270,31 @@ static int get_establishment_period(struct intel_dp *intel_dp,
>  	return establishment_period;
>  }
>  
> +
> +static int get_switch_to_active(const struct intel_crtc_state *crtc_state)
> +{
> +	int port_clock = crtc_state->port_clock;
> +	int switch_to_active;
> +
> +	if (intel_dp_is_uhbr(crtc_state)) {
> +		/* symbol_clock (fLink) in MHz */
> +		int symbol_clock = port_clock / intel_dp_link_symbol_size(port_clock) / 100;
> +
> +		/*
> +		 * tSwitch to Active = 32 * (ML_PHY_LOCK Length + 3 + 64) / fLink
> +		 *
> +		 * The "+ 3" term is the trailing zero padding after the
> +		 * POST_LT_SCRAMBLER_RESET, the "+ 64" term represents the MTP
> +		 * time slots. The result is in microseconds.
> +		 */
> +		switch_to_active = 32 * ((396 + 3 + 64) / symbol_clock);

[Severity: High]
Does this calculation lose precision by performing the division before the
multiplication?

For a UHBR20 link where symbol_clock is 625 MHz, the integer division
(396 + 3 + 64) / 625 will yield 0, resulting in a switch_to_active latency
of 0.

For UHBR10 (312 MHz) and UHBR13.5 (421 MHz), the division will yield 1,
making the result 32 instead of the mathematically correct values of ~47
and ~35, respectively.

Should this multiply before dividing, perhaps using DIV_ROUND_UP()?

> +	} else {
> +		switch_to_active = 0;
> +	}
> +
> +	return switch_to_active;
> +}
> +
>  /*
>   * AUX-Less Wake Time = CEILING( ((PHY P2 to P0) + tLFPS_Period, Max+
>   * tSilence, Max+ tPHY Establishment + tCDS) / tline)

[ ... ]

> @@ -329,7 +354,8 @@ _lnl_compute_aux_less_alpm_params(struct intel_dp *intel_dp,
>  	crtc_state->alpm_state.aux_less_wake_lines = aux_less_wake_lines;
>  	crtc_state->alpm_state.silence_period_sym_clocks = silence_period;
>  	crtc_state->alpm_state.lfps_half_cycle_num_of_syms = lfps_half_cycle;
> -
> +	crtc_state->alpm_state.switch_to_active = intel_usecs_to_scanlines(&crtc_state->hw.adjusted_mode,
> +									   get_switch_to_active(crtc_state));

[Severity: Medium]
Is it possible for the computed scanline value to exceed the hardware limits?

Earlier in _lnl_compute_aux_less_alpm_params(), values like
aux_less_wake_lines and silence_period are checked against their hardware
bounds, and the function returns false if they exceed limits to safely reject
the configuration.

However, switch_to_active is programmed into a 5-bit register field
(ALPM_CTL2_SWITCH_TO_ACTIVE_LATENCY_MASK). If the converted scanline value
exceeds 31, it will be silently truncated when passed to the macro in
lnl_alpm_configure().

Should there be a bounds check for switch_to_active before applying it?

>  	return true;
>  }

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20260825054536.3455704-1-animesh.manna@intel.com?part=14

[PATCH v5 15/15] drm/i915/alpm: Program zero-based LFPS half cycle duration

[Animesh Manna]

The LFPS Half Cycle Duration field, as well as the First and Last LFPS
Half Cycle Duration fields, in PORT_ALPM_LFPS_CTL are zero-based: per
Bspec the value programmed must be N_Symbol - 1. get_lfps_half_cycle_clocks()
returned N_Symbol and programmed it directly into all three fields, making
each half cycle one symbol clock too long.

Return N_Symbol - 1 so the programmed value matches the zero-based field
encoding.

Bspec: 71632
Cc: Jouni Högander <jouni.hogander@intel.com>
Assisted-by: Claude:claude-opus-4-8
Signed-off-by: Animesh Manna <animesh.manna@intel.com>
---
 drivers/gpu/drm/i915/display/intel_alpm.c | 12 ++++++++++--
 1 file changed, 10 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_alpm.c b/drivers/gpu/drm/i915/display/intel_alpm.c
index 5d2ac7561567..9768279f94ef 100644
--- a/drivers/gpu/drm/i915/display/intel_alpm.c
+++ b/drivers/gpu/drm/i915/display/intel_alpm.c
@@ -123,8 +123,16 @@ static int get_lfps_cycle_count(const struct intel_crtc_state *crtc_state)
 
 static int get_lfps_half_cycle_clocks(const struct intel_crtc_state *crtc_state)
 {
-	return get_lfps_cycle_time(crtc_state) * crtc_state->port_clock / 1000 /
-		1000 / (2 * get_lfps_cycle_count(crtc_state));
+	int n_symbols = get_lfps_cycle_time(crtc_state) * crtc_state->port_clock /
+			1000 / 1000 / (2 * get_lfps_cycle_count(crtc_state));
+
+	/*
+	 * The LFPS half cycle duration fields (including the first and last
+	 * half cycle) are zero-based, i.e. the value programmed is N_Symbol - 1.
+	 *
+	 * Bspec: 71632
+	 */
+	return n_symbols - 1;
 }
 
 #define ML_PHY_LOCK_LEN		252
-- 
2.29.0

Re: [PATCH v5 15/15] drm/i915/alpm: Program zero-based LFPS half cycle duration

[sashiko-bot]

Thank you for your contribution! Sashiko AI review found 3 potential issue(s) to consider:

Pre-existing issues:
- [High] Calculation of LFPS half cycle clocks incorrectly uses the link bit rate instead of the symbol clock, breaking UHBR configurations.
- [High] Signed 32-bit integer overflow in `get_establishment_period()` causes ALPM wake times to be calculated as negative values.
- [High] Premature integer division in `get_switch_to_active()` causes switch-to-active latency to incorrectly evaluate to 0 for UHBR20.
--

--- Patch [15]: [PATCH v5 15/15] drm/i915/alpm: Program zero-based LFPS half cycle duration ---
commit 6cd79e290a7ff8352dbda337c2c68d7456099444
Author: Animesh Manna <animesh.manna@intel.com>

drm/i915/alpm: Program zero-based LFPS half cycle duration

The LFPS Half Cycle Duration field, as well as the First and Last LFPS
Half Cycle Duration fields, in PORT_ALPM_LFPS_CTL are zero-based: per
Bspec the value programmed must be N_Symbol - 1. get_lfps_half_cycle_clocks()
returned N_Symbol and programmed it directly into all three fields, making
each half cycle one symbol clock too long.

> diff --git a/drivers/gpu/drm/i915/display/intel_alpm.c b/drivers/gpu/drm/i915/display/intel_alpm.c
> index 5d2ac75615670..9768279f94ef5 100644
> --- a/drivers/gpu/drm/i915/display/intel_alpm.c
> +++ b/drivers/gpu/drm/i915/display/intel_alpm.c
> @@ -123,8 +123,16 @@ static int get_lfps_cycle_count(const struct intel_crtc_state *crtc_state)
>  
>  static int get_lfps_half_cycle_clocks(const struct intel_crtc_state *crtc_state)
>  {
> -	return get_lfps_cycle_time(crtc_state) * crtc_state->port_clock / 1000 /
> -		1000 / (2 * get_lfps_cycle_count(crtc_state));
> +	int n_symbols = get_lfps_cycle_time(crtc_state) * crtc_state->port_clock /
> +			1000 / 1000 / (2 * get_lfps_cycle_count(crtc_state));

[Severity: High]
This is a pre-existing issue, but does this correctly calculate the frequency
multiplier for UHBR configurations?

For UHBR encoding (128b/132b), the symbol clock in kHz is
port_clock * 10 / 32, not port_clock. When used for UHBR20, using the
inflated bit rate results in n_symbols - 1 = 59, which exceeds
PORT_ALPM_LFPS_CTL_LAST_LFPS_HALF_CYCLE_DURATION_MASK (31).

Could this cause validation to fail and completely disable ALPM on UHBR
displays?

> +
> +	/*
> +	 * The LFPS half cycle duration fields (including the first and last
> +	 * half cycle) are zero-based, i.e. the value programmed is N_Symbol - 1.
> +	 *
> +	 * Bspec: 71632
> +	 */
> +	return n_symbols - 1;
>  }

[ ... ]

> static int get_establishment_period(struct intel_dp *intel_dp,
> 				    const struct intel_crtc_state *crtc_state)
> {
[ ... ]
> 	int tps4 = intel_dp_is_uhbr(crtc_state) ? (ML_PHY_LOCK_LEN_UHBR * 32) :
> 		   (ML_PHY_LOCK_LEN * 10);
> 	/* port_clock is link rate in 10kbit/s units */
> 	int tml_phy_lock = 1000 * 1000 * tps4 / crtc_state->port_clock / 10;

[Severity: High]
This isn't a bug introduced by this patch, but can this intermediate
expression overflow?

The sub-expression "1000 * 1000 * tps4" evaluates using signed 32-bit
arithmetic. For non-UHBR links, tps4 is 2520, making the result
2,520,000,000. Since this exceeds INT_MAX (2,147,483,647), it wraps around
to -1,774,967,296.

Does this negative value propagate through to the final establishment_period,
causing incorrect ALPM hardware programming?

[ ... ]

> static int get_switch_to_active(const struct intel_crtc_state *crtc_state)
> {
[ ... ]
> 	if (intel_dp_is_uhbr(crtc_state)) {
> 		/* symbol_clock (fLink) in MHz */
> 		int symbol_clock = port_clock / intel_dp_link_symbol_size(port_clock) / 100;
> 
> 		/*
> 		 * tSwitch to Active = 32 * (ML_PHY_LOCK Length + 3 + 64) / fLink
> 		 *
> 		 * The "+ 3" term is the trailing zero padding after the
> 		 * POST_LT_SCRAMBLER_RESET, the "+ 64" term represents the MTP
> 		 * time slots. The result is in microseconds.
> 		 */
> 		switch_to_active = 32 * ((396 + 3 + 64) / symbol_clock);

[Severity: High]
This is a pre-existing issue, but does this integer division evaluate to 0
for UHBR20 links?

The expression "396 + 3 + 64" equals 463. For a UHBR20 link, symbol_clock is
625 MHz. The integer division 463 / 625 truncates to 0, resulting in an
overall latency of 0 scanlines instead of the intended ~23 microseconds.

Could this zero-latency configuration break the link state machine recovery
for UHBR20 displays?

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20260825054536.3455704-1-animesh.manna@intel.com?part=15

✗ CI.checkpatch: warning for Enable DP2.1 alpm (rev5)

[Patchwork]

== Series Details ==

Series: Enable DP2.1 alpm (rev5)
URL   : https://patchwork.freedesktop.org/series/156416/
State : warning

== Summary ==

+ KERNEL=/kernel
+ git clone https://gitlab.freedesktop.org/drm/maintainer-tools mt
Cloning into 'mt'...
warning: redirecting to https://gitlab.freedesktop.org/drm/maintainer-tools.git/
+ git -C mt rev-list -n1 origin/master
061140b9bc586ae7f40abc1249c97e1cc72d1b9d
+ cd /kernel
+ git config --global --add safe.directory /kernel
+ git log -n1
commit 130dc5547864e3c936033feea09c35b4aabd0199
Author: Animesh Manna <animesh.manna@intel.com>
Date:   Tue Aug 25 11:15:36 2026 +0530

    drm/i915/alpm: Program zero-based LFPS half cycle duration
    
    The LFPS Half Cycle Duration field, as well as the First and Last LFPS
    Half Cycle Duration fields, in PORT_ALPM_LFPS_CTL are zero-based: per
    Bspec the value programmed must be N_Symbol - 1. get_lfps_half_cycle_clocks()
    returned N_Symbol and programmed it directly into all three fields, making
    each half cycle one symbol clock too long.
    
    Return N_Symbol - 1 so the programmed value matches the zero-based field
    encoding.
    
    Bspec: 71632
    Cc: Jouni Högander <jouni.hogander@intel.com>
    Assisted-by: Claude:claude-opus-4-8
    Signed-off-by: Animesh Manna <animesh.manna@intel.com>
+ /mt/dim checkpatch 15e2ba2fb6d25c03d89519aec46f8d5be3e118ad drm-intel
c04b8267f0cb drm/i915/alpm: Add DPCD definition for DP2.1 ALPM capability
f427829ab1c8 drm/i915/alpm: Move alpm sink capabality readout in separate function
e392a9445d08 drm/i915/alpm: alpm_init() for DP2.1
390f6cacdec7 drm/i915/alpm: Enable debugfs for DP2.1
c4093d992fc9 drm/i915/alpm: Refactor Auxless wake time calculation
3fbdd9a7669e drm/i915/alpm: Auxless wake time calculation for Xe3p
-:122: WARNING:LONG_LINE: line length of 108 exceeds 100 columns
#122: FILE: drivers/gpu/drm/i915/display/intel_alpm.c:469:
+			alpm_ctl |= ALPM_CTL_AUX_LESS_WAKE_TIME(crtc_state->alpm_state.aux_less_wake_lines);

-:124: WARNING:LONG_LINE: line length of 115 exceeds 100 columns
#124: FILE: drivers/gpu/drm/i915/display/intel_alpm.c:471:
+			alpm_ctl |= ALPM_CTL_AUX_LESS_WAKE_TIME_XE3LPD(crtc_state->alpm_state.aux_less_wake_lines);

-:138: WARNING:LONG_LINE: line length of 116 exceeds 100 columns
#138: FILE: drivers/gpu/drm/i915/display/intel_psr_regs.h:304:
+#define  ALPM_CTL_AUX_LESS_WAKE_TIME_XE3LPD(val)	REG_FIELD_PREP(ALPM_CTL_AUX_LESS_WAKE_TIME_MASK_XE3LPD, val)

total: 0 errors, 3 warnings, 0 checks, 106 lines checked
d5c6768df5ab drm/i915/alpm: table based establishment period
505b3b961aa5 drm/i915/alpm: Half LFPS cycle calculation
f19c517b0d09 drm/i915/alpm: Modify LFPS cycle count for DP ALPM
-:82: WARNING:LONG_LINE: line length of 176 exceeds 100 columns
#82: FILE: drivers/gpu/drm/i915/display/intel_psr_regs.h:339:
+#define  PORT_ALPM_LFPS_CTL_LFPS_CYCLE_COUNT_XE3LPD(val)	REG_FIELD_PREP(PORT_ALPM_LFPS_CTL_LFPS_CYCLE_COUNT_MASK_XE3LPD, (val) - PORT_ALPM_LFPS_CTL_LFPS_CYCLE_COUNT_MIN)

total: 0 errors, 1 warnings, 0 checks, 64 lines checked
531553729eeb drm/i915/alpm: Program LTTPR count for DP 2.1 ALPM
a079bb115bc9 drm/i915/alpm: Enable MAC Transmitting LFPS for LT PHY
c33ffa3dd09b drm/i915/alpm: Replace is_edp() with alpm_is_possible()
1cbd31f1fd9e drm/i915/alpm: Introduce has_alpm to decouple from pr/psr2/lobf
-:215: WARNING:LONG_LINE: line length of 101 exceeds 100 columns
#215: FILE: drivers/gpu/drm/i915/display/intel_psr.c:4557:
+							    crtc_state->alpm_state.fast_wake_lines) :

total: 0 errors, 1 warnings, 0 checks, 174 lines checked
5d109dc7ba1a drm/i915/alpm: Compute and program switch to active latency
-:24: CHECK:LINE_SPACING: Please don't use multiple blank lines
#24: FILE: drivers/gpu/drm/i915/display/intel_alpm.c:273:
 
+

-:57: WARNING:LONG_LINE: line length of 105 exceeds 100 columns
#57: FILE: drivers/gpu/drm/i915/display/intel_alpm.c:357:
+	crtc_state->alpm_state.switch_to_active = intel_usecs_to_scanlines(&crtc_state->hw.adjusted_mode,

-:58: WARNING:LONG_LINE: line length of 109 exceeds 100 columns
#58: FILE: drivers/gpu/drm/i915/display/intel_alpm.c:358:
+									   get_switch_to_active(crtc_state));

total: 0 errors, 2 warnings, 1 checks, 58 lines checked
130dc5547864 drm/i915/alpm: Program zero-based LFPS half cycle duration
-:11: WARNING:COMMIT_LOG_LONG_LINE: Prefer a maximum 75 chars per line (possible unwrapped commit description?)
#11: 
Bspec the value programmed must be N_Symbol - 1. get_lfps_half_cycle_clocks()

total: 0 errors, 1 warnings, 0 checks, 18 lines checked

✓ CI.KUnit: success for Enable DP2.1 alpm (rev5)

[Patchwork]

== Series Details ==

Series: Enable DP2.1 alpm (rev5)
URL   : https://patchwork.freedesktop.org/series/156416/
State : success

== Summary ==

+ trap cleanup EXIT
+ /kernel/tools/testing/kunit/kunit.py run --kunitconfig /kernel/drivers/gpu/drm/xe/.kunitconfig
[07:59:54] Configuring KUnit Kernel ...
Generating .config ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
[07:59:58] Building KUnit Kernel ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
Building with:
$ make all compile_commands.json scripts_gdb ARCH=um O=.kunit --jobs=48
[08:00:31] Starting KUnit Kernel (1/1)...
[08:00:31] ============================================================
Running tests with:
$ .kunit/linux kunit.enable=1 mem=1G console=tty kunit_shutdown=halt
[08:00:31] ================== guc_buf (11 subtests) ===================
[08:00:31] [PASSED] test_smallest
[08:00:31] [PASSED] test_largest
[08:00:31] [PASSED] test_granular
[08:00:31] [PASSED] test_unique
[08:00:31] [PASSED] test_overlap
[08:00:31] [PASSED] test_reusable
[08:00:31] [PASSED] test_too_big
[08:00:31] [PASSED] test_flush
[08:00:31] [PASSED] test_lookup
[08:00:31] [PASSED] test_data
[08:00:31] [PASSED] test_class
[08:00:31] ===================== [PASSED] guc_buf =====================
[08:00:31] =================== guc_dbm (7 subtests) ===================
[08:00:31] [PASSED] test_empty
[08:00:31] [PASSED] test_default
[08:00:31] ======================== test_size  ========================
[08:00:31] [PASSED] 4
[08:00:31] [PASSED] 8
[08:00:31] [PASSED] 32
[08:00:31] [PASSED] 256
[08:00:31] ==================== [PASSED] test_size ====================
[08:00:31] ======================= test_reuse  ========================
[08:00:31] [PASSED] 4
[08:00:31] [PASSED] 8
[08:00:31] [PASSED] 32
[08:00:31] [PASSED] 256
[08:00:31] =================== [PASSED] test_reuse ====================
[08:00:31] =================== test_range_overlap  ====================
[08:00:31] [PASSED] 4
[08:00:31] [PASSED] 8
[08:00:31] [PASSED] 32
[08:00:31] [PASSED] 256
[08:00:31] =============== [PASSED] test_range_overlap ================
[08:00:31] =================== test_range_compact  ====================
[08:00:31] [PASSED] 4
[08:00:31] [PASSED] 8
[08:00:31] [PASSED] 32
[08:00:31] [PASSED] 256
[08:00:31] =============== [PASSED] test_range_compact ================
[08:00:31] ==================== test_range_spare  =====================
[08:00:31] [PASSED] 4
[08:00:31] [PASSED] 8
[08:00:31] [PASSED] 32
[08:00:31] [PASSED] 256
[08:00:31] ================ [PASSED] test_range_spare =================
[08:00:31] ===================== [PASSED] guc_dbm =====================
[08:00:31] =================== guc_idm (6 subtests) ===================
[08:00:31] [PASSED] bad_init
[08:00:31] [PASSED] no_init
[08:00:31] [PASSED] init_fini
[08:00:31] [PASSED] check_used
[08:00:31] [PASSED] check_quota
[08:00:31] [PASSED] check_all
[08:00:31] ===================== [PASSED] guc_idm =====================
[08:00:31] =============== guc_klv_helpers (9 subtests) ===============
[08:00:31] [PASSED] test_count
[08:00:31] [PASSED] test_encode_u32
[08:00:31] [PASSED] test_encode_u64
[08:00:31] [PASSED] test_encode_string
[08:00:31] [PASSED] test_encode_object_raw
[08:00:31] [PASSED] test_encode_object_klv
[08:00:31] [PASSED] test_encode_object_nested
[08:00:31] [PASSED] test_encode_object_basic
[08:00:31] [PASSED] test_print
[08:00:31] ================= [PASSED] guc_klv_helpers =================
[08:00:31] =================== xe_log (4 subtests) ====================
[08:00:31] [PASSED] demo_cper
[08:00:31] [PASSED] demo_dmesg
[08:00:31] ======================= test_dmesg  ========================
[08:00:31] [PASSED] test_fatal
[08:00:31] [PASSED] test_fatal_tile
[08:00:31] [PASSED] test_fatal_gt
[08:00:31] [PASSED] test_fatal_comp
[08:00:31] [PASSED] test_fatal_comp_tile
[08:00:31] [PASSED] test_fatal_comp_gt
[08:00:31] [PASSED] test_fatal_all
[08:00:31] [PASSED] test_recoverable
[08:00:31] [PASSED] test_recoverable_tile
[08:00:31] [PASSED] test_recoverable_gt
[08:00:31] [PASSED] test_recoverable_comp
[08:00:31] [PASSED] test_recoverable_comp_tile
[08:00:31] [PASSED] test_recoverable_comp_gt
[08:00:31] [PASSED] test_recoverable_all
[08:00:31] [PASSED] test_info
[08:00:31] [PASSED] test_info_tile
[08:00:31] [PASSED] test_info_gt
[08:00:31] [PASSED] test_info_err
[08:00:31] [PASSED] test_info_comp
[08:00:31] [PASSED] test_info_comp_tile
[08:00:31] [PASSED] test_info_comp_gt
[08:00:31] [PASSED] test_info_all
[08:00:31] [PASSED] test_hw_fatal
[08:00:31] [PASSED] test_hw_recoverable
[08:00:31] [PASSED] test_hw_corrected
[08:00:31] [PASSED] test_hw_informational
[08:00:31] =================== [PASSED] test_dmesg ====================
[08:00:31] ====================== test_invalid  =======================
[08:00:31] [SKIPPED] no-component no-location no-warn (requires CONFIG_DRM_XE_DEBUG)
[08:00:31] [SKIPPED] reserved location (requires CONFIG_DRM_XE_DEBUG)
[08:00:31] [SKIPPED] unknown location (requires CONFIG_DRM_XE_DEBUG)
[08:00:31] [SKIPPED] nonzero-device-id location (requires CONFIG_DRM_XE_DEBUG)
[08:00:31] [SKIPPED] invalid-tile-id location (requires CONFIG_DRM_XE_DEBUG)
[08:00:31] [SKIPPED] invalid-gt-id location (requires CONFIG_DRM_XE_DEBUG)
[08:00:31] [SKIPPED] unknown component class (requires CONFIG_DRM_XE_DEBUG)
[08:00:31] [SKIPPED] unknown system component (requires CONFIG_DRM_XE_DEBUG)
[08:00:31] [SKIPPED] unknown hardware component (requires CONFIG_DRM_XE_DEBUG)
[08:00:31] [SKIPPED] unknown component and location (requires CONFIG_DRM_XE_DEBUG)
[08:00:31] ================== [SKIPPED] test_invalid ==================
[08:00:31] ===================== [PASSED] xe_log ======================
[08:00:31] ================== no_relay (3 subtests) ===================
[08:00:31] [PASSED] xe_drops_guc2pf_if_not_ready
[08:00:31] [PASSED] xe_drops_guc2vf_if_not_ready
[08:00:31] [PASSED] xe_rejects_send_if_not_ready
[08:00:31] ==================== [PASSED] no_relay =====================
[08:00:31] ================== pf_relay (14 subtests) ==================
[08:00:31] [PASSED] pf_rejects_guc2pf_too_short
[08:00:31] [PASSED] pf_rejects_guc2pf_too_long
[08:00:31] [PASSED] pf_rejects_guc2pf_no_payload
[08:00:31] [PASSED] pf_fails_no_payload
[08:00:31] [PASSED] pf_fails_bad_origin
[08:00:31] [PASSED] pf_fails_bad_type
[08:00:31] [PASSED] pf_txn_reports_error
[08:00:31] [PASSED] pf_txn_sends_pf2guc
[08:00:31] [PASSED] pf_sends_pf2guc
[08:00:31] [SKIPPED] pf_loopback_nop (requires CONFIG_DRM_XE_DEBUG_SRIOV)
[08:00:31] [SKIPPED] pf_loopback_echo (requires CONFIG_DRM_XE_DEBUG_SRIOV)
[08:00:31] [SKIPPED] pf_loopback_fail (requires CONFIG_DRM_XE_DEBUG_SRIOV)
[08:00:31] [SKIPPED] pf_loopback_busy (requires CONFIG_DRM_XE_DEBUG_SRIOV)
[08:00:31] [SKIPPED] pf_loopback_retry (requires CONFIG_DRM_XE_DEBUG_SRIOV)
[08:00:31] ==================== [PASSED] pf_relay =====================
[08:00:31] ================== vf_relay (3 subtests) ===================
[08:00:31] [PASSED] vf_rejects_guc2vf_too_short
[08:00:31] [PASSED] vf_rejects_guc2vf_too_long
[08:00:31] [PASSED] vf_rejects_guc2vf_no_payload
[08:00:31] ==================== [PASSED] vf_relay =====================
[08:00:31] ================ pf_gt_config (9 subtests) =================
[08:00:31] [PASSED] fair_contexts_1vf
[08:00:31] [PASSED] fair_doorbells_1vf
[08:00:31] [PASSED] fair_ggtt_1vf
[08:00:31] ====================== fair_vram_1vf  ======================
[08:00:31] [PASSED] 3.50 GiB
[08:00:31] [PASSED] 11.5 GiB
[08:00:31] [PASSED] 15.5 GiB
[08:00:31] [PASSED] 31.5 GiB
[08:00:31] [PASSED] 63.5 GiB
[08:00:31] [PASSED] 1.91 GiB
[08:00:31] ================== [PASSED] fair_vram_1vf ==================
[08:00:31] ================ fair_vram_1vf_admin_only  =================
[08:00:31] [PASSED] 3.50 GiB
[08:00:31] [PASSED] 11.5 GiB
[08:00:31] [PASSED] 15.5 GiB
[08:00:31] [PASSED] 31.5 GiB
[08:00:31] [PASSED] 63.5 GiB
[08:00:31] [PASSED] 1.91 GiB
[08:00:31] ============ [PASSED] fair_vram_1vf_admin_only =============
[08:00:31] ====================== fair_contexts  ======================
[08:00:31] [PASSED] 1 VF
[08:00:31] [PASSED] 2 VFs
[08:00:31] [PASSED] 3 VFs
[08:00:31] [PASSED] 4 VFs
[08:00:31] [PASSED] 5 VFs
[08:00:31] [PASSED] 6 VFs
[08:00:31] [PASSED] 7 VFs
[08:00:31] [PASSED] 8 VFs
[08:00:31] [PASSED] 9 VFs
[08:00:31] [PASSED] 10 VFs
[08:00:31] [PASSED] 11 VFs
[08:00:31] [PASSED] 12 VFs
[08:00:31] [PASSED] 13 VFs
[08:00:31] [PASSED] 14 VFs
[08:00:31] [PASSED] 15 VFs
[08:00:31] [PASSED] 16 VFs
[08:00:31] [PASSED] 17 VFs
[08:00:31] [PASSED] 18 VFs
[08:00:31] [PASSED] 19 VFs
[08:00:31] [PASSED] 20 VFs
[08:00:31] [PASSED] 21 VFs
[08:00:31] [PASSED] 22 VFs
[08:00:31] [PASSED] 23 VFs
[08:00:31] [PASSED] 24 VFs
[08:00:31] [PASSED] 25 VFs
[08:00:31] [PASSED] 26 VFs
[08:00:31] [PASSED] 27 VFs
[08:00:31] [PASSED] 28 VFs
[08:00:31] [PASSED] 29 VFs
[08:00:31] [PASSED] 30 VFs
[08:00:31] [PASSED] 31 VFs
[08:00:31] [PASSED] 32 VFs
[08:00:31] [PASSED] 33 VFs
[08:00:31] [PASSED] 34 VFs
[08:00:31] [PASSED] 35 VFs
[08:00:31] [PASSED] 36 VFs
[08:00:31] [PASSED] 37 VFs
[08:00:31] [PASSED] 38 VFs
[08:00:31] [PASSED] 39 VFs
[08:00:31] [PASSED] 40 VFs
[08:00:31] [PASSED] 41 VFs
[08:00:31] [PASSED] 42 VFs
[08:00:31] [PASSED] 43 VFs
[08:00:31] [PASSED] 44 VFs
[08:00:31] [PASSED] 45 VFs
[08:00:31] [PASSED] 46 VFs
[08:00:31] [PASSED] 47 VFs
[08:00:31] [PASSED] 48 VFs
[08:00:31] [PASSED] 49 VFs
[08:00:31] [PASSED] 50 VFs
[08:00:31] [PASSED] 51 VFs
[08:00:31] [PASSED] 52 VFs
[08:00:31] [PASSED] 53 VFs
[08:00:31] [PASSED] 54 VFs
[08:00:31] [PASSED] 55 VFs
[08:00:31] [PASSED] 56 VFs
[08:00:31] [PASSED] 57 VFs
[08:00:31] [PASSED] 58 VFs
[08:00:31] [PASSED] 59 VFs
[08:00:31] [PASSED] 60 VFs
[08:00:31] [PASSED] 61 VFs
[08:00:31] [PASSED] 62 VFs
[08:00:31] [PASSED] 63 VFs
[08:00:31] ================== [PASSED] fair_contexts ==================
[08:00:31] ===================== fair_doorbells  ======================
[08:00:31] [PASSED] 1 VF
[08:00:31] [PASSED] 2 VFs
[08:00:31] [PASSED] 3 VFs
[08:00:31] [PASSED] 4 VFs
[08:00:31] [PASSED] 5 VFs
[08:00:31] [PASSED] 6 VFs
[08:00:31] [PASSED] 7 VFs
[08:00:31] [PASSED] 8 VFs
[08:00:31] [PASSED] 9 VFs
[08:00:31] [PASSED] 10 VFs
[08:00:31] [PASSED] 11 VFs
[08:00:31] [PASSED] 12 VFs
[08:00:31] [PASSED] 13 VFs
[08:00:31] [PASSED] 14 VFs
[08:00:31] [PASSED] 15 VFs
[08:00:31] [PASSED] 16 VFs
[08:00:31] [PASSED] 17 VFs
[08:00:31] [PASSED] 18 VFs
[08:00:31] [PASSED] 19 VFs
[08:00:31] [PASSED] 20 VFs
[08:00:31] [PASSED] 21 VFs
[08:00:31] [PASSED] 22 VFs
[08:00:31] [PASSED] 23 VFs
[08:00:31] [PASSED] 24 VFs
[08:00:31] [PASSED] 25 VFs
[08:00:31] [PASSED] 26 VFs
[08:00:31] [PASSED] 27 VFs
[08:00:31] [PASSED] 28 VFs
[08:00:31] [PASSED] 29 VFs
[08:00:31] [PASSED] 30 VFs
[08:00:31] [PASSED] 31 VFs
[08:00:31] [PASSED] 32 VFs
[08:00:31] [PASSED] 33 VFs
[08:00:31] [PASSED] 34 VFs
[08:00:31] [PASSED] 35 VFs
[08:00:31] [PASSED] 36 VFs
[08:00:31] [PASSED] 37 VFs
[08:00:31] [PASSED] 38 VFs
[08:00:31] [PASSED] 39 VFs
[08:00:31] [PASSED] 40 VFs
[08:00:31] [PASSED] 41 VFs
[08:00:31] [PASSED] 42 VFs
[08:00:31] [PASSED] 43 VFs
[08:00:31] [PASSED] 44 VFs
[08:00:31] [PASSED] 45 VFs
[08:00:31] [PASSED] 46 VFs
[08:00:31] [PASSED] 47 VFs
[08:00:31] [PASSED] 48 VFs
[08:00:31] [PASSED] 49 VFs
[08:00:31] [PASSED] 50 VFs
[08:00:31] [PASSED] 51 VFs
[08:00:31] [PASSED] 52 VFs
[08:00:31] [PASSED] 53 VFs
[08:00:31] [PASSED] 54 VFs
[08:00:31] [PASSED] 55 VFs
[08:00:31] [PASSED] 56 VFs
[08:00:31] [PASSED] 57 VFs
[08:00:31] [PASSED] 58 VFs
[08:00:31] [PASSED] 59 VFs
[08:00:31] [PASSED] 60 VFs
[08:00:31] [PASSED] 61 VFs
[08:00:31] [PASSED] 62 VFs
[08:00:31] [PASSED] 63 VFs
[08:00:31] ================= [PASSED] fair_doorbells ==================
[08:00:31] ======================== fair_ggtt  ========================
[08:00:31] [PASSED] 1 VF
[08:00:31] [PASSED] 2 VFs
[08:00:31] [PASSED] 3 VFs
[08:00:31] [PASSED] 4 VFs
[08:00:31] [PASSED] 5 VFs
[08:00:31] [PASSED] 6 VFs
[08:00:31] [PASSED] 7 VFs
[08:00:31] [PASSED] 8 VFs
[08:00:31] [PASSED] 9 VFs
[08:00:31] [PASSED] 10 VFs
[08:00:31] [PASSED] 11 VFs
[08:00:31] [PASSED] 12 VFs
[08:00:31] [PASSED] 13 VFs
[08:00:31] [PASSED] 14 VFs
[08:00:31] [PASSED] 15 VFs
[08:00:31] [PASSED] 16 VFs
[08:00:31] [PASSED] 17 VFs
[08:00:31] [PASSED] 18 VFs
[08:00:31] [PASSED] 19 VFs
[08:00:31] [PASSED] 20 VFs
[08:00:31] [PASSED] 21 VFs
[08:00:31] [PASSED] 22 VFs
[08:00:31] [PASSED] 23 VFs
[08:00:31] [PASSED] 24 VFs
[08:00:31] [PASSED] 25 VFs
[08:00:31] [PASSED] 26 VFs
[08:00:31] [PASSED] 27 VFs
[08:00:31] [PASSED] 28 VFs
[08:00:31] [PASSED] 29 VFs
[08:00:31] [PASSED] 30 VFs
[08:00:31] [PASSED] 31 VFs
[08:00:31] [PASSED] 32 VFs
[08:00:31] [PASSED] 33 VFs
[08:00:31] [PASSED] 34 VFs
[08:00:31] [PASSED] 35 VFs
[08:00:31] [PASSED] 36 VFs
[08:00:31] [PASSED] 37 VFs
[08:00:31] [PASSED] 38 VFs
[08:00:31] [PASSED] 39 VFs
[08:00:31] [PASSED] 40 VFs
[08:00:31] [PASSED] 41 VFs
[08:00:31] [PASSED] 42 VFs
[08:00:31] [PASSED] 43 VFs
[08:00:31] [PASSED] 44 VFs
[08:00:31] [PASSED] 45 VFs
[08:00:31] [PASSED] 46 VFs
[08:00:31] [PASSED] 47 VFs
[08:00:31] [PASSED] 48 VFs
[08:00:31] [PASSED] 49 VFs
[08:00:31] [PASSED] 50 VFs
[08:00:31] [PASSED] 51 VFs
[08:00:31] [PASSED] 52 VFs
[08:00:31] [PASSED] 53 VFs
[08:00:31] [PASSED] 54 VFs
[08:00:31] [PASSED] 55 VFs
[08:00:31] [PASSED] 56 VFs
[08:00:31] [PASSED] 57 VFs
[08:00:31] [PASSED] 58 VFs
[08:00:31] [PASSED] 59 VFs
[08:00:31] [PASSED] 60 VFs
[08:00:31] [PASSED] 61 VFs
[08:00:31] [PASSED] 62 VFs
[08:00:31] [PASSED] 63 VFs
[08:00:31] ==================== [PASSED] fair_ggtt ====================
[08:00:31] ======================== fair_vram  ========================
[08:00:31] [PASSED] 1 VF
[08:00:31] [PASSED] 2 VFs
[08:00:31] [PASSED] 3 VFs
[08:00:31] [PASSED] 4 VFs
[08:00:31] [PASSED] 5 VFs
[08:00:31] [PASSED] 6 VFs
[08:00:31] [PASSED] 7 VFs
[08:00:31] [PASSED] 8 VFs
[08:00:31] [PASSED] 9 VFs
[08:00:31] [PASSED] 10 VFs
[08:00:31] [PASSED] 11 VFs
[08:00:31] [PASSED] 12 VFs
[08:00:31] [PASSED] 13 VFs
[08:00:31] [PASSED] 14 VFs
[08:00:31] [PASSED] 15 VFs
[08:00:31] [PASSED] 16 VFs
[08:00:31] [PASSED] 17 VFs
[08:00:31] [PASSED] 18 VFs
[08:00:31] [PASSED] 19 VFs
[08:00:31] [PASSED] 20 VFs
[08:00:31] [PASSED] 21 VFs
[08:00:31] [PASSED] 22 VFs
[08:00:31] [PASSED] 23 VFs
[08:00:31] [PASSED] 24 VFs
[08:00:31] [PASSED] 25 VFs
[08:00:31] [PASSED] 26 VFs
[08:00:31] [PASSED] 27 VFs
[08:00:31] [PASSED] 28 VFs
[08:00:31] [PASSED] 29 VFs
[08:00:31] [PASSED] 30 VFs
[08:00:31] [PASSED] 31 VFs
[08:00:31] [PASSED] 32 VFs
[08:00:31] [PASSED] 33 VFs
[08:00:31] [PASSED] 34 VFs
[08:00:31] [PASSED] 35 VFs
[08:00:31] [PASSED] 36 VFs
[08:00:31] [PASSED] 37 VFs
[08:00:31] [PASSED] 38 VFs
[08:00:31] [PASSED] 39 VFs
[08:00:31] [PASSED] 40 VFs
[08:00:31] [PASSED] 41 VFs
[08:00:31] [PASSED] 42 VFs
[08:00:31] [PASSED] 43 VFs
[08:00:31] [PASSED] 44 VFs
[08:00:31] [PASSED] 45 VFs
[08:00:31] [PASSED] 46 VFs
[08:00:31] [PASSED] 47 VFs
[08:00:31] [PASSED] 48 VFs
[08:00:31] [PASSED] 49 VFs
[08:00:31] [PASSED] 50 VFs
[08:00:31] [PASSED] 51 VFs
[08:00:31] [PASSED] 52 VFs
[08:00:31] [PASSED] 53 VFs
[08:00:31] [PASSED] 54 VFs
[08:00:31] [PASSED] 55 VFs
[08:00:31] [PASSED] 56 VFs
[08:00:31] [PASSED] 57 VFs
[08:00:31] [PASSED] 58 VFs
[08:00:31] [PASSED] 59 VFs
[08:00:31] [PASSED] 60 VFs
[08:00:31] [PASSED] 61 VFs
[08:00:31] [PASSED] 62 VFs
[08:00:31] [PASSED] 63 VFs
[08:00:31] ==================== [PASSED] fair_vram ====================
[08:00:31] ================== [PASSED] pf_gt_config ===================
[08:00:31] ===================== lmtt (1 subtest) =====================
[08:00:31] ======================== test_ops  =========================
[08:00:31] [PASSED] 2-level
[08:00:31] [PASSED] multi-level
[08:00:31] ==================== [PASSED] test_ops =====================
[08:00:31] ====================== [PASSED] lmtt =======================
[08:00:31] ================= sriov_packet (1 subtest) =================
[08:00:31] [PASSED] test_descriptor_init
[08:00:31] ================== [PASSED] sriov_packet ===================
[08:00:31] ================= pf_service (11 subtests) =================
[08:00:31] [PASSED] pf_negotiate_any
[08:00:31] [PASSED] pf_negotiate_base_match
[08:00:31] [PASSED] pf_negotiate_base_newer
[08:00:31] [PASSED] pf_negotiate_base_next
[08:00:31] [SKIPPED] pf_negotiate_base_older (no older minor)
[08:00:31] [PASSED] pf_negotiate_base_prev
[08:00:31] [PASSED] pf_negotiate_latest_match
[08:00:31] [PASSED] pf_negotiate_latest_newer
[08:00:31] [PASSED] pf_negotiate_latest_next
[08:00:31] [SKIPPED] pf_negotiate_latest_older (no older minor)
[08:00:31] [SKIPPED] pf_negotiate_latest_prev (no prev major)
[08:00:31] =================== [PASSED] pf_service ====================
[08:00:31] ================= xe_guc_g2g (2 subtests) ==================
[08:00:31] ============== xe_live_guc_g2g_kunit_default  ==============
[08:00:31] ========= [SKIPPED] xe_live_guc_g2g_kunit_default ==========
[08:00:31] ============== xe_live_guc_g2g_kunit_allmem  ===============
[08:00:31] ========== [SKIPPED] xe_live_guc_g2g_kunit_allmem ==========
[08:00:31] =================== [SKIPPED] xe_guc_g2g ===================
[08:00:31] =================== xe_mocs (2 subtests) ===================
[08:00:31] ================ xe_live_mocs_kernel_kunit  ================
[08:00:31] =========== [SKIPPED] xe_live_mocs_kernel_kunit ============
[08:00:31] ================ xe_live_mocs_reset_kunit  =================
[08:00:31] ============ [SKIPPED] xe_live_mocs_reset_kunit ============
[08:00:31] ==================== [SKIPPED] xe_mocs =====================
[08:00:31] ================= xe_migrate (2 subtests) ==================
[08:00:31] ================= xe_migrate_sanity_kunit  =================
[08:00:31] ============ [SKIPPED] xe_migrate_sanity_kunit =============
[08:00:31] ================== xe_validate_ccs_kunit  ==================
[08:00:31] ============= [SKIPPED] xe_validate_ccs_kunit ==============
[08:00:31] =================== [SKIPPED] xe_migrate ===================
[08:00:31] ================== xe_dma_buf (1 subtest) ==================
[08:00:31] ==================== xe_dma_buf_kunit  =====================
[08:00:31] ================ [SKIPPED] xe_dma_buf_kunit ================
[08:00:31] =================== [SKIPPED] xe_dma_buf ===================
[08:00:31] ================= xe_bo_shrink (1 subtest) =================
[08:00:31] =================== xe_bo_shrink_kunit  ====================
[08:00:31] =============== [SKIPPED] xe_bo_shrink_kunit ===============
[08:00:31] ================== [SKIPPED] xe_bo_shrink ==================
[08:00:31] ==================== xe_bo (2 subtests) ====================
[08:00:31] ================== xe_ccs_migrate_kunit  ===================
[08:00:31] ============== [SKIPPED] xe_ccs_migrate_kunit ==============
[08:00:31] ==================== xe_bo_evict_kunit  ====================
[08:00:31] =============== [SKIPPED] xe_bo_evict_kunit ================
[08:00:31] ===================== [SKIPPED] xe_bo ======================
[08:00:31] =================== xe_any (9 subtests) ====================
[08:00:31] [PASSED] test_to_xe
[08:00:31] [PASSED] test_to_dev
[08:00:31] [PASSED] test_to_pdev
[08:00:31] [PASSED] test_to_drm
[08:00:31] [PASSED] test_if_pdev
[08:00:31] [PASSED] test_if_xe
[08:00:31] [PASSED] test_if_tile
[08:00:31] [PASSED] test_if_gt
[08:00:31] [PASSED] test_to_id
[08:00:31] ===================== [PASSED] xe_any ======================
[08:00:31] ==================== args (13 subtests) ====================
[08:00:31] [PASSED] count_args_test
[08:00:31] [PASSED] call_args_example
[08:00:31] [PASSED] call_args_test
[08:00:31] [PASSED] drop_first_arg_example
[08:00:31] [PASSED] drop_first_arg_test
[08:00:31] [PASSED] first_arg_example
[08:00:31] [PASSED] first_arg_test
[08:00:31] [PASSED] last_arg_example
[08:00:31] [PASSED] last_arg_test
[08:00:31] [PASSED] pick_arg_example
[08:00:31] [PASSED] if_args_example
[08:00:31] [PASSED] if_args_test
[08:00:31] [PASSED] sep_comma_example
[08:00:31] ====================== [PASSED] args =======================
[08:00:31] =================== xe_pci (3 subtests) ====================
[08:00:31] ==================== check_graphics_ip  ====================
[08:00:31] [PASSED] 12.00 Xe_LP
[08:00:31] [PASSED] 12.10 Xe_LP+
[08:00:31] [PASSED] 12.55 Xe_HPG
[08:00:31] [PASSED] 12.60 Xe_HPC
[08:00:31] [PASSED] 12.70 Xe_LPG
[08:00:31] [PASSED] 12.71 Xe_LPG
[08:00:31] [PASSED] 12.74 Xe_LPG+
[08:00:31] [PASSED] 20.01 Xe2_HPG
[08:00:31] [PASSED] 20.02 Xe2_HPG
[08:00:31] [PASSED] 20.04 Xe2_LPG
[08:00:31] [PASSED] 30.00 Xe3_LPG
[08:00:31] [PASSED] 30.01 Xe3_LPG
[08:00:31] [PASSED] 30.03 Xe3_LPG
[08:00:31] [PASSED] 30.04 Xe3_LPG
[08:00:31] [PASSED] 30.05 Xe3_LPG
[08:00:31] [PASSED] 35.10 Xe3p_LPG
[08:00:31] [PASSED] 35.11 Xe3p_XPC
[08:00:31] ================ [PASSED] check_graphics_ip ================
[08:00:31] ===================== check_media_ip  ======================
[08:00:31] [PASSED] 12.00 Xe_M
[08:00:31] [PASSED] 12.55 Xe_HPM
[08:00:31] [PASSED] 13.00 Xe_LPM+
[08:00:31] [PASSED] 13.01 Xe2_HPM
[08:00:31] [PASSED] 20.00 Xe2_LPM
[08:00:31] [PASSED] 30.00 Xe3_LPM
[08:00:31] [PASSED] 30.02 Xe3_LPM
[08:00:31] [PASSED] 35.00 Xe3p_LPM
[08:00:31] [PASSED] 35.03 Xe3p_HPM
[08:00:31] ================= [PASSED] check_media_ip ==================
[08:00:31] =================== check_platform_desc  ===================
[08:00:31] [PASSED] 0x9A60 (TIGERLAKE)
[08:00:31] [PASSED] 0x9A68 (TIGERLAKE)
[08:00:31] [PASSED] 0x9A70 (TIGERLAKE)
[08:00:31] [PASSED] 0x9A40 (TIGERLAKE)
[08:00:31] [PASSED] 0x9A49 (TIGERLAKE)
[08:00:31] [PASSED] 0x9A59 (TIGERLAKE)
[08:00:31] [PASSED] 0x9A78 (TIGERLAKE)
[08:00:31] [PASSED] 0x9AC0 (TIGERLAKE)
[08:00:31] [PASSED] 0x9AC9 (TIGERLAKE)
[08:00:31] [PASSED] 0x9AD9 (TIGERLAKE)
[08:00:31] [PASSED] 0x9AF8 (TIGERLAKE)
[08:00:31] [PASSED] 0x4C80 (ROCKETLAKE)
[08:00:31] [PASSED] 0x4C8A (ROCKETLAKE)
[08:00:31] [PASSED] 0x4C8B (ROCKETLAKE)
[08:00:31] [PASSED] 0x4C8C (ROCKETLAKE)
[08:00:31] [PASSED] 0x4C90 (ROCKETLAKE)
[08:00:31] [PASSED] 0x4C9A (ROCKETLAKE)
[08:00:31] [PASSED] 0x4680 (ALDERLAKE_S)
[08:00:31] [PASSED] 0x4682 (ALDERLAKE_S)
[08:00:31] [PASSED] 0x4688 (ALDERLAKE_S)
[08:00:31] [PASSED] 0x468A (ALDERLAKE_S)
[08:00:31] [PASSED] 0x468B (ALDERLAKE_S)
[08:00:31] [PASSED] 0x4690 (ALDERLAKE_S)
[08:00:31] [PASSED] 0x4692 (ALDERLAKE_S)
[08:00:31] [PASSED] 0x4693 (ALDERLAKE_S)
[08:00:31] [PASSED] 0x46A0 (ALDERLAKE_P)
[08:00:31] [PASSED] 0x46A1 (ALDERLAKE_P)
[08:00:31] [PASSED] 0x46A2 (ALDERLAKE_P)
[08:00:31] [PASSED] 0x46A3 (ALDERLAKE_P)
[08:00:31] [PASSED] 0x46A6 (ALDERLAKE_P)
[08:00:31] [PASSED] 0x46A8 (ALDERLAKE_P)
[08:00:31] [PASSED] 0x46AA (ALDERLAKE_P)
[08:00:31] [PASSED] 0x462A (ALDERLAKE_P)
[08:00:31] [PASSED] 0x4626 (ALDERLAKE_P)
[08:00:31] [PASSED] 0x4628 (ALDERLAKE_P)
[08:00:31] [PASSED] 0x46B0 (ALDERLAKE_P)
[08:00:31] [PASSED] 0x46B1 (ALDERLAKE_P)
[08:00:31] [PASSED] 0x46B2 (ALDERLAKE_P)
[08:00:31] [PASSED] 0x46B3 (ALDERLAKE_P)
[08:00:31] [PASSED] 0x46C0 (ALDERLAKE_P)
[08:00:31] [PASSED] 0x46C1 (ALDERLAKE_P)
[08:00:31] [PASSED] 0x46C2 (ALDERLAKE_P)
[08:00:31] [PASSED] 0x46C3 (ALDERLAKE_P)
[08:00:31] [PASSED] 0x46D0 (ALDERLAKE_N)
[08:00:31] [PASSED] 0x46D1 (ALDERLAKE_N)
[08:00:31] [PASSED] 0x46D2 (ALDERLAKE_N)
[08:00:31] [PASSED] 0x46D3 (ALDERLAKE_N)
[08:00:31] [PASSED] 0x46D4 (ALDERLAKE_N)
[08:00:31] [PASSED] 0xA721 (ALDERLAKE_P)
[08:00:31] [PASSED] 0xA7A1 (ALDERLAKE_P)
[08:00:31] [PASSED] 0xA7A9 (ALDERLAKE_P)
[08:00:31] [PASSED] 0xA7AC (ALDERLAKE_P)
[08:00:31] [PASSED] 0xA7AD (ALDERLAKE_P)
[08:00:31] [PASSED] 0xA720 (ALDERLAKE_P)
[08:00:31] [PASSED] 0xA7A0 (ALDERLAKE_P)
[08:00:31] [PASSED] 0xA7A8 (ALDERLAKE_P)
[08:00:31] [PASSED] 0xA7AA (ALDERLAKE_P)
[08:00:31] [PASSED] 0xA7AB (ALDERLAKE_P)
[08:00:31] [PASSED] 0xA780 (ALDERLAKE_S)
[08:00:31] [PASSED] 0xA781 (ALDERLAKE_S)
[08:00:31] [PASSED] 0xA782 (ALDERLAKE_S)
[08:00:31] [PASSED] 0xA783 (ALDERLAKE_S)
[08:00:31] [PASSED] 0xA788 (ALDERLAKE_S)
[08:00:31] [PASSED] 0xA789 (ALDERLAKE_S)
[08:00:31] [PASSED] 0xA78A (ALDERLAKE_S)
[08:00:31] [PASSED] 0xA78B (ALDERLAKE_S)
[08:00:31] [PASSED] 0x4905 (DG1)
[08:00:31] [PASSED] 0x4906 (DG1)
[08:00:31] [PASSED] 0x4907 (DG1)
[08:00:31] [PASSED] 0x4908 (DG1)
[08:00:31] [PASSED] 0x4909 (DG1)
[08:00:31] [PASSED] 0x56C0 (DG2)
[08:00:31] [PASSED] 0x56C2 (DG2)
[08:00:31] [PASSED] 0x56C1 (DG2)
[08:00:31] [PASSED] 0x7D51 (METEORLAKE)
[08:00:31] [PASSED] 0x7DD1 (METEORLAKE)
[08:00:31] [PASSED] 0x7D41 (METEORLAKE)
[08:00:31] [PASSED] 0x7D67 (METEORLAKE)
[08:00:31] [PASSED] 0xB640 (METEORLAKE)
[08:00:31] [PASSED] 0x56A0 (DG2)
[08:00:31] [PASSED] 0x56A1 (DG2)
[08:00:31] [PASSED] 0x56A2 (DG2)
[08:00:31] [PASSED] 0x56BE (DG2)
[08:00:31] [PASSED] 0x56BF (DG2)
[08:00:31] [PASSED] 0x5690 (DG2)
[08:00:31] [PASSED] 0x5691 (DG2)
[08:00:31] [PASSED] 0x5692 (DG2)
[08:00:31] [PASSED] 0x56A5 (DG2)
[08:00:31] [PASSED] 0x56A6 (DG2)
[08:00:31] [PASSED] 0x56B0 (DG2)
[08:00:31] [PASSED] 0x56B1 (DG2)
[08:00:31] [PASSED] 0x56BA (DG2)
[08:00:31] [PASSED] 0x56BB (DG2)
[08:00:31] [PASSED] 0x56BC (DG2)
[08:00:31] [PASSED] 0x56BD (DG2)
[08:00:31] [PASSED] 0x5693 (DG2)
[08:00:31] [PASSED] 0x5694 (DG2)
[08:00:31] [PASSED] 0x5695 (DG2)
[08:00:31] [PASSED] 0x56A3 (DG2)
[08:00:31] [PASSED] 0x56A4 (DG2)
[08:00:31] [PASSED] 0x56B2 (DG2)
[08:00:31] [PASSED] 0x56B3 (DG2)
[08:00:31] [PASSED] 0x5696 (DG2)
[08:00:31] [PASSED] 0x5697 (DG2)
[08:00:31] [PASSED] 0xB69 (PVC)
[08:00:31] [PASSED] 0xB6E (PVC)
[08:00:31] [PASSED] 0xBD4 (PVC)
[08:00:31] [PASSED] 0xBD5 (PVC)
[08:00:31] [PASSED] 0xBD6 (PVC)
[08:00:31] [PASSED] 0xBD7 (PVC)
[08:00:31] [PASSED] 0xBD8 (PVC)
[08:00:31] [PASSED] 0xBD9 (PVC)
[08:00:31] [PASSED] 0xBDA (PVC)
[08:00:31] [PASSED] 0xBDB (PVC)
[08:00:31] [PASSED] 0xBE0 (PVC)
[08:00:31] [PASSED] 0xBE1 (PVC)
[08:00:31] [PASSED] 0xBE5 (PVC)
[08:00:31] [PASSED] 0x7D40 (METEORLAKE)
[08:00:31] [PASSED] 0x7D45 (METEORLAKE)
[08:00:31] [PASSED] 0x7D55 (METEORLAKE)
[08:00:31] [PASSED] 0x7D60 (METEORLAKE)
[08:00:31] [PASSED] 0x7DD5 (METEORLAKE)
[08:00:31] [PASSED] 0x6420 (LUNARLAKE)
[08:00:31] [PASSED] 0x64A0 (LUNARLAKE)
[08:00:31] [PASSED] 0x64B0 (LUNARLAKE)
[08:00:31] [PASSED] 0xE202 (BATTLEMAGE)
[08:00:31] [PASSED] 0xE209 (BATTLEMAGE)
[08:00:31] [PASSED] 0xE20B (BATTLEMAGE)
[08:00:31] [PASSED] 0xE20C (BATTLEMAGE)
[08:00:31] [PASSED] 0xE20D (BATTLEMAGE)
[08:00:31] [PASSED] 0xE210 (BATTLEMAGE)
[08:00:31] [PASSED] 0xE211 (BATTLEMAGE)
[08:00:31] [PASSED] 0xE212 (BATTLEMAGE)
[08:00:31] [PASSED] 0xE216 (BATTLEMAGE)
[08:00:31] [PASSED] 0xE220 (BATTLEMAGE)
[08:00:31] [PASSED] 0xE221 (BATTLEMAGE)
[08:00:31] [PASSED] 0xE222 (BATTLEMAGE)
[08:00:31] [PASSED] 0xE223 (BATTLEMAGE)
[08:00:31] [PASSED] 0xB080 (PANTHERLAKE)
[08:00:31] [PASSED] 0xB081 (PANTHERLAKE)
[08:00:31] [PASSED] 0xB082 (PANTHERLAKE)
[08:00:31] [PASSED] 0xB083 (PANTHERLAKE)
[08:00:31] [PASSED] 0xB084 (PANTHERLAKE)
[08:00:31] [PASSED] 0xB085 (PANTHERLAKE)
[08:00:31] [PASSED] 0xB086 (PANTHERLAKE)
[08:00:31] [PASSED] 0xB087 (PANTHERLAKE)
[08:00:31] [PASSED] 0xB08F (PANTHERLAKE)
[08:00:31] [PASSED] 0xB090 (PANTHERLAKE)
[08:00:31] [PASSED] 0xB0A0 (PANTHERLAKE)
[08:00:31] [PASSED] 0xB0B0 (PANTHERLAKE)
[08:00:31] [PASSED] 0xFD80 (PANTHERLAKE)
[08:00:31] [PASSED] 0xFD81 (PANTHERLAKE)
[08:00:31] [PASSED] 0xD740 (NOVALAKE_S)
[08:00:31] [PASSED] 0xD741 (NOVALAKE_S)
[08:00:31] [PASSED] 0xD742 (NOVALAKE_S)
[08:00:31] [PASSED] 0xD743 (NOVALAKE_S)
[08:00:31] [PASSED] 0xD745 (NOVALAKE_S)
[08:00:31] [PASSED] 0xD74A (NOVALAKE_S)
[08:00:31] [PASSED] 0xD74B (NOVALAKE_S)
[08:00:31] [PASSED] 0x674C (CRESCENTISLAND)
[08:00:31] [PASSED] 0x674D (CRESCENTISLAND)
[08:00:31] [PASSED] 0x674E (CRESCENTISLAND)
[08:00:31] [PASSED] 0x674F (CRESCENTISLAND)
[08:00:31] [PASSED] 0x6750 (CRESCENTISLAND)
[08:00:31] [PASSED] 0xD750 (NOVALAKE_P)
[08:00:31] [PASSED] 0xD751 (NOVALAKE_P)
[08:00:31] [PASSED] 0xD752 (NOVALAKE_P)
[08:00:31] [PASSED] 0xD753 (NOVALAKE_P)
[08:00:31] [PASSED] 0xD754 (NOVALAKE_P)
[08:00:31] [PASSED] 0xD755 (NOVALAKE_P)
[08:00:31] [PASSED] 0xD756 (NOVALAKE_P)
[08:00:31] [PASSED] 0xD757 (NOVALAKE_P)
[08:00:31] [PASSED] 0xD75F (NOVALAKE_P)
[08:00:31] =============== [PASSED] check_platform_desc ===============
[08:00:31] ===================== [PASSED] xe_pci ======================
[08:00:31] ============= xe_rtp_tables_test (5 subtests) ==============
[08:00:31] ================== xe_rtp_table_gt_test  ===================
[08:00:31] [PASSED] gt_was/14011060649
[08:00:31] [PASSED] gt_was/14011059788
[08:00:31] [PASSED] gt_was/14015795083
[08:00:31] [PASSED] gt_was/16021867713
[08:00:31] [PASSED] gt_was/14019449301
[08:00:31] [PASSED] gt_was/16028005424
[08:00:31] [PASSED] gt_was/14026578760
[08:00:31] [PASSED] gt_was/1409420604
[08:00:31] [PASSED] gt_was/1408615072
[08:00:31] [PASSED] gt_was/22010523718
[08:00:31] [PASSED] gt_was/14011006942
[08:00:31] [PASSED] gt_was/14014830051
[08:00:31] [PASSED] gt_was/18018781329
[08:00:31] [PASSED] gt_was/1509235366
[08:00:31] [PASSED] gt_was/18018781329
[08:00:31] [PASSED] gt_was/16016694945
[08:00:31] [PASSED] gt_was/14018575942
[08:00:31] [PASSED] gt_was/22016670082
[08:00:31] [PASSED] gt_was/22016670082
[08:00:31] [PASSED] gt_was/14017421178
[08:00:31] [PASSED] gt_was/16025250150
[08:00:31] [PASSED] gt_was/14021871409
[08:00:31] [PASSED] gt_was/16021865536
[08:00:31] [PASSED] gt_was/14021486841
[08:00:31] [PASSED] gt_was/14025160223
[08:00:31] [PASSED] gt_was/14026144927, 16029437861, 14026127056
[08:00:31] [PASSED] gt_was/14025635424
[08:00:31] [PASSED] gt_was/16028005424
[08:00:31] ============== [PASSED] xe_rtp_table_gt_test ===============
[08:00:31] ================== xe_rtp_table_gt_test  ===================
[08:00:31] [PASSED] gt_tunings/Tuning: Blend Fill Caching Optimization Disable
[08:00:31] [PASSED] gt_tunings/Tuning: 32B Access Enable
[08:00:31] [PASSED] gt_tunings/Tuning: L3 cache
[08:00:31] [PASSED] gt_tunings/Tuning: L3 cache - media
[08:00:31] [PASSED] gt_tunings/Tuning: Compression Overfetch
[08:00:31] [PASSED] gt_tunings/Tuning: Compression Overfetch - media
[08:00:31] [PASSED] gt_tunings/Tuning: Enable compressible partial write overfetch in L3
[08:00:31] [PASSED] gt_tunings/Tuning: Enable compressible partial write overfetch in L3 - media
[08:00:31] [PASSED] gt_tunings/Tuning: L2 Overfetch Compressible Only
[08:00:31] [PASSED] gt_tunings/Tuning: L2 Overfetch Compressible Only - media
[08:00:31] [PASSED] gt_tunings/Tuning: Stateless compression control
[08:00:31] [PASSED] gt_tunings/Tuning: Stateless compression control - media
[08:00:31] [PASSED] gt_tunings/Tuning: L3 RW flush all Cache
[08:00:31] [PASSED] gt_tunings/Tuning: L3 RW flush all cache - media
[08:00:31] [PASSED] gt_tunings/Tuning: Set STLB Bank Hash Mode to 4KB
[08:00:31] ============== [PASSED] xe_rtp_table_gt_test ===============
[08:00:31] ================== xe_rtp_table_oob_test  ==================
[08:00:31] [PASSED] oob_was/1607983814
[08:00:31] [PASSED] oob_was/16010904313
[08:00:31] [PASSED] oob_was/18022495364
[08:00:31] [PASSED] oob_was/22012773006
[08:00:31] [PASSED] oob_was/14014475959
[08:00:31] [PASSED] oob_was/22011391025
[08:00:31] [PASSED] oob_was/22012727170
[08:00:31] [PASSED] oob_was/22012727685
[08:00:31] [PASSED] oob_was/22016596838
[08:00:31] [PASSED] oob_was/18020744125
[08:00:31] [PASSED] oob_was/1409600907
[08:00:31] [PASSED] oob_was/22014953428
[08:00:31] [PASSED] oob_was/16017236439
[08:00:31] [PASSED] oob_was/14019821291
[08:00:31] [PASSED] oob_was/14015076503
[08:00:31] [PASSED] oob_was/14018913170
[08:00:31] [PASSED] oob_was/14018094691
[08:00:31] [PASSED] oob_was/18024947630
[08:00:31] [PASSED] oob_was/16022287689
[08:00:31] [PASSED] oob_was/13011645652
[08:00:31] [PASSED] oob_was/14022293748
[08:00:31] [PASSED] oob_was/22019794406
[08:00:31] [PASSED] oob_was/22019338487
[08:00:31] [PASSED] oob_was/16023588340
[08:00:31] [PASSED] oob_was/14019789679
[08:00:31] [PASSED] oob_was/14022866841
[08:00:31] [PASSED] oob_was/16021333562
[08:00:31] [PASSED] oob_was/14016712196
[08:00:31] [PASSED] oob_was/14015568240
[08:00:31] [PASSED] oob_was/18013179988
[08:00:31] [PASSED] oob_was/1508761755
[08:00:31] [PASSED] oob_was/16023105232
[08:00:31] [PASSED] oob_was/16026508708
[08:00:31] [PASSED] oob_was/14020001231
[08:00:31] [PASSED] oob_was/16023683509
[08:00:31] [PASSED] oob_was/14025515070
[08:00:31] [PASSED] oob_was/15015404425_disable
[08:00:31] [PASSED] oob_was/16026007364
[08:00:31] [PASSED] oob_was/14020316580
[08:00:31] [PASSED] oob_was/14025883347
[08:00:31] [PASSED] oob_was/16029380221
[08:00:31] [PASSED] oob_was/22022079272
[08:00:31] [PASSED] oob_was/16029897822
[08:00:31] [PASSED] oob_was/14027054324
[08:00:31] ============== [PASSED] xe_rtp_table_oob_test ==============
[08:00:31] ================ xe_rtp_table_dev_oob_test  ================
[08:00:31] [PASSED] device_oob_was/22010954014
[08:00:31] [PASSED] device_oob_was/15015404425
[08:00:31] [PASSED] device_oob_was/22019338487_display
[08:00:31] [PASSED] device_oob_was/14022085890
[08:00:31] [PASSED] device_oob_was/14026539277
[08:00:31] [PASSED] device_oob_was/14026633728
[08:00:31] [PASSED] device_oob_was/14026746987
[08:00:31] [PASSED] device_oob_was/14026779378
[08:00:31] ============ [PASSED] xe_rtp_table_dev_oob_test ============
[08:00:31] ========== xe_rtp_table_missing_upper_bound_test  ==========
[08:00:31] [PASSED] register_whitelist/WaAllowPMDepthAndInvocationCountAccessFromUMD, 1408556865
[08:00:31] [PASSED] register_whitelist/1508744258, 14012131227, 1808121037
[08:00:31] [PASSED] register_whitelist/1806527549
[08:00:31] [PASSED] register_whitelist/allow_read_ctx_timestamp
[08:00:31] [PASSED] register_whitelist/allow_read_queue_timestamp
[08:00:31] [PASSED] register_whitelist/16014440446
[08:00:31] [PASSED] register_whitelist/16017236439
[08:00:31] [PASSED] register_whitelist/16020183090
[08:00:31] [PASSED] register_whitelist/14024997852
[08:00:31] [PASSED] register_whitelist/14024997852
[08:00:31] ====== [PASSED] xe_rtp_table_missing_upper_bound_test ======
[08:00:31] =============== [PASSED] xe_rtp_tables_test ================
[08:00:31] =================== xe_rtp (3 subtests) ====================
[08:00:31] =================== xe_rtp_rules_tests  ====================
[08:00:31] [PASSED] no
[08:00:31] [PASSED] yes
[08:00:31] [PASSED] no-and-no
[08:00:31] [PASSED] no-and-yes
[08:00:31] [PASSED] yes-and-no
[08:00:31] [PASSED] yes-and-yes
[08:00:31] [PASSED] no-or-no
[08:00:31] [PASSED] no-or-yes
[08:00:31] [PASSED] yes-or-no
[08:00:31] [PASSED] yes-or-yes
[08:00:31] [PASSED] no-yes-or-yes-no
[08:00:31] [PASSED] no-yes-or-yes-yes
[08:00:31] [PASSED] yes-yes-or-no-yes
[08:00:31] [PASSED] yes-yes-or-yes-yes
[08:00:31] [PASSED] no-no-or-yes-or-no
[08:00:31] [PASSED] or
[08:00:31] [PASSED] or-yes
[08:00:31] [PASSED] or-no
[08:00:31] [PASSED] yes-or
[08:00:31] [PASSED] no-or
[08:00:31] [PASSED] no-or-or-yes
[08:00:31] [PASSED] yes-or-or-no
[08:00:31] [PASSED] no-or-or-no
[08:00:31] [PASSED] missing-context-engine-class
[08:00:31] [PASSED] missing-context-engine-class-or-yes
[08:00:31] [PASSED] missing-context-engine-class-or-or-yes
[08:00:31] =============== [PASSED] xe_rtp_rules_tests ================
[08:00:31] =============== xe_rtp_process_to_sr_tests  ================
[08:00:31] [PASSED] coalesce-same-reg
[08:00:31] [PASSED] coalesce-same-reg-literal-and-func
[08:00:31] [PASSED] no-match-no-add
[08:00:31] [PASSED] two-regs-two-entries
[08:00:31] [PASSED] clr-one-set-other
[08:00:31] [PASSED] set-field
[08:00:31] [PASSED] conflict-duplicate
[08:00:31] [PASSED] conflict-not-disjoint
[08:00:31] [PASSED] conflict-not-disjoint-literal-and-func
[08:00:31] [PASSED] conflict-reg-type
[08:00:31] [PASSED] bad-mcr-reg-forced-to-regular
[08:00:31] [PASSED] bad-regular-reg-forced-to-mcr
[08:00:31] =========== [PASSED] xe_rtp_process_to_sr_tests ============
[08:00:31] ================== xe_rtp_process_tests  ===================
[08:00:31] [PASSED] active1
[08:00:31] [PASSED] active2
[08:00:31] [PASSED] active-inactive
[08:00:31] [PASSED] inactive-active
[08:00:31] [PASSED] inactive-active-inactive
[08:00:31] [PASSED] inactive-inactive-inactive
[08:00:31] ============== [PASSED] xe_rtp_process_tests ===============
[08:00:31] ===================== [PASSED] xe_rtp ======================
[08:00:31] ==================== xe_wa (1 subtest) =====================
[08:00:31] ======================== xe_wa_gt  =========================
[08:00:31] [PASSED] TIGERLAKE B0
[08:00:31] [PASSED] DG1 A0
[08:00:31] [PASSED] DG1 B0
[08:00:31] [PASSED] ALDERLAKE_S A0
[08:00:31] [PASSED] ALDERLAKE_S B0
[08:00:31] [PASSED] ALDERLAKE_S C0
[08:00:31] [PASSED] ALDERLAKE_S D0
[08:00:31] [PASSED] ALDERLAKE_P A0
[08:00:31] [PASSED] ALDERLAKE_P B0
[08:00:31] [PASSED] ALDERLAKE_P C0
[08:00:31] [PASSED] ALDERLAKE_S RPLS D0
[08:00:31] [PASSED] ALDERLAKE_P RPLU E0
[08:00:31] [PASSED] DG2 G10 C0
[08:00:31] [PASSED] DG2 G11 B1
[08:00:31] [PASSED] DG2 G12 A1
[08:00:31] [PASSED] METEORLAKE 12.70(Xe_LPG) A0 13.00(Xe_LPM+) A0
[08:00:31] [PASSED] METEORLAKE 12.71(Xe_LPG) A0 13.00(Xe_LPM+) A0
[08:00:31] [PASSED] METEORLAKE 12.74(Xe_LPG+) A0 13.00(Xe_LPM+) A0
[08:00:31] [PASSED] LUNARLAKE 20.04(Xe2_LPG) A0 20.00(Xe2_LPM) A0
[08:00:31] [PASSED] LUNARLAKE 20.04(Xe2_LPG) B0 20.00(Xe2_LPM) A0
[08:00:31] [PASSED] BATTLEMAGE 20.01(Xe2_HPG) A0 13.01(Xe2_HPM) A1
[08:00:31] [PASSED] PANTHERLAKE 30.00(Xe3_LPG) A0 30.00(Xe3_LPM) A0
[08:00:31] ==================== [PASSED] xe_wa_gt =====================
[08:00:31] ====================== [PASSED] xe_wa ======================
[08:00:31] ============================================================
[08:00:31] Testing complete. Ran 789 tests: passed: 761, skipped: 28
[08:00:31] Elapsed time: 37.830s total, 4.441s configuring, 32.673s building, 0.682s running

+ /kernel/tools/testing/kunit/kunit.py run --kunitconfig /kernel/drivers/gpu/drm/tests/.kunitconfig
[08:00:32] Configuring KUnit Kernel ...
Regenerating .config ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
[08:00:33] Building KUnit Kernel ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
Building with:
$ make all compile_commands.json scripts_gdb ARCH=um O=.kunit --jobs=48
[08:00:59] Starting KUnit Kernel (1/1)...
[08:00:59] ============================================================
Running tests with:
$ .kunit/linux kunit.enable=1 mem=1G console=tty kunit_shutdown=halt
[08:00:59] ============ drm_test_pick_cmdline (2 subtests) ============
[08:00:59] [PASSED] drm_test_pick_cmdline_res_1920_1080_60
[08:00:59] =============== drm_test_pick_cmdline_named  ===============
[08:00:59] [PASSED] NTSC
[08:00:59] [PASSED] NTSC-J
[08:00:59] [PASSED] PAL
[08:00:59] [PASSED] PAL-M
[08:00:59] =========== [PASSED] drm_test_pick_cmdline_named ===========
[08:00:59] ============== [PASSED] drm_test_pick_cmdline ==============
[08:00:59] == drm_test_atomic_get_connector_for_encoder (1 subtest) ===
[08:00:59] [PASSED] drm_test_drm_atomic_get_connector_for_encoder
[08:00:59] ==== [PASSED] drm_test_atomic_get_connector_for_encoder ====
[08:00:59] =========== drm_validate_clone_mode (2 subtests) ===========
[08:00:59] ============== drm_test_check_in_clone_mode  ===============
[08:00:59] [PASSED] in_clone_mode
[08:00:59] [PASSED] not_in_clone_mode
[08:00:59] ========== [PASSED] drm_test_check_in_clone_mode ===========
[08:00:59] =============== drm_test_check_valid_clones  ===============
[08:00:59] [PASSED] not_in_clone_mode
[08:00:59] [PASSED] valid_clone
[08:00:59] [PASSED] invalid_clone
[08:00:59] =========== [PASSED] drm_test_check_valid_clones ===========
[08:00:59] ============= [PASSED] drm_validate_clone_mode =============
[08:00:59] ============= drm_validate_modeset (1 subtest) =============
[08:00:59] [PASSED] drm_test_check_connector_changed_modeset
[08:00:59] ============== [PASSED] drm_validate_modeset ===============
[08:00:59] ====== drm_test_bridge_get_current_state (1 subtest) =======
[08:00:59] [PASSED] drm_test_drm_bridge_get_current_state_atomic
[08:00:59] ======== [PASSED] drm_test_bridge_get_current_state ========
[08:00:59] ====== drm_test_bridge_helper_reset_crtc (3 subtests) ======
[08:00:59] [PASSED] drm_test_drm_bridge_helper_reset_crtc_atomic
[08:00:59] [PASSED] drm_test_drm_bridge_helper_reset_crtc_atomic_disabled
[08:00:59] [PASSED] drm_test_drm_bridge_helper_hdmi_output_bus_fmts
[08:00:59] ======== [PASSED] drm_test_bridge_helper_reset_crtc ========
[08:00:59] ============== drm_bridge_alloc (2 subtests) ===============
[08:00:59] [PASSED] drm_test_drm_bridge_alloc_basic
[08:00:59] [PASSED] drm_test_drm_bridge_alloc_get_put
[08:00:59] ================ [PASSED] drm_bridge_alloc =================
[08:00:59] ============= drm_bridge_bus_fmt (5 subtests) ==============
[08:00:59] [PASSED] drm_test_bridge_rgb_yuv_rgb
[08:00:59] [PASSED] drm_test_bridge_must_convert_to_yuv444
[08:00:59] [PASSED] drm_test_bridge_hdmi_auto_rgb
[08:00:59] [PASSED] drm_test_bridge_auto_first
[08:00:59] [PASSED] drm_test_bridge_rgb_yuv_no_path
[08:00:59] =============== [PASSED] drm_bridge_bus_fmt ================
[08:00:59] ============= drm_cmdline_parser (40 subtests) =============
[08:00:59] [PASSED] drm_test_cmdline_force_d_only
[08:00:59] [PASSED] drm_test_cmdline_force_D_only_dvi
[08:00:59] [PASSED] drm_test_cmdline_force_D_only_hdmi
[08:00:59] [PASSED] drm_test_cmdline_force_D_only_not_digital
[08:00:59] [PASSED] drm_test_cmdline_force_e_only
[08:00:59] [PASSED] drm_test_cmdline_res
[08:00:59] [PASSED] drm_test_cmdline_res_vesa
[08:00:59] [PASSED] drm_test_cmdline_res_vesa_rblank
[08:00:59] [PASSED] drm_test_cmdline_res_rblank
[08:00:59] [PASSED] drm_test_cmdline_res_bpp
[08:00:59] [PASSED] drm_test_cmdline_res_refresh
[08:00:59] [PASSED] drm_test_cmdline_res_bpp_refresh
[08:00:59] [PASSED] drm_test_cmdline_res_bpp_refresh_interlaced
[08:00:59] [PASSED] drm_test_cmdline_res_bpp_refresh_margins
[08:00:59] [PASSED] drm_test_cmdline_res_bpp_refresh_force_off
[08:00:59] [PASSED] drm_test_cmdline_res_bpp_refresh_force_on
[08:00:59] [PASSED] drm_test_cmdline_res_bpp_refresh_force_on_analog
[08:00:59] [PASSED] drm_test_cmdline_res_bpp_refresh_force_on_digital
[08:00:59] [PASSED] drm_test_cmdline_res_bpp_refresh_interlaced_margins_force_on
[08:00:59] [PASSED] drm_test_cmdline_res_margins_force_on
[08:00:59] [PASSED] drm_test_cmdline_res_vesa_margins
[08:00:59] [PASSED] drm_test_cmdline_name
[08:00:59] [PASSED] drm_test_cmdline_name_bpp
[08:00:59] [PASSED] drm_test_cmdline_name_option
[08:00:59] [PASSED] drm_test_cmdline_name_bpp_option
[08:00:59] [PASSED] drm_test_cmdline_rotate_0
[08:00:59] [PASSED] drm_test_cmdline_rotate_90
[08:00:59] [PASSED] drm_test_cmdline_rotate_180
[08:00:59] [PASSED] drm_test_cmdline_rotate_270
[08:00:59] [PASSED] drm_test_cmdline_hmirror
[08:00:59] [PASSED] drm_test_cmdline_vmirror
[08:00:59] [PASSED] drm_test_cmdline_margin_options
[08:00:59] [PASSED] drm_test_cmdline_multiple_options
[08:00:59] [PASSED] drm_test_cmdline_bpp_extra_and_option
[08:00:59] [PASSED] drm_test_cmdline_extra_and_option
[08:00:59] [PASSED] drm_test_cmdline_freestanding_options
[08:00:59] [PASSED] drm_test_cmdline_freestanding_force_e_and_options
[08:00:59] [PASSED] drm_test_cmdline_panel_orientation
[08:00:59] ================ drm_test_cmdline_invalid  =================
[08:00:59] [PASSED] margin_only
[08:00:59] [PASSED] interlace_only
[08:00:59] [PASSED] res_missing_x
[08:00:59] [PASSED] res_missing_y
[08:00:59] [PASSED] res_bad_y
[08:00:59] [PASSED] res_missing_y_bpp
[08:00:59] [PASSED] res_bad_bpp
[08:00:59] [PASSED] res_bad_refresh
[08:00:59] [PASSED] res_bpp_refresh_force_on_off
[08:00:59] [PASSED] res_invalid_mode
[08:00:59] [PASSED] res_bpp_wrong_place_mode
[08:00:59] [PASSED] name_bpp_refresh
[08:00:59] [PASSED] name_refresh
[08:00:59] [PASSED] name_refresh_wrong_mode
[08:00:59] [PASSED] name_refresh_invalid_mode
[08:00:59] [PASSED] rotate_multiple
[08:00:59] [PASSED] rotate_invalid_val
[08:00:59] [PASSED] rotate_truncated
[08:00:59] [PASSED] invalid_option
[08:00:59] [PASSED] invalid_tv_option
[08:00:59] [PASSED] truncated_tv_option
[08:00:59] ============ [PASSED] drm_test_cmdline_invalid =============
[08:00:59] =============== drm_test_cmdline_tv_options  ===============
[08:00:59] [PASSED] NTSC
[08:00:59] [PASSED] NTSC_443
[08:00:59] [PASSED] NTSC_J
[08:00:59] [PASSED] PAL
[08:00:59] [PASSED] PAL_M
[08:00:59] [PASSED] PAL_N
[08:00:59] [PASSED] SECAM
[08:00:59] [PASSED] MONO_525
[08:00:59] [PASSED] MONO_625
[08:00:59] =========== [PASSED] drm_test_cmdline_tv_options ===========
[08:00:59] =============== [PASSED] drm_cmdline_parser ================
[08:00:59] ========== drmm_connector_hdmi_init (20 subtests) ==========
[08:00:59] [PASSED] drm_test_connector_hdmi_init_valid
[08:00:59] [PASSED] drm_test_connector_hdmi_init_bpc_8
[08:00:59] [PASSED] drm_test_connector_hdmi_init_bpc_10
[08:00:59] [PASSED] drm_test_connector_hdmi_init_bpc_12
[08:00:59] [PASSED] drm_test_connector_hdmi_init_bpc_invalid
[08:00:59] [PASSED] drm_test_connector_hdmi_init_bpc_null
[08:00:59] [PASSED] drm_test_connector_hdmi_init_formats_empty
[08:00:59] [PASSED] drm_test_connector_hdmi_init_formats_no_rgb
[08:00:59] === drm_test_connector_hdmi_init_formats_yuv420_allowed  ===
[08:00:59] [PASSED] supported_formats=0x9 yuv420_allowed=1
[08:00:59] [PASSED] supported_formats=0x9 yuv420_allowed=0
[08:00:59] [PASSED] supported_formats=0x5 yuv420_allowed=1
[08:00:59] [PASSED] supported_formats=0x5 yuv420_allowed=0
[08:00:59] === [PASSED] drm_test_connector_hdmi_init_formats_yuv420_allowed ===
[08:00:59] [PASSED] drm_test_connector_hdmi_init_null_ddc
[08:00:59] [PASSED] drm_test_connector_hdmi_init_null_product
[08:00:59] [PASSED] drm_test_connector_hdmi_init_null_vendor
[08:00:59] [PASSED] drm_test_connector_hdmi_init_product_length_exact
[08:00:59] [PASSED] drm_test_connector_hdmi_init_product_length_too_long
[08:00:59] [PASSED] drm_test_connector_hdmi_init_product_valid
[08:00:59] [PASSED] drm_test_connector_hdmi_init_vendor_length_exact
[08:00:59] [PASSED] drm_test_connector_hdmi_init_vendor_length_too_long
[08:00:59] [PASSED] drm_test_connector_hdmi_init_vendor_valid
[08:00:59] ========= drm_test_connector_hdmi_init_type_valid  =========
[08:00:59] [PASSED] HDMI-A
[08:00:59] [PASSED] HDMI-B
[08:00:59] ===== [PASSED] drm_test_connector_hdmi_init_type_valid =====
[08:00:59] ======== drm_test_connector_hdmi_init_type_invalid  ========
[08:00:59] [PASSED] Unknown
[08:00:59] [PASSED] VGA
[08:00:59] [PASSED] DVI-I
[08:00:59] [PASSED] DVI-D
[08:00:59] [PASSED] DVI-A
[08:00:59] [PASSED] Composite
[08:00:59] [PASSED] SVIDEO
[08:00:59] [PASSED] LVDS
[08:00:59] [PASSED] Component
[08:00:59] [PASSED] DIN
[08:00:59] [PASSED] DP
[08:00:59] [PASSED] TV
[08:00:59] [PASSED] eDP
[08:00:59] [PASSED] Virtual
[08:00:59] [PASSED] DSI
[08:00:59] [PASSED] DPI
[08:00:59] [PASSED] Writeback
[08:00:59] [PASSED] SPI
[08:00:59] [PASSED] USB
[08:00:59] ==== [PASSED] drm_test_connector_hdmi_init_type_invalid ====
[08:00:59] ============ [PASSED] drmm_connector_hdmi_init =============
[08:00:59] ============= drmm_connector_init (3 subtests) =============
[08:00:59] [PASSED] drm_test_drmm_connector_init
[08:00:59] [PASSED] drm_test_drmm_connector_init_null_ddc
[08:00:59] ========= drm_test_drmm_connector_init_type_valid  =========
[08:00:59] [PASSED] Unknown
[08:00:59] [PASSED] VGA
[08:00:59] [PASSED] DVI-I
[08:00:59] [PASSED] DVI-D
[08:00:59] [PASSED] DVI-A
[08:00:59] [PASSED] Composite
[08:00:59] [PASSED] SVIDEO
[08:00:59] [PASSED] LVDS
[08:00:59] [PASSED] Component
[08:00:59] [PASSED] DIN
[08:00:59] [PASSED] DP
[08:00:59] [PASSED] HDMI-A
[08:00:59] [PASSED] HDMI-B
[08:00:59] [PASSED] TV
[08:00:59] [PASSED] eDP
[08:00:59] [PASSED] Virtual
[08:00:59] [PASSED] DSI
[08:00:59] [PASSED] DPI
[08:00:59] [PASSED] Writeback
[08:00:59] [PASSED] SPI
[08:00:59] [PASSED] USB
[08:00:59] ===== [PASSED] drm_test_drmm_connector_init_type_valid =====
[08:00:59] =============== [PASSED] drmm_connector_init ===============
[08:00:59] ========= drm_connector_dynamic_init (6 subtests) ==========
[08:00:59] [PASSED] drm_test_drm_connector_dynamic_init
[08:00:59] [PASSED] drm_test_drm_connector_dynamic_init_null_ddc
[08:00:59] [PASSED] drm_test_drm_connector_dynamic_init_not_added
[08:00:59] [PASSED] drm_test_drm_connector_dynamic_init_properties
[08:00:59] ===== drm_test_drm_connector_dynamic_init_type_valid  ======
[08:00:59] [PASSED] Unknown
[08:00:59] [PASSED] VGA
[08:00:59] [PASSED] DVI-I
[08:00:59] [PASSED] DVI-D
[08:00:59] [PASSED] DVI-A
[08:00:59] [PASSED] Composite
[08:00:59] [PASSED] SVIDEO
[08:00:59] [PASSED] LVDS
[08:00:59] [PASSED] Component
[08:00:59] [PASSED] DIN
[08:00:59] [PASSED] DP
[08:00:59] [PASSED] HDMI-A
[08:00:59] [PASSED] HDMI-B
[08:00:59] [PASSED] TV
[08:00:59] [PASSED] eDP
[08:00:59] [PASSED] Virtual
[08:00:59] [PASSED] DSI
[08:00:59] [PASSED] DPI
[08:00:59] [PASSED] Writeback
[08:00:59] [PASSED] SPI
[08:00:59] [PASSED] USB
[08:00:59] = [PASSED] drm_test_drm_connector_dynamic_init_type_valid ==
[08:00:59] ======== drm_test_drm_connector_dynamic_init_name  =========
[08:00:59] [PASSED] Unknown
[08:00:59] [PASSED] VGA
[08:00:59] [PASSED] DVI-I
[08:00:59] [PASSED] DVI-D
[08:00:59] [PASSED] DVI-A
[08:00:59] [PASSED] Composite
[08:00:59] [PASSED] SVIDEO
[08:00:59] [PASSED] LVDS
[08:00:59] [PASSED] Component
[08:00:59] [PASSED] DIN
[08:00:59] [PASSED] DP
[08:00:59] [PASSED] HDMI-A
[08:00:59] [PASSED] HDMI-B
[08:00:59] [PASSED] TV
[08:00:59] [PASSED] eDP
[08:00:59] [PASSED] Virtual
[08:00:59] [PASSED] DSI
[08:00:59] [PASSED] DPI
[08:00:59] [PASSED] Writeback
[08:00:59] [PASSED] SPI
[08:00:59] [PASSED] USB
[08:00:59] ==== [PASSED] drm_test_drm_connector_dynamic_init_name =====
[08:00:59] =========== [PASSED] drm_connector_dynamic_init ============
[08:00:59] ==== drm_connector_dynamic_register_early (4 subtests) =====
[08:00:59] [PASSED] drm_test_drm_connector_dynamic_register_early_on_list
[08:00:59] [PASSED] drm_test_drm_connector_dynamic_register_early_defer
[08:00:59] [PASSED] drm_test_drm_connector_dynamic_register_early_no_init
[08:00:59] [PASSED] drm_test_drm_connector_dynamic_register_early_no_mode_object
[08:00:59] ====== [PASSED] drm_connector_dynamic_register_early =======
[08:00:59] ======= drm_connector_dynamic_register (7 subtests) ========
[08:00:59] [PASSED] drm_test_drm_connector_dynamic_register_on_list
[08:00:59] [PASSED] drm_test_drm_connector_dynamic_register_no_defer
[08:00:59] [PASSED] drm_test_drm_connector_dynamic_register_no_init
[08:00:59] [PASSED] drm_test_drm_connector_dynamic_register_mode_object
[08:00:59] [PASSED] drm_test_drm_connector_dynamic_register_sysfs
[08:00:59] [PASSED] drm_test_drm_connector_dynamic_register_sysfs_name
[08:00:59] [PASSED] drm_test_drm_connector_dynamic_register_debugfs
[08:00:59] ========= [PASSED] drm_connector_dynamic_register ==========
[08:00:59] = drm_connector_attach_broadcast_rgb_property (2 subtests) =
[08:00:59] [PASSED] drm_test_drm_connector_attach_broadcast_rgb_property
[08:00:59] [PASSED] drm_test_drm_connector_attach_broadcast_rgb_property_hdmi_connector
[08:00:59] === [PASSED] drm_connector_attach_broadcast_rgb_property ===
[08:00:59] ========== drm_get_tv_mode_from_name (2 subtests) ==========
[08:00:59] ========== drm_test_get_tv_mode_from_name_valid  ===========
[08:00:59] [PASSED] NTSC
[08:00:59] [PASSED] NTSC-443
[08:00:59] [PASSED] NTSC-J
[08:00:59] [PASSED] PAL
[08:00:59] [PASSED] PAL-M
[08:00:59] [PASSED] PAL-N
[08:00:59] [PASSED] SECAM
[08:00:59] [PASSED] Mono
[08:00:59] ====== [PASSED] drm_test_get_tv_mode_from_name_valid =======
[08:00:59] [PASSED] drm_test_get_tv_mode_from_name_truncated
[08:00:59] ============ [PASSED] drm_get_tv_mode_from_name ============
[08:00:59] = drm_test_connector_hdmi_compute_mode_clock (12 subtests) =
[08:00:59] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb
[08:00:59] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_10bpc
[08:00:59] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_10bpc_vic_1
[08:00:59] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_12bpc
[08:00:59] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_12bpc_vic_1
[08:00:59] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_double
[08:00:59] = drm_test_connector_hdmi_compute_mode_clock_yuv420_valid  =
[08:00:59] [PASSED] VIC 96
[08:00:59] [PASSED] VIC 97
[08:00:59] [PASSED] VIC 101
[08:00:59] [PASSED] VIC 102
[08:00:59] [PASSED] VIC 106
[08:00:59] [PASSED] VIC 107
[08:00:59] === [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv420_valid ===
[08:00:59] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv420_10_bpc
[08:00:59] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv420_12_bpc
[08:00:59] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv422_8_bpc
[08:00:59] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv422_10_bpc
[08:00:59] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv422_12_bpc
[08:00:59] === [PASSED] drm_test_connector_hdmi_compute_mode_clock ====
[08:00:59] == drm_hdmi_connector_get_broadcast_rgb_name (2 subtests) ==
[08:00:59] === drm_test_drm_hdmi_connector_get_broadcast_rgb_name  ====
[08:00:59] [PASSED] Automatic
[08:00:59] [PASSED] Full
[08:00:59] [PASSED] Limited 16:235
[08:00:59] === [PASSED] drm_test_drm_hdmi_connector_get_broadcast_rgb_name ===
[08:00:59] [PASSED] drm_test_drm_hdmi_connector_get_broadcast_rgb_name_invalid
[08:00:59] ==== [PASSED] drm_hdmi_connector_get_broadcast_rgb_name ====
[08:00:59] == drm_hdmi_connector_get_output_format_name (2 subtests) ==
[08:00:59] === drm_test_drm_hdmi_connector_get_output_format_name  ====
[08:00:59] [PASSED] RGB
[08:00:59] [PASSED] YUV 4:2:0
[08:00:59] [PASSED] YUV 4:2:2
[08:00:59] [PASSED] YUV 4:4:4
[08:00:59] === [PASSED] drm_test_drm_hdmi_connector_get_output_format_name ===
[08:00:59] [PASSED] drm_test_drm_hdmi_connector_get_output_format_name_invalid
[08:00:59] ==== [PASSED] drm_hdmi_connector_get_output_format_name ====
[08:00:59] ============= drm_damage_helper (21 subtests) ==============
[08:00:59] [PASSED] drm_test_damage_iter_no_damage
[08:00:59] [PASSED] drm_test_damage_iter_no_damage_fractional_src
[08:00:59] [PASSED] drm_test_damage_iter_no_damage_src_moved
[08:00:59] [PASSED] drm_test_damage_iter_no_damage_fractional_src_moved
[08:00:59] [PASSED] drm_test_damage_iter_no_damage_not_visible
[08:00:59] [PASSED] drm_test_damage_iter_no_damage_no_crtc
[08:00:59] [PASSED] drm_test_damage_iter_no_damage_no_fb
[08:00:59] [PASSED] drm_test_damage_iter_simple_damage
[08:00:59] [PASSED] drm_test_damage_iter_single_damage
[08:00:59] [PASSED] drm_test_damage_iter_single_damage_intersect_src
[08:00:59] [PASSED] drm_test_damage_iter_single_damage_outside_src
[08:00:59] [PASSED] drm_test_damage_iter_single_damage_fractional_src
[08:00:59] [PASSED] drm_test_damage_iter_single_damage_intersect_fractional_src
[08:00:59] [PASSED] drm_test_damage_iter_single_damage_outside_fractional_src
[08:00:59] [PASSED] drm_test_damage_iter_single_damage_src_moved
[08:00:59] [PASSED] drm_test_damage_iter_single_damage_fractional_src_moved
[08:00:59] [PASSED] drm_test_damage_iter_damage
[08:00:59] [PASSED] drm_test_damage_iter_damage_one_intersect
[08:00:59] [PASSED] drm_test_damage_iter_damage_one_outside
[08:00:59] [PASSED] drm_test_damage_iter_damage_src_moved
[08:00:59] [PASSED] drm_test_damage_iter_damage_not_visible
[08:00:59] ================ [PASSED] drm_damage_helper ================
[08:00:59] ============== drm_dp_mst_helper (3 subtests) ==============
[08:00:59] ============== drm_test_dp_mst_calc_pbn_mode  ==============
[08:00:59] [PASSED] Clock 154000 BPP 30 DSC disabled
[08:00:59] [PASSED] Clock 234000 BPP 30 DSC disabled
[08:00:59] [PASSED] Clock 297000 BPP 24 DSC disabled
[08:00:59] [PASSED] Clock 332880 BPP 24 DSC enabled
[08:00:59] [PASSED] Clock 324540 BPP 24 DSC enabled
[08:00:59] ========== [PASSED] drm_test_dp_mst_calc_pbn_mode ==========
[08:00:59] ============== drm_test_dp_mst_calc_pbn_div  ===============
[08:00:59] [PASSED] Link rate 2000000 lane count 4
[08:00:59] [PASSED] Link rate 2000000 lane count 2
[08:00:59] [PASSED] Link rate 2000000 lane count 1
[08:00:59] [PASSED] Link rate 1350000 lane count 4
[08:00:59] [PASSED] Link rate 1350000 lane count 2
[08:00:59] [PASSED] Link rate 1350000 lane count 1
[08:00:59] [PASSED] Link rate 1000000 lane count 4
[08:00:59] [PASSED] Link rate 1000000 lane count 2
[08:00:59] [PASSED] Link rate 1000000 lane count 1
[08:00:59] [PASSED] Link rate 810000 lane count 4
[08:00:59] [PASSED] Link rate 810000 lane count 2
[08:00:59] [PASSED] Link rate 810000 lane count 1
[08:00:59] [PASSED] Link rate 540000 lane count 4
[08:00:59] [PASSED] Link rate 540000 lane count 2
[08:00:59] [PASSED] Link rate 540000 lane count 1
[08:00:59] [PASSED] Link rate 270000 lane count 4
[08:00:59] [PASSED] Link rate 270000 lane count 2
[08:00:59] [PASSED] Link rate 270000 lane count 1
[08:00:59] [PASSED] Link rate 162000 lane count 4
[08:00:59] [PASSED] Link rate 162000 lane count 2
[08:00:59] [PASSED] Link rate 162000 lane count 1
[08:00:59] ========== [PASSED] drm_test_dp_mst_calc_pbn_div ===========
[08:00:59] ========= drm_test_dp_mst_sideband_msg_req_decode  =========
[08:00:59] [PASSED] DP_ENUM_PATH_RESOURCES with port number
[08:00:59] [PASSED] DP_POWER_UP_PHY with port number
[08:00:59] [PASSED] DP_POWER_DOWN_PHY with port number
[08:00:59] [PASSED] DP_ALLOCATE_PAYLOAD with SDP stream sinks
[08:00:59] [PASSED] DP_ALLOCATE_PAYLOAD with port number
[08:00:59] [PASSED] DP_ALLOCATE_PAYLOAD with VCPI
[08:00:59] [PASSED] DP_ALLOCATE_PAYLOAD with PBN
[08:00:59] [PASSED] DP_QUERY_PAYLOAD with port number
[08:00:59] [PASSED] DP_QUERY_PAYLOAD with VCPI
[08:00:59] [PASSED] DP_REMOTE_DPCD_READ with port number
[08:00:59] [PASSED] DP_REMOTE_DPCD_READ with DPCD address
[08:00:59] [PASSED] DP_REMOTE_DPCD_READ with max number of bytes
[08:00:59] [PASSED] DP_REMOTE_DPCD_WRITE with port number
[08:00:59] [PASSED] DP_REMOTE_DPCD_WRITE with DPCD address
[08:00:59] [PASSED] DP_REMOTE_DPCD_WRITE with data array
[08:00:59] [PASSED] DP_REMOTE_I2C_READ with port number
[08:00:59] [PASSED] DP_REMOTE_I2C_READ with I2C device ID
[08:00:59] [PASSED] DP_REMOTE_I2C_READ with transactions array
[08:00:59] [PASSED] DP_REMOTE_I2C_WRITE with port number
[08:00:59] [PASSED] DP_REMOTE_I2C_WRITE with I2C device ID
[08:00:59] [PASSED] DP_REMOTE_I2C_WRITE with data array
[08:00:59] [PASSED] DP_QUERY_STREAM_ENC_STATUS with stream ID
[08:00:59] [PASSED] DP_QUERY_STREAM_ENC_STATUS with client ID
[08:00:59] [PASSED] DP_QUERY_STREAM_ENC_STATUS with stream event
[08:00:59] [PASSED] DP_QUERY_STREAM_ENC_STATUS with valid stream event
[08:00:59] [PASSED] DP_QUERY_STREAM_ENC_STATUS with stream behavior
[08:00:59] [PASSED] DP_QUERY_STREAM_ENC_STATUS with a valid stream behavior
[08:00:59] ===== [PASSED] drm_test_dp_mst_sideband_msg_req_decode =====
[08:00:59] ================ [PASSED] drm_dp_mst_helper ================
[08:00:59] ================== drm_exec (7 subtests) ===================
[08:00:59] [PASSED] sanitycheck
[08:00:59] [PASSED] test_lock
[08:00:59] [PASSED] test_lock_unlock
[08:00:59] [PASSED] test_duplicates
[08:00:59] [PASSED] test_prepare
[08:00:59] [PASSED] test_prepare_array
[08:00:59] [PASSED] test_multiple_loops
[08:00:59] ==================== [PASSED] drm_exec =====================
[08:00:59] =========== drm_format_helper_test (17 subtests) ===========
[08:00:59] ============== drm_test_fb_xrgb8888_to_gray8  ==============
[08:00:59] [PASSED] single_pixel_source_buffer
[08:00:59] [PASSED] single_pixel_clip_rectangle
[08:00:59] [PASSED] well_known_colors
[08:00:59] [PASSED] destination_pitch
[08:00:59] ========== [PASSED] drm_test_fb_xrgb8888_to_gray8 ==========
[08:00:59] ============= drm_test_fb_xrgb8888_to_rgb332  ==============
[08:00:59] [PASSED] single_pixel_source_buffer
[08:00:59] [PASSED] single_pixel_clip_rectangle
[08:00:59] [PASSED] well_known_colors
[08:00:59] [PASSED] destination_pitch
[08:00:59] ========= [PASSED] drm_test_fb_xrgb8888_to_rgb332 ==========
[08:00:59] ============= drm_test_fb_xrgb8888_to_rgb565  ==============
[08:00:59] [PASSED] single_pixel_source_buffer
[08:00:59] [PASSED] single_pixel_clip_rectangle
[08:00:59] [PASSED] well_known_colors
[08:00:59] [PASSED] destination_pitch
[08:00:59] ========= [PASSED] drm_test_fb_xrgb8888_to_rgb565 ==========
[08:00:59] ============ drm_test_fb_xrgb8888_to_xrgb1555  =============
[08:00:59] [PASSED] single_pixel_source_buffer
[08:00:59] [PASSED] single_pixel_clip_rectangle
[08:00:59] [PASSED] well_known_colors
[08:00:59] [PASSED] destination_pitch
[08:00:59] ======== [PASSED] drm_test_fb_xrgb8888_to_xrgb1555 =========
[08:00:59] ============ drm_test_fb_xrgb8888_to_argb1555  =============
[08:00:59] [PASSED] single_pixel_source_buffer
[08:00:59] [PASSED] single_pixel_clip_rectangle
[08:00:59] [PASSED] well_known_colors
[08:00:59] [PASSED] destination_pitch
[08:00:59] ======== [PASSED] drm_test_fb_xrgb8888_to_argb1555 =========
[08:00:59] ============ drm_test_fb_xrgb8888_to_rgba5551  =============
[08:00:59] [PASSED] single_pixel_source_buffer
[08:00:59] [PASSED] single_pixel_clip_rectangle
[08:00:59] [PASSED] well_known_colors
[08:00:59] [PASSED] destination_pitch
[08:00:59] ======== [PASSED] drm_test_fb_xrgb8888_to_rgba5551 =========
[08:00:59] ============= drm_test_fb_xrgb8888_to_rgb888  ==============
[08:00:59] [PASSED] single_pixel_source_buffer
[08:00:59] [PASSED] single_pixel_clip_rectangle
[08:00:59] [PASSED] well_known_colors
[08:00:59] [PASSED] destination_pitch
[08:00:59] ========= [PASSED] drm_test_fb_xrgb8888_to_rgb888 ==========
[08:00:59] ============= drm_test_fb_xrgb8888_to_bgr888  ==============
[08:00:59] [PASSED] single_pixel_source_buffer
[08:00:59] [PASSED] single_pixel_clip_rectangle
[08:00:59] [PASSED] well_known_colors
[08:00:59] [PASSED] destination_pitch
[08:00:59] ========= [PASSED] drm_test_fb_xrgb8888_to_bgr888 ==========
[08:00:59] ============ drm_test_fb_xrgb8888_to_argb8888  =============
[08:00:59] [PASSED] single_pixel_source_buffer
[08:00:59] [PASSED] single_pixel_clip_rectangle
[08:00:59] [PASSED] well_known_colors
[08:00:59] [PASSED] destination_pitch
[08:00:59] ======== [PASSED] drm_test_fb_xrgb8888_to_argb8888 =========
[08:00:59] =========== drm_test_fb_xrgb8888_to_xrgb2101010  ===========
[08:00:59] [PASSED] single_pixel_source_buffer
[08:00:59] [PASSED] single_pixel_clip_rectangle
[08:00:59] [PASSED] well_known_colors
[08:00:59] [PASSED] destination_pitch
[08:00:59] ======= [PASSED] drm_test_fb_xrgb8888_to_xrgb2101010 =======
[08:00:59] =========== drm_test_fb_xrgb8888_to_argb2101010  ===========
[08:00:59] [PASSED] single_pixel_source_buffer
[08:00:59] [PASSED] single_pixel_clip_rectangle
[08:00:59] [PASSED] well_known_colors
[08:00:59] [PASSED] destination_pitch
[08:00:59] ======= [PASSED] drm_test_fb_xrgb8888_to_argb2101010 =======
[08:00:59] ============== drm_test_fb_xrgb8888_to_mono  ===============
[08:00:59] [PASSED] single_pixel_source_buffer
[08:00:59] [PASSED] single_pixel_clip_rectangle
[08:00:59] [PASSED] well_known_colors
[08:00:59] [PASSED] destination_pitch
[08:00:59] ========== [PASSED] drm_test_fb_xrgb8888_to_mono ===========
[08:00:59] ==================== drm_test_fb_swab  =====================
[08:00:59] [PASSED] single_pixel_source_buffer
[08:00:59] [PASSED] single_pixel_clip_rectangle
[08:00:59] [PASSED] well_known_colors
[08:00:59] [PASSED] destination_pitch
[08:00:59] ================ [PASSED] drm_test_fb_swab =================
[08:00:59] ============ drm_test_fb_xrgb8888_to_xbgr8888  =============
[08:00:59] [PASSED] single_pixel_source_buffer
[08:00:59] [PASSED] single_pixel_clip_rectangle
[08:00:59] [PASSED] well_known_colors
[08:00:59] [PASSED] destination_pitch
[08:00:59] ======== [PASSED] drm_test_fb_xrgb8888_to_xbgr8888 =========
[08:00:59] ============ drm_test_fb_xrgb8888_to_abgr8888  =============
[08:00:59] [PASSED] single_pixel_source_buffer
[08:00:59] [PASSED] single_pixel_clip_rectangle
[08:00:59] [PASSED] well_known_colors
[08:00:59] [PASSED] destination_pitch
[08:00:59] ======== [PASSED] drm_test_fb_xrgb8888_to_abgr8888 =========
[08:00:59] ================= drm_test_fb_clip_offset  =================
[08:00:59] [PASSED] pass through
[08:00:59] [PASSED] horizontal offset
[08:00:59] [PASSED] vertical offset
[08:00:59] [PASSED] horizontal and vertical offset
[08:00:59] [PASSED] horizontal offset (custom pitch)
[08:00:59] [PASSED] vertical offset (custom pitch)
[08:00:59] [PASSED] horizontal and vertical offset (custom pitch)
[08:00:59] ============= [PASSED] drm_test_fb_clip_offset =============
[08:00:59] =================== drm_test_fb_memcpy  ====================
[08:00:59] [PASSED] single_pixel_source_buffer: XR24 little-endian (0x34325258)
[08:00:59] [PASSED] single_pixel_source_buffer: XRA8 little-endian (0x38415258)
[08:00:59] [PASSED] single_pixel_source_buffer: YU24 little-endian (0x34325559)
[08:00:59] [PASSED] single_pixel_clip_rectangle: XB24 little-endian (0x34324258)
[08:00:59] [PASSED] single_pixel_clip_rectangle: XRA8 little-endian (0x38415258)
[08:00:59] [PASSED] single_pixel_clip_rectangle: YU24 little-endian (0x34325559)
[08:00:59] [PASSED] well_known_colors: XB24 little-endian (0x34324258)
[08:00:59] [PASSED] well_known_colors: XRA8 little-endian (0x38415258)
[08:00:59] [PASSED] well_known_colors: YU24 little-endian (0x34325559)
[08:00:59] [PASSED] destination_pitch: XB24 little-endian (0x34324258)
[08:00:59] [PASSED] destination_pitch: XRA8 little-endian (0x38415258)
[08:00:59] [PASSED] destination_pitch: YU24 little-endian (0x34325559)
[08:00:59] =============== [PASSED] drm_test_fb_memcpy ================
[08:00:59] ============= [PASSED] drm_format_helper_test ==============
[08:00:59] ================= drm_format (18 subtests) =================
[08:00:59] [PASSED] drm_test_format_block_width_invalid
[08:00:59] [PASSED] drm_test_format_block_width_one_plane
[08:00:59] [PASSED] drm_test_format_block_width_two_plane
[08:00:59] [PASSED] drm_test_format_block_width_three_plane
[08:00:59] [PASSED] drm_test_format_block_width_tiled
[08:00:59] [PASSED] drm_test_format_block_height_invalid
[08:00:59] [PASSED] drm_test_format_block_height_one_plane
[08:00:59] [PASSED] drm_test_format_block_height_two_plane
[08:00:59] [PASSED] drm_test_format_block_height_three_plane
[08:00:59] [PASSED] drm_test_format_block_height_tiled
[08:00:59] [PASSED] drm_test_format_min_pitch_invalid
[08:00:59] [PASSED] drm_test_format_min_pitch_one_plane_8bpp
[08:00:59] [PASSED] drm_test_format_min_pitch_one_plane_16bpp
[08:00:59] [PASSED] drm_test_format_min_pitch_one_plane_24bpp
[08:00:59] [PASSED] drm_test_format_min_pitch_one_plane_32bpp
[08:00:59] [PASSED] drm_test_format_min_pitch_two_plane
[08:00:59] [PASSED] drm_test_format_min_pitch_three_plane_8bpp
[08:00:59] [PASSED] drm_test_format_min_pitch_tiled
[08:00:59] =================== [PASSED] drm_format ====================
[08:00:59] ============== drm_framebuffer (10 subtests) ===============
[08:00:59] ========== drm_test_framebuffer_check_src_coords  ==========
[08:00:59] [PASSED] Success: source fits into fb
[08:00:59] [PASSED] Fail: overflowing fb with x-axis coordinate
[08:00:59] [PASSED] Fail: overflowing fb with y-axis coordinate
[08:00:59] [PASSED] Fail: overflowing fb with source width
[08:00:59] [PASSED] Fail: overflowing fb with source height
[08:00:59] ====== [PASSED] drm_test_framebuffer_check_src_coords ======
[08:00:59] [PASSED] drm_test_framebuffer_cleanup
[08:00:59] =============== drm_test_framebuffer_create  ===============
[08:00:59] [PASSED] ABGR8888 normal sizes
[08:00:59] [PASSED] ABGR8888 max sizes
[08:00:59] [PASSED] ABGR8888 pitch greater than min required
[08:00:59] [PASSED] ABGR8888 pitch less than min required
[08:00:59] [PASSED] ABGR8888 Invalid width
[08:00:59] [PASSED] ABGR8888 Invalid buffer handle
[08:00:59] [PASSED] No pixel format
[08:00:59] [PASSED] ABGR8888 Width 0
[08:00:59] [PASSED] ABGR8888 Height 0
[08:00:59] [PASSED] ABGR8888 Out of bound height * pitch combination
[08:00:59] [PASSED] ABGR8888 Large buffer offset
[08:00:59] [PASSED] ABGR8888 Buffer offset for inexistent plane
[08:00:59] [PASSED] ABGR8888 Invalid flag
[08:00:59] [PASSED] ABGR8888 Set DRM_MODE_FB_MODIFIERS without modifiers
[08:00:59] [PASSED] ABGR8888 Valid buffer modifier
[08:00:59] [PASSED] ABGR8888 Invalid buffer modifier(DRM_FORMAT_MOD_SAMSUNG_64_32_TILE)
[08:00:59] [PASSED] ABGR8888 Extra pitches without DRM_MODE_FB_MODIFIERS
[08:00:59] [PASSED] ABGR8888 Extra pitches with DRM_MODE_FB_MODIFIERS
[08:00:59] [PASSED] NV12 Normal sizes
[08:00:59] [PASSED] NV12 Max sizes
[08:00:59] [PASSED] NV12 Invalid pitch
[08:00:59] [PASSED] NV12 Invalid modifier/missing DRM_MODE_FB_MODIFIERS flag
[08:00:59] [PASSED] NV12 different  modifier per-plane
[08:00:59] [PASSED] NV12 with DRM_FORMAT_MOD_SAMSUNG_64_32_TILE
[08:00:59] [PASSED] NV12 Valid modifiers without DRM_MODE_FB_MODIFIERS
[08:00:59] [PASSED] NV12 Modifier for inexistent plane
[08:00:59] [PASSED] NV12 Handle for inexistent plane
[08:00:59] [PASSED] NV12 Handle for inexistent plane without DRM_MODE_FB_MODIFIERS
[08:00:59] [PASSED] YVU420 DRM_MODE_FB_MODIFIERS set without modifier
[08:00:59] [PASSED] YVU420 Normal sizes
[08:00:59] [PASSED] YVU420 Max sizes
[08:00:59] [PASSED] YVU420 Invalid pitch
[08:00:59] [PASSED] YVU420 Different pitches
[08:00:59] [PASSED] YVU420 Different buffer offsets/pitches
[08:00:59] [PASSED] YVU420 Modifier set just for plane 0, without DRM_MODE_FB_MODIFIERS
[08:00:59] [PASSED] YVU420 Modifier set just for planes 0, 1, without DRM_MODE_FB_MODIFIERS
[08:00:59] [PASSED] YVU420 Modifier set just for plane 0, 1, with DRM_MODE_FB_MODIFIERS
[08:00:59] [PASSED] YVU420 Valid modifier
[08:00:59] [PASSED] YVU420 Different modifiers per plane
[08:00:59] [PASSED] YVU420 Modifier for inexistent plane
[08:00:59] [PASSED] YUV420_10BIT Invalid modifier(DRM_FORMAT_MOD_LINEAR)
[08:00:59] [PASSED] X0L2 Normal sizes
[08:00:59] [PASSED] X0L2 Max sizes
[08:00:59] [PASSED] X0L2 Invalid pitch
[08:00:59] [PASSED] X0L2 Pitch greater than minimum required
[08:00:59] [PASSED] X0L2 Handle for inexistent plane
[08:00:59] [PASSED] X0L2 Offset for inexistent plane, without DRM_MODE_FB_MODIFIERS set
[08:00:59] [PASSED] X0L2 Modifier without DRM_MODE_FB_MODIFIERS set
[08:00:59] [PASSED] X0L2 Valid modifier
[08:00:59] [PASSED] X0L2 Modifier for inexistent plane
[08:00:59] =========== [PASSED] drm_test_framebuffer_create ===========
[08:00:59] [PASSED] drm_test_framebuffer_free
[08:00:59] [PASSED] drm_test_framebuffer_init
[08:00:59] [PASSED] drm_test_framebuffer_init_bad_format
[08:00:59] [PASSED] drm_test_framebuffer_init_dev_mismatch
[08:00:59] [PASSED] drm_test_framebuffer_lookup
[08:00:59] [PASSED] drm_test_framebuffer_lookup_inexistent
[08:00:59] [PASSED] drm_test_framebuffer_modifiers_not_supported
[08:00:59] ================= [PASSED] drm_framebuffer =================
[08:00:59] ================ drm_gem_shmem (8 subtests) ================
[08:00:59] [PASSED] drm_gem_shmem_test_obj_create
[08:00:59] [PASSED] drm_gem_shmem_test_obj_create_private
[08:00:59] [PASSED] drm_gem_shmem_test_pin_pages
[08:00:59] [PASSED] drm_gem_shmem_test_vmap
[08:00:59] [PASSED] drm_gem_shmem_test_get_sg_table
[08:00:59] [PASSED] drm_gem_shmem_test_get_pages_sgt
[08:00:59] [PASSED] drm_gem_shmem_test_madvise
[08:00:59] [PASSED] drm_gem_shmem_test_purge
[08:00:59] ================== [PASSED] drm_gem_shmem ==================
[08:00:59] === drm_atomic_helper_connector_hdmi_check (29 subtests) ===
[08:00:59] [PASSED] drm_test_check_broadcast_rgb_auto_cea_mode
[08:00:59] [PASSED] drm_test_check_broadcast_rgb_auto_cea_mode_vic_1
[08:00:59] [PASSED] drm_test_check_broadcast_rgb_full_cea_mode
[08:00:59] [PASSED] drm_test_check_broadcast_rgb_full_cea_mode_vic_1
[08:00:59] [PASSED] drm_test_check_broadcast_rgb_limited_cea_mode
[08:00:59] [PASSED] drm_test_check_broadcast_rgb_limited_cea_mode_vic_1
[08:00:59] ====== drm_test_check_broadcast_rgb_cea_mode_yuv420  =======
[08:00:59] [PASSED] Automatic
[08:00:59] [PASSED] Full
[08:00:59] [PASSED] Limited 16:235
[08:00:59] == [PASSED] drm_test_check_broadcast_rgb_cea_mode_yuv420 ===
[08:00:59] [PASSED] drm_test_check_broadcast_rgb_crtc_mode_changed
[08:00:59] [PASSED] drm_test_check_broadcast_rgb_crtc_mode_not_changed
[08:00:59] [PASSED] drm_test_check_disable_connector
[08:00:59] [PASSED] drm_test_check_hdmi_funcs_reject_rate
[08:00:59] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_rgb
[08:00:59] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_yuv420
[08:00:59] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_ignore_yuv422
[08:00:59] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_ignore_yuv420
[08:00:59] [PASSED] drm_test_check_driver_unsupported_fallback_yuv420
[08:00:59] [PASSED] drm_test_check_output_bpc_crtc_mode_changed
[08:00:59] [PASSED] drm_test_check_output_bpc_crtc_mode_not_changed
[08:00:59] [PASSED] drm_test_check_output_bpc_dvi
[08:00:59] [PASSED] drm_test_check_output_bpc_format_vic_1
[08:00:59] [PASSED] drm_test_check_output_bpc_format_display_8bpc_only
[08:00:59] [PASSED] drm_test_check_output_bpc_format_display_rgb_only
[08:00:59] [PASSED] drm_test_check_output_bpc_format_driver_8bpc_only
[08:00:59] [PASSED] drm_test_check_output_bpc_format_driver_rgb_only
[08:00:59] [PASSED] drm_test_check_tmds_char_rate_rgb_8bpc
[08:00:59] [PASSED] drm_test_check_tmds_char_rate_rgb_10bpc
[08:00:59] [PASSED] drm_test_check_tmds_char_rate_rgb_12bpc
[08:00:59] ============ drm_test_check_hdmi_color_format  =============
[08:00:59] [PASSED] AUTO -> RGB
[08:00:59] [PASSED] YCBCR422 -> YUV422
[08:00:59] [PASSED] YCBCR420 -> YUV420
[08:00:59] [PASSED] YCBCR444 -> YUV444
[08:00:59] [PASSED] RGB -> RGB
[08:00:59] ======== [PASSED] drm_test_check_hdmi_color_format =========
[08:00:59] ======== drm_test_check_hdmi_color_format_420_only  ========
[08:00:59] [PASSED] RGB should fail
[08:00:59] [PASSED] YUV444 should fail
[08:00:59] [PASSED] YUV422 should fail
[08:00:59] [PASSED] YUV420 should work
[08:00:59] ==== [PASSED] drm_test_check_hdmi_color_format_420_only ====
[08:00:59] ===== [PASSED] drm_atomic_helper_connector_hdmi_check ======
[08:00:59] === drm_atomic_helper_connector_hdmi_reset (6 subtests) ====
[08:00:59] [PASSED] drm_test_check_broadcast_rgb_value
[08:00:59] [PASSED] drm_test_check_bpc_8_value
[08:00:59] [PASSED] drm_test_check_bpc_10_value
[08:00:59] [PASSED] drm_test_check_bpc_12_value
[08:00:59] [PASSED] drm_test_check_format_value
[08:00:59] [PASSED] drm_test_check_tmds_char_value
[08:00:59] ===== [PASSED] drm_atomic_helper_connector_hdmi_reset ======
[08:00:59] = drm_atomic_helper_connector_hdmi_mode_valid (7 subtests) =
[08:00:59] [PASSED] drm_test_check_mode_valid
[08:00:59] [PASSED] drm_test_check_mode_valid_reject
[08:00:59] [PASSED] drm_test_check_mode_valid_reject_rate
[08:00:59] [PASSED] drm_test_check_mode_valid_reject_max_clock
[08:00:59] [PASSED] drm_test_check_mode_valid_yuv420_only_max_clock
[08:00:59] [PASSED] drm_test_check_mode_valid_reject_yuv420_only_connector
[08:00:59] [PASSED] drm_test_check_mode_valid_accept_yuv420_also_connector_rgb
[08:00:59] === [PASSED] drm_atomic_helper_connector_hdmi_mode_valid ===
[08:00:59] = drm_atomic_helper_connector_hdmi_infoframes (5 subtests) =
[08:00:59] [PASSED] drm_test_check_infoframes
[08:00:59] [PASSED] drm_test_check_reject_avi_infoframe
[08:00:59] [PASSED] drm_test_check_reject_hdr_infoframe_bpc_8
[08:00:59] [PASSED] drm_test_check_reject_hdr_infoframe_bpc_10
[08:00:59] [PASSED] drm_test_check_reject_audio_infoframe
[08:00:59] === [PASSED] drm_atomic_helper_connector_hdmi_infoframes ===
[08:00:59] ================= drm_managed (2 subtests) =================
[08:00:59] [PASSED] drm_test_managed_release_action
[08:00:59] [PASSED] drm_test_managed_run_action
[08:00:59] =================== [PASSED] drm_managed ===================
[08:00:59] =================== drm_mm (6 subtests) ====================
[08:00:59] [PASSED] drm_test_mm_init
[08:00:59] [PASSED] drm_test_mm_debug
[08:00:59] [PASSED] drm_test_mm_align32
[08:00:59] [PASSED] drm_test_mm_align64
[08:00:59] [PASSED] drm_test_mm_lowest
[08:00:59] [PASSED] drm_test_mm_highest
[08:00:59] ===================== [PASSED] drm_mm ======================
[08:00:59] ============= drm_modes_analog_tv (5 subtests) =============
[08:00:59] [PASSED] drm_test_modes_analog_tv_mono_576i
[08:00:59] [PASSED] drm_test_modes_analog_tv_ntsc_480i
[08:00:59] [PASSED] drm_test_modes_analog_tv_ntsc_480i_inlined
[08:00:59] [PASSED] drm_test_modes_analog_tv_pal_576i
[08:00:59] [PASSED] drm_test_modes_analog_tv_pal_576i_inlined
[08:00:59] =============== [PASSED] drm_modes_analog_tv ===============
[08:00:59] ============== drm_plane_helper (2 subtests) ===============
[08:00:59] =============== drm_test_check_plane_state  ================
[08:00:59] [PASSED] clipping_simple
[08:00:59] [PASSED] clipping_rotate_reflect
[08:00:59] [PASSED] positioning_simple
[08:00:59] [PASSED] upscaling
[08:00:59] [PASSED] downscaling
[08:00:59] [PASSED] rounding1
[08:00:59] [PASSED] rounding2
[08:00:59] [PASSED] rounding3
[08:00:59] [PASSED] rounding4
[08:00:59] =========== [PASSED] drm_test_check_plane_state ============
[08:00:59] =========== drm_test_check_invalid_plane_state  ============
[08:00:59] [PASSED] positioning_invalid
[08:00:59] [PASSED] upscaling_invalid
[08:00:59] [PASSED] downscaling_invalid
[08:00:59] ======= [PASSED] drm_test_check_invalid_plane_state ========
[08:00:59] ================ [PASSED] drm_plane_helper =================
[08:00:59] ====== drm_connector_helper_tv_get_modes (1 subtest) =======
[08:00:59] ====== drm_test_connector_helper_tv_get_modes_check  =======
[08:00:59] [PASSED] None
[08:00:59] [PASSED] PAL
[08:00:59] [PASSED] NTSC
[08:00:59] [PASSED] Both, NTSC Default
[08:00:59] [PASSED] Both, PAL Default
[08:00:59] [PASSED] Both, NTSC Default, with PAL on command-line
[08:00:59] [PASSED] Both, PAL Default, with NTSC on command-line
[08:00:59] == [PASSED] drm_test_connector_helper_tv_get_modes_check ===
[08:00:59] ======== [PASSED] drm_connector_helper_tv_get_modes ========
[08:00:59] ================== drm_rect (9 subtests) ===================
[08:00:59] [PASSED] drm_test_rect_clip_scaled_div_by_zero
[08:00:59] [PASSED] drm_test_rect_clip_scaled_not_clipped
[08:00:59] [PASSED] drm_test_rect_clip_scaled_clipped
[08:00:59] [PASSED] drm_test_rect_clip_scaled_signed_vs_unsigned
[08:00:59] ================= drm_test_rect_intersect  =================
[08:00:59] [PASSED] top-left x bottom-right: 2x2+1+1 x 2x2+0+0
[08:00:59] [PASSED] top-right x bottom-left: 2x2+0+0 x 2x2+1-1
[08:00:59] [PASSED] bottom-left x top-right: 2x2+1-1 x 2x2+0+0
[08:00:59] [PASSED] bottom-right x top-left: 2x2+0+0 x 2x2+1+1
[08:00:59] [PASSED] right x left: 2x1+0+0 x 3x1+1+0
[08:00:59] [PASSED] left x right: 3x1+1+0 x 2x1+0+0
[08:00:59] [PASSED] up x bottom: 1x2+0+0 x 1x3+0-1
[08:00:59] [PASSED] bottom x up: 1x3+0-1 x 1x2+0+0
[08:00:59] [PASSED] touching corner: 1x1+0+0 x 2x2+1+1
[08:00:59] [PASSED] touching side: 1x1+0+0 x 1x1+1+0
[08:00:59] [PASSED] equal rects: 2x2+0+0 x 2x2+0+0
[08:00:59] [PASSED] inside another: 2x2+0+0 x 1x1+1+1
[08:00:59] [PASSED] far away: 1x1+0+0 x 1x1+3+6
[08:00:59] [PASSED] points intersecting: 0x0+5+10 x 0x0+5+10
[08:00:59] [PASSED] points not intersecting: 0x0+0+0 x 0x0+5+10
[08:00:59] ============= [PASSED] drm_test_rect_intersect =============
[08:00:59] ================ drm_test_rect_calc_hscale  ================
[08:00:59] [PASSED] normal use
[08:00:59] [PASSED] out of max range
[08:00:59] [PASSED] out of min range
[08:00:59] [PASSED] zero dst
[08:00:59] [PASSED] negative src
[08:00:59] [PASSED] negative dst
[08:00:59] ============ [PASSED] drm_test_rect_calc_hscale ============
[08:00:59] ================ drm_test_rect_calc_vscale  ================
[08:00:59] [PASSED] normal use
[08:00:59] [PASSED] out of max range
[08:00:59] [PASSED] out of min range
[08:00:59] [PASSED] zero dst
[08:00:59] [PASSED] negative src
[08:00:59] [PASSED] negative dst
[08:00:59] ============ [PASSED] drm_test_rect_calc_vscale ============
[08:00:59] ================== drm_test_rect_rotate  ===================
[08:00:59] [PASSED] reflect-x
[08:00:59] [PASSED] reflect-y
[08:00:59] [PASSED] rotate-0
[08:00:59] [PASSED] rotate-90
[08:00:59] [PASSED] rotate-180
[08:00:59] [PASSED] rotate-270
[08:00:59] ============== [PASSED] drm_test_rect_rotate ===============
[08:00:59] ================ drm_test_rect_rotate_inv  =================
[08:00:59] [PASSED] reflect-x
[08:00:59] [PASSED] reflect-y
[08:00:59] [PASSED] rotate-0
[08:00:59] [PASSED] rotate-90
[08:00:59] [PASSED] rotate-180
[08:00:59] [PASSED] rotate-270
[08:00:59] ============ [PASSED] drm_test_rect_rotate_inv =============
[08:00:59] ==================== [PASSED] drm_rect =====================
[08:00:59] ============ drm_sysfb_modeset_test (1 subtest) ============
[08:00:59] ============ drm_test_sysfb_build_fourcc_list  =============
[08:00:59] [PASSED] no native formats
[08:00:59] [PASSED] XRGB8888 as native format
[08:00:59] [PASSED] remove duplicates
[08:00:59] [PASSED] convert alpha formats
[08:00:59] [PASSED] random formats
[08:00:59] ======== [PASSED] drm_test_sysfb_build_fourcc_list =========
[08:00:59] ============= [PASSED] drm_sysfb_modeset_test ==============
[08:00:59] ================== drm_fixp (2 subtests) ===================
[08:00:59] [PASSED] drm_test_int2fixp
[08:00:59] [PASSED] drm_test_sm2fixp
[08:00:59] ==================== [PASSED] drm_fixp =====================
[08:00:59] ============================================================
[08:00:59] Testing complete. Ran 637 tests: passed: 637
[08:00:59] Elapsed time: 27.364s total, 1.806s configuring, 25.341s building, 0.182s running

+ /kernel/tools/testing/kunit/kunit.py run --kunitconfig /kernel/drivers/gpu/drm/ttm/tests/.kunitconfig
[08:00:59] Configuring KUnit Kernel ...
Regenerating .config ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
[08:01:01] Building KUnit Kernel ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
Building with:
$ make all compile_commands.json scripts_gdb ARCH=um O=.kunit --jobs=48
[08:01:11] Starting KUnit Kernel (1/1)...
[08:01:11] ============================================================
Running tests with:
$ .kunit/linux kunit.enable=1 mem=1G console=tty kunit_shutdown=halt
[08:01:11] ================= ttm_device (5 subtests) ==================
[08:01:11] [PASSED] ttm_device_init_basic
[08:01:11] [PASSED] ttm_device_init_multiple
[08:01:11] [PASSED] ttm_device_fini_basic
[08:01:11] [PASSED] ttm_device_init_no_vma_man
[08:01:11] ================== ttm_device_init_pools  ==================
[08:01:11] [PASSED] No DMA allocations, no DMA32 required
[08:01:11] [PASSED] DMA allocations, DMA32 required
[08:01:11] [PASSED] No DMA allocations, DMA32 required
[08:01:11] [PASSED] DMA allocations, no DMA32 required
[08:01:11] ============== [PASSED] ttm_device_init_pools ==============
[08:01:11] =================== [PASSED] ttm_device ====================
[08:01:11] ================== ttm_pool (8 subtests) ===================
[08:01:11] ================== ttm_pool_alloc_basic  ===================
[08:01:11] [PASSED] One page
[08:01:11] [PASSED] More than one page
[08:01:11] [PASSED] Above the allocation limit
[08:01:11] [PASSED] One page, with coherent DMA mappings enabled
[08:01:11] [PASSED] Above the allocation limit, with coherent DMA mappings enabled
[08:01:11] ============== [PASSED] ttm_pool_alloc_basic ===============
[08:01:11] ============== ttm_pool_alloc_basic_dma_addr  ==============
[08:01:11] [PASSED] One page
[08:01:11] [PASSED] More than one page
[08:01:11] [PASSED] Above the allocation limit
[08:01:11] [PASSED] One page, with coherent DMA mappings enabled
[08:01:11] [PASSED] Above the allocation limit, with coherent DMA mappings enabled
[08:01:11] ========== [PASSED] ttm_pool_alloc_basic_dma_addr ==========
[08:01:11] [PASSED] ttm_pool_alloc_order_caching_match
[08:01:11] [PASSED] ttm_pool_alloc_caching_mismatch
[08:01:11] [PASSED] ttm_pool_alloc_order_mismatch
[08:01:11] [PASSED] ttm_pool_free_dma_alloc
[08:01:11] [PASSED] ttm_pool_free_no_dma_alloc
[08:01:11] [PASSED] ttm_pool_fini_basic
[08:01:11] ==================== [PASSED] ttm_pool =====================
[08:01:11] ================ ttm_resource (8 subtests) =================
[08:01:11] ================= ttm_resource_init_basic  =================
[08:01:11] [PASSED] Init resource in TTM_PL_SYSTEM
[08:01:11] [PASSED] Init resource in TTM_PL_VRAM
[08:01:11] [PASSED] Init resource in a private placement
[08:01:11] [PASSED] Init resource in TTM_PL_SYSTEM, set placement flags
[08:01:11] ============= [PASSED] ttm_resource_init_basic =============
[08:01:11] [PASSED] ttm_resource_init_pinned
[08:01:11] [PASSED] ttm_resource_fini_basic
[08:01:11] [PASSED] ttm_resource_manager_init_basic
[08:01:11] [PASSED] ttm_resource_manager_usage_basic
[08:01:11] [PASSED] ttm_resource_manager_set_used_basic
[08:01:11] [PASSED] ttm_sys_man_alloc_basic
[08:01:11] [PASSED] ttm_sys_man_free_basic
[08:01:11] ================== [PASSED] ttm_resource ===================
[08:01:11] =================== ttm_tt (15 subtests) ===================
[08:01:11] ==================== ttm_tt_init_basic  ====================
[08:01:11] [PASSED] Page-aligned size
[08:01:11] [PASSED] Extra pages requested
[08:01:11] ================ [PASSED] ttm_tt_init_basic ================
[08:01:11] [PASSED] ttm_tt_init_misaligned
[08:01:11] [PASSED] ttm_tt_fini_basic
[08:01:11] [PASSED] ttm_tt_fini_sg
[08:01:11] [PASSED] ttm_tt_fini_shmem
[08:01:11] [PASSED] ttm_tt_create_basic
[08:01:11] [PASSED] ttm_tt_create_invalid_bo_type
[08:01:11] [PASSED] ttm_tt_create_ttm_exists
[08:01:11] [PASSED] ttm_tt_create_failed
[08:01:11] [PASSED] ttm_tt_destroy_basic
[08:01:11] [PASSED] ttm_tt_populate_null_ttm
[08:01:11] [PASSED] ttm_tt_populate_populated_ttm
[08:01:11] [PASSED] ttm_tt_unpopulate_basic
[08:01:11] [PASSED] ttm_tt_unpopulate_empty_ttm
[08:01:11] [PASSED] ttm_tt_swapin_basic
[08:01:11] ===================== [PASSED] ttm_tt ======================
[08:01:11] =================== ttm_bo (14 subtests) ===================
[08:01:11] =========== ttm_bo_reserve_optimistic_no_ticket  ===========
[08:01:11] [PASSED] Cannot be interrupted and sleeps
[08:01:11] [PASSED] Cannot be interrupted, locks straight away
[08:01:11] [PASSED] Can be interrupted, sleeps
[08:01:11] ======= [PASSED] ttm_bo_reserve_optimistic_no_ticket =======
[08:01:11] [PASSED] ttm_bo_reserve_locked_no_sleep
[08:01:11] [PASSED] ttm_bo_reserve_no_wait_ticket
[08:01:11] [PASSED] ttm_bo_reserve_double_resv
[08:01:11] [PASSED] ttm_bo_reserve_interrupted
[08:01:11] [PASSED] ttm_bo_reserve_deadlock
[08:01:11] [PASSED] ttm_bo_unreserve_basic
[08:01:11] [PASSED] ttm_bo_unreserve_pinned
[08:01:11] [PASSED] ttm_bo_unreserve_bulk
[08:01:11] [PASSED] ttm_bo_fini_basic
[08:01:11] [PASSED] ttm_bo_fini_shared_resv
[08:01:11] [PASSED] ttm_bo_pin_basic
[08:01:11] [PASSED] ttm_bo_pin_unpin_resource
[08:01:11] [PASSED] ttm_bo_multiple_pin_one_unpin
[08:01:11] ===================== [PASSED] ttm_bo ======================
[08:01:11] ============== ttm_bo_validate (22 subtests) ===============
[08:01:11] ============== ttm_bo_init_reserved_sys_man  ===============
[08:01:11] [PASSED] Buffer object for userspace
[08:01:11] [PASSED] Kernel buffer object
[08:01:11] [PASSED] Shared buffer object
[08:01:11] ========== [PASSED] ttm_bo_init_reserved_sys_man ===========
[08:01:11] ============== ttm_bo_init_reserved_mock_man  ==============
[08:01:11] [PASSED] Buffer object for userspace
[08:01:11] [PASSED] Kernel buffer object
[08:01:11] [PASSED] Shared buffer object
[08:01:11] ========== [PASSED] ttm_bo_init_reserved_mock_man ==========
[08:01:11] [PASSED] ttm_bo_init_reserved_resv
[08:01:11] ================== ttm_bo_validate_basic  ==================
[08:01:11] [PASSED] Buffer object for userspace
[08:01:11] [PASSED] Kernel buffer object
[08:01:11] [PASSED] Shared buffer object
[08:01:11] ============== [PASSED] ttm_bo_validate_basic ==============
[08:01:11] [PASSED] ttm_bo_validate_invalid_placement
[08:01:11] ============= ttm_bo_validate_same_placement  ==============
[08:01:11] [PASSED] System manager
[08:01:11] [PASSED] VRAM manager
[08:01:11] ========= [PASSED] ttm_bo_validate_same_placement ==========
[08:01:11] [PASSED] ttm_bo_validate_failed_alloc
[08:01:11] [PASSED] ttm_bo_validate_pinned
[08:01:11] [PASSED] ttm_bo_validate_busy_placement
[08:01:11] ================ ttm_bo_validate_multihop  =================
[08:01:11] [PASSED] Buffer object for userspace
[08:01:11] [PASSED] Kernel buffer object
[08:01:11] [PASSED] Shared buffer object
[08:01:11] ============ [PASSED] ttm_bo_validate_multihop =============
[08:01:11] ========== ttm_bo_validate_no_placement_signaled  ==========
[08:01:11] [PASSED] Buffer object in system domain, no page vector
[08:01:11] [PASSED] Buffer object in system domain with an existing page vector
[08:01:11] ====== [PASSED] ttm_bo_validate_no_placement_signaled ======
[08:01:11] ======== ttm_bo_validate_no_placement_not_signaled  ========
[08:01:11] [PASSED] Buffer object for userspace
[08:01:11] [PASSED] Kernel buffer object
[08:01:11] [PASSED] Shared buffer object
[08:01:11] ==== [PASSED] ttm_bo_validate_no_placement_not_signaled ====
[08:01:11] [PASSED] ttm_bo_validate_move_fence_signaled
[08:01:11] ========= ttm_bo_validate_move_fence_not_signaled  =========
[08:01:11] [PASSED] Waits for GPU
[08:01:11] [PASSED] Tries to lock straight away
[08:01:11] ===== [PASSED] ttm_bo_validate_move_fence_not_signaled =====
[08:01:11] [PASSED] ttm_bo_validate_swapout
[08:01:11] [PASSED] ttm_bo_validate_happy_evict
[08:01:11] [PASSED] ttm_bo_validate_all_pinned_evict
[08:01:11] [PASSED] ttm_bo_validate_allowed_only_evict
[08:01:11] [PASSED] ttm_bo_validate_deleted_evict
[08:01:11] [PASSED] ttm_bo_validate_busy_domain_evict
[08:01:11] [PASSED] ttm_bo_validate_evict_gutting
[08:01:11] [PASSED] ttm_bo_validate_recrusive_evict
[08:01:11] ================= [PASSED] ttm_bo_validate =================
[08:01:11] ============================================================
[08:01:11] Testing complete. Ran 102 tests: passed: 102
[08:01:11] Elapsed time: 12.069s total, 1.851s configuring, 9.953s building, 0.229s running

+ /kernel/tools/testing/kunit/kunit.py run --kunitconfig /kernel/drivers/dma-buf/.kunitconfig
[08:01:11] Configuring KUnit Kernel ...
Regenerating .config ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
[08:01:13] Building KUnit Kernel ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
Building with:
$ make all compile_commands.json scripts_gdb ARCH=um O=.kunit --jobs=48
[08:01:22] Starting KUnit Kernel (1/1)...
[08:01:22] ============================================================
Running tests with:
$ .kunit/linux kunit.enable=1 mem=1G console=tty kunit_shutdown=halt
[08:01:22] =============== dma-buf-fence (12 subtests) ================
[08:01:22] [PASSED] test_sanitycheck
[08:01:22] [PASSED] test_signaling
[08:01:22] [PASSED] test_add_callback
[08:01:22] [PASSED] test_late_add_callback
[08:01:22] [PASSED] test_rm_callback
[08:01:22] [PASSED] test_late_rm_callback
[08:01:22] [PASSED] test_status
[08:01:22] [PASSED] test_error
[08:01:22] [PASSED] test_wait
[08:01:22] [PASSED] test_wait_timeout
[08:01:22] [PASSED] test_stub
[08:01:22] [SKIPPED] test_race_signal_callback (requires at least 2 CPUs)
[08:01:22] ================== [PASSED] dma-buf-fence ==================
[08:01:22] ============ dma-buf-fence-chain (11 subtests) =============
[08:01:22] [PASSED] test_sanitycheck
[08:01:22] [PASSED] test_find_seqno
[08:01:22] [PASSED] test_find_signaled
[08:01:22] [PASSED] test_find_out_of_order
[08:01:27] [PASSED] test_find_gap
[08:01:27] [PASSED] test_find_race
[08:01:27] [PASSED] test_signal_forward
[08:01:27] [PASSED] test_signal_backward
[08:01:27] [PASSED] test_wait_forward
[08:01:27] [PASSED] test_wait_backward
[08:01:27] [PASSED] test_wait_random
[08:01:27] =============== [PASSED] dma-buf-fence-chain ===============
[08:01:27] ============ dma-buf-fence-unwrap (10 subtests) ============
[08:01:27] [PASSED] test_sanitycheck
[08:01:27] [PASSED] test_unwrap_array
[08:01:27] [PASSED] test_unwrap_chain
[08:01:27] [PASSED] test_unwrap_chain_array
[08:01:27] [PASSED] test_unwrap_merge
[08:01:27] [PASSED] test_unwrap_merge_duplicate
[08:01:27] [PASSED] test_unwrap_merge_seqno
[08:01:27] [PASSED] test_unwrap_merge_order
[08:01:27] [PASSED] test_unwrap_merge_complex
[08:01:27] [PASSED] test_unwrap_merge_complex_seqno
[08:01:27] ============== [PASSED] dma-buf-fence-unwrap ===============
[08:01:27] ================ dma-buf-resv (5 subtests) =================
[08:01:27] [PASSED] test_sanitycheck
[08:01:27] ===================== test_signaling  ======================
[08:01:27] [PASSED] kernel
[08:01:27] [PASSED] write
[08:01:27] [PASSED] read
[08:01:27] [PASSED] bookkeep
[08:01:27] ================= [PASSED] test_signaling ==================
[08:01:27] ====================== test_for_each  ======================
[08:01:27] [PASSED] kernel
[08:01:27] [PASSED] write
[08:01:27] [PASSED] read
[08:01:27] [PASSED] bookkeep
[08:01:27] ================== [PASSED] test_for_each ==================
[08:01:27] ================= test_for_each_unlocked  ==================
[08:01:27] [PASSED] kernel
[08:01:27] [PASSED] write
[08:01:27] [PASSED] read
[08:01:27] [PASSED] bookkeep
[08:01:27] ============= [PASSED] test_for_each_unlocked ==============
[08:01:27] ===================== test_get_fences  =====================
[08:01:27] [PASSED] kernel
[08:01:27] [PASSED] write
[08:01:27] [PASSED] read
[08:01:27] [PASSED] bookkeep
[08:01:27] ================= [PASSED] test_get_fences =================
[08:01:27] ================== [PASSED] dma-buf-resv ===================
[08:01:27] ============================================================
[08:01:27] Testing complete. Ran 50 tests: passed: 49, skipped: 1
[08:01:27] Elapsed time: 15.647s total, 1.797s configuring, 8.529s building, 5.278s running

+ cleanup
++ stat -c %u:%g /kernel
+ chown -R 1003:1003 /kernel

✓ Xe.CI.BAT: success for Enable DP2.1 alpm (rev5)

[Patchwork]

[-- Attachment #1: Type: text/plain, Size: 894 bytes --]

== Series Details ==

Series: Enable DP2.1 alpm (rev5)
URL   : https://patchwork.freedesktop.org/series/156416/
State : success

== Summary ==

CI Bug Log - changes from xe-5642-15e2ba2fb6d25c03d89519aec46f8d5be3e118ad_BAT -> xe-pw-156416v5_BAT
====================================================

Summary
-------

  **SUCCESS**

  No regressions found.

  

Participating hosts (13 -> 13)
------------------------------

  No changes in participating hosts


Changes
-------

  No changes found


Build changes
-------------

  * IGT: IGT_9071 -> IGT_9072
  * Linux: xe-5642-15e2ba2fb6d25c03d89519aec46f8d5be3e118ad -> xe-pw-156416v5

  IGT_9071: 9071
  IGT_9072: 9072
  xe-5642-15e2ba2fb6d25c03d89519aec46f8d5be3e118ad: 15e2ba2fb6d25c03d89519aec46f8d5be3e118ad
  xe-pw-156416v5: 156416v5

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-156416v5/index.html

[-- Attachment #2: Type: text/html, Size: 1456 bytes --]

✓ Xe.CI.FULL: success for Enable DP2.1 alpm (rev5)

[Patchwork]

[-- Attachment #1: Type: text/plain, Size: 31331 bytes --]

== Series Details ==

Series: Enable DP2.1 alpm (rev5)
URL   : https://patchwork.freedesktop.org/series/156416/
State : success

== Summary ==

CI Bug Log - changes from xe-5642-15e2ba2fb6d25c03d89519aec46f8d5be3e118ad_FULL -> xe-pw-156416v5_FULL
====================================================

Summary
-------

  **SUCCESS**

  No regressions found.

  

Participating hosts (2 -> 2)
------------------------------

  No changes in participating hosts

Known issues
------------

  Here are the changes found in xe-pw-156416v5_FULL that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@kms_async_flips@alternate-sync-async-flip-atomic:
    - shard-bmg:          [PASS][1] -> [FAIL][2] ([Intel XE#3718] / [Intel XE#6078])
   [1]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5642-15e2ba2fb6d25c03d89519aec46f8d5be3e118ad/shard-bmg-5/igt@kms_async_flips@alternate-sync-async-flip-atomic.html
   [2]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-156416v5/shard-bmg-3/igt@kms_async_flips@alternate-sync-async-flip-atomic.html
    - shard-lnl:          [PASS][3] -> [FAIL][4] ([Intel XE#3718] / [Intel XE#7265])
   [3]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5642-15e2ba2fb6d25c03d89519aec46f8d5be3e118ad/shard-lnl-5/igt@kms_async_flips@alternate-sync-async-flip-atomic.html
   [4]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-156416v5/shard-lnl-6/igt@kms_async_flips@alternate-sync-async-flip-atomic.html

  * igt@kms_async_flips@alternate-sync-async-flip-atomic@pipe-b-edp-1:
    - shard-lnl:          [PASS][5] -> [FAIL][6] ([Intel XE#7265]) +1 other test fail
   [5]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5642-15e2ba2fb6d25c03d89519aec46f8d5be3e118ad/shard-lnl-5/igt@kms_async_flips@alternate-sync-async-flip-atomic@pipe-b-edp-1.html
   [6]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-156416v5/shard-lnl-6/igt@kms_async_flips@alternate-sync-async-flip-atomic@pipe-b-edp-1.html

  * igt@kms_async_flips@alternate-sync-async-flip-atomic@pipe-b-hdmi-a-3:
    - shard-bmg:          [PASS][7] -> [FAIL][8] ([Intel XE#6078]) +3 other tests fail
   [7]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5642-15e2ba2fb6d25c03d89519aec46f8d5be3e118ad/shard-bmg-5/igt@kms_async_flips@alternate-sync-async-flip-atomic@pipe-b-hdmi-a-3.html
   [8]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-156416v5/shard-bmg-3/igt@kms_async_flips@alternate-sync-async-flip-atomic@pipe-b-hdmi-a-3.html

  * igt@kms_big_fb@4-tiled-32bpp-rotate-90:
    - shard-bmg:          NOTRUN -> [SKIP][9] ([Intel XE#2327]) +1 other test skip
   [9]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-156416v5/shard-bmg-2/igt@kms_big_fb@4-tiled-32bpp-rotate-90.html

  * igt@kms_big_fb@y-tiled-16bpp-rotate-180:
    - shard-bmg:          NOTRUN -> [SKIP][10] ([Intel XE#1124]) +2 other tests skip
   [10]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-156416v5/shard-bmg-7/igt@kms_big_fb@y-tiled-16bpp-rotate-180.html

  * igt@kms_big_fb@yf-tiled-addfb-size-overflow:
    - shard-bmg:          NOTRUN -> [SKIP][11] ([Intel XE#610] / [Intel XE#7387])
   [11]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-156416v5/shard-bmg-9/igt@kms_big_fb@yf-tiled-addfb-size-overflow.html

  * igt@kms_bw@linear-tiling-2-displays-target-1920x1080p:
    - shard-bmg:          NOTRUN -> [SKIP][12] ([Intel XE#367]) +1 other test skip
   [12]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-156416v5/shard-bmg-5/igt@kms_bw@linear-tiling-2-displays-target-1920x1080p.html

  * igt@kms_ccs@bad-pixel-format-4-tiled-mtl-rc-ccs-cc:
    - shard-bmg:          NOTRUN -> [SKIP][13] ([Intel XE#2887]) +10 other tests skip
   [13]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-156416v5/shard-bmg-6/igt@kms_ccs@bad-pixel-format-4-tiled-mtl-rc-ccs-cc.html

  * igt@kms_ccs@crc-primary-suspend-4-tiled-bmg-ccs@pipe-c-hdmi-a-3:
    - shard-bmg:          [PASS][14] -> [INCOMPLETE][15] ([Intel XE#7084] / [Intel XE#8150])
   [14]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5642-15e2ba2fb6d25c03d89519aec46f8d5be3e118ad/shard-bmg-9/igt@kms_ccs@crc-primary-suspend-4-tiled-bmg-ccs@pipe-c-hdmi-a-3.html
   [15]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-156416v5/shard-bmg-6/igt@kms_ccs@crc-primary-suspend-4-tiled-bmg-ccs@pipe-c-hdmi-a-3.html

  * igt@kms_ccs@crc-primary-suspend-4-tiled-lnl-ccs@pipe-a-dp-2:
    - shard-bmg:          NOTRUN -> [SKIP][16] ([Intel XE#2652]) +8 other tests skip
   [16]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-156416v5/shard-bmg-9/igt@kms_ccs@crc-primary-suspend-4-tiled-lnl-ccs@pipe-a-dp-2.html

  * igt@kms_cdclk@plane-scaling:
    - shard-bmg:          NOTRUN -> [SKIP][17] ([Intel XE#2724] / [Intel XE#7449])
   [17]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-156416v5/shard-bmg-6/igt@kms_cdclk@plane-scaling.html

  * igt@kms_chamelium_color@ctm-red-to-blue:
    - shard-bmg:          NOTRUN -> [SKIP][18] ([Intel XE#2325] / [Intel XE#7358]) +2 other tests skip
   [18]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-156416v5/shard-bmg-6/igt@kms_chamelium_color@ctm-red-to-blue.html

  * igt@kms_chamelium_hpd@hdmi-hpd-storm-disable:
    - shard-bmg:          NOTRUN -> [SKIP][19] ([Intel XE#2252]) +3 other tests skip
   [19]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-156416v5/shard-bmg-2/igt@kms_chamelium_hpd@hdmi-hpd-storm-disable.html

  * igt@kms_content_protection@dp-mst-lic-type-0-hdcp14:
    - shard-bmg:          NOTRUN -> [SKIP][20] ([Intel XE#6974])
   [20]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-156416v5/shard-bmg-4/igt@kms_content_protection@dp-mst-lic-type-0-hdcp14.html

  * igt@kms_content_protection@lic-type-0@pipe-a-dp-2:
    - shard-bmg:          NOTRUN -> [FAIL][21] ([Intel XE#1178] / [Intel XE#3304] / [Intel XE#7374]) +1 other test fail
   [21]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-156416v5/shard-bmg-6/igt@kms_content_protection@lic-type-0@pipe-a-dp-2.html

  * igt@kms_cursor_crc@cursor-offscreen-max-size:
    - shard-bmg:          NOTRUN -> [SKIP][22] ([Intel XE#2320]) +5 other tests skip
   [22]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-156416v5/shard-bmg-1/igt@kms_cursor_crc@cursor-offscreen-max-size.html

  * igt@kms_cursor_crc@cursor-random-512x170:
    - shard-bmg:          NOTRUN -> [SKIP][23] ([Intel XE#2321] / [Intel XE#7355]) +1 other test skip
   [23]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-156416v5/shard-bmg-7/igt@kms_cursor_crc@cursor-random-512x170.html

  * igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions:
    - shard-bmg:          [PASS][24] -> [FAIL][25] ([Intel XE#7809])
   [24]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5642-15e2ba2fb6d25c03d89519aec46f8d5be3e118ad/shard-bmg-7/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions.html
   [25]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-156416v5/shard-bmg-4/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions.html

  * igt@kms_dsc@dsc-fractional-bpp-with-bpc:
    - shard-bmg:          NOTRUN -> [SKIP][26] ([Intel XE#8265]) +1 other test skip
   [26]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-156416v5/shard-bmg-6/igt@kms_dsc@dsc-fractional-bpp-with-bpc.html

  * igt@kms_fbcon_fbt@fbc:
    - shard-bmg:          NOTRUN -> [SKIP][27] ([Intel XE#4156] / [Intel XE#7425])
   [27]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-156416v5/shard-bmg-3/igt@kms_fbcon_fbt@fbc.html

  * igt@kms_feature_discovery@display-4x:
    - shard-bmg:          NOTRUN -> [SKIP][28] ([Intel XE#1138] / [Intel XE#7344])
   [28]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-156416v5/shard-bmg-5/igt@kms_feature_discovery@display-4x.html

  * igt@kms_flip@flip-vs-expired-vblank@b-edp1:
    - shard-lnl:          [PASS][29] -> [FAIL][30] ([Intel XE#301])
   [29]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5642-15e2ba2fb6d25c03d89519aec46f8d5be3e118ad/shard-lnl-6/igt@kms_flip@flip-vs-expired-vblank@b-edp1.html
   [30]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-156416v5/shard-lnl-6/igt@kms_flip@flip-vs-expired-vblank@b-edp1.html

  * igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-32bpp-ytilegen12rcccs-upscaling:
    - shard-bmg:          NOTRUN -> [SKIP][31] ([Intel XE#7178] / [Intel XE#7351])
   [31]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-156416v5/shard-bmg-9/igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-32bpp-ytilegen12rcccs-upscaling.html

  * igt@kms_flip_scaled_crc@flip-64bpp-4tile-to-32bpp-4tiledg2rcccs-upscaling:
    - shard-bmg:          NOTRUN -> [SKIP][32] ([Intel XE#7178] / [Intel XE#7349]) +1 other test skip
   [32]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-156416v5/shard-bmg-8/igt@kms_flip_scaled_crc@flip-64bpp-4tile-to-32bpp-4tiledg2rcccs-upscaling.html

  * igt@kms_frontbuffer_tracking@drrs-rgb565-draw-render:
    - shard-bmg:          NOTRUN -> [SKIP][33] ([Intel XE#2311]) +37 other tests skip
   [33]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-156416v5/shard-bmg-2/igt@kms_frontbuffer_tracking@drrs-rgb565-draw-render.html

  * igt@kms_frontbuffer_tracking@fbc-1p-offscreen-pri-indfb-draw-render:
    - shard-bmg:          NOTRUN -> [SKIP][34] ([Intel XE#4141]) +12 other tests skip
   [34]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-156416v5/shard-bmg-8/igt@kms_frontbuffer_tracking@fbc-1p-offscreen-pri-indfb-draw-render.html

  * igt@kms_frontbuffer_tracking@fbcpsr-abgr161616f-draw-blt:
    - shard-bmg:          NOTRUN -> [SKIP][35] ([Intel XE#7061] / [Intel XE#7356]) +2 other tests skip
   [35]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-156416v5/shard-bmg-9/igt@kms_frontbuffer_tracking@fbcpsr-abgr161616f-draw-blt.html

  * igt@kms_frontbuffer_tracking@fbcpsrhdr-1p-primscrn-cur-indfb-move:
    - shard-bmg:          NOTRUN -> [SKIP][36] ([Intel XE#2313]) +34 other tests skip
   [36]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-156416v5/shard-bmg-1/igt@kms_frontbuffer_tracking@fbcpsrhdr-1p-primscrn-cur-indfb-move.html

  * igt@kms_frontbuffer_tracking@psrhdr-argb161616f-draw-render:
    - shard-bmg:          NOTRUN -> [SKIP][37] ([Intel XE#7061]) +3 other tests skip
   [37]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-156416v5/shard-bmg-8/igt@kms_frontbuffer_tracking@psrhdr-argb161616f-draw-render.html

  * igt@kms_joiner@basic-big-joiner:
    - shard-bmg:          NOTRUN -> [SKIP][38] ([Intel XE#6901])
   [38]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-156416v5/shard-bmg-1/igt@kms_joiner@basic-big-joiner.html

  * igt@kms_joiner@basic-ultra-joiner:
    - shard-bmg:          NOTRUN -> [SKIP][39] ([Intel XE#6911] / [Intel XE#7378])
   [39]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-156416v5/shard-bmg-2/igt@kms_joiner@basic-ultra-joiner.html

  * igt@kms_pipe_stress@stress-xrgb8888-yftiled:
    - shard-bmg:          NOTRUN -> [SKIP][40] ([Intel XE#6912] / [Intel XE#7375])
   [40]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-156416v5/shard-bmg-6/igt@kms_pipe_stress@stress-xrgb8888-yftiled.html

  * igt@kms_plane@pixel-format-4-tiled-modifier@pipe-a-plane-5:
    - shard-bmg:          NOTRUN -> [SKIP][41] ([Intel XE#8303]) +1 other test skip
   [41]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-156416v5/shard-bmg-9/igt@kms_plane@pixel-format-4-tiled-modifier@pipe-a-plane-5.html

  * igt@kms_plane@pixel-format-y-tiled-modifier:
    - shard-bmg:          NOTRUN -> [SKIP][42] ([Intel XE#7283]) +1 other test skip
   [42]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-156416v5/shard-bmg-8/igt@kms_plane@pixel-format-y-tiled-modifier.html

  * igt@kms_plane_lowres@tiling-yf:
    - shard-bmg:          NOTRUN -> [SKIP][43] ([Intel XE#2393])
   [43]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-156416v5/shard-bmg-2/igt@kms_plane_lowres@tiling-yf.html

  * igt@kms_plane_multiple@tiling-y:
    - shard-bmg:          NOTRUN -> [SKIP][44] ([Intel XE#5020] / [Intel XE#7348])
   [44]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-156416v5/shard-bmg-3/igt@kms_plane_multiple@tiling-y.html

  * igt@kms_plane_scaling@planes-upscale-factor-0-25-downscale-factor-0-75:
    - shard-bmg:          NOTRUN -> [SKIP][45] ([Intel XE#2763] / [Intel XE#6886]) +4 other tests skip
   [45]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-156416v5/shard-bmg-7/igt@kms_plane_scaling@planes-upscale-factor-0-25-downscale-factor-0-75.html

  * igt@kms_pm_backlight@fade-with-dpms:
    - shard-bmg:          NOTRUN -> [SKIP][46] ([Intel XE#7376] / [Intel XE#7760] / [Intel XE#870])
   [46]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-156416v5/shard-bmg-1/igt@kms_pm_backlight@fade-with-dpms.html

  * igt@kms_pm_dc@dc3co-after-dc6@pr-xrgb8888:
    - shard-bmg:          NOTRUN -> [SKIP][47] ([Intel XE#8395] / [Intel XE#8396]) +1 other test skip
   [47]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-156416v5/shard-bmg-5/igt@kms_pm_dc@dc3co-after-dc6@pr-xrgb8888.html

  * igt@kms_pm_dc@dc3co-after-dc6@psr2-yuv420:
    - shard-bmg:          NOTRUN -> [SKIP][48] ([Intel XE#8396]) +1 other test skip
   [48]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-156416v5/shard-bmg-5/igt@kms_pm_dc@dc3co-after-dc6@psr2-yuv420.html

  * igt@kms_pm_dc@dc5-dpms:
    - shard-lnl:          [PASS][49] -> [FAIL][50] ([Intel XE#8399])
   [49]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5642-15e2ba2fb6d25c03d89519aec46f8d5be3e118ad/shard-lnl-5/igt@kms_pm_dc@dc5-dpms.html
   [50]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-156416v5/shard-lnl-8/igt@kms_pm_dc@dc5-dpms.html

  * igt@kms_psr2_sf@fbc-pr-cursor-plane-move-continuous-sf:
    - shard-bmg:          NOTRUN -> [SKIP][51] ([Intel XE#1489]) +7 other tests skip
   [51]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-156416v5/shard-bmg-2/igt@kms_psr2_sf@fbc-pr-cursor-plane-move-continuous-sf.html

  * igt@kms_psr@pr-sprite-plane-onoff:
    - shard-bmg:          NOTRUN -> [SKIP][52] ([Intel XE#2234] / [Intel XE#2850]) +9 other tests skip
   [52]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-156416v5/shard-bmg-10/igt@kms_psr@pr-sprite-plane-onoff.html

  * igt@kms_psr_stress_test@invalidate-primary-flip-overlay:
    - shard-bmg:          NOTRUN -> [SKIP][53] ([Intel XE#7795])
   [53]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-156416v5/shard-bmg-8/igt@kms_psr_stress_test@invalidate-primary-flip-overlay.html

  * igt@kms_sharpness_filter@filter-scaler-downscale:
    - shard-bmg:          NOTRUN -> [SKIP][54] ([Intel XE#6503]) +1 other test skip
   [54]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-156416v5/shard-bmg-10/igt@kms_sharpness_filter@filter-scaler-downscale.html

  * igt@kms_vrr@flip-suspend:
    - shard-bmg:          NOTRUN -> [SKIP][55] ([Intel XE#1499]) +1 other test skip
   [55]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-156416v5/shard-bmg-3/igt@kms_vrr@flip-suspend.html

  * igt@xe_evict@evict-small-multi-queue-cm:
    - shard-bmg:          NOTRUN -> [SKIP][56] ([Intel XE#8370])
   [56]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-156416v5/shard-bmg-9/igt@xe_evict@evict-small-multi-queue-cm.html

  * igt@xe_exec_basic@multigpu-once-null-rebind:
    - shard-bmg:          NOTRUN -> [SKIP][57] ([Intel XE#2322] / [Intel XE#7372]) +2 other tests skip
   [57]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-156416v5/shard-bmg-5/igt@xe_exec_basic@multigpu-once-null-rebind.html

  * igt@xe_exec_fault_mode@twice-multi-queue:
    - shard-bmg:          NOTRUN -> [SKIP][58] ([Intel XE#8374]) +8 other tests skip
   [58]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-156416v5/shard-bmg-10/igt@xe_exec_fault_mode@twice-multi-queue.html

  * igt@xe_exec_multi_queue@few-execs-preempt-mode-fault-basic:
    - shard-bmg:          NOTRUN -> [SKIP][59] ([Intel XE#8364]) +16 other tests skip
   [59]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-156416v5/shard-bmg-7/igt@xe_exec_multi_queue@few-execs-preempt-mode-fault-basic.html

  * igt@xe_exec_reset@multi-queue-cat-error:
    - shard-bmg:          NOTRUN -> [SKIP][60] ([Intel XE#8369])
   [60]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-156416v5/shard-bmg-5/igt@xe_exec_reset@multi-queue-cat-error.html

  * igt@xe_exec_threads@threads-multi-queue-cm-fd-userptr:
    - shard-bmg:          NOTRUN -> [SKIP][61] ([Intel XE#8378]) +4 other tests skip
   [61]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-156416v5/shard-bmg-5/igt@xe_exec_threads@threads-multi-queue-cm-fd-userptr.html

  * igt@xe_fault_injection@inject-fault-probe-function-xe_pm_init_early:
    - shard-bmg:          [PASS][62] -> [ABORT][63] ([Intel XE#8007])
   [62]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5642-15e2ba2fb6d25c03d89519aec46f8d5be3e118ad/shard-bmg-10/igt@xe_fault_injection@inject-fault-probe-function-xe_pm_init_early.html
   [63]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-156416v5/shard-bmg-4/igt@xe_fault_injection@inject-fault-probe-function-xe_pm_init_early.html

  * igt@xe_live_ktest@xe_bo@xe_ccs_migrate_kunit:
    - shard-bmg:          NOTRUN -> [SKIP][64] ([Intel XE#2229])
   [64]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-156416v5/shard-bmg-7/igt@xe_live_ktest@xe_bo@xe_ccs_migrate_kunit.html

  * igt@xe_live_ktest@xe_eudebug:
    - shard-bmg:          NOTRUN -> [SKIP][65] ([Intel XE#2833])
   [65]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-156416v5/shard-bmg-4/igt@xe_live_ktest@xe_eudebug.html

  * igt@xe_multigpu_svm@mgpu-coherency-prefetch:
    - shard-bmg:          NOTRUN -> [SKIP][66] ([Intel XE#6964])
   [66]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-156416v5/shard-bmg-9/igt@xe_multigpu_svm@mgpu-coherency-prefetch.html

  * igt@xe_page_reclaim@binds-null-vma:
    - shard-bmg:          NOTRUN -> [SKIP][67] ([Intel XE#7793]) +2 other tests skip
   [67]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-156416v5/shard-bmg-2/igt@xe_page_reclaim@binds-null-vma.html

  * igt@xe_pat@pat-index-xelp:
    - shard-bmg:          NOTRUN -> [SKIP][68] ([Intel XE#2245] / [Intel XE#7590])
   [68]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-156416v5/shard-bmg-3/igt@xe_pat@pat-index-xelp.html

  * igt@xe_pat@xa-app-transient-media-off:
    - shard-bmg:          NOTRUN -> [SKIP][69] ([Intel XE#7590]) +1 other test skip
   [69]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-156416v5/shard-bmg-3/igt@xe_pat@xa-app-transient-media-off.html

  * igt@xe_peer2peer@read:
    - shard-bmg:          NOTRUN -> [SKIP][70] ([Intel XE#2427] / [Intel XE#6953] / [Intel XE#7326] / [Intel XE#7353])
   [70]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-156416v5/shard-bmg-4/igt@xe_peer2peer@read.html

  * igt@xe_pm@d3cold-mocs:
    - shard-bmg:          NOTRUN -> [SKIP][71] ([Intel XE#2284] / [Intel XE#7370]) +1 other test skip
   [71]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-156416v5/shard-bmg-5/igt@xe_pm@d3cold-mocs.html

  * igt@xe_pxp@pxp-stale-queue-post-suspend:
    - shard-bmg:          NOTRUN -> [SKIP][72] ([Intel XE#4733] / [Intel XE#7417]) +2 other tests skip
   [72]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-156416v5/shard-bmg-5/igt@xe_pxp@pxp-stale-queue-post-suspend.html

  * igt@xe_query@multigpu-query-invalid-extension:
    - shard-bmg:          NOTRUN -> [SKIP][73] ([Intel XE#944]) +3 other tests skip
   [73]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-156416v5/shard-bmg-10/igt@xe_query@multigpu-query-invalid-extension.html

  
#### Possible fixes ####

  * igt@core_hotunplug@hotrebind-with-load:
    - shard-bmg:          [ABORT][74] ([Intel XE#8007]) -> [PASS][75] +1 other test pass
   [74]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5642-15e2ba2fb6d25c03d89519aec46f8d5be3e118ad/shard-bmg-1/igt@core_hotunplug@hotrebind-with-load.html
   [75]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-156416v5/shard-bmg-5/igt@core_hotunplug@hotrebind-with-load.html

  * igt@kms_flip@flip-vs-expired-vblank-interruptible@b-edp1:
    - shard-lnl:          [FAIL][76] ([Intel XE#301]) -> [PASS][77]
   [76]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5642-15e2ba2fb6d25c03d89519aec46f8d5be3e118ad/shard-lnl-3/igt@kms_flip@flip-vs-expired-vblank-interruptible@b-edp1.html
   [77]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-156416v5/shard-lnl-3/igt@kms_flip@flip-vs-expired-vblank-interruptible@b-edp1.html

  * igt@kms_flip@flip-vs-expired-vblank@c-edp1:
    - shard-lnl:          [FAIL][78] ([Intel XE#301] / [Intel XE#3149]) -> [PASS][79] +2 other tests pass
   [78]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5642-15e2ba2fb6d25c03d89519aec46f8d5be3e118ad/shard-lnl-6/igt@kms_flip@flip-vs-expired-vblank@c-edp1.html
   [79]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-156416v5/shard-lnl-6/igt@kms_flip@flip-vs-expired-vblank@c-edp1.html

  * igt@kms_flip@modeset-vs-vblank-race-interruptible:
    - shard-bmg:          [FAIL][80] ([Intel XE#3098]) -> [PASS][81] +1 other test pass
   [80]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5642-15e2ba2fb6d25c03d89519aec46f8d5be3e118ad/shard-bmg-2/igt@kms_flip@modeset-vs-vblank-race-interruptible.html
   [81]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-156416v5/shard-bmg-3/igt@kms_flip@modeset-vs-vblank-race-interruptible.html

  * igt@kms_hdmi_inject@inject-audio:
    - shard-bmg:          [SKIP][82] ([Intel XE#7308]) -> [PASS][83]
   [82]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5642-15e2ba2fb6d25c03d89519aec46f8d5be3e118ad/shard-bmg-10/igt@kms_hdmi_inject@inject-audio.html
   [83]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-156416v5/shard-bmg-7/igt@kms_hdmi_inject@inject-audio.html

  * igt@xe_evict@evict-mixed-many-threads-small:
    - shard-bmg:          [INCOMPLETE][84] ([Intel XE#6321] / [Intel XE#8355]) -> [PASS][85]
   [84]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5642-15e2ba2fb6d25c03d89519aec46f8d5be3e118ad/shard-bmg-7/igt@xe_evict@evict-mixed-many-threads-small.html
   [85]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-156416v5/shard-bmg-1/igt@xe_evict@evict-mixed-many-threads-small.html

  * igt@xe_sriov_flr@flr-vfs-parallel:
    - shard-bmg:          [FAIL][86] ([Intel XE#6569]) -> [PASS][87] +1 other test pass
   [86]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5642-15e2ba2fb6d25c03d89519aec46f8d5be3e118ad/shard-bmg-5/igt@xe_sriov_flr@flr-vfs-parallel.html
   [87]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-156416v5/shard-bmg-6/igt@xe_sriov_flr@flr-vfs-parallel.html

  
#### Warnings ####

  * igt@kms_flip@flip-vs-expired-vblank:
    - shard-lnl:          [FAIL][88] ([Intel XE#301] / [Intel XE#3149]) -> [FAIL][89] ([Intel XE#301])
   [88]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5642-15e2ba2fb6d25c03d89519aec46f8d5be3e118ad/shard-lnl-6/igt@kms_flip@flip-vs-expired-vblank.html
   [89]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-156416v5/shard-lnl-6/igt@kms_flip@flip-vs-expired-vblank.html

  * igt@kms_tiled_display@basic-test-pattern:
    - shard-bmg:          [FAIL][90] ([Intel XE#1729] / [Intel XE#7424]) -> [SKIP][91] ([Intel XE#2426] / [Intel XE#5848])
   [90]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5642-15e2ba2fb6d25c03d89519aec46f8d5be3e118ad/shard-bmg-3/igt@kms_tiled_display@basic-test-pattern.html
   [91]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-156416v5/shard-bmg-8/igt@kms_tiled_display@basic-test-pattern.html

  * igt@kms_tiled_display@basic-test-pattern-with-chamelium:
    - shard-bmg:          [SKIP][92] ([Intel XE#2509] / [Intel XE#7437]) -> [SKIP][93] ([Intel XE#2426] / [Intel XE#5848])
   [92]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5642-15e2ba2fb6d25c03d89519aec46f8d5be3e118ad/shard-bmg-10/igt@kms_tiled_display@basic-test-pattern-with-chamelium.html
   [93]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-156416v5/shard-bmg-2/igt@kms_tiled_display@basic-test-pattern-with-chamelium.html

  
  [Intel XE#1124]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1124
  [Intel XE#1138]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1138
  [Intel XE#1178]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1178
  [Intel XE#1489]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1489
  [Intel XE#1499]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1499
  [Intel XE#1729]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1729
  [Intel XE#2229]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2229
  [Intel XE#2234]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2234
  [Intel XE#2245]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2245
  [Intel XE#2252]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2252
  [Intel XE#2284]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2284
  [Intel XE#2311]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2311
  [Intel XE#2313]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2313
  [Intel XE#2320]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2320
  [Intel XE#2321]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2321
  [Intel XE#2322]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2322
  [Intel XE#2325]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2325
  [Intel XE#2327]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2327
  [Intel XE#2393]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2393
  [Intel XE#2426]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2426
  [Intel XE#2427]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2427
  [Intel XE#2509]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2509
  [Intel XE#2652]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2652
  [Intel XE#2724]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2724
  [Intel XE#2763]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2763
  [Intel XE#2833]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2833
  [Intel XE#2850]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2850
  [Intel XE#2887]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2887
  [Intel XE#301]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/301
  [Intel XE#3098]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3098
  [Intel XE#3149]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3149
  [Intel XE#3304]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3304
  [Intel XE#367]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/367
  [Intel XE#3718]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3718
  [Intel XE#4141]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4141
  [Intel XE#4156]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4156
  [Intel XE#4733]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4733
  [Intel XE#5020]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5020
  [Intel XE#5848]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5848
  [Intel XE#6078]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6078
  [Intel XE#610]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/610
  [Intel XE#6321]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6321
  [Intel XE#6503]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6503
  [Intel XE#6569]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6569
  [Intel XE#6886]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6886
  [Intel XE#6901]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6901
  [Intel XE#6911]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6911
  [Intel XE#6912]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6912
  [Intel XE#6953]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6953
  [Intel XE#6964]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6964
  [Intel XE#6974]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6974
  [Intel XE#7061]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7061
  [Intel XE#7084]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7084
  [Intel XE#7178]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7178
  [Intel XE#7265]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7265
  [Intel XE#7283]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7283
  [Intel XE#7308]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7308
  [Intel XE#7326]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7326
  [Intel XE#7344]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7344
  [Intel XE#7348]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7348
  [Intel XE#7349]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7349
  [Intel XE#7351]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7351
  [Intel XE#7353]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7353
  [Intel XE#7355]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7355
  [Intel XE#7356]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7356
  [Intel XE#7358]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7358
  [Intel XE#7370]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7370
  [Intel XE#7372]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7372
  [Intel XE#7374]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7374
  [Intel XE#7375]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7375
  [Intel XE#7376]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7376
  [Intel XE#7378]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7378
  [Intel XE#7387]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7387
  [Intel XE#7417]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7417
  [Intel XE#7424]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7424
  [Intel XE#7425]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7425
  [Intel XE#7437]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7437
  [Intel XE#7449]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7449
  [Intel XE#7590]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7590
  [Intel XE#7760]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7760
  [Intel XE#7793]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7793
  [Intel XE#7795]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7795
  [Intel XE#7809]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7809
  [Intel XE#8007]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/8007
  [Intel XE#8150]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/8150
  [Intel XE#8265]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/8265
  [Intel XE#8303]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/8303
  [Intel XE#8355]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/8355
  [Intel XE#8364]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/8364
  [Intel XE#8369]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/8369
  [Intel XE#8370]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/8370
  [Intel XE#8374]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/8374
  [Intel XE#8378]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/8378
  [Intel XE#8395]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/8395
  [Intel XE#8396]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/8396
  [Intel XE#8399]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/8399
  [Intel XE#870]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/870
  [Intel XE#944]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/944


Build changes
-------------

  * IGT: IGT_9071 -> IGT_9072
  * Linux: xe-5642-15e2ba2fb6d25c03d89519aec46f8d5be3e118ad -> xe-pw-156416v5

  IGT_9071: 9071
  IGT_9072: 9072
  xe-5642-15e2ba2fb6d25c03d89519aec46f8d5be3e118ad: 15e2ba2fb6d25c03d89519aec46f8d5be3e118ad
  xe-pw-156416v5: 156416v5

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-156416v5/index.html

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