Re: [PATCH v2 03/11] drm/xe/cper: Add CPER structures and trace event

Re: [PATCH v2 03/11] drm/xe/cper: Add CPER structures and trace event

[sashiko-bot]

Thank you for your contribution! Sashiko AI review found 2 potential issue(s) to consider:
- [Medium] CPER structures use native integer types and C bitfields for a standardized external binary format, causing ABI corruption on non-little-endian architectures.
- [Medium] Tracepoint uses `%pU` to print `guid_t` fields, incorrectly formatting them as big-endian.
--

commit ad510a6c4b7008ac7d33a168936259e5f8400da7
Author: Badal Nilawar <badal.nilawar@intel.com>

drm/xe/cper: Add CPER structures and trace event

Define packed data structures and Intel-specific GUID macros needed
to build Intel GPU CPER (Common Platform Error Record) non-standard
records.

> diff --git a/drivers/gpu/drm/xe/xe_cper_types.h b/drivers/gpu/drm/xe/xe_cper_types.h
> new file mode 100644
> index 0000000000000..82167ea4eb161
> --- /dev/null
> +++ b/drivers/gpu/drm/xe/xe_cper_types.h
[ ... ]
> +struct xe_cper_sec_intel_err_hdr {
> +	/** @error_class: Error classification (type, component, location, cause) */
> +	union {
> +		struct {
> +			/** @error_class.error_type: RAS error severity */
> +			u8  error_type;
> +			/** @error_class.error_component: IP block that raised the error */
> +			u8  error_component;
> +			/** @error_class.tile: Tile number */
> +			u8  tile;
> +			/** @error_class.instance: Instance within the tile */
> +			u32 instance;
> +			/** @error_class.cause: Error cause code */
> +			u32 cause;
> +			/** @error_class.reserved: Reserved, must be zero */
> +			u8  reserved;
> +		} error_class;
> +		/** @class: Raw byte view of the error class */
> +		u8 class[12];
> +	};
> +	/** @first_timestamp: Timestamp of the first occurrence of this error class */
> +	u64 first_timestamp;

[Severity: Medium]
Can this native u64 type break the CPER binary layout on big-endian 
architectures?

The CPER standard dictates a strict binary layout and requires multi-byte fields
to be little-endian. Using architecture-dependent native integer types like u64
causes the struct's binary representation to vary based on host endianness,
which can produce corrupted CPER records on big-endian architectures.

Should this use explicitly sized and endian-specific types like __le64?

> +	/** @sig_id: Aggregated error class SIG ID; set to U32_MAX if unknown */
> +	u32 sig_id;
> +	/** @error_count: Number of times this error has been observed */
> +	u32 error_count;
> +	/** @valid_bits: Bitmask indicating which header fields are populated */
> +	union {
> +		struct {
> +			/** @valid_bits.location: @error_class field is valid */
> +			u16 location		: 1;

[Severity: Medium]
Will this compiler-dependent bitfield cause ABI corruption?

Since bitfield layout is compiler- and architecture-dependent, it breaks the
exact bit-level binary layout required for the CPER standard. 

Should this be handled with standard bitwise operations instead?

[ ... ]
> diff --git a/drivers/gpu/drm/xe/xe_trace_cper.h b/drivers/gpu/drm/xe/xe_trace_cper.h
> new file mode 100644
> index 0000000000000..6d2dbf5048884
> --- /dev/null
> +++ b/drivers/gpu/drm/xe/xe_trace_cper.h
[ ... ]
> +	TP_printk("dev=%s severity=%d platform_id=%pU fru_id=%pU "

[Severity: Medium]
Does this tracepoint format guid_t fields incorrectly?

The printk format specifier %pU defaults to %pUb, which formats UUIDs in
big-endian byte order (RFC 4122). However, guid_t represents little-endian
UUIDs.

Using %pU instead of %pUl causes the first three components of the GUID to be
incorrectly byte-swapped in the trace output, presenting a corrupted GUID to
userspace consumers.

> +		"intel_err_hdr_raw=%s cper_len=%u cper_raw=%s",
> +		__get_str(dev), __entry->sev,
> +		__entry->platform_id, __entry->fru_id,
> +		__print_hex(__entry->ihdr_raw,
> +		    sizeof(struct xe_cper_sec_intel_err_hdr)),
> +		__entry->cper_len,
> +		__print_hex(__get_dynamic_array(cper),
> +		    __entry->cper_len))
> +);

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20260825175916.1103841-13-badal.nilawar@intel.com?part=3

Re: [PATCH v2 01/11] drm/xe/xe_ras: Add support to retrieve info queue data for CRI

[sashiko-bot]

Thank you for your contribution! Sashiko AI review found 2 potential issue(s) to consider:
- [Medium] Unportable use of C bitfields inside a packed structure for a firmware message interface.
- [Low] The patch introduces a static function `get_info_queue_data` without any callers, causing a `-Wunused-function` compiler warning that breaks the build.
--

commit 82a6804e91047f9e3f922cd878001d1bc3e9d8ed
Author: Badal Nilawar <badal.nilawar@intel.com>

drm/xe/xe_ras: Add support to retrieve info queue data for CRI

This commit adds support to retrieve info queue data. It introduces
various structures for the info queue data request and response, and adds
a function to send the command to the system controller.

> diff --git a/drivers/gpu/drm/xe/xe_ras.c b/drivers/gpu/drm/xe/xe_ras.c
> index d25d25f775310..6830872354825 100644
> --- a/drivers/gpu/drm/xe/xe_ras.c
> +++ b/drivers/gpu/drm/xe/xe_ras.c
[ ... ]
> @@ -661,6 +661,40 @@ int xe_ras_clear_counter(struct xe_device *xe, u8 severity, u8 component)
>  	return 0;
>  }
>  
> +static int get_info_queue_data(struct xe_device *xe,
> +			       const struct xe_ras_get_info_queue_data_request *req,
> +			       struct xe_ras_get_info_queue_data_response *out)

[Severity: Low]
Does this function have any callers in this patch?

Adding a static function without using it in the same patch will cause a
-Wunused-function compiler warning, which breaks the build when compiling
with -Werror. To maintain git bisect functionality, every intermediate patch
should compile independently.

Could get_info_queue_data() be introduced in the patch that first uses it,
or temporarily marked with __maybe_unused?

> +{
> +	struct xe_ras_get_info_queue_data_response response = {0};
> +	struct xe_sysctrl_mailbox_command command = {0};
> +	size_t rlen;
> +	int ret;
[ ... ]
> diff --git a/drivers/gpu/drm/xe/xe_ras_types.h b/drivers/gpu/drm/xe/xe_ras_types.h
> index 99b2466e2062c..d87db9f5174a2 100644
> --- a/drivers/gpu/drm/xe/xe_ras_types.h
> +++ b/drivers/gpu/drm/xe/xe_ras_types.h
[ ... ]
> @@ -95,6 +99,109 @@ struct xe_ras_threshold_crossed {
>  	struct xe_ras_error_class counters[XE_RAS_NUM_COUNTERS];
>  } __packed;
>  
> +/**
> + * struct xe_ras_info_queue_header - Metadata for large info queue data transfers
> + *
> + * Provides chunk metadata for commands that support extended info queue
> + * functionality. Used when the total data exceeds a single mailbox response.
> + */
> +struct xe_ras_info_queue_header {
> +	/** @total_size: Total size of the complete info queue data in bytes */
> +	u32 total_size;
> +	/** @chunk_offset: Offset of this chunk within the total data in bytes */
> +	u32 chunk_offset;
> +	/** @chunk_size: Size of the data in this chunk in bytes */
> +	u32 chunk_size;
> +	/** @sequence_number: Sequence number for this chunk, starts at 0 */
> +	u32 sequence_number;
> +	/** @flags: Info queue control flags (RAS_INFO_QUEUE_FLAG_*) */
> +	u32 flags:8;
> +	/** @compression_type: Compression algorithm used; 0 = none */
> +	u32 compression_type:4;
> +	/** @num_headers: Number of detailed counter headers at start of queue_data */
> +	u32 num_headers:5;
> +	/** @reserved: Reserved for future use */
> +	u32 reserved:15;

[Severity: Medium]
Are these C bitfields safe to use for a firmware message interface?

When the driver communicates with the firmware on a big-endian architecture
or using a compiler with different bitfield ordering rules, the bitfields
in xe_ras_info_queue_header will map to the wrong bits in the underlying
32-bit word.

Using C bitfields inside a __packed struct for a hardware/firmware ABI is
generally avoided because their memory layout is compiler-dependent and
endian-dependent. Would it be safer to use fixed-width types like u32
along with FIELD_GET() and FIELD_PREP() macros?

> +	/** @checksum: CRC32 checksum of this chunk data */
> +	u32 checksum;
> +} __packed;
> +
[ ... ]

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20260825175916.1103841-13-badal.nilawar@intel.com?part=1

Re: [PATCH v2 05/11] drm/xe/cper: Prepare Intel CPER error info from info queue

[sashiko-bot]

Thank you for your contribution! Sashiko AI review found 6 potential issue(s) to consider:
- [Critical] Integer overflow in the info queue chunk bounds check allows a heap buffer overflow.
- [High] Missing bounds check on `chunk_size` against maximum chunk array length leads to a kernel stack out-of-bounds read and information leak.
- [High] Unbounded processing of info queue chunks can cause an infinite loop and Denial of Service.
- [Medium] Firmware-provided `total_size` is trusted over actual fetched bytes, leading to uninitialized memory being parsed as valid error logs.
- [Medium] Capping `num_logs` to `XE_RAS_NUM_COUNTERS` incorrectly truncates log streams and desynchronizes aggregate parsing.
- [Medium] The aggregate error counter parsing loop creates a sparse array when `num_logs == 0`, leading to the emission of corrupted empty CPER records.
--

commit 426ce853adfa4b210c0c07504ac804ae25dd5a2b
Author: Badal Nilawar <badal.nilawar@intel.com>

drm/xe/cper: Prepare Intel CPER error info from info queue

This commit adds a function to assemble raw info queue data embedded in a
GET_COUNTER response and subsequent chunks into an Intel CPER error info
structure. The data is retrieved in chunks from the firmware and parsed
into detail or aggregate error records.

> diff --git a/drivers/gpu/drm/xe/xe_ras.c b/drivers/gpu/drm/xe/xe_ras.c
> index e913235e9cceb..27c78800b5d27 100644
> --- a/drivers/gpu/drm/xe/xe_ras.c
> +++ b/drivers/gpu/drm/xe/xe_ras.c
[ ... ]
> +static struct xe_cper_einfo_entry *
> +prepare_cper_error_info(struct xe_device *xe,
> +			const struct xe_ras_get_counter_response *counter_resp,
> +			const struct xe_ras_error_class *error_class,
> +			u32 *count_out)
> +{
[ ... ]
> +	raw_buf = kzalloc(XE_RAS_INFO_QUEUE_MAX_TOTAL_SIZE, GFP_KERNEL);
> +	if (!raw_buf)
> +		return NULL;
> +
> +	/* Copy first chunk already embedded in the counter response */
> +	if (first_qhdr->chunk_size &&
> +	    first_qhdr->chunk_offset + first_qhdr->chunk_size <=
> +	    XE_RAS_INFO_QUEUE_MAX_TOTAL_SIZE) {

[Severity: Critical]
Is `chunk_offset + chunk_size` vulnerable to a 32-bit integer overflow here?
If the firmware provides large values, such as `chunk_offset = 0xFFFFFF00`
and `chunk_size = 0x200`, the sum would wrap around to 0x100, which is less
than `XE_RAS_INFO_QUEUE_MAX_TOTAL_SIZE` (5120). This would bypass the check
and allow the subsequent `memcpy` to write out-of-bounds on the heap.

> +		memcpy(raw_buf + first_qhdr->chunk_offset,
> +		       counter_resp->info_queue.queue_data,
> +		       first_qhdr->chunk_size);

[Severity: High]
Is `first_qhdr->chunk_size` validated against the actual capacity of the
source `queue_data` buffer? The check above only ensures it fits within
`XE_RAS_INFO_QUEUE_MAX_TOTAL_SIZE` (5120), but `queue_data` has a maximum
size of `XE_RAS_INFO_QUEUE_MAX_CHUNK_SIZE`. Since `counter_resp` is allocated
on the caller's stack, could a malicious or broken firmware return a
`chunk_size` greater than the array size and cause this `memcpy` to read past
the buffer, leaking adjacent kernel stack memory?

> +		iq_offset = first_qhdr->chunk_size;
> +	}
> +
> +	/* Fetch any remaining chunks */
> +	if (first_qhdr->flags & XE_RAS_INFO_QUEUE_FLAG_MORE_DATA) {
> +		iq_req.source_command			= XE_SYSCTRL_CMD_GET_COUNTER;
> +		iq_req.source_context			= counter_resp->counter;
> +		iq_req.queue_request.requested_size	= XE_RAS_INFO_QUEUE_MAX_CHUNK_SIZE;
> +		iq_req.queue_request.session_id		= counter_resp->counter;
> +
> +		do {
> +			struct xe_ras_info_queue_header *qhdr;
> +			u32 end;
> +
> +			iq_req.queue_request.requested_offset = iq_offset;
> +
> +			if (get_info_queue_data(xe, &iq_req, &iq_response))
> +				break;
> +
> +			qhdr = &iq_response.queue_response.queue_header;
> +			end  = qhdr->chunk_offset + qhdr->chunk_size;
> +
> +			if (end > XE_RAS_INFO_QUEUE_MAX_TOTAL_SIZE) {

[Severity: Critical]
Does the `qhdr->chunk_offset + qhdr->chunk_size` calculation here have the
same 32-bit integer overflow risk as the first chunk check, potentially
allowing out-of-bounds writes into `raw_buf`?

> +				xe_warn(xe, "[RAS]: CPER: info queue chunk out of bounds (offset=%u size=%u)\n",
> +					qhdr->chunk_offset, qhdr->chunk_size);
> +				break;
> +			}
> +
> +			memcpy(raw_buf + qhdr->chunk_offset,
> +			       iq_response.queue_response.queue_data,
> +			       qhdr->chunk_size);

[Severity: High]
Similar to the first chunk copy, is there a missing bounds check here to
ensure `qhdr->chunk_size` does not exceed the size of the stack-allocated
`iq_response.queue_response.queue_data` array, which could lead to another
stack out-of-bounds read?

> +
> +			if (!qhdr->chunk_size)
> +				break;
> +
> +			iq_offset += qhdr->chunk_size;
> +		} while (iq_response.queue_response.queue_header.flags &
> +			 XE_RAS_INFO_QUEUE_FLAG_MORE_DATA);

[Severity: High]
Does this `do-while` loop have a bounded maximum number of iterations or a
timeout? If a broken or malicious firmware repeatedly returns a valid small
chunk with the `XE_RAS_INFO_QUEUE_FLAG_MORE_DATA` flag set, could this
loop run indefinitely and cause a kernel soft lockup?

> +	}
> +
> +	raw_total = first_qhdr->total_size
> +		  ? min(first_qhdr->total_size, XE_RAS_INFO_QUEUE_MAX_TOTAL_SIZE)
> +		  : iq_offset;

[Severity: Medium]
If `get_info_queue_data()` fails or the fetch loop terminates early, `raw_buf`
is only partially populated. By unconditionally using `first_qhdr->total_size`
here (when non-zero) instead of `iq_offset`, won't the code later parse
trailing uninitialized (zero-filled) sections of `raw_buf` as valid dynamic
headers and error logs?

[ ... ]
> +	} else {
> +		/* Aggregate case: one einfo per dynamic-counter header */
> +		const struct xe_ras_info_queue_dynamic_counter_hdr *hdrs =
> +			(const struct xe_ras_info_queue_dynamic_counter_hdr *)raw_buf;
> +		const struct xe_ras_error_log *all_logs =
> +			(const struct xe_ras_error_log *)(raw_buf + headers_size);
> +		u32 avail_logs = (raw_total - headers_size) / sizeof(struct xe_ras_error_log);
> +		u32 log_offset = 0;
> +
> +		einfo_arr = kzalloc_objs(*einfo_arr, num_headers, GFP_KERNEL);
> +		if (!einfo_arr) {
> +			kfree(raw_buf);
> +			return NULL;
> +		}
> +
> +		for (i = 0; i < num_headers; i++) {
> +			u32 num_logs = min_t(u32, hdrs[i].counter, XE_RAS_NUM_COUNTERS);

[Severity: Medium]
Does capping `num_logs` to `XE_RAS_NUM_COUNTERS` (16) cause desynchronization
when parsing the raw log stream? If the hardware actually embedded more than
16 logs for a specific header, limiting `num_logs` to 16 means `log_offset`
will only advance by 16. Won't the remaining logs then be incorrectly parsed
as belonging to the next aggregate header in the stream?

> +			struct xe_cper_sec_intel_error_info *einfo;
> +			struct xe_intel_priv_event_entry *entry;
> +			u32 einfo_size;
> +			u32 j;
> +
> +			if (log_offset + num_logs > avail_logs) {
> +				xe_warn(xe, "[RAS]: CPER: header[%u] claims %u logs but only %u remain\n",
> +					i, num_logs, avail_logs - log_offset);
> +				break;
> +			}
> +
> +			if (!num_logs) {
> +				log_offset += num_logs;
> +				continue;
> +			}

[Severity: Medium]
If `num_logs` is 0, this branch continues without initializing the header data
for `einfo_arr[i]`. Does this leave an uninitialized gap in the `einfo_arr`
array that gets exposed to the caller, leading to the emission of malformed
empty CPER records?

> +
> +			einfo_size = sizeof(*einfo) + num_logs * entry_size;
> +			einfo = kzalloc(einfo_size, GFP_KERNEL);
[ ... ]
> +			einfo_arr[i].hdr        = hdrs[i];
> +			einfo_arr[i].einfo      = einfo;
> +			einfo_arr[i].einfo_size = einfo_size;
> +			log_offset += num_logs;
> +		}
> +
> +		*count_out = i;

[Severity: Medium]
If the loop encounters headers where `num_logs == 0`, `*count_out` is still
set to the total number of headers processed (including the skipped ones).
Could this cause the caller to consume the sparse, zero-filled array entries
that were skipped earlier?

> +	}
> +
> +	kfree(raw_buf);
> +	return einfo_arr;
> +}

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20260825175916.1103841-13-badal.nilawar@intel.com?part=5

Re: [PATCH v2 07/11] drm/xe/cper: Allow hardware error CPER reporting from xe_log

[sashiko-bot]

Thank you for your contribution! Sashiko AI review found 3 potential issue(s) to consider:
- [High] Blindly casting and passing the optional `data` parameter in `log_emit_cper` to hardware CPER emission paths causes kernel crashes if the pointer is NULL or an ERR_PTR.
- [High] Synchronous hardware CPER emission inside the `xe_log` backend introduces blocking and sleepable operations into general-purpose logging paths, leading to deadlocks and panics when called from atomic contexts.
- [Medium] Missing payload length validation before casting `data` to `struct xe_ras_error_class *` allows out-of-bounds memory access.
--

commit cde7fec12b9f07e68b4ed966ff02eeef7dd8e6db
Author: Badal Nilawar <badal.nilawar@intel.com>

drm/xe/cper: Allow hardware error CPER reporting from xe_log
    
Add a public wrapper xe_emit_hardware_error_cper() to enable xe_log.c to
emit hardware error CPER records. This hooks into log_emit_cper() to report
hardware signatures.

> diff --git a/drivers/gpu/drm/xe/xe_log.c b/drivers/gpu/drm/xe/xe_log.c
> index 5549ef6966fd8..c78fc195c55bd 100644
> --- a/drivers/gpu/drm/xe/xe_log.c
> +++ b/drivers/gpu/drm/xe/xe_log.c
[ ... ]
> @@ -10,15 +10,25 @@
>  
>  #include "xe_device.h"
>  #include "xe_log.h"
> +#include "xe_ras.h"
>  #include "xe_printk.h"
>  
> +static bool is_hw_sigid(enum xe_sigid sigid)
> +{
> +	return (int)sigid >= INTEL_SIGID_GPU_XE_HARDWARE_START;
> +}
> +
>  static void log_emit_cper(struct pci_dev *pdev, int cper_sev, enum xe_sigid sigid,
>  			  u32 component, u32 location, const void *data, size_t len,
>  			  struct va_format *vaf)
>  {
>  	KUNIT_STATIC_STUB_REDIRECT(log_emit_cper, pdev, cper_sev, sigid,
>  				   component, location, data, len, vaf);
> -	/* TODO */
> +	/* TODO software CPER */
> +
> +	if (is_hw_sigid(sigid))
> +		xe_emit_hardware_error_cper(pdev, cper_sev, sigid,
> +					    (struct xe_ras_error_class *)data);

[Severity: High]
Will this block or sleep when called from atomic contexts?

When a caller invokes xe_log macros (such as xe_log_comp_fatal()) from an
interrupt handler or while holding a spinlock, this synchronously invokes
xe_emit_hardware_error_cper() from a general-purpose logging path.

The underlying hardware CPER emission path eventually calls get_counter(),
which invokes xe_sysctrl_send_command(). That function explicitly checks
for sleep and acquires a mutex:

drivers/gpu/drm/xe/xe_sysctrl_mailbox.c:xe_sysctrl_send_command() {
    might_sleep();
    ...
    guard(mutex)(&sc->cmd_lock);
    ...
}

Should this operation be deferred to a workqueue to avoid deadlocks when
logging from atomic contexts?

[Severity: Medium]
Could this cause an out-of-bounds read if the provided payload is smaller
than the expected structure?

The __xe_log_emit() API accepts an opaque data pointer alongside a length
parameter. Since this cast ignores the len parameter, if a caller provides a
valid payload that is smaller than sizeof(struct xe_ras_error_class),
downstream functions like get_counter() will read past the end of the buffer
when dereferencing it:

drivers/gpu/drm/xe/xe_ras.c:get_counter() {
    ...
    request.counter = *counter;
    ...
}

>  }
[ ... ]
> diff --git a/drivers/gpu/drm/xe/xe_ras.c b/drivers/gpu/drm/xe/xe_ras.c
> index ff9d917b8e29c..b4cdb5ec64915 100644
> --- a/drivers/gpu/drm/xe/xe_ras.c
> +++ b/drivers/gpu/drm/xe/xe_ras.c
> @@ -837,6 +837,29 @@ static void emit_hw_error_cper(struct xe_device *xe,
>  	}
>  }
>  
> +/**
> + * xe_emit_hardware_error_cper() - Emit a hardware error CPER record
> + * @pdev: PCI device associated with the Xe device
> + * @cper_sev: CPER severity
> + * @sigid: Error signature identifier
> + * @error_class: Hardware error classification details
> + *
> + * Emit a CPER record for a hardware error
> + */
> +void xe_emit_hardware_error_cper(struct pci_dev *pdev, int cper_sev, enum xe_sigid sigid,
> +				 struct xe_ras_error_class *counter)
> +{
> +	struct xe_device *xe = pdev_to_xe_device(pdev);
> +
> +	if (!xe)
> +		return;
> +
> +	if (counter && !ras_counter_is_valid(xe, counter))
> +		return;

[Severity: High]
Does this check handle error pointers or NULL pointers safely?

The xe_log_err() macro permits the data parameter to be an ERR_PTR
(e.g., ERR_PTR(-EIO)). Because an error pointer is not NULL, this check
will pass it directly to ras_counter_is_valid(), which will dereference it
and cause a kernel panic:

drivers/gpu/drm/xe/xe_ras.c:ras_counter_is_valid() {
    u8 severity = counter->common.severity;
    ...
}

Furthermore, if counter is NULL, this check is bypassed entirely, but the
pointer is later unconditionally dereferenced inside get_counter() when
emit_hw_error_cper() is called:

drivers/gpu/drm/xe/xe_ras.c:get_counter() {
    ...
    request.counter = *counter;
    ...
}

> +
> +	emit_hw_error_cper(xe, counter, NULL, sigid, cper_sev);
> +}
> +
>  /**
>   * xe_ras_process_errors() - Process and contain hardware errors
>   * @xe: xe device instance
[ ... ]

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20260825175916.1103841-13-badal.nilawar@intel.com?part=7

Re: [PATCH v2 06/11] drm/xe/cper: Log CPER records for aggregate counter retrival

[sashiko-bot]

Thank you for your contribution! Sashiko AI review found 5 potential issue(s) to consider:

New issues:
- [Medium] Unconditional CPER record emission on counter retrieval causes log spam and zero-error records.
- [Medium] Spurious CPER records with empty metadata are emitted for info queue headers with zero logs.

Pre-existing issues:
- [Critical] An integer overflow in the bounds check `chunk_offset + chunk_size` allows firmware to perform an out-of-bounds write relative to the `raw_buf` heap allocation.
- [High] Missing bounds check on `chunk_size` against `XE_RAS_INFO_QUEUE_MAX_CHUNK_SIZE` allows a stack buffer over-read, leaking sensitive kernel stack data.
- [High] The do-while loop fetching info queue chunks can be forced into an infinite loop by malicious firmware, causing a kernel lockup.
--

commit 07283a153280cbc84316c197325268cbc06ecfe6
Author: Badal Nilawar <badal.nilawar@intel.com>

drm/xe/cper: Log CPER records for aggregate counter retrival
    
Log CPER records for aggregate counter retrieval from userspace.

> diff --git a/drivers/gpu/drm/xe/xe_ras.c b/drivers/gpu/drm/xe/xe_ras.c
> index 27c78800b5d27..ff9d917b8e29c 100644
> --- a/drivers/gpu/drm/xe/xe_ras.c
> +++ b/drivers/gpu/drm/xe/xe_ras.c
[ ... ]
> @@ -749,6 +777,66 @@ prepare_cper_error_info(struct xe_device *xe,
>  	return einfo_arr;
>  }
>  
> +static void emit_hw_error_cper(struct xe_device *xe,
> +			       struct xe_ras_error_class *error_class,
> +			       struct xe_ras_get_counter_response *resp,
> +			       u32 sig_id, u8 severity)
> +{
[ ... ]
> +	if (einfo_count > 0) {
> +		for (i = 0; i < einfo_count; i++) {
> +			struct xe_cper_sec_intel_err_hdr entry_ihdr = {};
> +
> +			xe_cper_init_intel_err_hdr(xe,
> +						   (const u8 *)&einfo_arr[i].hdr.error_class,

[Severity: Medium]
When prepare_cper_error_info() processes an info queue header with 0 logs, it
skips initializing einfo_arr[i] but still includes it in the *count_out total.
Does this loop unconditionally access and emit CPER records for potentially
uninitialized (zeroed) elements of the einfo_arr array?

[ ... ]
> +	} else {
> +		xe_cper_init_intel_err_hdr(xe,
> +					   (const u8 *)error_class,
> +					   counter_response->timestamp,
> +					   sig_id,
> +					   counter_response->value,
> +					   &ihdr);
> +		xe_cper_record_emit(xe, severity, &INTEL_CPER_NOTIFY_GPU_ERROR,
> +				    &ihdr, NULL, 0);
> +	}

[Severity: Medium]
If counter_response->value is 0 and there is no info queue, will this fallback
path explicitly emit a CPER record reporting 0 errors?

[ ... ]
> @@ -886,6 +974,10 @@ int xe_ras_get_counter(struct xe_device *xe, u8 severity, u8 component, u32 *val
>  		return ret;
>  
>  	*value = response.value;
> +
> +	emit_hw_error_cper(xe, &counter, &response,
> +			   ras_comp_to_hw_sigid(counter.common.component),
> +			   ras_sev_to_cper_sev(counter.common.severity));
>  	return 0;
>  }

[Severity: Medium]
Does this unconditional call trigger a CPER emission on every userspace read,
regardless of the counter's value or whether it has changed? This might lead
to log spam and incorrect zero-error telemetry when the counter is 0.

While reviewing this patch, I also noticed some pre-existing issues in the
nearby prepare_cper_error_info() function:

> 	if (first_qhdr->chunk_size &&
> 	    first_qhdr->chunk_offset + first_qhdr->chunk_size <=
> 	    XE_RAS_INFO_QUEUE_MAX_TOTAL_SIZE) {

[Severity: Critical]
This is a pre-existing issue, but is this boundary validation vulnerable to an
integer overflow? If the firmware provides a large chunk_offset (e.g.
0xFFFFFFF0) and a small chunk_size (e.g. 0x20), the sum could wrap around and
bypass the check, potentially allowing an out-of-bounds write relative to the
raw_buf heap allocation.

> 		memcpy(raw_buf + first_qhdr->chunk_offset,
> 		       counter_resp->info_queue.queue_data,
> 		       first_qhdr->chunk_size);

[Severity: High]
This is a pre-existing issue, but does this memcpy lack a bounds check on
chunk_size against the stack-allocated queue_data array bounds
(XE_RAS_INFO_QUEUE_MAX_CHUNK_SIZE)? If firmware provides a large chunk_size
that passes the total boundary check, could this read past the end of the array
and leak sensitive kernel stack memory into the heap buffer?

[ ... ]
> 		do {
> 			struct xe_ras_info_queue_header *qhdr;
> 			u32 end;
[ ... ]
> 			qhdr = &iq_response.queue_response.queue_header;
> 			end  = qhdr->chunk_offset + qhdr->chunk_size;
> 
> 			if (end > XE_RAS_INFO_QUEUE_MAX_TOTAL_SIZE) {

[Severity: Critical]
This is a pre-existing issue, but similar to the first chunk, is this
subsequent boundary validation also vulnerable to an integer overflow if
chunk_offset and chunk_size wrap around?

> 			memcpy(raw_buf + qhdr->chunk_offset,
> 			       iq_response.queue_response.queue_data,
> 			       qhdr->chunk_size);

[Severity: High]
This is a pre-existing issue, but does this location also lack a bounds check
on chunk_size against the size of the iq_response stack variable, potentially
allowing a stack buffer over-read?

[ ... ]
> 			if (!qhdr->chunk_size)
> 				break;
> 
> 			iq_offset += qhdr->chunk_size;
> 		} while (iq_response.queue_response.queue_header.flags &
> 			 XE_RAS_INFO_QUEUE_FLAG_MORE_DATA);

[Severity: High]
This is a pre-existing issue, but can this do-while loop be forced into an
infinite loop by malicious or unresponsive firmware? If the firmware repeatedly
returns a valid chunk_offset and chunk_size with the MORE_DATA flag set such
that the calculated end boundary never exceeds the limit, could this cause a
kernel soft lockup?

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20260825175916.1103841-13-badal.nilawar@intel.com?part=6

Re: [PATCH v2 09/11] drm/xe/ras: Report core compute errors using SIGID

[sashiko-bot]

Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [Medium] Correctable and Informational core compute errors are incorrectly logged as Recoverable (Uncorrectable).
--

commit 784da44cd9d1ac029dd88040b479607457b9f5e1
Author: Badal Nilawar <badal.nilawar@intel.com>

drm/xe/ras: Report core compute errors using SIGID

This commit updates the handling of core compute errors to utilize the
xe_log_* helpers for error reporting, passing the xe_device context to
handle_core_compute_errors().

> diff --git a/drivers/gpu/drm/xe/xe_ras.c b/drivers/gpu/drm/xe/xe_ras.c
> index 172653be1b829..3b43d363d5de5 100644
> --- a/drivers/gpu/drm/xe/xe_ras.c
> +++ b/drivers/gpu/drm/xe/xe_ras.c

[ ... ]

> @@ -340,13 +340,18 @@ static u8 handle_core_compute_errors(struct xe_ras_error_array *arr)
>  	uncorr_type = FIELD_GET(CORE_COMPUTE_UNCORR_TYPE, error_info->log_header);
>  
>  	/* Request a reset if error is global */
> -	if (uncorr_type == GLOBAL_UNCORR_ERROR)
> +	if (uncorr_type == GLOBAL_UNCORR_ERROR) {
> +		xe_log_comp_recoverable(xe, CORE_COMPUTE, &arr->counter, sizeof(arr->counter),
> +					"Global uncorrectable error detected\n");
>  		return XE_RAS_RECOVERY_ACTION_RESET;
> +	}
>  
>  	/*
>  	 * No action needed for other errors.
>  	 * Local errors are recovered using an engine reset by GuC.
>  	 */
> +	xe_log_comp_recoverable(xe, CORE_COMPUTE, &arr->counter, sizeof(arr->counter),
> +				"Other compute errors\n");

[Severity: Medium]
Does this incorrectly classify correctable and informational errors as
recoverable?

In handle_core_compute_errors(), all non-global errors (which can include
correctable and informational hardware errors) fall through to this path. By
using xe_log_comp_recoverable(), the code unconditionally logs these errors
with CPER_SEV_RECOVERABLE severity.

This misclassifies the severity in the CPER records, making non-critical
errors appear as recoverable uncorrectable errors in telemetry.

>  	return XE_RAS_RECOVERY_ACTION_RECOVERED;
>  }

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20260825175916.1103841-13-badal.nilawar@intel.com?part=9

Re: [PATCH v2 08/11] drm/xe/ras: Report device memory errors using SIGID

[sashiko-bot]

Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [Medium] The `xe_log_err` family of macros passes `ERR_PTR(err)` to the logging framework, which crashes when used with hardware component tags due to an unchecked cast.
--

commit 3a41849b5bfff0854c8490dfdd5d178d31641b09
Author: Badal Nilawar <badal.nilawar@intel.com>

drm/xe/ras: Report device memory errors using SIGID

This commit updates the device memory error handler to use the
xe_log_comp_info() helper instead of xe_info(). This allows reporting
these errors with the DEVICE_MEMORY hardware component tag.

> diff --git a/drivers/gpu/drm/xe/xe_ras.c b/drivers/gpu/drm/xe/xe_ras.c
> index b4cdb5ec64915..172653be1b829 100644
> --- a/drivers/gpu/drm/xe/xe_ras.c
> +++ b/drivers/gpu/drm/xe/xe_ras.c
> @@ -409,14 +409,17 @@ static u8 handle_device_memory_errors(struct xe_device *xe, struct xe_ras_error_
>  	 */
>  	switch (info->category) {
>  	case XE_RAS_MEMORY_POISON:
> -		xe_info(xe, "[RAS]: Poison error detected\n");
> +		xe_log_comp_info(xe, DEVICE_MEMORY, &arr->counter, sizeof(arr->counter),
> +				 "Poison error detected\n");

[Severity: Medium]
Does introducing the DEVICE_MEMORY hardware tag expose a latent API trap in
the logging framework?

While this specific call passes a valid pointer (&arr->counter), the logging
macro family is documented to allow passing ERR_PTR(err) as the data
parameter.

If a developer later calls xe_log_err(any, DEVICE_MEMORY, err, ...), it
passes ERR_PTR(err) as the data parameter. This gets processed in
log_emit_cper():

drivers/gpu/drm/xe/xe_log.c:log_emit_cper() {
    ...
    if (is_hw_sigid(sigid))
        xe_emit_hardware_error_cper(pdev, cper_sev, sigid,
                                    (struct xe_ras_error_class *)data);
    ...
}

This blindly casts the data parameter to struct xe_ras_error_class *.
Then xe_emit_hardware_error_cper() checks if it is non-NULL but fails to check
for an error pointer:

drivers/gpu/drm/xe/xe_ras.c:xe_emit_hardware_error_cper() {
    ...
    if (counter && !ras_counter_is_valid(xe, counter))
    ...
}

This leads to an invalid pointer dereference when ras_counter_is_valid()
accesses the severity field:

drivers/gpu/drm/xe/xe_ras.c:ras_counter_is_valid() {
    ...
    u8 severity = counter->common.severity;
    ...
}

Should an IS_ERR() check be added in log_emit_cper() or
xe_emit_hardware_error_cper() before dereferencing the pointer to prevent a
potential kernel crash?

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20260825175916.1103841-13-badal.nilawar@intel.com?part=8

[PATCH v2 00/11] Add CPER logging support for CRI

[Badal Nilawar]

This patch series adds CPER (Common Platform Error Record) logging support
for Correctable errors reported by Intel Xe GPUs. CPER logging is done
through trace event.

v2:
   - Extended CPER logging to Uncorrectable errors and xe_ras_get_counter
     request
   - Log CPER records via xe_log SIGID infra 

Badal Nilawar (11):
  drm/xe/xe_ras: Add support to retrieve info queue data for CRI
  drm/xe/xe_ras: Refactor get_counter() to return response structure
  drm/xe/cper: Add CPER structures and trace event
  drm/xe/cper: APIs to prepare and log CPER record
  drm/xe/cper: Prepare Intel CPER error info from info queue
  drm/xe/cper: Log CPER records for aggregate counter retrival
  drm/xe/cper: Allow hardware error CPER reporting from xe_log
  drm/xe/ras: Report device memory errors using SIGID
  drm/xe/ras: Report core compute errors using SIGID
  drm/xe/ras: Report soc internal errors using SIGID
  drm/xe/ras: Report correctable errors using SIGID

 drivers/gpu/drm/xe/Makefile                   |   4 +
 drivers/gpu/drm/xe/regs/xe_regs.h             |   2 +
 drivers/gpu/drm/xe/xe_cper.c                  | 184 +++++++
 drivers/gpu/drm/xe/xe_cper.h                  |  34 ++
 drivers/gpu/drm/xe/xe_cper_types.h            | 186 +++++++
 drivers/gpu/drm/xe/xe_log.c                   |  17 +-
 drivers/gpu/drm/xe/xe_ras.c                   | 506 ++++++++++++++++--
 drivers/gpu/drm/xe/xe_ras.h                   |   4 +
 drivers/gpu/drm/xe/xe_ras_types.h             | 118 +++-
 drivers/gpu/drm/xe/xe_sysctrl_mailbox_types.h |   2 +
 drivers/gpu/drm/xe/xe_trace_cper.c            |   9 +
 drivers/gpu/drm/xe/xe_trace_cper.h            |  66 +++
 12 files changed, 1093 insertions(+), 39 deletions(-)
 create mode 100644 drivers/gpu/drm/xe/xe_cper.c
 create mode 100644 drivers/gpu/drm/xe/xe_cper.h
 create mode 100644 drivers/gpu/drm/xe/xe_cper_types.h
 create mode 100644 drivers/gpu/drm/xe/xe_trace_cper.c
 create mode 100644 drivers/gpu/drm/xe/xe_trace_cper.h

-- 
2.54.0

[PATCH v2 01/11] drm/xe/xe_ras: Add support to retrieve info queue data for CRI

[Badal Nilawar]

Add support to retrieve info queue data. While constructing CPER
record info queue data will be retrieved when has_info_queue=1 is
set in get_counter response.

Signed-off-by: Badal Nilawar <badal.nilawar@intel.com>
Assisted-by: Copilot:claude-sonnet-4.6
---
v2: Drop unused flags (Mallesh)
---
 drivers/gpu/drm/xe/xe_ras.c                   |  34 ++++++
 drivers/gpu/drm/xe/xe_ras_types.h             | 108 ++++++++++++++++++
 drivers/gpu/drm/xe/xe_sysctrl_mailbox_types.h |   2 +
 3 files changed, 144 insertions(+)

diff --git a/drivers/gpu/drm/xe/xe_ras.c b/drivers/gpu/drm/xe/xe_ras.c
index d25d25f77531..683087235482 100644
--- a/drivers/gpu/drm/xe/xe_ras.c
+++ b/drivers/gpu/drm/xe/xe_ras.c
@@ -661,6 +661,40 @@ int xe_ras_clear_counter(struct xe_device *xe, u8 severity, u8 component)
 	return 0;
 }
 
+static int get_info_queue_data(struct xe_device *xe,
+			       const struct xe_ras_get_info_queue_data_request *req,
+			       struct xe_ras_get_info_queue_data_response *out)
+{
+	struct xe_ras_get_info_queue_data_response response = {0};
+	struct xe_sysctrl_mailbox_command command = {0};
+	size_t rlen;
+	int ret;
+
+	xe_sysctrl_create_command(&command, XE_SYSCTRL_GROUP_GFSP,
+				  XE_SYSCTRL_CMD_GET_INFO_QUEUE_DATA,
+				  (void *)req, sizeof(*req), &response, sizeof(response));
+
+	ret = xe_sysctrl_send_command(&xe->sc, &command, &rlen);
+	if (ret) {
+		xe_err(xe, "sysctrl: failed to get info queue data %d\n", ret);
+		return ret;
+	}
+
+	if (rlen != sizeof(response)) {
+		xe_err(xe, "sysctrl: unexpected get info queue data response length %zu (expected %zu)\n",
+		       rlen, sizeof(response));
+		return -EIO;
+	}
+
+	xe_dbg(xe, "[RAS]: info queue data: status=%u chunk_size=%u flags=0x%x\n",
+	       response.operation_status,
+	       response.queue_response.queue_header.chunk_size,
+	       response.queue_response.queue_header.flags);
+
+	*out = response;
+	return 0;
+}
+
 static ssize_t gpu_health_show(struct device *dev, struct device_attribute *attr, char *buf)
 {
 	struct xe_ras_get_health_response response = {0};
diff --git a/drivers/gpu/drm/xe/xe_ras_types.h b/drivers/gpu/drm/xe/xe_ras_types.h
index 99b2466e2062..d87db9f5174a 100644
--- a/drivers/gpu/drm/xe/xe_ras_types.h
+++ b/drivers/gpu/drm/xe/xe_ras_types.h
@@ -16,6 +16,10 @@
 #define XE_RAS_MEMORY_DB_ECC			BIT(1)
 #define XE_RAS_MEMORY_POISON			BIT(2)
 #define XE_RAS_MEMORY_DATA_PARITY		BIT(5)
+#define XE_RAS_INFO_QUEUE_MAX_CHUNK_SIZE	200
+#define XE_RAS_INFO_QUEUE_MAX_TOTAL_SIZE	5120
+#define XE_RAS_INFO_QUEUE_FLAG_AVAILABLE	0x01
+#define XE_RAS_INFO_QUEUE_FLAG_MORE_DATA	0x02
 
 /**
  * enum xe_ras_recovery_action - RAS recovery actions
@@ -95,6 +99,109 @@ struct xe_ras_threshold_crossed {
 	struct xe_ras_error_class counters[XE_RAS_NUM_COUNTERS];
 } __packed;
 
+/**
+ * struct xe_ras_info_queue_header - Metadata for large info queue data transfers
+ *
+ * Provides chunk metadata for commands that support extended info queue
+ * functionality. Used when the total data exceeds a single mailbox response.
+ */
+struct xe_ras_info_queue_header {
+	/** @total_size: Total size of the complete info queue data in bytes */
+	u32 total_size;
+	/** @chunk_offset: Offset of this chunk within the total data in bytes */
+	u32 chunk_offset;
+	/** @chunk_size: Size of the data in this chunk in bytes */
+	u32 chunk_size;
+	/** @sequence_number: Sequence number for this chunk, starts at 0 */
+	u32 sequence_number;
+	/** @flags: Info queue control flags (RAS_INFO_QUEUE_FLAG_*) */
+	u32 flags:8;
+	/** @compression_type: Compression algorithm used; 0 = none */
+	u32 compression_type:4;
+	/** @num_headers: Number of detailed counter headers at start of queue_data */
+	u32 num_headers:5;
+	/** @reserved: Reserved for future use */
+	u32 reserved:15;
+	/** @checksum: CRC32 checksum of this chunk data */
+	u32 checksum;
+} __packed;
+
+/**
+ * struct xe_ras_info_queue_request - Request for a specific chunk of info queue data
+ *
+ * Allows the driver to request continuation of large info queue transfers
+ * by specifying an offset and size within the full data set.
+ */
+struct xe_ras_info_queue_request {
+	/** @requested_offset: Byte offset of the requested data chunk */
+	u32 requested_offset;
+	/** @requested_size: Maximum size of the requested chunk in bytes */
+	u32 requested_size;
+	/** @session_id: Session ID to correlate multi-chunk transfers */
+	struct xe_ras_error_class session_id;
+	/** @reserved: Reserved for future use */
+	u32 reserved;
+} __packed;
+
+/**
+ * struct xe_ras_info_queue_response - Generic response for commands with info queues
+ *
+ * Standard response format for any command that returns an info queue
+ * payload. May be embedded in a command-specific response structure.
+ */
+struct xe_ras_info_queue_response {
+	/** @queue_header: Info queue metadata for this chunk */
+	struct xe_ras_info_queue_header queue_header;
+	/** @queue_data: Info queue data for this chunk */
+	u8 queue_data[XE_RAS_INFO_QUEUE_MAX_CHUNK_SIZE];
+} __packed;
+
+/**
+ * struct xe_ras_info_queue_dynamic_counter_hdr - Aggregate counter header entry
+ *
+ * When a session requests aggregate counter data, one header per matching
+ * dynamic counter class is prepended to the queue data. The @counter field
+ * indicates how many subsequent error log entries belong to this class.
+ */
+struct xe_ras_info_queue_dynamic_counter_hdr {
+	/** @error_class: Error class associated with this counter group */
+	struct xe_ras_error_class error_class;
+	/** @counter: Number of error log entries that follow for this class */
+	u32 counter;
+} __packed;
+
+/**
+ * struct xe_ras_error_log - Single error log entry following dynamic counter headers
+ */
+struct xe_ras_error_log {
+	/** @timestamp: Timestamp when the error was recorded */
+	u64 timestamp;
+	/** @error_details: Error-specific details */
+	u32 error_details[16];
+} __packed;
+
+/**
+ * struct xe_ras_get_info_queue_data_request - Request for RAS_CMD_GET_INFO_QUEUE_DATA
+ */
+struct xe_ras_get_info_queue_data_request {
+	/** @queue_request: Info queue request parameters */
+	struct xe_ras_info_queue_request queue_request;
+	/** @source_command: Original command that generated the info queue */
+	u32 source_command;
+	/** @source_context: Context from original command, if applicable */
+	struct xe_ras_error_class source_context;
+} __packed;
+
+/**
+ * struct xe_ras_get_info_queue_data_response - Response for RAS_CMD_GET_INFO_QUEUE_DATA
+ */
+struct xe_ras_get_info_queue_data_response {
+	/** @operation_status: Status of the retrieval operation */
+	u32 operation_status;
+	/** @queue_response: Info queue data chunk */
+	struct xe_ras_info_queue_response queue_response;
+} __packed;
+
 /**
  * struct xe_ras_get_counter_request - Request structure for get counter
  */
@@ -286,4 +393,5 @@ struct xe_ras_set_health_response {
 	/** @reserved1: Reserved for future use */
 	u32 reserved1[2];
 } __packed;
+
 #endif
diff --git a/drivers/gpu/drm/xe/xe_sysctrl_mailbox_types.h b/drivers/gpu/drm/xe/xe_sysctrl_mailbox_types.h
index d0341538ad05..17f53cb78dc4 100644
--- a/drivers/gpu/drm/xe/xe_sysctrl_mailbox_types.h
+++ b/drivers/gpu/drm/xe/xe_sysctrl_mailbox_types.h
@@ -28,6 +28,7 @@ enum xe_sysctrl_group {
  * @XE_SYSCTRL_CMD_GET_PENDING_EVENT: Retrieve pending event
  * @XE_SYSCTRL_CMD_GET_HEALTH: Retrieve gpu health
  * @XE_SYSCTRL_CMD_SET_HEALTH: Set gpu health
+ * @XE_SYSCTRL_CMD_GET_INFO_QUEUE_DATA: Retrieve a chunk of info queue data
  */
 enum xe_sysctrl_gfsp_cmd {
 	XE_SYSCTRL_CMD_GET_SOC_ERROR		= 0x01,
@@ -36,6 +37,7 @@ enum xe_sysctrl_gfsp_cmd {
 	XE_SYSCTRL_CMD_GET_PENDING_EVENT	= 0x07,
 	XE_SYSCTRL_CMD_GET_HEALTH		= 0x0B,
 	XE_SYSCTRL_CMD_SET_HEALTH		= 0x0C,
+	XE_SYSCTRL_CMD_GET_INFO_QUEUE_DATA	= 0x0D,
 };
 
 /**
-- 
2.54.0

[PATCH v2 02/11] drm/xe/xe_ras: Refactor get_counter() to return response structure

[Badal Nilawar]

Return the complete response structure from get_counter() instead of
only the counter value. This allows callers to access additional
response fields, such as has_info_queue for CPER record building.

Signed-off-by: Badal Nilawar <badal.nilawar@intel.com>
Assisted-by: Copilot:claude-sonnet-4.6
---
v2: Drop temporary response structure (Mallesh)
---
 drivers/gpu/drm/xe/xe_ras.c       | 36 +++++++++++++++++++------------
 drivers/gpu/drm/xe/xe_ras_types.h | 10 +++++++--
 2 files changed, 30 insertions(+), 16 deletions(-)

diff --git a/drivers/gpu/drm/xe/xe_ras.c b/drivers/gpu/drm/xe/xe_ras.c
index 683087235482..e913235e9cce 100644
--- a/drivers/gpu/drm/xe/xe_ras.c
+++ b/drivers/gpu/drm/xe/xe_ras.c
@@ -102,7 +102,8 @@ static const char * const gpu_health_states[] = {
 };
 static_assert(ARRAY_SIZE(gpu_health_states) == XE_RAS_HEALTH_MAX);
 
-static int get_counter(struct xe_device *xe, struct xe_ras_error_class *counter, u32 *value);
+static int get_counter(struct xe_device *xe, struct xe_ras_error_class *counter,
+		       struct xe_ras_get_counter_response *out);
 
 static u8 drm_to_xe_ras_severity(u8 severity)
 {
@@ -283,21 +284,21 @@ static void ras_usp_aer_init(struct xe_device *xe)
 static void ras_send_error_event(struct xe_device *xe, u8 severity, u8 component)
 {
 	struct xe_ras_error_class counter = {0};
+	struct xe_ras_get_counter_response response = {0};
 	u8 drm_severity, drm_component;
-	u32 value;
 	int ret;
 
 	counter.common.severity = severity;
 	counter.common.component = component;
 
-	ret = get_counter(xe, &counter, &value);
+	ret = get_counter(xe, &counter, &response);
 	if (ret)
 		return;
 
 	drm_severity = xe_to_drm_ras_severity(severity);
 	drm_component = xe_to_drm_ras_component(component);
 
-	xe_drm_ras_event(xe, drm_component, drm_severity, value);
+	xe_drm_ras_event(xe, drm_component, drm_severity, response.value);
 }
 
 static u8 handle_core_compute_errors(struct xe_ras_error_array *arr)
@@ -432,19 +433,20 @@ void xe_ras_counter_threshold_crossed(struct xe_device *xe,
 	}
 }
 
-static int get_counter(struct xe_device *xe, struct xe_ras_error_class *counter, u32 *value)
+static int get_counter(struct xe_device *xe, struct xe_ras_error_class *counter,
+		       struct xe_ras_get_counter_response *out)
 {
-	struct xe_ras_get_counter_response response = {0};
 	struct xe_ras_get_counter_request request = {0};
 	struct xe_sysctrl_mailbox_command command = {0};
 	struct xe_ras_error_common *common;
 	size_t rlen;
 	int ret;
 
+	memset(out, 0, sizeof(*out));
 	request.counter = *counter;
 
 	xe_sysctrl_create_command(&command, XE_SYSCTRL_GROUP_GFSP, XE_SYSCTRL_CMD_GET_COUNTER,
-				  &request, sizeof(request), &response, sizeof(response));
+				  &request, sizeof(request), out, sizeof(*out));
 
 	ret = xe_sysctrl_send_command(&xe->sc, &command, &rlen);
 	if (ret) {
@@ -452,19 +454,18 @@ static int get_counter(struct xe_device *xe, struct xe_ras_error_class *counter,
 		return ret;
 	}
 
-	if (rlen != sizeof(response)) {
+	if (rlen != sizeof(*out)) {
 		xe_err(xe, "sysctrl: unexpected get counter response length %zu (expected %zu)\n",
-		       rlen, sizeof(response));
+		       rlen, sizeof(*out));
 		return -EIO;
 	}
 
-	if (!ras_counter_is_valid(xe, &response.counter))
+	if (!ras_counter_is_valid(xe, &out->counter))
 		return -EBADMSG;
 
-	common = &response.counter.common;
-	*value = response.value;
+	common = &out->counter.common;
 
-	xe_dbg(xe, "[RAS]: get counter %u for %s %s\n", *value, comp_to_str(common->component),
+	xe_dbg(xe, "[RAS]: get counter %u for %s %s\n", out->value, comp_to_str(common->component),
 	       sev_to_str(common->severity));
 
 	return 0;
@@ -595,12 +596,19 @@ enum xe_ras_recovery_action xe_ras_process_errors(struct xe_device *xe)
 int xe_ras_get_counter(struct xe_device *xe, u8 severity, u8 component, u32 *value)
 {
 	struct xe_ras_error_class counter = {0};
+	struct xe_ras_get_counter_response response = {0};
+	int ret;
 
 	counter.common.severity = drm_to_xe_ras_severity(severity);
 	counter.common.component = drm_to_xe_ras_component(component);
 
 	guard(xe_pm_runtime)(xe);
-	return get_counter(xe, &counter, value);
+	ret = get_counter(xe, &counter, &response);
+	if (ret)
+		return ret;
+
+	*value = response.value;
+	return 0;
 }
 
 /**
diff --git a/drivers/gpu/drm/xe/xe_ras_types.h b/drivers/gpu/drm/xe/xe_ras_types.h
index d87db9f5174a..3c6d0419c51a 100644
--- a/drivers/gpu/drm/xe/xe_ras_types.h
+++ b/drivers/gpu/drm/xe/xe_ras_types.h
@@ -224,8 +224,14 @@ struct xe_ras_get_counter_response {
 	u64 timestamp;
 	/** @threshold: Threshold value for the counter */
 	u32 threshold;
-	/** @reserved: Reserved  */
-	u32 reserved[57];
+	/** @reserved: Reserved for future use */
+	u32 reserved:9;
+	/** @has_info_queue: Set if info queue is available */
+	u32 has_info_queue:1;
+	/** @reserved1: Reserved for future use */
+	u32 reserved1:22;
+	/** @info_queue: Initial info queue data (first chunk) if available */
+	struct xe_ras_info_queue_response info_queue;
 } __packed;
 
 /**
-- 
2.54.0

[PATCH v2 03/11] drm/xe/cper: Add CPER structures and trace event

[Badal Nilawar]

Define packed data structures and Intel-specific GUID macros needed
to build Intel GPU CPER (Common Platform Error Record) non-standard
records.

Add xe_error_cper trace event to log the assembled CPER record bytes.

Signed-off-by: Badal Nilawar <badal.nilawar@intel.com>
Assisted-by: Copilot:claude-sonnet-4.6
---
 drivers/gpu/drm/xe/Makefile        |   1 +
 drivers/gpu/drm/xe/xe_cper_types.h | 186 +++++++++++++++++++++++++++++
 drivers/gpu/drm/xe/xe_trace_cper.c |   9 ++
 drivers/gpu/drm/xe/xe_trace_cper.h |  66 ++++++++++
 4 files changed, 262 insertions(+)
 create mode 100644 drivers/gpu/drm/xe/xe_cper_types.h
 create mode 100644 drivers/gpu/drm/xe/xe_trace_cper.c
 create mode 100644 drivers/gpu/drm/xe/xe_trace_cper.h

diff --git a/drivers/gpu/drm/xe/Makefile b/drivers/gpu/drm/xe/Makefile
index 92134709d998..3ed60697f3f3 100644
--- a/drivers/gpu/drm/xe/Makefile
+++ b/drivers/gpu/drm/xe/Makefile
@@ -136,6 +136,7 @@ xe-y += xe_bb.o \
 	xe_tlb_inval_job.o \
 	xe_trace.o \
 	xe_trace_bo.o \
+	xe_trace_cper.o \
 	xe_trace_guc.o \
 	xe_trace_lrc.o \
 	xe_ttm_stolen_mgr.o \
diff --git a/drivers/gpu/drm/xe/xe_cper_types.h b/drivers/gpu/drm/xe/xe_cper_types.h
new file mode 100644
index 000000000000..82167ea4eb16
--- /dev/null
+++ b/drivers/gpu/drm/xe/xe_cper_types.h
@@ -0,0 +1,186 @@
+/* SPDX-License-Identifier: MIT */
+/*
+ * Copyright © 2026 Intel Corporation
+ */
+
+#ifndef _XE_CPER_TYPES_H_
+#define _XE_CPER_TYPES_H_
+
+#include <linux/cper.h>
+#include <linux/types.h>
+#include <linux/uuid.h>
+
+/* Intel CPER GUID Namespace — RFC 9562 UUIDv5 (SHA-1 name-based)
+ *
+ * All values below are generated deterministically by the shell script
+ * in the [Generation Script] section. Re-run that script to verify.
+ * Do NOT hand-edit the byte values.
+ */
+
+/* Creator IDs */
+#define INTEL_CPER_CREATOR_XEKMD \
+	GUID_INIT(0x9a42070f, 0xdf9d, 0x555e, \
+		  0xba, 0x02, 0x7c, 0xbc, 0x86, 0x3d, 0x37, 0x1c)
+
+#define INTEL_CPER_CREATOR_AMC \
+	GUID_INIT(0x215803da, 0xfc7a, 0x5925, \
+		  0xb7, 0x8b, 0x1f, 0xc1, 0x19, 0x61, 0x58, 0xd1)
+
+/* Notification Types */
+#define INTEL_CPER_NOTIFY_GPU_ERROR \
+	GUID_INIT(0x4ae12aef, 0x8745, 0x5fc7, \
+		  0xb9, 0x96, 0x71, 0xee, 0xbb, 0x51, 0xf2, 0x23)
+
+#define INTEL_CPER_NOTIFY_DRV_ERROR \
+	GUID_INIT(0xcef7e934, 0x51e7, 0x535f, \
+		  0xa6, 0x78, 0x5a, 0x4c, 0xcc, 0xb6, 0x96, 0x09)
+
+/* Section Types */
+#define INTEL_CPER_SECTION_ACCEL_GENERIC \
+	GUID_INIT(0xea9d8f84, 0x4258, 0x5227, \
+		  0x80, 0x28, 0xb9, 0xb1, 0x3e, 0x6d, 0x58, 0xb0)
+
+#pragma pack(push, 1)
+
+/**
+ * struct xe_cper_sec_intel_err_hdr - Intel-specific CPER error section header
+ *
+ * Fixed-size header for the Intel GPU error section of a CPER record.
+ * All multi-byte fields are little-endian; the structure is packed.
+ */
+struct xe_cper_sec_intel_err_hdr {
+	/** @error_class: Error classification (type, component, location, cause) */
+	union {
+		struct {
+			/** @error_class.error_type: RAS error severity */
+			u8  error_type;
+			/** @error_class.error_component: IP block that raised the error */
+			u8  error_component;
+			/** @error_class.tile: Tile number */
+			u8  tile;
+			/** @error_class.instance: Instance within the tile */
+			u32 instance;
+			/** @error_class.cause: Error cause code */
+			u32 cause;
+			/** @error_class.reserved: Reserved, must be zero */
+			u8  reserved;
+		} error_class;
+		/** @class: Raw byte view of the error class */
+		u8 class[12];
+	};
+	/** @first_timestamp: Timestamp of the first occurrence of this error class */
+	u64 first_timestamp;
+	/** @sig_id: Aggregated error class SIG ID; set to U32_MAX if unknown */
+	u32 sig_id;
+	/** @error_count: Number of times this error has been observed */
+	u32 error_count;
+	/** @valid_bits: Bitmask indicating which header fields are populated */
+	union {
+		struct {
+			/** @valid_bits.location: @error_class field is valid */
+			u16 location		: 1;
+			/** @valid_bits.first_timestamp: @first_timestamp field is valid */
+			u16 first_timestamp	: 1;
+			/** @valid_bits.sig_id: @sig_id field is valid */
+			u16 sig_id			: 1;
+			/** @valid_bits.pci_bdf: @pci_bdf field is valid */
+			u16 pci_bdf		: 1;
+			/** @valid_bits.drv_version: @drv_version field is valid */
+			u16 drv_version		: 1;
+			/** @valid_bits.fw_id: @fw_id field is valid */
+			u16 fw_id			: 1;
+			/** @valid_bits.reserved: Reserved, must be zero */
+			u16 reserved		: 10;
+		} valid_bits;
+		/** @validation_bits: Raw u16 view of all valid bits */
+		u16 validation_bits;
+	};
+	/** @pci_bdf: PCI location string, format "DDDD:bb:dd.f" */
+	char pci_bdf[16];
+	/** @drv_version: Driver source version string (THIS_MODULE->srcversion) */
+	char drv_version[25];
+	/** @fw_id: Firmware version string (GFSP+PCODE+CSC+GUC or MNG+NUC+RAS+GUC) */
+	char fw_id[256];
+	/** @reserved: Reserved for future use, must be zero */
+	u8 reserved[5];
+};
+
+/**
+ * struct xe_cper_sec_intel_error_info - Variable-length Intel GPU error payload
+ *
+ * Appended after &xe_cper_sec_intel_err_hdr when detailed per-event data
+ * is available. The @event_queue flexible array holds @event_queue_count
+ * packed &xe_intel_priv_event_entry records.
+ */
+struct xe_cper_sec_intel_error_info {
+	/** @error_class: Error classification (mirrors the header error_class) */
+	union {
+		struct {
+			u8  error_type;
+			u8  error_component;
+			u8  tile;
+			u32 instance;
+			u32 cause;
+			u8  reserved;
+		} error_class;
+		/** @class: Raw byte view of the error class */
+		u8 class[12];
+	};
+	/** @error_count: Total number of errors recorded */
+	u32 error_count;
+	/** @event_queue_length: Total byte size of the @event_queue array */
+	u32 event_queue_length;
+	/** @event_queue_count: Number of entries in @event_queue */
+	u32 event_queue_count;
+	/** @event_queue: Packed array of &xe_intel_priv_event_entry records */
+	u8 event_queue[];
+};
+
+/**
+ * struct xe_intel_priv_event_entry - Single error event in the event queue
+ *
+ * Each entry is variable-length; @entry_length gives the byte size of
+ * @metadata only (not including @entry_length or @timestamp).
+ */
+struct xe_intel_priv_event_entry {
+	/** @entry_length: Byte length of the @metadata payload */
+	u32 entry_length;
+	/** @timestamp: Hardware timestamp of this event */
+	u64 timestamp;
+	/** @metadata: Event-specific payload bytes */
+	u8  metadata[];
+};
+
+/**
+ * struct xe_cper_nonstd_record - Fixed-size portion of an Intel GPU CPER record
+ *
+ * Contains the standard CPER record header, section descriptor, and the
+ * Intel error section header. A &xe_cper_sec_intel_error_info payload
+ * (with its flexible @event_queue array) is appended dynamically.
+ */
+struct xe_cper_nonstd_record {
+	/** @record_hdr: Standard CPER record header (UEFI Appendix N.2.1) */
+	struct cper_record_header record_hdr;
+	/** @section_desc: CPER section descriptor */
+	struct cper_section_descriptor section_desc;
+	/** @intel_hdr: Intel-specific error section header */
+	struct xe_cper_sec_intel_err_hdr intel_hdr;
+};
+
+#pragma pack(pop)
+
+/**
+ * struct xe_platform_id_entry - Mapping from PCI device ID to CPER platform GUID
+ *
+ * Used to resolve the platform_id field in a CPER section descriptor.
+ * GUIDs are UUIDv5 (RFC 9562, SHA-1) derived from the Intel CPER namespace
+ * with name string "platform/8086:<dev_id_hex_lower>".
+ */
+struct xe_platform_id_entry {
+	/** @device_id: PCI device ID */
+	u16       device_id;
+	/** @platform_id: Corresponding UUIDv5 platform GUID */
+	guid_t    platform_id;
+};
+
+#endif
diff --git a/drivers/gpu/drm/xe/xe_trace_cper.c b/drivers/gpu/drm/xe/xe_trace_cper.c
new file mode 100644
index 000000000000..caea8783ab7c
--- /dev/null
+++ b/drivers/gpu/drm/xe/xe_trace_cper.c
@@ -0,0 +1,9 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Copyright © 2026 Intel Corporation
+ */
+
+#ifndef __CHECKER__
+#define CREATE_TRACE_POINTS
+#include "xe_trace_cper.h"
+#endif
diff --git a/drivers/gpu/drm/xe/xe_trace_cper.h b/drivers/gpu/drm/xe/xe_trace_cper.h
new file mode 100644
index 000000000000..6d2dbf504888
--- /dev/null
+++ b/drivers/gpu/drm/xe/xe_trace_cper.h
@@ -0,0 +1,66 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/*
+ * Copyright © 2026 Intel Corporation
+ */
+
+#undef TRACE_SYSTEM
+#define TRACE_SYSTEM xe
+
+#if !defined(_XE_TRACE_CPER_H_) || defined(TRACE_HEADER_MULTI_READ)
+#define _XE_TRACE_CPER_H_
+
+#include <linux/tracepoint.h>
+#include <linux/types.h>
+
+#include "xe_cper_types.h"
+#include "xe_device_types.h"
+
+#define __dev_name_xe(xe)	dev_name((xe)->drm.dev)
+
+TRACE_EVENT(xe_error_cper,
+	TP_PROTO(struct xe_device *xe,
+	    const guid_t *platform_id, const guid_t *fru_id,
+	    const u8 severity,
+	    const struct xe_cper_sec_intel_err_hdr *ihdr,
+	    u32 cper_len, const u8 *cper),
+	TP_ARGS(xe, platform_id, fru_id, severity, ihdr, cper_len, cper),
+
+	TP_STRUCT__entry(
+	    __string(dev, __dev_name_xe(xe))
+	    __array(char, platform_id, UUID_SIZE)
+	    __array(char, fru_id, UUID_SIZE)
+	    __field(u8, sev)
+	    __array(u8, ihdr_raw, sizeof(struct xe_cper_sec_intel_err_hdr))
+	    __field(u32, cper_len)
+	    __dynamic_array(u8, cper, cper_len)
+	    ),
+
+	TP_fast_assign(
+	    __assign_str(dev);
+	    __entry->sev = severity;
+	    memcpy(__entry->platform_id, platform_id, UUID_SIZE);
+	    memcpy(__entry->fru_id, fru_id, UUID_SIZE);
+	    memcpy(__entry->ihdr_raw, ihdr, sizeof(struct xe_cper_sec_intel_err_hdr));
+	    __entry->cper_len = cper_len;
+	    memcpy(__get_dynamic_array(cper), cper, cper_len);
+	    ),
+
+	TP_printk("dev=%s severity=%d platform_id=%pU fru_id=%pU "
+		"intel_err_hdr_raw=%s cper_len=%u cper_raw=%s",
+		__get_str(dev), __entry->sev,
+		__entry->platform_id, __entry->fru_id,
+		__print_hex(__entry->ihdr_raw,
+		    sizeof(struct xe_cper_sec_intel_err_hdr)),
+		__entry->cper_len,
+		__print_hex(__get_dynamic_array(cper),
+		    __entry->cper_len))
+);
+
+#endif
+
+/* This part must be outside protection */
+#undef TRACE_INCLUDE_PATH
+#undef TRACE_INCLUDE_FILE
+#define TRACE_INCLUDE_PATH ../../drivers/gpu/drm/xe
+#define TRACE_INCLUDE_FILE xe_trace_cper
+#include <trace/define_trace.h>
-- 
2.54.0

[PATCH v2 04/11] drm/xe/cper: APIs to prepare and log CPER record

[Badal Nilawar]

Add APIs to initialize Intel-specific CPER metadata, build a
non-standard CPER record, and emit it via the xe_error_cper tracepoint.

Signed-off-by: Badal Nilawar <badal.nilawar@intel.com>
Assisted-by: Copilot:claude-sonnet-4.6
---
 drivers/gpu/drm/xe/Makefile       |   5 +-
 drivers/gpu/drm/xe/regs/xe_regs.h |   2 +
 drivers/gpu/drm/xe/xe_cper.c      | 184 ++++++++++++++++++++++++++++++
 drivers/gpu/drm/xe/xe_cper.h      |  34 ++++++
 4 files changed, 224 insertions(+), 1 deletion(-)
 create mode 100644 drivers/gpu/drm/xe/xe_cper.c
 create mode 100644 drivers/gpu/drm/xe/xe_cper.h

diff --git a/drivers/gpu/drm/xe/Makefile b/drivers/gpu/drm/xe/Makefile
index 3ed60697f3f3..c7d13bb090a6 100644
--- a/drivers/gpu/drm/xe/Makefile
+++ b/drivers/gpu/drm/xe/Makefile
@@ -136,7 +136,6 @@ xe-y += xe_bb.o \
 	xe_tlb_inval_job.o \
 	xe_trace.o \
 	xe_trace_bo.o \
-	xe_trace_cper.o \
 	xe_trace_guc.o \
 	xe_trace_lrc.o \
 	xe_ttm_stolen_mgr.o \
@@ -165,6 +164,10 @@ xe-$(CONFIG_HWMON) += xe_hwmon.o
 xe-$(CONFIG_PERF_EVENTS) += xe_pmu.o
 xe-$(CONFIG_CONFIGFS_FS) += xe_configfs.o
 
+xe-$(CONFIG_UEFI_CPER_X86) += \
+			xe_cper.o \
+			xe_trace_cper.o
+
 # graphics virtualization (SR-IOV) support
 xe-y += \
 	xe_gt_sriov_vf.o \
diff --git a/drivers/gpu/drm/xe/regs/xe_regs.h b/drivers/gpu/drm/xe/regs/xe_regs.h
index ef4746b7b5d3..580c3dad858a 100644
--- a/drivers/gpu/drm/xe/regs/xe_regs.h
+++ b/drivers/gpu/drm/xe/regs/xe_regs.h
@@ -30,6 +30,8 @@
 #define XEHP_MTCFG_ADDR				XE_REG(0x101800)
 #define   TILE_COUNT				REG_GENMASK(15, 8)
 
+#define CRI_FRU_ID				XE_REG(0x102008)
+
 #define GGC					XE_REG(0x108040)
 #define   GMS_MASK				REG_GENMASK(15, 8)
 #define   GGMS_MASK				REG_GENMASK(7, 6)
diff --git a/drivers/gpu/drm/xe/xe_cper.c b/drivers/gpu/drm/xe/xe_cper.c
new file mode 100644
index 000000000000..371537052de3
--- /dev/null
+++ b/drivers/gpu/drm/xe/xe_cper.c
@@ -0,0 +1,184 @@
+// SPDX-License-Identifier: MIT
+/*
+ * Copyright © 2026 Intel Corporation
+ */
+
+#include <linux/cper.h>
+#include <linux/ktime.h>
+#include <linux/module.h>
+#include <linux/pci.h>
+#include <linux/slab.h>
+#include <linux/string.h>
+
+#include <drm/drm_print.h>
+
+#include "regs/xe_regs.h"
+#include "xe_cper.h"
+#include "xe_cper_types.h"
+#include "xe_device.h"
+#include "xe_device_types.h"
+#include "xe_mmio.h"
+#include "xe_ras_types.h"
+#include "xe_trace_cper.h"
+
+static const struct xe_platform_id_entry xe_platform_ids[] = {
+	/* 0x674C  platform/8086:674c */
+	{ 0x674C, GUID_INIT(0x9046afe5, 0x9041, 0x5124,
+			    0x86, 0x14, 0x92, 0x55, 0x0d, 0x9e, 0x9d, 0xa6) },
+};
+
+static const guid_t *lookup_platform_id(const struct pci_dev *pdev)
+{
+	int i;
+
+	for (i = 0; i < ARRAY_SIZE(xe_platform_ids); i++)
+		if (xe_platform_ids[i].device_id == pdev->device)
+			return &xe_platform_ids[i].platform_id;
+	return NULL;
+}
+
+static guid_t read_fru_id(struct xe_device *xe)
+{
+	struct xe_mmio *mmio = xe_root_tile_mmio(xe);
+	guid_t guid = GUID_INIT(0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0);
+	u64 val;
+
+	val = xe_mmio_read64_2x32(mmio, CRI_FRU_ID);
+
+	memcpy(&guid, &val, sizeof(val));
+
+	return guid;
+}
+
+static void fill_fw_id(struct xe_device *xe, struct xe_cper_sec_intel_err_hdr *ihdr)
+{
+	/* TODO: populate ihdr->fw_id from firmware version queries */
+}
+
+/**
+ * xe_cper_init_intel_err_hdr - Populate an Intel CPER section header
+ * @xe: xe device instance
+ * @location: 12-byte error classification blob (cast from the source
+ *            error class struct); pass %NULL if not applicable
+ * @first_timestamp: timestamp of the first occurrence; pass 0 if not available
+ * @sig_id: signal identifier for the error; pass %U32_MAX if not applicable
+ * @error_count: number of times this error has occurred
+ * @ihdr: Intel section header to populate
+ *
+ * Fills in @ihdr with the provided error metadata and sets the corresponding
+ * valid bits.
+ */
+void xe_cper_init_intel_err_hdr(struct xe_device *xe, const u8 location[12],
+				u64 first_timestamp, u32 sig_id,
+				u32 error_count, struct xe_cper_sec_intel_err_hdr *ihdr)
+{
+	if (location) {
+		memcpy(&ihdr->error_class, location, sizeof(ihdr->error_class));
+		ihdr->valid_bits.location = 1;
+	}
+
+	if (first_timestamp) {
+		ihdr->first_timestamp = first_timestamp;
+		ihdr->valid_bits.first_timestamp = 1;
+	}
+
+	if (sig_id != U32_MAX) {
+		ihdr->sig_id = sig_id;
+		ihdr->valid_bits.sig_id = 1;
+	}
+
+	ihdr->error_count = error_count;
+
+	strscpy(ihdr->pci_bdf, pci_name(to_pci_dev(xe->drm.dev)), sizeof(ihdr->pci_bdf));
+	ihdr->valid_bits.pci_bdf = 1;
+
+#ifdef MODULE
+	strscpy(ihdr->drv_version, THIS_MODULE->srcversion, sizeof(ihdr->drv_version));
+	ihdr->valid_bits.drv_version = 1;
+#else
+	ihdr->valid_bits.drv_version = 0;
+#endif
+
+	fill_fw_id(xe, ihdr);
+}
+
+/**
+ * xe_cper_record_emit - Build and emit a CPER record for an Intel GPU error
+ * @xe: xe device instance
+ * @notification_type: CPER notification type (INTEL_CPER_NOTIFY_*)
+ * @severity: CPER error severity (CPER_SEV_*)
+ * @ihdr: Intel-specific section header, fully populated by
+ *        xe_cper_init_intel_err_hdr()
+ * @einfo: optional xe_cper_sec_intel_error_info payload; may be %NULL
+ * @einfo_size: byte size of @einfo, including any event_queue data
+ *
+ * The platform_id is resolved automatically from xe_platform_ids[] using
+ * the PCI device ID.  If no entry matches, the field is left zeroed and
+ * the record is still emitted.
+ */
+void xe_cper_record_emit(struct xe_device *xe, u8 severity,
+			 guid_t *notification_type,
+			 struct xe_cper_sec_intel_err_hdr *ihdr,
+			 const void *einfo, u32 einfo_len)
+{
+	struct pci_dev *pdev = to_pci_dev(xe->drm.dev);
+	const guid_t *platform_id = lookup_platform_id(pdev);
+	u32 total_len = sizeof(struct xe_cper_nonstd_record) + einfo_len;
+	struct cper_section_descriptor *sdesc;
+	struct cper_record_header *rhdr;
+	struct xe_cper_nonstd_record *rec;
+
+	rec = kzalloc(total_len, GFP_KERNEL);
+	if (!rec)
+		return;
+
+	rhdr  = &rec->record_hdr;
+	sdesc = &rec->section_desc;
+
+	/* Assemble the CPER record header (UEFI Appendix N.2.1) */
+	memcpy(rhdr->signature, CPER_SIG_RECORD, CPER_SIG_SIZE);
+	rhdr->revision          = CPER_RECORD_REV;
+	rhdr->signature_end     = CPER_SIG_END;
+	rhdr->section_count     = 1;
+	rhdr->error_severity    = severity;
+	rhdr->validation_bits   = CPER_VALID_TIMESTAMP;
+	rhdr->record_length     = total_len;
+	rhdr->timestamp         = ktime_get_real_seconds();
+	if (platform_id) {
+		rhdr->platform_id      = *platform_id;
+		rhdr->validation_bits |= CPER_VALID_PLATFORM_ID;
+	}
+	rhdr->creator_id        = INTEL_CPER_CREATOR_XEKMD;
+	rhdr->notification_type = *notification_type;
+	rhdr->record_id         = cper_next_record_id();
+	rhdr->flags             = 0;
+
+	/* Assemble the section descriptor (UEFI Appendix N.2.2) */
+	sdesc->section_offset   = sizeof(struct cper_record_header) +
+				  sizeof(struct cper_section_descriptor);
+	sdesc->section_length   = sizeof(struct xe_cper_sec_intel_err_hdr) + einfo_len;
+	sdesc->revision         = CPER_RECORD_REV;
+	/*
+	 * Set validation_bits using CPER_SEC_VALID_FRU_ID / CPER_SEC_VALID_FRU_TEXT
+	 * when the corresponding fields are populated.
+	 */
+	sdesc->validation_bits  = 0;
+	sdesc->reserved         = 0;
+	sdesc->flags            = 0;
+	sdesc->section_type     = INTEL_CPER_SECTION_ACCEL_GENERIC;
+	sdesc->fru_id = read_fru_id(xe);
+	sdesc->validation_bits |= CPER_SEC_VALID_FRU_ID;
+	sdesc->section_severity = severity;
+
+	/* Copy the Intel-specific section header (updated with BDF/version) */
+	rec->intel_hdr = *ihdr;
+
+	/* Append optional variable-length error info */
+	if (einfo && einfo_len)
+		memcpy((u8 *)rec + sizeof(*rec), einfo, einfo_len);
+
+	trace_xe_error_cper(xe, &rhdr->platform_id, &sdesc->fru_id, severity,
+			    &rec->intel_hdr, total_len, (u8 *)rec);
+
+	kfree(rec);
+}
diff --git a/drivers/gpu/drm/xe/xe_cper.h b/drivers/gpu/drm/xe/xe_cper.h
new file mode 100644
index 000000000000..4d852a487b65
--- /dev/null
+++ b/drivers/gpu/drm/xe/xe_cper.h
@@ -0,0 +1,34 @@
+/* SPDX-License-Identifier: MIT */
+/*
+ * Copyright © 2026 Intel Corporation
+ */
+
+#ifndef _XE_CPER_H_
+#define _XE_CPER_H_
+
+#include <linux/types.h>
+#include <linux/uuid.h>
+
+struct xe_cper_sec_intel_err_hdr;
+struct xe_device;
+
+#if IS_REACHABLE(CONFIG_UEFI_CPER_X86)
+void xe_cper_record_emit(struct xe_device *xe, u8 severity,
+			 guid_t *notification_type,
+			 struct xe_cper_sec_intel_err_hdr *ihdr,
+			 const void *einfo, u32 einfo_size);
+
+void xe_cper_init_intel_err_hdr(struct xe_device *xe, const u8 location[12],
+				u64 first_timestamp, u32 sig_id, u32 error_count,
+				struct xe_cper_sec_intel_err_hdr *ihdr);
+#else
+static inline void xe_cper_record_emit(struct xe_device *xe, u8 severity,
+				       guid_t *notification_type,
+				       struct xe_cper_sec_intel_err_hdr *ihdr,
+				       const void *einfo, u32 einfo_size) {}
+
+static inline void xe_cper_init_intel_err_hdr(struct xe_device *xe, const u8 location[12],
+					      u64 first_timestamp, u32 sig_id, u32 error_count,
+					      struct xe_cper_sec_intel_err_hdr *ihdr) {}
+#endif
+#endif /* _XE_CPER_H_ */
-- 
2.54.0

[PATCH v2 05/11] drm/xe/cper: Prepare Intel CPER error info from info queue

[Badal Nilawar]

Add prepare_cper_error_info() to xe_ras.c which assembles the raw info
queue data embedded in a GET_COUNTER response (and any subsequent chunks
fetched via GET_INFO_QUEUE_DATA) into a xe_cper_sec_intel_error_info
that can be passed directly to cper logging function.

Signed-off-by: Badal Nilawar <badal.nilawar@intel.com>
Assisted-by: Copilot:claude-sonnet-4.6
---
 drivers/gpu/drm/xe/xe_ras.c | 278 ++++++++++++++++++++++++++++++++++++
 1 file changed, 278 insertions(+)

diff --git a/drivers/gpu/drm/xe/xe_ras.c b/drivers/gpu/drm/xe/xe_ras.c
index e913235e9cce..27c78800b5d2 100644
--- a/drivers/gpu/drm/xe/xe_ras.c
+++ b/drivers/gpu/drm/xe/xe_ras.c
@@ -3,8 +3,11 @@
  * Copyright © 2026 Intel Corporation
  */
 
+#include "xe_cper.h"
+#include "xe_cper_types.h"
 #include "xe_debugfs.h"
 #include "xe_device.h"
+#include "xe_device_types.h"
 #include "xe_drm_ras.h"
 #include "xe_log.h"
 #include "xe_pm.h"
@@ -471,6 +474,281 @@ static int get_counter(struct xe_device *xe, struct xe_ras_error_class *counter,
 	return 0;
 }
 
+static int get_info_queue_data(struct xe_device *xe,
+			       const struct xe_ras_get_info_queue_data_request *req,
+			       struct xe_ras_get_info_queue_data_response *out);
+
+/**
+ * struct xe_cper_einfo_entry - One CPER error-info buffer with its byte size
+ * @hdr: dynamic-counter header carrying the per-entry error_class and counter
+ *       value; used by the caller to build a dedicated xe_cper_sec_intel_err_hdr
+ *       for each CPER record
+ * @einfo: allocated error-info payload (caller must kfree)
+ * @einfo_size: byte size of @einfo including any event_queue data
+ * @timestamp: timestamp of first occurrence of dynamic-counter
+ */
+struct xe_cper_einfo_entry {
+	struct xe_ras_info_queue_dynamic_counter_hdr hdr;
+	struct xe_cper_sec_intel_error_info *einfo;
+	u32 einfo_size;
+	u64 timestamp;
+};
+
+/**
+ * prepare_cper_error_info - Assemble info queue chunks and convert to CPER einfo
+ * @xe: xe device instance
+ * @counter_resp: counter response containing the first embedded chunk
+ * @error_class: RAS error class used to populate the einfo error_class fields
+ * @einfo_size_out: output size of the allocated einfo buffer
+ *
+ * Assembles the complete raw info queue data from the first chunk already
+ * embedded in @counter_resp and any additional chunks fetched via
+ * GET_INFO_QUEUE_DATA.  Two use cases are supported based on num_headers in
+ * the info queue header:
+ *
+ * Detail error counter (num_headers == 0)::
+ *
+ *   [xe_ras_error_log * N]
+ *
+ *   Returns one xe_cper_einfo_entry covering all N logs.
+ *
+ * Aggregate error counter (num_headers > 0)::
+ *
+ *   [xe_ras_info_queue_dynamic_counter_hdr * num_headers]
+ *   [xe_ras_error_log * N]
+ *
+ *   Returns one xe_cper_einfo_entry per header.  Each header's @counter field
+ *   gives the number of consecutive xe_ras_error_log entries belonging to it
+ *   and its @error_class is used to populate the entry's einfo->error_class.
+ *
+ * Returns: allocated xe_cper_einfo_entry array on success (caller must kfree
+ *          each entry's einfo then kfree the array), NULL on failure.
+ *          @count_out is set to the number of entries in the array.
+ */
+static struct xe_cper_einfo_entry *
+prepare_cper_error_info(struct xe_device *xe,
+			const struct xe_ras_get_counter_response *counter_resp,
+			const struct xe_ras_error_class *error_class,
+			u32 *count_out)
+{
+	const struct xe_ras_info_queue_header *first_qhdr =
+		&counter_resp->info_queue.queue_header;
+	struct xe_ras_get_info_queue_data_request iq_req = {0};
+	struct xe_ras_get_info_queue_data_response iq_response = {0};
+	struct xe_cper_einfo_entry *einfo_arr;
+	u32 num_headers, headers_size;
+	u32 raw_total, iq_offset = 0;
+	u32 entry_size;
+	u8 *raw_buf;
+	u32 i;
+
+	raw_buf = kzalloc(XE_RAS_INFO_QUEUE_MAX_TOTAL_SIZE, GFP_KERNEL);
+	if (!raw_buf)
+		return NULL;
+
+	/* Copy first chunk already embedded in the counter response */
+	if (first_qhdr->chunk_size &&
+	    first_qhdr->chunk_offset + first_qhdr->chunk_size <=
+	    XE_RAS_INFO_QUEUE_MAX_TOTAL_SIZE) {
+		memcpy(raw_buf + first_qhdr->chunk_offset,
+		       counter_resp->info_queue.queue_data,
+		       first_qhdr->chunk_size);
+		iq_offset = first_qhdr->chunk_size;
+	}
+
+	/* Fetch any remaining chunks */
+	if (first_qhdr->flags & XE_RAS_INFO_QUEUE_FLAG_MORE_DATA) {
+		iq_req.source_command			= XE_SYSCTRL_CMD_GET_COUNTER;
+		iq_req.source_context			= counter_resp->counter;
+		iq_req.queue_request.requested_size	= XE_RAS_INFO_QUEUE_MAX_CHUNK_SIZE;
+		iq_req.queue_request.session_id		= counter_resp->counter;
+
+		do {
+			struct xe_ras_info_queue_header *qhdr;
+			u32 end;
+
+			iq_req.queue_request.requested_offset = iq_offset;
+
+			if (get_info_queue_data(xe, &iq_req, &iq_response))
+				break;
+
+			qhdr = &iq_response.queue_response.queue_header;
+			end  = qhdr->chunk_offset + qhdr->chunk_size;
+
+			if (end > XE_RAS_INFO_QUEUE_MAX_TOTAL_SIZE) {
+				xe_warn(xe, "[RAS]: CPER: info queue chunk out of bounds (offset=%u size=%u)\n",
+					qhdr->chunk_offset, qhdr->chunk_size);
+				break;
+			}
+
+			memcpy(raw_buf + qhdr->chunk_offset,
+			       iq_response.queue_response.queue_data,
+			       qhdr->chunk_size);
+
+			if (!qhdr->chunk_size)
+				break;
+
+			iq_offset += qhdr->chunk_size;
+		} while (iq_response.queue_response.queue_header.flags &
+			 XE_RAS_INFO_QUEUE_FLAG_MORE_DATA);
+	}
+
+	raw_total = first_qhdr->total_size
+		  ? min(first_qhdr->total_size, XE_RAS_INFO_QUEUE_MAX_TOTAL_SIZE)
+		  : iq_offset;
+
+	num_headers  = first_qhdr->num_headers;
+	headers_size = num_headers * sizeof(struct xe_ras_info_queue_dynamic_counter_hdr);
+
+	if (headers_size > raw_total) {
+		xe_warn(xe, "[RAS]: CPER: aggregate headers size (%u) exceeds raw total (%u)\n",
+			headers_size, raw_total);
+		kfree(raw_buf);
+		return NULL;
+	}
+
+	/*
+	 * entry_size is constant for every xe_intel_priv_event_entry:
+	 *   entry_length (u32) + timestamp (u64) + metadata[] (error_details)
+	 */
+	entry_size = offsetof(struct xe_intel_priv_event_entry, metadata) +
+		     sizeof_field(struct xe_ras_error_log, error_details);
+
+	if (num_headers == 0) {
+		/* Detail case: single einfo covering all log entries */
+		u32 num_logs = raw_total / sizeof(struct xe_ras_error_log);
+		struct xe_cper_sec_intel_error_info *einfo;
+		struct xe_intel_priv_event_entry *entry;
+		const struct xe_ras_error_log *logs;
+		u32 einfo_size;
+
+		if (!num_logs) {
+			kfree(raw_buf);
+			return NULL;
+		}
+
+		einfo_arr = kzalloc(sizeof(*einfo_arr), GFP_KERNEL);
+		if (!einfo_arr) {
+			kfree(raw_buf);
+			return NULL;
+		}
+
+		einfo_size = sizeof(*einfo) + num_logs * entry_size;
+		einfo = kzalloc(einfo_size, GFP_KERNEL);
+		if (!einfo) {
+			kfree(einfo_arr);
+			kfree(raw_buf);
+			return NULL;
+		}
+
+		einfo->error_count        = counter_resp->value;
+		einfo->event_queue_length = num_logs * entry_size;
+		einfo->event_queue_count  = num_logs;
+		einfo->error_class.error_type		= error_class->common.severity;
+		einfo->error_class.error_component	= error_class->common.component;
+		einfo->error_class.tile			= error_class->product.unit.tile;
+		einfo->error_class.instance		= error_class->product.unit.instance;
+		einfo->error_class.cause		= error_class->product.cause.cause;
+
+		logs  = (const struct xe_ras_error_log *)raw_buf;
+		entry = (struct xe_intel_priv_event_entry *)einfo->event_queue;
+
+		for (i = 0; i < num_logs; i++) {
+			entry->entry_length = sizeof_field(struct xe_ras_error_log, error_details);
+			entry->timestamp    = logs[i].timestamp;
+			memcpy(entry->metadata, logs[i].error_details,
+			       sizeof(logs[i].error_details));
+			entry = (struct xe_intel_priv_event_entry *)((u8 *)entry + entry_size);
+		}
+
+		einfo_arr[0].hdr.error_class = *error_class;
+		einfo_arr[0].hdr.counter     = counter_resp->value;
+		einfo_arr[0].einfo           = einfo;
+		einfo_arr[0].einfo_size      = einfo_size;
+		einfo_arr[0].timestamp       = logs[0].timestamp;
+		*count_out = 1;
+
+	} else {
+		/* Aggregate case: one einfo per dynamic-counter header */
+		const struct xe_ras_info_queue_dynamic_counter_hdr *hdrs =
+			(const struct xe_ras_info_queue_dynamic_counter_hdr *)raw_buf;
+		const struct xe_ras_error_log *all_logs =
+			(const struct xe_ras_error_log *)(raw_buf + headers_size);
+		u32 avail_logs = (raw_total - headers_size) / sizeof(struct xe_ras_error_log);
+		u32 log_offset = 0;
+
+		einfo_arr = kzalloc_objs(*einfo_arr, num_headers, GFP_KERNEL);
+		if (!einfo_arr) {
+			kfree(raw_buf);
+			return NULL;
+		}
+
+		for (i = 0; i < num_headers; i++) {
+			u32 num_logs = min_t(u32, hdrs[i].counter, XE_RAS_NUM_COUNTERS);
+			struct xe_cper_sec_intel_error_info *einfo;
+			struct xe_intel_priv_event_entry *entry;
+			u32 einfo_size;
+			u32 j;
+
+			if (log_offset + num_logs > avail_logs) {
+				xe_warn(xe, "[RAS]: CPER: header[%u] claims %u logs but only %u remain\n",
+					i, num_logs, avail_logs - log_offset);
+				break;
+			}
+
+			if (!num_logs) {
+				log_offset += num_logs;
+				continue;
+			}
+
+			einfo_size = sizeof(*einfo) + num_logs * entry_size;
+			einfo = kzalloc(einfo_size, GFP_KERNEL);
+			if (!einfo) {
+				u32 k;
+
+				for (k = 0; k < i; k++)
+					kfree(einfo_arr[k].einfo);
+				kfree(einfo_arr);
+				kfree(raw_buf);
+				return NULL;
+			}
+
+			einfo->error_count		= num_logs;
+			einfo->event_queue_length	= num_logs * entry_size;
+			einfo->event_queue_count	= num_logs;
+			einfo->error_class.error_type	= hdrs[i].error_class.common.severity;
+			einfo->error_class.tile		= hdrs[i].error_class.product.unit.tile;
+			einfo->error_class.instance	= hdrs[i].error_class.product.unit.instance;
+			einfo->error_class.cause	= hdrs[i].error_class.product.cause.cause;
+			einfo->error_class.error_component = hdrs[i].error_class.common.component;
+
+			entry = (struct xe_intel_priv_event_entry *)einfo->event_queue;
+			for (j = 0; j < num_logs; j++) {
+				const struct xe_ras_error_log *log = &all_logs[log_offset + j];
+
+				entry->entry_length = sizeof_field(struct xe_ras_error_log, error_details);
+				entry->timestamp    = log->timestamp;
+				memcpy(entry->metadata, log->error_details,
+				       sizeof(log->error_details));
+				entry = (struct xe_intel_priv_event_entry *)((u8 *)entry + entry_size);
+
+				if (j == 0)
+					einfo_arr[i].timestamp  = log->timestamp;
+			}
+
+			einfo_arr[i].hdr        = hdrs[i];
+			einfo_arr[i].einfo      = einfo;
+			einfo_arr[i].einfo_size = einfo_size;
+			log_offset += num_logs;
+		}
+
+		*count_out = i;
+	}
+
+	kfree(raw_buf);
+	return einfo_arr;
+}
+
 /**
  * xe_ras_process_errors() - Process and contain hardware errors
  * @xe: xe device instance
-- 
2.54.0

[PATCH v2 06/11] drm/xe/cper: Log CPER records for aggregate counter retrival

[Badal Nilawar]

Log CPER records for aggregate counter retrieval from userspace.

Signed-off-by: Badal Nilawar <badal.nilawar@intel.com>
---
 drivers/gpu/drm/xe/xe_ras.c | 92 +++++++++++++++++++++++++++++++++++++
 1 file changed, 92 insertions(+)

diff --git a/drivers/gpu/drm/xe/xe_ras.c b/drivers/gpu/drm/xe/xe_ras.c
index 27c78800b5d2..ff9d917b8e29 100644
--- a/drivers/gpu/drm/xe/xe_ras.c
+++ b/drivers/gpu/drm/xe/xe_ras.c
@@ -204,6 +204,34 @@ static inline const char *comp_to_str(u8 component)
 	return xe_ras_components[component];
 }
 
+static u32 ras_comp_to_hw_sigid(u8 component)
+{
+	switch (component) {
+	case XE_RAS_COMP_DEVICE_MEMORY:
+		return XE_SIGID_DEVICE_MEMORY;
+	case XE_RAS_COMP_CORE_COMPUTE:
+		return XE_SIGID_CORE_COMPUTE;
+	case XE_RAS_COMP_PCIE:
+		return XE_SIGID_PCIE;
+	case XE_RAS_COMP_FABRIC:
+		return XE_SIGID_FABRIC;
+	case XE_RAS_COMP_SOC_INTERNAL:
+		return XE_SIGID_SOC_INTERNAL;
+	default:
+		return U32_MAX;
+	}
+}
+
+static u8 ras_sev_to_cper_sev(u8 ras_sev)
+{
+	switch (ras_sev) {
+	case XE_RAS_SEV_CORRECTABLE:   return CPER_SEV_CORRECTED;     /* 2 */
+	case XE_RAS_SEV_UNCORRECTABLE: return CPER_SEV_RECOVERABLE;   /* 0 */
+	case XE_RAS_SEV_INFORMATIONAL: return CPER_SEV_INFORMATIONAL; /* 3 */
+	default:                       return CPER_SEV_RECOVERABLE;
+	}
+}
+
 static bool ras_counter_is_valid(struct xe_device *xe, struct xe_ras_error_class *counter)
 {
 	u8 severity = counter->common.severity;
@@ -749,6 +777,66 @@ prepare_cper_error_info(struct xe_device *xe,
 	return einfo_arr;
 }
 
+static void emit_hw_error_cper(struct xe_device *xe,
+			       struct xe_ras_error_class *error_class,
+			       struct xe_ras_get_counter_response *resp,
+			       u32 sig_id, u8 severity)
+{
+	struct xe_ras_get_counter_response local_resp = {};
+	struct xe_ras_get_counter_response *counter_response = resp;
+	struct xe_cper_sec_intel_err_hdr ihdr = {};
+	struct xe_cper_einfo_entry *einfo_arr = NULL;
+	u32 einfo_count = 0;
+	u32 i;
+
+	if (!counter_response) {
+		counter_response = &local_resp;
+		if (get_counter(xe, error_class, counter_response)) {
+			xe_err(xe, "[RAS]: CPER: failed to get counter, skipping record\n");
+			return;
+		}
+	}
+
+	if (counter_response->has_info_queue) {
+		einfo_arr = prepare_cper_error_info(xe, counter_response,
+						    error_class, &einfo_count);
+		if (!einfo_arr)
+			xe_err(xe, "[RAS]: CPER: failed to build einfo from info queue\n");
+	}
+
+	if (einfo_count > 0) {
+		for (i = 0; i < einfo_count; i++) {
+			struct xe_cper_sec_intel_err_hdr entry_ihdr = {};
+
+			xe_cper_init_intel_err_hdr(xe,
+						   (const u8 *)&einfo_arr[i].hdr.error_class,
+						   einfo_arr[i].timestamp,
+						   sig_id,
+						   einfo_arr[i].hdr.counter,
+						   &entry_ihdr);
+
+			xe_cper_record_emit(xe, severity, &INTEL_CPER_NOTIFY_GPU_ERROR,
+					    &entry_ihdr, einfo_arr[i].einfo,
+					    einfo_arr[i].einfo_size);
+		}
+	} else {
+		xe_cper_init_intel_err_hdr(xe,
+					   (const u8 *)error_class,
+					   counter_response->timestamp,
+					   sig_id,
+					   counter_response->value,
+					   &ihdr);
+		xe_cper_record_emit(xe, severity, &INTEL_CPER_NOTIFY_GPU_ERROR,
+				    &ihdr, NULL, 0);
+	}
+
+	if (einfo_arr) {
+		for (i = 0; i < einfo_count; i++)
+			kfree(einfo_arr[i].einfo);
+		kfree(einfo_arr);
+	}
+}
+
 /**
  * xe_ras_process_errors() - Process and contain hardware errors
  * @xe: xe device instance
@@ -886,6 +974,10 @@ int xe_ras_get_counter(struct xe_device *xe, u8 severity, u8 component, u32 *val
 		return ret;
 
 	*value = response.value;
+
+	emit_hw_error_cper(xe, &counter, &response,
+			   ras_comp_to_hw_sigid(counter.common.component),
+			   ras_sev_to_cper_sev(counter.common.severity));
 	return 0;
 }
 
-- 
2.54.0

[PATCH v2 07/11] drm/xe/cper: Allow hardware error CPER reporting from xe_log

[Badal Nilawar]

Add xe_emit_hardware_error_cper() as a public wrapper around the
internal hardware CPER emission helper, enabling xe_log.c to emit
hardware error CPER records.

Signed-off-by: Badal Nilawar <badal.nilawar@intel.com>
---
 drivers/gpu/drm/xe/xe_log.c | 17 +++++++++++------
 drivers/gpu/drm/xe/xe_ras.c | 23 +++++++++++++++++++++++
 drivers/gpu/drm/xe/xe_ras.h |  4 ++++
 3 files changed, 38 insertions(+), 6 deletions(-)

diff --git a/drivers/gpu/drm/xe/xe_log.c b/drivers/gpu/drm/xe/xe_log.c
index 5549ef6966fd..c78fc195c55b 100644
--- a/drivers/gpu/drm/xe/xe_log.c
+++ b/drivers/gpu/drm/xe/xe_log.c
@@ -10,15 +10,25 @@
 
 #include "xe_device.h"
 #include "xe_log.h"
+#include "xe_ras.h"
 #include "xe_printk.h"
 
+static bool is_hw_sigid(enum xe_sigid sigid)
+{
+	return (int)sigid >= INTEL_SIGID_GPU_XE_HARDWARE_START;
+}
+
 static void log_emit_cper(struct pci_dev *pdev, int cper_sev, enum xe_sigid sigid,
 			  u32 component, u32 location, const void *data, size_t len,
 			  struct va_format *vaf)
 {
 	KUNIT_STATIC_STUB_REDIRECT(log_emit_cper, pdev, cper_sev, sigid,
 				   component, location, data, len, vaf);
-	/* TODO */
+	/* TODO software CPER */
+
+	if (is_hw_sigid(sigid))
+		xe_emit_hardware_error_cper(pdev, cper_sev, sigid,
+					    (struct xe_ras_error_class *)data);
 }
 
 static const char *log_unknown_component_prefix(u32 component)
@@ -100,11 +110,6 @@ static const char *log_location_prefix(struct pci_dev *pdev, u32 location, char
 	return buf;
 }
 
-static bool is_hw_sigid(enum xe_sigid sigid)
-{
-	return (int)sigid >= INTEL_SIGID_GPU_XE_HARDWARE_START;
-}
-
 static bool is_sev_error(int cper_sev)
 {
 	return cper_sev != CPER_SEV_INFORMATIONAL;
diff --git a/drivers/gpu/drm/xe/xe_ras.c b/drivers/gpu/drm/xe/xe_ras.c
index ff9d917b8e29..b4cdb5ec6491 100644
--- a/drivers/gpu/drm/xe/xe_ras.c
+++ b/drivers/gpu/drm/xe/xe_ras.c
@@ -837,6 +837,29 @@ static void emit_hw_error_cper(struct xe_device *xe,
 	}
 }
 
+/**
+ * xe_emit_hardware_error_cper() - Emit a hardware error CPER record
+ * @pdev: PCI device associated with the Xe device
+ * @cper_sev: CPER severity
+ * @sigid: Error signature identifier
+ * @error_class: Hardware error classification details
+ *
+ * Emit a CPER record for a hardware error
+ */
+void xe_emit_hardware_error_cper(struct pci_dev *pdev, int cper_sev, enum xe_sigid sigid,
+				 struct xe_ras_error_class *counter)
+{
+	struct xe_device *xe = pdev_to_xe_device(pdev);
+
+	if (!xe)
+		return;
+
+	if (counter && !ras_counter_is_valid(xe, counter))
+		return;
+
+	emit_hw_error_cper(xe, counter, NULL, sigid, cper_sev);
+}
+
 /**
  * xe_ras_process_errors() - Process and contain hardware errors
  * @xe: xe device instance
diff --git a/drivers/gpu/drm/xe/xe_ras.h b/drivers/gpu/drm/xe/xe_ras.h
index 618364734043..e5c4b2e2e1fd 100644
--- a/drivers/gpu/drm/xe/xe_ras.h
+++ b/drivers/gpu/drm/xe/xe_ras.h
@@ -7,6 +7,8 @@
 #define _XE_RAS_H_
 
 #include <linux/types.h>
+#include "abi/xe_sigid_abi.h"
+#include "xe_device.h"
 #include "xe_ras_types.h"
 
 struct xe_device;
@@ -18,5 +20,7 @@ int xe_ras_get_counter(struct xe_device *xe, u8 severity, u8 component, u32 *val
 int xe_ras_clear_counter(struct xe_device *xe, u8 severity, u8 component);
 void xe_ras_init(struct xe_device *xe);
 enum xe_ras_recovery_action xe_ras_process_errors(struct xe_device *xe);
+void xe_emit_hardware_error_cper(struct pci_dev *pdev, int cper_sev, enum xe_sigid sigid,
+				 struct xe_ras_error_class *error_class);
 
 #endif
-- 
2.54.0

[PATCH v2 08/11] drm/xe/ras: Report device memory errors using SIGID

[Badal Nilawar]

Use xe_log_comp_info helper to report device memory errors.

Signed-off-by: Badal Nilawar <badal.nilawar@intel.com>
Cc: Riana Tauro <riana.tauro@intel.com>
---
 drivers/gpu/drm/xe/xe_ras.c | 11 +++++++----
 1 file changed, 7 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/xe/xe_ras.c b/drivers/gpu/drm/xe/xe_ras.c
index b4cdb5ec6491..172653be1b82 100644
--- a/drivers/gpu/drm/xe/xe_ras.c
+++ b/drivers/gpu/drm/xe/xe_ras.c
@@ -409,14 +409,17 @@ static u8 handle_device_memory_errors(struct xe_device *xe, struct xe_ras_error_
 	 */
 	switch (info->category) {
 	case XE_RAS_MEMORY_POISON:
-		xe_info(xe, "[RAS]: Poison error detected\n");
+		xe_log_comp_info(xe, DEVICE_MEMORY, &arr->counter, sizeof(arr->counter),
+				 "Poison error detected\n");
 		break;
 	case XE_RAS_MEMORY_DATA_PARITY:
-		xe_info(xe, "[RAS]: Data parity error detected\n");
+		xe_log_comp_info(xe, DEVICE_MEMORY, &arr->counter, sizeof(arr->counter),
+				 "Data parity error detected\n");
 		break;
 	case XE_RAS_MEMORY_DB_ECC:
-		xe_info(xe, "[RAS]: Double-bit ECC error detected at sw address 0x%llx\n",
-			info->sw_address);
+		xe_log_comp_info(xe, DEVICE_MEMORY, &arr->counter, sizeof(arr->counter),
+				 "Double-bit ECC error detected at sw address 0x%llx\n",
+				 info->sw_address);
 		/* TODO: Add page offlining for Double-bit ECC error */
 		fallthrough;
 	default:
-- 
2.54.0

[PATCH v2 09/11] drm/xe/ras: Report core compute errors using SIGID

[Badal Nilawar]

Use xe_log_* helpers to report core compute errors.

Signed-off-by: Badal Nilawar <badal.nilawar@intel.com>
Cc: Riana Tauro <riana.tauro@intel.com>
---
 drivers/gpu/drm/xe/xe_ras.c | 11 ++++++++---
 1 file changed, 8 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/xe/xe_ras.c b/drivers/gpu/drm/xe/xe_ras.c
index 172653be1b82..3b43d363d5de 100644
--- a/drivers/gpu/drm/xe/xe_ras.c
+++ b/drivers/gpu/drm/xe/xe_ras.c
@@ -332,7 +332,7 @@ static void ras_send_error_event(struct xe_device *xe, u8 severity, u8 component
 	xe_drm_ras_event(xe, drm_component, drm_severity, response.value);
 }
 
-static u8 handle_core_compute_errors(struct xe_ras_error_array *arr)
+static u8 handle_core_compute_errors(struct xe_device *xe, struct xe_ras_error_array *arr)
 {
 	struct xe_ras_compute_error *error_info = (void *)arr->details;
 	u8 uncorr_type;
@@ -340,13 +340,18 @@ static u8 handle_core_compute_errors(struct xe_ras_error_array *arr)
 	uncorr_type = FIELD_GET(CORE_COMPUTE_UNCORR_TYPE, error_info->log_header);
 
 	/* Request a reset if error is global */
-	if (uncorr_type == GLOBAL_UNCORR_ERROR)
+	if (uncorr_type == GLOBAL_UNCORR_ERROR) {
+		xe_log_comp_recoverable(xe, CORE_COMPUTE, &arr->counter, sizeof(arr->counter),
+					"Global uncorrectable error detected\n");
 		return XE_RAS_RECOVERY_ACTION_RESET;
+	}
 
 	/*
 	 * No action needed for other errors.
 	 * Local errors are recovered using an engine reset by GuC.
 	 */
+	xe_log_comp_recoverable(xe, CORE_COMPUTE, &arr->counter, sizeof(arr->counter),
+				"Other compute errors\n");
 	return XE_RAS_RECOVERY_ACTION_RECOVERED;
 }
 
@@ -940,7 +945,7 @@ enum xe_ras_recovery_action xe_ras_process_errors(struct xe_device *xe)
 
 			switch (component) {
 			case XE_RAS_COMP_CORE_COMPUTE:
-				action = handle_core_compute_errors(arr);
+				action = handle_core_compute_errors(xe, arr);
 				break;
 			case XE_RAS_COMP_SOC_INTERNAL:
 				action = handle_soc_internal_errors(xe, arr);
-- 
2.54.0

[PATCH v2 10/11] drm/xe/ras: Report soc internal errors using SIGID

[Badal Nilawar]

Use xe_log_* helpers to report soc internal errors.

Signed-off-by: Badal Nilawar <badal.nilawar@intel.com>
Cc: Riana Tauro <riana.tauro@intel.com>
---
 drivers/gpu/drm/xe/xe_ras.c | 14 ++++++--------
 1 file changed, 6 insertions(+), 8 deletions(-)

diff --git a/drivers/gpu/drm/xe/xe_ras.c b/drivers/gpu/drm/xe/xe_ras.c
index 3b43d363d5de..4cd1d5eb75f4 100644
--- a/drivers/gpu/drm/xe/xe_ras.c
+++ b/drivers/gpu/drm/xe/xe_ras.c
@@ -365,7 +365,6 @@ static u8 handle_soc_internal_errors(struct xe_device *xe, struct xe_ras_error_a
 {
 	struct xe_ras_soc_error *info = (void *)arr->details;
 	struct xe_ras_soc_error_source *source = &info->source;
-	struct xe_ras_error_class *counter = &arr->counter;
 
 	if (source->csc) {
 		struct xe_ras_csc_error *csc_error = (void *)info->details;
@@ -379,19 +378,18 @@ static u8 handle_soc_internal_errors(struct xe_device *xe, struct xe_ras_error_a
 		 * is required.
 		 */
 		if (csc_error->hec_fw_error) {
-			xe_err(xe, "[RAS]: CSC %s detected: 0x%x\n",
-			       sev_to_str(counter->common.severity),
-			       csc_error->hec_fw_error);
-			xe_survivability_mode_runtime_enable(xe);
+			xe_log_comp_fatal(xe, SOC_INTERNAL, &arr->counter, sizeof(arr->counter),
+					  "CSC error detected: 0x%x\n", csc_error->hec_fw_error);
+		xe_survivability_mode_runtime_enable(xe);
 			return XE_RAS_RECOVERY_ACTION_DISCONNECT;
 		}
 	} else if (source->ieh) {
 		struct xe_ras_ieh_error *ieh_error = (void *)info->details;
 
 		if (ieh_error->global_error_status & XE_RAS_SOC_IEH_PUNIT) {
-			xe_err(xe, "[RAS]: PUNIT %s detected: 0x%x\n",
-			       sev_to_str(counter->common.severity),
-			       ieh_error->global_error_status);
+			xe_log_comp_fatal(xe, SOC_INTERNAL, &arr->counter, sizeof(arr->counter),
+					  "PUNIT error detected: 0x%x\n",
+					  ieh_error->global_error_status);
 			punit_error_handler(xe);
 			return XE_RAS_RECOVERY_ACTION_DISCONNECT;
 		}
-- 
2.54.0

[PATCH v2 11/11] drm/xe/ras: Report correctable errors using SIGID

[Badal Nilawar]

Use xe_log_* helper to report correctable errors.

Signed-off-by: Badal Nilawar <badal.nilawar@intel.com>
Cc: Raag Jadav <raag.jadav@intel.com>
---
 drivers/gpu/drm/xe/xe_ras.c | 7 +++++--
 1 file changed, 5 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/xe/xe_ras.c b/drivers/gpu/drm/xe/xe_ras.c
index 4cd1d5eb75f4..0becfadbb4cd 100644
--- a/drivers/gpu/drm/xe/xe_ras.c
+++ b/drivers/gpu/drm/xe/xe_ras.c
@@ -458,8 +458,11 @@ void xe_ras_counter_threshold_crossed(struct xe_device *xe,
 		if (!ras_counter_is_valid(xe, &errors[id]))
 			continue;
 
-		xe_warn(xe, "[RAS]: %s %s detected\n",
-			comp_to_str(component), sev_to_str(severity));
+		xe_log_from(xe, ras_sev_to_cper_sev(severity),
+			    ras_comp_to_hw_sigid(component),
+			    component,
+			    &errors[id], sizeof(errors[id]),
+			    "error detected\n");
 
 		/* Send event once per component */
 		if (sent & BIT(component))
-- 
2.54.0

Re: [PATCH v2 04/11] drm/xe/cper: APIs to prepare and log CPER record

[sashiko-bot]

Thank you for your contribution! Sashiko AI review found 2 potential issue(s) to consider:
- [High] Unconditional dereference of potentially NULL `THIS_MODULE->srcversion` causes kernel panic.
- [Medium] Assigning `ktime_get_real_seconds()` to `rhdr->timestamp` violates the UEFI CPER standard, which requires a BCD timestamp.
--

commit 1a8a9f568395a2ce2ede1bcececcf688f5a25b63
Author: Badal Nilawar <badal.nilawar@intel.com>

drm/xe/cper: APIs to prepare and log CPER record

Add APIs to initialize Intel-specific CPER metadata, build a non-standard
CPER record, and emit it via the xe_error_cper tracepoint.

> diff --git a/drivers/gpu/drm/xe/xe_cper.c b/drivers/gpu/drm/xe/xe_cper.c
> new file mode 100644
> index 0000000000000..371537052de35
> --- /dev/null
> +++ b/drivers/gpu/drm/xe/xe_cper.c
[ ... ]
> +void xe_cper_init_intel_err_hdr(struct xe_device *xe, const u8 location[12],
> +				u64 first_timestamp, u32 sig_id,
> +				u32 error_count, struct xe_cper_sec_intel_err_hdr *ihdr)
> +{
[ ... ]
> +	strscpy(ihdr->pci_bdf, pci_name(to_pci_dev(xe->drm.dev)), sizeof(ihdr->pci_bdf));
> +	ihdr->valid_bits.pci_bdf = 1;
> +
> +#ifdef MODULE
> +	strscpy(ihdr->drv_version, THIS_MODULE->srcversion, sizeof(ihdr->drv_version));

[Severity: High]
Can this cause a kernel panic if the module's source version is not populated?

When the kernel is compiled without CONFIG_MODULE_SRCVERSION_ALL and the
module lacks an explicit MODULE_VERSION macro, the build system does not
generate the srcversion modinfo attribute. In this case,
THIS_MODULE->srcversion is left as NULL during module load.

Since strscpy() does not handle NULL source pointers gracefully, this
unconditional dereference of THIS_MODULE->srcversion in
xe_cper_init_intel_err_hdr() could lead to a kernel panic when hardware
error reporting is triggered.

> +	ihdr->valid_bits.drv_version = 1;
> +#else
> +	ihdr->valid_bits.drv_version = 0;
> +#endif
> +
> +	fill_fw_id(xe, ihdr);
> +}
[ ... ]
> +void xe_cper_record_emit(struct xe_device *xe, u8 severity,
> +			 guid_t *notification_type,
> +			 struct xe_cper_sec_intel_err_hdr *ihdr,
> +			 const void *einfo, u32 einfo_len)
> +{
[ ... ]
> +	/* Assemble the CPER record header (UEFI Appendix N.2.1) */
> +	memcpy(rhdr->signature, CPER_SIG_RECORD, CPER_SIG_SIZE);
> +	rhdr->revision          = CPER_RECORD_REV;
> +	rhdr->signature_end     = CPER_SIG_END;
> +	rhdr->section_count     = 1;
> +	rhdr->error_severity    = severity;
> +	rhdr->validation_bits   = CPER_VALID_TIMESTAMP;
> +	rhdr->record_length     = total_len;
> +	rhdr->timestamp         = ktime_get_real_seconds();

[Severity: Medium]
Does this assign a raw binary Unix timestamp to a field that requires a BCD
format?

ktime_get_real_seconds() returns a 64-bit binary integer representing
seconds since the Unix epoch. However, the UEFI standard (UEFI 2.8+
Appendix N.2.1) mandates that the timestamp field in a struct
cper_record_header is a 64-bit BCD-encoded date and time value (Century,
Year, Month, Day, Hours, Minutes, Seconds).

Assigning a raw binary Unix timestamp to rhdr->timestamp in
xe_cper_record_emit() could cause standard CPER parsers to read invalid
BCD characters or absurd dates.

> +	if (platform_id) {
> +		rhdr->platform_id      = *platform_id;
> +		rhdr->validation_bits |= CPER_VALID_PLATFORM_ID;
> +	}
[ ... ]

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20260825175916.1103841-13-badal.nilawar@intel.com?part=4

Re: [PATCH v2 11/11] drm/xe/ras: Report correctable errors using SIGID

[sashiko-bot]

Thank you for your contribution! Sashiko AI review found 2 potential issue(s) to consider:
- [Medium] Passing raw `enum xe_ras_component` to `xe_log_from()` instead of a properly constructed `enum xe_log_component`, causing incorrect logging format and kernel warnings.
- [Medium] Unmapped `XE_RAS_COMP_RESERVED` causes `U32_MAX` to be passed as a default SIGID, breaking the stable signature ID tracking scheme by logging `SIGID=4294967295`.
--

commit 9b392e724340e7b28bbb985e627346fd4f036a93
Author: Badal Nilawar <badal.nilawar@intel.com>

drm/xe/ras: Report correctable errors using SIGID

This commit replaces the xe_warn() call for correctable errors with the
xe_log_from() helper to report them using SIGID format.

> diff --git a/drivers/gpu/drm/xe/xe_ras.c b/drivers/gpu/drm/xe/xe_ras.c
> index 4cd1d5eb75f4d..0becfadbb4cdf 100644
> --- a/drivers/gpu/drm/xe/xe_ras.c
> +++ b/drivers/gpu/drm/xe/xe_ras.c
> @@ -458,8 +458,11 @@ void xe_ras_counter_threshold_crossed(struct xe_device *xe,
>  		if (!ras_counter_is_valid(xe, &errors[id]))
>  			continue;
>  
> -		xe_warn(xe, "[RAS]: %s %s detected\n",
> -			comp_to_str(component), sev_to_str(severity));
> +		xe_log_from(xe, ras_sev_to_cper_sev(severity),
> +			    ras_comp_to_hw_sigid(component),

[Severity: Medium]
Will this leak U32_MAX as a SIGID to the logging infrastructure?

If ras_counter_is_valid() allows XE_RAS_COMP_RESERVED (3) to proceed,
ras_comp_to_hw_sigid() hits the default case and returns U32_MAX.

U32_MAX is then passed as the sigid to xe_log_from(), and __xe_log_emit()
blindly formats the sigid using %u, logging "SIGID=4294967295". 
Does this break the stable, machine-matchable token format?

> +			    component,

[Severity: Medium]
Does this pass an invalid component type to xe_log_from()?

xe_log_from() expects its component parameter to be a constructed 
enum xe_log_component (via MAKE_XE_LOG_COMPONENT), where the lower byte is
class and the upper byte is type.

Passing the raw enum xe_ras_component directly causes it to be misinterpreted
as CLASS=1 and TYPE=0. This triggers log_unknown_component_prefix() to be
invoked, printing a corrupted "DRIVER? " prefix and triggering a kernel WARN
on every RAS event if CONFIG_DRM_XE_DEBUG is enabled.

> +			    &errors[id], sizeof(errors[id]),
> +			    "error detected\n");
>  
>  		/* Send event once per component */
>  		if (sent & BIT(component))

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20260825175916.1103841-13-badal.nilawar@intel.com?part=11

✗ CI.checkpatch: warning for Add CPER logging support for CRI (rev2)

[Patchwork]

== Series Details ==

Series: Add CPER logging support for CRI (rev2)
URL   : https://patchwork.freedesktop.org/series/169692/
State : warning

== Summary ==

+ KERNEL=/kernel
+ git clone https://gitlab.freedesktop.org/drm/maintainer-tools mt
Cloning into 'mt'...
warning: redirecting to https://gitlab.freedesktop.org/drm/maintainer-tools.git/
+ git -C mt rev-list -n1 origin/master
061140b9bc586ae7f40abc1249c97e1cc72d1b9d
+ cd /kernel
+ git config --global --add safe.directory /kernel
+ git log -n1
commit 2cb1cd991d2fee7e0a84b6d82c49210a8eb2f99e
Author: Badal Nilawar <badal.nilawar@intel.com>
Date:   Tue Aug 25 23:29:28 2026 +0530

    drm/xe/ras: Report correctable errors using SIGID
    
    Use xe_log_* helper to report correctable errors.
    
    Signed-off-by: Badal Nilawar <badal.nilawar@intel.com>
    Cc: Raag Jadav <raag.jadav@intel.com>
+ /mt/dim checkpatch 15e2ba2fb6d25c03d89519aec46f8d5be3e118ad drm-intel
57eafc44f9c1 drm/xe/xe_ras: Add support to retrieve info queue data for CRI
1cc6d987513b drm/xe/xe_ras: Refactor get_counter() to return response structure
84da341781ad drm/xe/cper: Add CPER structures and trace event
-:28: WARNING:FILE_PATH_CHANGES: added, moved or deleted file(s), does MAINTAINERS need updating?
#28: 
new file mode 100644

-:260: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#260: FILE: drivers/gpu/drm/xe/xe_trace_cper.h:21:
+TRACE_EVENT(xe_error_cper,
+	TP_PROTO(struct xe_device *xe,

-:261: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#261: FILE: drivers/gpu/drm/xe/xe_trace_cper.h:22:
+	TP_PROTO(struct xe_device *xe,
+	    const guid_t *platform_id, const guid_t *fru_id,

-:267: CHECK:OPEN_ENDED_LINE: Lines should not end with a '('
#267: FILE: drivers/gpu/drm/xe/xe_trace_cper.h:28:
+	TP_STRUCT__entry(

-:277: CHECK:OPEN_ENDED_LINE: Lines should not end with a '('
#277: FILE: drivers/gpu/drm/xe/xe_trace_cper.h:38:
+	TP_fast_assign(

-:292: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#292: FILE: drivers/gpu/drm/xe/xe_trace_cper.h:53:
+		__print_hex(__entry->ihdr_raw,
+		    sizeof(struct xe_cper_sec_intel_err_hdr)),

-:295: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#295: FILE: drivers/gpu/drm/xe/xe_trace_cper.h:56:
+		__print_hex(__get_dynamic_array(cper),
+		    __entry->cper_len))

-:303: CHECK:SPACING: spaces preferred around that '/' (ctx:VxV)
#303: FILE: drivers/gpu/drm/xe/xe_trace_cper.h:64:
+#define TRACE_INCLUDE_PATH ../../drivers/gpu/drm/xe
                              ^

-:303: CHECK:SPACING: spaces preferred around that '/' (ctx:VxV)
#303: FILE: drivers/gpu/drm/xe/xe_trace_cper.h:64:
+#define TRACE_INCLUDE_PATH ../../drivers/gpu/drm/xe
                                 ^

-:303: CHECK:SPACING: spaces preferred around that '/' (ctx:VxV)
#303: FILE: drivers/gpu/drm/xe/xe_trace_cper.h:64:
+#define TRACE_INCLUDE_PATH ../../drivers/gpu/drm/xe
                                         ^

-:303: CHECK:SPACING: spaces preferred around that '/' (ctx:VxV)
#303: FILE: drivers/gpu/drm/xe/xe_trace_cper.h:64:
+#define TRACE_INCLUDE_PATH ../../drivers/gpu/drm/xe
                                             ^

-:303: CHECK:SPACING: spaces preferred around that '/' (ctx:VxV)
#303: FILE: drivers/gpu/drm/xe/xe_trace_cper.h:64:
+#define TRACE_INCLUDE_PATH ../../drivers/gpu/drm/xe
                                                 ^

total: 0 errors, 1 warnings, 11 checks, 268 lines checked
50f1aa0aefdb drm/xe/cper: APIs to prepare and log CPER record
-:49: WARNING:FILE_PATH_CHANGES: added, moved or deleted file(s), does MAINTAINERS need updating?
#49: 
new file mode 100644

total: 0 errors, 1 warnings, 0 checks, 243 lines checked
368f568b8e10 drm/xe/cper: Prepare Intel CPER error info from info queue
-:286: WARNING:LONG_LINE: line length of 107 exceeds 100 columns
#286: FILE: drivers/gpu/drm/xe/xe_ras.c:729:
+				entry->entry_length = sizeof_field(struct xe_ras_error_log, error_details);

-:290: WARNING:LONG_LINE: line length of 103 exceeds 100 columns
#290: FILE: drivers/gpu/drm/xe/xe_ras.c:733:
+				entry = (struct xe_intel_priv_event_entry *)((u8 *)entry + entry_size);

total: 0 errors, 2 warnings, 0 checks, 292 lines checked
c6639bee4921 drm/xe/cper: Log CPER records for aggregate counter retrival
7951327c0fb6 drm/xe/cper: Allow hardware error CPER reporting from xe_log
c50455a77607 drm/xe/ras: Report device memory errors using SIGID
3fd5dd02e180 drm/xe/ras: Report core compute errors using SIGID
80221b625246 drm/xe/ras: Report soc internal errors using SIGID
2cb1cd991d2f drm/xe/ras: Report correctable errors using SIGID

✓ CI.KUnit: success for Add CPER logging support for CRI (rev2)

[Patchwork]

== Series Details ==

Series: Add CPER logging support for CRI (rev2)
URL   : https://patchwork.freedesktop.org/series/169692/
State : success

== Summary ==

+ trap cleanup EXIT
+ /kernel/tools/testing/kunit/kunit.py run --kunitconfig /kernel/drivers/gpu/drm/xe/.kunitconfig
[18:29:31] Configuring KUnit Kernel ...
Generating .config ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
[18:29:35] Building KUnit Kernel ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
Building with:
$ make all compile_commands.json scripts_gdb ARCH=um O=.kunit --jobs=48
[18:30:08] Starting KUnit Kernel (1/1)...
[18:30:08] ============================================================
Running tests with:
$ .kunit/linux kunit.enable=1 mem=1G console=tty kunit_shutdown=halt
[18:30:08] ================== guc_buf (11 subtests) ===================
[18:30:08] [PASSED] test_smallest
[18:30:08] [PASSED] test_largest
[18:30:08] [PASSED] test_granular
[18:30:08] [PASSED] test_unique
[18:30:08] [PASSED] test_overlap
[18:30:08] [PASSED] test_reusable
[18:30:08] [PASSED] test_too_big
[18:30:08] [PASSED] test_flush
[18:30:08] [PASSED] test_lookup
[18:30:08] [PASSED] test_data
[18:30:08] [PASSED] test_class
[18:30:08] ===================== [PASSED] guc_buf =====================
[18:30:08] =================== guc_dbm (7 subtests) ===================
[18:30:08] [PASSED] test_empty
[18:30:08] [PASSED] test_default
[18:30:08] ======================== test_size  ========================
[18:30:08] [PASSED] 4
[18:30:08] [PASSED] 8
[18:30:08] [PASSED] 32
[18:30:08] [PASSED] 256
[18:30:08] ==================== [PASSED] test_size ====================
[18:30:08] ======================= test_reuse  ========================
[18:30:08] [PASSED] 4
[18:30:08] [PASSED] 8
[18:30:08] [PASSED] 32
[18:30:08] [PASSED] 256
[18:30:08] =================== [PASSED] test_reuse ====================
[18:30:08] =================== test_range_overlap  ====================
[18:30:08] [PASSED] 4
[18:30:08] [PASSED] 8
[18:30:08] [PASSED] 32
[18:30:08] [PASSED] 256
[18:30:08] =============== [PASSED] test_range_overlap ================
[18:30:08] =================== test_range_compact  ====================
[18:30:08] [PASSED] 4
[18:30:08] [PASSED] 8
[18:30:08] [PASSED] 32
[18:30:08] [PASSED] 256
[18:30:08] =============== [PASSED] test_range_compact ================
[18:30:08] ==================== test_range_spare  =====================
[18:30:08] [PASSED] 4
[18:30:08] [PASSED] 8
[18:30:08] [PASSED] 32
[18:30:08] [PASSED] 256
[18:30:08] ================ [PASSED] test_range_spare =================
[18:30:08] ===================== [PASSED] guc_dbm =====================
[18:30:08] =================== guc_idm (6 subtests) ===================
[18:30:08] [PASSED] bad_init
[18:30:08] [PASSED] no_init
[18:30:08] [PASSED] init_fini
[18:30:08] [PASSED] check_used
[18:30:08] [PASSED] check_quota
[18:30:08] [PASSED] check_all
[18:30:08] ===================== [PASSED] guc_idm =====================
[18:30:08] =============== guc_klv_helpers (9 subtests) ===============
[18:30:08] [PASSED] test_count
[18:30:08] [PASSED] test_encode_u32
[18:30:08] [PASSED] test_encode_u64
[18:30:08] [PASSED] test_encode_string
[18:30:08] [PASSED] test_encode_object_raw
[18:30:08] [PASSED] test_encode_object_klv
[18:30:08] [PASSED] test_encode_object_nested
[18:30:08] [PASSED] test_encode_object_basic
[18:30:08] [PASSED] test_print
[18:30:08] ================= [PASSED] guc_klv_helpers =================
[18:30:08] =================== xe_log (4 subtests) ====================
[18:30:08] [PASSED] demo_cper
[18:30:08] [PASSED] demo_dmesg
[18:30:08] ======================= test_dmesg  ========================
[18:30:08] [PASSED] test_fatal
[18:30:08] [PASSED] test_fatal_tile
[18:30:08] [PASSED] test_fatal_gt
[18:30:08] [PASSED] test_fatal_comp
[18:30:08] [PASSED] test_fatal_comp_tile
[18:30:08] [PASSED] test_fatal_comp_gt
[18:30:08] [PASSED] test_fatal_all
[18:30:08] [PASSED] test_recoverable
[18:30:08] [PASSED] test_recoverable_tile
[18:30:08] [PASSED] test_recoverable_gt
[18:30:08] [PASSED] test_recoverable_comp
[18:30:08] [PASSED] test_recoverable_comp_tile
[18:30:08] [PASSED] test_recoverable_comp_gt
[18:30:08] [PASSED] test_recoverable_all
[18:30:08] [PASSED] test_info
[18:30:08] [PASSED] test_info_tile
[18:30:08] [PASSED] test_info_gt
[18:30:08] [PASSED] test_info_err
[18:30:08] [PASSED] test_info_comp
[18:30:08] [PASSED] test_info_comp_tile
[18:30:08] [PASSED] test_info_comp_gt
[18:30:08] [PASSED] test_info_all
[18:30:08] [PASSED] test_hw_fatal
[18:30:08] [PASSED] test_hw_recoverable
[18:30:08] [PASSED] test_hw_corrected
[18:30:08] [PASSED] test_hw_informational
[18:30:08] =================== [PASSED] test_dmesg ====================
[18:30:08] ====================== test_invalid  =======================
[18:30:08] [SKIPPED] no-component no-location no-warn (requires CONFIG_DRM_XE_DEBUG)
[18:30:08] [SKIPPED] reserved location (requires CONFIG_DRM_XE_DEBUG)
[18:30:08] [SKIPPED] unknown location (requires CONFIG_DRM_XE_DEBUG)
[18:30:08] [SKIPPED] nonzero-device-id location (requires CONFIG_DRM_XE_DEBUG)
[18:30:08] [SKIPPED] invalid-tile-id location (requires CONFIG_DRM_XE_DEBUG)
[18:30:08] [SKIPPED] invalid-gt-id location (requires CONFIG_DRM_XE_DEBUG)
[18:30:08] [SKIPPED] unknown component class (requires CONFIG_DRM_XE_DEBUG)
[18:30:08] [SKIPPED] unknown system component (requires CONFIG_DRM_XE_DEBUG)
[18:30:08] [SKIPPED] unknown hardware component (requires CONFIG_DRM_XE_DEBUG)
[18:30:08] [SKIPPED] unknown component and location (requires CONFIG_DRM_XE_DEBUG)
[18:30:08] ================== [SKIPPED] test_invalid ==================
[18:30:08] ===================== [PASSED] xe_log ======================
[18:30:08] ================== no_relay (3 subtests) ===================
[18:30:08] [PASSED] xe_drops_guc2pf_if_not_ready
[18:30:08] [PASSED] xe_drops_guc2vf_if_not_ready
[18:30:08] [PASSED] xe_rejects_send_if_not_ready
[18:30:08] ==================== [PASSED] no_relay =====================
[18:30:08] ================== pf_relay (14 subtests) ==================
[18:30:08] [PASSED] pf_rejects_guc2pf_too_short
[18:30:08] [PASSED] pf_rejects_guc2pf_too_long
[18:30:08] [PASSED] pf_rejects_guc2pf_no_payload
[18:30:08] [PASSED] pf_fails_no_payload
[18:30:08] [PASSED] pf_fails_bad_origin
[18:30:08] [PASSED] pf_fails_bad_type
[18:30:08] [PASSED] pf_txn_reports_error
[18:30:08] [PASSED] pf_txn_sends_pf2guc
[18:30:08] [PASSED] pf_sends_pf2guc
[18:30:08] [SKIPPED] pf_loopback_nop (requires CONFIG_DRM_XE_DEBUG_SRIOV)
[18:30:08] [SKIPPED] pf_loopback_echo (requires CONFIG_DRM_XE_DEBUG_SRIOV)
[18:30:08] [SKIPPED] pf_loopback_fail (requires CONFIG_DRM_XE_DEBUG_SRIOV)
[18:30:08] [SKIPPED] pf_loopback_busy (requires CONFIG_DRM_XE_DEBUG_SRIOV)
[18:30:08] [SKIPPED] pf_loopback_retry (requires CONFIG_DRM_XE_DEBUG_SRIOV)
[18:30:08] ==================== [PASSED] pf_relay =====================
[18:30:08] ================== vf_relay (3 subtests) ===================
[18:30:08] [PASSED] vf_rejects_guc2vf_too_short
[18:30:08] [PASSED] vf_rejects_guc2vf_too_long
[18:30:08] [PASSED] vf_rejects_guc2vf_no_payload
[18:30:08] ==================== [PASSED] vf_relay =====================
[18:30:08] ================ pf_gt_config (9 subtests) =================
[18:30:08] [PASSED] fair_contexts_1vf
[18:30:08] [PASSED] fair_doorbells_1vf
[18:30:08] [PASSED] fair_ggtt_1vf
[18:30:08] ====================== fair_vram_1vf  ======================
[18:30:08] [PASSED] 3.50 GiB
[18:30:08] [PASSED] 11.5 GiB
[18:30:08] [PASSED] 15.5 GiB
[18:30:08] [PASSED] 31.5 GiB
[18:30:08] [PASSED] 63.5 GiB
[18:30:08] [PASSED] 1.91 GiB
[18:30:08] ================== [PASSED] fair_vram_1vf ==================
[18:30:08] ================ fair_vram_1vf_admin_only  =================
[18:30:08] [PASSED] 3.50 GiB
[18:30:08] [PASSED] 11.5 GiB
[18:30:08] [PASSED] 15.5 GiB
[18:30:08] [PASSED] 31.5 GiB
[18:30:08] [PASSED] 63.5 GiB
[18:30:08] [PASSED] 1.91 GiB
[18:30:08] ============ [PASSED] fair_vram_1vf_admin_only =============
[18:30:08] ====================== fair_contexts  ======================
[18:30:08] [PASSED] 1 VF
[18:30:08] [PASSED] 2 VFs
[18:30:08] [PASSED] 3 VFs
[18:30:08] [PASSED] 4 VFs
[18:30:08] [PASSED] 5 VFs
[18:30:08] [PASSED] 6 VFs
[18:30:08] [PASSED] 7 VFs
[18:30:08] [PASSED] 8 VFs
[18:30:08] [PASSED] 9 VFs
[18:30:08] [PASSED] 10 VFs
[18:30:08] [PASSED] 11 VFs
[18:30:08] [PASSED] 12 VFs
[18:30:08] [PASSED] 13 VFs
[18:30:08] [PASSED] 14 VFs
[18:30:08] [PASSED] 15 VFs
[18:30:08] [PASSED] 16 VFs
[18:30:08] [PASSED] 17 VFs
[18:30:08] [PASSED] 18 VFs
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[18:30:08] [PASSED] 21 VFs
[18:30:08] [PASSED] 22 VFs
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[18:30:08] [PASSED] 27 VFs
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[18:30:08] [PASSED] 33 VFs
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[18:30:08] [PASSED] 37 VFs
[18:30:08] [PASSED] 38 VFs
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[18:30:08] [PASSED] 40 VFs
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[18:30:08] [PASSED] 42 VFs
[18:30:08] [PASSED] 43 VFs
[18:30:08] [PASSED] 44 VFs
[18:30:08] [PASSED] 45 VFs
[18:30:08] [PASSED] 46 VFs
[18:30:08] [PASSED] 47 VFs
[18:30:08] [PASSED] 48 VFs
[18:30:08] [PASSED] 49 VFs
[18:30:08] [PASSED] 50 VFs
[18:30:08] [PASSED] 51 VFs
[18:30:08] [PASSED] 52 VFs
[18:30:08] [PASSED] 53 VFs
[18:30:08] [PASSED] 54 VFs
[18:30:08] [PASSED] 55 VFs
[18:30:08] [PASSED] 56 VFs
[18:30:08] [PASSED] 57 VFs
[18:30:08] [PASSED] 58 VFs
[18:30:08] [PASSED] 59 VFs
[18:30:08] [PASSED] 60 VFs
[18:30:08] [PASSED] 61 VFs
[18:30:08] [PASSED] 62 VFs
[18:30:08] [PASSED] 63 VFs
[18:30:08] ================== [PASSED] fair_contexts ==================
[18:30:08] ===================== fair_doorbells  ======================
[18:30:08] [PASSED] 1 VF
[18:30:08] [PASSED] 2 VFs
[18:30:08] [PASSED] 3 VFs
[18:30:08] [PASSED] 4 VFs
[18:30:08] [PASSED] 5 VFs
[18:30:08] [PASSED] 6 VFs
[18:30:08] [PASSED] 7 VFs
[18:30:08] [PASSED] 8 VFs
[18:30:08] [PASSED] 9 VFs
[18:30:08] [PASSED] 10 VFs
[18:30:08] [PASSED] 11 VFs
[18:30:08] [PASSED] 12 VFs
[18:30:08] [PASSED] 13 VFs
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[18:30:08] [PASSED] 15 VFs
[18:30:08] [PASSED] 16 VFs
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[18:30:08] [PASSED] 18 VFs
[18:30:08] [PASSED] 19 VFs
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[18:30:08] [PASSED] 27 VFs
[18:30:08] [PASSED] 28 VFs
[18:30:08] [PASSED] 29 VFs
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[18:30:08] [PASSED] 32 VFs
[18:30:08] [PASSED] 33 VFs
[18:30:08] [PASSED] 34 VFs
[18:30:08] [PASSED] 35 VFs
[18:30:08] [PASSED] 36 VFs
[18:30:08] [PASSED] 37 VFs
[18:30:08] [PASSED] 38 VFs
[18:30:08] [PASSED] 39 VFs
[18:30:08] [PASSED] 40 VFs
[18:30:08] [PASSED] 41 VFs
[18:30:08] [PASSED] 42 VFs
[18:30:08] [PASSED] 43 VFs
[18:30:08] [PASSED] 44 VFs
[18:30:08] [PASSED] 45 VFs
[18:30:08] [PASSED] 46 VFs
[18:30:08] [PASSED] 47 VFs
[18:30:08] [PASSED] 48 VFs
[18:30:08] [PASSED] 49 VFs
[18:30:08] [PASSED] 50 VFs
[18:30:08] [PASSED] 51 VFs
[18:30:08] [PASSED] 52 VFs
[18:30:08] [PASSED] 53 VFs
[18:30:08] [PASSED] 54 VFs
[18:30:08] [PASSED] 55 VFs
[18:30:08] [PASSED] 56 VFs
[18:30:08] [PASSED] 57 VFs
[18:30:08] [PASSED] 58 VFs
[18:30:08] [PASSED] 59 VFs
[18:30:08] [PASSED] 60 VFs
[18:30:08] [PASSED] 61 VFs
[18:30:08] [PASSED] 62 VFs
[18:30:08] [PASSED] 63 VFs
[18:30:08] ================= [PASSED] fair_doorbells ==================
[18:30:08] ======================== fair_ggtt  ========================
[18:30:08] [PASSED] 1 VF
[18:30:08] [PASSED] 2 VFs
[18:30:08] [PASSED] 3 VFs
[18:30:08] [PASSED] 4 VFs
[18:30:08] [PASSED] 5 VFs
[18:30:08] [PASSED] 6 VFs
[18:30:08] [PASSED] 7 VFs
[18:30:08] [PASSED] 8 VFs
[18:30:08] [PASSED] 9 VFs
[18:30:08] [PASSED] 10 VFs
[18:30:08] [PASSED] 11 VFs
[18:30:08] [PASSED] 12 VFs
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[18:30:08] [PASSED] 14 VFs
[18:30:08] [PASSED] 15 VFs
[18:30:08] [PASSED] 16 VFs
[18:30:08] [PASSED] 17 VFs
[18:30:08] [PASSED] 18 VFs
[18:30:08] [PASSED] 19 VFs
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[18:30:08] [PASSED] 21 VFs
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[18:30:08] [PASSED] 24 VFs
[18:30:08] [PASSED] 25 VFs
[18:30:08] [PASSED] 26 VFs
[18:30:08] [PASSED] 27 VFs
[18:30:08] [PASSED] 28 VFs
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[18:30:08] [PASSED] 30 VFs
[18:30:08] [PASSED] 31 VFs
[18:30:08] [PASSED] 32 VFs
[18:30:08] [PASSED] 33 VFs
[18:30:08] [PASSED] 34 VFs
[18:30:08] [PASSED] 35 VFs
[18:30:08] [PASSED] 36 VFs
[18:30:08] [PASSED] 37 VFs
[18:30:08] [PASSED] 38 VFs
[18:30:08] [PASSED] 39 VFs
[18:30:08] [PASSED] 40 VFs
[18:30:08] [PASSED] 41 VFs
[18:30:08] [PASSED] 42 VFs
[18:30:08] [PASSED] 43 VFs
[18:30:08] [PASSED] 44 VFs
[18:30:08] [PASSED] 45 VFs
[18:30:08] [PASSED] 46 VFs
[18:30:08] [PASSED] 47 VFs
[18:30:08] [PASSED] 48 VFs
[18:30:08] [PASSED] 49 VFs
[18:30:08] [PASSED] 50 VFs
[18:30:08] [PASSED] 51 VFs
[18:30:08] [PASSED] 52 VFs
[18:30:08] [PASSED] 53 VFs
[18:30:08] [PASSED] 54 VFs
[18:30:08] [PASSED] 55 VFs
[18:30:08] [PASSED] 56 VFs
[18:30:08] [PASSED] 57 VFs
[18:30:08] [PASSED] 58 VFs
[18:30:08] [PASSED] 59 VFs
[18:30:08] [PASSED] 60 VFs
[18:30:08] [PASSED] 61 VFs
[18:30:08] [PASSED] 62 VFs
[18:30:08] [PASSED] 63 VFs
[18:30:08] ==================== [PASSED] fair_ggtt ====================
[18:30:08] ======================== fair_vram  ========================
[18:30:08] [PASSED] 1 VF
[18:30:08] [PASSED] 2 VFs
[18:30:08] [PASSED] 3 VFs
[18:30:08] [PASSED] 4 VFs
[18:30:08] [PASSED] 5 VFs
[18:30:08] [PASSED] 6 VFs
[18:30:08] [PASSED] 7 VFs
[18:30:08] [PASSED] 8 VFs
[18:30:08] [PASSED] 9 VFs
[18:30:08] [PASSED] 10 VFs
[18:30:08] [PASSED] 11 VFs
[18:30:08] [PASSED] 12 VFs
[18:30:08] [PASSED] 13 VFs
[18:30:08] [PASSED] 14 VFs
[18:30:08] [PASSED] 15 VFs
[18:30:08] [PASSED] 16 VFs
[18:30:08] [PASSED] 17 VFs
[18:30:08] [PASSED] 18 VFs
[18:30:08] [PASSED] 19 VFs
[18:30:08] [PASSED] 20 VFs
[18:30:08] [PASSED] 21 VFs
[18:30:08] [PASSED] 22 VFs
[18:30:08] [PASSED] 23 VFs
[18:30:08] [PASSED] 24 VFs
[18:30:08] [PASSED] 25 VFs
[18:30:08] [PASSED] 26 VFs
[18:30:08] [PASSED] 27 VFs
[18:30:08] [PASSED] 28 VFs
[18:30:08] [PASSED] 29 VFs
[18:30:08] [PASSED] 30 VFs
[18:30:08] [PASSED] 31 VFs
[18:30:08] [PASSED] 32 VFs
[18:30:08] [PASSED] 33 VFs
[18:30:08] [PASSED] 34 VFs
[18:30:08] [PASSED] 35 VFs
[18:30:08] [PASSED] 36 VFs
[18:30:08] [PASSED] 37 VFs
[18:30:08] [PASSED] 38 VFs
[18:30:08] [PASSED] 39 VFs
[18:30:08] [PASSED] 40 VFs
[18:30:08] [PASSED] 41 VFs
[18:30:08] [PASSED] 42 VFs
[18:30:08] [PASSED] 43 VFs
[18:30:08] [PASSED] 44 VFs
[18:30:08] [PASSED] 45 VFs
[18:30:08] [PASSED] 46 VFs
[18:30:08] [PASSED] 47 VFs
[18:30:08] [PASSED] 48 VFs
[18:30:08] [PASSED] 49 VFs
[18:30:08] [PASSED] 50 VFs
[18:30:08] [PASSED] 51 VFs
[18:30:08] [PASSED] 52 VFs
[18:30:08] [PASSED] 53 VFs
[18:30:08] [PASSED] 54 VFs
[18:30:08] [PASSED] 55 VFs
[18:30:08] [PASSED] 56 VFs
[18:30:08] [PASSED] 57 VFs
[18:30:08] [PASSED] 58 VFs
[18:30:08] [PASSED] 59 VFs
[18:30:08] [PASSED] 60 VFs
[18:30:08] [PASSED] 61 VFs
[18:30:08] [PASSED] 62 VFs
[18:30:08] [PASSED] 63 VFs
[18:30:08] ==================== [PASSED] fair_vram ====================
[18:30:08] ================== [PASSED] pf_gt_config ===================
[18:30:08] ===================== lmtt (1 subtest) =====================
[18:30:08] ======================== test_ops  =========================
[18:30:08] [PASSED] 2-level
[18:30:08] [PASSED] multi-level
[18:30:08] ==================== [PASSED] test_ops =====================
[18:30:08] ====================== [PASSED] lmtt =======================
[18:30:08] ================= sriov_packet (1 subtest) =================
[18:30:08] [PASSED] test_descriptor_init
[18:30:08] ================== [PASSED] sriov_packet ===================
[18:30:08] ================= pf_service (11 subtests) =================
[18:30:08] [PASSED] pf_negotiate_any
[18:30:08] [PASSED] pf_negotiate_base_match
[18:30:08] [PASSED] pf_negotiate_base_newer
[18:30:08] [PASSED] pf_negotiate_base_next
[18:30:08] [SKIPPED] pf_negotiate_base_older (no older minor)
[18:30:08] [PASSED] pf_negotiate_base_prev
[18:30:08] [PASSED] pf_negotiate_latest_match
[18:30:08] [PASSED] pf_negotiate_latest_newer
[18:30:08] [PASSED] pf_negotiate_latest_next
[18:30:08] [SKIPPED] pf_negotiate_latest_older (no older minor)
[18:30:08] [SKIPPED] pf_negotiate_latest_prev (no prev major)
[18:30:08] =================== [PASSED] pf_service ====================
[18:30:08] ================= xe_guc_g2g (2 subtests) ==================
[18:30:08] ============== xe_live_guc_g2g_kunit_default  ==============
[18:30:08] ========= [SKIPPED] xe_live_guc_g2g_kunit_default ==========
[18:30:08] ============== xe_live_guc_g2g_kunit_allmem  ===============
[18:30:08] ========== [SKIPPED] xe_live_guc_g2g_kunit_allmem ==========
[18:30:08] =================== [SKIPPED] xe_guc_g2g ===================
[18:30:08] =================== xe_mocs (2 subtests) ===================
[18:30:08] ================ xe_live_mocs_kernel_kunit  ================
[18:30:08] =========== [SKIPPED] xe_live_mocs_kernel_kunit ============
[18:30:08] ================ xe_live_mocs_reset_kunit  =================
[18:30:08] ============ [SKIPPED] xe_live_mocs_reset_kunit ============
[18:30:08] ==================== [SKIPPED] xe_mocs =====================
[18:30:08] ================= xe_migrate (2 subtests) ==================
[18:30:08] ================= xe_migrate_sanity_kunit  =================
[18:30:08] ============ [SKIPPED] xe_migrate_sanity_kunit =============
[18:30:08] ================== xe_validate_ccs_kunit  ==================
[18:30:08] ============= [SKIPPED] xe_validate_ccs_kunit ==============
[18:30:08] =================== [SKIPPED] xe_migrate ===================
[18:30:08] ================== xe_dma_buf (1 subtest) ==================
[18:30:08] ==================== xe_dma_buf_kunit  =====================
[18:30:08] ================ [SKIPPED] xe_dma_buf_kunit ================
[18:30:08] =================== [SKIPPED] xe_dma_buf ===================
[18:30:08] ================= xe_bo_shrink (1 subtest) =================
[18:30:08] =================== xe_bo_shrink_kunit  ====================
[18:30:08] =============== [SKIPPED] xe_bo_shrink_kunit ===============
[18:30:08] ================== [SKIPPED] xe_bo_shrink ==================
[18:30:08] ==================== xe_bo (2 subtests) ====================
[18:30:08] ================== xe_ccs_migrate_kunit  ===================
[18:30:08] ============== [SKIPPED] xe_ccs_migrate_kunit ==============
[18:30:08] ==================== xe_bo_evict_kunit  ====================
[18:30:08] =============== [SKIPPED] xe_bo_evict_kunit ================
[18:30:08] ===================== [SKIPPED] xe_bo ======================
[18:30:08] =================== xe_any (9 subtests) ====================
[18:30:08] [PASSED] test_to_xe
[18:30:08] [PASSED] test_to_dev
[18:30:08] [PASSED] test_to_pdev
[18:30:08] [PASSED] test_to_drm
[18:30:08] [PASSED] test_if_pdev
[18:30:08] [PASSED] test_if_xe
[18:30:08] [PASSED] test_if_tile
[18:30:08] [PASSED] test_if_gt
[18:30:08] [PASSED] test_to_id
[18:30:08] ===================== [PASSED] xe_any ======================
[18:30:08] ==================== args (13 subtests) ====================
[18:30:08] [PASSED] count_args_test
[18:30:08] [PASSED] call_args_example
[18:30:08] [PASSED] call_args_test
[18:30:08] [PASSED] drop_first_arg_example
[18:30:08] [PASSED] drop_first_arg_test
[18:30:08] [PASSED] first_arg_example
[18:30:08] [PASSED] first_arg_test
[18:30:08] [PASSED] last_arg_example
[18:30:08] [PASSED] last_arg_test
[18:30:08] [PASSED] pick_arg_example
[18:30:08] [PASSED] if_args_example
[18:30:08] [PASSED] if_args_test
[18:30:08] [PASSED] sep_comma_example
[18:30:08] ====================== [PASSED] args =======================
[18:30:08] =================== xe_pci (3 subtests) ====================
[18:30:08] ==================== check_graphics_ip  ====================
[18:30:08] [PASSED] 12.00 Xe_LP
[18:30:08] [PASSED] 12.10 Xe_LP+
[18:30:08] [PASSED] 12.55 Xe_HPG
[18:30:08] [PASSED] 12.60 Xe_HPC
[18:30:08] [PASSED] 12.70 Xe_LPG
[18:30:08] [PASSED] 12.71 Xe_LPG
[18:30:08] [PASSED] 12.74 Xe_LPG+
[18:30:08] [PASSED] 20.01 Xe2_HPG
[18:30:08] [PASSED] 20.02 Xe2_HPG
[18:30:08] [PASSED] 20.04 Xe2_LPG
[18:30:08] [PASSED] 30.00 Xe3_LPG
[18:30:08] [PASSED] 30.01 Xe3_LPG
[18:30:08] [PASSED] 30.03 Xe3_LPG
[18:30:08] [PASSED] 30.04 Xe3_LPG
[18:30:08] [PASSED] 30.05 Xe3_LPG
[18:30:08] [PASSED] 35.10 Xe3p_LPG
[18:30:08] [PASSED] 35.11 Xe3p_XPC
[18:30:08] ================ [PASSED] check_graphics_ip ================
[18:30:08] ===================== check_media_ip  ======================
[18:30:08] [PASSED] 12.00 Xe_M
[18:30:08] [PASSED] 12.55 Xe_HPM
[18:30:08] [PASSED] 13.00 Xe_LPM+
[18:30:08] [PASSED] 13.01 Xe2_HPM
[18:30:08] [PASSED] 20.00 Xe2_LPM
[18:30:08] [PASSED] 30.00 Xe3_LPM
[18:30:08] [PASSED] 30.02 Xe3_LPM
[18:30:08] [PASSED] 35.00 Xe3p_LPM
[18:30:08] [PASSED] 35.03 Xe3p_HPM
[18:30:08] ================= [PASSED] check_media_ip ==================
[18:30:08] =================== check_platform_desc  ===================
[18:30:08] [PASSED] 0x9A60 (TIGERLAKE)
[18:30:08] [PASSED] 0x9A68 (TIGERLAKE)
[18:30:08] [PASSED] 0x9A70 (TIGERLAKE)
[18:30:08] [PASSED] 0x9A40 (TIGERLAKE)
[18:30:08] [PASSED] 0x9A49 (TIGERLAKE)
[18:30:08] [PASSED] 0x9A59 (TIGERLAKE)
[18:30:08] [PASSED] 0x9A78 (TIGERLAKE)
[18:30:08] [PASSED] 0x9AC0 (TIGERLAKE)
[18:30:08] [PASSED] 0x9AC9 (TIGERLAKE)
[18:30:08] [PASSED] 0x9AD9 (TIGERLAKE)
[18:30:08] [PASSED] 0x9AF8 (TIGERLAKE)
[18:30:08] [PASSED] 0x4C80 (ROCKETLAKE)
[18:30:08] [PASSED] 0x4C8A (ROCKETLAKE)
[18:30:08] [PASSED] 0x4C8B (ROCKETLAKE)
[18:30:08] [PASSED] 0x4C8C (ROCKETLAKE)
[18:30:08] [PASSED] 0x4C90 (ROCKETLAKE)
[18:30:08] [PASSED] 0x4C9A (ROCKETLAKE)
[18:30:08] [PASSED] 0x4680 (ALDERLAKE_S)
[18:30:08] [PASSED] 0x4682 (ALDERLAKE_S)
[18:30:08] [PASSED] 0x4688 (ALDERLAKE_S)
[18:30:08] [PASSED] 0x468A (ALDERLAKE_S)
[18:30:08] [PASSED] 0x468B (ALDERLAKE_S)
[18:30:08] [PASSED] 0x4690 (ALDERLAKE_S)
[18:30:08] [PASSED] 0x4692 (ALDERLAKE_S)
[18:30:08] [PASSED] 0x4693 (ALDERLAKE_S)
[18:30:08] [PASSED] 0x46A0 (ALDERLAKE_P)
[18:30:08] [PASSED] 0x46A1 (ALDERLAKE_P)
[18:30:08] [PASSED] 0x46A2 (ALDERLAKE_P)
[18:30:08] [PASSED] 0x46A3 (ALDERLAKE_P)
[18:30:08] [PASSED] 0x46A6 (ALDERLAKE_P)
[18:30:08] [PASSED] 0x46A8 (ALDERLAKE_P)
[18:30:08] [PASSED] 0x46AA (ALDERLAKE_P)
[18:30:08] [PASSED] 0x462A (ALDERLAKE_P)
[18:30:08] [PASSED] 0x4626 (ALDERLAKE_P)
[18:30:08] [PASSED] 0x4628 (ALDERLAKE_P)
[18:30:08] [PASSED] 0x46B0 (ALDERLAKE_P)
[18:30:08] [PASSED] 0x46B1 (ALDERLAKE_P)
[18:30:08] [PASSED] 0x46B2 (ALDERLAKE_P)
[18:30:08] [PASSED] 0x46B3 (ALDERLAKE_P)
[18:30:08] [PASSED] 0x46C0 (ALDERLAKE_P)
[18:30:08] [PASSED] 0x46C1 (ALDERLAKE_P)
[18:30:08] [PASSED] 0x46C2 (ALDERLAKE_P)
[18:30:08] [PASSED] 0x46C3 (ALDERLAKE_P)
[18:30:08] [PASSED] 0x46D0 (ALDERLAKE_N)
[18:30:08] [PASSED] 0x46D1 (ALDERLAKE_N)
[18:30:08] [PASSED] 0x46D2 (ALDERLAKE_N)
[18:30:08] [PASSED] 0x46D3 (ALDERLAKE_N)
[18:30:08] [PASSED] 0x46D4 (ALDERLAKE_N)
[18:30:08] [PASSED] 0xA721 (ALDERLAKE_P)
[18:30:08] [PASSED] 0xA7A1 (ALDERLAKE_P)
[18:30:08] [PASSED] 0xA7A9 (ALDERLAKE_P)
[18:30:08] [PASSED] 0xA7AC (ALDERLAKE_P)
[18:30:08] [PASSED] 0xA7AD (ALDERLAKE_P)
[18:30:08] [PASSED] 0xA720 (ALDERLAKE_P)
[18:30:08] [PASSED] 0xA7A0 (ALDERLAKE_P)
[18:30:08] [PASSED] 0xA7A8 (ALDERLAKE_P)
[18:30:08] [PASSED] 0xA7AA (ALDERLAKE_P)
[18:30:08] [PASSED] 0xA7AB (ALDERLAKE_P)
[18:30:08] [PASSED] 0xA780 (ALDERLAKE_S)
[18:30:08] [PASSED] 0xA781 (ALDERLAKE_S)
[18:30:08] [PASSED] 0xA782 (ALDERLAKE_S)
[18:30:08] [PASSED] 0xA783 (ALDERLAKE_S)
[18:30:08] [PASSED] 0xA788 (ALDERLAKE_S)
[18:30:08] [PASSED] 0xA789 (ALDERLAKE_S)
[18:30:08] [PASSED] 0xA78A (ALDERLAKE_S)
[18:30:08] [PASSED] 0xA78B (ALDERLAKE_S)
[18:30:08] [PASSED] 0x4905 (DG1)
[18:30:08] [PASSED] 0x4906 (DG1)
[18:30:08] [PASSED] 0x4907 (DG1)
[18:30:08] [PASSED] 0x4908 (DG1)
[18:30:08] [PASSED] 0x4909 (DG1)
[18:30:08] [PASSED] 0x56C0 (DG2)
[18:30:08] [PASSED] 0x56C2 (DG2)
[18:30:08] [PASSED] 0x56C1 (DG2)
[18:30:08] [PASSED] 0x7D51 (METEORLAKE)
[18:30:08] [PASSED] 0x7DD1 (METEORLAKE)
[18:30:08] [PASSED] 0x7D41 (METEORLAKE)
[18:30:08] [PASSED] 0x7D67 (METEORLAKE)
[18:30:08] [PASSED] 0xB640 (METEORLAKE)
[18:30:08] [PASSED] 0x56A0 (DG2)
[18:30:08] [PASSED] 0x56A1 (DG2)
[18:30:08] [PASSED] 0x56A2 (DG2)
[18:30:08] [PASSED] 0x56BE (DG2)
[18:30:08] [PASSED] 0x56BF (DG2)
[18:30:08] [PASSED] 0x5690 (DG2)
[18:30:08] [PASSED] 0x5691 (DG2)
[18:30:08] [PASSED] 0x5692 (DG2)
[18:30:08] [PASSED] 0x56A5 (DG2)
[18:30:08] [PASSED] 0x56A6 (DG2)
[18:30:08] [PASSED] 0x56B0 (DG2)
[18:30:08] [PASSED] 0x56B1 (DG2)
[18:30:08] [PASSED] 0x56BA (DG2)
[18:30:08] [PASSED] 0x56BB (DG2)
[18:30:08] [PASSED] 0x56BC (DG2)
[18:30:08] [PASSED] 0x56BD (DG2)
[18:30:08] [PASSED] 0x5693 (DG2)
[18:30:08] [PASSED] 0x5694 (DG2)
[18:30:08] [PASSED] 0x5695 (DG2)
[18:30:08] [PASSED] 0x56A3 (DG2)
[18:30:08] [PASSED] 0x56A4 (DG2)
[18:30:08] [PASSED] 0x56B2 (DG2)
[18:30:08] [PASSED] 0x56B3 (DG2)
[18:30:08] [PASSED] 0x5696 (DG2)
[18:30:08] [PASSED] 0x5697 (DG2)
[18:30:08] [PASSED] 0xB69 (PVC)
[18:30:08] [PASSED] 0xB6E (PVC)
[18:30:08] [PASSED] 0xBD4 (PVC)
[18:30:08] [PASSED] 0xBD5 (PVC)
[18:30:08] [PASSED] 0xBD6 (PVC)
[18:30:08] [PASSED] 0xBD7 (PVC)
[18:30:08] [PASSED] 0xBD8 (PVC)
[18:30:08] [PASSED] 0xBD9 (PVC)
[18:30:08] [PASSED] 0xBDA (PVC)
[18:30:08] [PASSED] 0xBDB (PVC)
[18:30:08] [PASSED] 0xBE0 (PVC)
[18:30:08] [PASSED] 0xBE1 (PVC)
[18:30:08] [PASSED] 0xBE5 (PVC)
[18:30:08] [PASSED] 0x7D40 (METEORLAKE)
[18:30:08] [PASSED] 0x7D45 (METEORLAKE)
[18:30:08] [PASSED] 0x7D55 (METEORLAKE)
[18:30:08] [PASSED] 0x7D60 (METEORLAKE)
[18:30:08] [PASSED] 0x7DD5 (METEORLAKE)
[18:30:08] [PASSED] 0x6420 (LUNARLAKE)
[18:30:08] [PASSED] 0x64A0 (LUNARLAKE)
[18:30:08] [PASSED] 0x64B0 (LUNARLAKE)
[18:30:08] [PASSED] 0xE202 (BATTLEMAGE)
[18:30:08] [PASSED] 0xE209 (BATTLEMAGE)
[18:30:08] [PASSED] 0xE20B (BATTLEMAGE)
[18:30:08] [PASSED] 0xE20C (BATTLEMAGE)
[18:30:08] [PASSED] 0xE20D (BATTLEMAGE)
[18:30:08] [PASSED] 0xE210 (BATTLEMAGE)
[18:30:08] [PASSED] 0xE211 (BATTLEMAGE)
[18:30:08] [PASSED] 0xE212 (BATTLEMAGE)
[18:30:08] [PASSED] 0xE216 (BATTLEMAGE)
[18:30:08] [PASSED] 0xE220 (BATTLEMAGE)
[18:30:08] [PASSED] 0xE221 (BATTLEMAGE)
[18:30:08] [PASSED] 0xE222 (BATTLEMAGE)
[18:30:08] [PASSED] 0xE223 (BATTLEMAGE)
[18:30:08] [PASSED] 0xB080 (PANTHERLAKE)
[18:30:08] [PASSED] 0xB081 (PANTHERLAKE)
[18:30:08] [PASSED] 0xB082 (PANTHERLAKE)
[18:30:08] [PASSED] 0xB083 (PANTHERLAKE)
[18:30:08] [PASSED] 0xB084 (PANTHERLAKE)
[18:30:08] [PASSED] 0xB085 (PANTHERLAKE)
[18:30:08] [PASSED] 0xB086 (PANTHERLAKE)
[18:30:08] [PASSED] 0xB087 (PANTHERLAKE)
[18:30:08] [PASSED] 0xB08F (PANTHERLAKE)
[18:30:08] [PASSED] 0xB090 (PANTHERLAKE)
[18:30:08] [PASSED] 0xB0A0 (PANTHERLAKE)
[18:30:08] [PASSED] 0xB0B0 (PANTHERLAKE)
[18:30:08] [PASSED] 0xFD80 (PANTHERLAKE)
[18:30:08] [PASSED] 0xFD81 (PANTHERLAKE)
[18:30:08] [PASSED] 0xD740 (NOVALAKE_S)
[18:30:08] [PASSED] 0xD741 (NOVALAKE_S)
[18:30:08] [PASSED] 0xD742 (NOVALAKE_S)
[18:30:08] [PASSED] 0xD743 (NOVALAKE_S)
[18:30:08] [PASSED] 0xD745 (NOVALAKE_S)
[18:30:08] [PASSED] 0xD74A (NOVALAKE_S)
[18:30:08] [PASSED] 0xD74B (NOVALAKE_S)
[18:30:08] [PASSED] 0x674C (CRESCENTISLAND)
[18:30:08] [PASSED] 0x674D (CRESCENTISLAND)
[18:30:08] [PASSED] 0x674E (CRESCENTISLAND)
[18:30:08] [PASSED] 0x674F (CRESCENTISLAND)
[18:30:08] [PASSED] 0x6750 (CRESCENTISLAND)
[18:30:08] [PASSED] 0xD750 (NOVALAKE_P)
[18:30:08] [PASSED] 0xD751 (NOVALAKE_P)
[18:30:08] [PASSED] 0xD752 (NOVALAKE_P)
[18:30:08] [PASSED] 0xD753 (NOVALAKE_P)
[18:30:08] [PASSED] 0xD754 (NOVALAKE_P)
[18:30:08] [PASSED] 0xD755 (NOVALAKE_P)
[18:30:08] [PASSED] 0xD756 (NOVALAKE_P)
[18:30:08] [PASSED] 0xD757 (NOVALAKE_P)
[18:30:08] [PASSED] 0xD75F (NOVALAKE_P)
[18:30:08] =============== [PASSED] check_platform_desc ===============
[18:30:08] ===================== [PASSED] xe_pci ======================
[18:30:08] ============= xe_rtp_tables_test (5 subtests) ==============
[18:30:08] ================== xe_rtp_table_gt_test  ===================
[18:30:08] [PASSED] gt_was/14011060649
[18:30:08] [PASSED] gt_was/14011059788
[18:30:08] [PASSED] gt_was/14015795083
[18:30:08] [PASSED] gt_was/16021867713
[18:30:08] [PASSED] gt_was/14019449301
[18:30:08] [PASSED] gt_was/16028005424
[18:30:08] [PASSED] gt_was/14026578760
[18:30:08] [PASSED] gt_was/1409420604
[18:30:08] [PASSED] gt_was/1408615072
[18:30:08] [PASSED] gt_was/22010523718
[18:30:08] [PASSED] gt_was/14011006942
[18:30:08] [PASSED] gt_was/14014830051
[18:30:08] [PASSED] gt_was/18018781329
[18:30:08] [PASSED] gt_was/1509235366
[18:30:08] [PASSED] gt_was/18018781329
[18:30:08] [PASSED] gt_was/16016694945
[18:30:08] [PASSED] gt_was/14018575942
[18:30:08] [PASSED] gt_was/22016670082
[18:30:08] [PASSED] gt_was/22016670082
[18:30:08] [PASSED] gt_was/14017421178
[18:30:08] [PASSED] gt_was/16025250150
[18:30:08] [PASSED] gt_was/14021871409
[18:30:08] [PASSED] gt_was/16021865536
[18:30:08] [PASSED] gt_was/14021486841
[18:30:08] [PASSED] gt_was/14025160223
[18:30:08] [PASSED] gt_was/14026144927, 16029437861, 14026127056
[18:30:08] [PASSED] gt_was/14025635424
[18:30:08] [PASSED] gt_was/16028005424
[18:30:08] ============== [PASSED] xe_rtp_table_gt_test ===============
[18:30:08] ================== xe_rtp_table_gt_test  ===================
[18:30:08] [PASSED] gt_tunings/Tuning: Blend Fill Caching Optimization Disable
[18:30:08] [PASSED] gt_tunings/Tuning: 32B Access Enable
[18:30:08] [PASSED] gt_tunings/Tuning: L3 cache
[18:30:08] [PASSED] gt_tunings/Tuning: L3 cache - media
[18:30:08] [PASSED] gt_tunings/Tuning: Compression Overfetch
[18:30:08] [PASSED] gt_tunings/Tuning: Compression Overfetch - media
[18:30:08] [PASSED] gt_tunings/Tuning: Enable compressible partial write overfetch in L3
[18:30:08] [PASSED] gt_tunings/Tuning: Enable compressible partial write overfetch in L3 - media
[18:30:08] [PASSED] gt_tunings/Tuning: L2 Overfetch Compressible Only
[18:30:08] [PASSED] gt_tunings/Tuning: L2 Overfetch Compressible Only - media
[18:30:08] [PASSED] gt_tunings/Tuning: Stateless compression control
[18:30:08] [PASSED] gt_tunings/Tuning: Stateless compression control - media
[18:30:08] [PASSED] gt_tunings/Tuning: L3 RW flush all Cache
[18:30:08] [PASSED] gt_tunings/Tuning: L3 RW flush all cache - media
[18:30:08] [PASSED] gt_tunings/Tuning: Set STLB Bank Hash Mode to 4KB
[18:30:08] ============== [PASSED] xe_rtp_table_gt_test ===============
[18:30:08] ================== xe_rtp_table_oob_test  ==================
[18:30:08] [PASSED] oob_was/1607983814
[18:30:08] [PASSED] oob_was/16010904313
[18:30:08] [PASSED] oob_was/18022495364
[18:30:08] [PASSED] oob_was/22012773006
[18:30:08] [PASSED] oob_was/14014475959
[18:30:08] [PASSED] oob_was/22011391025
[18:30:08] [PASSED] oob_was/22012727170
[18:30:08] [PASSED] oob_was/22012727685
[18:30:08] [PASSED] oob_was/22016596838
[18:30:08] [PASSED] oob_was/18020744125
[18:30:08] [PASSED] oob_was/1409600907
[18:30:08] [PASSED] oob_was/22014953428
[18:30:08] [PASSED] oob_was/16017236439
[18:30:08] [PASSED] oob_was/14019821291
[18:30:08] [PASSED] oob_was/14015076503
[18:30:08] [PASSED] oob_was/14018913170
[18:30:08] [PASSED] oob_was/14018094691
[18:30:08] [PASSED] oob_was/18024947630
[18:30:08] [PASSED] oob_was/16022287689
[18:30:08] [PASSED] oob_was/13011645652
[18:30:08] [PASSED] oob_was/14022293748
[18:30:08] [PASSED] oob_was/22019794406
[18:30:08] [PASSED] oob_was/22019338487
[18:30:08] [PASSED] oob_was/16023588340
[18:30:08] [PASSED] oob_was/14019789679
[18:30:08] [PASSED] oob_was/14022866841
[18:30:08] [PASSED] oob_was/16021333562
[18:30:08] [PASSED] oob_was/14016712196
[18:30:08] [PASSED] oob_was/14015568240
[18:30:08] [PASSED] oob_was/18013179988
[18:30:08] [PASSED] oob_was/1508761755
[18:30:08] [PASSED] oob_was/16023105232
[18:30:08] [PASSED] oob_was/16026508708
[18:30:08] [PASSED] oob_was/14020001231
[18:30:08] [PASSED] oob_was/16023683509
[18:30:08] [PASSED] oob_was/14025515070
[18:30:08] [PASSED] oob_was/15015404425_disable
[18:30:08] [PASSED] oob_was/16026007364
[18:30:08] [PASSED] oob_was/14020316580
[18:30:08] [PASSED] oob_was/14025883347
[18:30:08] [PASSED] oob_was/16029380221
[18:30:08] [PASSED] oob_was/22022079272
[18:30:08] [PASSED] oob_was/16029897822
[18:30:08] [PASSED] oob_was/14027054324
[18:30:08] ============== [PASSED] xe_rtp_table_oob_test ==============
[18:30:08] ================ xe_rtp_table_dev_oob_test  ================
[18:30:08] [PASSED] device_oob_was/22010954014
[18:30:08] [PASSED] device_oob_was/15015404425
[18:30:08] [PASSED] device_oob_was/22019338487_display
[18:30:08] [PASSED] device_oob_was/14022085890
[18:30:08] [PASSED] device_oob_was/14026539277
[18:30:08] [PASSED] device_oob_was/14026633728
[18:30:08] [PASSED] device_oob_was/14026746987
[18:30:08] [PASSED] device_oob_was/14026779378
[18:30:08] ============ [PASSED] xe_rtp_table_dev_oob_test ============
[18:30:08] ========== xe_rtp_table_missing_upper_bound_test  ==========
[18:30:08] [PASSED] register_whitelist/WaAllowPMDepthAndInvocationCountAccessFromUMD, 1408556865
[18:30:08] [PASSED] register_whitelist/1508744258, 14012131227, 1808121037
[18:30:08] [PASSED] register_whitelist/1806527549
[18:30:08] [PASSED] register_whitelist/allow_read_ctx_timestamp
[18:30:08] [PASSED] register_whitelist/allow_read_queue_timestamp
[18:30:08] [PASSED] register_whitelist/16014440446
[18:30:08] [PASSED] register_whitelist/16017236439
[18:30:08] [PASSED] register_whitelist/16020183090
[18:30:08] [PASSED] register_whitelist/14024997852
[18:30:08] [PASSED] register_whitelist/14024997852
[18:30:08] ====== [PASSED] xe_rtp_table_missing_upper_bound_test ======
[18:30:08] =============== [PASSED] xe_rtp_tables_test ================
[18:30:08] =================== xe_rtp (3 subtests) ====================
[18:30:08] =================== xe_rtp_rules_tests  ====================
[18:30:08] [PASSED] no
[18:30:08] [PASSED] yes
[18:30:08] [PASSED] no-and-no
[18:30:08] [PASSED] no-and-yes
[18:30:08] [PASSED] yes-and-no
[18:30:08] [PASSED] yes-and-yes
[18:30:08] [PASSED] no-or-no
[18:30:08] [PASSED] no-or-yes
[18:30:08] [PASSED] yes-or-no
[18:30:08] [PASSED] yes-or-yes
[18:30:08] [PASSED] no-yes-or-yes-no
[18:30:08] [PASSED] no-yes-or-yes-yes
[18:30:08] [PASSED] yes-yes-or-no-yes
[18:30:08] [PASSED] yes-yes-or-yes-yes
[18:30:08] [PASSED] no-no-or-yes-or-no
[18:30:08] [PASSED] or
[18:30:08] [PASSED] or-yes
[18:30:08] [PASSED] or-no
[18:30:08] [PASSED] yes-or
[18:30:08] [PASSED] no-or
[18:30:08] [PASSED] no-or-or-yes
[18:30:08] [PASSED] yes-or-or-no
[18:30:08] [PASSED] no-or-or-no
[18:30:08] [PASSED] missing-context-engine-class
[18:30:08] [PASSED] missing-context-engine-class-or-yes
[18:30:08] [PASSED] missing-context-engine-class-or-or-yes
[18:30:08] =============== [PASSED] xe_rtp_rules_tests ================
[18:30:08] =============== xe_rtp_process_to_sr_tests  ================
[18:30:08] [PASSED] coalesce-same-reg
[18:30:08] [PASSED] coalesce-same-reg-literal-and-func
[18:30:08] [PASSED] no-match-no-add
[18:30:08] [PASSED] two-regs-two-entries
[18:30:08] [PASSED] clr-one-set-other
[18:30:08] [PASSED] set-field
[18:30:08] [PASSED] conflict-duplicate
[18:30:08] [PASSED] conflict-not-disjoint
[18:30:08] [PASSED] conflict-not-disjoint-literal-and-func
[18:30:08] [PASSED] conflict-reg-type
[18:30:08] [PASSED] bad-mcr-reg-forced-to-regular
[18:30:08] [PASSED] bad-regular-reg-forced-to-mcr
[18:30:08] =========== [PASSED] xe_rtp_process_to_sr_tests ============
[18:30:08] ================== xe_rtp_process_tests  ===================
[18:30:08] [PASSED] active1
[18:30:08] [PASSED] active2
[18:30:08] [PASSED] active-inactive
[18:30:08] [PASSED] inactive-active
[18:30:08] [PASSED] inactive-active-inactive
[18:30:08] [PASSED] inactive-inactive-inactive
[18:30:08] ============== [PASSED] xe_rtp_process_tests ===============
[18:30:08] ===================== [PASSED] xe_rtp ======================
[18:30:08] ==================== xe_wa (1 subtest) =====================
[18:30:08] ======================== xe_wa_gt  =========================
[18:30:08] [PASSED] TIGERLAKE B0
[18:30:08] [PASSED] DG1 A0
[18:30:08] [PASSED] DG1 B0
[18:30:08] [PASSED] ALDERLAKE_S A0
[18:30:08] [PASSED] ALDERLAKE_S B0
[18:30:08] [PASSED] ALDERLAKE_S C0
[18:30:08] [PASSED] ALDERLAKE_S D0
[18:30:08] [PASSED] ALDERLAKE_P A0
[18:30:08] [PASSED] ALDERLAKE_P B0
[18:30:08] [PASSED] ALDERLAKE_P C0
[18:30:08] [PASSED] ALDERLAKE_S RPLS D0
[18:30:08] [PASSED] ALDERLAKE_P RPLU E0
[18:30:08] [PASSED] DG2 G10 C0
[18:30:08] [PASSED] DG2 G11 B1
[18:30:08] [PASSED] DG2 G12 A1
[18:30:08] [PASSED] METEORLAKE 12.70(Xe_LPG) A0 13.00(Xe_LPM+) A0
[18:30:08] [PASSED] METEORLAKE 12.71(Xe_LPG) A0 13.00(Xe_LPM+) A0
[18:30:08] [PASSED] METEORLAKE 12.74(Xe_LPG+) A0 13.00(Xe_LPM+) A0
[18:30:08] [PASSED] LUNARLAKE 20.04(Xe2_LPG) A0 20.00(Xe2_LPM) A0
[18:30:08] [PASSED] LUNARLAKE 20.04(Xe2_LPG) B0 20.00(Xe2_LPM) A0
[18:30:08] [PASSED] BATTLEMAGE 20.01(Xe2_HPG) A0 13.01(Xe2_HPM) A1
[18:30:08] [PASSED] PANTHERLAKE 30.00(Xe3_LPG) A0 30.00(Xe3_LPM) A0
[18:30:08] ==================== [PASSED] xe_wa_gt =====================
[18:30:08] ====================== [PASSED] xe_wa ======================
[18:30:08] ============================================================
[18:30:08] Testing complete. Ran 789 tests: passed: 761, skipped: 28
[18:30:08] Elapsed time: 37.821s total, 4.387s configuring, 32.718s building, 0.680s running

+ /kernel/tools/testing/kunit/kunit.py run --kunitconfig /kernel/drivers/gpu/drm/tests/.kunitconfig
[18:30:09] Configuring KUnit Kernel ...
Regenerating .config ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
[18:30:10] Building KUnit Kernel ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
Building with:
$ make all compile_commands.json scripts_gdb ARCH=um O=.kunit --jobs=48
[18:30:36] Starting KUnit Kernel (1/1)...
[18:30:36] ============================================================
Running tests with:
$ .kunit/linux kunit.enable=1 mem=1G console=tty kunit_shutdown=halt
[18:30:36] ============ drm_test_pick_cmdline (2 subtests) ============
[18:30:36] [PASSED] drm_test_pick_cmdline_res_1920_1080_60
[18:30:36] =============== drm_test_pick_cmdline_named  ===============
[18:30:36] [PASSED] NTSC
[18:30:36] [PASSED] NTSC-J
[18:30:36] [PASSED] PAL
[18:30:36] [PASSED] PAL-M
[18:30:36] =========== [PASSED] drm_test_pick_cmdline_named ===========
[18:30:36] ============== [PASSED] drm_test_pick_cmdline ==============
[18:30:36] == drm_test_atomic_get_connector_for_encoder (1 subtest) ===
[18:30:36] [PASSED] drm_test_drm_atomic_get_connector_for_encoder
[18:30:36] ==== [PASSED] drm_test_atomic_get_connector_for_encoder ====
[18:30:36] =========== drm_validate_clone_mode (2 subtests) ===========
[18:30:36] ============== drm_test_check_in_clone_mode  ===============
[18:30:36] [PASSED] in_clone_mode
[18:30:36] [PASSED] not_in_clone_mode
[18:30:36] ========== [PASSED] drm_test_check_in_clone_mode ===========
[18:30:36] =============== drm_test_check_valid_clones  ===============
[18:30:36] [PASSED] not_in_clone_mode
[18:30:36] [PASSED] valid_clone
[18:30:36] [PASSED] invalid_clone
[18:30:36] =========== [PASSED] drm_test_check_valid_clones ===========
[18:30:36] ============= [PASSED] drm_validate_clone_mode =============
[18:30:36] ============= drm_validate_modeset (1 subtest) =============
[18:30:36] [PASSED] drm_test_check_connector_changed_modeset
[18:30:36] ============== [PASSED] drm_validate_modeset ===============
[18:30:36] ====== drm_test_bridge_get_current_state (1 subtest) =======
[18:30:36] [PASSED] drm_test_drm_bridge_get_current_state_atomic
[18:30:36] ======== [PASSED] drm_test_bridge_get_current_state ========
[18:30:36] ====== drm_test_bridge_helper_reset_crtc (3 subtests) ======
[18:30:36] [PASSED] drm_test_drm_bridge_helper_reset_crtc_atomic
[18:30:36] [PASSED] drm_test_drm_bridge_helper_reset_crtc_atomic_disabled
[18:30:36] [PASSED] drm_test_drm_bridge_helper_hdmi_output_bus_fmts
[18:30:36] ======== [PASSED] drm_test_bridge_helper_reset_crtc ========
[18:30:36] ============== drm_bridge_alloc (2 subtests) ===============
[18:30:36] [PASSED] drm_test_drm_bridge_alloc_basic
[18:30:36] [PASSED] drm_test_drm_bridge_alloc_get_put
[18:30:36] ================ [PASSED] drm_bridge_alloc =================
[18:30:36] ============= drm_bridge_bus_fmt (5 subtests) ==============
[18:30:36] [PASSED] drm_test_bridge_rgb_yuv_rgb
[18:30:36] [PASSED] drm_test_bridge_must_convert_to_yuv444
[18:30:36] [PASSED] drm_test_bridge_hdmi_auto_rgb
[18:30:36] [PASSED] drm_test_bridge_auto_first
[18:30:36] [PASSED] drm_test_bridge_rgb_yuv_no_path
[18:30:36] =============== [PASSED] drm_bridge_bus_fmt ================
[18:30:36] ============= drm_cmdline_parser (40 subtests) =============
[18:30:36] [PASSED] drm_test_cmdline_force_d_only
[18:30:36] [PASSED] drm_test_cmdline_force_D_only_dvi
[18:30:36] [PASSED] drm_test_cmdline_force_D_only_hdmi
[18:30:36] [PASSED] drm_test_cmdline_force_D_only_not_digital
[18:30:36] [PASSED] drm_test_cmdline_force_e_only
[18:30:36] [PASSED] drm_test_cmdline_res
[18:30:36] [PASSED] drm_test_cmdline_res_vesa
[18:30:36] [PASSED] drm_test_cmdline_res_vesa_rblank
[18:30:36] [PASSED] drm_test_cmdline_res_rblank
[18:30:36] [PASSED] drm_test_cmdline_res_bpp
[18:30:36] [PASSED] drm_test_cmdline_res_refresh
[18:30:36] [PASSED] drm_test_cmdline_res_bpp_refresh
[18:30:36] [PASSED] drm_test_cmdline_res_bpp_refresh_interlaced
[18:30:36] [PASSED] drm_test_cmdline_res_bpp_refresh_margins
[18:30:36] [PASSED] drm_test_cmdline_res_bpp_refresh_force_off
[18:30:36] [PASSED] drm_test_cmdline_res_bpp_refresh_force_on
[18:30:36] [PASSED] drm_test_cmdline_res_bpp_refresh_force_on_analog
[18:30:36] [PASSED] drm_test_cmdline_res_bpp_refresh_force_on_digital
[18:30:36] [PASSED] drm_test_cmdline_res_bpp_refresh_interlaced_margins_force_on
[18:30:36] [PASSED] drm_test_cmdline_res_margins_force_on
[18:30:36] [PASSED] drm_test_cmdline_res_vesa_margins
[18:30:36] [PASSED] drm_test_cmdline_name
[18:30:36] [PASSED] drm_test_cmdline_name_bpp
[18:30:36] [PASSED] drm_test_cmdline_name_option
[18:30:36] [PASSED] drm_test_cmdline_name_bpp_option
[18:30:36] [PASSED] drm_test_cmdline_rotate_0
[18:30:36] [PASSED] drm_test_cmdline_rotate_90
[18:30:36] [PASSED] drm_test_cmdline_rotate_180
[18:30:36] [PASSED] drm_test_cmdline_rotate_270
[18:30:36] [PASSED] drm_test_cmdline_hmirror
[18:30:36] [PASSED] drm_test_cmdline_vmirror
[18:30:36] [PASSED] drm_test_cmdline_margin_options
[18:30:36] [PASSED] drm_test_cmdline_multiple_options
[18:30:36] [PASSED] drm_test_cmdline_bpp_extra_and_option
[18:30:36] [PASSED] drm_test_cmdline_extra_and_option
[18:30:36] [PASSED] drm_test_cmdline_freestanding_options
[18:30:36] [PASSED] drm_test_cmdline_freestanding_force_e_and_options
[18:30:36] [PASSED] drm_test_cmdline_panel_orientation
[18:30:36] ================ drm_test_cmdline_invalid  =================
[18:30:36] [PASSED] margin_only
[18:30:36] [PASSED] interlace_only
[18:30:36] [PASSED] res_missing_x
[18:30:36] [PASSED] res_missing_y
[18:30:36] [PASSED] res_bad_y
[18:30:36] [PASSED] res_missing_y_bpp
[18:30:36] [PASSED] res_bad_bpp
[18:30:36] [PASSED] res_bad_refresh
[18:30:36] [PASSED] res_bpp_refresh_force_on_off
[18:30:36] [PASSED] res_invalid_mode
[18:30:36] [PASSED] res_bpp_wrong_place_mode
[18:30:36] [PASSED] name_bpp_refresh
[18:30:36] [PASSED] name_refresh
[18:30:36] [PASSED] name_refresh_wrong_mode
[18:30:36] [PASSED] name_refresh_invalid_mode
[18:30:36] [PASSED] rotate_multiple
[18:30:36] [PASSED] rotate_invalid_val
[18:30:36] [PASSED] rotate_truncated
[18:30:36] [PASSED] invalid_option
[18:30:36] [PASSED] invalid_tv_option
[18:30:36] [PASSED] truncated_tv_option
[18:30:36] ============ [PASSED] drm_test_cmdline_invalid =============
[18:30:36] =============== drm_test_cmdline_tv_options  ===============
[18:30:36] [PASSED] NTSC
[18:30:36] [PASSED] NTSC_443
[18:30:36] [PASSED] NTSC_J
[18:30:36] [PASSED] PAL
[18:30:36] [PASSED] PAL_M
[18:30:36] [PASSED] PAL_N
[18:30:36] [PASSED] SECAM
[18:30:36] [PASSED] MONO_525
[18:30:36] [PASSED] MONO_625
[18:30:36] =========== [PASSED] drm_test_cmdline_tv_options ===========
[18:30:36] =============== [PASSED] drm_cmdline_parser ================
[18:30:36] ========== drmm_connector_hdmi_init (20 subtests) ==========
[18:30:36] [PASSED] drm_test_connector_hdmi_init_valid
[18:30:36] [PASSED] drm_test_connector_hdmi_init_bpc_8
[18:30:36] [PASSED] drm_test_connector_hdmi_init_bpc_10
[18:30:36] [PASSED] drm_test_connector_hdmi_init_bpc_12
[18:30:36] [PASSED] drm_test_connector_hdmi_init_bpc_invalid
[18:30:36] [PASSED] drm_test_connector_hdmi_init_bpc_null
[18:30:36] [PASSED] drm_test_connector_hdmi_init_formats_empty
[18:30:36] [PASSED] drm_test_connector_hdmi_init_formats_no_rgb
[18:30:36] === drm_test_connector_hdmi_init_formats_yuv420_allowed  ===
[18:30:36] [PASSED] supported_formats=0x9 yuv420_allowed=1
[18:30:36] [PASSED] supported_formats=0x9 yuv420_allowed=0
[18:30:36] [PASSED] supported_formats=0x5 yuv420_allowed=1
[18:30:36] [PASSED] supported_formats=0x5 yuv420_allowed=0
[18:30:36] === [PASSED] drm_test_connector_hdmi_init_formats_yuv420_allowed ===
[18:30:36] [PASSED] drm_test_connector_hdmi_init_null_ddc
[18:30:36] [PASSED] drm_test_connector_hdmi_init_null_product
[18:30:36] [PASSED] drm_test_connector_hdmi_init_null_vendor
[18:30:36] [PASSED] drm_test_connector_hdmi_init_product_length_exact
[18:30:36] [PASSED] drm_test_connector_hdmi_init_product_length_too_long
[18:30:36] [PASSED] drm_test_connector_hdmi_init_product_valid
[18:30:36] [PASSED] drm_test_connector_hdmi_init_vendor_length_exact
[18:30:36] [PASSED] drm_test_connector_hdmi_init_vendor_length_too_long
[18:30:36] [PASSED] drm_test_connector_hdmi_init_vendor_valid
[18:30:36] ========= drm_test_connector_hdmi_init_type_valid  =========
[18:30:36] [PASSED] HDMI-A
[18:30:36] [PASSED] HDMI-B
[18:30:36] ===== [PASSED] drm_test_connector_hdmi_init_type_valid =====
[18:30:36] ======== drm_test_connector_hdmi_init_type_invalid  ========
[18:30:36] [PASSED] Unknown
[18:30:36] [PASSED] VGA
[18:30:36] [PASSED] DVI-I
[18:30:36] [PASSED] DVI-D
[18:30:36] [PASSED] DVI-A
[18:30:36] [PASSED] Composite
[18:30:36] [PASSED] SVIDEO
[18:30:36] [PASSED] LVDS
[18:30:36] [PASSED] Component
[18:30:36] [PASSED] DIN
[18:30:36] [PASSED] DP
[18:30:36] [PASSED] TV
[18:30:36] [PASSED] eDP
[18:30:36] [PASSED] Virtual
[18:30:36] [PASSED] DSI
[18:30:36] [PASSED] DPI
[18:30:36] [PASSED] Writeback
[18:30:36] [PASSED] SPI
[18:30:36] [PASSED] USB
[18:30:36] ==== [PASSED] drm_test_connector_hdmi_init_type_invalid ====
[18:30:36] ============ [PASSED] drmm_connector_hdmi_init =============
[18:30:36] ============= drmm_connector_init (3 subtests) =============
[18:30:36] [PASSED] drm_test_drmm_connector_init
[18:30:36] [PASSED] drm_test_drmm_connector_init_null_ddc
[18:30:36] ========= drm_test_drmm_connector_init_type_valid  =========
[18:30:36] [PASSED] Unknown
[18:30:36] [PASSED] VGA
[18:30:36] [PASSED] DVI-I
[18:30:36] [PASSED] DVI-D
[18:30:36] [PASSED] DVI-A
[18:30:36] [PASSED] Composite
[18:30:36] [PASSED] SVIDEO
[18:30:36] [PASSED] LVDS
[18:30:36] [PASSED] Component
[18:30:36] [PASSED] DIN
[18:30:36] [PASSED] DP
[18:30:36] [PASSED] HDMI-A
[18:30:36] [PASSED] HDMI-B
[18:30:36] [PASSED] TV
[18:30:36] [PASSED] eDP
[18:30:36] [PASSED] Virtual
[18:30:36] [PASSED] DSI
[18:30:36] [PASSED] DPI
[18:30:36] [PASSED] Writeback
[18:30:36] [PASSED] SPI
[18:30:36] [PASSED] USB
[18:30:36] ===== [PASSED] drm_test_drmm_connector_init_type_valid =====
[18:30:36] =============== [PASSED] drmm_connector_init ===============
[18:30:36] ========= drm_connector_dynamic_init (6 subtests) ==========
[18:30:36] [PASSED] drm_test_drm_connector_dynamic_init
[18:30:36] [PASSED] drm_test_drm_connector_dynamic_init_null_ddc
[18:30:36] [PASSED] drm_test_drm_connector_dynamic_init_not_added
[18:30:36] [PASSED] drm_test_drm_connector_dynamic_init_properties
[18:30:36] ===== drm_test_drm_connector_dynamic_init_type_valid  ======
[18:30:36] [PASSED] Unknown
[18:30:36] [PASSED] VGA
[18:30:36] [PASSED] DVI-I
[18:30:36] [PASSED] DVI-D
[18:30:36] [PASSED] DVI-A
[18:30:36] [PASSED] Composite
[18:30:36] [PASSED] SVIDEO
[18:30:36] [PASSED] LVDS
[18:30:36] [PASSED] Component
[18:30:36] [PASSED] DIN
[18:30:36] [PASSED] DP
[18:30:36] [PASSED] HDMI-A
[18:30:36] [PASSED] HDMI-B
[18:30:36] [PASSED] TV
[18:30:36] [PASSED] eDP
[18:30:36] [PASSED] Virtual
[18:30:36] [PASSED] DSI
[18:30:36] [PASSED] DPI
[18:30:36] [PASSED] Writeback
[18:30:36] [PASSED] SPI
[18:30:36] [PASSED] USB
[18:30:36] = [PASSED] drm_test_drm_connector_dynamic_init_type_valid ==
[18:30:36] ======== drm_test_drm_connector_dynamic_init_name  =========
[18:30:36] [PASSED] Unknown
[18:30:36] [PASSED] VGA
[18:30:36] [PASSED] DVI-I
[18:30:36] [PASSED] DVI-D
[18:30:36] [PASSED] DVI-A
[18:30:36] [PASSED] Composite
[18:30:36] [PASSED] SVIDEO
[18:30:36] [PASSED] LVDS
[18:30:36] [PASSED] Component
[18:30:36] [PASSED] DIN
[18:30:36] [PASSED] DP
[18:30:36] [PASSED] HDMI-A
[18:30:36] [PASSED] HDMI-B
[18:30:36] [PASSED] TV
[18:30:36] [PASSED] eDP
[18:30:36] [PASSED] Virtual
[18:30:36] [PASSED] DSI
[18:30:36] [PASSED] DPI
[18:30:36] [PASSED] Writeback
[18:30:36] [PASSED] SPI
[18:30:36] [PASSED] USB
[18:30:36] ==== [PASSED] drm_test_drm_connector_dynamic_init_name =====
[18:30:36] =========== [PASSED] drm_connector_dynamic_init ============
[18:30:36] ==== drm_connector_dynamic_register_early (4 subtests) =====
[18:30:36] [PASSED] drm_test_drm_connector_dynamic_register_early_on_list
[18:30:36] [PASSED] drm_test_drm_connector_dynamic_register_early_defer
[18:30:36] [PASSED] drm_test_drm_connector_dynamic_register_early_no_init
[18:30:36] [PASSED] drm_test_drm_connector_dynamic_register_early_no_mode_object
[18:30:36] ====== [PASSED] drm_connector_dynamic_register_early =======
[18:30:36] ======= drm_connector_dynamic_register (7 subtests) ========
[18:30:36] [PASSED] drm_test_drm_connector_dynamic_register_on_list
[18:30:36] [PASSED] drm_test_drm_connector_dynamic_register_no_defer
[18:30:36] [PASSED] drm_test_drm_connector_dynamic_register_no_init
[18:30:36] [PASSED] drm_test_drm_connector_dynamic_register_mode_object
[18:30:36] [PASSED] drm_test_drm_connector_dynamic_register_sysfs
[18:30:36] [PASSED] drm_test_drm_connector_dynamic_register_sysfs_name
[18:30:36] [PASSED] drm_test_drm_connector_dynamic_register_debugfs
[18:30:36] ========= [PASSED] drm_connector_dynamic_register ==========
[18:30:36] = drm_connector_attach_broadcast_rgb_property (2 subtests) =
[18:30:36] [PASSED] drm_test_drm_connector_attach_broadcast_rgb_property
[18:30:36] [PASSED] drm_test_drm_connector_attach_broadcast_rgb_property_hdmi_connector
[18:30:36] === [PASSED] drm_connector_attach_broadcast_rgb_property ===
[18:30:36] ========== drm_get_tv_mode_from_name (2 subtests) ==========
[18:30:36] ========== drm_test_get_tv_mode_from_name_valid  ===========
[18:30:36] [PASSED] NTSC
[18:30:36] [PASSED] NTSC-443
[18:30:36] [PASSED] NTSC-J
[18:30:36] [PASSED] PAL
[18:30:36] [PASSED] PAL-M
[18:30:36] [PASSED] PAL-N
[18:30:36] [PASSED] SECAM
[18:30:36] [PASSED] Mono
[18:30:36] ====== [PASSED] drm_test_get_tv_mode_from_name_valid =======
[18:30:36] [PASSED] drm_test_get_tv_mode_from_name_truncated
[18:30:36] ============ [PASSED] drm_get_tv_mode_from_name ============
[18:30:36] = drm_test_connector_hdmi_compute_mode_clock (12 subtests) =
[18:30:36] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb
[18:30:36] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_10bpc
[18:30:36] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_10bpc_vic_1
[18:30:36] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_12bpc
[18:30:36] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_12bpc_vic_1
[18:30:36] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_double
[18:30:36] = drm_test_connector_hdmi_compute_mode_clock_yuv420_valid  =
[18:30:36] [PASSED] VIC 96
[18:30:36] [PASSED] VIC 97
[18:30:36] [PASSED] VIC 101
[18:30:36] [PASSED] VIC 102
[18:30:36] [PASSED] VIC 106
[18:30:36] [PASSED] VIC 107
[18:30:36] === [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv420_valid ===
[18:30:36] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv420_10_bpc
[18:30:36] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv420_12_bpc
[18:30:36] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv422_8_bpc
[18:30:36] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv422_10_bpc
[18:30:36] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv422_12_bpc
[18:30:36] === [PASSED] drm_test_connector_hdmi_compute_mode_clock ====
[18:30:36] == drm_hdmi_connector_get_broadcast_rgb_name (2 subtests) ==
[18:30:36] === drm_test_drm_hdmi_connector_get_broadcast_rgb_name  ====
[18:30:36] [PASSED] Automatic
[18:30:36] [PASSED] Full
[18:30:36] [PASSED] Limited 16:235
[18:30:36] === [PASSED] drm_test_drm_hdmi_connector_get_broadcast_rgb_name ===
[18:30:36] [PASSED] drm_test_drm_hdmi_connector_get_broadcast_rgb_name_invalid
[18:30:36] ==== [PASSED] drm_hdmi_connector_get_broadcast_rgb_name ====
[18:30:36] == drm_hdmi_connector_get_output_format_name (2 subtests) ==
[18:30:36] === drm_test_drm_hdmi_connector_get_output_format_name  ====
[18:30:36] [PASSED] RGB
[18:30:36] [PASSED] YUV 4:2:0
[18:30:36] [PASSED] YUV 4:2:2
[18:30:36] [PASSED] YUV 4:4:4
[18:30:36] === [PASSED] drm_test_drm_hdmi_connector_get_output_format_name ===
[18:30:36] [PASSED] drm_test_drm_hdmi_connector_get_output_format_name_invalid
[18:30:36] ==== [PASSED] drm_hdmi_connector_get_output_format_name ====
[18:30:36] ============= drm_damage_helper (21 subtests) ==============
[18:30:36] [PASSED] drm_test_damage_iter_no_damage
[18:30:36] [PASSED] drm_test_damage_iter_no_damage_fractional_src
[18:30:36] [PASSED] drm_test_damage_iter_no_damage_src_moved
[18:30:36] [PASSED] drm_test_damage_iter_no_damage_fractional_src_moved
[18:30:36] [PASSED] drm_test_damage_iter_no_damage_not_visible
[18:30:36] [PASSED] drm_test_damage_iter_no_damage_no_crtc
[18:30:36] [PASSED] drm_test_damage_iter_no_damage_no_fb
[18:30:36] [PASSED] drm_test_damage_iter_simple_damage
[18:30:36] [PASSED] drm_test_damage_iter_single_damage
[18:30:36] [PASSED] drm_test_damage_iter_single_damage_intersect_src
[18:30:36] [PASSED] drm_test_damage_iter_single_damage_outside_src
[18:30:36] [PASSED] drm_test_damage_iter_single_damage_fractional_src
[18:30:36] [PASSED] drm_test_damage_iter_single_damage_intersect_fractional_src
[18:30:36] [PASSED] drm_test_damage_iter_single_damage_outside_fractional_src
[18:30:36] [PASSED] drm_test_damage_iter_single_damage_src_moved
[18:30:36] [PASSED] drm_test_damage_iter_single_damage_fractional_src_moved
[18:30:36] [PASSED] drm_test_damage_iter_damage
[18:30:36] [PASSED] drm_test_damage_iter_damage_one_intersect
[18:30:36] [PASSED] drm_test_damage_iter_damage_one_outside
[18:30:36] [PASSED] drm_test_damage_iter_damage_src_moved
[18:30:36] [PASSED] drm_test_damage_iter_damage_not_visible
[18:30:36] ================ [PASSED] drm_damage_helper ================
[18:30:36] ============== drm_dp_mst_helper (3 subtests) ==============
[18:30:36] ============== drm_test_dp_mst_calc_pbn_mode  ==============
[18:30:36] [PASSED] Clock 154000 BPP 30 DSC disabled
[18:30:36] [PASSED] Clock 234000 BPP 30 DSC disabled
[18:30:36] [PASSED] Clock 297000 BPP 24 DSC disabled
[18:30:36] [PASSED] Clock 332880 BPP 24 DSC enabled
[18:30:36] [PASSED] Clock 324540 BPP 24 DSC enabled
[18:30:36] ========== [PASSED] drm_test_dp_mst_calc_pbn_mode ==========
[18:30:36] ============== drm_test_dp_mst_calc_pbn_div  ===============
[18:30:36] [PASSED] Link rate 2000000 lane count 4
[18:30:36] [PASSED] Link rate 2000000 lane count 2
[18:30:36] [PASSED] Link rate 2000000 lane count 1
[18:30:36] [PASSED] Link rate 1350000 lane count 4
[18:30:36] [PASSED] Link rate 1350000 lane count 2
[18:30:36] [PASSED] Link rate 1350000 lane count 1
[18:30:36] [PASSED] Link rate 1000000 lane count 4
[18:30:36] [PASSED] Link rate 1000000 lane count 2
[18:30:36] [PASSED] Link rate 1000000 lane count 1
[18:30:36] [PASSED] Link rate 810000 lane count 4
[18:30:36] [PASSED] Link rate 810000 lane count 2
[18:30:36] [PASSED] Link rate 810000 lane count 1
[18:30:36] [PASSED] Link rate 540000 lane count 4
[18:30:36] [PASSED] Link rate 540000 lane count 2
[18:30:36] [PASSED] Link rate 540000 lane count 1
[18:30:36] [PASSED] Link rate 270000 lane count 4
[18:30:36] [PASSED] Link rate 270000 lane count 2
[18:30:36] [PASSED] Link rate 270000 lane count 1
[18:30:36] [PASSED] Link rate 162000 lane count 4
[18:30:36] [PASSED] Link rate 162000 lane count 2
[18:30:36] [PASSED] Link rate 162000 lane count 1
[18:30:36] ========== [PASSED] drm_test_dp_mst_calc_pbn_div ===========
[18:30:36] ========= drm_test_dp_mst_sideband_msg_req_decode  =========
[18:30:36] [PASSED] DP_ENUM_PATH_RESOURCES with port number
[18:30:36] [PASSED] DP_POWER_UP_PHY with port number
[18:30:36] [PASSED] DP_POWER_DOWN_PHY with port number
[18:30:36] [PASSED] DP_ALLOCATE_PAYLOAD with SDP stream sinks
[18:30:36] [PASSED] DP_ALLOCATE_PAYLOAD with port number
[18:30:36] [PASSED] DP_ALLOCATE_PAYLOAD with VCPI
[18:30:36] [PASSED] DP_ALLOCATE_PAYLOAD with PBN
[18:30:36] [PASSED] DP_QUERY_PAYLOAD with port number
[18:30:36] [PASSED] DP_QUERY_PAYLOAD with VCPI
[18:30:36] [PASSED] DP_REMOTE_DPCD_READ with port number
[18:30:36] [PASSED] DP_REMOTE_DPCD_READ with DPCD address
[18:30:36] [PASSED] DP_REMOTE_DPCD_READ with max number of bytes
[18:30:36] [PASSED] DP_REMOTE_DPCD_WRITE with port number
[18:30:36] [PASSED] DP_REMOTE_DPCD_WRITE with DPCD address
[18:30:36] [PASSED] DP_REMOTE_DPCD_WRITE with data array
[18:30:36] [PASSED] DP_REMOTE_I2C_READ with port number
[18:30:36] [PASSED] DP_REMOTE_I2C_READ with I2C device ID
[18:30:36] [PASSED] DP_REMOTE_I2C_READ with transactions array
[18:30:36] [PASSED] DP_REMOTE_I2C_WRITE with port number
[18:30:36] [PASSED] DP_REMOTE_I2C_WRITE with I2C device ID
[18:30:36] [PASSED] DP_REMOTE_I2C_WRITE with data array
[18:30:36] [PASSED] DP_QUERY_STREAM_ENC_STATUS with stream ID
[18:30:36] [PASSED] DP_QUERY_STREAM_ENC_STATUS with client ID
[18:30:36] [PASSED] DP_QUERY_STREAM_ENC_STATUS with stream event
[18:30:36] [PASSED] DP_QUERY_STREAM_ENC_STATUS with valid stream event
[18:30:36] [PASSED] DP_QUERY_STREAM_ENC_STATUS with stream behavior
[18:30:36] [PASSED] DP_QUERY_STREAM_ENC_STATUS with a valid stream behavior
[18:30:36] ===== [PASSED] drm_test_dp_mst_sideband_msg_req_decode =====
[18:30:36] ================ [PASSED] drm_dp_mst_helper ================
[18:30:36] ================== drm_exec (7 subtests) ===================
[18:30:36] [PASSED] sanitycheck
[18:30:36] [PASSED] test_lock
[18:30:36] [PASSED] test_lock_unlock
[18:30:36] [PASSED] test_duplicates
[18:30:36] [PASSED] test_prepare
[18:30:36] [PASSED] test_prepare_array
[18:30:36] [PASSED] test_multiple_loops
[18:30:36] ==================== [PASSED] drm_exec =====================
[18:30:36] =========== drm_format_helper_test (17 subtests) ===========
[18:30:36] ============== drm_test_fb_xrgb8888_to_gray8  ==============
[18:30:36] [PASSED] single_pixel_source_buffer
[18:30:36] [PASSED] single_pixel_clip_rectangle
[18:30:36] [PASSED] well_known_colors
[18:30:36] [PASSED] destination_pitch
[18:30:36] ========== [PASSED] drm_test_fb_xrgb8888_to_gray8 ==========
[18:30:36] ============= drm_test_fb_xrgb8888_to_rgb332  ==============
[18:30:36] [PASSED] single_pixel_source_buffer
[18:30:36] [PASSED] single_pixel_clip_rectangle
[18:30:36] [PASSED] well_known_colors
[18:30:36] [PASSED] destination_pitch
[18:30:36] ========= [PASSED] drm_test_fb_xrgb8888_to_rgb332 ==========
[18:30:36] ============= drm_test_fb_xrgb8888_to_rgb565  ==============
[18:30:36] [PASSED] single_pixel_source_buffer
[18:30:36] [PASSED] single_pixel_clip_rectangle
[18:30:36] [PASSED] well_known_colors
[18:30:36] [PASSED] destination_pitch
[18:30:36] ========= [PASSED] drm_test_fb_xrgb8888_to_rgb565 ==========
[18:30:36] ============ drm_test_fb_xrgb8888_to_xrgb1555  =============
[18:30:36] [PASSED] single_pixel_source_buffer
[18:30:36] [PASSED] single_pixel_clip_rectangle
[18:30:36] [PASSED] well_known_colors
[18:30:36] [PASSED] destination_pitch
[18:30:36] ======== [PASSED] drm_test_fb_xrgb8888_to_xrgb1555 =========
[18:30:36] ============ drm_test_fb_xrgb8888_to_argb1555  =============
[18:30:36] [PASSED] single_pixel_source_buffer
[18:30:36] [PASSED] single_pixel_clip_rectangle
[18:30:36] [PASSED] well_known_colors
[18:30:36] [PASSED] destination_pitch
[18:30:36] ======== [PASSED] drm_test_fb_xrgb8888_to_argb1555 =========
[18:30:36] ============ drm_test_fb_xrgb8888_to_rgba5551  =============
[18:30:36] [PASSED] single_pixel_source_buffer
[18:30:36] [PASSED] single_pixel_clip_rectangle
[18:30:36] [PASSED] well_known_colors
[18:30:36] [PASSED] destination_pitch
[18:30:36] ======== [PASSED] drm_test_fb_xrgb8888_to_rgba5551 =========
[18:30:36] ============= drm_test_fb_xrgb8888_to_rgb888  ==============
[18:30:36] [PASSED] single_pixel_source_buffer
[18:30:36] [PASSED] single_pixel_clip_rectangle
[18:30:36] [PASSED] well_known_colors
[18:30:36] [PASSED] destination_pitch
[18:30:36] ========= [PASSED] drm_test_fb_xrgb8888_to_rgb888 ==========
[18:30:36] ============= drm_test_fb_xrgb8888_to_bgr888  ==============
[18:30:36] [PASSED] single_pixel_source_buffer
[18:30:36] [PASSED] single_pixel_clip_rectangle
[18:30:36] [PASSED] well_known_colors
[18:30:36] [PASSED] destination_pitch
[18:30:36] ========= [PASSED] drm_test_fb_xrgb8888_to_bgr888 ==========
[18:30:36] ============ drm_test_fb_xrgb8888_to_argb8888  =============
[18:30:36] [PASSED] single_pixel_source_buffer
[18:30:36] [PASSED] single_pixel_clip_rectangle
[18:30:36] [PASSED] well_known_colors
[18:30:36] [PASSED] destination_pitch
[18:30:36] ======== [PASSED] drm_test_fb_xrgb8888_to_argb8888 =========
[18:30:36] =========== drm_test_fb_xrgb8888_to_xrgb2101010  ===========
[18:30:36] [PASSED] single_pixel_source_buffer
[18:30:36] [PASSED] single_pixel_clip_rectangle
[18:30:36] [PASSED] well_known_colors
[18:30:36] [PASSED] destination_pitch
[18:30:36] ======= [PASSED] drm_test_fb_xrgb8888_to_xrgb2101010 =======
[18:30:36] =========== drm_test_fb_xrgb8888_to_argb2101010  ===========
[18:30:36] [PASSED] single_pixel_source_buffer
[18:30:36] [PASSED] single_pixel_clip_rectangle
[18:30:36] [PASSED] well_known_colors
[18:30:36] [PASSED] destination_pitch
[18:30:36] ======= [PASSED] drm_test_fb_xrgb8888_to_argb2101010 =======
[18:30:36] ============== drm_test_fb_xrgb8888_to_mono  ===============
[18:30:36] [PASSED] single_pixel_source_buffer
[18:30:36] [PASSED] single_pixel_clip_rectangle
[18:30:36] [PASSED] well_known_colors
[18:30:36] [PASSED] destination_pitch
[18:30:36] ========== [PASSED] drm_test_fb_xrgb8888_to_mono ===========
[18:30:36] ==================== drm_test_fb_swab  =====================
[18:30:36] [PASSED] single_pixel_source_buffer
[18:30:36] [PASSED] single_pixel_clip_rectangle
[18:30:36] [PASSED] well_known_colors
[18:30:36] [PASSED] destination_pitch
[18:30:36] ================ [PASSED] drm_test_fb_swab =================
[18:30:36] ============ drm_test_fb_xrgb8888_to_xbgr8888  =============
[18:30:36] [PASSED] single_pixel_source_buffer
[18:30:36] [PASSED] single_pixel_clip_rectangle
[18:30:36] [PASSED] well_known_colors
[18:30:36] [PASSED] destination_pitch
[18:30:36] ======== [PASSED] drm_test_fb_xrgb8888_to_xbgr8888 =========
[18:30:36] ============ drm_test_fb_xrgb8888_to_abgr8888  =============
[18:30:36] [PASSED] single_pixel_source_buffer
[18:30:36] [PASSED] single_pixel_clip_rectangle
[18:30:36] [PASSED] well_known_colors
[18:30:36] [PASSED] destination_pitch
[18:30:36] ======== [PASSED] drm_test_fb_xrgb8888_to_abgr8888 =========
[18:30:36] ================= drm_test_fb_clip_offset  =================
[18:30:36] [PASSED] pass through
[18:30:36] [PASSED] horizontal offset
[18:30:36] [PASSED] vertical offset
[18:30:36] [PASSED] horizontal and vertical offset
[18:30:36] [PASSED] horizontal offset (custom pitch)
[18:30:36] [PASSED] vertical offset (custom pitch)
[18:30:36] [PASSED] horizontal and vertical offset (custom pitch)
[18:30:36] ============= [PASSED] drm_test_fb_clip_offset =============
[18:30:36] =================== drm_test_fb_memcpy  ====================
[18:30:36] [PASSED] single_pixel_source_buffer: XR24 little-endian (0x34325258)
[18:30:36] [PASSED] single_pixel_source_buffer: XRA8 little-endian (0x38415258)
[18:30:36] [PASSED] single_pixel_source_buffer: YU24 little-endian (0x34325559)
[18:30:36] [PASSED] single_pixel_clip_rectangle: XB24 little-endian (0x34324258)
[18:30:36] [PASSED] single_pixel_clip_rectangle: XRA8 little-endian (0x38415258)
[18:30:36] [PASSED] single_pixel_clip_rectangle: YU24 little-endian (0x34325559)
[18:30:36] [PASSED] well_known_colors: XB24 little-endian (0x34324258)
[18:30:36] [PASSED] well_known_colors: XRA8 little-endian (0x38415258)
[18:30:36] [PASSED] well_known_colors: YU24 little-endian (0x34325559)
[18:30:36] [PASSED] destination_pitch: XB24 little-endian (0x34324258)
[18:30:36] [PASSED] destination_pitch: XRA8 little-endian (0x38415258)
[18:30:36] [PASSED] destination_pitch: YU24 little-endian (0x34325559)
[18:30:36] =============== [PASSED] drm_test_fb_memcpy ================
[18:30:36] ============= [PASSED] drm_format_helper_test ==============
[18:30:36] ================= drm_format (18 subtests) =================
[18:30:36] [PASSED] drm_test_format_block_width_invalid
[18:30:36] [PASSED] drm_test_format_block_width_one_plane
[18:30:36] [PASSED] drm_test_format_block_width_two_plane
[18:30:36] [PASSED] drm_test_format_block_width_three_plane
[18:30:36] [PASSED] drm_test_format_block_width_tiled
[18:30:36] [PASSED] drm_test_format_block_height_invalid
[18:30:36] [PASSED] drm_test_format_block_height_one_plane
[18:30:36] [PASSED] drm_test_format_block_height_two_plane
[18:30:36] [PASSED] drm_test_format_block_height_three_plane
[18:30:36] [PASSED] drm_test_format_block_height_tiled
[18:30:36] [PASSED] drm_test_format_min_pitch_invalid
[18:30:36] [PASSED] drm_test_format_min_pitch_one_plane_8bpp
[18:30:36] [PASSED] drm_test_format_min_pitch_one_plane_16bpp
[18:30:36] [PASSED] drm_test_format_min_pitch_one_plane_24bpp
[18:30:36] [PASSED] drm_test_format_min_pitch_one_plane_32bpp
[18:30:36] [PASSED] drm_test_format_min_pitch_two_plane
[18:30:36] [PASSED] drm_test_format_min_pitch_three_plane_8bpp
[18:30:36] [PASSED] drm_test_format_min_pitch_tiled
[18:30:36] =================== [PASSED] drm_format ====================
[18:30:36] ============== drm_framebuffer (10 subtests) ===============
[18:30:36] ========== drm_test_framebuffer_check_src_coords  ==========
[18:30:36] [PASSED] Success: source fits into fb
[18:30:36] [PASSED] Fail: overflowing fb with x-axis coordinate
[18:30:36] [PASSED] Fail: overflowing fb with y-axis coordinate
[18:30:36] [PASSED] Fail: overflowing fb with source width
[18:30:36] [PASSED] Fail: overflowing fb with source height
[18:30:36] ====== [PASSED] drm_test_framebuffer_check_src_coords ======
[18:30:36] [PASSED] drm_test_framebuffer_cleanup
[18:30:36] =============== drm_test_framebuffer_create  ===============
[18:30:36] [PASSED] ABGR8888 normal sizes
[18:30:36] [PASSED] ABGR8888 max sizes
[18:30:36] [PASSED] ABGR8888 pitch greater than min required
[18:30:36] [PASSED] ABGR8888 pitch less than min required
[18:30:36] [PASSED] ABGR8888 Invalid width
[18:30:36] [PASSED] ABGR8888 Invalid buffer handle
[18:30:36] [PASSED] No pixel format
[18:30:36] [PASSED] ABGR8888 Width 0
[18:30:36] [PASSED] ABGR8888 Height 0
[18:30:36] [PASSED] ABGR8888 Out of bound height * pitch combination
[18:30:36] [PASSED] ABGR8888 Large buffer offset
[18:30:36] [PASSED] ABGR8888 Buffer offset for inexistent plane
[18:30:36] [PASSED] ABGR8888 Invalid flag
[18:30:36] [PASSED] ABGR8888 Set DRM_MODE_FB_MODIFIERS without modifiers
[18:30:36] [PASSED] ABGR8888 Valid buffer modifier
[18:30:36] [PASSED] ABGR8888 Invalid buffer modifier(DRM_FORMAT_MOD_SAMSUNG_64_32_TILE)
[18:30:36] [PASSED] ABGR8888 Extra pitches without DRM_MODE_FB_MODIFIERS
[18:30:36] [PASSED] ABGR8888 Extra pitches with DRM_MODE_FB_MODIFIERS
[18:30:36] [PASSED] NV12 Normal sizes
[18:30:36] [PASSED] NV12 Max sizes
[18:30:36] [PASSED] NV12 Invalid pitch
[18:30:36] [PASSED] NV12 Invalid modifier/missing DRM_MODE_FB_MODIFIERS flag
[18:30:36] [PASSED] NV12 different  modifier per-plane
[18:30:36] [PASSED] NV12 with DRM_FORMAT_MOD_SAMSUNG_64_32_TILE
[18:30:36] [PASSED] NV12 Valid modifiers without DRM_MODE_FB_MODIFIERS
[18:30:36] [PASSED] NV12 Modifier for inexistent plane
[18:30:36] [PASSED] NV12 Handle for inexistent plane
[18:30:36] [PASSED] NV12 Handle for inexistent plane without DRM_MODE_FB_MODIFIERS
[18:30:36] [PASSED] YVU420 DRM_MODE_FB_MODIFIERS set without modifier
[18:30:36] [PASSED] YVU420 Normal sizes
[18:30:36] [PASSED] YVU420 Max sizes
[18:30:36] [PASSED] YVU420 Invalid pitch
[18:30:36] [PASSED] YVU420 Different pitches
[18:30:36] [PASSED] YVU420 Different buffer offsets/pitches
[18:30:36] [PASSED] YVU420 Modifier set just for plane 0, without DRM_MODE_FB_MODIFIERS
[18:30:36] [PASSED] YVU420 Modifier set just for planes 0, 1, without DRM_MODE_FB_MODIFIERS
[18:30:36] [PASSED] YVU420 Modifier set just for plane 0, 1, with DRM_MODE_FB_MODIFIERS
[18:30:36] [PASSED] YVU420 Valid modifier
[18:30:36] [PASSED] YVU420 Different modifiers per plane
[18:30:36] [PASSED] YVU420 Modifier for inexistent plane
[18:30:36] [PASSED] YUV420_10BIT Invalid modifier(DRM_FORMAT_MOD_LINEAR)
[18:30:36] [PASSED] X0L2 Normal sizes
[18:30:36] [PASSED] X0L2 Max sizes
[18:30:36] [PASSED] X0L2 Invalid pitch
[18:30:36] [PASSED] X0L2 Pitch greater than minimum required
[18:30:36] [PASSED] X0L2 Handle for inexistent plane
[18:30:36] [PASSED] X0L2 Offset for inexistent plane, without DRM_MODE_FB_MODIFIERS set
[18:30:36] [PASSED] X0L2 Modifier without DRM_MODE_FB_MODIFIERS set
[18:30:36] [PASSED] X0L2 Valid modifier
[18:30:36] [PASSED] X0L2 Modifier for inexistent plane
[18:30:36] =========== [PASSED] drm_test_framebuffer_create ===========
[18:30:36] [PASSED] drm_test_framebuffer_free
[18:30:36] [PASSED] drm_test_framebuffer_init
[18:30:36] [PASSED] drm_test_framebuffer_init_bad_format
[18:30:36] [PASSED] drm_test_framebuffer_init_dev_mismatch
[18:30:36] [PASSED] drm_test_framebuffer_lookup
[18:30:36] [PASSED] drm_test_framebuffer_lookup_inexistent
[18:30:36] [PASSED] drm_test_framebuffer_modifiers_not_supported
[18:30:36] ================= [PASSED] drm_framebuffer =================
[18:30:36] ================ drm_gem_shmem (8 subtests) ================
[18:30:36] [PASSED] drm_gem_shmem_test_obj_create
[18:30:36] [PASSED] drm_gem_shmem_test_obj_create_private
[18:30:36] [PASSED] drm_gem_shmem_test_pin_pages
[18:30:36] [PASSED] drm_gem_shmem_test_vmap
[18:30:36] [PASSED] drm_gem_shmem_test_get_sg_table
[18:30:36] [PASSED] drm_gem_shmem_test_get_pages_sgt
[18:30:36] [PASSED] drm_gem_shmem_test_madvise
[18:30:36] [PASSED] drm_gem_shmem_test_purge
[18:30:36] ================== [PASSED] drm_gem_shmem ==================
[18:30:36] === drm_atomic_helper_connector_hdmi_check (29 subtests) ===
[18:30:36] [PASSED] drm_test_check_broadcast_rgb_auto_cea_mode
[18:30:36] [PASSED] drm_test_check_broadcast_rgb_auto_cea_mode_vic_1
[18:30:36] [PASSED] drm_test_check_broadcast_rgb_full_cea_mode
[18:30:36] [PASSED] drm_test_check_broadcast_rgb_full_cea_mode_vic_1
[18:30:36] [PASSED] drm_test_check_broadcast_rgb_limited_cea_mode
[18:30:36] [PASSED] drm_test_check_broadcast_rgb_limited_cea_mode_vic_1
[18:30:36] ====== drm_test_check_broadcast_rgb_cea_mode_yuv420  =======
[18:30:36] [PASSED] Automatic
[18:30:36] [PASSED] Full
[18:30:36] [PASSED] Limited 16:235
[18:30:36] == [PASSED] drm_test_check_broadcast_rgb_cea_mode_yuv420 ===
[18:30:36] [PASSED] drm_test_check_broadcast_rgb_crtc_mode_changed
[18:30:36] [PASSED] drm_test_check_broadcast_rgb_crtc_mode_not_changed
[18:30:36] [PASSED] drm_test_check_disable_connector
[18:30:36] [PASSED] drm_test_check_hdmi_funcs_reject_rate
[18:30:36] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_rgb
[18:30:36] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_yuv420
[18:30:36] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_ignore_yuv422
[18:30:36] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_ignore_yuv420
[18:30:36] [PASSED] drm_test_check_driver_unsupported_fallback_yuv420
[18:30:36] [PASSED] drm_test_check_output_bpc_crtc_mode_changed
[18:30:36] [PASSED] drm_test_check_output_bpc_crtc_mode_not_changed
[18:30:36] [PASSED] drm_test_check_output_bpc_dvi
[18:30:36] [PASSED] drm_test_check_output_bpc_format_vic_1
[18:30:36] [PASSED] drm_test_check_output_bpc_format_display_8bpc_only
[18:30:36] [PASSED] drm_test_check_output_bpc_format_display_rgb_only
[18:30:36] [PASSED] drm_test_check_output_bpc_format_driver_8bpc_only
[18:30:36] [PASSED] drm_test_check_output_bpc_format_driver_rgb_only
[18:30:36] [PASSED] drm_test_check_tmds_char_rate_rgb_8bpc
[18:30:36] [PASSED] drm_test_check_tmds_char_rate_rgb_10bpc
[18:30:36] [PASSED] drm_test_check_tmds_char_rate_rgb_12bpc
[18:30:36] ============ drm_test_check_hdmi_color_format  =============
[18:30:36] [PASSED] AUTO -> RGB
[18:30:36] [PASSED] YCBCR422 -> YUV422
[18:30:36] [PASSED] YCBCR420 -> YUV420
[18:30:36] [PASSED] YCBCR444 -> YUV444
[18:30:36] [PASSED] RGB -> RGB
[18:30:36] ======== [PASSED] drm_test_check_hdmi_color_format =========
[18:30:36] ======== drm_test_check_hdmi_color_format_420_only  ========
[18:30:36] [PASSED] RGB should fail
[18:30:36] [PASSED] YUV444 should fail
[18:30:36] [PASSED] YUV422 should fail
[18:30:36] [PASSED] YUV420 should work
[18:30:36] ==== [PASSED] drm_test_check_hdmi_color_format_420_only ====
[18:30:36] ===== [PASSED] drm_atomic_helper_connector_hdmi_check ======
[18:30:36] === drm_atomic_helper_connector_hdmi_reset (6 subtests) ====
[18:30:36] [PASSED] drm_test_check_broadcast_rgb_value
[18:30:36] [PASSED] drm_test_check_bpc_8_value
[18:30:36] [PASSED] drm_test_check_bpc_10_value
[18:30:36] [PASSED] drm_test_check_bpc_12_value
[18:30:36] [PASSED] drm_test_check_format_value
[18:30:36] [PASSED] drm_test_check_tmds_char_value
[18:30:36] ===== [PASSED] drm_atomic_helper_connector_hdmi_reset ======
[18:30:36] = drm_atomic_helper_connector_hdmi_mode_valid (7 subtests) =
[18:30:36] [PASSED] drm_test_check_mode_valid
[18:30:36] [PASSED] drm_test_check_mode_valid_reject
[18:30:36] [PASSED] drm_test_check_mode_valid_reject_rate
[18:30:36] [PASSED] drm_test_check_mode_valid_reject_max_clock
[18:30:36] [PASSED] drm_test_check_mode_valid_yuv420_only_max_clock
[18:30:36] [PASSED] drm_test_check_mode_valid_reject_yuv420_only_connector
[18:30:36] [PASSED] drm_test_check_mode_valid_accept_yuv420_also_connector_rgb
[18:30:36] === [PASSED] drm_atomic_helper_connector_hdmi_mode_valid ===
[18:30:36] = drm_atomic_helper_connector_hdmi_infoframes (5 subtests) =
[18:30:36] [PASSED] drm_test_check_infoframes
[18:30:36] [PASSED] drm_test_check_reject_avi_infoframe
[18:30:36] [PASSED] drm_test_check_reject_hdr_infoframe_bpc_8
[18:30:36] [PASSED] drm_test_check_reject_hdr_infoframe_bpc_10
[18:30:36] [PASSED] drm_test_check_reject_audio_infoframe
[18:30:36] === [PASSED] drm_atomic_helper_connector_hdmi_infoframes ===
[18:30:36] ================= drm_managed (2 subtests) =================
[18:30:36] [PASSED] drm_test_managed_release_action
[18:30:36] [PASSED] drm_test_managed_run_action
[18:30:36] =================== [PASSED] drm_managed ===================
[18:30:36] =================== drm_mm (6 subtests) ====================
[18:30:36] [PASSED] drm_test_mm_init
[18:30:36] [PASSED] drm_test_mm_debug
[18:30:36] [PASSED] drm_test_mm_align32
[18:30:36] [PASSED] drm_test_mm_align64
[18:30:36] [PASSED] drm_test_mm_lowest
[18:30:36] [PASSED] drm_test_mm_highest
[18:30:36] ===================== [PASSED] drm_mm ======================
[18:30:36] ============= drm_modes_analog_tv (5 subtests) =============
[18:30:36] [PASSED] drm_test_modes_analog_tv_mono_576i
[18:30:36] [PASSED] drm_test_modes_analog_tv_ntsc_480i
[18:30:36] [PASSED] drm_test_modes_analog_tv_ntsc_480i_inlined
[18:30:36] [PASSED] drm_test_modes_analog_tv_pal_576i
[18:30:36] [PASSED] drm_test_modes_analog_tv_pal_576i_inlined
[18:30:36] =============== [PASSED] drm_modes_analog_tv ===============
[18:30:36] ============== drm_plane_helper (2 subtests) ===============
[18:30:36] =============== drm_test_check_plane_state  ================
[18:30:36] [PASSED] clipping_simple
[18:30:36] [PASSED] clipping_rotate_reflect
[18:30:36] [PASSED] positioning_simple
[18:30:36] [PASSED] upscaling
[18:30:36] [PASSED] downscaling
[18:30:36] [PASSED] rounding1
[18:30:36] [PASSED] rounding2
[18:30:36] [PASSED] rounding3
[18:30:36] [PASSED] rounding4
[18:30:36] =========== [PASSED] drm_test_check_plane_state ============
[18:30:36] =========== drm_test_check_invalid_plane_state  ============
[18:30:36] [PASSED] positioning_invalid
[18:30:36] [PASSED] upscaling_invalid
[18:30:36] [PASSED] downscaling_invalid
[18:30:36] ======= [PASSED] drm_test_check_invalid_plane_state ========
[18:30:36] ================ [PASSED] drm_plane_helper =================
[18:30:36] ====== drm_connector_helper_tv_get_modes (1 subtest) =======
[18:30:36] ====== drm_test_connector_helper_tv_get_modes_check  =======
[18:30:36] [PASSED] None
[18:30:36] [PASSED] PAL
[18:30:36] [PASSED] NTSC
[18:30:36] [PASSED] Both, NTSC Default
[18:30:36] [PASSED] Both, PAL Default
[18:30:36] [PASSED] Both, NTSC Default, with PAL on command-line
[18:30:36] [PASSED] Both, PAL Default, with NTSC on command-line
[18:30:36] == [PASSED] drm_test_connector_helper_tv_get_modes_check ===
[18:30:36] ======== [PASSED] drm_connector_helper_tv_get_modes ========
[18:30:36] ================== drm_rect (9 subtests) ===================
[18:30:36] [PASSED] drm_test_rect_clip_scaled_div_by_zero
[18:30:36] [PASSED] drm_test_rect_clip_scaled_not_clipped
[18:30:36] [PASSED] drm_test_rect_clip_scaled_clipped
[18:30:36] [PASSED] drm_test_rect_clip_scaled_signed_vs_unsigned
[18:30:36] ================= drm_test_rect_intersect  =================
[18:30:36] [PASSED] top-left x bottom-right: 2x2+1+1 x 2x2+0+0
[18:30:36] [PASSED] top-right x bottom-left: 2x2+0+0 x 2x2+1-1
[18:30:36] [PASSED] bottom-left x top-right: 2x2+1-1 x 2x2+0+0
[18:30:36] [PASSED] bottom-right x top-left: 2x2+0+0 x 2x2+1+1
[18:30:36] [PASSED] right x left: 2x1+0+0 x 3x1+1+0
[18:30:36] [PASSED] left x right: 3x1+1+0 x 2x1+0+0
[18:30:36] [PASSED] up x bottom: 1x2+0+0 x 1x3+0-1
[18:30:36] [PASSED] bottom x up: 1x3+0-1 x 1x2+0+0
[18:30:36] [PASSED] touching corner: 1x1+0+0 x 2x2+1+1
[18:30:36] [PASSED] touching side: 1x1+0+0 x 1x1+1+0
[18:30:36] [PASSED] equal rects: 2x2+0+0 x 2x2+0+0
[18:30:36] [PASSED] inside another: 2x2+0+0 x 1x1+1+1
[18:30:36] [PASSED] far away: 1x1+0+0 x 1x1+3+6
[18:30:36] [PASSED] points intersecting: 0x0+5+10 x 0x0+5+10
[18:30:36] [PASSED] points not intersecting: 0x0+0+0 x 0x0+5+10
[18:30:36] ============= [PASSED] drm_test_rect_intersect =============
[18:30:36] ================ drm_test_rect_calc_hscale  ================
[18:30:36] [PASSED] normal use
[18:30:36] [PASSED] out of max range
[18:30:36] [PASSED] out of min range
[18:30:36] [PASSED] zero dst
[18:30:36] [PASSED] negative src
[18:30:36] [PASSED] negative dst
[18:30:36] ============ [PASSED] drm_test_rect_calc_hscale ============
[18:30:36] ================ drm_test_rect_calc_vscale  ================
[18:30:36] [PASSED] normal use
[18:30:36] [PASSED] out of max range
[18:30:36] [PASSED] out of min range
[18:30:36] [PASSED] zero dst
[18:30:36] [PASSED] negative src
[18:30:36] [PASSED] negative dst
[18:30:36] ============ [PASSED] drm_test_rect_calc_vscale ============
[18:30:36] ================== drm_test_rect_rotate  ===================
[18:30:36] [PASSED] reflect-x
[18:30:36] [PASSED] reflect-y
[18:30:36] [PASSED] rotate-0
[18:30:36] [PASSED] rotate-90
[18:30:36] [PASSED] rotate-180
[18:30:36] [PASSED] rotate-270
[18:30:36] ============== [PASSED] drm_test_rect_rotate ===============
[18:30:36] ================ drm_test_rect_rotate_inv  =================
[18:30:36] [PASSED] reflect-x
[18:30:36] [PASSED] reflect-y
[18:30:36] [PASSED] rotate-0
[18:30:36] [PASSED] rotate-90
[18:30:36] [PASSED] rotate-180
[18:30:36] [PASSED] rotate-270
[18:30:36] ============ [PASSED] drm_test_rect_rotate_inv =============
[18:30:36] ==================== [PASSED] drm_rect =====================
[18:30:36] ============ drm_sysfb_modeset_test (1 subtest) ============
[18:30:36] ============ drm_test_sysfb_build_fourcc_list  =============
[18:30:36] [PASSED] no native formats
[18:30:36] [PASSED] XRGB8888 as native format
[18:30:36] [PASSED] remove duplicates
[18:30:36] [PASSED] convert alpha formats
[18:30:36] [PASSED] random formats
[18:30:36] ======== [PASSED] drm_test_sysfb_build_fourcc_list =========
[18:30:36] ============= [PASSED] drm_sysfb_modeset_test ==============
[18:30:36] ================== drm_fixp (2 subtests) ===================
[18:30:36] [PASSED] drm_test_int2fixp
[18:30:36] [PASSED] drm_test_sm2fixp
[18:30:36] ==================== [PASSED] drm_fixp =====================
[18:30:36] ============================================================
[18:30:36] Testing complete. Ran 637 tests: passed: 637
[18:30:36] Elapsed time: 27.344s total, 1.855s configuring, 25.321s building, 0.145s running

+ /kernel/tools/testing/kunit/kunit.py run --kunitconfig /kernel/drivers/gpu/drm/ttm/tests/.kunitconfig
[18:30:36] Configuring KUnit Kernel ...
Regenerating .config ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
[18:30:38] Building KUnit Kernel ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
Building with:
$ make all compile_commands.json scripts_gdb ARCH=um O=.kunit --jobs=48
[18:30:48] Starting KUnit Kernel (1/1)...
[18:30:48] ============================================================
Running tests with:
$ .kunit/linux kunit.enable=1 mem=1G console=tty kunit_shutdown=halt
[18:30:48] ================= ttm_device (5 subtests) ==================
[18:30:48] [PASSED] ttm_device_init_basic
[18:30:48] [PASSED] ttm_device_init_multiple
[18:30:48] [PASSED] ttm_device_fini_basic
[18:30:48] [PASSED] ttm_device_init_no_vma_man
[18:30:48] ================== ttm_device_init_pools  ==================
[18:30:48] [PASSED] No DMA allocations, no DMA32 required
[18:30:48] [PASSED] DMA allocations, DMA32 required
[18:30:48] [PASSED] No DMA allocations, DMA32 required
[18:30:48] [PASSED] DMA allocations, no DMA32 required
[18:30:48] ============== [PASSED] ttm_device_init_pools ==============
[18:30:48] =================== [PASSED] ttm_device ====================
[18:30:48] ================== ttm_pool (8 subtests) ===================
[18:30:48] ================== ttm_pool_alloc_basic  ===================
[18:30:48] [PASSED] One page
[18:30:48] [PASSED] More than one page
[18:30:48] [PASSED] Above the allocation limit
[18:30:48] [PASSED] One page, with coherent DMA mappings enabled
[18:30:48] [PASSED] Above the allocation limit, with coherent DMA mappings enabled
[18:30:48] ============== [PASSED] ttm_pool_alloc_basic ===============
[18:30:48] ============== ttm_pool_alloc_basic_dma_addr  ==============
[18:30:48] [PASSED] One page
[18:30:48] [PASSED] More than one page
[18:30:48] [PASSED] Above the allocation limit
[18:30:48] [PASSED] One page, with coherent DMA mappings enabled
[18:30:48] [PASSED] Above the allocation limit, with coherent DMA mappings enabled
[18:30:48] ========== [PASSED] ttm_pool_alloc_basic_dma_addr ==========
[18:30:48] [PASSED] ttm_pool_alloc_order_caching_match
[18:30:48] [PASSED] ttm_pool_alloc_caching_mismatch
[18:30:48] [PASSED] ttm_pool_alloc_order_mismatch
[18:30:48] [PASSED] ttm_pool_free_dma_alloc
[18:30:48] [PASSED] ttm_pool_free_no_dma_alloc
[18:30:48] [PASSED] ttm_pool_fini_basic
[18:30:48] ==================== [PASSED] ttm_pool =====================
[18:30:48] ================ ttm_resource (8 subtests) =================
[18:30:48] ================= ttm_resource_init_basic  =================
[18:30:48] [PASSED] Init resource in TTM_PL_SYSTEM
[18:30:48] [PASSED] Init resource in TTM_PL_VRAM
[18:30:48] [PASSED] Init resource in a private placement
[18:30:48] [PASSED] Init resource in TTM_PL_SYSTEM, set placement flags
[18:30:48] ============= [PASSED] ttm_resource_init_basic =============
[18:30:48] [PASSED] ttm_resource_init_pinned
[18:30:48] [PASSED] ttm_resource_fini_basic
[18:30:48] [PASSED] ttm_resource_manager_init_basic
[18:30:48] [PASSED] ttm_resource_manager_usage_basic
[18:30:48] [PASSED] ttm_resource_manager_set_used_basic
[18:30:48] [PASSED] ttm_sys_man_alloc_basic
[18:30:48] [PASSED] ttm_sys_man_free_basic
[18:30:48] ================== [PASSED] ttm_resource ===================
[18:30:48] =================== ttm_tt (15 subtests) ===================
[18:30:48] ==================== ttm_tt_init_basic  ====================
[18:30:48] [PASSED] Page-aligned size
[18:30:48] [PASSED] Extra pages requested
[18:30:48] ================ [PASSED] ttm_tt_init_basic ================
[18:30:48] [PASSED] ttm_tt_init_misaligned
[18:30:48] [PASSED] ttm_tt_fini_basic
[18:30:48] [PASSED] ttm_tt_fini_sg
[18:30:48] [PASSED] ttm_tt_fini_shmem
[18:30:48] [PASSED] ttm_tt_create_basic
[18:30:48] [PASSED] ttm_tt_create_invalid_bo_type
[18:30:48] [PASSED] ttm_tt_create_ttm_exists
[18:30:48] [PASSED] ttm_tt_create_failed
[18:30:48] [PASSED] ttm_tt_destroy_basic
[18:30:48] [PASSED] ttm_tt_populate_null_ttm
[18:30:48] [PASSED] ttm_tt_populate_populated_ttm
[18:30:48] [PASSED] ttm_tt_unpopulate_basic
[18:30:48] [PASSED] ttm_tt_unpopulate_empty_ttm
[18:30:48] [PASSED] ttm_tt_swapin_basic
[18:30:48] ===================== [PASSED] ttm_tt ======================
[18:30:48] =================== ttm_bo (14 subtests) ===================
[18:30:48] =========== ttm_bo_reserve_optimistic_no_ticket  ===========
[18:30:48] [PASSED] Cannot be interrupted and sleeps
[18:30:48] [PASSED] Cannot be interrupted, locks straight away
[18:30:48] [PASSED] Can be interrupted, sleeps
[18:30:48] ======= [PASSED] ttm_bo_reserve_optimistic_no_ticket =======
[18:30:48] [PASSED] ttm_bo_reserve_locked_no_sleep
[18:30:48] [PASSED] ttm_bo_reserve_no_wait_ticket
[18:30:48] [PASSED] ttm_bo_reserve_double_resv
[18:30:48] [PASSED] ttm_bo_reserve_interrupted
[18:30:48] [PASSED] ttm_bo_reserve_deadlock
[18:30:48] [PASSED] ttm_bo_unreserve_basic
[18:30:48] [PASSED] ttm_bo_unreserve_pinned
[18:30:48] [PASSED] ttm_bo_unreserve_bulk
[18:30:48] [PASSED] ttm_bo_fini_basic
[18:30:48] [PASSED] ttm_bo_fini_shared_resv
[18:30:48] [PASSED] ttm_bo_pin_basic
[18:30:48] [PASSED] ttm_bo_pin_unpin_resource
[18:30:48] [PASSED] ttm_bo_multiple_pin_one_unpin
[18:30:48] ===================== [PASSED] ttm_bo ======================
[18:30:48] ============== ttm_bo_validate (22 subtests) ===============
[18:30:48] ============== ttm_bo_init_reserved_sys_man  ===============
[18:30:48] [PASSED] Buffer object for userspace
[18:30:48] [PASSED] Kernel buffer object
[18:30:48] [PASSED] Shared buffer object
[18:30:48] ========== [PASSED] ttm_bo_init_reserved_sys_man ===========
[18:30:48] ============== ttm_bo_init_reserved_mock_man  ==============
[18:30:48] [PASSED] Buffer object for userspace
[18:30:48] [PASSED] Kernel buffer object
[18:30:48] [PASSED] Shared buffer object
[18:30:48] ========== [PASSED] ttm_bo_init_reserved_mock_man ==========
[18:30:48] [PASSED] ttm_bo_init_reserved_resv
[18:30:48] ================== ttm_bo_validate_basic  ==================
[18:30:48] [PASSED] Buffer object for userspace
[18:30:48] [PASSED] Kernel buffer object
[18:30:48] [PASSED] Shared buffer object
[18:30:48] ============== [PASSED] ttm_bo_validate_basic ==============
[18:30:48] [PASSED] ttm_bo_validate_invalid_placement
[18:30:48] ============= ttm_bo_validate_same_placement  ==============
[18:30:48] [PASSED] System manager
[18:30:48] [PASSED] VRAM manager
[18:30:48] ========= [PASSED] ttm_bo_validate_same_placement ==========
[18:30:48] [PASSED] ttm_bo_validate_failed_alloc
[18:30:48] [PASSED] ttm_bo_validate_pinned
[18:30:48] [PASSED] ttm_bo_validate_busy_placement
[18:30:48] ================ ttm_bo_validate_multihop  =================
[18:30:48] [PASSED] Buffer object for userspace
[18:30:48] [PASSED] Kernel buffer object
[18:30:48] [PASSED] Shared buffer object
[18:30:48] ============ [PASSED] ttm_bo_validate_multihop =============
[18:30:48] ========== ttm_bo_validate_no_placement_signaled  ==========
[18:30:48] [PASSED] Buffer object in system domain, no page vector
[18:30:48] [PASSED] Buffer object in system domain with an existing page vector
[18:30:48] ====== [PASSED] ttm_bo_validate_no_placement_signaled ======
[18:30:48] ======== ttm_bo_validate_no_placement_not_signaled  ========
[18:30:48] [PASSED] Buffer object for userspace
[18:30:48] [PASSED] Kernel buffer object
[18:30:48] [PASSED] Shared buffer object
[18:30:48] ==== [PASSED] ttm_bo_validate_no_placement_not_signaled ====
[18:30:48] [PASSED] ttm_bo_validate_move_fence_signaled
[18:30:48] ========= ttm_bo_validate_move_fence_not_signaled  =========
[18:30:48] [PASSED] Waits for GPU
[18:30:48] [PASSED] Tries to lock straight away
[18:30:48] ===== [PASSED] ttm_bo_validate_move_fence_not_signaled =====
[18:30:48] [PASSED] ttm_bo_validate_swapout
[18:30:48] [PASSED] ttm_bo_validate_happy_evict
[18:30:48] [PASSED] ttm_bo_validate_all_pinned_evict
[18:30:48] [PASSED] ttm_bo_validate_allowed_only_evict
[18:30:48] [PASSED] ttm_bo_validate_deleted_evict
[18:30:48] [PASSED] ttm_bo_validate_busy_domain_evict
[18:30:48] [PASSED] ttm_bo_validate_evict_gutting
[18:30:48] [PASSED] ttm_bo_validate_recrusive_evict
[18:30:48] ================= [PASSED] ttm_bo_validate =================
[18:30:48] ============================================================
[18:30:48] Testing complete. Ran 102 tests: passed: 102
[18:30:48] Elapsed time: 11.961s total, 1.837s configuring, 9.909s building, 0.184s running

+ /kernel/tools/testing/kunit/kunit.py run --kunitconfig /kernel/drivers/dma-buf/.kunitconfig
[18:30:48] Configuring KUnit Kernel ...
Regenerating .config ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
[18:30:50] Building KUnit Kernel ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
Building with:
$ make all compile_commands.json scripts_gdb ARCH=um O=.kunit --jobs=48
[18:30:59] Starting KUnit Kernel (1/1)...
[18:30:59] ============================================================
Running tests with:
$ .kunit/linux kunit.enable=1 mem=1G console=tty kunit_shutdown=halt
[18:30:59] =============== dma-buf-fence (12 subtests) ================
[18:30:59] [PASSED] test_sanitycheck
[18:30:59] [PASSED] test_signaling
[18:30:59] [PASSED] test_add_callback
[18:30:59] [PASSED] test_late_add_callback
[18:30:59] [PASSED] test_rm_callback
[18:30:59] [PASSED] test_late_rm_callback
[18:30:59] [PASSED] test_status
[18:30:59] [PASSED] test_error
[18:30:59] [PASSED] test_wait
[18:30:59] [PASSED] test_wait_timeout
[18:30:59] [PASSED] test_stub
[18:30:59] [SKIPPED] test_race_signal_callback (requires at least 2 CPUs)
[18:30:59] ================== [PASSED] dma-buf-fence ==================
[18:30:59] ============ dma-buf-fence-chain (11 subtests) =============
[18:30:59] [PASSED] test_sanitycheck
[18:30:59] [PASSED] test_find_seqno
[18:30:59] [PASSED] test_find_signaled
[18:30:59] [PASSED] test_find_out_of_order
[18:31:04] [PASSED] test_find_gap
[18:31:04] [PASSED] test_find_race
[18:31:04] [PASSED] test_signal_forward
[18:31:04] [PASSED] test_signal_backward
[18:31:04] [PASSED] test_wait_forward
[18:31:04] [PASSED] test_wait_backward
[18:31:04] [PASSED] test_wait_random
[18:31:04] =============== [PASSED] dma-buf-fence-chain ===============
[18:31:04] ============ dma-buf-fence-unwrap (10 subtests) ============
[18:31:04] [PASSED] test_sanitycheck
[18:31:04] [PASSED] test_unwrap_array
[18:31:04] [PASSED] test_unwrap_chain
[18:31:04] [PASSED] test_unwrap_chain_array
[18:31:04] [PASSED] test_unwrap_merge
[18:31:04] [PASSED] test_unwrap_merge_duplicate
[18:31:04] [PASSED] test_unwrap_merge_seqno
[18:31:04] [PASSED] test_unwrap_merge_order
[18:31:04] [PASSED] test_unwrap_merge_complex
[18:31:04] [PASSED] test_unwrap_merge_complex_seqno
[18:31:04] ============== [PASSED] dma-buf-fence-unwrap ===============
[18:31:04] ================ dma-buf-resv (5 subtests) =================
[18:31:04] [PASSED] test_sanitycheck
[18:31:04] ===================== test_signaling  ======================
[18:31:04] [PASSED] kernel
[18:31:04] [PASSED] write
[18:31:04] [PASSED] read
[18:31:04] [PASSED] bookkeep
[18:31:04] ================= [PASSED] test_signaling ==================
[18:31:04] ====================== test_for_each  ======================
[18:31:04] [PASSED] kernel
[18:31:04] [PASSED] write
[18:31:04] [PASSED] read
[18:31:04] [PASSED] bookkeep
[18:31:04] ================== [PASSED] test_for_each ==================
[18:31:04] ================= test_for_each_unlocked  ==================
[18:31:04] [PASSED] kernel
[18:31:04] [PASSED] write
[18:31:04] [PASSED] read
[18:31:04] [PASSED] bookkeep
[18:31:04] ============= [PASSED] test_for_each_unlocked ==============
[18:31:04] ===================== test_get_fences  =====================
[18:31:04] [PASSED] kernel
[18:31:04] [PASSED] write
[18:31:04] [PASSED] read
[18:31:04] [PASSED] bookkeep
[18:31:04] ================= [PASSED] test_get_fences =================
[18:31:04] ================== [PASSED] dma-buf-resv ===================
[18:31:04] ============================================================
[18:31:04] Testing complete. Ran 50 tests: passed: 49, skipped: 1
[18:31:04] Elapsed time: 15.947s total, 1.871s configuring, 8.755s building, 5.286s running

+ cleanup
++ stat -c %u:%g /kernel
+ chown -R 1003:1003 /kernel

✓ Xe.CI.BAT: success for Add CPER logging support for CRI (rev2)

[Patchwork]

[-- Attachment #1: Type: text/plain, Size: 913 bytes --]

== Series Details ==

Series: Add CPER logging support for CRI (rev2)
URL   : https://patchwork.freedesktop.org/series/169692/
State : success

== Summary ==

CI Bug Log - changes from xe-5642-15e2ba2fb6d25c03d89519aec46f8d5be3e118ad_BAT -> xe-pw-169692v2_BAT
====================================================

Summary
-------

  **SUCCESS**

  No regressions found.

  

Participating hosts (13 -> 11)
------------------------------

  Missing    (2): bat-bmg-2 bat-nvls-1 


Changes
-------

  No changes found


Build changes
-------------

  * IGT: IGT_9071 -> IGT_9074
  * Linux: xe-5642-15e2ba2fb6d25c03d89519aec46f8d5be3e118ad -> xe-pw-169692v2

  IGT_9071: 9071
  IGT_9074: 9074
  xe-5642-15e2ba2fb6d25c03d89519aec46f8d5be3e118ad: 15e2ba2fb6d25c03d89519aec46f8d5be3e118ad
  xe-pw-169692v2: 169692v2

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-169692v2/index.html

[-- Attachment #2: Type: text/html, Size: 1475 bytes --]

Re: [PATCH v2 01/11] drm/xe/xe_ras: Add support to retrieve info queue data for CRI

[Michal Wajdeczko]

On 8/25/2026 7:59 PM, Badal Nilawar wrote:
> Add support to retrieve info queue data. While constructing CPER
> record info queue data will be retrieved when has_info_queue=1 is
> set in get_counter response.
> 
> Signed-off-by: Badal Nilawar <badal.nilawar@intel.com>
> Assisted-by: Copilot:claude-sonnet-4.6
> ---
> v2: Drop unused flags (Mallesh)
> ---
>  drivers/gpu/drm/xe/xe_ras.c                   |  34 ++++++
>  drivers/gpu/drm/xe/xe_ras_types.h             | 108 ++++++++++++++++++
>  drivers/gpu/drm/xe/xe_sysctrl_mailbox_types.h |   2 +
>  3 files changed, 144 insertions(+)
> 
> diff --git a/drivers/gpu/drm/xe/xe_ras.c b/drivers/gpu/drm/xe/xe_ras.c
> index d25d25f77531..683087235482 100644
> --- a/drivers/gpu/drm/xe/xe_ras.c
> +++ b/drivers/gpu/drm/xe/xe_ras.c
> @@ -661,6 +661,40 @@ int xe_ras_clear_counter(struct xe_device *xe, u8 severity, u8 component)
>  	return 0;
>  }
>  
> +static int get_info_queue_data(struct xe_device *xe,
> +			       const struct xe_ras_get_info_queue_data_request *req,
> +			       struct xe_ras_get_info_queue_data_response *out)
> +{
> +	struct xe_ras_get_info_queue_data_response response = {0};
> +	struct xe_sysctrl_mailbox_command command = {0};
> +	size_t rlen;
> +	int ret;
> +
> +	xe_sysctrl_create_command(&command, XE_SYSCTRL_GROUP_GFSP,
> +				  XE_SYSCTRL_CMD_GET_INFO_QUEUE_DATA,
> +				  (void *)req, sizeof(*req), &response, sizeof(response));
> +
> +	ret = xe_sysctrl_send_command(&xe->sc, &command, &rlen);
> +	if (ret) {
> +		xe_err(xe, "sysctrl: failed to get info queue data %d\n", ret);
> +		return ret;
> +	}
> +
> +	if (rlen != sizeof(response)) {
> +		xe_err(xe, "sysctrl: unexpected get info queue data response length %zu (expected %zu)\n",
> +		       rlen, sizeof(response));
> +		return -EIO;
> +	}
> +
> +	xe_dbg(xe, "[RAS]: info queue data: status=%u chunk_size=%u flags=0x%x\n",
> +	       response.operation_status,
> +	       response.queue_response.queue_header.chunk_size,
> +	       response.queue_response.queue_header.flags);
> +
> +	*out = response;
> +	return 0;
> +}
> +
>  static ssize_t gpu_health_show(struct device *dev, struct device_attribute *attr, char *buf)
>  {
>  	struct xe_ras_get_health_response response = {0};
> diff --git a/drivers/gpu/drm/xe/xe_ras_types.h b/drivers/gpu/drm/xe/xe_ras_types.h
> index 99b2466e2062..d87db9f5174a 100644
> --- a/drivers/gpu/drm/xe/xe_ras_types.h
> +++ b/drivers/gpu/drm/xe/xe_ras_types.h
> @@ -16,6 +16,10 @@
>  #define XE_RAS_MEMORY_DB_ECC			BIT(1)
>  #define XE_RAS_MEMORY_POISON			BIT(2)
>  #define XE_RAS_MEMORY_DATA_PARITY		BIT(5)
> +#define XE_RAS_INFO_QUEUE_MAX_CHUNK_SIZE	200
> +#define XE_RAS_INFO_QUEUE_MAX_TOTAL_SIZE	5120
> +#define XE_RAS_INFO_QUEUE_FLAG_AVAILABLE	0x01
> +#define XE_RAS_INFO_QUEUE_FLAG_MORE_DATA	0x02
>  
>  /**
>   * enum xe_ras_recovery_action - RAS recovery actions
> @@ -95,6 +99,109 @@ struct xe_ras_threshold_crossed {
>  	struct xe_ras_error_class counters[XE_RAS_NUM_COUNTERS];
>  } __packed;
>  
> +/**
> + * struct xe_ras_info_queue_header - Metadata for large info queue data transfers
> + *
> + * Provides chunk metadata for commands that support extended info queue
> + * functionality. Used when the total data exceeds a single mailbox response.
> + */
> +struct xe_ras_info_queue_header {
> +	/** @total_size: Total size of the complete info queue data in bytes */
> +	u32 total_size;
> +	/** @chunk_offset: Offset of this chunk within the total data in bytes */
> +	u32 chunk_offset;
> +	/** @chunk_size: Size of the data in this chunk in bytes */
> +	u32 chunk_size;
> +	/** @sequence_number: Sequence number for this chunk, starts at 0 */
> +	u32 sequence_number;
> +	/** @flags: Info queue control flags (RAS_INFO_QUEUE_FLAG_*) */
> +	u32 flags:8;
> +	/** @compression_type: Compression algorithm used; 0 = none */
> +	u32 compression_type:4;
> +	/** @num_headers: Number of detailed counter headers at start of queue_data */
> +	u32 num_headers:5;
> +	/** @reserved: Reserved for future use */
> +	u32 reserved:15;
> +	/** @checksum: CRC32 checksum of this chunk data */
> +	u32 checksum;
> +} __packed;

all those __packed structs look like part of the firmware ABI
shouldn't we keep them in a separate file in abi/ folder
> +
> +/**
> + * struct xe_ras_info_queue_request - Request for a specific chunk of info queue data
> + *
> + * Allows the driver to request continuation of large info queue transfers
> + * by specifying an offset and size within the full data set.
> + */
> +struct xe_ras_info_queue_request {
> +	/** @requested_offset: Byte offset of the requested data chunk */
> +	u32 requested_offset;
> +	/** @requested_size: Maximum size of the requested chunk in bytes */
> +	u32 requested_size;
> +	/** @session_id: Session ID to correlate multi-chunk transfers */
> +	struct xe_ras_error_class session_id;
> +	/** @reserved: Reserved for future use */
> +	u32 reserved;
> +} __packed;
> +
> +/**
> + * struct xe_ras_info_queue_response - Generic response for commands with info queues
> + *
> + * Standard response format for any command that returns an info queue
> + * payload. May be embedded in a command-specific response structure.
> + */
> +struct xe_ras_info_queue_response {
> +	/** @queue_header: Info queue metadata for this chunk */
> +	struct xe_ras_info_queue_header queue_header;
> +	/** @queue_data: Info queue data for this chunk */
> +	u8 queue_data[XE_RAS_INFO_QUEUE_MAX_CHUNK_SIZE];
> +} __packed;
> +
> +/**
> + * struct xe_ras_info_queue_dynamic_counter_hdr - Aggregate counter header entry
> + *
> + * When a session requests aggregate counter data, one header per matching
> + * dynamic counter class is prepended to the queue data. The @counter field
> + * indicates how many subsequent error log entries belong to this class.
> + */
> +struct xe_ras_info_queue_dynamic_counter_hdr {
> +	/** @error_class: Error class associated with this counter group */
> +	struct xe_ras_error_class error_class;
> +	/** @counter: Number of error log entries that follow for this class */
> +	u32 counter;
> +} __packed;
> +
> +/**
> + * struct xe_ras_error_log - Single error log entry following dynamic counter headers
> + */
> +struct xe_ras_error_log {
> +	/** @timestamp: Timestamp when the error was recorded */
> +	u64 timestamp;
> +	/** @error_details: Error-specific details */
> +	u32 error_details[16];
> +} __packed;
> +
> +/**
> + * struct xe_ras_get_info_queue_data_request - Request for RAS_CMD_GET_INFO_QUEUE_DATA
> + */
> +struct xe_ras_get_info_queue_data_request {
> +	/** @queue_request: Info queue request parameters */
> +	struct xe_ras_info_queue_request queue_request;
> +	/** @source_command: Original command that generated the info queue */
> +	u32 source_command;
> +	/** @source_context: Context from original command, if applicable */
> +	struct xe_ras_error_class source_context;
> +} __packed;
> +
> +/**
> + * struct xe_ras_get_info_queue_data_response - Response for RAS_CMD_GET_INFO_QUEUE_DATA
> + */
> +struct xe_ras_get_info_queue_data_response {
> +	/** @operation_status: Status of the retrieval operation */
> +	u32 operation_status;
> +	/** @queue_response: Info queue data chunk */
> +	struct xe_ras_info_queue_response queue_response;
> +} __packed;
> +
>  /**
>   * struct xe_ras_get_counter_request - Request structure for get counter
>   */
> @@ -286,4 +393,5 @@ struct xe_ras_set_health_response {
>  	/** @reserved1: Reserved for future use */
>  	u32 reserved1[2];
>  } __packed;
> +
>  #endif
> diff --git a/drivers/gpu/drm/xe/xe_sysctrl_mailbox_types.h b/drivers/gpu/drm/xe/xe_sysctrl_mailbox_types.h
> index d0341538ad05..17f53cb78dc4 100644
> --- a/drivers/gpu/drm/xe/xe_sysctrl_mailbox_types.h
> +++ b/drivers/gpu/drm/xe/xe_sysctrl_mailbox_types.h
> @@ -28,6 +28,7 @@ enum xe_sysctrl_group {
>   * @XE_SYSCTRL_CMD_GET_PENDING_EVENT: Retrieve pending event
>   * @XE_SYSCTRL_CMD_GET_HEALTH: Retrieve gpu health
>   * @XE_SYSCTRL_CMD_SET_HEALTH: Set gpu health
> + * @XE_SYSCTRL_CMD_GET_INFO_QUEUE_DATA: Retrieve a chunk of info queue data
>   */
>  enum xe_sysctrl_gfsp_cmd {
>  	XE_SYSCTRL_CMD_GET_SOC_ERROR		= 0x01,
> @@ -36,6 +37,7 @@ enum xe_sysctrl_gfsp_cmd {
>  	XE_SYSCTRL_CMD_GET_PENDING_EVENT	= 0x07,
>  	XE_SYSCTRL_CMD_GET_HEALTH		= 0x0B,
>  	XE_SYSCTRL_CMD_SET_HEALTH		= 0x0C,
> +	XE_SYSCTRL_CMD_GET_INFO_QUEUE_DATA	= 0x0D,
>  };
>  
>  /**

✗ Xe.CI.FULL: failure for Add CPER logging support for CRI (rev2)

[Patchwork]

[-- Attachment #1: Type: text/plain, Size: 37995 bytes --]

== Series Details ==

Series: Add CPER logging support for CRI (rev2)
URL   : https://patchwork.freedesktop.org/series/169692/
State : failure

== Summary ==

CI Bug Log - changes from xe-5642-15e2ba2fb6d25c03d89519aec46f8d5be3e118ad_FULL -> xe-pw-169692v2_FULL
====================================================

Summary
-------

  **FAILURE**

  Serious unknown changes coming with xe-pw-169692v2_FULL absolutely need to be
  verified manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in xe-pw-169692v2_FULL, please notify your bug team (I915-ci-infra@lists.freedesktop.org) to allow them
  to document this new failure mode, which will reduce false positives in CI.

  

Participating hosts (2 -> 2)
------------------------------

  No changes in participating hosts

Possible new issues
-------------------

  Here are the unknown changes that may have been introduced in xe-pw-169692v2_FULL:

### IGT changes ###

#### Possible regressions ####

  * igt@xe_exec_reset@gt-stress-reset-bo-invalidation:
    - shard-bmg:          [PASS][1] -> [DMESG-WARN][2]
   [1]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5642-15e2ba2fb6d25c03d89519aec46f8d5be3e118ad/shard-bmg-2/igt@xe_exec_reset@gt-stress-reset-bo-invalidation.html
   [2]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-169692v2/shard-bmg-7/igt@xe_exec_reset@gt-stress-reset-bo-invalidation.html

  
New tests
---------

  New tests have been introduced between xe-5642-15e2ba2fb6d25c03d89519aec46f8d5be3e118ad_FULL and xe-pw-169692v2_FULL:

### New IGT tests (3) ###

  * igt@kms_frontbuffer_tracking@fbcdrrs-tiling-4:
    - Statuses : 2 skip(s)
    - Exec time: [0.01, 0.02] s

  * igt@kms_frontbuffer_tracking@fbcdrrs-tiling-linear:
    - Statuses : 1 skip(s)
    - Exec time: [0.01] s

  * igt@kms_frontbuffer_tracking@fbcdrrs-tiling-y:
    - Statuses : 1 skip(s)
    - Exec time: [0.02] s

  

Known issues
------------

  Here are the changes found in xe-pw-169692v2_FULL that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@core_hotunplug@hotunbind-rebind-with-load:
    - shard-bmg:          [PASS][3] -> [ABORT][4] ([Intel XE#8007]) +1 other test abort
   [3]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5642-15e2ba2fb6d25c03d89519aec46f8d5be3e118ad/shard-bmg-2/igt@core_hotunplug@hotunbind-rebind-with-load.html
   [4]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-169692v2/shard-bmg-10/igt@core_hotunplug@hotunbind-rebind-with-load.html

  * igt@kms_addfb_basic@addfb25-y-tiled-small-legacy:
    - shard-bmg:          NOTRUN -> [SKIP][5] ([Intel XE#2233])
   [5]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-169692v2/shard-bmg-10/igt@kms_addfb_basic@addfb25-y-tiled-small-legacy.html

  * igt@kms_big_fb@linear-32bpp-rotate-270:
    - shard-bmg:          NOTRUN -> [SKIP][6] ([Intel XE#2327])
   [6]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-169692v2/shard-bmg-1/igt@kms_big_fb@linear-32bpp-rotate-270.html

  * igt@kms_big_fb@y-tiled-max-hw-stride-32bpp-rotate-180-async-flip:
    - shard-bmg:          NOTRUN -> [SKIP][7] ([Intel XE#1124]) +4 other tests skip
   [7]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-169692v2/shard-bmg-3/igt@kms_big_fb@y-tiled-max-hw-stride-32bpp-rotate-180-async-flip.html

  * igt@kms_big_fb@yf-tiled-addfb-size-overflow:
    - shard-bmg:          NOTRUN -> [SKIP][8] ([Intel XE#610] / [Intel XE#7387])
   [8]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-169692v2/shard-bmg-3/igt@kms_big_fb@yf-tiled-addfb-size-overflow.html

  * igt@kms_bw@linear-tiling-2-displays-target-1920x1080p:
    - shard-bmg:          NOTRUN -> [SKIP][9] ([Intel XE#367]) +1 other test skip
   [9]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-169692v2/shard-bmg-6/igt@kms_bw@linear-tiling-2-displays-target-1920x1080p.html

  * igt@kms_ccs@bad-pixel-format-4-tiled-mtl-rc-ccs-cc:
    - shard-bmg:          NOTRUN -> [SKIP][10] ([Intel XE#2887]) +9 other tests skip
   [10]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-169692v2/shard-bmg-2/igt@kms_ccs@bad-pixel-format-4-tiled-mtl-rc-ccs-cc.html

  * igt@kms_ccs@crc-primary-suspend-4-tiled-lnl-ccs@pipe-a-dp-2:
    - shard-bmg:          NOTRUN -> [SKIP][11] ([Intel XE#2652]) +8 other tests skip
   [11]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-169692v2/shard-bmg-9/igt@kms_ccs@crc-primary-suspend-4-tiled-lnl-ccs@pipe-a-dp-2.html

  * igt@kms_cdclk@plane-scaling:
    - shard-bmg:          NOTRUN -> [SKIP][12] ([Intel XE#2724] / [Intel XE#7449])
   [12]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-169692v2/shard-bmg-5/igt@kms_cdclk@plane-scaling.html

  * igt@kms_chamelium_color@ctm-red-to-blue:
    - shard-bmg:          NOTRUN -> [SKIP][13] ([Intel XE#2325] / [Intel XE#7358]) +1 other test skip
   [13]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-169692v2/shard-bmg-8/igt@kms_chamelium_color@ctm-red-to-blue.html

  * igt@kms_chamelium_hpd@dp-hpd-after-suspend:
    - shard-bmg:          NOTRUN -> [SKIP][14] ([Intel XE#2252]) +3 other tests skip
   [14]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-169692v2/shard-bmg-1/igt@kms_chamelium_hpd@dp-hpd-after-suspend.html

  * igt@kms_content_protection@dp-mst-lic-type-0-hdcp14:
    - shard-bmg:          NOTRUN -> [SKIP][15] ([Intel XE#6974])
   [15]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-169692v2/shard-bmg-1/igt@kms_content_protection@dp-mst-lic-type-0-hdcp14.html

  * igt@kms_content_protection@lic-type-0@pipe-a-dp-2:
    - shard-bmg:          NOTRUN -> [FAIL][16] ([Intel XE#1178] / [Intel XE#3304] / [Intel XE#7374]) +1 other test fail
   [16]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-169692v2/shard-bmg-4/igt@kms_content_protection@lic-type-0@pipe-a-dp-2.html

  * igt@kms_cursor_crc@cursor-random-512x170:
    - shard-bmg:          NOTRUN -> [SKIP][17] ([Intel XE#2321] / [Intel XE#7355]) +1 other test skip
   [17]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-169692v2/shard-bmg-5/igt@kms_cursor_crc@cursor-random-512x170.html

  * igt@kms_cursor_crc@cursor-sliding-64x21:
    - shard-bmg:          NOTRUN -> [SKIP][18] ([Intel XE#2320]) +4 other tests skip
   [18]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-169692v2/shard-bmg-3/igt@kms_cursor_crc@cursor-sliding-64x21.html

  * igt@kms_dsc@dsc-with-bpc:
    - shard-bmg:          NOTRUN -> [SKIP][19] ([Intel XE#8265])
   [19]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-169692v2/shard-bmg-9/igt@kms_dsc@dsc-with-bpc.html

  * igt@kms_fbcon_fbt@fbc:
    - shard-bmg:          NOTRUN -> [SKIP][20] ([Intel XE#4156] / [Intel XE#7425])
   [20]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-169692v2/shard-bmg-5/igt@kms_fbcon_fbt@fbc.html

  * igt@kms_flip@flip-vs-absolute-wf_vblank-interruptible@b-edp1:
    - shard-lnl:          [PASS][21] -> [FAIL][22] ([Intel XE#3098]) +1 other test fail
   [21]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5642-15e2ba2fb6d25c03d89519aec46f8d5be3e118ad/shard-lnl-4/igt@kms_flip@flip-vs-absolute-wf_vblank-interruptible@b-edp1.html
   [22]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-169692v2/shard-lnl-1/igt@kms_flip@flip-vs-absolute-wf_vblank-interruptible@b-edp1.html

  * igt@kms_flip@flip-vs-expired-vblank@b-edp1:
    - shard-lnl:          [PASS][23] -> [FAIL][24] ([Intel XE#301]) +1 other test fail
   [23]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5642-15e2ba2fb6d25c03d89519aec46f8d5be3e118ad/shard-lnl-6/igt@kms_flip@flip-vs-expired-vblank@b-edp1.html
   [24]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-169692v2/shard-lnl-6/igt@kms_flip@flip-vs-expired-vblank@b-edp1.html

  * igt@kms_flip_scaled_crc@flip-64bpp-4tile-to-32bpp-4tiledg2rcccs-upscaling:
    - shard-bmg:          NOTRUN -> [SKIP][25] ([Intel XE#7178] / [Intel XE#7349]) +1 other test skip
   [25]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-169692v2/shard-bmg-3/igt@kms_flip_scaled_crc@flip-64bpp-4tile-to-32bpp-4tiledg2rcccs-upscaling.html

  * igt@kms_frontbuffer_tracking@drrs-2p-pri-indfb-multidraw:
    - shard-bmg:          NOTRUN -> [SKIP][26] ([Intel XE#2311]) +32 other tests skip
   [26]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-169692v2/shard-bmg-7/igt@kms_frontbuffer_tracking@drrs-2p-pri-indfb-multidraw.html

  * igt@kms_frontbuffer_tracking@fbc-1p-primscrn-indfb-pgflip-blt:
    - shard-bmg:          NOTRUN -> [SKIP][27] ([Intel XE#4141]) +12 other tests skip
   [27]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-169692v2/shard-bmg-7/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-indfb-pgflip-blt.html

  * igt@kms_frontbuffer_tracking@fbcpsr-abgr161616f-draw-blt:
    - shard-bmg:          NOTRUN -> [SKIP][28] ([Intel XE#7061] / [Intel XE#7356]) +1 other test skip
   [28]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-169692v2/shard-bmg-7/igt@kms_frontbuffer_tracking@fbcpsr-abgr161616f-draw-blt.html

  * igt@kms_frontbuffer_tracking@fbcpsrhdr-1p-primscrn-cur-indfb-move:
    - shard-bmg:          NOTRUN -> [SKIP][29] ([Intel XE#2313]) +36 other tests skip
   [29]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-169692v2/shard-bmg-10/igt@kms_frontbuffer_tracking@fbcpsrhdr-1p-primscrn-cur-indfb-move.html

  * igt@kms_frontbuffer_tracking@psrhdr-argb161616f-draw-render:
    - shard-bmg:          NOTRUN -> [SKIP][30] ([Intel XE#7061]) +2 other tests skip
   [30]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-169692v2/shard-bmg-10/igt@kms_frontbuffer_tracking@psrhdr-argb161616f-draw-render.html

  * igt@kms_joiner@basic-big-joiner:
    - shard-bmg:          NOTRUN -> [SKIP][31] ([Intel XE#6901])
   [31]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-169692v2/shard-bmg-5/igt@kms_joiner@basic-big-joiner.html

  * igt@kms_joiner@basic-ultra-joiner:
    - shard-bmg:          NOTRUN -> [SKIP][32] ([Intel XE#6911] / [Intel XE#7378])
   [32]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-169692v2/shard-bmg-3/igt@kms_joiner@basic-ultra-joiner.html

  * igt@kms_pipe_stress@stress-xrgb8888-yftiled:
    - shard-bmg:          NOTRUN -> [SKIP][33] ([Intel XE#6912] / [Intel XE#7375])
   [33]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-169692v2/shard-bmg-1/igt@kms_pipe_stress@stress-xrgb8888-yftiled.html

  * igt@kms_plane@pixel-format-4-tiled-modifier@pipe-a-plane-5:
    - shard-bmg:          NOTRUN -> [SKIP][34] ([Intel XE#8303]) +1 other test skip
   [34]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-169692v2/shard-bmg-3/igt@kms_plane@pixel-format-4-tiled-modifier@pipe-a-plane-5.html

  * igt@kms_plane@pixel-format-y-tiled-modifier:
    - shard-bmg:          NOTRUN -> [SKIP][35] ([Intel XE#7283]) +2 other tests skip
   [35]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-169692v2/shard-bmg-7/igt@kms_plane@pixel-format-y-tiled-modifier.html

  * igt@kms_plane_lowres@tiling-yf:
    - shard-bmg:          NOTRUN -> [SKIP][36] ([Intel XE#2393])
   [36]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-169692v2/shard-bmg-2/igt@kms_plane_lowres@tiling-yf.html

  * igt@kms_plane_multiple@tiling-y:
    - shard-bmg:          NOTRUN -> [SKIP][37] ([Intel XE#5020] / [Intel XE#7348])
   [37]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-169692v2/shard-bmg-2/igt@kms_plane_multiple@tiling-y.html

  * igt@kms_plane_scaling@planes-upscale-factor-0-25-downscale-factor-0-75:
    - shard-bmg:          NOTRUN -> [SKIP][38] ([Intel XE#2763] / [Intel XE#6886]) +4 other tests skip
   [38]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-169692v2/shard-bmg-1/igt@kms_plane_scaling@planes-upscale-factor-0-25-downscale-factor-0-75.html

  * igt@kms_pm_backlight@fade-with-dpms:
    - shard-bmg:          NOTRUN -> [SKIP][39] ([Intel XE#7376] / [Intel XE#7760] / [Intel XE#870])
   [39]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-169692v2/shard-bmg-5/igt@kms_pm_backlight@fade-with-dpms.html

  * igt@kms_pm_dc@dc3co-after-dc6@psr2-yuv420:
    - shard-bmg:          NOTRUN -> [SKIP][40] ([Intel XE#8396]) +3 other tests skip
   [40]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-169692v2/shard-bmg-3/igt@kms_pm_dc@dc3co-after-dc6@psr2-yuv420.html

  * igt@kms_pm_dc@dc3co-vpb-framegap:
    - shard-bmg:          NOTRUN -> [SKIP][41] ([Intel XE#8395] / [Intel XE#8396]) +3 other tests skip
   [41]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-169692v2/shard-bmg-2/igt@kms_pm_dc@dc3co-vpb-framegap.html

  * igt@kms_pm_dc@dc5-dpms:
    - shard-lnl:          [PASS][42] -> [FAIL][43] ([Intel XE#8399])
   [42]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5642-15e2ba2fb6d25c03d89519aec46f8d5be3e118ad/shard-lnl-5/igt@kms_pm_dc@dc5-dpms.html
   [43]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-169692v2/shard-lnl-1/igt@kms_pm_dc@dc5-dpms.html

  * igt@kms_pm_dc@dc5-pageflip-negative:
    - shard-bmg:          NOTRUN -> [SKIP][44] ([Intel XE#6927])
   [44]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-169692v2/shard-bmg-5/igt@kms_pm_dc@dc5-pageflip-negative.html

  * igt@kms_pm_rpm@package-g7:
    - shard-bmg:          NOTRUN -> [SKIP][45] ([Intel XE#6814] / [Intel XE#7428])
   [45]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-169692v2/shard-bmg-3/igt@kms_pm_rpm@package-g7.html

  * igt@kms_psr2_sf@fbc-pr-cursor-plane-move-continuous-sf:
    - shard-bmg:          NOTRUN -> [SKIP][46] ([Intel XE#1489]) +6 other tests skip
   [46]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-169692v2/shard-bmg-1/igt@kms_psr2_sf@fbc-pr-cursor-plane-move-continuous-sf.html

  * igt@kms_psr@psr-sprite-plane-move:
    - shard-bmg:          NOTRUN -> [SKIP][47] ([Intel XE#2234] / [Intel XE#2850]) +5 other tests skip
   [47]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-169692v2/shard-bmg-7/igt@kms_psr@psr-sprite-plane-move.html

  * igt@kms_psr_stress_test@invalidate-primary-flip-overlay:
    - shard-bmg:          NOTRUN -> [SKIP][48] ([Intel XE#7795])
   [48]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-169692v2/shard-bmg-6/igt@kms_psr_stress_test@invalidate-primary-flip-overlay.html

  * igt@kms_sharpness_filter@filter-scaler-downscale:
    - shard-bmg:          NOTRUN -> [SKIP][49] ([Intel XE#6503]) +1 other test skip
   [49]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-169692v2/shard-bmg-2/igt@kms_sharpness_filter@filter-scaler-downscale.html

  * igt@kms_vrr@flip-suspend:
    - shard-bmg:          NOTRUN -> [SKIP][50] ([Intel XE#1499]) +1 other test skip
   [50]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-169692v2/shard-bmg-9/igt@kms_vrr@flip-suspend.html

  * igt@xe_exec_basic@multigpu-once-null-rebind:
    - shard-bmg:          NOTRUN -> [SKIP][51] ([Intel XE#2322] / [Intel XE#7372]) +4 other tests skip
   [51]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-169692v2/shard-bmg-5/igt@xe_exec_basic@multigpu-once-null-rebind.html

  * igt@xe_exec_fault_mode@twice-multi-queue:
    - shard-bmg:          NOTRUN -> [SKIP][52] ([Intel XE#8374]) +6 other tests skip
   [52]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-169692v2/shard-bmg-3/igt@xe_exec_fault_mode@twice-multi-queue.html

  * igt@xe_exec_multi_queue@few-execs-preempt-mode-fault-priority:
    - shard-bmg:          NOTRUN -> [SKIP][53] ([Intel XE#8364]) +12 other tests skip
   [53]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-169692v2/shard-bmg-9/igt@xe_exec_multi_queue@few-execs-preempt-mode-fault-priority.html

  * igt@xe_exec_reset@multi-queue-cat-error:
    - shard-bmg:          NOTRUN -> [SKIP][54] ([Intel XE#8369])
   [54]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-169692v2/shard-bmg-9/igt@xe_exec_reset@multi-queue-cat-error.html

  * igt@xe_exec_threads@threads-multi-queue-hang-fd-userptr-invalidate-race:
    - shard-bmg:          NOTRUN -> [SKIP][55] ([Intel XE#8378]) +3 other tests skip
   [55]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-169692v2/shard-bmg-4/igt@xe_exec_threads@threads-multi-queue-hang-fd-userptr-invalidate-race.html

  * igt@xe_live_ktest@xe_bo@xe_ccs_migrate_kunit:
    - shard-bmg:          NOTRUN -> [SKIP][56] ([Intel XE#2229])
   [56]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-169692v2/shard-bmg-5/igt@xe_live_ktest@xe_bo@xe_ccs_migrate_kunit.html

  * igt@xe_live_ktest@xe_eudebug:
    - shard-bmg:          NOTRUN -> [SKIP][57] ([Intel XE#2833])
   [57]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-169692v2/shard-bmg-10/igt@xe_live_ktest@xe_eudebug.html

  * igt@xe_multigpu_svm@mgpu-coherency-prefetch:
    - shard-bmg:          NOTRUN -> [SKIP][58] ([Intel XE#6964]) +1 other test skip
   [58]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-169692v2/shard-bmg-1/igt@xe_multigpu_svm@mgpu-coherency-prefetch.html

  * igt@xe_page_reclaim@binds-null-vma:
    - shard-bmg:          NOTRUN -> [SKIP][59] ([Intel XE#7793]) +2 other tests skip
   [59]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-169692v2/shard-bmg-10/igt@xe_page_reclaim@binds-null-vma.html

  * igt@xe_pat@pat-index-xelp:
    - shard-bmg:          NOTRUN -> [SKIP][60] ([Intel XE#2245] / [Intel XE#7590])
   [60]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-169692v2/shard-bmg-10/igt@xe_pat@pat-index-xelp.html

  * igt@xe_pat@xa-app-transient-media-off:
    - shard-bmg:          NOTRUN -> [SKIP][61] ([Intel XE#7590]) +1 other test skip
   [61]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-169692v2/shard-bmg-8/igt@xe_pat@xa-app-transient-media-off.html

  * igt@xe_peer2peer@read:
    - shard-bmg:          NOTRUN -> [SKIP][62] ([Intel XE#2427] / [Intel XE#6953] / [Intel XE#7326] / [Intel XE#7353])
   [62]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-169692v2/shard-bmg-2/igt@xe_peer2peer@read.html

  * igt@xe_pm@d3cold-mocs:
    - shard-bmg:          NOTRUN -> [SKIP][63] ([Intel XE#2284] / [Intel XE#7370]) +1 other test skip
   [63]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-169692v2/shard-bmg-9/igt@xe_pm@d3cold-mocs.html

  * igt@xe_pxp@pxp-stale-bo-exec-post-rpm:
    - shard-bmg:          NOTRUN -> [SKIP][64] ([Intel XE#4733] / [Intel XE#7417])
   [64]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-169692v2/shard-bmg-4/igt@xe_pxp@pxp-stale-bo-exec-post-rpm.html

  * igt@xe_query@multigpu-query-hwconfig:
    - shard-bmg:          NOTRUN -> [SKIP][65] ([Intel XE#944]) +1 other test skip
   [65]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-169692v2/shard-bmg-5/igt@xe_query@multigpu-query-hwconfig.html

  * igt@xe_sriov_auto_provisioning@selfconfig-reprovision-increase-numvfs@vf-random:
    - shard-bmg:          [PASS][66] -> [FAIL][67] ([Intel XE#7992]) +1 other test fail
   [66]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5642-15e2ba2fb6d25c03d89519aec46f8d5be3e118ad/shard-bmg-3/igt@xe_sriov_auto_provisioning@selfconfig-reprovision-increase-numvfs@vf-random.html
   [67]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-169692v2/shard-bmg-3/igt@xe_sriov_auto_provisioning@selfconfig-reprovision-increase-numvfs@vf-random.html

  
#### Possible fixes ####

  * igt@kms_ccs@crc-primary-suspend-4-tiled-bmg-ccs:
    - shard-bmg:          [INCOMPLETE][68] ([Intel XE#7084] / [Intel XE#8150]) -> [PASS][69] +1 other test pass
   [68]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5642-15e2ba2fb6d25c03d89519aec46f8d5be3e118ad/shard-bmg-9/igt@kms_ccs@crc-primary-suspend-4-tiled-bmg-ccs.html
   [69]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-169692v2/shard-bmg-8/igt@kms_ccs@crc-primary-suspend-4-tiled-bmg-ccs.html

  * igt@kms_cursor_legacy@flip-vs-cursor-legacy:
    - shard-bmg:          [FAIL][70] ([Intel XE#7571]) -> [PASS][71]
   [70]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5642-15e2ba2fb6d25c03d89519aec46f8d5be3e118ad/shard-bmg-5/igt@kms_cursor_legacy@flip-vs-cursor-legacy.html
   [71]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-169692v2/shard-bmg-2/igt@kms_cursor_legacy@flip-vs-cursor-legacy.html

  * igt@kms_flip@flip-vs-expired-vblank@a-edp1:
    - shard-lnl:          [FAIL][72] ([Intel XE#301]) -> [PASS][73]
   [72]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5642-15e2ba2fb6d25c03d89519aec46f8d5be3e118ad/shard-lnl-6/igt@kms_flip@flip-vs-expired-vblank@a-edp1.html
   [73]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-169692v2/shard-lnl-6/igt@kms_flip@flip-vs-expired-vblank@a-edp1.html

  * igt@kms_flip@flip-vs-expired-vblank@c-edp1:
    - shard-lnl:          [FAIL][74] ([Intel XE#301] / [Intel XE#3149]) -> [PASS][75] +1 other test pass
   [74]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5642-15e2ba2fb6d25c03d89519aec46f8d5be3e118ad/shard-lnl-6/igt@kms_flip@flip-vs-expired-vblank@c-edp1.html
   [75]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-169692v2/shard-lnl-6/igt@kms_flip@flip-vs-expired-vblank@c-edp1.html

  * igt@xe_fault_injection@probe-fail-guc-xe_guc_ct_send_recv:
    - shard-bmg:          [ABORT][76] ([Intel XE#8007]) -> [PASS][77]
   [76]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5642-15e2ba2fb6d25c03d89519aec46f8d5be3e118ad/shard-bmg-5/igt@xe_fault_injection@probe-fail-guc-xe_guc_ct_send_recv.html
   [77]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-169692v2/shard-bmg-7/igt@xe_fault_injection@probe-fail-guc-xe_guc_ct_send_recv.html

  * igt@xe_module_load@load:
    - shard-bmg:          ([PASS][78], [PASS][79], [PASS][80], [PASS][81], [PASS][82], [PASS][83], [PASS][84], [PASS][85], [PASS][86], [PASS][87], [PASS][88], [PASS][89], [PASS][90], [PASS][91], [PASS][92], [PASS][93], [SKIP][94], [PASS][95], [PASS][96], [PASS][97], [PASS][98], [PASS][99], [PASS][100], [PASS][101], [PASS][102], [PASS][103]) ([Intel XE#2457] / [Intel XE#7405]) -> ([PASS][104], [PASS][105], [PASS][106], [PASS][107], [PASS][108], [PASS][109], [PASS][110], [PASS][111], [PASS][112], [PASS][113], [PASS][114], [PASS][115], [PASS][116], [PASS][117], [PASS][118], [PASS][119], [PASS][120], [PASS][121], [PASS][122], [PASS][123], [PASS][124], [PASS][125], [PASS][126], [PASS][127], [PASS][128])
   [78]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5642-15e2ba2fb6d25c03d89519aec46f8d5be3e118ad/shard-bmg-1/igt@xe_module_load@load.html
   [79]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5642-15e2ba2fb6d25c03d89519aec46f8d5be3e118ad/shard-bmg-2/igt@xe_module_load@load.html
   [80]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5642-15e2ba2fb6d25c03d89519aec46f8d5be3e118ad/shard-bmg-3/igt@xe_module_load@load.html
   [81]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5642-15e2ba2fb6d25c03d89519aec46f8d5be3e118ad/shard-bmg-10/igt@xe_module_load@load.html
   [82]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5642-15e2ba2fb6d25c03d89519aec46f8d5be3e118ad/shard-bmg-1/igt@xe_module_load@load.html
   [83]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5642-15e2ba2fb6d25c03d89519aec46f8d5be3e118ad/shard-bmg-2/igt@xe_module_load@load.html
   [84]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5642-15e2ba2fb6d25c03d89519aec46f8d5be3e118ad/shard-bmg-8/igt@xe_module_load@load.html
   [85]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5642-15e2ba2fb6d25c03d89519aec46f8d5be3e118ad/shard-bmg-6/igt@xe_module_load@load.html
   [86]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5642-15e2ba2fb6d25c03d89519aec46f8d5be3e118ad/shard-bmg-10/igt@xe_module_load@load.html
   [87]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5642-15e2ba2fb6d25c03d89519aec46f8d5be3e118ad/shard-bmg-9/igt@xe_module_load@load.html
   [88]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5642-15e2ba2fb6d25c03d89519aec46f8d5be3e118ad/shard-bmg-6/igt@xe_module_load@load.html
   [89]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5642-15e2ba2fb6d25c03d89519aec46f8d5be3e118ad/shard-bmg-9/igt@xe_module_load@load.html
   [90]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5642-15e2ba2fb6d25c03d89519aec46f8d5be3e118ad/shard-bmg-2/igt@xe_module_load@load.html
   [91]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5642-15e2ba2fb6d25c03d89519aec46f8d5be3e118ad/shard-bmg-2/igt@xe_module_load@load.html
   [92]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5642-15e2ba2fb6d25c03d89519aec46f8d5be3e118ad/shard-bmg-4/igt@xe_module_load@load.html
   [93]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5642-15e2ba2fb6d25c03d89519aec46f8d5be3e118ad/shard-bmg-4/igt@xe_module_load@load.html
   [94]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5642-15e2ba2fb6d25c03d89519aec46f8d5be3e118ad/shard-bmg-10/igt@xe_module_load@load.html
   [95]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5642-15e2ba2fb6d25c03d89519aec46f8d5be3e118ad/shard-bmg-9/igt@xe_module_load@load.html
   [96]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5642-15e2ba2fb6d25c03d89519aec46f8d5be3e118ad/shard-bmg-7/igt@xe_module_load@load.html
   [97]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5642-15e2ba2fb6d25c03d89519aec46f8d5be3e118ad/shard-bmg-5/igt@xe_module_load@load.html
   [98]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5642-15e2ba2fb6d25c03d89519aec46f8d5be3e118ad/shard-bmg-8/igt@xe_module_load@load.html
   [99]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5642-15e2ba2fb6d25c03d89519aec46f8d5be3e118ad/shard-bmg-5/igt@xe_module_load@load.html
   [100]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5642-15e2ba2fb6d25c03d89519aec46f8d5be3e118ad/shard-bmg-8/igt@xe_module_load@load.html
   [101]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5642-15e2ba2fb6d25c03d89519aec46f8d5be3e118ad/shard-bmg-3/igt@xe_module_load@load.html
   [102]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5642-15e2ba2fb6d25c03d89519aec46f8d5be3e118ad/shard-bmg-10/igt@xe_module_load@load.html
   [103]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5642-15e2ba2fb6d25c03d89519aec46f8d5be3e118ad/shard-bmg-7/igt@xe_module_load@load.html
   [104]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-169692v2/shard-bmg-10/igt@xe_module_load@load.html
   [105]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-169692v2/shard-bmg-6/igt@xe_module_load@load.html
   [106]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-169692v2/shard-bmg-5/igt@xe_module_load@load.html
   [107]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-169692v2/shard-bmg-8/igt@xe_module_load@load.html
   [108]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-169692v2/shard-bmg-10/igt@xe_module_load@load.html
   [109]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-169692v2/shard-bmg-1/igt@xe_module_load@load.html
   [110]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-169692v2/shard-bmg-1/igt@xe_module_load@load.html
   [111]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-169692v2/shard-bmg-7/igt@xe_module_load@load.html
   [112]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-169692v2/shard-bmg-7/igt@xe_module_load@load.html
   [113]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-169692v2/shard-bmg-7/igt@xe_module_load@load.html
   [114]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-169692v2/shard-bmg-2/igt@xe_module_load@load.html
   [115]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-169692v2/shard-bmg-2/igt@xe_module_load@load.html
   [116]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-169692v2/shard-bmg-9/igt@xe_module_load@load.html
   [117]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-169692v2/shard-bmg-9/igt@xe_module_load@load.html
   [118]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-169692v2/shard-bmg-9/igt@xe_module_load@load.html
   [119]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-169692v2/shard-bmg-4/igt@xe_module_load@load.html
   [120]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-169692v2/shard-bmg-6/igt@xe_module_load@load.html
   [121]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-169692v2/shard-bmg-4/igt@xe_module_load@load.html
   [122]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-169692v2/shard-bmg-3/igt@xe_module_load@load.html
   [123]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-169692v2/shard-bmg-3/igt@xe_module_load@load.html
   [124]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-169692v2/shard-bmg-3/igt@xe_module_load@load.html
   [125]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-169692v2/shard-bmg-1/igt@xe_module_load@load.html
   [126]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-169692v2/shard-bmg-5/igt@xe_module_load@load.html
   [127]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-169692v2/shard-bmg-5/igt@xe_module_load@load.html
   [128]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-169692v2/shard-bmg-2/igt@xe_module_load@load.html

  * igt@xe_sriov_flr@flr-vfs-parallel:
    - shard-bmg:          [FAIL][129] ([Intel XE#6569]) -> [PASS][130] +1 other test pass
   [129]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5642-15e2ba2fb6d25c03d89519aec46f8d5be3e118ad/shard-bmg-5/igt@xe_sriov_flr@flr-vfs-parallel.html
   [130]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-169692v2/shard-bmg-4/igt@xe_sriov_flr@flr-vfs-parallel.html

  
#### Warnings ####

  * igt@kms_flip@flip-vs-expired-vblank-interruptible:
    - shard-lnl:          [FAIL][131] ([Intel XE#301] / [Intel XE#3149]) -> [FAIL][132] ([Intel XE#301]) +1 other test fail
   [131]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5642-15e2ba2fb6d25c03d89519aec46f8d5be3e118ad/shard-lnl-3/igt@kms_flip@flip-vs-expired-vblank-interruptible.html
   [132]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-169692v2/shard-lnl-8/igt@kms_flip@flip-vs-expired-vblank-interruptible.html

  * igt@kms_tiled_display@basic-test-pattern:
    - shard-bmg:          [FAIL][133] ([Intel XE#1729] / [Intel XE#7424]) -> [SKIP][134] ([Intel XE#2426] / [Intel XE#5848])
   [133]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5642-15e2ba2fb6d25c03d89519aec46f8d5be3e118ad/shard-bmg-3/igt@kms_tiled_display@basic-test-pattern.html
   [134]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-169692v2/shard-bmg-9/igt@kms_tiled_display@basic-test-pattern.html

  * igt@kms_tiled_display@basic-test-pattern-with-chamelium:
    - shard-bmg:          [SKIP][135] ([Intel XE#2509] / [Intel XE#7437]) -> [SKIP][136] ([Intel XE#2426] / [Intel XE#5848])
   [135]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5642-15e2ba2fb6d25c03d89519aec46f8d5be3e118ad/shard-bmg-10/igt@kms_tiled_display@basic-test-pattern-with-chamelium.html
   [136]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-169692v2/shard-bmg-7/igt@kms_tiled_display@basic-test-pattern-with-chamelium.html

  * igt@sriov_basic@pf-unbind-with-vfs-enabled-numvfs-all:
    - shard-bmg:          [ABORT][137] ([Intel XE#8868]) -> [ABORT][138] ([Intel XE#8007] / [Intel XE#8868])
   [137]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5642-15e2ba2fb6d25c03d89519aec46f8d5be3e118ad/shard-bmg-2/igt@sriov_basic@pf-unbind-with-vfs-enabled-numvfs-all.html
   [138]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-169692v2/shard-bmg-4/igt@sriov_basic@pf-unbind-with-vfs-enabled-numvfs-all.html

  
  [Intel XE#1124]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1124
  [Intel XE#1178]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1178
  [Intel XE#1489]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1489
  [Intel XE#1499]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1499
  [Intel XE#1729]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1729
  [Intel XE#2229]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2229
  [Intel XE#2233]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2233
  [Intel XE#2234]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2234
  [Intel XE#2245]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2245
  [Intel XE#2252]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2252
  [Intel XE#2284]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2284
  [Intel XE#2311]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2311
  [Intel XE#2313]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2313
  [Intel XE#2320]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2320
  [Intel XE#2321]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2321
  [Intel XE#2322]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2322
  [Intel XE#2325]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2325
  [Intel XE#2327]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2327
  [Intel XE#2393]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2393
  [Intel XE#2426]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2426
  [Intel XE#2427]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2427
  [Intel XE#2457]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2457
  [Intel XE#2509]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2509
  [Intel XE#2652]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2652
  [Intel XE#2724]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2724
  [Intel XE#2763]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2763
  [Intel XE#2833]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2833
  [Intel XE#2850]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2850
  [Intel XE#2887]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2887
  [Intel XE#301]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/301
  [Intel XE#3098]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3098
  [Intel XE#3149]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3149
  [Intel XE#3304]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3304
  [Intel XE#367]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/367
  [Intel XE#4141]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4141
  [Intel XE#4156]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4156
  [Intel XE#4733]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4733
  [Intel XE#5020]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5020
  [Intel XE#5848]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5848
  [Intel XE#610]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/610
  [Intel XE#6503]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6503
  [Intel XE#6569]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6569
  [Intel XE#6814]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6814
  [Intel XE#6886]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6886
  [Intel XE#6901]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6901
  [Intel XE#6911]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6911
  [Intel XE#6912]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6912
  [Intel XE#6927]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6927
  [Intel XE#6953]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6953
  [Intel XE#6964]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6964
  [Intel XE#6974]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6974
  [Intel XE#7061]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7061
  [Intel XE#7084]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7084
  [Intel XE#7178]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7178
  [Intel XE#7283]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7283
  [Intel XE#7326]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7326
  [Intel XE#7348]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7348
  [Intel XE#7349]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7349
  [Intel XE#7353]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7353
  [Intel XE#7355]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7355
  [Intel XE#7356]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7356
  [Intel XE#7358]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7358
  [Intel XE#7370]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7370
  [Intel XE#7372]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7372
  [Intel XE#7374]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7374
  [Intel XE#7375]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7375
  [Intel XE#7376]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7376
  [Intel XE#7378]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7378
  [Intel XE#7387]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7387
  [Intel XE#7405]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7405
  [Intel XE#7417]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7417
  [Intel XE#7424]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7424
  [Intel XE#7425]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7425
  [Intel XE#7428]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7428
  [Intel XE#7437]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7437
  [Intel XE#7449]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7449
  [Intel XE#7571]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7571
  [Intel XE#7590]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7590
  [Intel XE#7760]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7760
  [Intel XE#7793]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7793
  [Intel XE#7795]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7795
  [Intel XE#7992]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7992
  [Intel XE#8007]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/8007
  [Intel XE#8150]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/8150
  [Intel XE#8265]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/8265
  [Intel XE#8303]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/8303
  [Intel XE#8364]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/8364
  [Intel XE#8369]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/8369
  [Intel XE#8374]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/8374
  [Intel XE#8378]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/8378
  [Intel XE#8395]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/8395
  [Intel XE#8396]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/8396
  [Intel XE#8399]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/8399
  [Intel XE#870]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/870
  [Intel XE#8868]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/8868
  [Intel XE#944]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/944


Build changes
-------------

  * IGT: IGT_9071 -> IGT_9074
  * Linux: xe-5642-15e2ba2fb6d25c03d89519aec46f8d5be3e118ad -> xe-pw-169692v2

  IGT_9071: 9071
  IGT_9074: 9074
  xe-5642-15e2ba2fb6d25c03d89519aec46f8d5be3e118ad: 15e2ba2fb6d25c03d89519aec46f8d5be3e118ad
  xe-pw-169692v2: 169692v2

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-169692v2/index.html

[-- Attachment #2: Type: text/html, Size: 41386 bytes --]

Re: [PATCH v2 01/11] drm/xe/xe_ras: Add support to retrieve info queue data for CRI

[Rodrigo Vivi]

On Tue, Aug 25, 2026 at 05:53:16PM +0000, sashiko-bot@kernel.org wrote:
> Thank you for your contribution! Sashiko AI review found 2 potential issue(s) to consider:
> - [Medium] Unportable use of C bitfields inside a packed structure for a firmware message interface.
> - [Low] The patch introduces a static function `get_info_queue_data` without any callers, causing a `-Wunused-function` compiler warning that breaks the build.
> --
> 
> commit 82a6804e91047f9e3f922cd878001d1bc3e9d8ed
> Author: Badal Nilawar <badal.nilawar@intel.com>
> 
> drm/xe/xe_ras: Add support to retrieve info queue data for CRI
> 
> This commit adds support to retrieve info queue data. It introduces
> various structures for the info queue data request and response, and adds
> a function to send the command to the system controller.
> 
> > diff --git a/drivers/gpu/drm/xe/xe_ras.c b/drivers/gpu/drm/xe/xe_ras.c
> > index d25d25f775310..6830872354825 100644
> > --- a/drivers/gpu/drm/xe/xe_ras.c
> > +++ b/drivers/gpu/drm/xe/xe_ras.c
> [ ... ]
> > @@ -661,6 +661,40 @@ int xe_ras_clear_counter(struct xe_device *xe, u8 severity, u8 component)
> >  	return 0;
> >  }
> >  
> > +static int get_info_queue_data(struct xe_device *xe,
> > +			       const struct xe_ras_get_info_queue_data_request *req,
> > +			       struct xe_ras_get_info_queue_data_response *out)
> 
> [Severity: Low]
> Does this function have any callers in this patch?
> 
> Adding a static function without using it in the same patch will cause a
> -Wunused-function compiler warning, which breaks the build when compiling
> with -Werror. To maintain git bisect functionality, every intermediate patch
> should compile independently.

Although sashiko tags this as low, this might break the bisect for most of
us because -werror...
So, please add the maybe unused mark or squash this with the user.

Sometimes separate small patches help reviews, sometimes it is the other way
around. A bigger but complete patch might be easier to review.

And then perhaps only the ABI itself in a separate patch and in a separate
directory like Michal pointed out.

> 
> Could get_info_queue_data() be introduced in the patch that first uses it,
> or temporarily marked with __maybe_unused?
> 
> > +{
> > +	struct xe_ras_get_info_queue_data_response response = {0};
> > +	struct xe_sysctrl_mailbox_command command = {0};
> > +	size_t rlen;
> > +	int ret;
> [ ... ]
> > diff --git a/drivers/gpu/drm/xe/xe_ras_types.h b/drivers/gpu/drm/xe/xe_ras_types.h
> > index 99b2466e2062c..d87db9f5174a2 100644
> > --- a/drivers/gpu/drm/xe/xe_ras_types.h
> > +++ b/drivers/gpu/drm/xe/xe_ras_types.h
> [ ... ]
> > @@ -95,6 +99,109 @@ struct xe_ras_threshold_crossed {
> >  	struct xe_ras_error_class counters[XE_RAS_NUM_COUNTERS];
> >  } __packed;
> >  
> > +/**
> > + * struct xe_ras_info_queue_header - Metadata for large info queue data transfers
> > + *
> > + * Provides chunk metadata for commands that support extended info queue
> > + * functionality. Used when the total data exceeds a single mailbox response.
> > + */
> > +struct xe_ras_info_queue_header {
> > +	/** @total_size: Total size of the complete info queue data in bytes */
> > +	u32 total_size;
> > +	/** @chunk_offset: Offset of this chunk within the total data in bytes */
> > +	u32 chunk_offset;
> > +	/** @chunk_size: Size of the data in this chunk in bytes */
> > +	u32 chunk_size;
> > +	/** @sequence_number: Sequence number for this chunk, starts at 0 */
> > +	u32 sequence_number;
> > +	/** @flags: Info queue control flags (RAS_INFO_QUEUE_FLAG_*) */
> > +	u32 flags:8;
> > +	/** @compression_type: Compression algorithm used; 0 = none */
> > +	u32 compression_type:4;
> > +	/** @num_headers: Number of detailed counter headers at start of queue_data */
> > +	u32 num_headers:5;
> > +	/** @reserved: Reserved for future use */
> > +	u32 reserved:15;
> 
> [Severity: Medium]
> Are these C bitfields safe to use for a firmware message interface?
> 
> When the driver communicates with the firmware on a big-endian architecture
> or using a compiler with different bitfield ordering rules, the bitfields
> in xe_ras_info_queue_header will map to the wrong bits in the underlying
> 32-bit word.
> 
> Using C bitfields inside a __packed struct for a hardware/firmware ABI is
> generally avoided because their memory layout is compiler-dependent and
> endian-dependent. Would it be safer to use fixed-width types like u32
> along with FIELD_GET() and FIELD_PREP() macros?
> 
> > +	/** @checksum: CRC32 checksum of this chunk data */
> > +	u32 checksum;
> > +} __packed;
> > +
> [ ... ]
> 
> -- 
> Sashiko AI review · https://sashiko.dev/#/patchset/20260825175916.1103841-13-badal.nilawar@intel.com?part=1

Re: [PATCH v2 04/11] drm/xe/cper: APIs to prepare and log CPER record

[Rodrigo Vivi]

On Tue, Aug 25, 2026 at 06:02:18PM +0000, sashiko-bot@kernel.org wrote:
> Thank you for your contribution! Sashiko AI review found 2 potential issue(s) to consider:
> - [High] Unconditional dereference of potentially NULL `THIS_MODULE->srcversion` causes kernel panic.
> - [Medium] Assigning `ktime_get_real_seconds()` to `rhdr->timestamp` violates the UEFI CPER standard, which requires a BCD timestamp.
> --
> 
> commit 1a8a9f568395a2ce2ede1bcececcf688f5a25b63
> Author: Badal Nilawar <badal.nilawar@intel.com>
> 
> drm/xe/cper: APIs to prepare and log CPER record
> 
> Add APIs to initialize Intel-specific CPER metadata, build a non-standard
> CPER record, and emit it via the xe_error_cper tracepoint.
> 
> > diff --git a/drivers/gpu/drm/xe/xe_cper.c b/drivers/gpu/drm/xe/xe_cper.c
> > new file mode 100644
> > index 0000000000000..371537052de35
> > --- /dev/null
> > +++ b/drivers/gpu/drm/xe/xe_cper.c
> [ ... ]
> > +void xe_cper_init_intel_err_hdr(struct xe_device *xe, const u8 location[12],
> > +				u64 first_timestamp, u32 sig_id,
> > +				u32 error_count, struct xe_cper_sec_intel_err_hdr *ihdr)
> > +{
> [ ... ]
> > +	strscpy(ihdr->pci_bdf, pci_name(to_pci_dev(xe->drm.dev)), sizeof(ihdr->pci_bdf));
> > +	ihdr->valid_bits.pci_bdf = 1;
> > +
> > +#ifdef MODULE
> > +	strscpy(ihdr->drv_version, THIS_MODULE->srcversion, sizeof(ihdr->drv_version));
> 
> [Severity: High]
> Can this cause a kernel panic if the module's source version is not populated?
> 
> When the kernel is compiled without CONFIG_MODULE_SRCVERSION_ALL and the
> module lacks an explicit MODULE_VERSION macro, the build system does not
> generate the srcversion modinfo attribute. In this case,
> THIS_MODULE->srcversion is left as NULL during module load.
> 
> Since strscpy() does not handle NULL source pointers gracefully, this
> unconditional dereference of THIS_MODULE->srcversion in
> xe_cper_init_intel_err_hdr() could lead to a kernel panic when hardware
> error reporting is triggered.
> 
> > +	ihdr->valid_bits.drv_version = 1;
> > +#else
> > +	ihdr->valid_bits.drv_version = 0;
> > +#endif
> > +
> > +	fill_fw_id(xe, ihdr);
> > +}
> [ ... ]
> > +void xe_cper_record_emit(struct xe_device *xe, u8 severity,
> > +			 guid_t *notification_type,
> > +			 struct xe_cper_sec_intel_err_hdr *ihdr,
> > +			 const void *einfo, u32 einfo_len)
> > +{
> [ ... ]
> > +	/* Assemble the CPER record header (UEFI Appendix N.2.1) */
> > +	memcpy(rhdr->signature, CPER_SIG_RECORD, CPER_SIG_SIZE);
> > +	rhdr->revision          = CPER_RECORD_REV;
> > +	rhdr->signature_end     = CPER_SIG_END;
> > +	rhdr->section_count     = 1;
> > +	rhdr->error_severity    = severity;
> > +	rhdr->validation_bits   = CPER_VALID_TIMESTAMP;
> > +	rhdr->record_length     = total_len;
> > +	rhdr->timestamp         = ktime_get_real_seconds();
> 
> [Severity: Medium]
> Does this assign a raw binary Unix timestamp to a field that requires a BCD
> format?
> 
> ktime_get_real_seconds() returns a 64-bit binary integer representing
> seconds since the Unix epoch. However, the UEFI standard (UEFI 2.8+
> Appendix N.2.1) mandates that the timestamp field in a struct
> cper_record_header is a 64-bit BCD-encoded date and time value (Century,
> Year, Month, Day, Hours, Minutes, Seconds).
> 
> Assigning a raw binary Unix timestamp to rhdr->timestamp in
> xe_cper_record_emit() could cause standard CPER parsers to read invalid
> BCD characters or absurd dates.
> 
> > +	if (platform_id) {
> > +		rhdr->platform_id      = *platform_id;
> > +		rhdr->validation_bits |= CPER_VALID_PLATFORM_ID;
> > +	}
> [ ... ]
> 
> -- 
> Sashiko AI review · https://sashiko.dev/#/patchset/20260825175916.1103841-13-badal.nilawar@intel.com?part=4

please take a careful look to these... but overall this is in the right direction.

Re: [PATCH v2 06/11] drm/xe/cper: Log CPER records for aggregate counter retrival

[Rodrigo Vivi]

On Tue, Aug 25, 2026 at 11:29:23PM +0530, Badal Nilawar wrote:
> Log CPER records for aggregate counter retrieval from userspace.

please add a better commit message.

> 
> Signed-off-by: Badal Nilawar <badal.nilawar@intel.com>
> ---
>  drivers/gpu/drm/xe/xe_ras.c | 92 +++++++++++++++++++++++++++++++++++++
>  1 file changed, 92 insertions(+)
> 
> diff --git a/drivers/gpu/drm/xe/xe_ras.c b/drivers/gpu/drm/xe/xe_ras.c
> index 27c78800b5d2..ff9d917b8e29 100644
> --- a/drivers/gpu/drm/xe/xe_ras.c
> +++ b/drivers/gpu/drm/xe/xe_ras.c
> @@ -204,6 +204,34 @@ static inline const char *comp_to_str(u8 component)
>  	return xe_ras_components[component];
>  }
>  
> +static u32 ras_comp_to_hw_sigid(u8 component)
> +{
> +	switch (component) {
> +	case XE_RAS_COMP_DEVICE_MEMORY:
> +		return XE_SIGID_DEVICE_MEMORY;
> +	case XE_RAS_COMP_CORE_COMPUTE:
> +		return XE_SIGID_CORE_COMPUTE;
> +	case XE_RAS_COMP_PCIE:
> +		return XE_SIGID_PCIE;
> +	case XE_RAS_COMP_FABRIC:
> +		return XE_SIGID_FABRIC;
> +	case XE_RAS_COMP_SOC_INTERNAL:
> +		return XE_SIGID_SOC_INTERNAL;
> +	default:
> +		return U32_MAX;
> +	}
> +}
> +
> +static u8 ras_sev_to_cper_sev(u8 ras_sev)
> +{
> +	switch (ras_sev) {
> +	case XE_RAS_SEV_CORRECTABLE:   return CPER_SEV_CORRECTED;     /* 2 */
> +	case XE_RAS_SEV_UNCORRECTABLE: return CPER_SEV_RECOVERABLE;   /* 0 */
> +	case XE_RAS_SEV_INFORMATIONAL: return CPER_SEV_INFORMATIONAL; /* 3 */

if we have to write the numbers themselves we don't need enums and defines.
Please remove these comments....

> +	default:                       return CPER_SEV_RECOVERABLE;
> +	}
> +}
> +
>  static bool ras_counter_is_valid(struct xe_device *xe, struct xe_ras_error_class *counter)
>  {
>  	u8 severity = counter->common.severity;
> @@ -749,6 +777,66 @@ prepare_cper_error_info(struct xe_device *xe,
>  	return einfo_arr;
>  }
>  
> +static void emit_hw_error_cper(struct xe_device *xe,
> +			       struct xe_ras_error_class *error_class,
> +			       struct xe_ras_get_counter_response *resp,
> +			       u32 sig_id, u8 severity)
> +{
> +	struct xe_ras_get_counter_response local_resp = {};
> +	struct xe_ras_get_counter_response *counter_response = resp;
> +	struct xe_cper_sec_intel_err_hdr ihdr = {};
> +	struct xe_cper_einfo_entry *einfo_arr = NULL;
> +	u32 einfo_count = 0;
> +	u32 i;
> +
> +	if (!counter_response) {
> +		counter_response = &local_resp;
> +		if (get_counter(xe, error_class, counter_response)) {
> +			xe_err(xe, "[RAS]: CPER: failed to get counter, skipping record\n");
> +			return;
> +		}
> +	}
> +
> +	if (counter_response->has_info_queue) {
> +		einfo_arr = prepare_cper_error_info(xe, counter_response,
> +						    error_class, &einfo_count);
> +		if (!einfo_arr)
> +			xe_err(xe, "[RAS]: CPER: failed to build einfo from info queue\n");
> +	}
> +
> +	if (einfo_count > 0) {
> +		for (i = 0; i < einfo_count; i++) {
> +			struct xe_cper_sec_intel_err_hdr entry_ihdr = {};
> +
> +			xe_cper_init_intel_err_hdr(xe,
> +						   (const u8 *)&einfo_arr[i].hdr.error_class,
> +						   einfo_arr[i].timestamp,
> +						   sig_id,
> +						   einfo_arr[i].hdr.counter,
> +						   &entry_ihdr);
> +
> +			xe_cper_record_emit(xe, severity, &INTEL_CPER_NOTIFY_GPU_ERROR,
> +					    &entry_ihdr, einfo_arr[i].einfo,
> +					    einfo_arr[i].einfo_size);
> +		}
> +	} else {
> +		xe_cper_init_intel_err_hdr(xe,
> +					   (const u8 *)error_class,
> +					   counter_response->timestamp,
> +					   sig_id,
> +					   counter_response->value,
> +					   &ihdr);
> +		xe_cper_record_emit(xe, severity, &INTEL_CPER_NOTIFY_GPU_ERROR,
> +				    &ihdr, NULL, 0);
> +	}
> +
> +	if (einfo_arr) {
> +		for (i = 0; i < einfo_count; i++)
> +			kfree(einfo_arr[i].einfo);
> +		kfree(einfo_arr);
> +	}
> +}
> +
>  /**
>   * xe_ras_process_errors() - Process and contain hardware errors
>   * @xe: xe device instance
> @@ -886,6 +974,10 @@ int xe_ras_get_counter(struct xe_device *xe, u8 severity, u8 component, u32 *val
>  		return ret;
>  
>  	*value = response.value;
> +
> +	emit_hw_error_cper(xe, &counter, &response,
> +			   ras_comp_to_hw_sigid(counter.common.component),
> +			   ras_sev_to_cper_sev(counter.common.severity));
>  	return 0;
>  }
>  
> -- 
> 2.54.0
> 

Re: [PATCH v2 00/11] Add CPER logging support for CRI

[Matt Roper]

On Tue, Aug 25, 2026 at 11:29:17PM +0530, Badal Nilawar wrote:
> This patch series adds CPER (Common Platform Error Record) logging support
> for Correctable errors reported by Intel Xe GPUs. CPER logging is done
> through trace event.

Is the expectation that real-world applications are going to pick up
these logs via tracefs rather than some other kind of dedicated uapi?
That worries me a bit...

I think tracepoints have been a bit of a gray area in the past with some
people feeling that they're formal interfaces with all the ABI
requirements of traditional uapi, and other people feeling that they're
just debugging aids for driver developers that don't need to provide
stable ABI guarantees.  If we're saying this will be the official
interface that userspace software should use to obtain these CPER logs,
then it sounds like we're taking a firm stance that yes, these are now
formal uapi with hard ABI requirements.  In that case it means that this
work now needs to satisfy the DRM subsystem's ABI rules --- we need a
real-world opensource userspace consumer, acks from the userspace teams
on the interface, etc.  And we can never change/break the interface here
after it lands.

This may also have implications for other tracepoints, current or
future, so we should make sure we've thought through this carefully.
Please make sure you discuss this with the maintainers and ensure
they're aligned on the direction here.


Matt

> 
> v2:
>    - Extended CPER logging to Uncorrectable errors and xe_ras_get_counter
>      request
>    - Log CPER records via xe_log SIGID infra 
> 
> Badal Nilawar (11):
>   drm/xe/xe_ras: Add support to retrieve info queue data for CRI
>   drm/xe/xe_ras: Refactor get_counter() to return response structure
>   drm/xe/cper: Add CPER structures and trace event
>   drm/xe/cper: APIs to prepare and log CPER record
>   drm/xe/cper: Prepare Intel CPER error info from info queue
>   drm/xe/cper: Log CPER records for aggregate counter retrival
>   drm/xe/cper: Allow hardware error CPER reporting from xe_log
>   drm/xe/ras: Report device memory errors using SIGID
>   drm/xe/ras: Report core compute errors using SIGID
>   drm/xe/ras: Report soc internal errors using SIGID
>   drm/xe/ras: Report correctable errors using SIGID
> 
>  drivers/gpu/drm/xe/Makefile                   |   4 +
>  drivers/gpu/drm/xe/regs/xe_regs.h             |   2 +
>  drivers/gpu/drm/xe/xe_cper.c                  | 184 +++++++
>  drivers/gpu/drm/xe/xe_cper.h                  |  34 ++
>  drivers/gpu/drm/xe/xe_cper_types.h            | 186 +++++++
>  drivers/gpu/drm/xe/xe_log.c                   |  17 +-
>  drivers/gpu/drm/xe/xe_ras.c                   | 506 ++++++++++++++++--
>  drivers/gpu/drm/xe/xe_ras.h                   |   4 +
>  drivers/gpu/drm/xe/xe_ras_types.h             | 118 +++-
>  drivers/gpu/drm/xe/xe_sysctrl_mailbox_types.h |   2 +
>  drivers/gpu/drm/xe/xe_trace_cper.c            |   9 +
>  drivers/gpu/drm/xe/xe_trace_cper.h            |  66 +++
>  12 files changed, 1093 insertions(+), 39 deletions(-)
>  create mode 100644 drivers/gpu/drm/xe/xe_cper.c
>  create mode 100644 drivers/gpu/drm/xe/xe_cper.h
>  create mode 100644 drivers/gpu/drm/xe/xe_cper_types.h
>  create mode 100644 drivers/gpu/drm/xe/xe_trace_cper.c
>  create mode 100644 drivers/gpu/drm/xe/xe_trace_cper.h
> 
> -- 
> 2.54.0
> 

-- 
Matt Roper
Graphics Software Engineer
Linux GPU Platform Enablement
Intel Corporation

Re: [PATCH v2 00/11] Add CPER logging support for CRI

[Rodrigo Vivi]

On Wed, Aug 26, 2026 at 12:50:17PM -0700, Matt Roper wrote:
> On Tue, Aug 25, 2026 at 11:29:17PM +0530, Badal Nilawar wrote:
> > This patch series adds CPER (Common Platform Error Record) logging support
> > for Correctable errors reported by Intel Xe GPUs. CPER logging is done
> > through trace event.
> 
> Is the expectation that real-world applications are going to pick up
> these logs via tracefs rather than some other kind of dedicated uapi?
> That worries me a bit...
> 
> I think tracepoints have been a bit of a gray area in the past with some
> people feeling that they're formal interfaces with all the ABI
> requirements of traditional uapi, and other people feeling that they're
> just debugging aids for driver developers that don't need to provide
> stable ABI guarantees.  If we're saying this will be the official
> interface that userspace software should use to obtain these CPER logs,
> then it sounds like we're taking a firm stance that yes, these are now
> formal uapi with hard ABI requirements.  In that case it means that this
> work now needs to satisfy the DRM subsystem's ABI rules --- we need a
> real-world opensource userspace consumer, acks from the userspace teams
> on the interface, etc.  And we can never change/break the interface here
> after it lands.
> 
> This may also have implications for other tracepoints, current or
> future, so we should make sure we've thought through this carefully.
> Please make sure you discuss this with the maintainers and ensure
> they're aligned on the direction here.

Cc: Dave

relates to our old discussion on drm-ras vs tracefs for the cper logs:
https://lore.kernel.org/all/CAPM=9tybY_LECdMNH6iw5pzxtd2=Z+4vwLt-_kuMQFUaEXsdpw@mail.gmail.com/

The main motivation behind having the logs on tracefs is that debugfs is usually
not available in production and to avoid flooding the small kernel buf log.
Specially with some CPER format that is starting to be the convergence of log
format in the data center world. Mostly driven by OCP standards.

That said, I don't believe we need to draw a hard line and demand that the
tracefs become a hard ABI like our uAPIs. As you mentioned already that will
have consequences that are much higher than the logs use case.

Also, we are not proposing a dedicated userspace consumer for these traces,
nor do we expect applications to interact with them through a Xe-specific API.
Users already have standard mechanisms for collecting trace data, such as
trace-cmd, perf, KernelShark, and other tracing pipelines.

Similar to other trace events, those generic tracing tools can be used to
collect and process the records when desired. Because of that, I don't think
it is reasonable to require a new dedicated userspace project as a prerequisite
for exposing these events.

Thanks,
Rodrigo.

> 
> 
> Matt
> 
> > 
> > v2:
> >    - Extended CPER logging to Uncorrectable errors and xe_ras_get_counter
> >      request
> >    - Log CPER records via xe_log SIGID infra 
> > 
> > Badal Nilawar (11):
> >   drm/xe/xe_ras: Add support to retrieve info queue data for CRI
> >   drm/xe/xe_ras: Refactor get_counter() to return response structure
> >   drm/xe/cper: Add CPER structures and trace event
> >   drm/xe/cper: APIs to prepare and log CPER record
> >   drm/xe/cper: Prepare Intel CPER error info from info queue
> >   drm/xe/cper: Log CPER records for aggregate counter retrival
> >   drm/xe/cper: Allow hardware error CPER reporting from xe_log
> >   drm/xe/ras: Report device memory errors using SIGID
> >   drm/xe/ras: Report core compute errors using SIGID
> >   drm/xe/ras: Report soc internal errors using SIGID
> >   drm/xe/ras: Report correctable errors using SIGID
> > 
> >  drivers/gpu/drm/xe/Makefile                   |   4 +
> >  drivers/gpu/drm/xe/regs/xe_regs.h             |   2 +
> >  drivers/gpu/drm/xe/xe_cper.c                  | 184 +++++++
> >  drivers/gpu/drm/xe/xe_cper.h                  |  34 ++
> >  drivers/gpu/drm/xe/xe_cper_types.h            | 186 +++++++
> >  drivers/gpu/drm/xe/xe_log.c                   |  17 +-
> >  drivers/gpu/drm/xe/xe_ras.c                   | 506 ++++++++++++++++--
> >  drivers/gpu/drm/xe/xe_ras.h                   |   4 +
> >  drivers/gpu/drm/xe/xe_ras_types.h             | 118 +++-
> >  drivers/gpu/drm/xe/xe_sysctrl_mailbox_types.h |   2 +
> >  drivers/gpu/drm/xe/xe_trace_cper.c            |   9 +
> >  drivers/gpu/drm/xe/xe_trace_cper.h            |  66 +++
> >  12 files changed, 1093 insertions(+), 39 deletions(-)
> >  create mode 100644 drivers/gpu/drm/xe/xe_cper.c
> >  create mode 100644 drivers/gpu/drm/xe/xe_cper.h
> >  create mode 100644 drivers/gpu/drm/xe/xe_cper_types.h
> >  create mode 100644 drivers/gpu/drm/xe/xe_trace_cper.c
> >  create mode 100644 drivers/gpu/drm/xe/xe_trace_cper.h
> > 
> > -- 
> > 2.54.0
> > 
> 
> -- 
> Matt Roper
> Graphics Software Engineer
> Linux GPU Platform Enablement
> Intel Corporation

Re: [PATCH v2 08/11] drm/xe/ras: Report device memory errors using SIGID

[Michal Wajdeczko]

On 8/25/2026 7:59 PM, Badal Nilawar wrote:
> Use xe_log_comp_info helper to report device memory errors.
> 
> Signed-off-by: Badal Nilawar <badal.nilawar@intel.com>
> Cc: Riana Tauro <riana.tauro@intel.com>
> ---
>  drivers/gpu/drm/xe/xe_ras.c | 11 +++++++----
>  1 file changed, 7 insertions(+), 4 deletions(-)
> 
> diff --git a/drivers/gpu/drm/xe/xe_ras.c b/drivers/gpu/drm/xe/xe_ras.c
> index b4cdb5ec6491..172653be1b82 100644
> --- a/drivers/gpu/drm/xe/xe_ras.c
> +++ b/drivers/gpu/drm/xe/xe_ras.c
> @@ -409,14 +409,17 @@ static u8 handle_device_memory_errors(struct xe_device *xe, struct xe_ras_error_
>  	 */
>  	switch (info->category) {
>  	case XE_RAS_MEMORY_POISON:
> -		xe_info(xe, "[RAS]: Poison error detected\n");
> +		xe_log_comp_info(xe, DEVICE_MEMORY, &arr->counter, sizeof(arr->counter),
> +				 "Poison error detected\n");
>  		break;
>  	case XE_RAS_MEMORY_DATA_PARITY:
> -		xe_info(xe, "[RAS]: Data parity error detected\n");
> +		xe_log_comp_info(xe, DEVICE_MEMORY, &arr->counter, sizeof(arr->counter),
> +				 "Data parity error detected\n");
>  		break;
>  	case XE_RAS_MEMORY_DB_ECC:
> -		xe_info(xe, "[RAS]: Double-bit ECC error detected at sw address 0x%llx\n",
> -			info->sw_address);
> +		xe_log_comp_info(xe, DEVICE_MEMORY, &arr->counter, sizeof(arr->counter),
> +				 "Double-bit ECC error detected at sw address 0x%llx\n",
> +				 info->sw_address);

are we sure that all of above HW errors are INFORMATIONAL severity only?

>  		/* TODO: Add page offlining for Double-bit ECC error */
>  		fallthrough;
>  	default:

Re: [PATCH v2 07/11] drm/xe/cper: Allow hardware error CPER reporting from xe_log

[Michal Wajdeczko]

On 8/25/2026 7:59 PM, Badal Nilawar wrote:
> Add xe_emit_hardware_error_cper() as a public wrapper around the
> internal hardware CPER emission helper, enabling xe_log.c to emit
> hardware error CPER records.
> 
> Signed-off-by: Badal Nilawar <badal.nilawar@intel.com>
> ---
>  drivers/gpu/drm/xe/xe_log.c | 17 +++++++++++------
>  drivers/gpu/drm/xe/xe_ras.c | 23 +++++++++++++++++++++++
>  drivers/gpu/drm/xe/xe_ras.h |  4 ++++
>  3 files changed, 38 insertions(+), 6 deletions(-)
> 
> diff --git a/drivers/gpu/drm/xe/xe_log.c b/drivers/gpu/drm/xe/xe_log.c
> index 5549ef6966fd..c78fc195c55b 100644
> --- a/drivers/gpu/drm/xe/xe_log.c
> +++ b/drivers/gpu/drm/xe/xe_log.c
> @@ -10,15 +10,25 @@
>  
>  #include "xe_device.h"
>  #include "xe_log.h"
> +#include "xe_ras.h"
>  #include "xe_printk.h"
>  
> +static bool is_hw_sigid(enum xe_sigid sigid)
> +{
> +	return (int)sigid >= INTEL_SIGID_GPU_XE_HARDWARE_START;
> +}
> +
>  static void log_emit_cper(struct pci_dev *pdev, int cper_sev, enum xe_sigid sigid,
>  			  u32 component, u32 location, const void *data, size_t len,
>  			  struct va_format *vaf)
>  {
>  	KUNIT_STATIC_STUB_REDIRECT(log_emit_cper, pdev, cper_sev, sigid,
>  				   component, location, data, len, vaf);
> -	/* TODO */
> +	/* TODO software CPER */
> +
> +	if (is_hw_sigid(sigid))
> +		xe_emit_hardware_error_cper(pdev, cper_sev, sigid,
> +					    (struct xe_ras_error_class *)data);

make sure to check data len before doing a cast
also, maybe do all that in xe_emit_hardware_error_cper()
in case we would want to pass other blobs to xe_log

>  }
>  
>  static const char *log_unknown_component_prefix(u32 component)
> @@ -100,11 +110,6 @@ static const char *log_location_prefix(struct pci_dev *pdev, u32 location, char
>  	return buf;
>  }
>  
> -static bool is_hw_sigid(enum xe_sigid sigid)
> -{
> -	return (int)sigid >= INTEL_SIGID_GPU_XE_HARDWARE_START;
> -}
> -
>  static bool is_sev_error(int cper_sev)
>  {
>  	return cper_sev != CPER_SEV_INFORMATIONAL;
> diff --git a/drivers/gpu/drm/xe/xe_ras.c b/drivers/gpu/drm/xe/xe_ras.c
> index ff9d917b8e29..b4cdb5ec6491 100644
> --- a/drivers/gpu/drm/xe/xe_ras.c
> +++ b/drivers/gpu/drm/xe/xe_ras.c
> @@ -837,6 +837,29 @@ static void emit_hw_error_cper(struct xe_device *xe,
>  	}
>  }
>  
> +/**
> + * xe_emit_hardware_error_cper() - Emit a hardware error CPER record

shouldn't this be named as:

	xe_ras_emit_hardware_cper

as we should use xe_ras prefix for functions in this file
and error is redundant as we already have cper in the name
> + * @pdev: PCI device associated with the Xe device
> + * @cper_sev: CPER severity
> + * @sigid: Error signature identifier
> + * @error_class: Hardware error classification details
> + *
> + * Emit a CPER record for a hardware error
> + */
> +void xe_emit_hardware_error_cper(struct pci_dev *pdev, int cper_sev, enum xe_sigid sigid,
> +				 struct xe_ras_error_class *counter)
> +{
> +	struct xe_device *xe = pdev_to_xe_device(pdev);

I guess we can pass xe to xe_emit_hardware_error_cper()
pdev was only needed in xe_log to cover early probe errors

> +
> +	if (!xe)
> +		return;
> +
> +	if (counter && !ras_counter_is_valid(xe, counter))
> +		return;
> +
> +	emit_hw_error_cper(xe, counter, NULL, sigid, cper_sev);
> +}
> +
>  /**
>   * xe_ras_process_errors() - Process and contain hardware errors
>   * @xe: xe device instance
> diff --git a/drivers/gpu/drm/xe/xe_ras.h b/drivers/gpu/drm/xe/xe_ras.h
> index 618364734043..e5c4b2e2e1fd 100644
> --- a/drivers/gpu/drm/xe/xe_ras.h
> +++ b/drivers/gpu/drm/xe/xe_ras.h
> @@ -7,6 +7,8 @@
>  #define _XE_RAS_H_
>  
>  #include <linux/types.h>
> +#include "abi/xe_sigid_abi.h"
> +#include "xe_device.h"

do we need this?

>  #include "xe_ras_types.h"
>  
>  struct xe_device;
> @@ -18,5 +20,7 @@ int xe_ras_get_counter(struct xe_device *xe, u8 severity, u8 component, u32 *val
>  int xe_ras_clear_counter(struct xe_device *xe, u8 severity, u8 component);
>  void xe_ras_init(struct xe_device *xe);
>  enum xe_ras_recovery_action xe_ras_process_errors(struct xe_device *xe);
> +void xe_emit_hardware_error_cper(struct pci_dev *pdev, int cper_sev, enum xe_sigid sigid,
> +				 struct xe_ras_error_class *error_class);
>  
>  #endif

Re: [PATCH v2 10/11] drm/xe/ras: Report soc internal errors using SIGID

[Rodrigo Vivi]

On Tue, Aug 25, 2026 at 11:29:27PM +0530, Badal Nilawar wrote:
> Use xe_log_* helpers to report soc internal errors.
> 
> Signed-off-by: Badal Nilawar <badal.nilawar@intel.com>
> Cc: Riana Tauro <riana.tauro@intel.com>
> ---
>  drivers/gpu/drm/xe/xe_ras.c | 14 ++++++--------
>  1 file changed, 6 insertions(+), 8 deletions(-)
> 
> diff --git a/drivers/gpu/drm/xe/xe_ras.c b/drivers/gpu/drm/xe/xe_ras.c
> index 3b43d363d5de..4cd1d5eb75f4 100644
> --- a/drivers/gpu/drm/xe/xe_ras.c
> +++ b/drivers/gpu/drm/xe/xe_ras.c
> @@ -365,7 +365,6 @@ static u8 handle_soc_internal_errors(struct xe_device *xe, struct xe_ras_error_a
>  {
>  	struct xe_ras_soc_error *info = (void *)arr->details;
>  	struct xe_ras_soc_error_source *source = &info->source;
> -	struct xe_ras_error_class *counter = &arr->counter;
>  
>  	if (source->csc) {
>  		struct xe_ras_csc_error *csc_error = (void *)info->details;
> @@ -379,19 +378,18 @@ static u8 handle_soc_internal_errors(struct xe_device *xe, struct xe_ras_error_a
>  		 * is required.
>  		 */
>  		if (csc_error->hec_fw_error) {
> -			xe_err(xe, "[RAS]: CSC %s detected: 0x%x\n",
> -			       sev_to_str(counter->common.severity),
> -			       csc_error->hec_fw_error);
> -			xe_survivability_mode_runtime_enable(xe);
> +			xe_log_comp_fatal(xe, SOC_INTERNAL, &arr->counter, sizeof(arr->counter),
> +					  "CSC error detected: 0x%x\n", csc_error->hec_fw_error);
> +		xe_survivability_mode_runtime_enable(xe);

please fix the identation here, this survivability line change cannot appear in the
patch.

with that fixed: Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>

>  			return XE_RAS_RECOVERY_ACTION_DISCONNECT;
>  		}
>  	} else if (source->ieh) {
>  		struct xe_ras_ieh_error *ieh_error = (void *)info->details;
>  
>  		if (ieh_error->global_error_status & XE_RAS_SOC_IEH_PUNIT) {
> -			xe_err(xe, "[RAS]: PUNIT %s detected: 0x%x\n",
> -			       sev_to_str(counter->common.severity),
> -			       ieh_error->global_error_status);
> +			xe_log_comp_fatal(xe, SOC_INTERNAL, &arr->counter, sizeof(arr->counter),
> +					  "PUNIT error detected: 0x%x\n",
> +					  ieh_error->global_error_status);
>  			punit_error_handler(xe);
>  			return XE_RAS_RECOVERY_ACTION_DISCONNECT;
>  		}
> -- 
> 2.54.0
> 

Re: [PATCH v2 03/11] drm/xe/cper: Add CPER structures and trace event

[Rodrigo Vivi]

On Tue, Aug 25, 2026 at 11:29:20PM +0530, Badal Nilawar wrote:
> Define packed data structures and Intel-specific GUID macros needed
> to build Intel GPU CPER (Common Platform Error Record) non-standard
> records.
> 
> Add xe_error_cper trace event to log the assembled CPER record bytes.
> 
> Signed-off-by: Badal Nilawar <badal.nilawar@intel.com>
> Assisted-by: Copilot:claude-sonnet-4.6
> ---
>  drivers/gpu/drm/xe/Makefile        |   1 +
>  drivers/gpu/drm/xe/xe_cper_types.h | 186 +++++++++++++++++++++++++++++
>  drivers/gpu/drm/xe/xe_trace_cper.c |   9 ++
>  drivers/gpu/drm/xe/xe_trace_cper.h |  66 ++++++++++
>  4 files changed, 262 insertions(+)
>  create mode 100644 drivers/gpu/drm/xe/xe_cper_types.h
>  create mode 100644 drivers/gpu/drm/xe/xe_trace_cper.c
>  create mode 100644 drivers/gpu/drm/xe/xe_trace_cper.h
> 
> diff --git a/drivers/gpu/drm/xe/Makefile b/drivers/gpu/drm/xe/Makefile
> index 92134709d998..3ed60697f3f3 100644
> --- a/drivers/gpu/drm/xe/Makefile
> +++ b/drivers/gpu/drm/xe/Makefile
> @@ -136,6 +136,7 @@ xe-y += xe_bb.o \
>  	xe_tlb_inval_job.o \
>  	xe_trace.o \
>  	xe_trace_bo.o \
> +	xe_trace_cper.o \
>  	xe_trace_guc.o \
>  	xe_trace_lrc.o \
>  	xe_ttm_stolen_mgr.o \
> diff --git a/drivers/gpu/drm/xe/xe_cper_types.h b/drivers/gpu/drm/xe/xe_cper_types.h
> new file mode 100644
> index 000000000000..82167ea4eb16
> --- /dev/null
> +++ b/drivers/gpu/drm/xe/xe_cper_types.h
> @@ -0,0 +1,186 @@
> +/* SPDX-License-Identifier: MIT */
> +/*
> + * Copyright © 2026 Intel Corporation
> + */
> +
> +#ifndef _XE_CPER_TYPES_H_
> +#define _XE_CPER_TYPES_H_
> +
> +#include <linux/cper.h>
> +#include <linux/types.h>
> +#include <linux/uuid.h>
> +
> +/* Intel CPER GUID Namespace — RFC 9562 UUIDv5 (SHA-1 name-based)
> + *
> + * All values below are generated deterministically by the shell script
> + * in the [Generation Script] section. Re-run that script to verify.
> + * Do NOT hand-edit the byte values.
> + */
> +
> +/* Creator IDs */
> +#define INTEL_CPER_CREATOR_XEKMD \
> +	GUID_INIT(0x9a42070f, 0xdf9d, 0x555e, \
> +		  0xba, 0x02, 0x7c, 0xbc, 0x86, 0x3d, 0x37, 0x1c)
> +
> +#define INTEL_CPER_CREATOR_AMC \
> +	GUID_INIT(0x215803da, 0xfc7a, 0x5925, \
> +		  0xb7, 0x8b, 0x1f, 0xc1, 0x19, 0x61, 0x58, 0xd1)
> +
> +/* Notification Types */
> +#define INTEL_CPER_NOTIFY_GPU_ERROR \
> +	GUID_INIT(0x4ae12aef, 0x8745, 0x5fc7, \
> +		  0xb9, 0x96, 0x71, 0xee, 0xbb, 0x51, 0xf2, 0x23)
> +
> +#define INTEL_CPER_NOTIFY_DRV_ERROR \
> +	GUID_INIT(0xcef7e934, 0x51e7, 0x535f, \
> +		  0xa6, 0x78, 0x5a, 0x4c, 0xcc, 0xb6, 0x96, 0x09)
> +
> +/* Section Types */
> +#define INTEL_CPER_SECTION_ACCEL_GENERIC \
> +	GUID_INIT(0xea9d8f84, 0x4258, 0x5227, \
> +		  0x80, 0x28, 0xb9, 0xb1, 0x3e, 0x6d, 0x58, 0xb0)

Where all these numbers come from?

> +
> +#pragma pack(push, 1)
> +
> +/**
> + * struct xe_cper_sec_intel_err_hdr - Intel-specific CPER error section header
> + *
> + * Fixed-size header for the Intel GPU error section of a CPER record.
> + * All multi-byte fields are little-endian; the structure is packed.
> + */
> +struct xe_cper_sec_intel_err_hdr {
> +	/** @error_class: Error classification (type, component, location, cause) */
> +	union {
> +		struct {
> +			/** @error_class.error_type: RAS error severity */
> +			u8  error_type;
> +			/** @error_class.error_component: IP block that raised the error */
> +			u8  error_component;
> +			/** @error_class.tile: Tile number */
> +			u8  tile;
> +			/** @error_class.instance: Instance within the tile */
> +			u32 instance;
> +			/** @error_class.cause: Error cause code */
> +			u32 cause;
> +			/** @error_class.reserved: Reserved, must be zero */
> +			u8  reserved;
> +		} error_class;
> +		/** @class: Raw byte view of the error class */
> +		u8 class[12];
> +	};
> +	/** @first_timestamp: Timestamp of the first occurrence of this error class */
> +	u64 first_timestamp;
> +	/** @sig_id: Aggregated error class SIG ID; set to U32_MAX if unknown */
> +	u32 sig_id;
> +	/** @error_count: Number of times this error has been observed */
> +	u32 error_count;
> +	/** @valid_bits: Bitmask indicating which header fields are populated */
> +	union {
> +		struct {
> +			/** @valid_bits.location: @error_class field is valid */
> +			u16 location		: 1;
> +			/** @valid_bits.first_timestamp: @first_timestamp field is valid */
> +			u16 first_timestamp	: 1;
> +			/** @valid_bits.sig_id: @sig_id field is valid */
> +			u16 sig_id			: 1;
> +			/** @valid_bits.pci_bdf: @pci_bdf field is valid */
> +			u16 pci_bdf		: 1;
> +			/** @valid_bits.drv_version: @drv_version field is valid */
> +			u16 drv_version		: 1;
> +			/** @valid_bits.fw_id: @fw_id field is valid */
> +			u16 fw_id			: 1;
> +			/** @valid_bits.reserved: Reserved, must be zero */
> +			u16 reserved		: 10;
> +		} valid_bits;
> +		/** @validation_bits: Raw u16 view of all valid bits */
> +		u16 validation_bits;
> +	};
> +	/** @pci_bdf: PCI location string, format "DDDD:bb:dd.f" */
> +	char pci_bdf[16];
> +	/** @drv_version: Driver source version string (THIS_MODULE->srcversion) */
> +	char drv_version[25];
> +	/** @fw_id: Firmware version string (GFSP+PCODE+CSC+GUC or MNG+NUC+RAS+GUC) */
> +	char fw_id[256];
> +	/** @reserved: Reserved for future use, must be zero */
> +	u8 reserved[5];
> +};
> +
> +/**
> + * struct xe_cper_sec_intel_error_info - Variable-length Intel GPU error payload
> + *
> + * Appended after &xe_cper_sec_intel_err_hdr when detailed per-event data
> + * is available. The @event_queue flexible array holds @event_queue_count
> + * packed &xe_intel_priv_event_entry records.
> + */
> +struct xe_cper_sec_intel_error_info {
> +	/** @error_class: Error classification (mirrors the header error_class) */
> +	union {
> +		struct {
> +			u8  error_type;
> +			u8  error_component;
> +			u8  tile;
> +			u32 instance;
> +			u32 cause;
> +			u8  reserved;
> +		} error_class;
> +		/** @class: Raw byte view of the error class */
> +		u8 class[12];
> +	};
> +	/** @error_count: Total number of errors recorded */
> +	u32 error_count;
> +	/** @event_queue_length: Total byte size of the @event_queue array */
> +	u32 event_queue_length;
> +	/** @event_queue_count: Number of entries in @event_queue */
> +	u32 event_queue_count;
> +	/** @event_queue: Packed array of &xe_intel_priv_event_entry records */
> +	u8 event_queue[];
> +};
> +
> +/**
> + * struct xe_intel_priv_event_entry - Single error event in the event queue
> + *
> + * Each entry is variable-length; @entry_length gives the byte size of
> + * @metadata only (not including @entry_length or @timestamp).
> + */
> +struct xe_intel_priv_event_entry {
> +	/** @entry_length: Byte length of the @metadata payload */
> +	u32 entry_length;
> +	/** @timestamp: Hardware timestamp of this event */
> +	u64 timestamp;
> +	/** @metadata: Event-specific payload bytes */
> +	u8  metadata[];
> +};
> +
> +/**
> + * struct xe_cper_nonstd_record - Fixed-size portion of an Intel GPU CPER record
> + *
> + * Contains the standard CPER record header, section descriptor, and the
> + * Intel error section header. A &xe_cper_sec_intel_error_info payload
> + * (with its flexible @event_queue array) is appended dynamically.
> + */
> +struct xe_cper_nonstd_record {
> +	/** @record_hdr: Standard CPER record header (UEFI Appendix N.2.1) */
> +	struct cper_record_header record_hdr;
> +	/** @section_desc: CPER section descriptor */
> +	struct cper_section_descriptor section_desc;
> +	/** @intel_hdr: Intel-specific error section header */
> +	struct xe_cper_sec_intel_err_hdr intel_hdr;
> +};
> +
> +#pragma pack(pop)
> +
> +/**
> + * struct xe_platform_id_entry - Mapping from PCI device ID to CPER platform GUID
> + *
> + * Used to resolve the platform_id field in a CPER section descriptor.
> + * GUIDs are UUIDv5 (RFC 9562, SHA-1) derived from the Intel CPER namespace
> + * with name string "platform/8086:<dev_id_hex_lower>".
> + */
> +struct xe_platform_id_entry {
> +	/** @device_id: PCI device ID */
> +	u16       device_id;
> +	/** @platform_id: Corresponding UUIDv5 platform GUID */
> +	guid_t    platform_id;
> +};
> +
> +#endif
> diff --git a/drivers/gpu/drm/xe/xe_trace_cper.c b/drivers/gpu/drm/xe/xe_trace_cper.c
> new file mode 100644
> index 000000000000..caea8783ab7c
> --- /dev/null
> +++ b/drivers/gpu/drm/xe/xe_trace_cper.c
> @@ -0,0 +1,9 @@
> +// SPDX-License-Identifier: GPL-2.0-only
> +/*
> + * Copyright © 2026 Intel Corporation
> + */
> +
> +#ifndef __CHECKER__
> +#define CREATE_TRACE_POINTS
> +#include "xe_trace_cper.h"
> +#endif
> diff --git a/drivers/gpu/drm/xe/xe_trace_cper.h b/drivers/gpu/drm/xe/xe_trace_cper.h
> new file mode 100644
> index 000000000000..6d2dbf504888
> --- /dev/null
> +++ b/drivers/gpu/drm/xe/xe_trace_cper.h
> @@ -0,0 +1,66 @@
> +/* SPDX-License-Identifier: GPL-2.0-only */
> +/*
> + * Copyright © 2026 Intel Corporation
> + */
> +
> +#undef TRACE_SYSTEM
> +#define TRACE_SYSTEM xe
> +
> +#if !defined(_XE_TRACE_CPER_H_) || defined(TRACE_HEADER_MULTI_READ)
> +#define _XE_TRACE_CPER_H_
> +
> +#include <linux/tracepoint.h>
> +#include <linux/types.h>
> +
> +#include "xe_cper_types.h"
> +#include "xe_device_types.h"
> +
> +#define __dev_name_xe(xe)	dev_name((xe)->drm.dev)
> +
> +TRACE_EVENT(xe_error_cper,
> +	TP_PROTO(struct xe_device *xe,
> +	    const guid_t *platform_id, const guid_t *fru_id,
> +	    const u8 severity,
> +	    const struct xe_cper_sec_intel_err_hdr *ihdr,
> +	    u32 cper_len, const u8 *cper),
> +	TP_ARGS(xe, platform_id, fru_id, severity, ihdr, cper_len, cper),
> +
> +	TP_STRUCT__entry(
> +	    __string(dev, __dev_name_xe(xe))
> +	    __array(char, platform_id, UUID_SIZE)
> +	    __array(char, fru_id, UUID_SIZE)
> +	    __field(u8, sev)
> +	    __array(u8, ihdr_raw, sizeof(struct xe_cper_sec_intel_err_hdr))
> +	    __field(u32, cper_len)
> +	    __dynamic_array(u8, cper, cper_len)
> +	    ),
> +
> +	TP_fast_assign(
> +	    __assign_str(dev);
> +	    __entry->sev = severity;
> +	    memcpy(__entry->platform_id, platform_id, UUID_SIZE);
> +	    memcpy(__entry->fru_id, fru_id, UUID_SIZE);
> +	    memcpy(__entry->ihdr_raw, ihdr, sizeof(struct xe_cper_sec_intel_err_hdr));
> +	    __entry->cper_len = cper_len;
> +	    memcpy(__get_dynamic_array(cper), cper, cper_len);
> +	    ),
> +
> +	TP_printk("dev=%s severity=%d platform_id=%pU fru_id=%pU "
> +		"intel_err_hdr_raw=%s cper_len=%u cper_raw=%s",
> +		__get_str(dev), __entry->sev,
> +		__entry->platform_id, __entry->fru_id,
> +		__print_hex(__entry->ihdr_raw,
> +		    sizeof(struct xe_cper_sec_intel_err_hdr)),
> +		__entry->cper_len,
> +		__print_hex(__get_dynamic_array(cper),
> +		    __entry->cper_len))
> +);
> +
> +#endif
> +
> +/* This part must be outside protection */
> +#undef TRACE_INCLUDE_PATH
> +#undef TRACE_INCLUDE_FILE
> +#define TRACE_INCLUDE_PATH ../../drivers/gpu/drm/xe
> +#define TRACE_INCLUDE_FILE xe_trace_cper
> +#include <trace/define_trace.h>
> -- 
> 2.54.0
>