* [CI] drm/xe: Disable scheduling early on FD close to avoid CAT error cascade
@ 2026-08-25 20:11 Matthew Brost
2026-08-25 20:21 ` ✓ CI.KUnit: success for drm/xe: Disable scheduling early on FD close to avoid CAT error cascade (rev5) Patchwork
` (2 more replies)
0 siblings, 3 replies; 6+ messages in thread
From: Matthew Brost @ 2026-08-25 20:11 UTC (permalink / raw)
To: intel-xe; +Cc: Wang Xin, Jia Yao, Jonathan Cavitt
When an FD is closed with many exec queues, teardown relies on the TDR
path to clean up scheduling. However, the TDR handling is serialized
(i.e., only one exec queue is processed at a time), which can make it
too slow compared to GuC scheduling activity.
In this window, GuC may continue to schedule contexts backed by
invalid page tables, leading to a cascade of CAT errors and repeated
engine resets. This significantly increases recovery time and can
degrade system stability.
To mitigate this, eagerly disable scheduling by sending a self-message
outside of the TDR path. This prevents further scheduling of invalid
contexts and avoids the CAT error/reset cascade.
This change improves robustness and reduces recovery latency in
multiple queue teardown scenarios.
Cc: Wang Xin <x.wang@intel.com>
Cc: Jia Yao <jia.yao@intel.com>
Signed-off-by: Matthew Brost <matthew.brost@intel.com>
Tested-by: Jia Yao <jia.yao@intel.com>
Reviewed-by: Jonathan Cavitt <jonathan.cavitt@intel.com>
---
drivers/gpu/drm/xe/xe_guc_exec_queue_types.h | 2 +-
drivers/gpu/drm/xe/xe_guc_submit.c | 45 ++++++++++++++++++--
2 files changed, 42 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/xe/xe_guc_exec_queue_types.h b/drivers/gpu/drm/xe/xe_guc_exec_queue_types.h
index d27826b36649..a46cde5ed81f 100644
--- a/drivers/gpu/drm/xe/xe_guc_exec_queue_types.h
+++ b/drivers/gpu/drm/xe/xe_guc_exec_queue_types.h
@@ -36,7 +36,7 @@ struct xe_guc_exec_queue {
* a message needs to sent through the GPU scheduler but memory
* allocations are not allowed.
*/
-#define MAX_STATIC_MSG_TYPE 4
+#define MAX_STATIC_MSG_TYPE 5
struct xe_sched_msg static_msgs[MAX_STATIC_MSG_TYPE];
/** @destroy_async: do final destroy async from this worker */
struct work_struct destroy_async;
diff --git a/drivers/gpu/drm/xe/xe_guc_submit.c b/drivers/gpu/drm/xe/xe_guc_submit.c
index 99d8c807ff05..8b8972b2ebea 100644
--- a/drivers/gpu/drm/xe/xe_guc_submit.c
+++ b/drivers/gpu/drm/xe/xe_guc_submit.c
@@ -1969,12 +1969,22 @@ static void __guc_exec_queue_process_msg_cgp_sync(struct xe_sched_msg *msg,
guc_exec_queue_send_cgp_sync(q, 0);
}
+static void __guc_exec_queue_process_msg_kill(struct xe_sched_msg *msg)
+{
+ struct xe_exec_queue *q = msg->private_data;
+ struct xe_exec_queue *primary = xe_exec_queue_multi_queue_primary(q);
+
+ if (exec_queue_enabled(primary))
+ disable_scheduling(primary, true);
+}
+
#define CLEANUP 1 /* Non-zero values to catch uninitialized msg */
#define SET_SCHED_PROPS 2
#define SUSPEND 3
#define RESUME 4
#define SET_MULTI_QUEUE_PRIORITY 5
#define CGP_SYNC_MSG 6
+#define KILL 7
#define OPCODE_MASK 0xf
#define MSG_LOCKED BIT(8)
#define MSG_HEAD BIT(9)
@@ -2008,6 +2018,9 @@ static void guc_exec_queue_process_msg(struct xe_sched_msg *msg)
case CGP_SYNC_MSG:
__guc_exec_queue_process_msg_cgp_sync(msg, bound);
break;
+ case KILL:
+ __guc_exec_queue_process_msg_kill(msg);
+ break;
default:
XE_WARN_ON("Unknown message type");
}
@@ -2130,11 +2143,39 @@ static int guc_exec_queue_init(struct xe_exec_queue *q)
return err;
}
+static bool guc_exec_queue_try_add_msg(struct xe_exec_queue *q,
+ struct xe_sched_msg *msg,
+ u32 opcode);
+
+#define STATIC_MSG_CLEANUP 0
+#define STATIC_MSG_SUSPEND 1
+#define STATIC_MSG_RESUME 2
+#define STATIC_MSG_CGP_SYNC 3
+#define STATIC_MSG_KILL 4
static void guc_exec_queue_kill(struct xe_exec_queue *q)
{
+ struct xe_sched_msg *msg = q->guc->static_msgs + STATIC_MSG_KILL;
+
trace_xe_exec_queue_kill(q);
set_exec_queue_killed(q);
__suspend_fence_signal(q);
+
+ /*
+ * We eagerly send a message to ourselves to disable scheduling, as the
+ * TDR is serialized (i.e., only one exec queue is processed at a time).
+ * If an FD is closed with many exec queues, the TDR can be slower than
+ * the GuC scheduling contexts with invalid page tables, creating a
+ * cascade of CAT errors and engine resets, which is quite slow. Avoid
+ * this by immediately disabling scheduling outside of the TDR.
+ */
+ if (kref_read(&q->refcount) && !exec_queue_wedged(q)) {
+ struct xe_gpu_scheduler *sched = &q->guc->sched;
+
+ xe_sched_msg_lock(sched);
+ guc_exec_queue_try_add_msg(q, msg, KILL);
+ xe_sched_msg_unlock(sched);
+ }
+
xe_guc_exec_queue_trigger_cleanup(q);
}
@@ -2187,10 +2228,6 @@ static bool guc_exec_queue_try_add_msg(struct xe_exec_queue *q,
return true;
}
-#define STATIC_MSG_CLEANUP 0
-#define STATIC_MSG_SUSPEND 1
-#define STATIC_MSG_RESUME 2
-#define STATIC_MSG_CGP_SYNC 3
static void guc_exec_queue_destroy(struct xe_exec_queue *q)
{
struct xe_sched_msg *msg = q->guc->static_msgs + STATIC_MSG_CLEANUP;
--
2.34.1
^ permalink raw reply related [flat|nested] 6+ messages in thread* ✓ CI.KUnit: success for drm/xe: Disable scheduling early on FD close to avoid CAT error cascade (rev5)
2026-08-25 20:11 [CI] drm/xe: Disable scheduling early on FD close to avoid CAT error cascade Matthew Brost
@ 2026-08-25 20:21 ` Patchwork
2026-08-25 20:29 ` [CI] drm/xe: Disable scheduling early on FD close to avoid CAT error cascade sashiko-bot
2026-08-25 21:04 ` ✓ Xe.CI.BAT: success for drm/xe: Disable scheduling early on FD close to avoid CAT error cascade (rev5) Patchwork
2 siblings, 0 replies; 6+ messages in thread
From: Patchwork @ 2026-08-25 20:21 UTC (permalink / raw)
To: Matthew Brost; +Cc: intel-xe
== Series Details ==
Series: drm/xe: Disable scheduling early on FD close to avoid CAT error cascade (rev5)
URL : https://patchwork.freedesktop.org/series/168398/
State : success
== Summary ==
+ trap cleanup EXIT
+ /kernel/tools/testing/kunit/kunit.py run --kunitconfig /kernel/drivers/gpu/drm/xe/.kunitconfig
[20:20:00] Configuring KUnit Kernel ...
Generating .config ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
[20:20:04] Building KUnit Kernel ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
Building with:
$ make all compile_commands.json scripts_gdb ARCH=um O=.kunit --jobs=48
[20:20:37] Starting KUnit Kernel (1/1)...
[20:20:37] ============================================================
Running tests with:
$ .kunit/linux kunit.enable=1 mem=1G console=tty kunit_shutdown=halt
[20:20:37] ================== guc_buf (11 subtests) ===================
[20:20:37] [PASSED] test_smallest
[20:20:37] [PASSED] test_largest
[20:20:37] [PASSED] test_granular
[20:20:37] [PASSED] test_unique
[20:20:37] [PASSED] test_overlap
[20:20:37] [PASSED] test_reusable
[20:20:37] [PASSED] test_too_big
[20:20:37] [PASSED] test_flush
[20:20:37] [PASSED] test_lookup
[20:20:37] [PASSED] test_data
[20:20:37] [PASSED] test_class
[20:20:37] ===================== [PASSED] guc_buf =====================
[20:20:37] =================== guc_dbm (7 subtests) ===================
[20:20:37] [PASSED] test_empty
[20:20:37] [PASSED] test_default
[20:20:37] ======================== test_size ========================
[20:20:37] [PASSED] 4
[20:20:37] [PASSED] 8
[20:20:37] [PASSED] 32
[20:20:37] [PASSED] 256
[20:20:37] ==================== [PASSED] test_size ====================
[20:20:37] ======================= test_reuse ========================
[20:20:37] [PASSED] 4
[20:20:37] [PASSED] 8
[20:20:37] [PASSED] 32
[20:20:37] [PASSED] 256
[20:20:37] =================== [PASSED] test_reuse ====================
[20:20:37] =================== test_range_overlap ====================
[20:20:37] [PASSED] 4
[20:20:37] [PASSED] 8
[20:20:37] [PASSED] 32
[20:20:37] [PASSED] 256
[20:20:37] =============== [PASSED] test_range_overlap ================
[20:20:37] =================== test_range_compact ====================
[20:20:37] [PASSED] 4
[20:20:37] [PASSED] 8
[20:20:37] [PASSED] 32
[20:20:37] [PASSED] 256
[20:20:37] =============== [PASSED] test_range_compact ================
[20:20:37] ==================== test_range_spare =====================
[20:20:37] [PASSED] 4
[20:20:37] [PASSED] 8
[20:20:37] [PASSED] 32
[20:20:37] [PASSED] 256
[20:20:37] ================ [PASSED] test_range_spare =================
[20:20:37] ===================== [PASSED] guc_dbm =====================
[20:20:37] =================== guc_idm (6 subtests) ===================
[20:20:37] [PASSED] bad_init
[20:20:37] [PASSED] no_init
[20:20:37] [PASSED] init_fini
[20:20:37] [PASSED] check_used
[20:20:37] [PASSED] check_quota
[20:20:37] [PASSED] check_all
[20:20:37] ===================== [PASSED] guc_idm =====================
[20:20:37] =============== guc_klv_helpers (9 subtests) ===============
[20:20:37] [PASSED] test_count
[20:20:37] [PASSED] test_encode_u32
[20:20:37] [PASSED] test_encode_u64
[20:20:37] [PASSED] test_encode_string
[20:20:37] [PASSED] test_encode_object_raw
[20:20:37] [PASSED] test_encode_object_klv
[20:20:37] [PASSED] test_encode_object_nested
[20:20:37] [PASSED] test_encode_object_basic
[20:20:37] [PASSED] test_print
[20:20:37] ================= [PASSED] guc_klv_helpers =================
[20:20:37] =================== xe_log (4 subtests) ====================
[20:20:37] [PASSED] demo_cper
[20:20:37] [PASSED] demo_dmesg
[20:20:37] ======================= test_dmesg ========================
[20:20:37] [PASSED] test_fatal
[20:20:37] [PASSED] test_fatal_tile
[20:20:37] [PASSED] test_fatal_gt
[20:20:37] [PASSED] test_fatal_comp
[20:20:37] [PASSED] test_fatal_comp_tile
[20:20:37] [PASSED] test_fatal_comp_gt
[20:20:37] [PASSED] test_fatal_all
[20:20:37] [PASSED] test_recoverable
[20:20:37] [PASSED] test_recoverable_tile
[20:20:37] [PASSED] test_recoverable_gt
[20:20:37] [PASSED] test_recoverable_comp
[20:20:37] [PASSED] test_recoverable_comp_tile
[20:20:37] [PASSED] test_recoverable_comp_gt
[20:20:37] [PASSED] test_recoverable_all
[20:20:37] [PASSED] test_info
[20:20:37] [PASSED] test_info_tile
[20:20:37] [PASSED] test_info_gt
[20:20:37] [PASSED] test_info_err
[20:20:37] [PASSED] test_info_comp
[20:20:37] [PASSED] test_info_comp_tile
[20:20:37] [PASSED] test_info_comp_gt
[20:20:37] [PASSED] test_info_all
[20:20:37] [PASSED] test_hw_fatal
[20:20:37] [PASSED] test_hw_recoverable
[20:20:37] [PASSED] test_hw_corrected
[20:20:37] [PASSED] test_hw_informational
[20:20:37] =================== [PASSED] test_dmesg ====================
[20:20:37] ====================== test_invalid =======================
[20:20:37] [SKIPPED] no-component no-location no-warn (requires CONFIG_DRM_XE_DEBUG)
[20:20:37] [SKIPPED] reserved location (requires CONFIG_DRM_XE_DEBUG)
[20:20:37] [SKIPPED] unknown location (requires CONFIG_DRM_XE_DEBUG)
[20:20:37] [SKIPPED] nonzero-device-id location (requires CONFIG_DRM_XE_DEBUG)
[20:20:37] [SKIPPED] invalid-tile-id location (requires CONFIG_DRM_XE_DEBUG)
[20:20:37] [SKIPPED] invalid-gt-id location (requires CONFIG_DRM_XE_DEBUG)
[20:20:37] [SKIPPED] unknown component class (requires CONFIG_DRM_XE_DEBUG)
[20:20:37] [SKIPPED] unknown system component (requires CONFIG_DRM_XE_DEBUG)
[20:20:37] [SKIPPED] unknown hardware component (requires CONFIG_DRM_XE_DEBUG)
[20:20:37] [SKIPPED] unknown component and location (requires CONFIG_DRM_XE_DEBUG)
[20:20:37] ================== [SKIPPED] test_invalid ==================
[20:20:37] ===================== [PASSED] xe_log ======================
[20:20:37] ================== no_relay (3 subtests) ===================
[20:20:37] [PASSED] xe_drops_guc2pf_if_not_ready
[20:20:37] [PASSED] xe_drops_guc2vf_if_not_ready
[20:20:37] [PASSED] xe_rejects_send_if_not_ready
[20:20:37] ==================== [PASSED] no_relay =====================
[20:20:37] ================== pf_relay (14 subtests) ==================
[20:20:37] [PASSED] pf_rejects_guc2pf_too_short
[20:20:37] [PASSED] pf_rejects_guc2pf_too_long
[20:20:37] [PASSED] pf_rejects_guc2pf_no_payload
[20:20:37] [PASSED] pf_fails_no_payload
[20:20:37] [PASSED] pf_fails_bad_origin
[20:20:37] [PASSED] pf_fails_bad_type
[20:20:37] [PASSED] pf_txn_reports_error
[20:20:37] [PASSED] pf_txn_sends_pf2guc
[20:20:37] [PASSED] pf_sends_pf2guc
[20:20:37] [SKIPPED] pf_loopback_nop (requires CONFIG_DRM_XE_DEBUG_SRIOV)
[20:20:37] [SKIPPED] pf_loopback_echo (requires CONFIG_DRM_XE_DEBUG_SRIOV)
[20:20:37] [SKIPPED] pf_loopback_fail (requires CONFIG_DRM_XE_DEBUG_SRIOV)
[20:20:37] [SKIPPED] pf_loopback_busy (requires CONFIG_DRM_XE_DEBUG_SRIOV)
[20:20:37] [SKIPPED] pf_loopback_retry (requires CONFIG_DRM_XE_DEBUG_SRIOV)
[20:20:37] ==================== [PASSED] pf_relay =====================
[20:20:37] ================== vf_relay (3 subtests) ===================
[20:20:37] [PASSED] vf_rejects_guc2vf_too_short
[20:20:37] [PASSED] vf_rejects_guc2vf_too_long
[20:20:37] [PASSED] vf_rejects_guc2vf_no_payload
[20:20:37] ==================== [PASSED] vf_relay =====================
[20:20:37] ================ pf_gt_config (9 subtests) =================
[20:20:37] [PASSED] fair_contexts_1vf
[20:20:37] [PASSED] fair_doorbells_1vf
[20:20:37] [PASSED] fair_ggtt_1vf
[20:20:37] ====================== fair_vram_1vf ======================
[20:20:37] [PASSED] 3.50 GiB
[20:20:37] [PASSED] 11.5 GiB
[20:20:37] [PASSED] 15.5 GiB
[20:20:37] [PASSED] 31.5 GiB
[20:20:37] [PASSED] 63.5 GiB
[20:20:37] [PASSED] 1.91 GiB
[20:20:37] ================== [PASSED] fair_vram_1vf ==================
[20:20:37] ================ fair_vram_1vf_admin_only =================
[20:20:37] [PASSED] 3.50 GiB
[20:20:37] [PASSED] 11.5 GiB
[20:20:37] [PASSED] 15.5 GiB
[20:20:37] [PASSED] 31.5 GiB
[20:20:37] [PASSED] 63.5 GiB
[20:20:37] [PASSED] 1.91 GiB
[20:20:37] ============ [PASSED] fair_vram_1vf_admin_only =============
[20:20:37] ====================== fair_contexts ======================
[20:20:37] [PASSED] 1 VF
[20:20:37] [PASSED] 2 VFs
[20:20:37] [PASSED] 3 VFs
[20:20:37] [PASSED] 4 VFs
[20:20:37] [PASSED] 5 VFs
[20:20:37] [PASSED] 6 VFs
[20:20:37] [PASSED] 7 VFs
[20:20:37] [PASSED] 8 VFs
[20:20:37] [PASSED] 9 VFs
[20:20:37] [PASSED] 10 VFs
[20:20:37] [PASSED] 11 VFs
[20:20:37] [PASSED] 12 VFs
[20:20:37] [PASSED] 13 VFs
[20:20:37] [PASSED] 14 VFs
[20:20:37] [PASSED] 15 VFs
[20:20:37] [PASSED] 16 VFs
[20:20:37] [PASSED] 17 VFs
[20:20:37] [PASSED] 18 VFs
[20:20:37] [PASSED] 19 VFs
[20:20:37] [PASSED] 20 VFs
[20:20:37] [PASSED] 21 VFs
[20:20:37] [PASSED] 22 VFs
[20:20:37] [PASSED] 23 VFs
[20:20:37] [PASSED] 24 VFs
[20:20:37] [PASSED] 25 VFs
[20:20:37] [PASSED] 26 VFs
[20:20:37] [PASSED] 27 VFs
[20:20:37] [PASSED] 28 VFs
[20:20:37] [PASSED] 29 VFs
[20:20:37] [PASSED] 30 VFs
[20:20:37] [PASSED] 31 VFs
[20:20:37] [PASSED] 32 VFs
[20:20:37] [PASSED] 33 VFs
[20:20:37] [PASSED] 34 VFs
[20:20:37] [PASSED] 35 VFs
[20:20:37] [PASSED] 36 VFs
[20:20:37] [PASSED] 37 VFs
[20:20:37] [PASSED] 38 VFs
[20:20:37] [PASSED] 39 VFs
[20:20:37] [PASSED] 40 VFs
[20:20:37] [PASSED] 41 VFs
[20:20:37] [PASSED] 42 VFs
[20:20:37] [PASSED] 43 VFs
[20:20:37] [PASSED] 44 VFs
[20:20:37] [PASSED] 45 VFs
[20:20:37] [PASSED] 46 VFs
[20:20:37] [PASSED] 47 VFs
[20:20:37] [PASSED] 48 VFs
[20:20:37] [PASSED] 49 VFs
[20:20:37] [PASSED] 50 VFs
[20:20:37] [PASSED] 51 VFs
[20:20:37] [PASSED] 52 VFs
[20:20:37] [PASSED] 53 VFs
[20:20:37] [PASSED] 54 VFs
[20:20:37] [PASSED] 55 VFs
[20:20:37] [PASSED] 56 VFs
[20:20:37] [PASSED] 57 VFs
[20:20:37] [PASSED] 58 VFs
[20:20:37] [PASSED] 59 VFs
[20:20:37] [PASSED] 60 VFs
[20:20:37] [PASSED] 61 VFs
[20:20:37] [PASSED] 62 VFs
[20:20:37] [PASSED] 63 VFs
[20:20:37] ================== [PASSED] fair_contexts ==================
[20:20:37] ===================== fair_doorbells ======================
[20:20:37] [PASSED] 1 VF
[20:20:37] [PASSED] 2 VFs
[20:20:37] [PASSED] 3 VFs
[20:20:37] [PASSED] 4 VFs
[20:20:37] [PASSED] 5 VFs
[20:20:37] [PASSED] 6 VFs
[20:20:37] [PASSED] 7 VFs
[20:20:37] [PASSED] 8 VFs
[20:20:37] [PASSED] 9 VFs
[20:20:37] [PASSED] 10 VFs
[20:20:37] [PASSED] 11 VFs
[20:20:37] [PASSED] 12 VFs
[20:20:37] [PASSED] 13 VFs
[20:20:37] [PASSED] 14 VFs
[20:20:37] [PASSED] 15 VFs
[20:20:37] [PASSED] 16 VFs
[20:20:37] [PASSED] 17 VFs
[20:20:37] [PASSED] 18 VFs
[20:20:38] [PASSED] 19 VFs
[20:20:38] [PASSED] 20 VFs
[20:20:38] [PASSED] 21 VFs
[20:20:38] [PASSED] 22 VFs
[20:20:38] [PASSED] 23 VFs
[20:20:38] [PASSED] 24 VFs
[20:20:38] [PASSED] 25 VFs
[20:20:38] [PASSED] 26 VFs
[20:20:38] [PASSED] 27 VFs
[20:20:38] [PASSED] 28 VFs
[20:20:38] [PASSED] 29 VFs
[20:20:38] [PASSED] 30 VFs
[20:20:38] [PASSED] 31 VFs
[20:20:38] [PASSED] 32 VFs
[20:20:38] [PASSED] 33 VFs
[20:20:38] [PASSED] 34 VFs
[20:20:38] [PASSED] 35 VFs
[20:20:38] [PASSED] 36 VFs
[20:20:38] [PASSED] 37 VFs
[20:20:38] [PASSED] 38 VFs
[20:20:38] [PASSED] 39 VFs
[20:20:38] [PASSED] 40 VFs
[20:20:38] [PASSED] 41 VFs
[20:20:38] [PASSED] 42 VFs
[20:20:38] [PASSED] 43 VFs
[20:20:38] [PASSED] 44 VFs
[20:20:38] [PASSED] 45 VFs
[20:20:38] [PASSED] 46 VFs
[20:20:38] [PASSED] 47 VFs
[20:20:38] [PASSED] 48 VFs
[20:20:38] [PASSED] 49 VFs
[20:20:38] [PASSED] 50 VFs
[20:20:38] [PASSED] 51 VFs
[20:20:38] [PASSED] 52 VFs
[20:20:38] [PASSED] 53 VFs
[20:20:38] [PASSED] 54 VFs
[20:20:38] [PASSED] 55 VFs
[20:20:38] [PASSED] 56 VFs
[20:20:38] [PASSED] 57 VFs
[20:20:38] [PASSED] 58 VFs
[20:20:38] [PASSED] 59 VFs
[20:20:38] [PASSED] 60 VFs
[20:20:38] [PASSED] 61 VFs
[20:20:38] [PASSED] 62 VFs
[20:20:38] [PASSED] 63 VFs
[20:20:38] ================= [PASSED] fair_doorbells ==================
[20:20:38] ======================== fair_ggtt ========================
[20:20:38] [PASSED] 1 VF
[20:20:38] [PASSED] 2 VFs
[20:20:38] [PASSED] 3 VFs
[20:20:38] [PASSED] 4 VFs
[20:20:38] [PASSED] 5 VFs
[20:20:38] [PASSED] 6 VFs
[20:20:38] [PASSED] 7 VFs
[20:20:38] [PASSED] 8 VFs
[20:20:38] [PASSED] 9 VFs
[20:20:38] [PASSED] 10 VFs
[20:20:38] [PASSED] 11 VFs
[20:20:38] [PASSED] 12 VFs
[20:20:38] [PASSED] 13 VFs
[20:20:38] [PASSED] 14 VFs
[20:20:38] [PASSED] 15 VFs
[20:20:38] [PASSED] 16 VFs
[20:20:38] [PASSED] 17 VFs
[20:20:38] [PASSED] 18 VFs
[20:20:38] [PASSED] 19 VFs
[20:20:38] [PASSED] 20 VFs
[20:20:38] [PASSED] 21 VFs
[20:20:38] [PASSED] 22 VFs
[20:20:38] [PASSED] 23 VFs
[20:20:38] [PASSED] 24 VFs
[20:20:38] [PASSED] 25 VFs
[20:20:38] [PASSED] 26 VFs
[20:20:38] [PASSED] 27 VFs
[20:20:38] [PASSED] 28 VFs
[20:20:38] [PASSED] 29 VFs
[20:20:38] [PASSED] 30 VFs
[20:20:38] [PASSED] 31 VFs
[20:20:38] [PASSED] 32 VFs
[20:20:38] [PASSED] 33 VFs
[20:20:38] [PASSED] 34 VFs
[20:20:38] [PASSED] 35 VFs
[20:20:38] [PASSED] 36 VFs
[20:20:38] [PASSED] 37 VFs
[20:20:38] [PASSED] 38 VFs
[20:20:38] [PASSED] 39 VFs
[20:20:38] [PASSED] 40 VFs
[20:20:38] [PASSED] 41 VFs
[20:20:38] [PASSED] 42 VFs
[20:20:38] [PASSED] 43 VFs
[20:20:38] [PASSED] 44 VFs
[20:20:38] [PASSED] 45 VFs
[20:20:38] [PASSED] 46 VFs
[20:20:38] [PASSED] 47 VFs
[20:20:38] [PASSED] 48 VFs
[20:20:38] [PASSED] 49 VFs
[20:20:38] [PASSED] 50 VFs
[20:20:38] [PASSED] 51 VFs
[20:20:38] [PASSED] 52 VFs
[20:20:38] [PASSED] 53 VFs
[20:20:38] [PASSED] 54 VFs
[20:20:38] [PASSED] 55 VFs
[20:20:38] [PASSED] 56 VFs
[20:20:38] [PASSED] 57 VFs
[20:20:38] [PASSED] 58 VFs
[20:20:38] [PASSED] 59 VFs
[20:20:38] [PASSED] 60 VFs
[20:20:38] [PASSED] 61 VFs
[20:20:38] [PASSED] 62 VFs
[20:20:38] [PASSED] 63 VFs
[20:20:38] ==================== [PASSED] fair_ggtt ====================
[20:20:38] ======================== fair_vram ========================
[20:20:38] [PASSED] 1 VF
[20:20:38] [PASSED] 2 VFs
[20:20:38] [PASSED] 3 VFs
[20:20:38] [PASSED] 4 VFs
[20:20:38] [PASSED] 5 VFs
[20:20:38] [PASSED] 6 VFs
[20:20:38] [PASSED] 7 VFs
[20:20:38] [PASSED] 8 VFs
[20:20:38] [PASSED] 9 VFs
[20:20:38] [PASSED] 10 VFs
[20:20:38] [PASSED] 11 VFs
[20:20:38] [PASSED] 12 VFs
[20:20:38] [PASSED] 13 VFs
[20:20:38] [PASSED] 14 VFs
[20:20:38] [PASSED] 15 VFs
[20:20:38] [PASSED] 16 VFs
[20:20:38] [PASSED] 17 VFs
[20:20:38] [PASSED] 18 VFs
[20:20:38] [PASSED] 19 VFs
[20:20:38] [PASSED] 20 VFs
[20:20:38] [PASSED] 21 VFs
[20:20:38] [PASSED] 22 VFs
[20:20:38] [PASSED] 23 VFs
[20:20:38] [PASSED] 24 VFs
[20:20:38] [PASSED] 25 VFs
[20:20:38] [PASSED] 26 VFs
[20:20:38] [PASSED] 27 VFs
[20:20:38] [PASSED] 28 VFs
[20:20:38] [PASSED] 29 VFs
[20:20:38] [PASSED] 30 VFs
[20:20:38] [PASSED] 31 VFs
[20:20:38] [PASSED] 32 VFs
[20:20:38] [PASSED] 33 VFs
[20:20:38] [PASSED] 34 VFs
[20:20:38] [PASSED] 35 VFs
[20:20:38] [PASSED] 36 VFs
[20:20:38] [PASSED] 37 VFs
[20:20:38] [PASSED] 38 VFs
[20:20:38] [PASSED] 39 VFs
[20:20:38] [PASSED] 40 VFs
[20:20:38] [PASSED] 41 VFs
[20:20:38] [PASSED] 42 VFs
[20:20:38] [PASSED] 43 VFs
[20:20:38] [PASSED] 44 VFs
[20:20:38] [PASSED] 45 VFs
[20:20:38] [PASSED] 46 VFs
[20:20:38] [PASSED] 47 VFs
[20:20:38] [PASSED] 48 VFs
[20:20:38] [PASSED] 49 VFs
[20:20:38] [PASSED] 50 VFs
[20:20:38] [PASSED] 51 VFs
[20:20:38] [PASSED] 52 VFs
[20:20:38] [PASSED] 53 VFs
[20:20:38] [PASSED] 54 VFs
[20:20:38] [PASSED] 55 VFs
[20:20:38] [PASSED] 56 VFs
[20:20:38] [PASSED] 57 VFs
[20:20:38] [PASSED] 58 VFs
[20:20:38] [PASSED] 59 VFs
[20:20:38] [PASSED] 60 VFs
[20:20:38] [PASSED] 61 VFs
[20:20:38] [PASSED] 62 VFs
[20:20:38] [PASSED] 63 VFs
[20:20:38] ==================== [PASSED] fair_vram ====================
[20:20:38] ================== [PASSED] pf_gt_config ===================
[20:20:38] ===================== lmtt (1 subtest) =====================
[20:20:38] ======================== test_ops =========================
[20:20:38] [PASSED] 2-level
[20:20:38] [PASSED] multi-level
[20:20:38] ==================== [PASSED] test_ops =====================
[20:20:38] ====================== [PASSED] lmtt =======================
[20:20:38] ================= sriov_packet (1 subtest) =================
[20:20:38] [PASSED] test_descriptor_init
[20:20:38] ================== [PASSED] sriov_packet ===================
[20:20:38] ================= pf_service (11 subtests) =================
[20:20:38] [PASSED] pf_negotiate_any
[20:20:38] [PASSED] pf_negotiate_base_match
[20:20:38] [PASSED] pf_negotiate_base_newer
[20:20:38] [PASSED] pf_negotiate_base_next
[20:20:38] [SKIPPED] pf_negotiate_base_older (no older minor)
[20:20:38] [PASSED] pf_negotiate_base_prev
[20:20:38] [PASSED] pf_negotiate_latest_match
[20:20:38] [PASSED] pf_negotiate_latest_newer
[20:20:38] [PASSED] pf_negotiate_latest_next
[20:20:38] [SKIPPED] pf_negotiate_latest_older (no older minor)
[20:20:38] [SKIPPED] pf_negotiate_latest_prev (no prev major)
[20:20:38] =================== [PASSED] pf_service ====================
[20:20:38] ================= xe_guc_g2g (2 subtests) ==================
[20:20:38] ============== xe_live_guc_g2g_kunit_default ==============
[20:20:38] ========= [SKIPPED] xe_live_guc_g2g_kunit_default ==========
[20:20:38] ============== xe_live_guc_g2g_kunit_allmem ===============
[20:20:38] ========== [SKIPPED] xe_live_guc_g2g_kunit_allmem ==========
[20:20:38] =================== [SKIPPED] xe_guc_g2g ===================
[20:20:38] =================== xe_mocs (2 subtests) ===================
[20:20:38] ================ xe_live_mocs_kernel_kunit ================
[20:20:38] =========== [SKIPPED] xe_live_mocs_kernel_kunit ============
[20:20:38] ================ xe_live_mocs_reset_kunit =================
[20:20:38] ============ [SKIPPED] xe_live_mocs_reset_kunit ============
[20:20:38] ==================== [SKIPPED] xe_mocs =====================
[20:20:38] ================= xe_migrate (2 subtests) ==================
[20:20:38] ================= xe_migrate_sanity_kunit =================
[20:20:38] ============ [SKIPPED] xe_migrate_sanity_kunit =============
[20:20:38] ================== xe_validate_ccs_kunit ==================
[20:20:38] ============= [SKIPPED] xe_validate_ccs_kunit ==============
[20:20:38] =================== [SKIPPED] xe_migrate ===================
[20:20:38] ================== xe_dma_buf (1 subtest) ==================
[20:20:38] ==================== xe_dma_buf_kunit =====================
[20:20:38] ================ [SKIPPED] xe_dma_buf_kunit ================
[20:20:38] =================== [SKIPPED] xe_dma_buf ===================
[20:20:38] ================= xe_bo_shrink (1 subtest) =================
[20:20:38] =================== xe_bo_shrink_kunit ====================
[20:20:38] =============== [SKIPPED] xe_bo_shrink_kunit ===============
[20:20:38] ================== [SKIPPED] xe_bo_shrink ==================
[20:20:38] ==================== xe_bo (2 subtests) ====================
[20:20:38] ================== xe_ccs_migrate_kunit ===================
[20:20:38] ============== [SKIPPED] xe_ccs_migrate_kunit ==============
[20:20:38] ==================== xe_bo_evict_kunit ====================
[20:20:38] =============== [SKIPPED] xe_bo_evict_kunit ================
[20:20:38] ===================== [SKIPPED] xe_bo ======================
[20:20:38] =================== xe_any (9 subtests) ====================
[20:20:38] [PASSED] test_to_xe
[20:20:38] [PASSED] test_to_dev
[20:20:38] [PASSED] test_to_pdev
[20:20:38] [PASSED] test_to_drm
[20:20:38] [PASSED] test_if_pdev
[20:20:38] [PASSED] test_if_xe
[20:20:38] [PASSED] test_if_tile
[20:20:38] [PASSED] test_if_gt
[20:20:38] [PASSED] test_to_id
[20:20:38] ===================== [PASSED] xe_any ======================
[20:20:38] ==================== args (13 subtests) ====================
[20:20:38] [PASSED] count_args_test
[20:20:38] [PASSED] call_args_example
[20:20:38] [PASSED] call_args_test
[20:20:38] [PASSED] drop_first_arg_example
[20:20:38] [PASSED] drop_first_arg_test
[20:20:38] [PASSED] first_arg_example
[20:20:38] [PASSED] first_arg_test
[20:20:38] [PASSED] last_arg_example
[20:20:38] [PASSED] last_arg_test
[20:20:38] [PASSED] pick_arg_example
[20:20:38] [PASSED] if_args_example
[20:20:38] [PASSED] if_args_test
[20:20:38] [PASSED] sep_comma_example
[20:20:38] ====================== [PASSED] args =======================
[20:20:38] =================== xe_pci (3 subtests) ====================
[20:20:38] ==================== check_graphics_ip ====================
[20:20:38] [PASSED] 12.00 Xe_LP
[20:20:38] [PASSED] 12.10 Xe_LP+
[20:20:38] [PASSED] 12.55 Xe_HPG
[20:20:38] [PASSED] 12.60 Xe_HPC
[20:20:38] [PASSED] 12.70 Xe_LPG
[20:20:38] [PASSED] 12.71 Xe_LPG
[20:20:38] [PASSED] 12.74 Xe_LPG+
[20:20:38] [PASSED] 20.01 Xe2_HPG
[20:20:38] [PASSED] 20.02 Xe2_HPG
[20:20:38] [PASSED] 20.04 Xe2_LPG
[20:20:38] [PASSED] 30.00 Xe3_LPG
[20:20:38] [PASSED] 30.01 Xe3_LPG
[20:20:38] [PASSED] 30.03 Xe3_LPG
[20:20:38] [PASSED] 30.04 Xe3_LPG
[20:20:38] [PASSED] 30.05 Xe3_LPG
[20:20:38] [PASSED] 35.10 Xe3p_LPG
[20:20:38] [PASSED] 35.11 Xe3p_XPC
[20:20:38] ================ [PASSED] check_graphics_ip ================
[20:20:38] ===================== check_media_ip ======================
[20:20:38] [PASSED] 12.00 Xe_M
[20:20:38] [PASSED] 12.55 Xe_HPM
[20:20:38] [PASSED] 13.00 Xe_LPM+
[20:20:38] [PASSED] 13.01 Xe2_HPM
[20:20:38] [PASSED] 20.00 Xe2_LPM
[20:20:38] [PASSED] 30.00 Xe3_LPM
[20:20:38] [PASSED] 30.02 Xe3_LPM
[20:20:38] [PASSED] 35.00 Xe3p_LPM
[20:20:38] [PASSED] 35.03 Xe3p_HPM
[20:20:38] ================= [PASSED] check_media_ip ==================
[20:20:38] =================== check_platform_desc ===================
[20:20:38] [PASSED] 0x9A60 (TIGERLAKE)
[20:20:38] [PASSED] 0x9A68 (TIGERLAKE)
[20:20:38] [PASSED] 0x9A70 (TIGERLAKE)
[20:20:38] [PASSED] 0x9A40 (TIGERLAKE)
[20:20:38] [PASSED] 0x9A49 (TIGERLAKE)
[20:20:38] [PASSED] 0x9A59 (TIGERLAKE)
[20:20:38] [PASSED] 0x9A78 (TIGERLAKE)
[20:20:38] [PASSED] 0x9AC0 (TIGERLAKE)
[20:20:38] [PASSED] 0x9AC9 (TIGERLAKE)
[20:20:38] [PASSED] 0x9AD9 (TIGERLAKE)
[20:20:38] [PASSED] 0x9AF8 (TIGERLAKE)
[20:20:38] [PASSED] 0x4C80 (ROCKETLAKE)
[20:20:38] [PASSED] 0x4C8A (ROCKETLAKE)
[20:20:38] [PASSED] 0x4C8B (ROCKETLAKE)
[20:20:38] [PASSED] 0x4C8C (ROCKETLAKE)
[20:20:38] [PASSED] 0x4C90 (ROCKETLAKE)
[20:20:38] [PASSED] 0x4C9A (ROCKETLAKE)
[20:20:38] [PASSED] 0x4680 (ALDERLAKE_S)
[20:20:38] [PASSED] 0x4682 (ALDERLAKE_S)
[20:20:38] [PASSED] 0x4688 (ALDERLAKE_S)
[20:20:38] [PASSED] 0x468A (ALDERLAKE_S)
[20:20:38] [PASSED] 0x468B (ALDERLAKE_S)
[20:20:38] [PASSED] 0x4690 (ALDERLAKE_S)
[20:20:38] [PASSED] 0x4692 (ALDERLAKE_S)
[20:20:38] [PASSED] 0x4693 (ALDERLAKE_S)
[20:20:38] [PASSED] 0x46A0 (ALDERLAKE_P)
[20:20:38] [PASSED] 0x46A1 (ALDERLAKE_P)
[20:20:38] [PASSED] 0x46A2 (ALDERLAKE_P)
[20:20:38] [PASSED] 0x46A3 (ALDERLAKE_P)
[20:20:38] [PASSED] 0x46A6 (ALDERLAKE_P)
[20:20:38] [PASSED] 0x46A8 (ALDERLAKE_P)
[20:20:38] [PASSED] 0x46AA (ALDERLAKE_P)
[20:20:38] [PASSED] 0x462A (ALDERLAKE_P)
[20:20:38] [PASSED] 0x4626 (ALDERLAKE_P)
[20:20:38] [PASSED] 0x4628 (ALDERLAKE_P)
[20:20:38] [PASSED] 0x46B0 (ALDERLAKE_P)
[20:20:38] [PASSED] 0x46B1 (ALDERLAKE_P)
[20:20:38] [PASSED] 0x46B2 (ALDERLAKE_P)
[20:20:38] [PASSED] 0x46B3 (ALDERLAKE_P)
[20:20:38] [PASSED] 0x46C0 (ALDERLAKE_P)
[20:20:38] [PASSED] 0x46C1 (ALDERLAKE_P)
[20:20:38] [PASSED] 0x46C2 (ALDERLAKE_P)
[20:20:38] [PASSED] 0x46C3 (ALDERLAKE_P)
[20:20:38] [PASSED] 0x46D0 (ALDERLAKE_N)
[20:20:38] [PASSED] 0x46D1 (ALDERLAKE_N)
[20:20:38] [PASSED] 0x46D2 (ALDERLAKE_N)
[20:20:38] [PASSED] 0x46D3 (ALDERLAKE_N)
[20:20:38] [PASSED] 0x46D4 (ALDERLAKE_N)
[20:20:38] [PASSED] 0xA721 (ALDERLAKE_P)
[20:20:38] [PASSED] 0xA7A1 (ALDERLAKE_P)
[20:20:38] [PASSED] 0xA7A9 (ALDERLAKE_P)
[20:20:38] [PASSED] 0xA7AC (ALDERLAKE_P)
[20:20:38] [PASSED] 0xA7AD (ALDERLAKE_P)
[20:20:38] [PASSED] 0xA720 (ALDERLAKE_P)
[20:20:38] [PASSED] 0xA7A0 (ALDERLAKE_P)
[20:20:38] [PASSED] 0xA7A8 (ALDERLAKE_P)
[20:20:38] [PASSED] 0xA7AA (ALDERLAKE_P)
[20:20:38] [PASSED] 0xA7AB (ALDERLAKE_P)
[20:20:38] [PASSED] 0xA780 (ALDERLAKE_S)
[20:20:38] [PASSED] 0xA781 (ALDERLAKE_S)
[20:20:38] [PASSED] 0xA782 (ALDERLAKE_S)
[20:20:38] [PASSED] 0xA783 (ALDERLAKE_S)
[20:20:38] [PASSED] 0xA788 (ALDERLAKE_S)
[20:20:38] [PASSED] 0xA789 (ALDERLAKE_S)
[20:20:38] [PASSED] 0xA78A (ALDERLAKE_S)
[20:20:38] [PASSED] 0xA78B (ALDERLAKE_S)
[20:20:38] [PASSED] 0x4905 (DG1)
[20:20:38] [PASSED] 0x4906 (DG1)
[20:20:38] [PASSED] 0x4907 (DG1)
[20:20:38] [PASSED] 0x4908 (DG1)
[20:20:38] [PASSED] 0x4909 (DG1)
[20:20:38] [PASSED] 0x56C0 (DG2)
[20:20:38] [PASSED] 0x56C2 (DG2)
[20:20:38] [PASSED] 0x56C1 (DG2)
[20:20:38] [PASSED] 0x7D51 (METEORLAKE)
[20:20:38] [PASSED] 0x7DD1 (METEORLAKE)
[20:20:38] [PASSED] 0x7D41 (METEORLAKE)
[20:20:38] [PASSED] 0x7D67 (METEORLAKE)
[20:20:38] [PASSED] 0xB640 (METEORLAKE)
[20:20:38] [PASSED] 0x56A0 (DG2)
[20:20:38] [PASSED] 0x56A1 (DG2)
[20:20:38] [PASSED] 0x56A2 (DG2)
[20:20:38] [PASSED] 0x56BE (DG2)
[20:20:38] [PASSED] 0x56BF (DG2)
[20:20:38] [PASSED] 0x5690 (DG2)
[20:20:38] [PASSED] 0x5691 (DG2)
[20:20:38] [PASSED] 0x5692 (DG2)
[20:20:38] [PASSED] 0x56A5 (DG2)
[20:20:38] [PASSED] 0x56A6 (DG2)
[20:20:38] [PASSED] 0x56B0 (DG2)
[20:20:38] [PASSED] 0x56B1 (DG2)
[20:20:38] [PASSED] 0x56BA (DG2)
[20:20:38] [PASSED] 0x56BB (DG2)
[20:20:38] [PASSED] 0x56BC (DG2)
[20:20:38] [PASSED] 0x56BD (DG2)
[20:20:38] [PASSED] 0x5693 (DG2)
[20:20:38] [PASSED] 0x5694 (DG2)
[20:20:38] [PASSED] 0x5695 (DG2)
[20:20:38] [PASSED] 0x56A3 (DG2)
[20:20:38] [PASSED] 0x56A4 (DG2)
[20:20:38] [PASSED] 0x56B2 (DG2)
[20:20:38] [PASSED] 0x56B3 (DG2)
[20:20:38] [PASSED] 0x5696 (DG2)
[20:20:38] [PASSED] 0x5697 (DG2)
[20:20:38] [PASSED] 0xB69 (PVC)
[20:20:38] [PASSED] 0xB6E (PVC)
[20:20:38] [PASSED] 0xBD4 (PVC)
[20:20:38] [PASSED] 0xBD5 (PVC)
[20:20:38] [PASSED] 0xBD6 (PVC)
[20:20:38] [PASSED] 0xBD7 (PVC)
[20:20:38] [PASSED] 0xBD8 (PVC)
[20:20:38] [PASSED] 0xBD9 (PVC)
[20:20:38] [PASSED] 0xBDA (PVC)
[20:20:38] [PASSED] 0xBDB (PVC)
[20:20:38] [PASSED] 0xBE0 (PVC)
[20:20:38] [PASSED] 0xBE1 (PVC)
[20:20:38] [PASSED] 0xBE5 (PVC)
[20:20:38] [PASSED] 0x7D40 (METEORLAKE)
[20:20:38] [PASSED] 0x7D45 (METEORLAKE)
[20:20:38] [PASSED] 0x7D55 (METEORLAKE)
[20:20:38] [PASSED] 0x7D60 (METEORLAKE)
[20:20:38] [PASSED] 0x7DD5 (METEORLAKE)
[20:20:38] [PASSED] 0x6420 (LUNARLAKE)
[20:20:38] [PASSED] 0x64A0 (LUNARLAKE)
[20:20:38] [PASSED] 0x64B0 (LUNARLAKE)
[20:20:38] [PASSED] 0xE202 (BATTLEMAGE)
[20:20:38] [PASSED] 0xE209 (BATTLEMAGE)
[20:20:38] [PASSED] 0xE20B (BATTLEMAGE)
[20:20:38] [PASSED] 0xE20C (BATTLEMAGE)
[20:20:38] [PASSED] 0xE20D (BATTLEMAGE)
[20:20:38] [PASSED] 0xE210 (BATTLEMAGE)
[20:20:38] [PASSED] 0xE211 (BATTLEMAGE)
[20:20:38] [PASSED] 0xE212 (BATTLEMAGE)
[20:20:38] [PASSED] 0xE216 (BATTLEMAGE)
[20:20:38] [PASSED] 0xE220 (BATTLEMAGE)
[20:20:38] [PASSED] 0xE221 (BATTLEMAGE)
[20:20:38] [PASSED] 0xE222 (BATTLEMAGE)
[20:20:38] [PASSED] 0xE223 (BATTLEMAGE)
[20:20:38] [PASSED] 0xB080 (PANTHERLAKE)
[20:20:38] [PASSED] 0xB081 (PANTHERLAKE)
[20:20:38] [PASSED] 0xB082 (PANTHERLAKE)
[20:20:38] [PASSED] 0xB083 (PANTHERLAKE)
[20:20:38] [PASSED] 0xB084 (PANTHERLAKE)
[20:20:38] [PASSED] 0xB085 (PANTHERLAKE)
[20:20:38] [PASSED] 0xB086 (PANTHERLAKE)
[20:20:38] [PASSED] 0xB087 (PANTHERLAKE)
[20:20:38] [PASSED] 0xB08F (PANTHERLAKE)
[20:20:38] [PASSED] 0xB090 (PANTHERLAKE)
[20:20:38] [PASSED] 0xB0A0 (PANTHERLAKE)
[20:20:38] [PASSED] 0xB0B0 (PANTHERLAKE)
[20:20:38] [PASSED] 0xFD80 (PANTHERLAKE)
[20:20:38] [PASSED] 0xFD81 (PANTHERLAKE)
[20:20:38] [PASSED] 0xD740 (NOVALAKE_S)
[20:20:38] [PASSED] 0xD741 (NOVALAKE_S)
[20:20:38] [PASSED] 0xD742 (NOVALAKE_S)
[20:20:38] [PASSED] 0xD743 (NOVALAKE_S)
[20:20:38] [PASSED] 0xD745 (NOVALAKE_S)
[20:20:38] [PASSED] 0xD74A (NOVALAKE_S)
[20:20:38] [PASSED] 0xD74B (NOVALAKE_S)
[20:20:38] [PASSED] 0x674C (CRESCENTISLAND)
[20:20:38] [PASSED] 0x674D (CRESCENTISLAND)
[20:20:38] [PASSED] 0x674E (CRESCENTISLAND)
[20:20:38] [PASSED] 0x674F (CRESCENTISLAND)
[20:20:38] [PASSED] 0x6750 (CRESCENTISLAND)
[20:20:38] [PASSED] 0xD750 (NOVALAKE_P)
[20:20:38] [PASSED] 0xD751 (NOVALAKE_P)
[20:20:38] [PASSED] 0xD752 (NOVALAKE_P)
[20:20:38] [PASSED] 0xD753 (NOVALAKE_P)
[20:20:38] [PASSED] 0xD754 (NOVALAKE_P)
[20:20:38] [PASSED] 0xD755 (NOVALAKE_P)
[20:20:38] [PASSED] 0xD756 (NOVALAKE_P)
[20:20:38] [PASSED] 0xD757 (NOVALAKE_P)
[20:20:38] [PASSED] 0xD75F (NOVALAKE_P)
[20:20:38] =============== [PASSED] check_platform_desc ===============
[20:20:38] ===================== [PASSED] xe_pci ======================
[20:20:38] ============= xe_rtp_tables_test (5 subtests) ==============
[20:20:38] ================== xe_rtp_table_gt_test ===================
[20:20:38] [PASSED] gt_was/14011060649
[20:20:38] [PASSED] gt_was/14011059788
[20:20:38] [PASSED] gt_was/14015795083
[20:20:38] [PASSED] gt_was/16021867713
[20:20:38] [PASSED] gt_was/14019449301
[20:20:38] [PASSED] gt_was/16028005424
[20:20:38] [PASSED] gt_was/14026578760
[20:20:38] [PASSED] gt_was/1409420604
[20:20:38] [PASSED] gt_was/1408615072
[20:20:38] [PASSED] gt_was/22010523718
[20:20:38] [PASSED] gt_was/14011006942
[20:20:38] [PASSED] gt_was/14014830051
[20:20:38] [PASSED] gt_was/18018781329
[20:20:38] [PASSED] gt_was/1509235366
[20:20:38] [PASSED] gt_was/18018781329
[20:20:38] [PASSED] gt_was/16016694945
[20:20:38] [PASSED] gt_was/14018575942
[20:20:38] [PASSED] gt_was/22016670082
[20:20:38] [PASSED] gt_was/22016670082
[20:20:38] [PASSED] gt_was/14017421178
[20:20:38] [PASSED] gt_was/16025250150
[20:20:38] [PASSED] gt_was/14021871409
[20:20:38] [PASSED] gt_was/16021865536
[20:20:38] [PASSED] gt_was/14021486841
[20:20:38] [PASSED] gt_was/14025160223
[20:20:38] [PASSED] gt_was/14026144927, 16029437861, 14026127056
[20:20:38] [PASSED] gt_was/14025635424
[20:20:38] [PASSED] gt_was/16028005424
[20:20:38] ============== [PASSED] xe_rtp_table_gt_test ===============
[20:20:38] ================== xe_rtp_table_gt_test ===================
[20:20:38] [PASSED] gt_tunings/Tuning: Blend Fill Caching Optimization Disable
[20:20:38] [PASSED] gt_tunings/Tuning: 32B Access Enable
[20:20:38] [PASSED] gt_tunings/Tuning: L3 cache
[20:20:38] [PASSED] gt_tunings/Tuning: L3 cache - media
[20:20:38] [PASSED] gt_tunings/Tuning: Compression Overfetch
[20:20:38] [PASSED] gt_tunings/Tuning: Compression Overfetch - media
[20:20:38] [PASSED] gt_tunings/Tuning: Enable compressible partial write overfetch in L3
[20:20:38] [PASSED] gt_tunings/Tuning: Enable compressible partial write overfetch in L3 - media
[20:20:38] [PASSED] gt_tunings/Tuning: L2 Overfetch Compressible Only
[20:20:38] [PASSED] gt_tunings/Tuning: L2 Overfetch Compressible Only - media
[20:20:38] [PASSED] gt_tunings/Tuning: Stateless compression control
[20:20:38] [PASSED] gt_tunings/Tuning: Stateless compression control - media
[20:20:38] [PASSED] gt_tunings/Tuning: L3 RW flush all Cache
[20:20:38] [PASSED] gt_tunings/Tuning: L3 RW flush all cache - media
[20:20:38] [PASSED] gt_tunings/Tuning: Set STLB Bank Hash Mode to 4KB
[20:20:38] ============== [PASSED] xe_rtp_table_gt_test ===============
[20:20:38] ================== xe_rtp_table_oob_test ==================
[20:20:38] [PASSED] oob_was/1607983814
[20:20:38] [PASSED] oob_was/16010904313
[20:20:38] [PASSED] oob_was/18022495364
[20:20:38] [PASSED] oob_was/22012773006
[20:20:38] [PASSED] oob_was/14014475959
[20:20:38] [PASSED] oob_was/22011391025
[20:20:38] [PASSED] oob_was/22012727170
[20:20:38] [PASSED] oob_was/22012727685
[20:20:38] [PASSED] oob_was/22016596838
[20:20:38] [PASSED] oob_was/18020744125
[20:20:38] [PASSED] oob_was/1409600907
[20:20:38] [PASSED] oob_was/22014953428
[20:20:38] [PASSED] oob_was/16017236439
[20:20:38] [PASSED] oob_was/14019821291
[20:20:38] [PASSED] oob_was/14015076503
[20:20:38] [PASSED] oob_was/14018913170
[20:20:38] [PASSED] oob_was/14018094691
[20:20:38] [PASSED] oob_was/18024947630
[20:20:38] [PASSED] oob_was/16022287689
[20:20:38] [PASSED] oob_was/13011645652
[20:20:38] [PASSED] oob_was/14022293748
[20:20:38] [PASSED] oob_was/22019794406
[20:20:38] [PASSED] oob_was/22019338487
[20:20:38] [PASSED] oob_was/16023588340
[20:20:38] [PASSED] oob_was/14019789679
[20:20:38] [PASSED] oob_was/14022866841
[20:20:38] [PASSED] oob_was/16021333562
[20:20:38] [PASSED] oob_was/14016712196
[20:20:38] [PASSED] oob_was/14015568240
[20:20:38] [PASSED] oob_was/18013179988
[20:20:38] [PASSED] oob_was/1508761755
[20:20:38] [PASSED] oob_was/16023105232
[20:20:38] [PASSED] oob_was/16026508708
[20:20:38] [PASSED] oob_was/14020001231
[20:20:38] [PASSED] oob_was/16023683509
[20:20:38] [PASSED] oob_was/14025515070
[20:20:38] [PASSED] oob_was/15015404425_disable
[20:20:38] [PASSED] oob_was/16026007364
[20:20:38] [PASSED] oob_was/14020316580
[20:20:38] [PASSED] oob_was/14025883347
[20:20:38] [PASSED] oob_was/16029380221
[20:20:38] [PASSED] oob_was/22022079272
[20:20:38] [PASSED] oob_was/16029897822
[20:20:38] [PASSED] oob_was/14027054324
[20:20:38] ============== [PASSED] xe_rtp_table_oob_test ==============
[20:20:38] ================ xe_rtp_table_dev_oob_test ================
[20:20:38] [PASSED] device_oob_was/22010954014
[20:20:38] [PASSED] device_oob_was/15015404425
[20:20:38] [PASSED] device_oob_was/22019338487_display
[20:20:38] [PASSED] device_oob_was/14022085890
[20:20:38] [PASSED] device_oob_was/14026539277
[20:20:38] [PASSED] device_oob_was/14026633728
[20:20:38] [PASSED] device_oob_was/14026746987
[20:20:38] [PASSED] device_oob_was/14026779378
[20:20:38] ============ [PASSED] xe_rtp_table_dev_oob_test ============
[20:20:38] ========== xe_rtp_table_missing_upper_bound_test ==========
[20:20:38] [PASSED] register_whitelist/WaAllowPMDepthAndInvocationCountAccessFromUMD, 1408556865
[20:20:38] [PASSED] register_whitelist/1508744258, 14012131227, 1808121037
[20:20:38] [PASSED] register_whitelist/1806527549
[20:20:38] [PASSED] register_whitelist/allow_read_ctx_timestamp
[20:20:38] [PASSED] register_whitelist/allow_read_queue_timestamp
[20:20:38] [PASSED] register_whitelist/16014440446
[20:20:38] [PASSED] register_whitelist/16017236439
[20:20:38] [PASSED] register_whitelist/16020183090
[20:20:38] [PASSED] register_whitelist/14024997852
[20:20:38] [PASSED] register_whitelist/14024997852
[20:20:38] ====== [PASSED] xe_rtp_table_missing_upper_bound_test ======
[20:20:38] =============== [PASSED] xe_rtp_tables_test ================
[20:20:38] =================== xe_rtp (3 subtests) ====================
[20:20:38] =================== xe_rtp_rules_tests ====================
[20:20:38] [PASSED] no
[20:20:38] [PASSED] yes
[20:20:38] [PASSED] no-and-no
[20:20:38] [PASSED] no-and-yes
[20:20:38] [PASSED] yes-and-no
[20:20:38] [PASSED] yes-and-yes
[20:20:38] [PASSED] no-or-no
[20:20:38] [PASSED] no-or-yes
[20:20:38] [PASSED] yes-or-no
[20:20:38] [PASSED] yes-or-yes
[20:20:38] [PASSED] no-yes-or-yes-no
[20:20:38] [PASSED] no-yes-or-yes-yes
[20:20:38] [PASSED] yes-yes-or-no-yes
[20:20:38] [PASSED] yes-yes-or-yes-yes
[20:20:38] [PASSED] no-no-or-yes-or-no
[20:20:38] [PASSED] or
[20:20:38] [PASSED] or-yes
[20:20:38] [PASSED] or-no
[20:20:38] [PASSED] yes-or
[20:20:38] [PASSED] no-or
[20:20:38] [PASSED] no-or-or-yes
[20:20:38] [PASSED] yes-or-or-no
[20:20:38] [PASSED] no-or-or-no
[20:20:38] [PASSED] missing-context-engine-class
[20:20:38] [PASSED] missing-context-engine-class-or-yes
[20:20:38] [PASSED] missing-context-engine-class-or-or-yes
[20:20:38] =============== [PASSED] xe_rtp_rules_tests ================
[20:20:38] =============== xe_rtp_process_to_sr_tests ================
[20:20:38] [PASSED] coalesce-same-reg
[20:20:38] [PASSED] coalesce-same-reg-literal-and-func
[20:20:38] [PASSED] no-match-no-add
[20:20:38] [PASSED] two-regs-two-entries
[20:20:38] [PASSED] clr-one-set-other
[20:20:38] [PASSED] set-field
[20:20:38] [PASSED] conflict-duplicate
[20:20:38] [PASSED] conflict-not-disjoint
[20:20:38] [PASSED] conflict-not-disjoint-literal-and-func
[20:20:38] [PASSED] conflict-reg-type
[20:20:38] [PASSED] bad-mcr-reg-forced-to-regular
[20:20:38] [PASSED] bad-regular-reg-forced-to-mcr
[20:20:38] =========== [PASSED] xe_rtp_process_to_sr_tests ============
[20:20:38] ================== xe_rtp_process_tests ===================
[20:20:38] [PASSED] active1
[20:20:38] [PASSED] active2
[20:20:38] [PASSED] active-inactive
[20:20:38] [PASSED] inactive-active
[20:20:38] [PASSED] inactive-active-inactive
[20:20:38] [PASSED] inactive-inactive-inactive
[20:20:38] ============== [PASSED] xe_rtp_process_tests ===============
[20:20:38] ===================== [PASSED] xe_rtp ======================
[20:20:38] ==================== xe_wa (1 subtest) =====================
[20:20:38] ======================== xe_wa_gt =========================
[20:20:38] [PASSED] TIGERLAKE B0
[20:20:38] [PASSED] DG1 A0
[20:20:38] [PASSED] DG1 B0
[20:20:38] [PASSED] ALDERLAKE_S A0
[20:20:38] [PASSED] ALDERLAKE_S B0
[20:20:38] [PASSED] ALDERLAKE_S C0
[20:20:38] [PASSED] ALDERLAKE_S D0
[20:20:38] [PASSED] ALDERLAKE_P A0
[20:20:38] [PASSED] ALDERLAKE_P B0
[20:20:38] [PASSED] ALDERLAKE_P C0
[20:20:38] [PASSED] ALDERLAKE_S RPLS D0
[20:20:38] [PASSED] ALDERLAKE_P RPLU E0
[20:20:38] [PASSED] DG2 G10 C0
[20:20:38] [PASSED] DG2 G11 B1
[20:20:38] [PASSED] DG2 G12 A1
[20:20:38] [PASSED] METEORLAKE 12.70(Xe_LPG) A0 13.00(Xe_LPM+) A0
[20:20:38] [PASSED] METEORLAKE 12.71(Xe_LPG) A0 13.00(Xe_LPM+) A0
[20:20:38] [PASSED] METEORLAKE 12.74(Xe_LPG+) A0 13.00(Xe_LPM+) A0
[20:20:38] [PASSED] LUNARLAKE 20.04(Xe2_LPG) A0 20.00(Xe2_LPM) A0
[20:20:38] [PASSED] LUNARLAKE 20.04(Xe2_LPG) B0 20.00(Xe2_LPM) A0
[20:20:38] [PASSED] BATTLEMAGE 20.01(Xe2_HPG) A0 13.01(Xe2_HPM) A1
[20:20:38] [PASSED] PANTHERLAKE 30.00(Xe3_LPG) A0 30.00(Xe3_LPM) A0
[20:20:38] ==================== [PASSED] xe_wa_gt =====================
[20:20:38] ====================== [PASSED] xe_wa ======================
[20:20:38] ============================================================
[20:20:38] Testing complete. Ran 789 tests: passed: 761, skipped: 28
[20:20:38] Elapsed time: 37.928s total, 4.357s configuring, 32.855s building, 0.695s running
+ /kernel/tools/testing/kunit/kunit.py run --kunitconfig /kernel/drivers/gpu/drm/tests/.kunitconfig
[20:20:38] Configuring KUnit Kernel ...
Regenerating .config ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
[20:20:40] Building KUnit Kernel ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
Building with:
$ make all compile_commands.json scripts_gdb ARCH=um O=.kunit --jobs=48
[20:21:05] Starting KUnit Kernel (1/1)...
[20:21:05] ============================================================
Running tests with:
$ .kunit/linux kunit.enable=1 mem=1G console=tty kunit_shutdown=halt
[20:21:05] ============ drm_test_pick_cmdline (2 subtests) ============
[20:21:05] [PASSED] drm_test_pick_cmdline_res_1920_1080_60
[20:21:05] =============== drm_test_pick_cmdline_named ===============
[20:21:05] [PASSED] NTSC
[20:21:05] [PASSED] NTSC-J
[20:21:05] [PASSED] PAL
[20:21:05] [PASSED] PAL-M
[20:21:05] =========== [PASSED] drm_test_pick_cmdline_named ===========
[20:21:05] ============== [PASSED] drm_test_pick_cmdline ==============
[20:21:05] == drm_test_atomic_get_connector_for_encoder (1 subtest) ===
[20:21:05] [PASSED] drm_test_drm_atomic_get_connector_for_encoder
[20:21:05] ==== [PASSED] drm_test_atomic_get_connector_for_encoder ====
[20:21:05] =========== drm_validate_clone_mode (2 subtests) ===========
[20:21:05] ============== drm_test_check_in_clone_mode ===============
[20:21:05] [PASSED] in_clone_mode
[20:21:05] [PASSED] not_in_clone_mode
[20:21:05] ========== [PASSED] drm_test_check_in_clone_mode ===========
[20:21:05] =============== drm_test_check_valid_clones ===============
[20:21:05] [PASSED] not_in_clone_mode
[20:21:05] [PASSED] valid_clone
[20:21:05] [PASSED] invalid_clone
[20:21:05] =========== [PASSED] drm_test_check_valid_clones ===========
[20:21:05] ============= [PASSED] drm_validate_clone_mode =============
[20:21:05] ============= drm_validate_modeset (1 subtest) =============
[20:21:05] [PASSED] drm_test_check_connector_changed_modeset
[20:21:05] ============== [PASSED] drm_validate_modeset ===============
[20:21:05] ====== drm_test_bridge_get_current_state (1 subtest) =======
[20:21:05] [PASSED] drm_test_drm_bridge_get_current_state_atomic
[20:21:05] ======== [PASSED] drm_test_bridge_get_current_state ========
[20:21:05] ====== drm_test_bridge_helper_reset_crtc (3 subtests) ======
[20:21:05] [PASSED] drm_test_drm_bridge_helper_reset_crtc_atomic
[20:21:05] [PASSED] drm_test_drm_bridge_helper_reset_crtc_atomic_disabled
[20:21:05] [PASSED] drm_test_drm_bridge_helper_hdmi_output_bus_fmts
[20:21:05] ======== [PASSED] drm_test_bridge_helper_reset_crtc ========
[20:21:05] ============== drm_bridge_alloc (2 subtests) ===============
[20:21:05] [PASSED] drm_test_drm_bridge_alloc_basic
[20:21:05] [PASSED] drm_test_drm_bridge_alloc_get_put
[20:21:05] ================ [PASSED] drm_bridge_alloc =================
[20:21:05] ============= drm_bridge_bus_fmt (5 subtests) ==============
[20:21:05] [PASSED] drm_test_bridge_rgb_yuv_rgb
[20:21:05] [PASSED] drm_test_bridge_must_convert_to_yuv444
[20:21:05] [PASSED] drm_test_bridge_hdmi_auto_rgb
[20:21:05] [PASSED] drm_test_bridge_auto_first
[20:21:05] [PASSED] drm_test_bridge_rgb_yuv_no_path
[20:21:05] =============== [PASSED] drm_bridge_bus_fmt ================
[20:21:05] ============= drm_cmdline_parser (40 subtests) =============
[20:21:05] [PASSED] drm_test_cmdline_force_d_only
[20:21:05] [PASSED] drm_test_cmdline_force_D_only_dvi
[20:21:05] [PASSED] drm_test_cmdline_force_D_only_hdmi
[20:21:05] [PASSED] drm_test_cmdline_force_D_only_not_digital
[20:21:05] [PASSED] drm_test_cmdline_force_e_only
[20:21:05] [PASSED] drm_test_cmdline_res
[20:21:05] [PASSED] drm_test_cmdline_res_vesa
[20:21:05] [PASSED] drm_test_cmdline_res_vesa_rblank
[20:21:05] [PASSED] drm_test_cmdline_res_rblank
[20:21:05] [PASSED] drm_test_cmdline_res_bpp
[20:21:05] [PASSED] drm_test_cmdline_res_refresh
[20:21:05] [PASSED] drm_test_cmdline_res_bpp_refresh
[20:21:05] [PASSED] drm_test_cmdline_res_bpp_refresh_interlaced
[20:21:05] [PASSED] drm_test_cmdline_res_bpp_refresh_margins
[20:21:05] [PASSED] drm_test_cmdline_res_bpp_refresh_force_off
[20:21:05] [PASSED] drm_test_cmdline_res_bpp_refresh_force_on
[20:21:05] [PASSED] drm_test_cmdline_res_bpp_refresh_force_on_analog
[20:21:05] [PASSED] drm_test_cmdline_res_bpp_refresh_force_on_digital
[20:21:05] [PASSED] drm_test_cmdline_res_bpp_refresh_interlaced_margins_force_on
[20:21:05] [PASSED] drm_test_cmdline_res_margins_force_on
[20:21:05] [PASSED] drm_test_cmdline_res_vesa_margins
[20:21:05] [PASSED] drm_test_cmdline_name
[20:21:05] [PASSED] drm_test_cmdline_name_bpp
[20:21:05] [PASSED] drm_test_cmdline_name_option
[20:21:05] [PASSED] drm_test_cmdline_name_bpp_option
[20:21:05] [PASSED] drm_test_cmdline_rotate_0
[20:21:05] [PASSED] drm_test_cmdline_rotate_90
[20:21:05] [PASSED] drm_test_cmdline_rotate_180
[20:21:05] [PASSED] drm_test_cmdline_rotate_270
[20:21:05] [PASSED] drm_test_cmdline_hmirror
[20:21:05] [PASSED] drm_test_cmdline_vmirror
[20:21:05] [PASSED] drm_test_cmdline_margin_options
[20:21:05] [PASSED] drm_test_cmdline_multiple_options
[20:21:05] [PASSED] drm_test_cmdline_bpp_extra_and_option
[20:21:05] [PASSED] drm_test_cmdline_extra_and_option
[20:21:05] [PASSED] drm_test_cmdline_freestanding_options
[20:21:05] [PASSED] drm_test_cmdline_freestanding_force_e_and_options
[20:21:05] [PASSED] drm_test_cmdline_panel_orientation
[20:21:05] ================ drm_test_cmdline_invalid =================
[20:21:05] [PASSED] margin_only
[20:21:05] [PASSED] interlace_only
[20:21:05] [PASSED] res_missing_x
[20:21:05] [PASSED] res_missing_y
[20:21:05] [PASSED] res_bad_y
[20:21:05] [PASSED] res_missing_y_bpp
[20:21:05] [PASSED] res_bad_bpp
[20:21:05] [PASSED] res_bad_refresh
[20:21:05] [PASSED] res_bpp_refresh_force_on_off
[20:21:05] [PASSED] res_invalid_mode
[20:21:05] [PASSED] res_bpp_wrong_place_mode
[20:21:05] [PASSED] name_bpp_refresh
[20:21:05] [PASSED] name_refresh
[20:21:05] [PASSED] name_refresh_wrong_mode
[20:21:05] [PASSED] name_refresh_invalid_mode
[20:21:05] [PASSED] rotate_multiple
[20:21:05] [PASSED] rotate_invalid_val
[20:21:05] [PASSED] rotate_truncated
[20:21:05] [PASSED] invalid_option
[20:21:05] [PASSED] invalid_tv_option
[20:21:05] [PASSED] truncated_tv_option
[20:21:05] ============ [PASSED] drm_test_cmdline_invalid =============
[20:21:05] =============== drm_test_cmdline_tv_options ===============
[20:21:05] [PASSED] NTSC
[20:21:05] [PASSED] NTSC_443
[20:21:05] [PASSED] NTSC_J
[20:21:05] [PASSED] PAL
[20:21:05] [PASSED] PAL_M
[20:21:05] [PASSED] PAL_N
[20:21:05] [PASSED] SECAM
[20:21:05] [PASSED] MONO_525
[20:21:05] [PASSED] MONO_625
[20:21:05] =========== [PASSED] drm_test_cmdline_tv_options ===========
[20:21:05] =============== [PASSED] drm_cmdline_parser ================
[20:21:05] ========== drmm_connector_hdmi_init (20 subtests) ==========
[20:21:05] [PASSED] drm_test_connector_hdmi_init_valid
[20:21:05] [PASSED] drm_test_connector_hdmi_init_bpc_8
[20:21:05] [PASSED] drm_test_connector_hdmi_init_bpc_10
[20:21:05] [PASSED] drm_test_connector_hdmi_init_bpc_12
[20:21:05] [PASSED] drm_test_connector_hdmi_init_bpc_invalid
[20:21:05] [PASSED] drm_test_connector_hdmi_init_bpc_null
[20:21:05] [PASSED] drm_test_connector_hdmi_init_formats_empty
[20:21:05] [PASSED] drm_test_connector_hdmi_init_formats_no_rgb
[20:21:05] === drm_test_connector_hdmi_init_formats_yuv420_allowed ===
[20:21:05] [PASSED] supported_formats=0x9 yuv420_allowed=1
[20:21:05] [PASSED] supported_formats=0x9 yuv420_allowed=0
[20:21:05] [PASSED] supported_formats=0x5 yuv420_allowed=1
[20:21:05] [PASSED] supported_formats=0x5 yuv420_allowed=0
[20:21:05] === [PASSED] drm_test_connector_hdmi_init_formats_yuv420_allowed ===
[20:21:05] [PASSED] drm_test_connector_hdmi_init_null_ddc
[20:21:05] [PASSED] drm_test_connector_hdmi_init_null_product
[20:21:05] [PASSED] drm_test_connector_hdmi_init_null_vendor
[20:21:05] [PASSED] drm_test_connector_hdmi_init_product_length_exact
[20:21:05] [PASSED] drm_test_connector_hdmi_init_product_length_too_long
[20:21:05] [PASSED] drm_test_connector_hdmi_init_product_valid
[20:21:05] [PASSED] drm_test_connector_hdmi_init_vendor_length_exact
[20:21:05] [PASSED] drm_test_connector_hdmi_init_vendor_length_too_long
[20:21:05] [PASSED] drm_test_connector_hdmi_init_vendor_valid
[20:21:05] ========= drm_test_connector_hdmi_init_type_valid =========
[20:21:05] [PASSED] HDMI-A
[20:21:05] [PASSED] HDMI-B
[20:21:05] ===== [PASSED] drm_test_connector_hdmi_init_type_valid =====
[20:21:05] ======== drm_test_connector_hdmi_init_type_invalid ========
[20:21:05] [PASSED] Unknown
[20:21:05] [PASSED] VGA
[20:21:05] [PASSED] DVI-I
[20:21:05] [PASSED] DVI-D
[20:21:05] [PASSED] DVI-A
[20:21:05] [PASSED] Composite
[20:21:05] [PASSED] SVIDEO
[20:21:05] [PASSED] LVDS
[20:21:05] [PASSED] Component
[20:21:05] [PASSED] DIN
[20:21:05] [PASSED] DP
[20:21:05] [PASSED] TV
[20:21:05] [PASSED] eDP
[20:21:05] [PASSED] Virtual
[20:21:05] [PASSED] DSI
[20:21:05] [PASSED] DPI
[20:21:05] [PASSED] Writeback
[20:21:05] [PASSED] SPI
[20:21:05] [PASSED] USB
[20:21:05] ==== [PASSED] drm_test_connector_hdmi_init_type_invalid ====
[20:21:05] ============ [PASSED] drmm_connector_hdmi_init =============
[20:21:05] ============= drmm_connector_init (3 subtests) =============
[20:21:05] [PASSED] drm_test_drmm_connector_init
[20:21:05] [PASSED] drm_test_drmm_connector_init_null_ddc
[20:21:05] ========= drm_test_drmm_connector_init_type_valid =========
[20:21:05] [PASSED] Unknown
[20:21:05] [PASSED] VGA
[20:21:05] [PASSED] DVI-I
[20:21:05] [PASSED] DVI-D
[20:21:05] [PASSED] DVI-A
[20:21:05] [PASSED] Composite
[20:21:05] [PASSED] SVIDEO
[20:21:05] [PASSED] LVDS
[20:21:05] [PASSED] Component
[20:21:05] [PASSED] DIN
[20:21:05] [PASSED] DP
[20:21:05] [PASSED] HDMI-A
[20:21:05] [PASSED] HDMI-B
[20:21:05] [PASSED] TV
[20:21:05] [PASSED] eDP
[20:21:05] [PASSED] Virtual
[20:21:05] [PASSED] DSI
[20:21:05] [PASSED] DPI
[20:21:05] [PASSED] Writeback
[20:21:05] [PASSED] SPI
[20:21:05] [PASSED] USB
[20:21:05] ===== [PASSED] drm_test_drmm_connector_init_type_valid =====
[20:21:05] =============== [PASSED] drmm_connector_init ===============
[20:21:05] ========= drm_connector_dynamic_init (6 subtests) ==========
[20:21:05] [PASSED] drm_test_drm_connector_dynamic_init
[20:21:05] [PASSED] drm_test_drm_connector_dynamic_init_null_ddc
[20:21:05] [PASSED] drm_test_drm_connector_dynamic_init_not_added
[20:21:05] [PASSED] drm_test_drm_connector_dynamic_init_properties
[20:21:05] ===== drm_test_drm_connector_dynamic_init_type_valid ======
[20:21:05] [PASSED] Unknown
[20:21:05] [PASSED] VGA
[20:21:05] [PASSED] DVI-I
[20:21:05] [PASSED] DVI-D
[20:21:05] [PASSED] DVI-A
[20:21:05] [PASSED] Composite
[20:21:05] [PASSED] SVIDEO
[20:21:05] [PASSED] LVDS
[20:21:05] [PASSED] Component
[20:21:05] [PASSED] DIN
[20:21:05] [PASSED] DP
[20:21:05] [PASSED] HDMI-A
[20:21:05] [PASSED] HDMI-B
[20:21:05] [PASSED] TV
[20:21:05] [PASSED] eDP
[20:21:05] [PASSED] Virtual
[20:21:05] [PASSED] DSI
[20:21:05] [PASSED] DPI
[20:21:05] [PASSED] Writeback
[20:21:05] [PASSED] SPI
[20:21:05] [PASSED] USB
[20:21:05] = [PASSED] drm_test_drm_connector_dynamic_init_type_valid ==
[20:21:05] ======== drm_test_drm_connector_dynamic_init_name =========
[20:21:05] [PASSED] Unknown
[20:21:05] [PASSED] VGA
[20:21:05] [PASSED] DVI-I
[20:21:05] [PASSED] DVI-D
[20:21:05] [PASSED] DVI-A
[20:21:05] [PASSED] Composite
[20:21:05] [PASSED] SVIDEO
[20:21:05] [PASSED] LVDS
[20:21:05] [PASSED] Component
[20:21:05] [PASSED] DIN
[20:21:05] [PASSED] DP
[20:21:05] [PASSED] HDMI-A
[20:21:05] [PASSED] HDMI-B
[20:21:05] [PASSED] TV
[20:21:05] [PASSED] eDP
[20:21:05] [PASSED] Virtual
[20:21:05] [PASSED] DSI
[20:21:05] [PASSED] DPI
[20:21:05] [PASSED] Writeback
[20:21:05] [PASSED] SPI
[20:21:05] [PASSED] USB
[20:21:05] ==== [PASSED] drm_test_drm_connector_dynamic_init_name =====
[20:21:05] =========== [PASSED] drm_connector_dynamic_init ============
[20:21:05] ==== drm_connector_dynamic_register_early (4 subtests) =====
[20:21:05] [PASSED] drm_test_drm_connector_dynamic_register_early_on_list
[20:21:05] [PASSED] drm_test_drm_connector_dynamic_register_early_defer
[20:21:05] [PASSED] drm_test_drm_connector_dynamic_register_early_no_init
[20:21:05] [PASSED] drm_test_drm_connector_dynamic_register_early_no_mode_object
[20:21:05] ====== [PASSED] drm_connector_dynamic_register_early =======
[20:21:05] ======= drm_connector_dynamic_register (7 subtests) ========
[20:21:05] [PASSED] drm_test_drm_connector_dynamic_register_on_list
[20:21:05] [PASSED] drm_test_drm_connector_dynamic_register_no_defer
[20:21:05] [PASSED] drm_test_drm_connector_dynamic_register_no_init
[20:21:05] [PASSED] drm_test_drm_connector_dynamic_register_mode_object
[20:21:05] [PASSED] drm_test_drm_connector_dynamic_register_sysfs
[20:21:05] [PASSED] drm_test_drm_connector_dynamic_register_sysfs_name
[20:21:05] [PASSED] drm_test_drm_connector_dynamic_register_debugfs
[20:21:05] ========= [PASSED] drm_connector_dynamic_register ==========
[20:21:05] = drm_connector_attach_broadcast_rgb_property (2 subtests) =
[20:21:05] [PASSED] drm_test_drm_connector_attach_broadcast_rgb_property
[20:21:05] [PASSED] drm_test_drm_connector_attach_broadcast_rgb_property_hdmi_connector
[20:21:05] === [PASSED] drm_connector_attach_broadcast_rgb_property ===
[20:21:05] ========== drm_get_tv_mode_from_name (2 subtests) ==========
[20:21:05] ========== drm_test_get_tv_mode_from_name_valid ===========
[20:21:05] [PASSED] NTSC
[20:21:05] [PASSED] NTSC-443
[20:21:05] [PASSED] NTSC-J
[20:21:05] [PASSED] PAL
[20:21:05] [PASSED] PAL-M
[20:21:05] [PASSED] PAL-N
[20:21:05] [PASSED] SECAM
[20:21:05] [PASSED] Mono
[20:21:05] ====== [PASSED] drm_test_get_tv_mode_from_name_valid =======
[20:21:05] [PASSED] drm_test_get_tv_mode_from_name_truncated
[20:21:05] ============ [PASSED] drm_get_tv_mode_from_name ============
[20:21:05] = drm_test_connector_hdmi_compute_mode_clock (12 subtests) =
[20:21:05] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb
[20:21:05] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_10bpc
[20:21:05] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_10bpc_vic_1
[20:21:05] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_12bpc
[20:21:05] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_12bpc_vic_1
[20:21:05] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_double
[20:21:05] = drm_test_connector_hdmi_compute_mode_clock_yuv420_valid =
[20:21:05] [PASSED] VIC 96
[20:21:05] [PASSED] VIC 97
[20:21:05] [PASSED] VIC 101
[20:21:05] [PASSED] VIC 102
[20:21:05] [PASSED] VIC 106
[20:21:05] [PASSED] VIC 107
[20:21:05] === [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv420_valid ===
[20:21:05] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv420_10_bpc
[20:21:05] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv420_12_bpc
[20:21:05] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv422_8_bpc
[20:21:05] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv422_10_bpc
[20:21:05] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv422_12_bpc
[20:21:05] === [PASSED] drm_test_connector_hdmi_compute_mode_clock ====
[20:21:05] == drm_hdmi_connector_get_broadcast_rgb_name (2 subtests) ==
[20:21:05] === drm_test_drm_hdmi_connector_get_broadcast_rgb_name ====
[20:21:05] [PASSED] Automatic
[20:21:05] [PASSED] Full
[20:21:05] [PASSED] Limited 16:235
[20:21:05] === [PASSED] drm_test_drm_hdmi_connector_get_broadcast_rgb_name ===
[20:21:05] [PASSED] drm_test_drm_hdmi_connector_get_broadcast_rgb_name_invalid
[20:21:05] ==== [PASSED] drm_hdmi_connector_get_broadcast_rgb_name ====
[20:21:05] == drm_hdmi_connector_get_output_format_name (2 subtests) ==
[20:21:05] === drm_test_drm_hdmi_connector_get_output_format_name ====
[20:21:05] [PASSED] RGB
[20:21:05] [PASSED] YUV 4:2:0
[20:21:05] [PASSED] YUV 4:2:2
[20:21:05] [PASSED] YUV 4:4:4
[20:21:05] === [PASSED] drm_test_drm_hdmi_connector_get_output_format_name ===
[20:21:05] [PASSED] drm_test_drm_hdmi_connector_get_output_format_name_invalid
[20:21:05] ==== [PASSED] drm_hdmi_connector_get_output_format_name ====
[20:21:05] ============= drm_damage_helper (21 subtests) ==============
[20:21:05] [PASSED] drm_test_damage_iter_no_damage
[20:21:05] [PASSED] drm_test_damage_iter_no_damage_fractional_src
[20:21:05] [PASSED] drm_test_damage_iter_no_damage_src_moved
[20:21:05] [PASSED] drm_test_damage_iter_no_damage_fractional_src_moved
[20:21:05] [PASSED] drm_test_damage_iter_no_damage_not_visible
[20:21:05] [PASSED] drm_test_damage_iter_no_damage_no_crtc
[20:21:05] [PASSED] drm_test_damage_iter_no_damage_no_fb
[20:21:05] [PASSED] drm_test_damage_iter_simple_damage
[20:21:05] [PASSED] drm_test_damage_iter_single_damage
[20:21:05] [PASSED] drm_test_damage_iter_single_damage_intersect_src
[20:21:05] [PASSED] drm_test_damage_iter_single_damage_outside_src
[20:21:05] [PASSED] drm_test_damage_iter_single_damage_fractional_src
[20:21:05] [PASSED] drm_test_damage_iter_single_damage_intersect_fractional_src
[20:21:05] [PASSED] drm_test_damage_iter_single_damage_outside_fractional_src
[20:21:05] [PASSED] drm_test_damage_iter_single_damage_src_moved
[20:21:05] [PASSED] drm_test_damage_iter_single_damage_fractional_src_moved
[20:21:05] [PASSED] drm_test_damage_iter_damage
[20:21:05] [PASSED] drm_test_damage_iter_damage_one_intersect
[20:21:05] [PASSED] drm_test_damage_iter_damage_one_outside
[20:21:05] [PASSED] drm_test_damage_iter_damage_src_moved
[20:21:05] [PASSED] drm_test_damage_iter_damage_not_visible
[20:21:05] ================ [PASSED] drm_damage_helper ================
[20:21:05] ============== drm_dp_mst_helper (3 subtests) ==============
[20:21:05] ============== drm_test_dp_mst_calc_pbn_mode ==============
[20:21:05] [PASSED] Clock 154000 BPP 30 DSC disabled
[20:21:05] [PASSED] Clock 234000 BPP 30 DSC disabled
[20:21:05] [PASSED] Clock 297000 BPP 24 DSC disabled
[20:21:05] [PASSED] Clock 332880 BPP 24 DSC enabled
[20:21:05] [PASSED] Clock 324540 BPP 24 DSC enabled
[20:21:05] ========== [PASSED] drm_test_dp_mst_calc_pbn_mode ==========
[20:21:05] ============== drm_test_dp_mst_calc_pbn_div ===============
[20:21:05] [PASSED] Link rate 2000000 lane count 4
[20:21:05] [PASSED] Link rate 2000000 lane count 2
[20:21:05] [PASSED] Link rate 2000000 lane count 1
[20:21:05] [PASSED] Link rate 1350000 lane count 4
[20:21:05] [PASSED] Link rate 1350000 lane count 2
[20:21:05] [PASSED] Link rate 1350000 lane count 1
[20:21:05] [PASSED] Link rate 1000000 lane count 4
[20:21:05] [PASSED] Link rate 1000000 lane count 2
[20:21:05] [PASSED] Link rate 1000000 lane count 1
[20:21:05] [PASSED] Link rate 810000 lane count 4
[20:21:05] [PASSED] Link rate 810000 lane count 2
[20:21:05] [PASSED] Link rate 810000 lane count 1
[20:21:05] [PASSED] Link rate 540000 lane count 4
[20:21:05] [PASSED] Link rate 540000 lane count 2
[20:21:05] [PASSED] Link rate 540000 lane count 1
[20:21:05] [PASSED] Link rate 270000 lane count 4
[20:21:05] [PASSED] Link rate 270000 lane count 2
[20:21:05] [PASSED] Link rate 270000 lane count 1
[20:21:05] [PASSED] Link rate 162000 lane count 4
[20:21:05] [PASSED] Link rate 162000 lane count 2
[20:21:05] [PASSED] Link rate 162000 lane count 1
[20:21:05] ========== [PASSED] drm_test_dp_mst_calc_pbn_div ===========
[20:21:05] ========= drm_test_dp_mst_sideband_msg_req_decode =========
[20:21:05] [PASSED] DP_ENUM_PATH_RESOURCES with port number
[20:21:05] [PASSED] DP_POWER_UP_PHY with port number
[20:21:05] [PASSED] DP_POWER_DOWN_PHY with port number
[20:21:05] [PASSED] DP_ALLOCATE_PAYLOAD with SDP stream sinks
[20:21:05] [PASSED] DP_ALLOCATE_PAYLOAD with port number
[20:21:05] [PASSED] DP_ALLOCATE_PAYLOAD with VCPI
[20:21:05] [PASSED] DP_ALLOCATE_PAYLOAD with PBN
[20:21:05] [PASSED] DP_QUERY_PAYLOAD with port number
[20:21:05] [PASSED] DP_QUERY_PAYLOAD with VCPI
[20:21:05] [PASSED] DP_REMOTE_DPCD_READ with port number
[20:21:05] [PASSED] DP_REMOTE_DPCD_READ with DPCD address
[20:21:05] [PASSED] DP_REMOTE_DPCD_READ with max number of bytes
[20:21:05] [PASSED] DP_REMOTE_DPCD_WRITE with port number
[20:21:05] [PASSED] DP_REMOTE_DPCD_WRITE with DPCD address
[20:21:05] [PASSED] DP_REMOTE_DPCD_WRITE with data array
[20:21:05] [PASSED] DP_REMOTE_I2C_READ with port number
[20:21:05] [PASSED] DP_REMOTE_I2C_READ with I2C device ID
[20:21:05] [PASSED] DP_REMOTE_I2C_READ with transactions array
[20:21:05] [PASSED] DP_REMOTE_I2C_WRITE with port number
[20:21:05] [PASSED] DP_REMOTE_I2C_WRITE with I2C device ID
[20:21:05] [PASSED] DP_REMOTE_I2C_WRITE with data array
[20:21:05] [PASSED] DP_QUERY_STREAM_ENC_STATUS with stream ID
[20:21:05] [PASSED] DP_QUERY_STREAM_ENC_STATUS with client ID
[20:21:05] [PASSED] DP_QUERY_STREAM_ENC_STATUS with stream event
[20:21:05] [PASSED] DP_QUERY_STREAM_ENC_STATUS with valid stream event
[20:21:05] [PASSED] DP_QUERY_STREAM_ENC_STATUS with stream behavior
[20:21:05] [PASSED] DP_QUERY_STREAM_ENC_STATUS with a valid stream behavior
[20:21:05] ===== [PASSED] drm_test_dp_mst_sideband_msg_req_decode =====
[20:21:05] ================ [PASSED] drm_dp_mst_helper ================
[20:21:05] ================== drm_exec (7 subtests) ===================
[20:21:05] [PASSED] sanitycheck
[20:21:05] [PASSED] test_lock
[20:21:05] [PASSED] test_lock_unlock
[20:21:05] [PASSED] test_duplicates
[20:21:05] [PASSED] test_prepare
[20:21:05] [PASSED] test_prepare_array
[20:21:05] [PASSED] test_multiple_loops
[20:21:05] ==================== [PASSED] drm_exec =====================
[20:21:05] =========== drm_format_helper_test (17 subtests) ===========
[20:21:05] ============== drm_test_fb_xrgb8888_to_gray8 ==============
[20:21:05] [PASSED] single_pixel_source_buffer
[20:21:05] [PASSED] single_pixel_clip_rectangle
[20:21:05] [PASSED] well_known_colors
[20:21:05] [PASSED] destination_pitch
[20:21:05] ========== [PASSED] drm_test_fb_xrgb8888_to_gray8 ==========
[20:21:05] ============= drm_test_fb_xrgb8888_to_rgb332 ==============
[20:21:05] [PASSED] single_pixel_source_buffer
[20:21:05] [PASSED] single_pixel_clip_rectangle
[20:21:05] [PASSED] well_known_colors
[20:21:05] [PASSED] destination_pitch
[20:21:05] ========= [PASSED] drm_test_fb_xrgb8888_to_rgb332 ==========
[20:21:05] ============= drm_test_fb_xrgb8888_to_rgb565 ==============
[20:21:05] [PASSED] single_pixel_source_buffer
[20:21:05] [PASSED] single_pixel_clip_rectangle
[20:21:05] [PASSED] well_known_colors
[20:21:05] [PASSED] destination_pitch
[20:21:05] ========= [PASSED] drm_test_fb_xrgb8888_to_rgb565 ==========
[20:21:05] ============ drm_test_fb_xrgb8888_to_xrgb1555 =============
[20:21:05] [PASSED] single_pixel_source_buffer
[20:21:05] [PASSED] single_pixel_clip_rectangle
[20:21:05] [PASSED] well_known_colors
[20:21:05] [PASSED] destination_pitch
[20:21:05] ======== [PASSED] drm_test_fb_xrgb8888_to_xrgb1555 =========
[20:21:05] ============ drm_test_fb_xrgb8888_to_argb1555 =============
[20:21:05] [PASSED] single_pixel_source_buffer
[20:21:05] [PASSED] single_pixel_clip_rectangle
[20:21:05] [PASSED] well_known_colors
[20:21:05] [PASSED] destination_pitch
[20:21:05] ======== [PASSED] drm_test_fb_xrgb8888_to_argb1555 =========
[20:21:05] ============ drm_test_fb_xrgb8888_to_rgba5551 =============
[20:21:05] [PASSED] single_pixel_source_buffer
[20:21:05] [PASSED] single_pixel_clip_rectangle
[20:21:05] [PASSED] well_known_colors
[20:21:05] [PASSED] destination_pitch
[20:21:05] ======== [PASSED] drm_test_fb_xrgb8888_to_rgba5551 =========
[20:21:05] ============= drm_test_fb_xrgb8888_to_rgb888 ==============
[20:21:05] [PASSED] single_pixel_source_buffer
[20:21:05] [PASSED] single_pixel_clip_rectangle
[20:21:05] [PASSED] well_known_colors
[20:21:05] [PASSED] destination_pitch
[20:21:05] ========= [PASSED] drm_test_fb_xrgb8888_to_rgb888 ==========
[20:21:05] ============= drm_test_fb_xrgb8888_to_bgr888 ==============
[20:21:05] [PASSED] single_pixel_source_buffer
[20:21:05] [PASSED] single_pixel_clip_rectangle
[20:21:05] [PASSED] well_known_colors
[20:21:05] [PASSED] destination_pitch
[20:21:05] ========= [PASSED] drm_test_fb_xrgb8888_to_bgr888 ==========
[20:21:05] ============ drm_test_fb_xrgb8888_to_argb8888 =============
[20:21:05] [PASSED] single_pixel_source_buffer
[20:21:05] [PASSED] single_pixel_clip_rectangle
[20:21:05] [PASSED] well_known_colors
[20:21:05] [PASSED] destination_pitch
[20:21:05] ======== [PASSED] drm_test_fb_xrgb8888_to_argb8888 =========
[20:21:05] =========== drm_test_fb_xrgb8888_to_xrgb2101010 ===========
[20:21:05] [PASSED] single_pixel_source_buffer
[20:21:05] [PASSED] single_pixel_clip_rectangle
[20:21:05] [PASSED] well_known_colors
[20:21:05] [PASSED] destination_pitch
[20:21:05] ======= [PASSED] drm_test_fb_xrgb8888_to_xrgb2101010 =======
[20:21:05] =========== drm_test_fb_xrgb8888_to_argb2101010 ===========
[20:21:05] [PASSED] single_pixel_source_buffer
[20:21:05] [PASSED] single_pixel_clip_rectangle
[20:21:05] [PASSED] well_known_colors
[20:21:05] [PASSED] destination_pitch
[20:21:05] ======= [PASSED] drm_test_fb_xrgb8888_to_argb2101010 =======
[20:21:05] ============== drm_test_fb_xrgb8888_to_mono ===============
[20:21:05] [PASSED] single_pixel_source_buffer
[20:21:05] [PASSED] single_pixel_clip_rectangle
[20:21:05] [PASSED] well_known_colors
[20:21:05] [PASSED] destination_pitch
[20:21:05] ========== [PASSED] drm_test_fb_xrgb8888_to_mono ===========
[20:21:05] ==================== drm_test_fb_swab =====================
[20:21:05] [PASSED] single_pixel_source_buffer
[20:21:05] [PASSED] single_pixel_clip_rectangle
[20:21:05] [PASSED] well_known_colors
[20:21:05] [PASSED] destination_pitch
[20:21:05] ================ [PASSED] drm_test_fb_swab =================
[20:21:05] ============ drm_test_fb_xrgb8888_to_xbgr8888 =============
[20:21:05] [PASSED] single_pixel_source_buffer
[20:21:05] [PASSED] single_pixel_clip_rectangle
[20:21:05] [PASSED] well_known_colors
[20:21:05] [PASSED] destination_pitch
[20:21:05] ======== [PASSED] drm_test_fb_xrgb8888_to_xbgr8888 =========
[20:21:05] ============ drm_test_fb_xrgb8888_to_abgr8888 =============
[20:21:05] [PASSED] single_pixel_source_buffer
[20:21:05] [PASSED] single_pixel_clip_rectangle
[20:21:05] [PASSED] well_known_colors
[20:21:05] [PASSED] destination_pitch
[20:21:05] ======== [PASSED] drm_test_fb_xrgb8888_to_abgr8888 =========
[20:21:05] ================= drm_test_fb_clip_offset =================
[20:21:05] [PASSED] pass through
[20:21:05] [PASSED] horizontal offset
[20:21:05] [PASSED] vertical offset
[20:21:05] [PASSED] horizontal and vertical offset
[20:21:05] [PASSED] horizontal offset (custom pitch)
[20:21:05] [PASSED] vertical offset (custom pitch)
[20:21:05] [PASSED] horizontal and vertical offset (custom pitch)
[20:21:05] ============= [PASSED] drm_test_fb_clip_offset =============
[20:21:05] =================== drm_test_fb_memcpy ====================
[20:21:05] [PASSED] single_pixel_source_buffer: XR24 little-endian (0x34325258)
[20:21:05] [PASSED] single_pixel_source_buffer: XRA8 little-endian (0x38415258)
[20:21:05] [PASSED] single_pixel_source_buffer: YU24 little-endian (0x34325559)
[20:21:05] [PASSED] single_pixel_clip_rectangle: XB24 little-endian (0x34324258)
[20:21:05] [PASSED] single_pixel_clip_rectangle: XRA8 little-endian (0x38415258)
[20:21:05] [PASSED] single_pixel_clip_rectangle: YU24 little-endian (0x34325559)
[20:21:05] [PASSED] well_known_colors: XB24 little-endian (0x34324258)
[20:21:05] [PASSED] well_known_colors: XRA8 little-endian (0x38415258)
[20:21:05] [PASSED] well_known_colors: YU24 little-endian (0x34325559)
[20:21:05] [PASSED] destination_pitch: XB24 little-endian (0x34324258)
[20:21:05] [PASSED] destination_pitch: XRA8 little-endian (0x38415258)
[20:21:05] [PASSED] destination_pitch: YU24 little-endian (0x34325559)
[20:21:05] =============== [PASSED] drm_test_fb_memcpy ================
[20:21:05] ============= [PASSED] drm_format_helper_test ==============
[20:21:05] ================= drm_format (18 subtests) =================
[20:21:05] [PASSED] drm_test_format_block_width_invalid
[20:21:05] [PASSED] drm_test_format_block_width_one_plane
[20:21:05] [PASSED] drm_test_format_block_width_two_plane
[20:21:05] [PASSED] drm_test_format_block_width_three_plane
[20:21:05] [PASSED] drm_test_format_block_width_tiled
[20:21:05] [PASSED] drm_test_format_block_height_invalid
[20:21:05] [PASSED] drm_test_format_block_height_one_plane
[20:21:05] [PASSED] drm_test_format_block_height_two_plane
[20:21:05] [PASSED] drm_test_format_block_height_three_plane
[20:21:05] [PASSED] drm_test_format_block_height_tiled
[20:21:05] [PASSED] drm_test_format_min_pitch_invalid
[20:21:05] [PASSED] drm_test_format_min_pitch_one_plane_8bpp
[20:21:05] [PASSED] drm_test_format_min_pitch_one_plane_16bpp
[20:21:05] [PASSED] drm_test_format_min_pitch_one_plane_24bpp
[20:21:05] [PASSED] drm_test_format_min_pitch_one_plane_32bpp
[20:21:05] [PASSED] drm_test_format_min_pitch_two_plane
[20:21:05] [PASSED] drm_test_format_min_pitch_three_plane_8bpp
[20:21:05] [PASSED] drm_test_format_min_pitch_tiled
[20:21:05] =================== [PASSED] drm_format ====================
[20:21:05] ============== drm_framebuffer (10 subtests) ===============
[20:21:05] ========== drm_test_framebuffer_check_src_coords ==========
[20:21:05] [PASSED] Success: source fits into fb
[20:21:05] [PASSED] Fail: overflowing fb with x-axis coordinate
[20:21:05] [PASSED] Fail: overflowing fb with y-axis coordinate
[20:21:05] [PASSED] Fail: overflowing fb with source width
[20:21:05] [PASSED] Fail: overflowing fb with source height
[20:21:05] ====== [PASSED] drm_test_framebuffer_check_src_coords ======
[20:21:05] [PASSED] drm_test_framebuffer_cleanup
[20:21:05] =============== drm_test_framebuffer_create ===============
[20:21:05] [PASSED] ABGR8888 normal sizes
[20:21:05] [PASSED] ABGR8888 max sizes
[20:21:05] [PASSED] ABGR8888 pitch greater than min required
[20:21:05] [PASSED] ABGR8888 pitch less than min required
[20:21:05] [PASSED] ABGR8888 Invalid width
[20:21:05] [PASSED] ABGR8888 Invalid buffer handle
[20:21:05] [PASSED] No pixel format
[20:21:05] [PASSED] ABGR8888 Width 0
[20:21:05] [PASSED] ABGR8888 Height 0
[20:21:05] [PASSED] ABGR8888 Out of bound height * pitch combination
[20:21:05] [PASSED] ABGR8888 Large buffer offset
[20:21:05] [PASSED] ABGR8888 Buffer offset for inexistent plane
[20:21:05] [PASSED] ABGR8888 Invalid flag
[20:21:05] [PASSED] ABGR8888 Set DRM_MODE_FB_MODIFIERS without modifiers
[20:21:05] [PASSED] ABGR8888 Valid buffer modifier
[20:21:05] [PASSED] ABGR8888 Invalid buffer modifier(DRM_FORMAT_MOD_SAMSUNG_64_32_TILE)
[20:21:05] [PASSED] ABGR8888 Extra pitches without DRM_MODE_FB_MODIFIERS
[20:21:05] [PASSED] ABGR8888 Extra pitches with DRM_MODE_FB_MODIFIERS
[20:21:05] [PASSED] NV12 Normal sizes
[20:21:05] [PASSED] NV12 Max sizes
[20:21:05] [PASSED] NV12 Invalid pitch
[20:21:05] [PASSED] NV12 Invalid modifier/missing DRM_MODE_FB_MODIFIERS flag
[20:21:05] [PASSED] NV12 different modifier per-plane
[20:21:05] [PASSED] NV12 with DRM_FORMAT_MOD_SAMSUNG_64_32_TILE
[20:21:05] [PASSED] NV12 Valid modifiers without DRM_MODE_FB_MODIFIERS
[20:21:05] [PASSED] NV12 Modifier for inexistent plane
[20:21:05] [PASSED] NV12 Handle for inexistent plane
[20:21:05] [PASSED] NV12 Handle for inexistent plane without DRM_MODE_FB_MODIFIERS
[20:21:05] [PASSED] YVU420 DRM_MODE_FB_MODIFIERS set without modifier
[20:21:05] [PASSED] YVU420 Normal sizes
[20:21:05] [PASSED] YVU420 Max sizes
[20:21:05] [PASSED] YVU420 Invalid pitch
[20:21:05] [PASSED] YVU420 Different pitches
[20:21:05] [PASSED] YVU420 Different buffer offsets/pitches
[20:21:05] [PASSED] YVU420 Modifier set just for plane 0, without DRM_MODE_FB_MODIFIERS
[20:21:05] [PASSED] YVU420 Modifier set just for planes 0, 1, without DRM_MODE_FB_MODIFIERS
[20:21:05] [PASSED] YVU420 Modifier set just for plane 0, 1, with DRM_MODE_FB_MODIFIERS
[20:21:05] [PASSED] YVU420 Valid modifier
[20:21:05] [PASSED] YVU420 Different modifiers per plane
[20:21:05] [PASSED] YVU420 Modifier for inexistent plane
[20:21:05] [PASSED] YUV420_10BIT Invalid modifier(DRM_FORMAT_MOD_LINEAR)
[20:21:05] [PASSED] X0L2 Normal sizes
[20:21:05] [PASSED] X0L2 Max sizes
[20:21:05] [PASSED] X0L2 Invalid pitch
[20:21:05] [PASSED] X0L2 Pitch greater than minimum required
[20:21:05] [PASSED] X0L2 Handle for inexistent plane
[20:21:05] [PASSED] X0L2 Offset for inexistent plane, without DRM_MODE_FB_MODIFIERS set
[20:21:05] [PASSED] X0L2 Modifier without DRM_MODE_FB_MODIFIERS set
[20:21:05] [PASSED] X0L2 Valid modifier
[20:21:05] [PASSED] X0L2 Modifier for inexistent plane
[20:21:05] =========== [PASSED] drm_test_framebuffer_create ===========
[20:21:05] [PASSED] drm_test_framebuffer_free
[20:21:05] [PASSED] drm_test_framebuffer_init
[20:21:05] [PASSED] drm_test_framebuffer_init_bad_format
[20:21:05] [PASSED] drm_test_framebuffer_init_dev_mismatch
[20:21:05] [PASSED] drm_test_framebuffer_lookup
[20:21:05] [PASSED] drm_test_framebuffer_lookup_inexistent
[20:21:05] [PASSED] drm_test_framebuffer_modifiers_not_supported
[20:21:05] ================= [PASSED] drm_framebuffer =================
[20:21:05] ================ drm_gem_shmem (8 subtests) ================
[20:21:05] [PASSED] drm_gem_shmem_test_obj_create
[20:21:05] [PASSED] drm_gem_shmem_test_obj_create_private
[20:21:05] [PASSED] drm_gem_shmem_test_pin_pages
[20:21:05] [PASSED] drm_gem_shmem_test_vmap
[20:21:05] [PASSED] drm_gem_shmem_test_get_sg_table
[20:21:05] [PASSED] drm_gem_shmem_test_get_pages_sgt
[20:21:05] [PASSED] drm_gem_shmem_test_madvise
[20:21:05] [PASSED] drm_gem_shmem_test_purge
[20:21:05] ================== [PASSED] drm_gem_shmem ==================
[20:21:05] === drm_atomic_helper_connector_hdmi_check (29 subtests) ===
[20:21:05] [PASSED] drm_test_check_broadcast_rgb_auto_cea_mode
[20:21:05] [PASSED] drm_test_check_broadcast_rgb_auto_cea_mode_vic_1
[20:21:05] [PASSED] drm_test_check_broadcast_rgb_full_cea_mode
[20:21:05] [PASSED] drm_test_check_broadcast_rgb_full_cea_mode_vic_1
[20:21:05] [PASSED] drm_test_check_broadcast_rgb_limited_cea_mode
[20:21:05] [PASSED] drm_test_check_broadcast_rgb_limited_cea_mode_vic_1
[20:21:05] ====== drm_test_check_broadcast_rgb_cea_mode_yuv420 =======
[20:21:05] [PASSED] Automatic
[20:21:05] [PASSED] Full
[20:21:05] [PASSED] Limited 16:235
[20:21:05] == [PASSED] drm_test_check_broadcast_rgb_cea_mode_yuv420 ===
[20:21:05] [PASSED] drm_test_check_broadcast_rgb_crtc_mode_changed
[20:21:05] [PASSED] drm_test_check_broadcast_rgb_crtc_mode_not_changed
[20:21:05] [PASSED] drm_test_check_disable_connector
[20:21:05] [PASSED] drm_test_check_hdmi_funcs_reject_rate
[20:21:05] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_rgb
[20:21:05] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_yuv420
[20:21:05] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_ignore_yuv422
[20:21:05] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_ignore_yuv420
[20:21:05] [PASSED] drm_test_check_driver_unsupported_fallback_yuv420
[20:21:05] [PASSED] drm_test_check_output_bpc_crtc_mode_changed
[20:21:05] [PASSED] drm_test_check_output_bpc_crtc_mode_not_changed
[20:21:05] [PASSED] drm_test_check_output_bpc_dvi
[20:21:05] [PASSED] drm_test_check_output_bpc_format_vic_1
[20:21:05] [PASSED] drm_test_check_output_bpc_format_display_8bpc_only
[20:21:05] [PASSED] drm_test_check_output_bpc_format_display_rgb_only
[20:21:05] [PASSED] drm_test_check_output_bpc_format_driver_8bpc_only
[20:21:05] [PASSED] drm_test_check_output_bpc_format_driver_rgb_only
[20:21:05] [PASSED] drm_test_check_tmds_char_rate_rgb_8bpc
[20:21:05] [PASSED] drm_test_check_tmds_char_rate_rgb_10bpc
[20:21:05] [PASSED] drm_test_check_tmds_char_rate_rgb_12bpc
[20:21:05] ============ drm_test_check_hdmi_color_format =============
[20:21:05] [PASSED] AUTO -> RGB
[20:21:05] [PASSED] YCBCR422 -> YUV422
[20:21:05] [PASSED] YCBCR420 -> YUV420
[20:21:05] [PASSED] YCBCR444 -> YUV444
[20:21:05] [PASSED] RGB -> RGB
[20:21:05] ======== [PASSED] drm_test_check_hdmi_color_format =========
[20:21:05] ======== drm_test_check_hdmi_color_format_420_only ========
[20:21:05] [PASSED] RGB should fail
[20:21:05] [PASSED] YUV444 should fail
[20:21:05] [PASSED] YUV422 should fail
[20:21:05] [PASSED] YUV420 should work
[20:21:05] ==== [PASSED] drm_test_check_hdmi_color_format_420_only ====
[20:21:05] ===== [PASSED] drm_atomic_helper_connector_hdmi_check ======
[20:21:05] === drm_atomic_helper_connector_hdmi_reset (6 subtests) ====
[20:21:05] [PASSED] drm_test_check_broadcast_rgb_value
[20:21:05] [PASSED] drm_test_check_bpc_8_value
[20:21:05] [PASSED] drm_test_check_bpc_10_value
[20:21:05] [PASSED] drm_test_check_bpc_12_value
[20:21:05] [PASSED] drm_test_check_format_value
[20:21:05] [PASSED] drm_test_check_tmds_char_value
[20:21:05] ===== [PASSED] drm_atomic_helper_connector_hdmi_reset ======
[20:21:05] = drm_atomic_helper_connector_hdmi_mode_valid (7 subtests) =
[20:21:05] [PASSED] drm_test_check_mode_valid
[20:21:05] [PASSED] drm_test_check_mode_valid_reject
[20:21:05] [PASSED] drm_test_check_mode_valid_reject_rate
[20:21:05] [PASSED] drm_test_check_mode_valid_reject_max_clock
[20:21:05] [PASSED] drm_test_check_mode_valid_yuv420_only_max_clock
[20:21:05] [PASSED] drm_test_check_mode_valid_reject_yuv420_only_connector
[20:21:05] [PASSED] drm_test_check_mode_valid_accept_yuv420_also_connector_rgb
[20:21:05] === [PASSED] drm_atomic_helper_connector_hdmi_mode_valid ===
[20:21:05] = drm_atomic_helper_connector_hdmi_infoframes (5 subtests) =
[20:21:05] [PASSED] drm_test_check_infoframes
[20:21:05] [PASSED] drm_test_check_reject_avi_infoframe
[20:21:05] [PASSED] drm_test_check_reject_hdr_infoframe_bpc_8
[20:21:05] [PASSED] drm_test_check_reject_hdr_infoframe_bpc_10
[20:21:05] [PASSED] drm_test_check_reject_audio_infoframe
[20:21:05] === [PASSED] drm_atomic_helper_connector_hdmi_infoframes ===
[20:21:05] ================= drm_managed (2 subtests) =================
[20:21:05] [PASSED] drm_test_managed_release_action
[20:21:05] [PASSED] drm_test_managed_run_action
[20:21:05] =================== [PASSED] drm_managed ===================
[20:21:05] =================== drm_mm (6 subtests) ====================
[20:21:05] [PASSED] drm_test_mm_init
[20:21:05] [PASSED] drm_test_mm_debug
[20:21:05] [PASSED] drm_test_mm_align32
[20:21:05] [PASSED] drm_test_mm_align64
[20:21:05] [PASSED] drm_test_mm_lowest
[20:21:05] [PASSED] drm_test_mm_highest
[20:21:05] ===================== [PASSED] drm_mm ======================
[20:21:05] ============= drm_modes_analog_tv (5 subtests) =============
[20:21:05] [PASSED] drm_test_modes_analog_tv_mono_576i
[20:21:05] [PASSED] drm_test_modes_analog_tv_ntsc_480i
[20:21:05] [PASSED] drm_test_modes_analog_tv_ntsc_480i_inlined
[20:21:05] [PASSED] drm_test_modes_analog_tv_pal_576i
[20:21:05] [PASSED] drm_test_modes_analog_tv_pal_576i_inlined
[20:21:05] =============== [PASSED] drm_modes_analog_tv ===============
[20:21:05] ============== drm_plane_helper (2 subtests) ===============
[20:21:05] =============== drm_test_check_plane_state ================
[20:21:05] [PASSED] clipping_simple
[20:21:05] [PASSED] clipping_rotate_reflect
[20:21:05] [PASSED] positioning_simple
[20:21:05] [PASSED] upscaling
[20:21:05] [PASSED] downscaling
[20:21:05] [PASSED] rounding1
[20:21:05] [PASSED] rounding2
[20:21:05] [PASSED] rounding3
[20:21:05] [PASSED] rounding4
[20:21:05] =========== [PASSED] drm_test_check_plane_state ============
[20:21:05] =========== drm_test_check_invalid_plane_state ============
[20:21:05] [PASSED] positioning_invalid
[20:21:05] [PASSED] upscaling_invalid
[20:21:05] [PASSED] downscaling_invalid
[20:21:05] ======= [PASSED] drm_test_check_invalid_plane_state ========
[20:21:05] ================ [PASSED] drm_plane_helper =================
[20:21:05] ====== drm_connector_helper_tv_get_modes (1 subtest) =======
[20:21:05] ====== drm_test_connector_helper_tv_get_modes_check =======
[20:21:05] [PASSED] None
[20:21:05] [PASSED] PAL
[20:21:05] [PASSED] NTSC
[20:21:05] [PASSED] Both, NTSC Default
[20:21:05] [PASSED] Both, PAL Default
[20:21:05] [PASSED] Both, NTSC Default, with PAL on command-line
[20:21:05] [PASSED] Both, PAL Default, with NTSC on command-line
[20:21:05] == [PASSED] drm_test_connector_helper_tv_get_modes_check ===
[20:21:05] ======== [PASSED] drm_connector_helper_tv_get_modes ========
[20:21:05] ================== drm_rect (9 subtests) ===================
[20:21:05] [PASSED] drm_test_rect_clip_scaled_div_by_zero
[20:21:05] [PASSED] drm_test_rect_clip_scaled_not_clipped
[20:21:05] [PASSED] drm_test_rect_clip_scaled_clipped
[20:21:05] [PASSED] drm_test_rect_clip_scaled_signed_vs_unsigned
[20:21:05] ================= drm_test_rect_intersect =================
[20:21:05] [PASSED] top-left x bottom-right: 2x2+1+1 x 2x2+0+0
[20:21:05] [PASSED] top-right x bottom-left: 2x2+0+0 x 2x2+1-1
[20:21:05] [PASSED] bottom-left x top-right: 2x2+1-1 x 2x2+0+0
[20:21:05] [PASSED] bottom-right x top-left: 2x2+0+0 x 2x2+1+1
[20:21:05] [PASSED] right x left: 2x1+0+0 x 3x1+1+0
[20:21:05] [PASSED] left x right: 3x1+1+0 x 2x1+0+0
[20:21:05] [PASSED] up x bottom: 1x2+0+0 x 1x3+0-1
[20:21:05] [PASSED] bottom x up: 1x3+0-1 x 1x2+0+0
[20:21:05] [PASSED] touching corner: 1x1+0+0 x 2x2+1+1
[20:21:05] [PASSED] touching side: 1x1+0+0 x 1x1+1+0
[20:21:05] [PASSED] equal rects: 2x2+0+0 x 2x2+0+0
[20:21:05] [PASSED] inside another: 2x2+0+0 x 1x1+1+1
[20:21:05] [PASSED] far away: 1x1+0+0 x 1x1+3+6
[20:21:05] [PASSED] points intersecting: 0x0+5+10 x 0x0+5+10
[20:21:05] [PASSED] points not intersecting: 0x0+0+0 x 0x0+5+10
[20:21:05] ============= [PASSED] drm_test_rect_intersect =============
[20:21:05] ================ drm_test_rect_calc_hscale ================
[20:21:05] [PASSED] normal use
[20:21:05] [PASSED] out of max range
[20:21:05] [PASSED] out of min range
[20:21:05] [PASSED] zero dst
[20:21:05] [PASSED] negative src
[20:21:05] [PASSED] negative dst
[20:21:05] ============ [PASSED] drm_test_rect_calc_hscale ============
[20:21:05] ================ drm_test_rect_calc_vscale ================
[20:21:05] [PASSED] normal use
[20:21:05] [PASSED] out of max range
[20:21:05] [PASSED] out of min range
[20:21:05] [PASSED] zero dst
[20:21:05] [PASSED] negative src
[20:21:05] [PASSED] negative dst
[20:21:05] ============ [PASSED] drm_test_rect_calc_vscale ============
[20:21:05] ================== drm_test_rect_rotate ===================
[20:21:05] [PASSED] reflect-x
[20:21:05] [PASSED] reflect-y
[20:21:05] [PASSED] rotate-0
[20:21:05] [PASSED] rotate-90
[20:21:05] [PASSED] rotate-180
[20:21:05] [PASSED] rotate-270
[20:21:05] ============== [PASSED] drm_test_rect_rotate ===============
[20:21:05] ================ drm_test_rect_rotate_inv =================
[20:21:05] [PASSED] reflect-x
[20:21:05] [PASSED] reflect-y
[20:21:05] [PASSED] rotate-0
[20:21:05] [PASSED] rotate-90
[20:21:05] [PASSED] rotate-180
[20:21:05] [PASSED] rotate-270
[20:21:05] ============ [PASSED] drm_test_rect_rotate_inv =============
[20:21:05] ==================== [PASSED] drm_rect =====================
[20:21:05] ============ drm_sysfb_modeset_test (1 subtest) ============
[20:21:05] ============ drm_test_sysfb_build_fourcc_list =============
[20:21:05] [PASSED] no native formats
[20:21:05] [PASSED] XRGB8888 as native format
[20:21:05] [PASSED] remove duplicates
[20:21:05] [PASSED] convert alpha formats
[20:21:05] [PASSED] random formats
[20:21:05] ======== [PASSED] drm_test_sysfb_build_fourcc_list =========
[20:21:05] ============= [PASSED] drm_sysfb_modeset_test ==============
[20:21:05] ================== drm_fixp (2 subtests) ===================
[20:21:05] [PASSED] drm_test_int2fixp
[20:21:05] [PASSED] drm_test_sm2fixp
[20:21:05] ==================== [PASSED] drm_fixp =====================
[20:21:05] ============================================================
[20:21:05] Testing complete. Ran 637 tests: passed: 637
[20:21:05] Elapsed time: 27.285s total, 1.881s configuring, 25.238s building, 0.155s running
+ /kernel/tools/testing/kunit/kunit.py run --kunitconfig /kernel/drivers/gpu/drm/ttm/tests/.kunitconfig
[20:21:05] Configuring KUnit Kernel ...
Regenerating .config ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
[20:21:07] Building KUnit Kernel ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
Building with:
$ make all compile_commands.json scripts_gdb ARCH=um O=.kunit --jobs=48
[20:21:17] Starting KUnit Kernel (1/1)...
[20:21:17] ============================================================
Running tests with:
$ .kunit/linux kunit.enable=1 mem=1G console=tty kunit_shutdown=halt
[20:21:17] ================= ttm_device (5 subtests) ==================
[20:21:17] [PASSED] ttm_device_init_basic
[20:21:17] [PASSED] ttm_device_init_multiple
[20:21:17] [PASSED] ttm_device_fini_basic
[20:21:17] [PASSED] ttm_device_init_no_vma_man
[20:21:17] ================== ttm_device_init_pools ==================
[20:21:17] [PASSED] No DMA allocations, no DMA32 required
[20:21:17] [PASSED] DMA allocations, DMA32 required
[20:21:17] [PASSED] No DMA allocations, DMA32 required
[20:21:17] [PASSED] DMA allocations, no DMA32 required
[20:21:17] ============== [PASSED] ttm_device_init_pools ==============
[20:21:17] =================== [PASSED] ttm_device ====================
[20:21:17] ================== ttm_pool (8 subtests) ===================
[20:21:17] ================== ttm_pool_alloc_basic ===================
[20:21:17] [PASSED] One page
[20:21:17] [PASSED] More than one page
[20:21:17] [PASSED] Above the allocation limit
[20:21:17] [PASSED] One page, with coherent DMA mappings enabled
[20:21:17] [PASSED] Above the allocation limit, with coherent DMA mappings enabled
[20:21:17] ============== [PASSED] ttm_pool_alloc_basic ===============
[20:21:17] ============== ttm_pool_alloc_basic_dma_addr ==============
[20:21:17] [PASSED] One page
[20:21:17] [PASSED] More than one page
[20:21:17] [PASSED] Above the allocation limit
[20:21:17] [PASSED] One page, with coherent DMA mappings enabled
[20:21:17] [PASSED] Above the allocation limit, with coherent DMA mappings enabled
[20:21:17] ========== [PASSED] ttm_pool_alloc_basic_dma_addr ==========
[20:21:17] [PASSED] ttm_pool_alloc_order_caching_match
[20:21:17] [PASSED] ttm_pool_alloc_caching_mismatch
[20:21:17] [PASSED] ttm_pool_alloc_order_mismatch
[20:21:17] [PASSED] ttm_pool_free_dma_alloc
[20:21:17] [PASSED] ttm_pool_free_no_dma_alloc
[20:21:17] [PASSED] ttm_pool_fini_basic
[20:21:17] ==================== [PASSED] ttm_pool =====================
[20:21:17] ================ ttm_resource (8 subtests) =================
[20:21:17] ================= ttm_resource_init_basic =================
[20:21:17] [PASSED] Init resource in TTM_PL_SYSTEM
[20:21:17] [PASSED] Init resource in TTM_PL_VRAM
[20:21:17] [PASSED] Init resource in a private placement
[20:21:17] [PASSED] Init resource in TTM_PL_SYSTEM, set placement flags
[20:21:17] ============= [PASSED] ttm_resource_init_basic =============
[20:21:17] [PASSED] ttm_resource_init_pinned
[20:21:17] [PASSED] ttm_resource_fini_basic
[20:21:17] [PASSED] ttm_resource_manager_init_basic
[20:21:17] [PASSED] ttm_resource_manager_usage_basic
[20:21:17] [PASSED] ttm_resource_manager_set_used_basic
[20:21:17] [PASSED] ttm_sys_man_alloc_basic
[20:21:17] [PASSED] ttm_sys_man_free_basic
[20:21:17] ================== [PASSED] ttm_resource ===================
[20:21:17] =================== ttm_tt (15 subtests) ===================
[20:21:17] ==================== ttm_tt_init_basic ====================
[20:21:17] [PASSED] Page-aligned size
[20:21:17] [PASSED] Extra pages requested
[20:21:17] ================ [PASSED] ttm_tt_init_basic ================
[20:21:17] [PASSED] ttm_tt_init_misaligned
[20:21:17] [PASSED] ttm_tt_fini_basic
[20:21:17] [PASSED] ttm_tt_fini_sg
[20:21:17] [PASSED] ttm_tt_fini_shmem
[20:21:17] [PASSED] ttm_tt_create_basic
[20:21:17] [PASSED] ttm_tt_create_invalid_bo_type
[20:21:17] [PASSED] ttm_tt_create_ttm_exists
[20:21:17] [PASSED] ttm_tt_create_failed
[20:21:17] [PASSED] ttm_tt_destroy_basic
[20:21:17] [PASSED] ttm_tt_populate_null_ttm
[20:21:17] [PASSED] ttm_tt_populate_populated_ttm
[20:21:17] [PASSED] ttm_tt_unpopulate_basic
[20:21:17] [PASSED] ttm_tt_unpopulate_empty_ttm
[20:21:17] [PASSED] ttm_tt_swapin_basic
[20:21:17] ===================== [PASSED] ttm_tt ======================
[20:21:17] =================== ttm_bo (14 subtests) ===================
[20:21:17] =========== ttm_bo_reserve_optimistic_no_ticket ===========
[20:21:17] [PASSED] Cannot be interrupted and sleeps
[20:21:17] [PASSED] Cannot be interrupted, locks straight away
[20:21:17] [PASSED] Can be interrupted, sleeps
[20:21:17] ======= [PASSED] ttm_bo_reserve_optimistic_no_ticket =======
[20:21:17] [PASSED] ttm_bo_reserve_locked_no_sleep
[20:21:17] [PASSED] ttm_bo_reserve_no_wait_ticket
[20:21:17] [PASSED] ttm_bo_reserve_double_resv
[20:21:17] [PASSED] ttm_bo_reserve_interrupted
[20:21:17] [PASSED] ttm_bo_reserve_deadlock
[20:21:17] [PASSED] ttm_bo_unreserve_basic
[20:21:17] [PASSED] ttm_bo_unreserve_pinned
[20:21:17] [PASSED] ttm_bo_unreserve_bulk
[20:21:17] [PASSED] ttm_bo_fini_basic
[20:21:17] [PASSED] ttm_bo_fini_shared_resv
[20:21:17] [PASSED] ttm_bo_pin_basic
[20:21:17] [PASSED] ttm_bo_pin_unpin_resource
[20:21:17] [PASSED] ttm_bo_multiple_pin_one_unpin
[20:21:17] ===================== [PASSED] ttm_bo ======================
[20:21:17] ============== ttm_bo_validate (22 subtests) ===============
[20:21:17] ============== ttm_bo_init_reserved_sys_man ===============
[20:21:17] [PASSED] Buffer object for userspace
[20:21:17] [PASSED] Kernel buffer object
[20:21:17] [PASSED] Shared buffer object
[20:21:17] ========== [PASSED] ttm_bo_init_reserved_sys_man ===========
[20:21:17] ============== ttm_bo_init_reserved_mock_man ==============
[20:21:17] [PASSED] Buffer object for userspace
[20:21:17] [PASSED] Kernel buffer object
[20:21:17] [PASSED] Shared buffer object
[20:21:17] ========== [PASSED] ttm_bo_init_reserved_mock_man ==========
[20:21:17] [PASSED] ttm_bo_init_reserved_resv
[20:21:17] ================== ttm_bo_validate_basic ==================
[20:21:17] [PASSED] Buffer object for userspace
[20:21:17] [PASSED] Kernel buffer object
[20:21:17] [PASSED] Shared buffer object
[20:21:17] ============== [PASSED] ttm_bo_validate_basic ==============
[20:21:17] [PASSED] ttm_bo_validate_invalid_placement
[20:21:17] ============= ttm_bo_validate_same_placement ==============
[20:21:17] [PASSED] System manager
[20:21:17] [PASSED] VRAM manager
[20:21:17] ========= [PASSED] ttm_bo_validate_same_placement ==========
[20:21:17] [PASSED] ttm_bo_validate_failed_alloc
[20:21:17] [PASSED] ttm_bo_validate_pinned
[20:21:17] [PASSED] ttm_bo_validate_busy_placement
[20:21:17] ================ ttm_bo_validate_multihop =================
[20:21:17] [PASSED] Buffer object for userspace
[20:21:17] [PASSED] Kernel buffer object
[20:21:17] [PASSED] Shared buffer object
[20:21:17] ============ [PASSED] ttm_bo_validate_multihop =============
[20:21:17] ========== ttm_bo_validate_no_placement_signaled ==========
[20:21:17] [PASSED] Buffer object in system domain, no page vector
[20:21:17] [PASSED] Buffer object in system domain with an existing page vector
[20:21:17] ====== [PASSED] ttm_bo_validate_no_placement_signaled ======
[20:21:17] ======== ttm_bo_validate_no_placement_not_signaled ========
[20:21:17] [PASSED] Buffer object for userspace
[20:21:17] [PASSED] Kernel buffer object
[20:21:17] [PASSED] Shared buffer object
[20:21:17] ==== [PASSED] ttm_bo_validate_no_placement_not_signaled ====
[20:21:17] [PASSED] ttm_bo_validate_move_fence_signaled
[20:21:17] ========= ttm_bo_validate_move_fence_not_signaled =========
[20:21:17] [PASSED] Waits for GPU
[20:21:17] [PASSED] Tries to lock straight away
[20:21:17] ===== [PASSED] ttm_bo_validate_move_fence_not_signaled =====
[20:21:17] [PASSED] ttm_bo_validate_swapout
[20:21:17] [PASSED] ttm_bo_validate_happy_evict
[20:21:17] [PASSED] ttm_bo_validate_all_pinned_evict
[20:21:17] [PASSED] ttm_bo_validate_allowed_only_evict
[20:21:17] [PASSED] ttm_bo_validate_deleted_evict
[20:21:17] [PASSED] ttm_bo_validate_busy_domain_evict
[20:21:17] [PASSED] ttm_bo_validate_evict_gutting
[20:21:17] [PASSED] ttm_bo_validate_recrusive_evict
[20:21:17] ================= [PASSED] ttm_bo_validate =================
[20:21:17] ============================================================
[20:21:17] Testing complete. Ran 102 tests: passed: 102
[20:21:17] Elapsed time: 12.034s total, 1.889s configuring, 9.930s building, 0.184s running
+ /kernel/tools/testing/kunit/kunit.py run --kunitconfig /kernel/drivers/dma-buf/.kunitconfig
[20:21:18] Configuring KUnit Kernel ...
Regenerating .config ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
[20:21:19] Building KUnit Kernel ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
Building with:
$ make all compile_commands.json scripts_gdb ARCH=um O=.kunit --jobs=48
[20:21:28] Starting KUnit Kernel (1/1)...
[20:21:28] ============================================================
Running tests with:
$ .kunit/linux kunit.enable=1 mem=1G console=tty kunit_shutdown=halt
[20:21:28] =============== dma-buf-fence (12 subtests) ================
[20:21:28] [PASSED] test_sanitycheck
[20:21:28] [PASSED] test_signaling
[20:21:28] [PASSED] test_add_callback
[20:21:28] [PASSED] test_late_add_callback
[20:21:28] [PASSED] test_rm_callback
[20:21:28] [PASSED] test_late_rm_callback
[20:21:28] [PASSED] test_status
[20:21:28] [PASSED] test_error
[20:21:28] [PASSED] test_wait
[20:21:28] [PASSED] test_wait_timeout
[20:21:28] [PASSED] test_stub
[20:21:28] [SKIPPED] test_race_signal_callback (requires at least 2 CPUs)
[20:21:28] ================== [PASSED] dma-buf-fence ==================
[20:21:28] ============ dma-buf-fence-chain (11 subtests) =============
[20:21:28] [PASSED] test_sanitycheck
[20:21:28] [PASSED] test_find_seqno
[20:21:28] [PASSED] test_find_signaled
[20:21:28] [PASSED] test_find_out_of_order
[20:21:33] [PASSED] test_find_gap
[20:21:33] [PASSED] test_find_race
[20:21:33] [PASSED] test_signal_forward
[20:21:33] [PASSED] test_signal_backward
[20:21:33] [PASSED] test_wait_forward
[20:21:33] [PASSED] test_wait_backward
[20:21:33] [PASSED] test_wait_random
[20:21:33] =============== [PASSED] dma-buf-fence-chain ===============
[20:21:33] ============ dma-buf-fence-unwrap (10 subtests) ============
[20:21:33] [PASSED] test_sanitycheck
[20:21:33] [PASSED] test_unwrap_array
[20:21:33] [PASSED] test_unwrap_chain
[20:21:33] [PASSED] test_unwrap_chain_array
[20:21:33] [PASSED] test_unwrap_merge
[20:21:33] [PASSED] test_unwrap_merge_duplicate
[20:21:33] [PASSED] test_unwrap_merge_seqno
[20:21:33] [PASSED] test_unwrap_merge_order
[20:21:33] [PASSED] test_unwrap_merge_complex
[20:21:33] [PASSED] test_unwrap_merge_complex_seqno
[20:21:33] ============== [PASSED] dma-buf-fence-unwrap ===============
[20:21:33] ================ dma-buf-resv (5 subtests) =================
[20:21:33] [PASSED] test_sanitycheck
[20:21:33] ===================== test_signaling ======================
[20:21:33] [PASSED] kernel
[20:21:33] [PASSED] write
[20:21:33] [PASSED] read
[20:21:33] [PASSED] bookkeep
[20:21:33] ================= [PASSED] test_signaling ==================
[20:21:33] ====================== test_for_each ======================
[20:21:33] [PASSED] kernel
[20:21:33] [PASSED] write
[20:21:33] [PASSED] read
[20:21:33] [PASSED] bookkeep
[20:21:33] ================== [PASSED] test_for_each ==================
[20:21:33] ================= test_for_each_unlocked ==================
[20:21:33] [PASSED] kernel
[20:21:33] [PASSED] write
[20:21:33] [PASSED] read
[20:21:33] [PASSED] bookkeep
[20:21:33] ============= [PASSED] test_for_each_unlocked ==============
[20:21:33] ===================== test_get_fences =====================
[20:21:33] [PASSED] kernel
[20:21:33] [PASSED] write
[20:21:33] [PASSED] read
[20:21:33] [PASSED] bookkeep
[20:21:33] ================= [PASSED] test_get_fences =================
[20:21:33] ================== [PASSED] dma-buf-resv ===================
[20:21:33] ============================================================
[20:21:33] Testing complete. Ran 50 tests: passed: 49, skipped: 1
[20:21:33] Elapsed time: 15.865s total, 1.865s configuring, 8.679s building, 5.279s running
+ cleanup
++ stat -c %u:%g /kernel
+ chown -R 1003:1003 /kernel
^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [CI] drm/xe: Disable scheduling early on FD close to avoid CAT error cascade
2026-08-25 20:11 [CI] drm/xe: Disable scheduling early on FD close to avoid CAT error cascade Matthew Brost
2026-08-25 20:21 ` ✓ CI.KUnit: success for drm/xe: Disable scheduling early on FD close to avoid CAT error cascade (rev5) Patchwork
@ 2026-08-25 20:29 ` sashiko-bot
2026-08-25 21:04 ` ✓ Xe.CI.BAT: success for drm/xe: Disable scheduling early on FD close to avoid CAT error cascade (rev5) Patchwork
2 siblings, 0 replies; 6+ messages in thread
From: sashiko-bot @ 2026-08-25 20:29 UTC (permalink / raw)
To: Matthew Brost; +Cc: intel-xe
Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [High] The `KILL` message handler unconditionally accesses hardware without checking if the device is physically present, which can lead to crashes on hot-unplug.
--
commit 6b34abf1203c0a3c2fe102d1601b9f19c5a65d6b
Author: Matthew Brost <matthew.brost@intel.com>
drm/xe: Disable scheduling early on FD close to avoid CAT error cascade
This commit mitigates CAT error cascades by eagerly sending a self-message
to disable scheduling outside the serialized TDR path when an FD is closed.
> diff --git a/drivers/gpu/drm/xe/xe_guc_submit.c b/drivers/gpu/drm/xe/xe_guc_submit.c
> index 99d8c807ff056..8b8972b2ebea1 100644
> --- a/drivers/gpu/drm/xe/xe_guc_submit.c
> +++ b/drivers/gpu/drm/xe/xe_guc_submit.c
[ ... ]
> @@ -1969,12 +1969,22 @@ static void __guc_exec_queue_process_msg_cgp_sync(struct xe_sched_msg *msg,
> guc_exec_queue_send_cgp_sync(q, 0);
> }
>
> +static void __guc_exec_queue_process_msg_kill(struct xe_sched_msg *msg)
> +{
> + struct xe_exec_queue *q = msg->private_data;
> + struct xe_exec_queue *primary = xe_exec_queue_multi_queue_primary(q);
> +
> + if (exec_queue_enabled(primary))
> + disable_scheduling(primary, true);
> +}
[Severity: High]
Could this lead to an MMIO crash on device hot-unplug?
When a hot-unplug event occurs, the device is disconnected and
drm_dev_enter() will return false, indicating the hardware is gone.
If userspace then closes the file descriptor, guc_exec_queue_kill()
will send the KILL message.
Because disable_scheduling() eventually invokes xe_guc_ct_send(), which
performs an unconditional MMIO write (xe_mmio_write32()), calling it
without verifying if the device is still physically present might trigger
a fatal bus error (Machine Check Exception).
Should this handler accept and check the bound state before touching the
hardware, similar to how other message handlers like
__guc_exec_queue_process_msg_cgp_sync() handle it?
> #define CLEANUP 1 /* Non-zero values to catch uninitialized msg */
> #define SET_SCHED_PROPS 2
> #define SUSPEND 3
> #define RESUME 4
> #define SET_MULTI_QUEUE_PRIORITY 5
> #define CGP_SYNC_MSG 6
> +#define KILL 7
> #define OPCODE_MASK 0xf
> #define MSG_LOCKED BIT(8)
> #define MSG_HEAD BIT(9)
> @@ -2008,6 +2018,9 @@ static void guc_exec_queue_process_msg(struct xe_sched_msg *msg)
> case CGP_SYNC_MSG:
> __guc_exec_queue_process_msg_cgp_sync(msg, bound);
> break;
> + case KILL:
> + __guc_exec_queue_process_msg_kill(msg);
> + break;
[Severity: High]
Does this miss passing the bound state to the KILL handler?
At the start of guc_exec_queue_process_msg(), the bound state is acquired
via drm_dev_enter():
bool bound = drm_dev_enter(&xe->drm, &idx);
Other handlers like __guc_exec_queue_process_msg_cgp_sync(msg, bound)
receive this state so they can avoid hardware access if the device is gone.
Since __guc_exec_queue_process_msg_kill() isn't receiving bound, it seems
to bypass this safety check.
--
Sashiko AI review · https://sashiko.dev/#/patchset/20260825201148.1780176-1-matthew.brost@intel.com?part=1
^ permalink raw reply [flat|nested] 6+ messages in thread* ✓ Xe.CI.BAT: success for drm/xe: Disable scheduling early on FD close to avoid CAT error cascade (rev5)
2026-08-25 20:11 [CI] drm/xe: Disable scheduling early on FD close to avoid CAT error cascade Matthew Brost
2026-08-25 20:21 ` ✓ CI.KUnit: success for drm/xe: Disable scheduling early on FD close to avoid CAT error cascade (rev5) Patchwork
2026-08-25 20:29 ` [CI] drm/xe: Disable scheduling early on FD close to avoid CAT error cascade sashiko-bot
@ 2026-08-25 21:04 ` Patchwork
2 siblings, 0 replies; 6+ messages in thread
From: Patchwork @ 2026-08-25 21:04 UTC (permalink / raw)
To: Matthew Brost; +Cc: intel-xe
[-- Attachment #1: Type: text/plain, Size: 941 bytes --]
== Series Details ==
Series: drm/xe: Disable scheduling early on FD close to avoid CAT error cascade (rev5)
URL : https://patchwork.freedesktop.org/series/168398/
State : success
== Summary ==
CI Bug Log - changes from xe-5642-15e2ba2fb6d25c03d89519aec46f8d5be3e118ad_BAT -> xe-pw-168398v5_BAT
====================================================
Summary
-------
**SUCCESS**
No regressions found.
Participating hosts (13 -> 12)
------------------------------
Missing (1): bat-bmg-2
Changes
-------
No changes found
Build changes
-------------
* IGT: IGT_9071 -> IGT_9074
* Linux: xe-5642-15e2ba2fb6d25c03d89519aec46f8d5be3e118ad -> xe-pw-168398v5
IGT_9071: 9071
IGT_9074: 9074
xe-5642-15e2ba2fb6d25c03d89519aec46f8d5be3e118ad: 15e2ba2fb6d25c03d89519aec46f8d5be3e118ad
xe-pw-168398v5: 168398v5
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-168398v5/index.html
[-- Attachment #2: Type: text/html, Size: 1503 bytes --]
^ permalink raw reply [flat|nested] 6+ messages in thread
* [CI] drm/xe: Disable scheduling early on FD close to avoid CAT error cascade
@ 2026-08-25 20:35 Matthew Brost
2026-08-25 20:54 ` sashiko-bot
0 siblings, 1 reply; 6+ messages in thread
From: Matthew Brost @ 2026-08-25 20:35 UTC (permalink / raw)
To: intel-xe; +Cc: Wang Xin, Jia Yao, Jonathan Cavitt
When an FD is closed with many exec queues, teardown relies on the TDR
path to clean up scheduling. However, the TDR handling is serialized
(i.e., only one exec queue is processed at a time), which can make it
too slow compared to GuC scheduling activity.
In this window, GuC may continue to schedule contexts backed by
invalid page tables, leading to a cascade of CAT errors and repeated
engine resets. This significantly increases recovery time and can
degrade system stability.
To mitigate this, eagerly disable scheduling by sending a self-message
outside of the TDR path. This prevents further scheduling of invalid
contexts and avoids the CAT error/reset cascade.
This change improves robustness and reduces recovery latency in
multiple queue teardown scenarios.
Cc: Wang Xin <x.wang@intel.com>
Cc: Jia Yao <jia.yao@intel.com>
Signed-off-by: Matthew Brost <matthew.brost@intel.com>
Tested-by: Jia Yao <jia.yao@intel.com>
Reviewed-by: Jonathan Cavitt <jonathan.cavitt@intel.com>
---
drivers/gpu/drm/xe/xe_guc_exec_queue_types.h | 2 +-
drivers/gpu/drm/xe/xe_guc_submit.c | 46 ++++++++++++++++++--
2 files changed, 43 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/xe/xe_guc_exec_queue_types.h b/drivers/gpu/drm/xe/xe_guc_exec_queue_types.h
index d27826b36649..a46cde5ed81f 100644
--- a/drivers/gpu/drm/xe/xe_guc_exec_queue_types.h
+++ b/drivers/gpu/drm/xe/xe_guc_exec_queue_types.h
@@ -36,7 +36,7 @@ struct xe_guc_exec_queue {
* a message needs to sent through the GPU scheduler but memory
* allocations are not allowed.
*/
-#define MAX_STATIC_MSG_TYPE 4
+#define MAX_STATIC_MSG_TYPE 5
struct xe_sched_msg static_msgs[MAX_STATIC_MSG_TYPE];
/** @destroy_async: do final destroy async from this worker */
struct work_struct destroy_async;
diff --git a/drivers/gpu/drm/xe/xe_guc_submit.c b/drivers/gpu/drm/xe/xe_guc_submit.c
index 99d8c807ff05..33ef884cd316 100644
--- a/drivers/gpu/drm/xe/xe_guc_submit.c
+++ b/drivers/gpu/drm/xe/xe_guc_submit.c
@@ -1969,12 +1969,23 @@ static void __guc_exec_queue_process_msg_cgp_sync(struct xe_sched_msg *msg,
guc_exec_queue_send_cgp_sync(q, 0);
}
+static void __guc_exec_queue_process_msg_kill(struct xe_sched_msg *msg,
+ bool bound)
+{
+ struct xe_exec_queue *q = msg->private_data;
+ struct xe_exec_queue *primary = xe_exec_queue_multi_queue_primary(q);
+
+ if (exec_queue_enabled(primary) && bound)
+ disable_scheduling(primary, true);
+}
+
#define CLEANUP 1 /* Non-zero values to catch uninitialized msg */
#define SET_SCHED_PROPS 2
#define SUSPEND 3
#define RESUME 4
#define SET_MULTI_QUEUE_PRIORITY 5
#define CGP_SYNC_MSG 6
+#define KILL 7
#define OPCODE_MASK 0xf
#define MSG_LOCKED BIT(8)
#define MSG_HEAD BIT(9)
@@ -2008,6 +2019,9 @@ static void guc_exec_queue_process_msg(struct xe_sched_msg *msg)
case CGP_SYNC_MSG:
__guc_exec_queue_process_msg_cgp_sync(msg, bound);
break;
+ case KILL:
+ __guc_exec_queue_process_msg_kill(msg, bound);
+ break;
default:
XE_WARN_ON("Unknown message type");
}
@@ -2130,11 +2144,39 @@ static int guc_exec_queue_init(struct xe_exec_queue *q)
return err;
}
+static bool guc_exec_queue_try_add_msg(struct xe_exec_queue *q,
+ struct xe_sched_msg *msg,
+ u32 opcode);
+
+#define STATIC_MSG_CLEANUP 0
+#define STATIC_MSG_SUSPEND 1
+#define STATIC_MSG_RESUME 2
+#define STATIC_MSG_CGP_SYNC 3
+#define STATIC_MSG_KILL 4
static void guc_exec_queue_kill(struct xe_exec_queue *q)
{
+ struct xe_sched_msg *msg = q->guc->static_msgs + STATIC_MSG_KILL;
+
trace_xe_exec_queue_kill(q);
set_exec_queue_killed(q);
__suspend_fence_signal(q);
+
+ /*
+ * We eagerly send a message to ourselves to disable scheduling, as the
+ * TDR is serialized (i.e., only one exec queue is processed at a time).
+ * If an FD is closed with many exec queues, the TDR can be slower than
+ * the GuC scheduling contexts with invalid page tables, creating a
+ * cascade of CAT errors and engine resets, which is quite slow. Avoid
+ * this by immediately disabling scheduling outside of the TDR.
+ */
+ if (kref_read(&q->refcount) && !exec_queue_wedged(q)) {
+ struct xe_gpu_scheduler *sched = &q->guc->sched;
+
+ xe_sched_msg_lock(sched);
+ guc_exec_queue_try_add_msg(q, msg, KILL);
+ xe_sched_msg_unlock(sched);
+ }
+
xe_guc_exec_queue_trigger_cleanup(q);
}
@@ -2187,10 +2229,6 @@ static bool guc_exec_queue_try_add_msg(struct xe_exec_queue *q,
return true;
}
-#define STATIC_MSG_CLEANUP 0
-#define STATIC_MSG_SUSPEND 1
-#define STATIC_MSG_RESUME 2
-#define STATIC_MSG_CGP_SYNC 3
static void guc_exec_queue_destroy(struct xe_exec_queue *q)
{
struct xe_sched_msg *msg = q->guc->static_msgs + STATIC_MSG_CLEANUP;
--
2.34.1
^ permalink raw reply related [flat|nested] 6+ messages in thread* Re: [CI] drm/xe: Disable scheduling early on FD close to avoid CAT error cascade
2026-08-25 20:35 [CI] drm/xe: Disable scheduling early on FD close to avoid CAT error cascade Matthew Brost
@ 2026-08-25 20:54 ` sashiko-bot
0 siblings, 0 replies; 6+ messages in thread
From: sashiko-bot @ 2026-08-25 20:54 UTC (permalink / raw)
To: Matthew Brost; +Cc: intel-xe
Thank you for your contribution! Sashiko AI review found 2 potential issue(s) to consider:
- [High] A data race on the shared static message buffer causes a Power Management (PM) runtime reference leak when an exec queue is killed concurrently.
- [Medium] Double-disable of scheduling when KILL message races with TDR, potentially causing an unnecessary GT reset.
--
commit cb0a16de6bfaa13bc0da2d9c7548fe3a5d58a847
Author: Matthew Brost <matthew.brost@intel.com>
Subject: drm/xe: Disable scheduling early on FD close to avoid CAT error cascade
This commit introduces a mechanism to eagerly disable scheduling on FD close
by sending a self-message (KILL) outside of the TDR path. This prevents
contexts with invalid page tables from continuing to schedule, avoiding CAT
error cascades.
> diff --git a/drivers/gpu/drm/xe/xe_guc_submit.c b/drivers/gpu/drm/xe/xe_guc_submit.c
> index 99d8c807ff056..33ef884cd3162 100644
> --- a/drivers/gpu/drm/xe/xe_guc_submit.c
> +++ b/drivers/gpu/drm/xe/xe_guc_submit.c
[ ... ]
> @@ -2130,11 +2144,39 @@ static int guc_exec_queue_init(struct xe_exec_queue *q)
> return err;
> }
>
> +static bool guc_exec_queue_try_add_msg(struct xe_exec_queue *q,
> + struct xe_sched_msg *msg,
> + u32 opcode);
> +
> +#define STATIC_MSG_CLEANUP 0
> +#define STATIC_MSG_SUSPEND 1
> +#define STATIC_MSG_RESUME 2
> +#define STATIC_MSG_CGP_SYNC 3
> +#define STATIC_MSG_KILL 4
> static void guc_exec_queue_kill(struct xe_exec_queue *q)
> {
> + struct xe_sched_msg *msg = q->guc->static_msgs + STATIC_MSG_KILL;
> +
> trace_xe_exec_queue_kill(q);
> set_exec_queue_killed(q);
> __suspend_fence_signal(q);
> +
> + /*
> + * We eagerly send a message to ourselves to disable scheduling, as the
> + * TDR is serialized (i.e., only one exec queue is processed at a time).
> + * If an FD is closed with many exec queues, the TDR can be slower than
> + * the GuC scheduling contexts with invalid page tables, creating a
> + * cascade of CAT errors and engine resets, which is quite slow. Avoid
> + * this by immediately disabling scheduling outside of the TDR.
> + */
> + if (kref_read(&q->refcount) && !exec_queue_wedged(q)) {
> + struct xe_gpu_scheduler *sched = &q->guc->sched;
> +
> + xe_sched_msg_lock(sched);
> + guc_exec_queue_try_add_msg(q, msg, KILL);
[Severity: High]
Could this cause a Power Management (PM) runtime reference leak if multiple
threads call this concurrently?
When an exec queue is killed, this code enqueues the shared static KILL
message. Since guc_exec_queue_try_add_msg() checks list_empty(), what
happens if the background worker has already dequeued this message and is
currently processing it?
If a second concurrent kill re-enqueues the same static message,
guc_exec_queue_add_msg() will overwrite msg->opcode, temporarily clearing
the MSG_PM_REF flag:
xe_guc_submit.c:guc_exec_queue_add_msg() {
...
msg->opcode = opcode & OPCODE_MASK;
if (bound) {
xe_pm_runtime_get_noresume(xe);
msg->opcode |= MSG_PM_REF;
}
...
}
Meanwhile, the worker might be concurrently reading msg->opcode without a
lock in guc_exec_queue_process_msg():
bool pm_ref = !!(msg->opcode & MSG_PM_REF);
If the worker observes MSG_PM_REF as 0, could it skip xe_pm_runtime_put()
and permanently leak the PM runtime reference?
[Severity: Medium]
Could queuing this KILL message race with the TDR worker and cause an
unnecessary full GT reset?
The commit intentionally queues both the KILL message and the TDR worker
simultaneously when a queue is killed. If the KILL message executes first,
it calls disable_scheduling() which sets pending_disable.
When TDR executes guc_exec_queue_timedout_job(), it enters its disable block
because pending_disable is true, waits for it to clear, and then
unconditionally calls disable_scheduling() again:
xe_guc_submit.c:guc_exec_queue_timedout_job() {
...
disable_scheduling(primary, skip_timeout_check);
...
}
If the GuC firmware rejects this redundant state change and does not return
a successful SCHED_DONE response, could TDR's subsequent wait time out and
trigger a stall followed by a full GT reset?
> + xe_sched_msg_unlock(sched);
> + }
> +
> xe_guc_exec_queue_trigger_cleanup(q);
> }
--
Sashiko AI review · https://sashiko.dev/#/patchset/20260825203506.1791216-1-matthew.brost@intel.com?part=1
^ permalink raw reply [flat|nested] 6+ messages in thread
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2026-08-25 20:11 [CI] drm/xe: Disable scheduling early on FD close to avoid CAT error cascade Matthew Brost
2026-08-25 20:21 ` ✓ CI.KUnit: success for drm/xe: Disable scheduling early on FD close to avoid CAT error cascade (rev5) Patchwork
2026-08-25 20:29 ` [CI] drm/xe: Disable scheduling early on FD close to avoid CAT error cascade sashiko-bot
2026-08-25 21:04 ` ✓ Xe.CI.BAT: success for drm/xe: Disable scheduling early on FD close to avoid CAT error cascade (rev5) Patchwork
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2026-08-25 20:35 [CI] drm/xe: Disable scheduling early on FD close to avoid CAT error cascade Matthew Brost
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