From: Ville Syrjala <ville.syrjala@linux.intel.com>
To: intel-gfx@lists.freedesktop.org
Cc: intel-xe@lists.freedesktop.org, Jani Nikula <jani.nikula@intel.com>
Subject: [PATCH v2 05/14] drm/i915/cdclk: Stop forcing voltage level to 3 all the time on DG2
Date: Wed, 26 Aug 2026 16:40:24 +0300 [thread overview]
Message-ID: <20260826134033.13976-6-ville.syrjala@linux.intel.com> (raw)
In-Reply-To: <20260826134033.13976-1-ville.syrjala@linux.intel.com>
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
SKL_CDCLK_PREPARE_FOR_CHANGE == DISPLAY_TO_PCODE_VOLTAGE(3) so
we are currently forcing the voltage level to 3 all the time on
DG2. Remove SKL_CDCLK_PREPARE_FOR_CHANGE from the mask to avoid
this.
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/display/intel_cdclk.c | 1 -
1 file changed, 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c b/drivers/gpu/drm/i915/display/intel_cdclk.c
index 052274cd0e19..e05b6e76363c 100644
--- a/drivers/gpu/drm/i915/display/intel_cdclk.c
+++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
@@ -2647,7 +2647,6 @@ static void intel_pcode_notify(struct intel_display *display,
update_mask |= DISPLAY_TO_PCODE_PIPE_COUNT_VALID;
ret = intel_parent_pcode_request(display, SKL_PCODE_CDCLK_CONTROL,
- SKL_CDCLK_PREPARE_FOR_CHANGE |
update_mask,
SKL_CDCLK_READY_FOR_CHANGE,
SKL_CDCLK_READY_FOR_CHANGE, 3);
--
2.54.0
next prev parent reply other threads:[~2026-08-26 13:41 UTC|newest]
Thread overview: 20+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-08-26 13:40 [PATCH v2 00/14] drm/i915/cdclk: cdclk pcode related fixes and refactoring Ville Syrjala
2026-08-26 13:40 ` [PATCH v2 01/14] drm/i915/cdclk: Don't bail if pcode post nofify fails Ville Syrjala
2026-08-26 13:40 ` [PATCH v2 02/14] drm/i915/cdclk: Pass CDCLK in MHz to pcode on DG2 Ville Syrjala
2026-08-26 13:40 ` [PATCH v2 03/14] drm/i915/cdclk: Do the DG2 CDCLK/pipe power well notify properly Ville Syrjala
2026-08-26 13:40 ` [PATCH v2 04/14] drm/i915/cdclk: Notify DG2 pcode about pipe power wells regardless of CDCLK Ville Syrjala
2026-08-26 13:58 ` sashiko-bot
2026-08-26 13:40 ` Ville Syrjala [this message]
2026-08-26 13:40 ` [PATCH v2 06/14] drm/i915/cdclk: Drop pointless platform check from bxt_set_cdclk() Ville Syrjala
2026-08-26 13:40 ` [PATCH v2 07/14] drm/i915/dg2: s/intel_/dg2_/ for DG2 specific stuff Ville Syrjala
2026-08-26 13:52 ` sashiko-bot
2026-08-26 13:40 ` [PATCH v2 08/14] drm/i915/cdclk: Unify the pcode pre/post notify in bxt_set_cdclk() Ville Syrjala
2026-08-26 13:40 ` [PATCH v2 09/14] drm/i915/cdclk: Unify pcode related debugs Ville Syrjala
2026-08-26 13:40 ` [PATCH v2 10/14] drm/i915/cdclk: Extract bdw_cdclk_pcode_{pre, post}_notify() Ville Syrjala
2026-08-26 13:40 ` [PATCH v2 11/14] drm/i915/cdclk: Extract skl_cdclk_pcode_{pre, post}_notify() Ville Syrjala
2026-08-26 13:40 ` [PATCH v2 12/14] drm/i915/cdclk: Extract bxt_cdclk_pcode_{pre, post}_notify() Ville Syrjala
2026-08-26 13:40 ` [PATCH v2 13/14] drm/i915/cdclk: Introduce CDCLK .{pre, post}_notify() vfuncs Ville Syrjala
2026-08-26 13:40 ` [PATCH v2 14/14] drm/i915/cdclk: Hoist intel_cdclk_{pre, post}_notify() calls upwards Ville Syrjala
2026-08-26 13:48 ` ✓ CI.KUnit: success for drm/i915/cdclk: cdclk pcode related fixes and refactoring (rev2) Patchwork
2026-08-26 14:49 ` ✓ Xe.CI.BAT: " Patchwork
2026-08-26 18:28 ` ✓ Xe.CI.FULL: " Patchwork
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