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From: Ville Syrjala <ville.syrjala@linux.intel.com>
To: intel-gfx@lists.freedesktop.org
Cc: intel-xe@lists.freedesktop.org, Jani Nikula <jani.nikula@intel.com>
Subject: [PATCH v2 06/14] drm/i915/cdclk: Drop pointless platform check from bxt_set_cdclk()
Date: Wed, 26 Aug 2026 16:40:25 +0300	[thread overview]
Message-ID: <20260826134033.13976-7-ville.syrjala@linux.intel.com> (raw)
In-Reply-To: <20260826134033.13976-1-ville.syrjala@linux.intel.com>

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

Overwrite cdclk.hw.voltage_level from intel_update_cdclk() at the
end on bxt_set_cdclk() also on bxt/glk. While this isn't actually
necessary due to bxt/glk not having any extra DDI based voltage
level requirements, it does avoid one less silly 'if' in the code.

On icl+ the value derived by bxt_get_cdclk() may not be correct
if the voltage level was bumped up due to DDI requirements, thus
overwriting the assumed value is crucial there.

Reviewed-by: Jani Nikula <jani.nikula@intel.com>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/display/intel_cdclk.c | 11 +++++------
 1 file changed, 5 insertions(+), 6 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c b/drivers/gpu/drm/i915/display/intel_cdclk.c
index e05b6e76363c..6453a7cc0cee 100644
--- a/drivers/gpu/drm/i915/display/intel_cdclk.c
+++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
@@ -2335,12 +2335,11 @@ static void bxt_set_cdclk(struct intel_display *display,
 
 	intel_update_cdclk(display);
 
-	if (DISPLAY_VER(display) >= 11)
-		/*
-		 * Can't read out the voltage level :(
-		 * Let's just assume everything is as expected.
-		 */
-		display->cdclk.hw.voltage_level = cdclk_config->voltage_level;
+	/*
+	 * Can't read out the voltage level :(
+	 * Let's just assume everything is as expected.
+	 */
+	display->cdclk.hw.voltage_level = cdclk_config->voltage_level;
 }
 
 static void bxt_sanitize_cdclk(struct intel_display *display)
-- 
2.54.0


  parent reply	other threads:[~2026-08-26 13:41 UTC|newest]

Thread overview: 20+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2026-08-26 13:40 [PATCH v2 00/14] drm/i915/cdclk: cdclk pcode related fixes and refactoring Ville Syrjala
2026-08-26 13:40 ` [PATCH v2 01/14] drm/i915/cdclk: Don't bail if pcode post nofify fails Ville Syrjala
2026-08-26 13:40 ` [PATCH v2 02/14] drm/i915/cdclk: Pass CDCLK in MHz to pcode on DG2 Ville Syrjala
2026-08-26 13:40 ` [PATCH v2 03/14] drm/i915/cdclk: Do the DG2 CDCLK/pipe power well notify properly Ville Syrjala
2026-08-26 13:40 ` [PATCH v2 04/14] drm/i915/cdclk: Notify DG2 pcode about pipe power wells regardless of CDCLK Ville Syrjala
2026-08-26 13:58   ` sashiko-bot
2026-08-26 13:40 ` [PATCH v2 05/14] drm/i915/cdclk: Stop forcing voltage level to 3 all the time on DG2 Ville Syrjala
2026-08-26 13:40 ` Ville Syrjala [this message]
2026-08-26 13:40 ` [PATCH v2 07/14] drm/i915/dg2: s/intel_/dg2_/ for DG2 specific stuff Ville Syrjala
2026-08-26 13:52   ` sashiko-bot
2026-08-26 13:40 ` [PATCH v2 08/14] drm/i915/cdclk: Unify the pcode pre/post notify in bxt_set_cdclk() Ville Syrjala
2026-08-26 13:40 ` [PATCH v2 09/14] drm/i915/cdclk: Unify pcode related debugs Ville Syrjala
2026-08-26 13:40 ` [PATCH v2 10/14] drm/i915/cdclk: Extract bdw_cdclk_pcode_{pre, post}_notify() Ville Syrjala
2026-08-26 13:40 ` [PATCH v2 11/14] drm/i915/cdclk: Extract skl_cdclk_pcode_{pre, post}_notify() Ville Syrjala
2026-08-26 13:40 ` [PATCH v2 12/14] drm/i915/cdclk: Extract bxt_cdclk_pcode_{pre, post}_notify() Ville Syrjala
2026-08-26 13:40 ` [PATCH v2 13/14] drm/i915/cdclk: Introduce CDCLK .{pre, post}_notify() vfuncs Ville Syrjala
2026-08-26 13:40 ` [PATCH v2 14/14] drm/i915/cdclk: Hoist intel_cdclk_{pre, post}_notify() calls upwards Ville Syrjala
2026-08-26 13:48 ` ✓ CI.KUnit: success for drm/i915/cdclk: cdclk pcode related fixes and refactoring (rev2) Patchwork
2026-08-26 14:49 ` ✓ Xe.CI.BAT: " Patchwork
2026-08-26 18:28 ` ✓ Xe.CI.FULL: " Patchwork

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