From: sashiko-bot@kernel.org
To: "Michael J. Ruhl" <michael.j.ruhl@intel.com>
Cc: intel-xe@lists.freedesktop.org
Subject: Re: [PATCH v6 12/18] drm/xe/vsec: Refactor BattleMage PMT defines
Date: Fri, 04 Sep 2026 18:53:27 +0000 [thread overview]
Message-ID: <20260904185328.5EC681F00A3D@smtp.kernel.org> (raw)
In-Reply-To: <20260904182451.1164868-32-michael.j.ruhl@intel.com>
Thank you for your contribution! Sashiko AI review found 2 potential issue(s) to consider:
New issues:
- [High] Uninitialized `xe->pmt.base_offset` causes `xe_pmt_telem_read()` to read from the wrong MMIO address when accessed before `xe_vsec_init()` completes.
Pre-existing issues:
- [High] Crashlog control sysfs attributes perform direct MMIO reads/writes on Xe without waking the device, risking hardware hangs.
--
commit 584b4caa6a3ecc5f2e93919c5b1cb6ab09e0654c
Author: Michael J. Ruhl <michael.j.ruhl@intel.com>
drm/xe/vsec: Refactor BattleMage PMT defines
This commit refactors PMT definitions for Battlemage and introduces a
configurable base offset to support multiple platforms. It modifies the
PMT telemetry read path to use the new offset rather than a hardcoded macro.
> diff --git a/drivers/gpu/drm/xe/xe_vsec.c b/drivers/gpu/drm/xe/xe_vsec.c
> index a9baf0bfe572c..031c1c0ae5706 100644
> --- a/drivers/gpu/drm/xe/xe_vsec.c
> +++ b/drivers/gpu/drm/xe/xe_vsec.c
[ ... ]
> @@ -140,37 +201,79 @@ static int xe_guid_decode(u32 guid, int *index, u32 *offset)
[ ... ]
> int xe_pmt_telem_read(struct device *dev, u32 guid, u64 *data, loff_t user_offset,
> u32 count)
> {
> struct xe_device *xe = kdev_to_xe_device(dev);
> - void __iomem *telem_addr = xe->mmio.regs + BMG_TELEMETRY_OFFSET;
> + u32 cap_type = FIELD_GET(GUID_CAP_TYPE, guid);
> + void __iomem *telem_addr = xe->mmio.regs + xe->pmt.base_offset;
[Severity: High]
Does this read from the wrong MMIO address during early probe?
During device initialization in xe_device_probe(), xe_hwmon_register() is
called before xe_vsec_init(). The hwmon registration synchronously reads the
initial energy value through this call chain:
xe_hwmon_register()
xe_hwmon_energy_is_visible()
xe_hwmon_energy_get()
xe_pmt_telem_read()
Since xe->pmt.base_offset is not initialized until xe_vsec_init() is called
later in the probe sequence, it will still be 0 here. This would cause an
out-of-bounds MMIO read (xe->mmio.regs + 0 + offset) that misses the
SOC_BASE offset entirely, potentially triggering a machine check exception
or hanging the system.
[ ... ]
> @@ -210,6 +313,9 @@ void xe_vsec_init(struct xe_device *xe)
>
> switch (platform) {
> case XE_VSEC_BMG:
> + if (IS_SRIOV_VF(xe))
> + return;
> + xe->pmt.base_offset = BMG_TELEMETRY_OFFSET;
> info->priv_data = &xe_pmt_cb;
> break;
[Severity: High]
This is a pre-existing issue, but does the lack of .read_reg and .write_reg
callbacks in xe_pmt_cb risk unclocked MMIO accesses?
The crashlog.c driver implements sysfs attributes (e.g., clear, trigger)
that read and write PMT crashlog control registers. If the parent driver
doesn't provide .read_reg and .write_reg callbacks, pmt_crashlog_read_reg()
and pmt_crashlog_rmw() fall back to direct readl() and writel() on the
mapped MMIO region (entry->disc_table).
Since xe_pmt_cb only provides .read_telem, reading or writing these sysfs
attributes while the Xe device is suspended (D3cold) will trigger unclocked
MMIO accesses without waking the device via runtime PM. This can cause PCIe
Unsupported Request faults or system hangs.
Could .read_reg and .write_reg be implemented for Battlemage to ensure the
device is woken up during these accesses?
--
Sashiko AI review · https://sashiko.dev/#/patchset/20260904182451.1164868-20-michael.j.ruhl@intel.com?part=12
next prev parent reply other threads:[~2026-09-04 18:53 UTC|newest]
Thread overview: 29+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-09-04 18:24 [PATCH v6 00/18] Crescent Island PMT support Michael J. Ruhl
2026-09-04 18:24 ` [PATCH v6 01/18] platform/x86/intel/pmt: complete pcidev to device update Michael J. Ruhl
2026-09-04 18:45 ` sashiko-bot
2026-09-04 18:24 ` [PATCH v6 02/18] platform/x86/intel/pmt: refactor rmw with a return value Michael J. Ruhl
2026-09-04 18:24 ` [PATCH v6 03/18] platform/x86/intel/pmt: refactor rc " Michael J. Ruhl
2026-09-04 18:24 ` [PATCH v6 04/18] platform/x86/intel/pmt: Add register access callbacks Michael J. Ruhl
2026-09-04 18:24 ` [PATCH v6 05/18] platform/x86/intel/pmt: Do not remap when using callbacks Michael J. Ruhl
2026-09-04 18:42 ` sashiko-bot
2026-09-04 18:24 ` [PATCH v6 06/18] drm/xe/vsec: Do not register BMG PMT for VF Michael J. Ruhl
2026-09-04 18:24 ` [PATCH v6 07/18] drm/xe/vsec: Correct locking order Michael J. Ruhl
2026-09-04 18:24 ` [PATCH v6 08/18] drm/xe/vsec: Use correct pm state get Michael J. Ruhl
2026-09-04 18:24 ` [PATCH v6 09/18] drm/xe/vsec: Add DOC text for VSEC Michael J. Ruhl
2026-09-04 18:25 ` [PATCH v6 10/18] drm/xe/vsec: Support possible hotplug exit Michael J. Ruhl
2026-09-04 18:25 ` [PATCH v6 11/18] drm/xe/vsec: Support Crescent Island PMT Michael J. Ruhl
2026-09-04 18:25 ` [PATCH v6 12/18] drm/xe/vsec: Refactor BattleMage PMT defines Michael J. Ruhl
2026-09-04 18:53 ` sashiko-bot [this message]
2026-09-04 19:37 ` Ruhl, Michael J
2026-09-04 18:25 ` [PATCH v6 13/18] drm/xe/vsec: Crescent Island PMT decode Michael J. Ruhl
2026-09-04 18:50 ` sashiko-bot
2026-09-04 18:25 ` [PATCH v6 14/18] drm/xe/vsec: Crescent Island PMT callbacks Michael J. Ruhl
2026-09-04 18:51 ` sashiko-bot
2026-09-04 18:25 ` [PATCH v6 15/18] drm/xe/vsec: Support late bind fw information Michael J. Ruhl
2026-09-04 18:56 ` sashiko-bot
2026-09-04 18:25 ` [PATCH v6 16/18] drm/xe/vsec: Add PMT GUID internal access Michael J. Ruhl
2026-09-04 18:25 ` [PATCH v6 17/18] drm/xe/vsec: Update PMT " Michael J. Ruhl
2026-09-04 18:55 ` sashiko-bot
2026-09-04 18:25 ` [PATCH v6 18/18] drm/xe/vsec: Refactor platform check Michael J. Ruhl
2026-09-04 18:55 ` ✗ CI.checkpatch: warning for Crescent Island PMT support (rev8) Patchwork
2026-09-04 18:56 ` ✗ CI.KUnit: failure " Patchwork
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