Re: [PATCH v6 07/24] drm/xe: Update scheduler job layer to support PT jobs

[sashiko-bot@kernel.org]

Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [Critical] PT jobs consume the TLB flush seqno without executing a hardware TLB flush, potentially causing subsequent GPU jobs to run with stale page tables.
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commit 3d489d315c4f278dad409a11a04984a2139095c2
Author: Matthew Brost <matthew.brost@intel.com>

drm/xe: Update scheduler job layer to support PT jobs

Update the scheduler job layer to support PT jobs which execute entirely
on the CPU without requiring LRC fences or a batch address. Repurpose
LRC fence storage for PT-job arguments.

Link: https://patch.msgid.link/20260228013501.106680-8-matthew.brost@intel.com

> diff --git a/drivers/gpu/drm/xe/xe_sched_job.c b/drivers/gpu/drm/xe/xe_sched_job.c
> --- a/drivers/gpu/drm/xe/xe_sched_job.c
> +++ b/drivers/gpu/drm/xe/xe_sched_job.c
[ ... ]
> @@ -266,6 +293,9 @@ void xe_sched_job_arm(struct xe_sched_job *job)
>  		job->ring_ops_flush_tlb = true;
>  	}
>  
> +	if (job->is_pt_job)
> +		goto arm;
> +
>  	/* Arm the pre-allocated fences */
>  	for (i = 0; i < q->width; prev = fence, ++i) {

[Severity: Critical]
Will this cause subsequent GPU jobs to run with stale page tables?

Looking at xe_sched_job_arm() in drivers/gpu/drm/xe/xe_sched_job.c, the code
just above this addition checks if a TLB flush is needed and updates
q->tlb_flush_seqno:

        if (vm && !xe_sched_job_is_migration(q) && !xe_vm_in_lr_mode(vm) &&
            (vm->batch_invalidate_tlb || vm->tlb_flush_seqno != q->tlb_flush_seqno)) {
                xe_vm_assert_held(vm);
                q->tlb_flush_seqno = vm->tlb_flush_seqno;
                job->ring_ops_flush_tlb = true;
        }

If the current job is a PT job, the new check jumps to the arm label,
skipping the hardware ring submission where the flush would normally execute.
Because q->tlb_flush_seqno was already updated, when a subsequent GPU payload
job is submitted to this same queue, it will see the seqnos match and skip
flushing. This could allow the GPU to access memory using a stale TLB.

Should the job->is_pt_job check precede the TLB invalidation check to prevent
the CPU-only PT job from stealing the flush notification?

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Sashiko AI review · https://sashiko.dev/#/patchset/20260904211613.3934307-1-matthew.brost@intel.com?part=7