From: sashiko-bot@kernel.org
To: "Karthik Poosa" <karthik.poosa@intel.com>
Cc: intel-xe@lists.freedesktop.org
Subject: Re: [PATCH v5 01/13] drm/xe/hwmon: Handle pcode read failures of xe_hwmon_pcode_rmw_power_limit
Date: Thu, 24 Sep 2026 11:23:32 +0000 [thread overview]
Message-ID: <20260924112332.E27421F000FF@smtp.kernel.org> (raw)
In-Reply-To: <20260924111156.2628915-2-karthik.poosa@intel.com>
Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [Medium] sysfs: returning 0 on error in store callback causes userspace infinite loop
--
commit fdbe8069cbe324980fc35768d7993da6a046117b
Author: Karthik Poosa <karthik.poosa@intel.com>
drm/xe/hwmon: Handle pcode read failures of xe_hwmon_pcode_rmw_power_limit
This commit adds error handling for pcode read failures in
xe_hwmon_pcode_rmw_power_limit() and checks the returned error in callers
to prevent updating power limit settings with invalid data.
> diff --git a/drivers/gpu/drm/xe/xe_hwmon.c b/drivers/gpu/drm/xe/xe_hwmon.c
> --- a/drivers/gpu/drm/xe/xe_hwmon.c
> +++ b/drivers/gpu/drm/xe/xe_hwmon.c
[ ... ]
> @@ -679,11 +683,13 @@ xe_hwmon_power_max_interval_store(struct device *dev, struct device_attribute *a
>
> mutex_lock(&hwmon->hwmon_lock);
>
> - if (hwmon->xe->info.has_mbx_power_limits)
> - xe_hwmon_pcode_rmw_power_limit(hwmon, power_attr, channel, PWR_LIM_TIME, rxy);
> - else
> + if (hwmon->xe->info.has_mbx_power_limits) {
> + if (xe_hwmon_pcode_rmw_power_limit(hwmon, power_attr, channel, PWR_LIM_TIME, rxy))
> + count = 0;
[Severity: Medium]
In xe_hwmon_power_max_interval_store() within drivers/gpu/drm/xe/xe_hwmon.c,
will setting count to 0 here cause userspace tools to enter an infinite loop?
When a sysfs store callback returns 0 instead of a negative error code, it
indicates to the virtual file system that 0 bytes were written and swallows
the error. Standard userspace utilities (like echo or dd) often treat a
0-byte write as a short write and retry infinitely.
If an administrative user or script writes to the sysfs attribute and the
underlying pcode mailbox operation fails, could this cause an infinite loop
that consumes maximum processor time while simultaneously flooding the kernel
log with error messages?
Should this return the negative error code from
xe_hwmon_pcode_rmw_power_limit() instead of setting count to 0?
> + } else {
> r = xe_mmio_rmw32(mmio, xe_hwmon_get_reg(hwmon, REG_PKG_RAPL_LIMIT, channel),
> PWR_LIM_TIME, rxy);
> + }
>
> mutex_unlock(&hwmon->hwmon_lock);
--
Sashiko AI review · https://sashiko.dev/#/patchset/20260924111156.2628915-1-karthik.poosa@intel.com?part=1
next prev parent reply other threads:[~2026-09-24 11:23 UTC|newest]
Thread overview: 26+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-09-24 11:11 [PATCH v5 00/13] drm/xe/hwmon: Update hwmon thermal mailbox Karthik Poosa
2026-09-24 11:11 ` [PATCH v5 01/13] drm/xe/hwmon: Handle pcode read failures of xe_hwmon_pcode_rmw_power_limit Karthik Poosa
2026-09-24 11:23 ` sashiko-bot [this message]
2026-09-24 14:26 ` Poosa, Karthik
2026-09-24 11:11 ` [PATCH v5 02/13] drm/xe/hwmon: Decode mailbox temperature as sign-magnitude Karthik Poosa
2026-09-24 11:11 ` [PATCH v5 03/13] drm/xe/hwmon: Fix memory controller thermal data handling Karthik Poosa
2026-09-24 11:24 ` sashiko-bot
2026-09-24 11:11 ` [PATCH v5 04/13] drm/xe/hwmon: Add helpers to validate thermal sensor readings Karthik Poosa
2026-09-24 11:11 ` [PATCH v5 05/13] drm/xe/hwmon: Handle unavailable memory controller sensors Karthik Poosa
2026-09-24 11:11 ` [PATCH v5 06/13] drm/xe/hwmon: Detect unavailable PCIe thermal sensors Karthik Poosa
2026-09-24 11:11 ` [PATCH v5 07/13] drm/xe/hwmon: Consolidate temperature sensor availability checks Karthik Poosa
2026-09-24 11:24 ` sashiko-bot
2026-09-24 13:16 ` Poosa, Karthik
2026-09-24 11:11 ` [PATCH v5 08/13] drm/xe/hwmon: Cache temperature availability to reduce probe time Karthik Poosa
2026-09-24 11:11 ` [PATCH v5 09/13] drm/xe/hwmon: Add platform-aware VRAM thermal channel support Karthik Poosa
2026-09-24 11:24 ` sashiko-bot
2026-09-24 13:40 ` Poosa, Karthik
2026-09-24 11:11 ` [PATCH v5 10/13] drm/xe/hwmon: use CRI-specific package and VRAM temperature registers Karthik Poosa
2026-09-24 11:27 ` sashiko-bot
2026-09-24 13:41 ` Poosa, Karthik
2026-09-24 11:11 ` [PATCH v5 11/13] drm/xe/hwmon: Decode CRI temperature registers as IEEE-754 Karthik Poosa
2026-09-24 11:27 ` sashiko-bot
2026-09-24 11:11 ` [PATCH v5 12/13] drm/xe/hwmon: Update memory controller temperature offset for CRI Karthik Poosa
2026-09-24 11:11 ` [PATCH v5 13/13] drm/xe/hwmon: Update PCIE temperature sensor " Karthik Poosa
2026-09-24 11:40 ` ✓ CI.KUnit: success for drm/xe/hwmon: Update hwmon thermal mailbox (rev2) Patchwork
2026-09-24 12:56 ` ✓ Xe.CI.BAT: " Patchwork
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