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From: sashiko-bot@kernel.org
To: "Karthik Poosa" <karthik.poosa@intel.com>
Cc: intel-xe@lists.freedesktop.org
Subject: Re: [PATCH v5 07/13] drm/xe/hwmon: Consolidate temperature sensor availability checks
Date: Thu, 24 Sep 2026 11:24:34 +0000	[thread overview]
Message-ID: <20260924112434.E374A1F000FF@smtp.kernel.org> (raw)
In-Reply-To: <20260924111156.2628915-8-karthik.poosa@intel.com>

Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [Medium] hwmon: initialization race causes permanent attribute loss on slow sensors
--

commit c02db655e6dabb60e61a8acbe0daf64a353e248d
Author: Karthik Poosa <karthik.poosa@intel.com>
Subject: drm/xe/hwmon: Consolidate temperature sensor availability checks

This commit replaces is_vram_ch_available() with a generalized 
is_temp_available() to validate multiple sensor types. It uses this new 
helper during hwmon registration to prevent exposing sysfs attributes for 
sensors that are not present.

> diff --git a/drivers/gpu/drm/xe/xe_hwmon.c b/drivers/gpu/drm/xe/xe_hwmon.c
> index 7bb7a5f402d1e..d62f95a1912f3 100644
> --- a/drivers/gpu/drm/xe/xe_hwmon.c
> +++ b/drivers/gpu/drm/xe/xe_hwmon.c
[ ... ]
> -static inline bool is_vram_ch_available(struct xe_hwmon *hwmon, int channel)
> +static bool is_temp_available(struct xe_hwmon *hwmon, int channel)
>  {
>  	struct xe_mmio *mmio = xe_root_tile_mmio(hwmon->xe);
> -	int vram_id = channel - CHANNEL_VRAM_N;
> -	struct xe_reg vram_reg;
> +	struct xe_reg reg;
> +	u32 reg_val;
>  
> -	vram_reg = xe_hwmon_get_reg(hwmon, REG_TEMP, channel);
> -	if (!xe_reg_is_valid(vram_reg) || !xe_mmio_read32(mmio, vram_reg))
> -		return false;
> +	switch (channel) {
> +	case CHANNEL_PKG:
> +	case CHANNEL_VRAM:
> +	case CHANNEL_VRAM_N...CHANNEL_VRAM_N_MAX:
> +		reg = xe_hwmon_get_reg(hwmon, REG_TEMP, channel);
> +		if (!xe_reg_is_valid(reg))
> +			return false;
> +
> +		reg_val = xe_mmio_read32(mmio, reg);
> +		if (!mmio_temp_valid(hwmon, reg_val)) {
> +			drm_dbg(&hwmon->xe->drm,
> +				"channel %d temperature unavailable, val 0x%x\n", channel, reg_val);
> +			return false;
> +		}

[Severity: Medium]
Could this cause functional sensors to be permanently hidden if the firmware
is slow to initialize them?

During hwmon registration, is_temp_available() performs a live MMIO read to
determine attribute visibility. If the firmware hasn't populated a valid
temperature yet at the exact moment of device probe (for instance, returning
0 or U32_MAX), mmio_temp_valid() will return false.

Since this determines sysfs attribute visibility, doesn't this create a
silent failure where perfectly functional PKG sensors disappear intermittently
depending on boot timing?

> +
> +		if (channel >= CHANNEL_VRAM_N)
> +			sprintf(hwmon->temp.vram_label[channel - CHANNEL_VRAM_N],
> +				"vram_ch_%d", channel - CHANNEL_VRAM_N);
>  
> -	/* Create label only for available vram channel */
> -	sprintf(hwmon->temp.vram_label[vram_id], "vram_ch_%d", vram_id);
> -	return true;
> +		return true;
> +	case CHANNEL_MCTRL:
> +		return hwmon->temp.count && !get_mc_temp(hwmon, NULL);
> +	case CHANNEL_PCIE:
> +		return hwmon->temp.count && !get_pcie_temp(hwmon, NULL);

[Severity: Medium]
Similarly, does this live PCODE mailbox polling risk permanently hiding the
Memory Controller and PCIe temperature sensors?

If PCODE is slow to respond during device probe, get_mc_temp() and
get_pcie_temp() might fail or return invalid data. Because this check
replaces static capability checks (such as hwmon->temp.count) with live
sensor data, it seems to introduce a race condition where a temporary
initialization delay results in permanent attribute loss.

> +	default:
> +		return false;
> +	}
>  }

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20260924111156.2628915-1-karthik.poosa@intel.com?part=7

  reply	other threads:[~2026-09-24 11:24 UTC|newest]

Thread overview: 26+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2026-09-24 11:11 [PATCH v5 00/13] drm/xe/hwmon: Update hwmon thermal mailbox Karthik Poosa
2026-09-24 11:11 ` [PATCH v5 01/13] drm/xe/hwmon: Handle pcode read failures of xe_hwmon_pcode_rmw_power_limit Karthik Poosa
2026-09-24 11:23   ` sashiko-bot
2026-09-24 14:26     ` Poosa, Karthik
2026-09-24 11:11 ` [PATCH v5 02/13] drm/xe/hwmon: Decode mailbox temperature as sign-magnitude Karthik Poosa
2026-09-24 11:11 ` [PATCH v5 03/13] drm/xe/hwmon: Fix memory controller thermal data handling Karthik Poosa
2026-09-24 11:24   ` sashiko-bot
2026-09-24 11:11 ` [PATCH v5 04/13] drm/xe/hwmon: Add helpers to validate thermal sensor readings Karthik Poosa
2026-09-24 11:11 ` [PATCH v5 05/13] drm/xe/hwmon: Handle unavailable memory controller sensors Karthik Poosa
2026-09-24 11:11 ` [PATCH v5 06/13] drm/xe/hwmon: Detect unavailable PCIe thermal sensors Karthik Poosa
2026-09-24 11:11 ` [PATCH v5 07/13] drm/xe/hwmon: Consolidate temperature sensor availability checks Karthik Poosa
2026-09-24 11:24   ` sashiko-bot [this message]
2026-09-24 13:16     ` Poosa, Karthik
2026-09-24 11:11 ` [PATCH v5 08/13] drm/xe/hwmon: Cache temperature availability to reduce probe time Karthik Poosa
2026-09-24 11:11 ` [PATCH v5 09/13] drm/xe/hwmon: Add platform-aware VRAM thermal channel support Karthik Poosa
2026-09-24 11:24   ` sashiko-bot
2026-09-24 13:40     ` Poosa, Karthik
2026-09-24 11:11 ` [PATCH v5 10/13] drm/xe/hwmon: use CRI-specific package and VRAM temperature registers Karthik Poosa
2026-09-24 11:27   ` sashiko-bot
2026-09-24 13:41     ` Poosa, Karthik
2026-09-24 11:11 ` [PATCH v5 11/13] drm/xe/hwmon: Decode CRI temperature registers as IEEE-754 Karthik Poosa
2026-09-24 11:27   ` sashiko-bot
2026-09-24 11:11 ` [PATCH v5 12/13] drm/xe/hwmon: Update memory controller temperature offset for CRI Karthik Poosa
2026-09-24 11:11 ` [PATCH v5 13/13] drm/xe/hwmon: Update PCIE temperature sensor " Karthik Poosa
2026-09-24 11:40 ` ✓ CI.KUnit: success for drm/xe/hwmon: Update hwmon thermal mailbox (rev2) Patchwork
2026-09-24 12:56 ` ✓ Xe.CI.BAT: " Patchwork

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