[PATCH v5 00/13] drm/xe/hwmon: Update hwmon thermal mailbox

[PATCH v5 00/13] drm/xe/hwmon: Update hwmon thermal mailbox

[Karthik Poosa]

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This series adds CRI-specific temperature sensor handling to the Xe
hwmon implementation and fixes couple of hwmon issues.

CRI platforms may report unavailable temperature sensors and support
a variable number of VRAM temperature channels depending on platform
configuration. This series adds the required sensor presence checks and
uses platform-reported thermal configuration data to expose only valid
temperature-related hwmon attributes.

The series also corrects the telemetry group selection used for memory
controller temperature reporting.

v2:
 - Address review comments from Sashiko, Badal and Raag.
 - Enable IEEE 754 temperature decoding for MMIO temperature registers.
  - Split sensor validity check into mailbox vs MMIO handling; add
    is_temp_available() / is_temp_is_visible().
 - Temporarily disable memory controller and PCIe temperatures on CRI.

v3:
  - Detect unavailable temperature sensors: rephrase a debug log.
  - Decode mailbox temperatures as 8-bit sign-magnitude values instead of
    s8.
  - Use VRAM temperature sensor count from thermal config on CRI: address
    review comments from sashiko-bot@kernel.org and Rodrigo.
  - Decode CRI temperature registers as IEEE-754: reject temperatures that
    overflow long on 32-bit systems.

v4:
  - Address review comments and issues report from Rodrigo and
    sashiko-bot@kernel.org.
  - Decode mailbox temperatures as 8-bit sign-magnitude values.
  - Cache sensor availability during registration.
  - Enable memory controller and pcie sensors for CRI.
  - Derive the VRAM channel count from the CRI MSU enable mask.
  - Use CRI-specific package and VRAM temperature registers.
  - Handle the CRI memory controller and pcie sensor offsets as per CRI.

v5:
 - Remove the unintended IGT prefix from the patch titles.

Karthik Poosa (13):
  drm/xe/hwmon: Handle pcode read failures of
    xe_hwmon_pcode_rmw_power_limit
  drm/xe/hwmon: Decode mailbox temperature as sign-magnitude
  drm/xe/hwmon: Fix memory controller thermal data handling
  drm/xe/hwmon: Add helpers to validate thermal sensor readings
  drm/xe/hwmon: Handle unavailable memory controller sensors
  drm/xe/hwmon: Detect unavailable PCIe thermal sensors
  drm/xe/hwmon: Consolidate temperature sensor availability checks
  drm/xe/hwmon: Cache temperature availability to reduce probe time
  drm/xe/hwmon: Add platform-aware VRAM thermal channel support
  drm/xe/hwmon: use CRI-specific package and VRAM temperature registers
  drm/xe/hwmon: Decode CRI temperature registers as IEEE-754
  drm/xe/hwmon: Update memory controller temperature offset for CRI
  drm/xe/hwmon: Update PCIE temperature sensor offset for CRI

 drivers/gpu/drm/xe/regs/xe_pcode_regs.h |   3 +
 drivers/gpu/drm/xe/xe_device_types.h    |   4 +
 drivers/gpu/drm/xe/xe_hwmon.c           | 452 ++++++++++++++++++++----
 drivers/gpu/drm/xe/xe_pci.c             |   4 +
 drivers/gpu/drm/xe/xe_pci_types.h       |   2 +
 5 files changed, 393 insertions(+), 72 deletions(-)

-- 
2.25.1

[PATCH v5 01/13] drm/xe/hwmon: Handle pcode read failures of xe_hwmon_pcode_rmw_power_limit

[Karthik Poosa]

Return early when the pcode read operation fails in
xe_hwmon_pcode_rmw_power_limit() and check the returned error in
callers to avoid updating power limit settings with invalid data.

Fixes: 8aa7306631f0 ("drm/xe/hwmon: Fix xe_hwmon_power_max_write")
Signed-off-by: Karthik Poosa <karthik.poosa@intel.com>
---
 drivers/gpu/drm/xe/xe_hwmon.c | 18 ++++++++++++------
 1 file changed, 12 insertions(+), 6 deletions(-)

diff --git a/drivers/gpu/drm/xe/xe_hwmon.c b/drivers/gpu/drm/xe/xe_hwmon.c
index 5edeac961ec3..514573f172eb 100644
--- a/drivers/gpu/drm/xe/xe_hwmon.c
+++ b/drivers/gpu/drm/xe/xe_hwmon.c
@@ -232,9 +232,11 @@ static int xe_hwmon_pcode_rmw_power_limit(const struct xe_hwmon *hwmon, u32 attr
 						  READ_PSYSGPU_POWER_LIMIT :
 						  READ_PACKAGE_POWER_LIMIT,
 						  prepare_power_limit_param2(hwmon)), &val0, &val1);
-	if (ret)
-		drm_dbg(&hwmon->xe->drm, "read failed ch %d val0 0x%08x, val1 0x%08x, ret %d\n",
+	if (ret) {
+		drm_err(&hwmon->xe->drm, "read failed ch %d val0 0x%08x, val1 0x%08x, ret %d\n",
 			channel, val0, val1, ret);
+		return ret;
+	}
 
 	if (attr == PL1_HWMON_ATTR)
 		val0 = (val0 & ~clr) | set;
@@ -394,7 +396,9 @@ static int xe_hwmon_power_max_write(struct xe_hwmon *hwmon, u32 attr, int channe
 		if (hwmon->xe->info.has_mbx_power_limits) {
 			drm_dbg(&hwmon->xe->drm, "disabling %s on channel %d\n",
 				PWR_ATTR_TO_STR(attr), channel);
-			xe_hwmon_pcode_rmw_power_limit(hwmon, attr, channel, PWR_LIM_EN, 0);
+			ret = xe_hwmon_pcode_rmw_power_limit(hwmon, attr, channel, PWR_LIM_EN, 0);
+			if (ret)
+				goto unlock;
 			xe_hwmon_pcode_read_power_limit(hwmon, attr, channel, &reg_val);
 		} else {
 			reg_val = xe_mmio_rmw32(mmio, rapl_limit, PWR_LIM_EN, 0);
@@ -679,11 +683,13 @@ xe_hwmon_power_max_interval_store(struct device *dev, struct device_attribute *a
 
 	mutex_lock(&hwmon->hwmon_lock);
 
-	if (hwmon->xe->info.has_mbx_power_limits)
-		xe_hwmon_pcode_rmw_power_limit(hwmon, power_attr, channel, PWR_LIM_TIME, rxy);
-	else
+	if (hwmon->xe->info.has_mbx_power_limits) {
+		if (xe_hwmon_pcode_rmw_power_limit(hwmon, power_attr, channel, PWR_LIM_TIME, rxy))
+			count = 0;
+	} else {
 		r = xe_mmio_rmw32(mmio, xe_hwmon_get_reg(hwmon, REG_PKG_RAPL_LIMIT, channel),
 				  PWR_LIM_TIME, rxy);
+	}
 
 	mutex_unlock(&hwmon->hwmon_lock);
 
-- 
2.25.1

Re: [PATCH v5 01/13] drm/xe/hwmon: Handle pcode read failures of xe_hwmon_pcode_rmw_power_limit

[sashiko-bot]

Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [Medium] sysfs: returning 0 on error in store callback causes userspace infinite loop
--

commit fdbe8069cbe324980fc35768d7993da6a046117b
Author: Karthik Poosa <karthik.poosa@intel.com>
drm/xe/hwmon: Handle pcode read failures of xe_hwmon_pcode_rmw_power_limit

This commit adds error handling for pcode read failures in
xe_hwmon_pcode_rmw_power_limit() and checks the returned error in callers
to prevent updating power limit settings with invalid data.

> diff --git a/drivers/gpu/drm/xe/xe_hwmon.c b/drivers/gpu/drm/xe/xe_hwmon.c
> --- a/drivers/gpu/drm/xe/xe_hwmon.c
> +++ b/drivers/gpu/drm/xe/xe_hwmon.c
[ ... ]
> @@ -679,11 +683,13 @@ xe_hwmon_power_max_interval_store(struct device *dev, struct device_attribute *a
>  
>  	mutex_lock(&hwmon->hwmon_lock);
>  
> -	if (hwmon->xe->info.has_mbx_power_limits)
> -		xe_hwmon_pcode_rmw_power_limit(hwmon, power_attr, channel, PWR_LIM_TIME, rxy);
> -	else
> +	if (hwmon->xe->info.has_mbx_power_limits) {
> +		if (xe_hwmon_pcode_rmw_power_limit(hwmon, power_attr, channel, PWR_LIM_TIME, rxy))
> +			count = 0;

[Severity: Medium]
In xe_hwmon_power_max_interval_store() within drivers/gpu/drm/xe/xe_hwmon.c,
will setting count to 0 here cause userspace tools to enter an infinite loop?

When a sysfs store callback returns 0 instead of a negative error code, it
indicates to the virtual file system that 0 bytes were written and swallows
the error. Standard userspace utilities (like echo or dd) often treat a
0-byte write as a short write and retry infinitely.

If an administrative user or script writes to the sysfs attribute and the
underlying pcode mailbox operation fails, could this cause an infinite loop
that consumes maximum processor time while simultaneously flooding the kernel
log with error messages?

Should this return the negative error code from
xe_hwmon_pcode_rmw_power_limit() instead of setting count to 0?

> +	} else {
>  		r = xe_mmio_rmw32(mmio, xe_hwmon_get_reg(hwmon, REG_PKG_RAPL_LIMIT, channel),
>  				  PWR_LIM_TIME, rxy);
> +	}
>  
>  	mutex_unlock(&hwmon->hwmon_lock);

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20260924111156.2628915-1-karthik.poosa@intel.com?part=1

Re: [PATCH v5 01/13] drm/xe/hwmon: Handle pcode read failures of xe_hwmon_pcode_rmw_power_limit

[Poosa, Karthik]

On 24-09-2026 16:53, sashiko-bot@kernel.org wrote:
> Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
> - [Medium] sysfs: returning 0 on error in store callback causes userspace infinite loop
> --
>
> commit fdbe8069cbe324980fc35768d7993da6a046117b
> Author: Karthik Poosa <karthik.poosa@intel.com>
> drm/xe/hwmon: Handle pcode read failures of xe_hwmon_pcode_rmw_power_limit
>
> This commit adds error handling for pcode read failures in
> xe_hwmon_pcode_rmw_power_limit() and checks the returned error in callers
> to prevent updating power limit settings with invalid data.
>
>> diff --git a/drivers/gpu/drm/xe/xe_hwmon.c b/drivers/gpu/drm/xe/xe_hwmon.c
>> --- a/drivers/gpu/drm/xe/xe_hwmon.c
>> +++ b/drivers/gpu/drm/xe/xe_hwmon.c
> [ ... ]
>> @@ -679,11 +683,13 @@ xe_hwmon_power_max_interval_store(struct device *dev, struct device_attribute *a
>>   
>>   	mutex_lock(&hwmon->hwmon_lock);
>>   
>> -	if (hwmon->xe->info.has_mbx_power_limits)
>> -		xe_hwmon_pcode_rmw_power_limit(hwmon, power_attr, channel, PWR_LIM_TIME, rxy);
>> -	else
>> +	if (hwmon->xe->info.has_mbx_power_limits) {
>> +		if (xe_hwmon_pcode_rmw_power_limit(hwmon, power_attr, channel, PWR_LIM_TIME, rxy))
>> +			count = 0;
> [Severity: Medium]
> In xe_hwmon_power_max_interval_store() within drivers/gpu/drm/xe/xe_hwmon.c,
> will setting count to 0 here cause userspace tools to enter an infinite loop?
>
> When a sysfs store callback returns 0 instead of a negative error code, it
> indicates to the virtual file system that 0 bytes were written and swallows
> the error. Standard userspace utilities (like echo or dd) often treat a
> 0-byte write as a short write and retry infinitely.
>
> If an administrative user or script writes to the sysfs attribute and the
> underlying pcode mailbox operation fails, could this cause an infinite loop
> that consumes maximum processor time while simultaneously flooding the kernel
> log with error messages?
>
> Should this return the negative error code from
> xe_hwmon_pcode_rmw_power_limit() instead of setting count to 0?
I shall return -EIO instead of 0 here in next revision.
>
>> +	} else {
>>   		r = xe_mmio_rmw32(mmio, xe_hwmon_get_reg(hwmon, REG_PKG_RAPL_LIMIT, channel),
>>   				  PWR_LIM_TIME, rxy);
>> +	}
>>   
>>   	mutex_unlock(&hwmon->hwmon_lock);

[PATCH v5 02/13] drm/xe/hwmon: Decode mailbox temperature as sign-magnitude

[Karthik Poosa]

The mailbox temperature is an 8-bit sign-magnitude value (bit 7 sign,
bits 6:0 magnitude, range -127..127), not two's-complement. Casting the
raw byte to s8 decodes negative readings incorrectly.

Add mbx_temp_decode(), store the raw byte as u8, and use it in
get_mc_temp() and get_pcie_temp() so temperatures are decoded correctly.

Fixes: 3a0cb885e111 ("drm/xe/hwmon: Expose memory controller temperature")
Signed-off-by: Karthik Poosa <karthik.poosa@intel.com>
---
 drivers/gpu/drm/xe/xe_hwmon.c | 20 ++++++++++++++++----
 1 file changed, 16 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/xe/xe_hwmon.c b/drivers/gpu/drm/xe/xe_hwmon.c
index 514573f172eb..d82da9be9e5b 100644
--- a/drivers/gpu/drm/xe/xe_hwmon.c
+++ b/drivers/gpu/drm/xe/xe_hwmon.c
@@ -104,6 +104,10 @@ enum sensor_attr_power {
 /* Index of memory controller in READ_THERMAL_DATA output */
 #define TEMP_INDEX_MCTRL	2
 
+/* Mailbox temperature is sign-magnitude: bit 7 sign, bits 6:0 magnitude. */
+#define TEMP_MBX_SIGN		BIT(7)
+#define TEMP_MBX_MAG		GENMASK(6, 0)
+
 /* Maximum characters in hwmon label name */
 #define MAX_LABEL_SIZE		16
 
@@ -139,8 +143,8 @@ struct xe_hwmon_thermal_info {
 	};
 	/** @count: no of temperature sensors available for the platform */
 	u8 count;
-	/** @value: signed value from each sensor */
-	s8 value[U8_MAX];
+	/** @value: per-sensor raw mailbox temperature; bit7=sign, bits6:0=magnitude */
+	u8 value[U8_MAX];
 	/** @vram_label: vram label names */
 	char vram_label[MAX_VRAM_CHANNELS][MAX_LABEL_SIZE];
 };
@@ -814,6 +818,14 @@ static int xe_hwmon_pcode_read_thermal_info(struct xe_hwmon *hwmon)
 	return ret;
 }
 
+/* Decode an 8-bit sign-magnitude mailbox temperature to degrees Celsius. */
+static int mbx_temp_decode(u8 value)
+{
+	int temp = value & TEMP_MBX_MAG;
+
+	return (value & TEMP_MBX_SIGN) ? -temp : temp;
+}
+
 static int get_mc_temp(struct xe_hwmon *hwmon, long *val)
 {
 	struct xe_tile *root_tile = xe_device_get_root_tile(hwmon->xe);
@@ -830,7 +842,7 @@ static int get_mc_temp(struct xe_hwmon *hwmon, long *val)
 	}
 
 	for (i = TEMP_INDEX_MCTRL; i < hwmon->temp.count - 1; i++)
-		average += hwmon->temp.value[i];
+		average += mbx_temp_decode(hwmon->temp.value[i]);
 
 	average /= (hwmon->temp.count - TEMP_INDEX_MCTRL - 1);
 	*val = average * MILLIDEGREE_PER_DEGREE;
@@ -853,7 +865,7 @@ static int get_pcie_temp(struct xe_hwmon *hwmon, long *val)
 		data = REG_FIELD_GET(PCIE_SENSOR_MASK, data);
 
 	data = REG_FIELD_GET(TEMP_MASK, data);
-	*val = (s8)data * MILLIDEGREE_PER_DEGREE;
+	*val = mbx_temp_decode(data) * MILLIDEGREE_PER_DEGREE;
 
 	return 0;
 }
-- 
2.25.1

[PATCH v5 03/13] drm/xe/hwmon: Fix memory controller thermal data handling

[Karthik Poosa]

Read all required thermal groups in get_mc_temp() and use an aligned
u32 buffer for PCODE accesses to avoid unaligned memory accesses and
ensure correct MC temperature reporting.

Signed-off-by: Karthik Poosa <karthik.poosa@intel.com>
Fixes: 3a0cb885e111 ("drm/xe/hwmon: Expose memory controller temperature")
Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
---
 drivers/gpu/drm/xe/xe_hwmon.c | 16 ++++++++++------
 1 file changed, 10 insertions(+), 6 deletions(-)

diff --git a/drivers/gpu/drm/xe/xe_hwmon.c b/drivers/gpu/drm/xe/xe_hwmon.c
index d82da9be9e5b..658b6902af7f 100644
--- a/drivers/gpu/drm/xe/xe_hwmon.c
+++ b/drivers/gpu/drm/xe/xe_hwmon.c
@@ -143,8 +143,12 @@ struct xe_hwmon_thermal_info {
 	};
 	/** @count: no of temperature sensors available for the platform */
 	u8 count;
-	/** @value: per-sensor raw mailbox temperature; bit7=sign, bits6:0=magnitude */
-	u8 value[U8_MAX];
+	union {
+		/** @vavlue: per-sensor raw mailbox temperature; bit7=sign, bits6:0=magnitude */
+		u8 value[U8_MAX + 1];
+		/** @dword: sensor values as dwords, u32-aligned for pcode reads */
+		u32 dword[DIV_ROUND_UP(U8_MAX + 1, sizeof(u32))];
+	};
 	/** @vram_label: vram label names */
 	char vram_label[MAX_VRAM_CHANNELS][MAX_LABEL_SIZE];
 };
@@ -829,16 +833,16 @@ static int mbx_temp_decode(u8 value)
 static int get_mc_temp(struct xe_hwmon *hwmon, long *val)
 {
 	struct xe_tile *root_tile = xe_device_get_root_tile(hwmon->xe);
-	u32 *dword = (u32 *)hwmon->temp.value;
 	s32 average = 0;
 	int ret, i;
 
-	for (i = 0; i < DIV_ROUND_UP(TEMP_LIMIT_MAX, sizeof(u32)); i++) {
+	for (i = 0; i < DIV_ROUND_UP(hwmon->temp.count, sizeof(u32)); i++) {
 		ret = xe_pcode_read(root_tile, PCODE_MBOX(PCODE_THERMAL_INFO, READ_THERMAL_DATA, i),
-				    (dword + i), NULL);
+				    &hwmon->temp.dword[i], NULL);
 		if (ret)
 			return ret;
-		drm_dbg(&hwmon->xe->drm, "thermal data for group %d val 0x%x\n", i, dword[i]);
+		drm_dbg(&hwmon->xe->drm, "thermal data for group %d val 0x%x\n", i,
+			hwmon->temp.dword[i]);
 	}
 
 	for (i = TEMP_INDEX_MCTRL; i < hwmon->temp.count - 1; i++)
-- 
2.25.1

Re: [PATCH v5 03/13] drm/xe/hwmon: Fix memory controller thermal data handling

[sashiko-bot]

Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [Low] xe_hwmon: kernel-doc mismatch due to typo '@vavlue'
--

commit af26cf662405440ebacf68b7cf48c30a800a4da6
Author: Karthik Poosa <karthik.poosa@intel.com>

drm/xe/hwmon: Fix memory controller thermal data handling

This commit fixes memory controller thermal data handling by reading all
required thermal groups in get_mc_temp() and using a u32-aligned buffer for
PCODE accesses to avoid unaligned memory access issues.

> diff --git a/drivers/gpu/drm/xe/xe_hwmon.c b/drivers/gpu/drm/xe/xe_hwmon.c
> --- a/drivers/gpu/drm/xe/xe_hwmon.c
> +++ b/drivers/gpu/drm/xe/xe_hwmon.c
> @@ -143,8 +143,12 @@ struct xe_hwmon_thermal_info {
>  	};
>  	/** @count: no of temperature sensors available for the platform */
>  	u8 count;
> -	/** @value: per-sensor raw mailbox temperature; bit7=sign, bits6:0=magnitude */
> -	u8 value[U8_MAX];
> +	union {
> +		/** @vavlue: per-sensor raw mailbox temperature; bit7=sign, bits6:0=magnitude */

[Severity: Low]
This isn't a bug, but is there a typo in the kernel-doc here? It looks like
it should be @value instead of @vavlue to match the union member name.

> +		u8 value[U8_MAX + 1];
> +		/** @dword: sensor values as dwords, u32-aligned for pcode reads */
> +		u32 dword[DIV_ROUND_UP(U8_MAX + 1, sizeof(u32))];
> +	};
>  	/** @vram_label: vram label names */
>  	char vram_label[MAX_VRAM_CHANNELS][MAX_LABEL_SIZE];
>  };

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20260924111156.2628915-1-karthik.poosa@intel.com?part=3

[PATCH v5 04/13] drm/xe/hwmon: Add helpers to validate thermal sensor readings

[Karthik Poosa]

Add mmio_temp_valid() and mbx_temp_valid() to check whether a temperature
sensor reading is valid. An MMIO value of 0xFFFFFFFF or a mailbox value of
0xFF indicates the sensor is unavailable.

Gate these checks behind has_mbx_temp_sentinel, enabled on CRI currently.

Signed-off-by: Karthik Poosa <karthik.poosa@intel.com>
---
 drivers/gpu/drm/xe/xe_device_types.h |  2 ++
 drivers/gpu/drm/xe/xe_hwmon.c        | 16 ++++++++++++++++
 drivers/gpu/drm/xe/xe_pci.c          |  2 ++
 drivers/gpu/drm/xe/xe_pci_types.h    |  1 +
 4 files changed, 21 insertions(+)

diff --git a/drivers/gpu/drm/xe/xe_device_types.h b/drivers/gpu/drm/xe/xe_device_types.h
index 4661bfce2f4e..87554605fa41 100644
--- a/drivers/gpu/drm/xe/xe_device_types.h
+++ b/drivers/gpu/drm/xe/xe_device_types.h
@@ -202,6 +202,8 @@ struct xe_device {
 		 * pcode mailbox commands.
 		 */
 		u8 has_mbx_power_limits:1;
+		/** @info.has_mbx_temp_sentinel: Device has temperature-unavailable sentinels */
+		u8 has_mbx_temp_sentinel:1;
 		/** @info.has_mbx_thermal_info: Device supports thermal mailbox commands */
 		u8 has_mbx_thermal_info:1;
 		/** @info.has_mem_copy_instr: Device supports MEM_COPY instruction */
diff --git a/drivers/gpu/drm/xe/xe_hwmon.c b/drivers/gpu/drm/xe/xe_hwmon.c
index 658b6902af7f..349423bf6f5a 100644
--- a/drivers/gpu/drm/xe/xe_hwmon.c
+++ b/drivers/gpu/drm/xe/xe_hwmon.c
@@ -104,6 +104,9 @@ enum sensor_attr_power {
 /* Index of memory controller in READ_THERMAL_DATA output */
 #define TEMP_INDEX_MCTRL	2
 
+/* Mailbox sentinel reported for an unavailable temperature sensor */
+#define TEMP_MBX_INVALID	0xFF
+
 /* Mailbox temperature is sign-magnitude: bit 7 sign, bits 6:0 magnitude. */
 #define TEMP_MBX_SIGN		BIT(7)
 #define TEMP_MBX_MAG		GENMASK(6, 0)
@@ -822,6 +825,19 @@ static int xe_hwmon_pcode_read_thermal_info(struct xe_hwmon *hwmon)
 	return ret;
 }
 
+static inline bool mmio_temp_valid(const struct xe_hwmon *hwmon, u32 value)
+{
+	return hwmon->xe->info.has_mbx_temp_sentinel ? value != U32_MAX
+						     : value != 0;
+}
+
+/* Mailbox temperature is sign-magnitude (bit 7 sign, bits 6:0 magnitude). */
+static inline bool mbx_temp_valid(const struct xe_hwmon *hwmon, u8 value)
+{
+	return hwmon->xe->info.has_mbx_temp_sentinel ? value != TEMP_MBX_INVALID
+						     : value != 0;
+}
+
 /* Decode an 8-bit sign-magnitude mailbox temperature to degrees Celsius. */
 static int mbx_temp_decode(u8 value)
 {
diff --git a/drivers/gpu/drm/xe/xe_pci.c b/drivers/gpu/drm/xe/xe_pci.c
index d66d5a0339ae..e656fc012902 100644
--- a/drivers/gpu/drm/xe/xe_pci.c
+++ b/drivers/gpu/drm/xe/xe_pci.c
@@ -476,6 +476,7 @@ static const struct xe_device_desc cri_desc = {
 	.has_gsc_nvm = 1,
 	.has_i2c = true,
 	.has_mbx_power_limits = true,
+	.has_mbx_temp_sentinel = true,
 	.has_mbx_thermal_info = true,
 	.has_mert = true,
 	.has_pre_prod_wa = 1,
@@ -796,6 +797,7 @@ static int xe_info_init_early(struct xe_device *xe,
 	/* runtime fusing may force flat_ccs to disabled later */
 	xe->info.has_flat_ccs = desc->has_flat_ccs;
 	xe->info.has_mbx_power_limits = desc->has_mbx_power_limits;
+	xe->info.has_mbx_temp_sentinel = desc->has_mbx_temp_sentinel;
 	xe->info.has_mbx_thermal_info = desc->has_mbx_thermal_info;
 	xe->info.has_gsc_nvm = desc->has_gsc_nvm;
 	xe->info.has_heci_gscfi = desc->has_heci_gscfi;
diff --git a/drivers/gpu/drm/xe/xe_pci_types.h b/drivers/gpu/drm/xe/xe_pci_types.h
index fed509ff601e..0041ec5676d3 100644
--- a/drivers/gpu/drm/xe/xe_pci_types.h
+++ b/drivers/gpu/drm/xe/xe_pci_types.h
@@ -50,6 +50,7 @@ struct xe_device_desc {
 	u8 has_late_bind:1;
 	u8 has_llc:1;
 	u8 has_mbx_power_limits:1;
+	u8 has_mbx_temp_sentinel:1;
 	u8 has_mbx_thermal_info:1;
 	u8 has_mert:1;
 	u8 has_pre_prod_wa:1;
-- 
2.25.1

[PATCH v5 05/13] drm/xe/hwmon: Handle unavailable memory controller sensors

[Karthik Poosa]

Skip memory controller sensors that report invalid readings when
computing the average temperature in get_mc_temp(). Return -ENXIO when
no valid sensor data is available, and allow the helper to be used as
an availability probe by making the output parameter optional.

Signed-off-by: Karthik Poosa <karthik.poosa@intel.com>
---
 drivers/gpu/drm/xe/xe_hwmon.c | 20 ++++++++++++++++----
 1 file changed, 16 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/xe/xe_hwmon.c b/drivers/gpu/drm/xe/xe_hwmon.c
index 349423bf6f5a..905c3d6b3d3f 100644
--- a/drivers/gpu/drm/xe/xe_hwmon.c
+++ b/drivers/gpu/drm/xe/xe_hwmon.c
@@ -849,8 +849,8 @@ static int mbx_temp_decode(u8 value)
 static int get_mc_temp(struct xe_hwmon *hwmon, long *val)
 {
 	struct xe_tile *root_tile = xe_device_get_root_tile(hwmon->xe);
+	int ret, i, count = 0;
 	s32 average = 0;
-	int ret, i;
 
 	for (i = 0; i < DIV_ROUND_UP(hwmon->temp.count, sizeof(u32)); i++) {
 		ret = xe_pcode_read(root_tile, PCODE_MBOX(PCODE_THERMAL_INFO, READ_THERMAL_DATA, i),
@@ -861,11 +861,23 @@ static int get_mc_temp(struct xe_hwmon *hwmon, long *val)
 			hwmon->temp.dword[i]);
 	}
 
-	for (i = TEMP_INDEX_MCTRL; i < hwmon->temp.count - 1; i++)
+	for (i = TEMP_INDEX_MCTRL; i < hwmon->temp.count - 1; i++) {
+		if (!mbx_temp_valid(hwmon, hwmon->temp.value[i]))
+			continue;
 		average += mbx_temp_decode(hwmon->temp.value[i]);
+		count++;
+	}
+
+	if (!count) {
+		drm_dbg(&hwmon->xe->drm, "Memory controller temperature unavailable!\n");
+		return -ENXIO;
+	}
+
+	average /= count;
+
+	if (val)
+		*val = average * MILLIDEGREE_PER_DEGREE;
 
-	average /= (hwmon->temp.count - TEMP_INDEX_MCTRL - 1);
-	*val = average * MILLIDEGREE_PER_DEGREE;
 	return 0;
 }
 
-- 
2.25.1

[PATCH v5 06/13] drm/xe/hwmon: Detect unavailable PCIe thermal sensors

[Karthik Poosa]

Return -ENXIO from get_pcie_temp() when the mailbox reports an invalid
reading, so the PCIe sensor can be treated as unavailable. Guard the val
store so the function can be used purely as an availability probe. No
sysfs visibility changes.

Signed-off-by: Karthik Poosa <karthik.poosa@intel.com>
---
 drivers/gpu/drm/xe/xe_hwmon.c | 8 +++++++-
 1 file changed, 7 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/xe/xe_hwmon.c b/drivers/gpu/drm/xe/xe_hwmon.c
index 905c3d6b3d3f..7bb7a5f402d1 100644
--- a/drivers/gpu/drm/xe/xe_hwmon.c
+++ b/drivers/gpu/drm/xe/xe_hwmon.c
@@ -897,7 +897,13 @@ static int get_pcie_temp(struct xe_hwmon *hwmon, long *val)
 		data = REG_FIELD_GET(PCIE_SENSOR_MASK, data);
 
 	data = REG_FIELD_GET(TEMP_MASK, data);
-	*val = mbx_temp_decode(data) * MILLIDEGREE_PER_DEGREE;
+	if (!mbx_temp_valid(hwmon, data)) {
+		drm_dbg(&hwmon->xe->drm, "PCIe temperature not available\n");
+		return -ENXIO;
+	}
+
+	if (val)
+		*val = mbx_temp_decode(data) * MILLIDEGREE_PER_DEGREE;
 
 	return 0;
 }
-- 
2.25.1

[PATCH v5 07/13] drm/xe/hwmon: Consolidate temperature sensor availability checks

[Karthik Poosa]

Replace is_vram_ch_available() with a generalized is_temp_available()
that validates PKG, VRAM, per-channel VRAM, memory controller and PCIe
sensors using the new validity helpers. Rename the existing callers to
the new helper.

Use is_temp_available() from xe_hwmon_temp_is_visible() so attributes for
sensors that are not present are not exposed during hwmon registration.

Signed-off-by: Karthik Poosa <karthik.poosa@intel.com>
Assisted-by: LLM
---
 drivers/gpu/drm/xe/xe_hwmon.c | 64 ++++++++++++++++++++++-------------
 1 file changed, 40 insertions(+), 24 deletions(-)

diff --git a/drivers/gpu/drm/xe/xe_hwmon.c b/drivers/gpu/drm/xe/xe_hwmon.c
index 7bb7a5f402d1..d62f95a1912f 100644
--- a/drivers/gpu/drm/xe/xe_hwmon.c
+++ b/drivers/gpu/drm/xe/xe_hwmon.c
@@ -1002,19 +1002,39 @@ static void xe_hwmon_get_voltage(struct xe_hwmon *hwmon, int channel, long *valu
 	*value = DIV_ROUND_CLOSEST(REG_FIELD_GET(VOLTAGE_MASK, reg_val) * 2500, SF_VOLTAGE);
 }
 
-static inline bool is_vram_ch_available(struct xe_hwmon *hwmon, int channel)
+static bool is_temp_available(struct xe_hwmon *hwmon, int channel)
 {
 	struct xe_mmio *mmio = xe_root_tile_mmio(hwmon->xe);
-	int vram_id = channel - CHANNEL_VRAM_N;
-	struct xe_reg vram_reg;
+	struct xe_reg reg;
+	u32 reg_val;
 
-	vram_reg = xe_hwmon_get_reg(hwmon, REG_TEMP, channel);
-	if (!xe_reg_is_valid(vram_reg) || !xe_mmio_read32(mmio, vram_reg))
-		return false;
+	switch (channel) {
+	case CHANNEL_PKG:
+	case CHANNEL_VRAM:
+	case CHANNEL_VRAM_N...CHANNEL_VRAM_N_MAX:
+		reg = xe_hwmon_get_reg(hwmon, REG_TEMP, channel);
+		if (!xe_reg_is_valid(reg))
+			return false;
+
+		reg_val = xe_mmio_read32(mmio, reg);
+		if (!mmio_temp_valid(hwmon, reg_val)) {
+			drm_dbg(&hwmon->xe->drm,
+				"channel %d temperature unavailable, val 0x%x\n", channel, reg_val);
+			return false;
+		}
+
+		if (channel >= CHANNEL_VRAM_N)
+			sprintf(hwmon->temp.vram_label[channel - CHANNEL_VRAM_N],
+				"vram_ch_%d", channel - CHANNEL_VRAM_N);
 
-	/* Create label only for available vram channel */
-	sprintf(hwmon->temp.vram_label[vram_id], "vram_ch_%d", vram_id);
-	return true;
+		return true;
+	case CHANNEL_MCTRL:
+		return hwmon->temp.count && !get_mc_temp(hwmon, NULL);
+	case CHANNEL_PCIE:
+		return hwmon->temp.count && !get_pcie_temp(hwmon, NULL);
+	default:
+		return false;
+	}
 }
 
 static umode_t
@@ -1024,14 +1044,13 @@ xe_hwmon_temp_is_visible(struct xe_hwmon *hwmon, u32 attr, int channel)
 	case hwmon_temp_emergency:
 		switch (channel) {
 		case CHANNEL_PKG:
-			return hwmon->temp.limit[TEMP_LIMIT_PKG_SHUTDOWN] ? 0444 : 0;
-		case CHANNEL_VRAM:
-			return hwmon->temp.limit[TEMP_LIMIT_MEM_SHUTDOWN] ? 0444 : 0;
 		case CHANNEL_MCTRL:
 		case CHANNEL_PCIE:
-			return hwmon->temp.count ? 0444 : 0;
+			return (is_temp_available(hwmon, channel) &&
+				hwmon->temp.limit[TEMP_LIMIT_PKG_SHUTDOWN]) ? 0444 : 0;
+		case CHANNEL_VRAM:
 		case CHANNEL_VRAM_N...CHANNEL_VRAM_N_MAX:
-			return (is_vram_ch_available(hwmon, channel) &&
+			return (is_temp_available(hwmon, channel) &&
 				hwmon->temp.limit[TEMP_LIMIT_MEM_SHUTDOWN]) ? 0444 : 0;
 		default:
 			return 0;
@@ -1039,14 +1058,13 @@ xe_hwmon_temp_is_visible(struct xe_hwmon *hwmon, u32 attr, int channel)
 	case hwmon_temp_crit:
 		switch (channel) {
 		case CHANNEL_PKG:
-			return hwmon->temp.limit[TEMP_LIMIT_PKG_CRIT] ? 0444 : 0;
-		case CHANNEL_VRAM:
-			return hwmon->temp.limit[TEMP_LIMIT_MEM_CRIT] ? 0444 : 0;
 		case CHANNEL_MCTRL:
 		case CHANNEL_PCIE:
-			return hwmon->temp.count ? 0444 : 0;
+			return (is_temp_available(hwmon, channel) &&
+				hwmon->temp.limit[TEMP_LIMIT_PKG_CRIT]) ? 0444 : 0;
+		case CHANNEL_VRAM:
 		case CHANNEL_VRAM_N...CHANNEL_VRAM_N_MAX:
-			return (is_vram_ch_available(hwmon, channel) &&
+			return (is_temp_available(hwmon, channel) &&
 				hwmon->temp.limit[TEMP_LIMIT_MEM_CRIT]) ? 0444 : 0;
 		default:
 			return 0;
@@ -1054,7 +1072,8 @@ xe_hwmon_temp_is_visible(struct xe_hwmon *hwmon, u32 attr, int channel)
 	case hwmon_temp_max:
 		switch (channel) {
 		case CHANNEL_PKG:
-			return hwmon->temp.limit[TEMP_LIMIT_PKG_MAX] ? 0444 : 0;
+			return (is_temp_available(hwmon, channel) &&
+				hwmon->temp.limit[TEMP_LIMIT_PKG_MAX]) ? 0444 : 0;
 		default:
 			return 0;
 		}
@@ -1063,13 +1082,10 @@ xe_hwmon_temp_is_visible(struct xe_hwmon *hwmon, u32 attr, int channel)
 		switch (channel) {
 		case CHANNEL_PKG:
 		case CHANNEL_VRAM:
-			return xe_reg_is_valid(xe_hwmon_get_reg(hwmon, REG_TEMP,
-								channel)) ? 0444 : 0;
 		case CHANNEL_MCTRL:
 		case CHANNEL_PCIE:
-			return hwmon->temp.count ? 0444 : 0;
 		case CHANNEL_VRAM_N...CHANNEL_VRAM_N_MAX:
-			return is_vram_ch_available(hwmon, channel) ? 0444 : 0;
+			return is_temp_available(hwmon, channel) ? 0444 : 0;
 		default:
 			return 0;
 		}
-- 
2.25.1

Re: [PATCH v5 07/13] drm/xe/hwmon: Consolidate temperature sensor availability checks

[sashiko-bot]

Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [Medium] hwmon: initialization race causes permanent attribute loss on slow sensors
--

commit c02db655e6dabb60e61a8acbe0daf64a353e248d
Author: Karthik Poosa <karthik.poosa@intel.com>
Subject: drm/xe/hwmon: Consolidate temperature sensor availability checks

This commit replaces is_vram_ch_available() with a generalized 
is_temp_available() to validate multiple sensor types. It uses this new 
helper during hwmon registration to prevent exposing sysfs attributes for 
sensors that are not present.

> diff --git a/drivers/gpu/drm/xe/xe_hwmon.c b/drivers/gpu/drm/xe/xe_hwmon.c
> index 7bb7a5f402d1e..d62f95a1912f3 100644
> --- a/drivers/gpu/drm/xe/xe_hwmon.c
> +++ b/drivers/gpu/drm/xe/xe_hwmon.c
[ ... ]
> -static inline bool is_vram_ch_available(struct xe_hwmon *hwmon, int channel)
> +static bool is_temp_available(struct xe_hwmon *hwmon, int channel)
>  {
>  	struct xe_mmio *mmio = xe_root_tile_mmio(hwmon->xe);
> -	int vram_id = channel - CHANNEL_VRAM_N;
> -	struct xe_reg vram_reg;
> +	struct xe_reg reg;
> +	u32 reg_val;
>  
> -	vram_reg = xe_hwmon_get_reg(hwmon, REG_TEMP, channel);
> -	if (!xe_reg_is_valid(vram_reg) || !xe_mmio_read32(mmio, vram_reg))
> -		return false;
> +	switch (channel) {
> +	case CHANNEL_PKG:
> +	case CHANNEL_VRAM:
> +	case CHANNEL_VRAM_N...CHANNEL_VRAM_N_MAX:
> +		reg = xe_hwmon_get_reg(hwmon, REG_TEMP, channel);
> +		if (!xe_reg_is_valid(reg))
> +			return false;
> +
> +		reg_val = xe_mmio_read32(mmio, reg);
> +		if (!mmio_temp_valid(hwmon, reg_val)) {
> +			drm_dbg(&hwmon->xe->drm,
> +				"channel %d temperature unavailable, val 0x%x\n", channel, reg_val);
> +			return false;
> +		}

[Severity: Medium]
Could this cause functional sensors to be permanently hidden if the firmware
is slow to initialize them?

During hwmon registration, is_temp_available() performs a live MMIO read to
determine attribute visibility. If the firmware hasn't populated a valid
temperature yet at the exact moment of device probe (for instance, returning
0 or U32_MAX), mmio_temp_valid() will return false.

Since this determines sysfs attribute visibility, doesn't this create a
silent failure where perfectly functional PKG sensors disappear intermittently
depending on boot timing?

> +
> +		if (channel >= CHANNEL_VRAM_N)
> +			sprintf(hwmon->temp.vram_label[channel - CHANNEL_VRAM_N],
> +				"vram_ch_%d", channel - CHANNEL_VRAM_N);
>  
> -	/* Create label only for available vram channel */
> -	sprintf(hwmon->temp.vram_label[vram_id], "vram_ch_%d", vram_id);
> -	return true;
> +		return true;
> +	case CHANNEL_MCTRL:
> +		return hwmon->temp.count && !get_mc_temp(hwmon, NULL);
> +	case CHANNEL_PCIE:
> +		return hwmon->temp.count && !get_pcie_temp(hwmon, NULL);

[Severity: Medium]
Similarly, does this live PCODE mailbox polling risk permanently hiding the
Memory Controller and PCIe temperature sensors?

If PCODE is slow to respond during device probe, get_mc_temp() and
get_pcie_temp() might fail or return invalid data. Because this check
replaces static capability checks (such as hwmon->temp.count) with live
sensor data, it seems to introduce a race condition where a temporary
initialization delay results in permanent attribute loss.

> +	default:
> +		return false;
> +	}
>  }

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20260924111156.2628915-1-karthik.poosa@intel.com?part=7

Re: [PATCH v5 07/13] drm/xe/hwmon: Consolidate temperature sensor availability checks

[Poosa, Karthik]

On 24-09-2026 16:54, sashiko-bot@kernel.org wrote:
> Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
> - [Medium] hwmon: initialization race causes permanent attribute loss on slow sensors
> --
>
> commit c02db655e6dabb60e61a8acbe0daf64a353e248d
> Author: Karthik Poosa <karthik.poosa@intel.com>
> Subject: drm/xe/hwmon: Consolidate temperature sensor availability checks
>
> This commit replaces is_vram_ch_available() with a generalized
> is_temp_available() to validate multiple sensor types. It uses this new
> helper during hwmon registration to prevent exposing sysfs attributes for
> sensors that are not present.
>
>> diff --git a/drivers/gpu/drm/xe/xe_hwmon.c b/drivers/gpu/drm/xe/xe_hwmon.c
>> index 7bb7a5f402d1e..d62f95a1912f3 100644
>> --- a/drivers/gpu/drm/xe/xe_hwmon.c
>> +++ b/drivers/gpu/drm/xe/xe_hwmon.c
> [ ... ]
>> -static inline bool is_vram_ch_available(struct xe_hwmon *hwmon, int channel)
>> +static bool is_temp_available(struct xe_hwmon *hwmon, int channel)
>>   {
>>   	struct xe_mmio *mmio = xe_root_tile_mmio(hwmon->xe);
>> -	int vram_id = channel - CHANNEL_VRAM_N;
>> -	struct xe_reg vram_reg;
>> +	struct xe_reg reg;
>> +	u32 reg_val;
>>   
>> -	vram_reg = xe_hwmon_get_reg(hwmon, REG_TEMP, channel);
>> -	if (!xe_reg_is_valid(vram_reg) || !xe_mmio_read32(mmio, vram_reg))
>> -		return false;
>> +	switch (channel) {
>> +	case CHANNEL_PKG:
>> +	case CHANNEL_VRAM:
>> +	case CHANNEL_VRAM_N...CHANNEL_VRAM_N_MAX:
>> +		reg = xe_hwmon_get_reg(hwmon, REG_TEMP, channel);
>> +		if (!xe_reg_is_valid(reg))
>> +			return false;
>> +
>> +		reg_val = xe_mmio_read32(mmio, reg);
>> +		if (!mmio_temp_valid(hwmon, reg_val)) {
>> +			drm_dbg(&hwmon->xe->drm,
>> +				"channel %d temperature unavailable, val 0x%x\n", channel, reg_val);
>> +			return false;
>> +		}
> [Severity: Medium]
> Could this cause functional sensors to be permanently hidden if the firmware
> is slow to initialize them?
>
> During hwmon registration, is_temp_available() performs a live MMIO read to
> determine attribute visibility. If the firmware hasn't populated a valid
> temperature yet at the exact moment of device probe (for instance, returning
> 0 or U32_MAX), mmio_temp_valid() will return false.
>
> Since this determines sysfs attribute visibility, doesn't this create a
> silent failure where perfectly functional PKG sensors disappear intermittently
> depending on boot timing?

xe_pcode_probe_early() wait for pcode ready before hwmon registration.

These sensors and pcode are expected to be ready by then.

>
>> +
>> +		if (channel >= CHANNEL_VRAM_N)
>> +			sprintf(hwmon->temp.vram_label[channel - CHANNEL_VRAM_N],
>> +				"vram_ch_%d", channel - CHANNEL_VRAM_N);
>>   
>> -	/* Create label only for available vram channel */
>> -	sprintf(hwmon->temp.vram_label[vram_id], "vram_ch_%d", vram_id);
>> -	return true;
>> +		return true;
>> +	case CHANNEL_MCTRL:
>> +		return hwmon->temp.count && !get_mc_temp(hwmon, NULL);
>> +	case CHANNEL_PCIE:
>> +		return hwmon->temp.count && !get_pcie_temp(hwmon, NULL);
> [Severity: Medium]
> Similarly, does this live PCODE mailbox polling risk permanently hiding the
> Memory Controller and PCIe temperature sensors?
>
> If PCODE is slow to respond during device probe, get_mc_temp() and
> get_pcie_temp() might fail or return invalid data. Because this check
> replaces static capability checks (such as hwmon->temp.count) with live
> sensor data, it seems to introduce a race condition where a temporary
> initialization delay results in permanent attribute loss.
same as above.
>
>> +	default:
>> +		return false;
>> +	}
>>   }

[PATCH v5 08/13] drm/xe/hwmon: Cache temperature availability to reduce probe time

[Karthik Poosa]

Avoid probing temperature sensor availability from the hwmon is_visible()
callback. For MCTRL and PCIe channels, that path can trigger repeated
blocking mailbox reads while sysfs attributes are being created, increasing
probe time and making attribute creation sensitive to transient failures.

Probe temperature availability once during preregistration and cache the
result for subsequent visibility checks.

Signed-off-by: Karthik Poosa <karthik.poosa@intel.com>
Assisted-by: LLM
---
 drivers/gpu/drm/xe/xe_hwmon.c | 39 +++++++++++++++++++++++------------
 1 file changed, 26 insertions(+), 13 deletions(-)

diff --git a/drivers/gpu/drm/xe/xe_hwmon.c b/drivers/gpu/drm/xe/xe_hwmon.c
index d62f95a1912f..cf5d51c68536 100644
--- a/drivers/gpu/drm/xe/xe_hwmon.c
+++ b/drivers/gpu/drm/xe/xe_hwmon.c
@@ -146,6 +146,8 @@ struct xe_hwmon_thermal_info {
 	};
 	/** @count: no of temperature sensors available for the platform */
 	u8 count;
+	/** @available: temperature sensor availability cached at registration */
+	bool available[CHANNEL_MAX];
 	union {
 		/** @vavlue: per-sensor raw mailbox temperature; bit7=sign, bits6:0=magnitude */
 		u8 value[U8_MAX + 1];
@@ -1002,7 +1004,7 @@ static void xe_hwmon_get_voltage(struct xe_hwmon *hwmon, int channel, long *valu
 	*value = DIV_ROUND_CLOSEST(REG_FIELD_GET(VOLTAGE_MASK, reg_val) * 2500, SF_VOLTAGE);
 }
 
-static bool is_temp_available(struct xe_hwmon *hwmon, int channel)
+static bool xe_hwmon_temp_probe(struct xe_hwmon *hwmon, int channel)
 {
 	struct xe_mmio *mmio = xe_root_tile_mmio(hwmon->xe);
 	struct xe_reg reg;
@@ -1023,10 +1025,6 @@ static bool is_temp_available(struct xe_hwmon *hwmon, int channel)
 			return false;
 		}
 
-		if (channel >= CHANNEL_VRAM_N)
-			sprintf(hwmon->temp.vram_label[channel - CHANNEL_VRAM_N],
-				"vram_ch_%d", channel - CHANNEL_VRAM_N);
-
 		return true;
 	case CHANNEL_MCTRL:
 		return hwmon->temp.count && !get_mc_temp(hwmon, NULL);
@@ -1037,6 +1035,22 @@ static bool is_temp_available(struct xe_hwmon *hwmon, int channel)
 	}
 }
 
+static void xe_hwmon_init_temp_info(struct xe_hwmon *hwmon)
+{
+	int channel;
+
+	if (hwmon->xe->info.has_mbx_thermal_info && xe_hwmon_pcode_read_thermal_info(hwmon))
+		drm_warn(&hwmon->xe->drm, "Thermal mailbox not supported by card firmware\n");
+
+	for (channel = 0; channel < CHANNEL_MAX; channel++) {
+		hwmon->temp.available[channel] = xe_hwmon_temp_probe(hwmon, channel);
+		if (hwmon->temp.available[channel] &&
+		    in_range(channel, CHANNEL_VRAM_N, MAX_VRAM_CHANNELS))
+			snprintf(hwmon->temp.vram_label[channel - CHANNEL_VRAM_N], MAX_LABEL_SIZE,
+				 "vram_ch_%d", channel - CHANNEL_VRAM_N);
+	}
+}
+
 static umode_t
 xe_hwmon_temp_is_visible(struct xe_hwmon *hwmon, u32 attr, int channel)
 {
@@ -1046,11 +1060,11 @@ xe_hwmon_temp_is_visible(struct xe_hwmon *hwmon, u32 attr, int channel)
 		case CHANNEL_PKG:
 		case CHANNEL_MCTRL:
 		case CHANNEL_PCIE:
-			return (is_temp_available(hwmon, channel) &&
+			return (hwmon->temp.available[channel] &&
 				hwmon->temp.limit[TEMP_LIMIT_PKG_SHUTDOWN]) ? 0444 : 0;
 		case CHANNEL_VRAM:
 		case CHANNEL_VRAM_N...CHANNEL_VRAM_N_MAX:
-			return (is_temp_available(hwmon, channel) &&
+			return (hwmon->temp.available[channel] &&
 				hwmon->temp.limit[TEMP_LIMIT_MEM_SHUTDOWN]) ? 0444 : 0;
 		default:
 			return 0;
@@ -1060,11 +1074,11 @@ xe_hwmon_temp_is_visible(struct xe_hwmon *hwmon, u32 attr, int channel)
 		case CHANNEL_PKG:
 		case CHANNEL_MCTRL:
 		case CHANNEL_PCIE:
-			return (is_temp_available(hwmon, channel) &&
+			return (hwmon->temp.available[channel] &&
 				hwmon->temp.limit[TEMP_LIMIT_PKG_CRIT]) ? 0444 : 0;
 		case CHANNEL_VRAM:
 		case CHANNEL_VRAM_N...CHANNEL_VRAM_N_MAX:
-			return (is_temp_available(hwmon, channel) &&
+			return (hwmon->temp.available[channel] &&
 				hwmon->temp.limit[TEMP_LIMIT_MEM_CRIT]) ? 0444 : 0;
 		default:
 			return 0;
@@ -1072,7 +1086,7 @@ xe_hwmon_temp_is_visible(struct xe_hwmon *hwmon, u32 attr, int channel)
 	case hwmon_temp_max:
 		switch (channel) {
 		case CHANNEL_PKG:
-			return (is_temp_available(hwmon, channel) &&
+			return (hwmon->temp.available[channel] &&
 				hwmon->temp.limit[TEMP_LIMIT_PKG_MAX]) ? 0444 : 0;
 		default:
 			return 0;
@@ -1085,7 +1099,7 @@ xe_hwmon_temp_is_visible(struct xe_hwmon *hwmon, u32 attr, int channel)
 		case CHANNEL_MCTRL:
 		case CHANNEL_PCIE:
 		case CHANNEL_VRAM_N...CHANNEL_VRAM_N_MAX:
-			return is_temp_available(hwmon, channel) ? 0444 : 0;
+			return hwmon->temp.available[channel] ? 0444 : 0;
 		default:
 			return 0;
 		}
@@ -1627,8 +1641,7 @@ xe_hwmon_get_preregistration_info(struct xe_hwmon *hwmon)
 		if (xe_hwmon_is_visible(hwmon, hwmon_fan, hwmon_fan_input, channel))
 			xe_hwmon_fan_input_read(hwmon, channel, &fan_speed);
 
-	if (hwmon->xe->info.has_mbx_thermal_info && xe_hwmon_pcode_read_thermal_info(hwmon))
-		drm_warn(&hwmon->xe->drm, "Thermal mailbox not supported by card firmware\n");
+	xe_hwmon_init_temp_info(hwmon);
 }
 
 int xe_hwmon_register(struct xe_device *xe)
-- 
2.25.1

[PATCH v5 09/13] drm/xe/hwmon: Add platform-aware VRAM thermal channel support

[Karthik Poosa]

On CRI, derive the number of available VRAM temperature channels from the
CRI_MSU_VRAM_ENABLE register, where each enabled MSU contributes
VRAM_CHANNELS_PER_MSU channels.
 
Increase the maximum supported VRAM channel count to 80 and use the
derived count to control VRAM sensor enumeration, channel access, and
VRAM label allocation. Add a has_fixed_vram_channels platform flag to
preserve the existing fixed-channel behavior on non-CRI platforms.

Signed-off-by: Karthik Poosa <karthik.poosa@intel.com>
---
 drivers/gpu/drm/xe/regs/xe_pcode_regs.h |   1 +
 drivers/gpu/drm/xe/xe_device_types.h    |   2 +
 drivers/gpu/drm/xe/xe_hwmon.c           | 160 +++++++++++++++++++++---
 drivers/gpu/drm/xe/xe_pci.c             |   2 +
 drivers/gpu/drm/xe/xe_pci_types.h       |   1 +
 5 files changed, 151 insertions(+), 15 deletions(-)

diff --git a/drivers/gpu/drm/xe/regs/xe_pcode_regs.h b/drivers/gpu/drm/xe/regs/xe_pcode_regs.h
index c63b409d7a82..11916b4f7cfc 100644
--- a/drivers/gpu/drm/xe/regs/xe_pcode_regs.h
+++ b/drivers/gpu/drm/xe/regs/xe_pcode_regs.h
@@ -29,5 +29,6 @@
 
 #define CRI_PACKAGE_ENERGY_STATUS		XE_REG(0x138120)
 #define CRI_PLATFORM_ENERGY_STATUS		XE_REG(0x138458)
+#define CRI_MSU_VRAM_ENABLE             XE_REG(0x138340)
 
 #endif /* _XE_PCODE_REGS_H_ */
diff --git a/drivers/gpu/drm/xe/xe_device_types.h b/drivers/gpu/drm/xe/xe_device_types.h
index 87554605fa41..8a1ca65f5665 100644
--- a/drivers/gpu/drm/xe/xe_device_types.h
+++ b/drivers/gpu/drm/xe/xe_device_types.h
@@ -184,6 +184,8 @@ struct xe_device {
 		u8 has_drm_ras:1;
 		/** @info.has_fan_control: Device supports fan control */
 		u8 has_fan_control:1;
+		/** @info.has_fixed_vram_channels: Device has fixed VRAM temperature channels */
+		u8 has_fixed_vram_channels:1;
 		/** @info.has_flat_ccs: Whether flat CCS metadata is used */
 		u8 has_flat_ccs:1;
 		/** @info.has_gsc_nvm: Device has gsc non-volatile memory */
diff --git a/drivers/gpu/drm/xe/xe_hwmon.c b/drivers/gpu/drm/xe/xe_hwmon.c
index cf5d51c68536..1b587bd9487e 100644
--- a/drivers/gpu/drm/xe/xe_hwmon.c
+++ b/drivers/gpu/drm/xe/xe_hwmon.c
@@ -39,7 +39,11 @@ enum xe_hwmon_reg_operation {
 	REG_READ64,
 };
 
-#define MAX_VRAM_CHANNELS      (16)
+#define MAX_VRAM_CHANNELS	80
+#define FIXED_VRAM_CHANNELS	16
+
+/* Each MSU enable bit maps to one VRAM subsystem of 4 channels. */
+#define VRAM_CHANNELS_PER_MSU	4
 
 enum xe_hwmon_channel {
 	CHANNEL_CARD,
@@ -48,6 +52,7 @@ enum xe_hwmon_channel {
 	CHANNEL_MCTRL,
 	CHANNEL_PCIE,
 	CHANNEL_VRAM_N,
+	/* Compile-time upper bound; actual channel count is hwmon->temp.vram_count */
 	CHANNEL_VRAM_N_MAX = CHANNEL_VRAM_N + MAX_VRAM_CHANNELS - 1,
 	CHANNEL_MAX,
 };
@@ -144,18 +149,22 @@ struct xe_hwmon_thermal_info {
 		/** @data: temperature limits in dwords */
 		u32 data[DIV_ROUND_UP(TEMP_LIMIT_MAX, sizeof(u32))];
 	};
-	/** @count: no of temperature sensors available for the platform */
+	/** @count: temperature sensors count from READ_THERMAL_CONFIG */
 	u8 count;
+	/** @vram_count: number of VRAM temperature sensors available for the platform */
+	u8 vram_count;
 	/** @available: temperature sensor availability cached at registration */
 	bool available[CHANNEL_MAX];
+	/** @msu_mask: VRAM subsystem enable mask read from MMIO */
+	u32 msu_mask;
 	union {
 		/** @vavlue: per-sensor raw mailbox temperature; bit7=sign, bits6:0=magnitude */
 		u8 value[U8_MAX + 1];
 		/** @dword: sensor values as dwords, u32-aligned for pcode reads */
 		u32 dword[DIV_ROUND_UP(U8_MAX + 1, sizeof(u32))];
 	};
-	/** @vram_label: vram label names */
-	char vram_label[MAX_VRAM_CHANNELS][MAX_LABEL_SIZE];
+	/** @vram_label: vram label names, dynamically allocated based on vram_count */
+	char (*vram_label)[MAX_LABEL_SIZE];
 };
 
 /**
@@ -269,6 +278,14 @@ static int xe_hwmon_pcode_rmw_power_limit(const struct xe_hwmon *hwmon, u32 attr
 	return ret;
 }
 
+static bool xe_hwmon_vram_channel_enabled(const struct xe_hwmon *hwmon, int index)
+{
+	if (hwmon->xe->info.platform == XE_CRESCENTISLAND)
+		return hwmon->temp.msu_mask & BIT(index / VRAM_CHANNELS_PER_MSU);
+
+	return true;
+}
+
 static struct xe_reg xe_hwmon_get_reg(struct xe_hwmon *hwmon, enum xe_hwmon_reg hwmon_reg,
 				      int channel)
 {
@@ -281,7 +298,8 @@ static struct xe_reg xe_hwmon_get_reg(struct xe_hwmon *hwmon, enum xe_hwmon_reg
 				return BMG_PACKAGE_TEMPERATURE;
 			else if (channel == CHANNEL_VRAM)
 				return BMG_VRAM_TEMPERATURE;
-			else if (in_range(channel, CHANNEL_VRAM_N, MAX_VRAM_CHANNELS))
+			else if (in_range(channel, CHANNEL_VRAM_N, hwmon->temp.vram_count) &&
+				 xe_hwmon_vram_channel_enabled(hwmon, channel - CHANNEL_VRAM_N))
 				return BMG_VRAM_TEMPERATURE_N(channel - CHANNEL_VRAM_N);
 		} else if (xe->info.platform == XE_DG2) {
 			if (channel == CHANNEL_PKG)
@@ -791,6 +809,70 @@ static const struct hwmon_channel_info * const hwmon_info[] = {
 			   HWMON_T_CRIT | HWMON_T_EMERGENCY | HWMON_T_INPUT | HWMON_T_LABEL,
 			   HWMON_T_CRIT | HWMON_T_EMERGENCY | HWMON_T_INPUT | HWMON_T_LABEL,
 			   HWMON_T_CRIT | HWMON_T_EMERGENCY | HWMON_T_INPUT | HWMON_T_LABEL,
+			   HWMON_T_CRIT | HWMON_T_EMERGENCY | HWMON_T_INPUT | HWMON_T_LABEL,
+			   HWMON_T_CRIT | HWMON_T_EMERGENCY | HWMON_T_INPUT | HWMON_T_LABEL,
+			   HWMON_T_CRIT | HWMON_T_EMERGENCY | HWMON_T_INPUT | HWMON_T_LABEL,
+			   HWMON_T_CRIT | HWMON_T_EMERGENCY | HWMON_T_INPUT | HWMON_T_LABEL,
+			   HWMON_T_CRIT | HWMON_T_EMERGENCY | HWMON_T_INPUT | HWMON_T_LABEL,
+			   HWMON_T_CRIT | HWMON_T_EMERGENCY | HWMON_T_INPUT | HWMON_T_LABEL,
+			   HWMON_T_CRIT | HWMON_T_EMERGENCY | HWMON_T_INPUT | HWMON_T_LABEL,
+			   HWMON_T_CRIT | HWMON_T_EMERGENCY | HWMON_T_INPUT | HWMON_T_LABEL,
+			   HWMON_T_CRIT | HWMON_T_EMERGENCY | HWMON_T_INPUT | HWMON_T_LABEL,
+			   HWMON_T_CRIT | HWMON_T_EMERGENCY | HWMON_T_INPUT | HWMON_T_LABEL,
+			   HWMON_T_CRIT | HWMON_T_EMERGENCY | HWMON_T_INPUT | HWMON_T_LABEL,
+			   HWMON_T_CRIT | HWMON_T_EMERGENCY | HWMON_T_INPUT | HWMON_T_LABEL,
+			   HWMON_T_CRIT | HWMON_T_EMERGENCY | HWMON_T_INPUT | HWMON_T_LABEL,
+			   HWMON_T_CRIT | HWMON_T_EMERGENCY | HWMON_T_INPUT | HWMON_T_LABEL,
+			   HWMON_T_CRIT | HWMON_T_EMERGENCY | HWMON_T_INPUT | HWMON_T_LABEL,
+			   HWMON_T_CRIT | HWMON_T_EMERGENCY | HWMON_T_INPUT | HWMON_T_LABEL,
+			   HWMON_T_CRIT | HWMON_T_EMERGENCY | HWMON_T_INPUT | HWMON_T_LABEL,
+			   HWMON_T_CRIT | HWMON_T_EMERGENCY | HWMON_T_INPUT | HWMON_T_LABEL,
+			   HWMON_T_CRIT | HWMON_T_EMERGENCY | HWMON_T_INPUT | HWMON_T_LABEL,
+			   HWMON_T_CRIT | HWMON_T_EMERGENCY | HWMON_T_INPUT | HWMON_T_LABEL,
+			   HWMON_T_CRIT | HWMON_T_EMERGENCY | HWMON_T_INPUT | HWMON_T_LABEL,
+			   HWMON_T_CRIT | HWMON_T_EMERGENCY | HWMON_T_INPUT | HWMON_T_LABEL,
+			   HWMON_T_CRIT | HWMON_T_EMERGENCY | HWMON_T_INPUT | HWMON_T_LABEL,
+			   HWMON_T_CRIT | HWMON_T_EMERGENCY | HWMON_T_INPUT | HWMON_T_LABEL,
+			   HWMON_T_CRIT | HWMON_T_EMERGENCY | HWMON_T_INPUT | HWMON_T_LABEL,
+			   HWMON_T_CRIT | HWMON_T_EMERGENCY | HWMON_T_INPUT | HWMON_T_LABEL,
+			   HWMON_T_CRIT | HWMON_T_EMERGENCY | HWMON_T_INPUT | HWMON_T_LABEL,
+			   HWMON_T_CRIT | HWMON_T_EMERGENCY | HWMON_T_INPUT | HWMON_T_LABEL,
+			   HWMON_T_CRIT | HWMON_T_EMERGENCY | HWMON_T_INPUT | HWMON_T_LABEL,
+			   HWMON_T_CRIT | HWMON_T_EMERGENCY | HWMON_T_INPUT | HWMON_T_LABEL,
+			   HWMON_T_CRIT | HWMON_T_EMERGENCY | HWMON_T_INPUT | HWMON_T_LABEL,
+			   HWMON_T_CRIT | HWMON_T_EMERGENCY | HWMON_T_INPUT | HWMON_T_LABEL,
+			   HWMON_T_CRIT | HWMON_T_EMERGENCY | HWMON_T_INPUT | HWMON_T_LABEL,
+			   HWMON_T_CRIT | HWMON_T_EMERGENCY | HWMON_T_INPUT | HWMON_T_LABEL,
+			   HWMON_T_CRIT | HWMON_T_EMERGENCY | HWMON_T_INPUT | HWMON_T_LABEL,
+			   HWMON_T_CRIT | HWMON_T_EMERGENCY | HWMON_T_INPUT | HWMON_T_LABEL,
+			   HWMON_T_CRIT | HWMON_T_EMERGENCY | HWMON_T_INPUT | HWMON_T_LABEL,
+			   HWMON_T_CRIT | HWMON_T_EMERGENCY | HWMON_T_INPUT | HWMON_T_LABEL,
+			   HWMON_T_CRIT | HWMON_T_EMERGENCY | HWMON_T_INPUT | HWMON_T_LABEL,
+			   HWMON_T_CRIT | HWMON_T_EMERGENCY | HWMON_T_INPUT | HWMON_T_LABEL,
+			   HWMON_T_CRIT | HWMON_T_EMERGENCY | HWMON_T_INPUT | HWMON_T_LABEL,
+			   HWMON_T_CRIT | HWMON_T_EMERGENCY | HWMON_T_INPUT | HWMON_T_LABEL,
+			   HWMON_T_CRIT | HWMON_T_EMERGENCY | HWMON_T_INPUT | HWMON_T_LABEL,
+			   HWMON_T_CRIT | HWMON_T_EMERGENCY | HWMON_T_INPUT | HWMON_T_LABEL,
+			   HWMON_T_CRIT | HWMON_T_EMERGENCY | HWMON_T_INPUT | HWMON_T_LABEL,
+			   HWMON_T_CRIT | HWMON_T_EMERGENCY | HWMON_T_INPUT | HWMON_T_LABEL,
+			   HWMON_T_CRIT | HWMON_T_EMERGENCY | HWMON_T_INPUT | HWMON_T_LABEL,
+			   HWMON_T_CRIT | HWMON_T_EMERGENCY | HWMON_T_INPUT | HWMON_T_LABEL,
+			   HWMON_T_CRIT | HWMON_T_EMERGENCY | HWMON_T_INPUT | HWMON_T_LABEL,
+			   HWMON_T_CRIT | HWMON_T_EMERGENCY | HWMON_T_INPUT | HWMON_T_LABEL,
+			   HWMON_T_CRIT | HWMON_T_EMERGENCY | HWMON_T_INPUT | HWMON_T_LABEL,
+			   HWMON_T_CRIT | HWMON_T_EMERGENCY | HWMON_T_INPUT | HWMON_T_LABEL,
+			   HWMON_T_CRIT | HWMON_T_EMERGENCY | HWMON_T_INPUT | HWMON_T_LABEL,
+			   HWMON_T_CRIT | HWMON_T_EMERGENCY | HWMON_T_INPUT | HWMON_T_LABEL,
+			   HWMON_T_CRIT | HWMON_T_EMERGENCY | HWMON_T_INPUT | HWMON_T_LABEL,
+			   HWMON_T_CRIT | HWMON_T_EMERGENCY | HWMON_T_INPUT | HWMON_T_LABEL,
+			   HWMON_T_CRIT | HWMON_T_EMERGENCY | HWMON_T_INPUT | HWMON_T_LABEL,
+			   HWMON_T_CRIT | HWMON_T_EMERGENCY | HWMON_T_INPUT | HWMON_T_LABEL,
+			   HWMON_T_CRIT | HWMON_T_EMERGENCY | HWMON_T_INPUT | HWMON_T_LABEL,
+			   HWMON_T_CRIT | HWMON_T_EMERGENCY | HWMON_T_INPUT | HWMON_T_LABEL,
+			   HWMON_T_CRIT | HWMON_T_EMERGENCY | HWMON_T_INPUT | HWMON_T_LABEL,
+			   HWMON_T_CRIT | HWMON_T_EMERGENCY | HWMON_T_INPUT | HWMON_T_LABEL,
+			   HWMON_T_CRIT | HWMON_T_EMERGENCY | HWMON_T_INPUT | HWMON_T_LABEL,
+			   HWMON_T_CRIT | HWMON_T_EMERGENCY | HWMON_T_INPUT | HWMON_T_LABEL,
 			   HWMON_T_CRIT | HWMON_T_EMERGENCY | HWMON_T_INPUT | HWMON_T_LABEL),
 	HWMON_CHANNEL_INFO(power, HWMON_P_MAX | HWMON_P_RATED_MAX | HWMON_P_LABEL | HWMON_P_CRIT |
 			   HWMON_P_CAP,
@@ -805,15 +887,38 @@ static const struct hwmon_channel_info * const hwmon_info[] = {
 static int xe_hwmon_pcode_read_thermal_info(struct xe_hwmon *hwmon)
 {
 	struct xe_tile *root_tile = xe_device_get_root_tile(hwmon->xe);
+	struct xe_mmio *mmio = xe_root_tile_mmio(hwmon->xe);
 	u32 config = 0;
 	int ret;
 
+	/*
+	 * Only CRI reports dynamic VRAM channel state. Fixed-channel platforms
+	 * set the count up front so those sensors stay visible even if the thermal
+	 * mailbox reads below fail.
+	 */
+	if (hwmon->xe->info.has_fixed_vram_channels)
+		hwmon->temp.vram_count = FIXED_VRAM_CHANNELS;
+
+	if (hwmon->xe->info.platform == XE_CRESCENTISLAND) {
+		hwmon->temp.msu_mask = xe_mmio_read32(mmio, CRI_MSU_VRAM_ENABLE);
+		/* Each enabled MSU bit maps to VRAM_CHANNELS_PER_MSU channels. */
+		hwmon->temp.vram_count = hweight32(hwmon->temp.msu_mask) * VRAM_CHANNELS_PER_MSU;
+		drm_dbg(&hwmon->xe->drm, "MSU VRAM enable mask 0x%x, VRAM channel count %d\n",
+			hwmon->temp.msu_mask, hwmon->temp.vram_count);
+		if (hwmon->temp.vram_count > MAX_VRAM_CHANNELS) {
+			drm_warn(&hwmon->xe->drm,
+				 "VRAM channel count %d exceeds max %d, clamping\n",
+				 hwmon->temp.vram_count, MAX_VRAM_CHANNELS);
+			hwmon->temp.vram_count = MAX_VRAM_CHANNELS;
+		}
+	}
+
 	ret = xe_pcode_read(root_tile, PCODE_MBOX(PCODE_THERMAL_INFO, READ_THERMAL_LIMITS, 0),
 			    &hwmon->temp.data[0], &hwmon->temp.data[1]);
 	if (ret)
 		return ret;
 
-	drm_dbg(&hwmon->xe->drm, "thermal info read val 0x%x val1 0x%x\n",
+	drm_dbg(&hwmon->xe->drm, "thermal info read val 0x%08x val1 0x%08x\n",
 		hwmon->temp.data[0], hwmon->temp.data[1]);
 
 	ret = xe_pcode_read(root_tile, PCODE_MBOX(PCODE_THERMAL_INFO, READ_THERMAL_CONFIG, 0),
@@ -1018,6 +1123,14 @@ static bool xe_hwmon_temp_probe(struct xe_hwmon *hwmon, int channel)
 		if (!xe_reg_is_valid(reg))
 			return false;
 
+		/*
+		 * On CRI, VRAM channel presence comes from the MSU enable mask
+		 * (applied in xe_hwmon_get_reg()); the temperature register's
+		 * 0xffffffff sentinel is not reliable for VRAM channels.
+		 */
+		if (hwmon->xe->info.platform == XE_CRESCENTISLAND && channel >= CHANNEL_VRAM_N)
+			return true;
+
 		reg_val = xe_mmio_read32(mmio, reg);
 		if (!mmio_temp_valid(hwmon, reg_val)) {
 			drm_dbg(&hwmon->xe->drm,
@@ -1035,20 +1148,31 @@ static bool xe_hwmon_temp_probe(struct xe_hwmon *hwmon, int channel)
 	}
 }
 
-static void xe_hwmon_init_temp_info(struct xe_hwmon *hwmon)
+static int xe_hwmon_init_temp_info(struct xe_hwmon *hwmon)
 {
+	struct device *dev = hwmon->xe->drm.dev;
 	int channel;
 
 	if (hwmon->xe->info.has_mbx_thermal_info && xe_hwmon_pcode_read_thermal_info(hwmon))
 		drm_warn(&hwmon->xe->drm, "Thermal mailbox not supported by card firmware\n");
 
+	/* vram_count is known only after reading thermal info above. */
+	if (hwmon->temp.vram_count) {
+		hwmon->temp.vram_label = devm_kcalloc(dev, hwmon->temp.vram_count,
+						      MAX_LABEL_SIZE, GFP_KERNEL);
+		if (!hwmon->temp.vram_label)
+			return -ENOMEM;
+	}
+
 	for (channel = 0; channel < CHANNEL_MAX; channel++) {
 		hwmon->temp.available[channel] = xe_hwmon_temp_probe(hwmon, channel);
-		if (hwmon->temp.available[channel] &&
-		    in_range(channel, CHANNEL_VRAM_N, MAX_VRAM_CHANNELS))
+		if (hwmon->temp.available[channel] && hwmon->temp.vram_label &&
+		    in_range(channel, CHANNEL_VRAM_N, hwmon->temp.vram_count))
 			snprintf(hwmon->temp.vram_label[channel - CHANNEL_VRAM_N], MAX_LABEL_SIZE,
 				 "vram_ch_%d", channel - CHANNEL_VRAM_N);
 	}
+
+	return 0;
 }
 
 static umode_t
@@ -1544,7 +1668,7 @@ static int xe_hwmon_read_label(struct device *dev,
 			*str = "mctrl";
 		else if (channel == CHANNEL_PCIE)
 			*str = "pcie";
-		else if (in_range(channel, CHANNEL_VRAM_N, MAX_VRAM_CHANNELS))
+		else if (in_range(channel, CHANNEL_VRAM_N, hwmon->temp.vram_count))
 			*str = hwmon->temp.vram_label[channel - CHANNEL_VRAM_N];
 		return 0;
 	case hwmon_power:
@@ -1573,7 +1697,7 @@ static const struct hwmon_chip_info hwmon_chip_info = {
 	.info = hwmon_info,
 };
 
-static void
+static int
 xe_hwmon_get_preregistration_info(struct xe_hwmon *hwmon)
 {
 	struct xe_mmio *mmio = xe_root_tile_mmio(hwmon->xe);
@@ -1641,7 +1765,7 @@ xe_hwmon_get_preregistration_info(struct xe_hwmon *hwmon)
 		if (xe_hwmon_is_visible(hwmon, hwmon_fan, hwmon_fan_input, channel))
 			xe_hwmon_fan_input_read(hwmon, channel, &fan_speed);
 
-	xe_hwmon_init_temp_info(hwmon);
+	return xe_hwmon_init_temp_info(hwmon);
 }
 
 int xe_hwmon_register(struct xe_device *xe)
@@ -1670,7 +1794,9 @@ int xe_hwmon_register(struct xe_device *xe)
 	hwmon->xe = xe;
 	xe->hwmon = hwmon;
 
-	xe_hwmon_get_preregistration_info(hwmon);
+	ret = xe_hwmon_get_preregistration_info(hwmon);
+	if (ret)
+		goto err_null_hwmon;
 
 	drm_dbg(&xe->drm, "Register xe hwmon interface\n");
 
@@ -1680,10 +1806,14 @@ int xe_hwmon_register(struct xe_device *xe)
 								hwmon_groups);
 	if (IS_ERR(hwmon->hwmon_dev)) {
 		drm_err(&xe->drm, "Failed to register xe hwmon (%pe)\n", hwmon->hwmon_dev);
-		xe->hwmon = NULL;
-		return PTR_ERR(hwmon->hwmon_dev);
+		ret = PTR_ERR(hwmon->hwmon_dev);
+		goto err_null_hwmon;
 	}
 
 	return 0;
+
+err_null_hwmon:
+	xe->hwmon = NULL;
+	return ret;
 }
 MODULE_IMPORT_NS("INTEL_PMT_TELEMETRY");
diff --git a/drivers/gpu/drm/xe/xe_pci.c b/drivers/gpu/drm/xe/xe_pci.c
index e656fc012902..fa32436ecf6f 100644
--- a/drivers/gpu/drm/xe/xe_pci.c
+++ b/drivers/gpu/drm/xe/xe_pci.c
@@ -416,6 +416,7 @@ static const struct xe_device_desc bmg_desc = {
 	.dma_mask_size = 46,
 	.has_display = true,
 	.has_fan_control = true,
+	.has_fixed_vram_channels = true,
 	.has_flat_ccs = 1,
 	.has_mbx_power_limits = true,
 	.has_mbx_thermal_info = true,
@@ -794,6 +795,7 @@ static int xe_info_init_early(struct xe_device *xe,
 	xe->info.has_cached_pt = desc->has_cached_pt;
 	xe->info.has_drm_ras = desc->has_drm_ras;
 	xe->info.has_fan_control = desc->has_fan_control;
+	xe->info.has_fixed_vram_channels = desc->has_fixed_vram_channels;
 	/* runtime fusing may force flat_ccs to disabled later */
 	xe->info.has_flat_ccs = desc->has_flat_ccs;
 	xe->info.has_mbx_power_limits = desc->has_mbx_power_limits;
diff --git a/drivers/gpu/drm/xe/xe_pci_types.h b/drivers/gpu/drm/xe/xe_pci_types.h
index 0041ec5676d3..4d1048ca7abe 100644
--- a/drivers/gpu/drm/xe/xe_pci_types.h
+++ b/drivers/gpu/drm/xe/xe_pci_types.h
@@ -42,6 +42,7 @@ struct xe_device_desc {
 	u8 has_display:1;
 	u8 has_drm_ras:1;
 	u8 has_fan_control:1;
+	u8 has_fixed_vram_channels:1;
 	u8 has_flat_ccs:1;
 	u8 has_gsc_nvm:1;
 	u8 has_heci_gscfi:1;
-- 
2.25.1

Re: [PATCH v5 09/13] drm/xe/hwmon: Add platform-aware VRAM thermal channel support

[sashiko-bot]

Thank you for your contribution! Sashiko AI review found 2 potential issue(s) to consider:
- [High] hwmon: VRAM temperature array overlaps with CRI control registers
- [Medium] hwmon: VRAM temperature channels truncated for sparse MSU masks
--

commit e9469679c20c906facf743cdf68972d046f4524d
Author: Karthik Poosa <karthik.poosa@intel.com>

drm/xe/hwmon: Add platform-aware VRAM thermal channel support

On CRI, derive the number of available VRAM temperature channels from the
CRI_MSU_VRAM_ENABLE register, where each enabled MSU contributes
VRAM_CHANNELS_PER_MSU channels.
 
Increase the maximum supported VRAM channel count to 80 and use the
derived count to control VRAM sensor enumeration, channel access, and
VRAM label allocation. Add a has_fixed_vram_channels platform flag to
preserve the existing fixed-channel behavior on non-CRI platforms.

> diff --git a/drivers/gpu/drm/xe/regs/xe_pcode_regs.h b/drivers/gpu/drm/xe/regs/xe_pcode_regs.h
> index c63b409d7a821..11916b4f7cfc0 100644
> --- a/drivers/gpu/drm/xe/regs/xe_pcode_regs.h
> +++ b/drivers/gpu/drm/xe/regs/xe_pcode_regs.h
> @@ -29,5 +29,6 @@
>  
>  #define CRI_PACKAGE_ENERGY_STATUS		XE_REG(0x138120)
>  #define CRI_PLATFORM_ENERGY_STATUS		XE_REG(0x138458)
> +#define CRI_MSU_VRAM_ENABLE             XE_REG(0x138340)
>  
>  #endif /* _XE_PCODE_REGS_H_ */
> diff --git a/drivers/gpu/drm/xe/xe_hwmon.c b/drivers/gpu/drm/xe/xe_hwmon.c
> index cf5d51c685360..1b587bd9487e1 100644
> --- a/drivers/gpu/drm/xe/xe_hwmon.c
> +++ b/drivers/gpu/drm/xe/xe_hwmon.c
> @@ -39,7 +39,11 @@ enum xe_hwmon_reg_operation {
>  	REG_READ64,
>  };
>  
> -#define MAX_VRAM_CHANNELS      (16)
> +#define MAX_VRAM_CHANNELS	80

[Severity: High]
Does the VRAM temperature array overlap with the newly added CRI control
registers?

The BMG_VRAM_TEMPERATURE_N(n) macro calculates the register address as
0x138260 + (n * 4). By increasing MAX_VRAM_CHANNELS to 80, this expands the
temperature array significantly.

For channel 56, the address evaluates to 0x138260 + 0xE0 = 0x138340, which
overlaps with the newly added CRI_MSU_VRAM_ENABLE. Channel 57 overlaps with
CRI_PACKAGE_TEMPERATURE (0x138344), and channel 58 overlaps with
CRI_VRAM_TEMPERATURE (0x138348).

Reading VRAM temperature channels >= 56 will read unrelated control or
status registers. This regression can lead to bogus temperature reporting or
potential hardware side-effects on platforms that enable them.

> +#define FIXED_VRAM_CHANNELS	16
> +
> +/* Each MSU enable bit maps to one VRAM subsystem of 4 channels. */
> +#define VRAM_CHANNELS_PER_MSU	4
>  
>  enum xe_hwmon_channel {
[ ... ]
> @@ -805,15 +887,38 @@ static const struct hwmon_channel_info * const hwmon_info[] = {
>  static int xe_hwmon_pcode_read_thermal_info(struct xe_hwmon *hwmon)
>  {
>  	struct xe_tile *root_tile = xe_device_get_root_tile(hwmon->xe);
> +	struct xe_mmio *mmio = xe_root_tile_mmio(hwmon->xe);
>  	u32 config = 0;
>  	int ret;
>  
> +	/*
> +	 * Only CRI reports dynamic VRAM channel state. Fixed-channel platforms
> +	 * set the count up front so those sensors stay visible even if the thermal
> +	 * mailbox reads below fail.
> +	 */
> +	if (hwmon->xe->info.has_fixed_vram_channels)
> +		hwmon->temp.vram_count = FIXED_VRAM_CHANNELS;
> +
> +	if (hwmon->xe->info.platform == XE_CRESCENTISLAND) {
> +		hwmon->temp.msu_mask = xe_mmio_read32(mmio, CRI_MSU_VRAM_ENABLE);
> +		/* Each enabled MSU bit maps to VRAM_CHANNELS_PER_MSU channels. */
> +		hwmon->temp.vram_count = hweight32(hwmon->temp.msu_mask) * VRAM_CHANNELS_PER_MSU;

[Severity: Medium]
Does this calculate the upper bound as the population count rather than the
maximum active index?

If the msu_mask is sparse (e.g., bit 0 and bit 4 enabled, yielding 8 total
channels), vram_count will evaluate to 8.

Later in xe_hwmon_get_reg(), this vram_count is used as an upper bound:
in_range(channel, CHANNEL_VRAM_N, hwmon->temp.vram_count)

When iterating, channels 16-19 (corresponding to bit 4) will fail the
in_range(..., 8) check because their relative index (16) is >= 8. This
regression causes valid hardware sensors for higher-indexed MSUs to be
silently skipped and not exported to userspace.

> +		drm_dbg(&hwmon->xe->drm, "MSU VRAM enable mask 0x%x, VRAM channel count %d\n",
> +			hwmon->temp.msu_mask, hwmon->temp.vram_count);

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20260924111156.2628915-1-karthik.poosa@intel.com?part=9

Re: [PATCH v5 09/13] drm/xe/hwmon: Add platform-aware VRAM thermal channel support

[Poosa, Karthik]

[-- Attachment #1: Type: text/plain, Size: 4695 bytes --]


On 24-09-2026 16:54, sashiko-bot@kernel.org wrote:
> Thank you for your contribution! Sashiko AI review found 2 potential issue(s) to consider:
> - [High] hwmon: VRAM temperature array overlaps with CRI control registers
> - [Medium] hwmon: VRAM temperature channels truncated for sparse MSU masks
> --
>
> commit e9469679c20c906facf743cdf68972d046f4524d
> Author: Karthik Poosa<karthik.poosa@intel.com>
>
> drm/xe/hwmon: Add platform-aware VRAM thermal channel support
>
> On CRI, derive the number of available VRAM temperature channels from the
> CRI_MSU_VRAM_ENABLE register, where each enabled MSU contributes
> VRAM_CHANNELS_PER_MSU channels.
>   
> Increase the maximum supported VRAM channel count to 80 and use the
> derived count to control VRAM sensor enumeration, channel access, and
> VRAM label allocation. Add a has_fixed_vram_channels platform flag to
> preserve the existing fixed-channel behavior on non-CRI platforms.
>
>> diff --git a/drivers/gpu/drm/xe/regs/xe_pcode_regs.h b/drivers/gpu/drm/xe/regs/xe_pcode_regs.h
>> index c63b409d7a821..11916b4f7cfc0 100644
>> --- a/drivers/gpu/drm/xe/regs/xe_pcode_regs.h
>> +++ b/drivers/gpu/drm/xe/regs/xe_pcode_regs.h
>> @@ -29,5 +29,6 @@
>>   
>>   #define CRI_PACKAGE_ENERGY_STATUS		XE_REG(0x138120)
>>   #define CRI_PLATFORM_ENERGY_STATUS		XE_REG(0x138458)
>> +#define CRI_MSU_VRAM_ENABLE             XE_REG(0x138340)
>>   
>>   #endif /* _XE_PCODE_REGS_H_ */
>> diff --git a/drivers/gpu/drm/xe/xe_hwmon.c b/drivers/gpu/drm/xe/xe_hwmon.c
>> index cf5d51c685360..1b587bd9487e1 100644
>> --- a/drivers/gpu/drm/xe/xe_hwmon.c
>> +++ b/drivers/gpu/drm/xe/xe_hwmon.c
>> @@ -39,7 +39,11 @@ enum xe_hwmon_reg_operation {
>>   	REG_READ64,
>>   };
>>   
>> -#define MAX_VRAM_CHANNELS      (16)
>> +#define MAX_VRAM_CHANNELS	80
> [Severity: High]
> Does the VRAM temperature array overlap with the newly added CRI control
> registers?
>
> The BMG_VRAM_TEMPERATURE_N(n) macro calculates the register address as
> 0x138260 + (n * 4). By increasing MAX_VRAM_CHANNELS to 80, this expands the
> temperature array significantly.
>
> For channel 56, the address evaluates to 0x138260 + 0xE0 = 0x138340, which
> overlaps with the newly added CRI_MSU_VRAM_ENABLE. Channel 57 overlaps with
> CRI_PACKAGE_TEMPERATURE (0x138344), and channel 58 overlaps with
> CRI_VRAM_TEMPERATURE (0x138348).
>
> Reading VRAM temperature channels >= 56 will read unrelated control or
> status registers. This regression can lead to bogus temperature reporting or
> potential hardware side-effects on platforms that enable them.
0x138a00 is the offset for CRI_VRAM_TEMPERATURE_N, This is missed 
change, which will be add.
>
>> +#define FIXED_VRAM_CHANNELS	16
>> +
>> +/* Each MSU enable bit maps to one VRAM subsystem of 4 channels. */
>> +#define VRAM_CHANNELS_PER_MSU	4
>>   
>>   enum xe_hwmon_channel {
> [ ... ]
>> @@ -805,15 +887,38 @@ static const struct hwmon_channel_info * const hwmon_info[] = {
>>   static int xe_hwmon_pcode_read_thermal_info(struct xe_hwmon *hwmon)
>>   {
>>   	struct xe_tile *root_tile = xe_device_get_root_tile(hwmon->xe);
>> +	struct xe_mmio *mmio = xe_root_tile_mmio(hwmon->xe);
>>   	u32 config = 0;
>>   	int ret;
>>   
>> +	/*
>> +	 * Only CRI reports dynamic VRAM channel state. Fixed-channel platforms
>> +	 * set the count up front so those sensors stay visible even if the thermal
>> +	 * mailbox reads below fail.
>> +	 */
>> +	if (hwmon->xe->info.has_fixed_vram_channels)
>> +		hwmon->temp.vram_count = FIXED_VRAM_CHANNELS;
>> +
>> +	if (hwmon->xe->info.platform == XE_CRESCENTISLAND) {
>> +		hwmon->temp.msu_mask = xe_mmio_read32(mmio, CRI_MSU_VRAM_ENABLE);
>> +		/* Each enabled MSU bit maps to VRAM_CHANNELS_PER_MSU channels. */
>> +		hwmon->temp.vram_count = hweight32(hwmon->temp.msu_mask) * VRAM_CHANNELS_PER_MSU;
> [Severity: Medium]
> Does this calculate the upper bound as the population count rather than the
> maximum active index?
>
> If the msu_mask is sparse (e.g., bit 0 and bit 4 enabled, yielding 8 total
> channels), vram_count will evaluate to 8.
>
> Later in xe_hwmon_get_reg(), this vram_count is used as an upper bound:
> in_range(channel, CHANNEL_VRAM_N, hwmon->temp.vram_count)
>
> When iterating, channels 16-19 (corresponding to bit 4) will fail the
> in_range(..., 8) check because their relative index (16) is >= 8. This
> regression causes valid hardware sensors for higher-indexed MSUs to be
> silently skipped and not exported to userspace.
>
>> +		drm_dbg(&hwmon->xe->drm, "MSU VRAM enable mask 0x%x, VRAM channel count %d\n",
>> +			hwmon->temp.msu_mask, hwmon->temp.vram_count);
> Agree this will be fixed in next revision. For CRI we shall use the MAX_VRAM_CHANNELS in xe_hwmon_get_reg()

[-- Attachment #2: Type: text/html, Size: 6311 bytes --]

[PATCH v5 10/13] drm/xe/hwmon: use CRI-specific package and VRAM temperature registers

[Karthik Poosa]

Crescent Island uses different MMIO offsets for package and VRAM
temperature than Battlemage. Add CRI-specific register definitions
and select them in xe_hwmon_get_reg() for REG_TEMP handling.

Signed-off-by: Karthik Poosa <karthik.poosa@intel.com>
---
 drivers/gpu/drm/xe/regs/xe_pcode_regs.h |  4 +++-
 drivers/gpu/drm/xe/xe_hwmon.c           | 10 +++++++++-
 2 files changed, 12 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/xe/regs/xe_pcode_regs.h b/drivers/gpu/drm/xe/regs/xe_pcode_regs.h
index 11916b4f7cfc..a6f13d7c3989 100644
--- a/drivers/gpu/drm/xe/regs/xe_pcode_regs.h
+++ b/drivers/gpu/drm/xe/regs/xe_pcode_regs.h
@@ -28,7 +28,9 @@
 #define BMG_PACKAGE_TEMPERATURE			XE_REG(0x138434)
 
 #define CRI_PACKAGE_ENERGY_STATUS		XE_REG(0x138120)
-#define CRI_PLATFORM_ENERGY_STATUS		XE_REG(0x138458)
 #define CRI_MSU_VRAM_ENABLE             XE_REG(0x138340)
+#define CRI_PACKAGE_TEMPERATURE			XE_REG(0x138344)
+#define CRI_VRAM_TEMPERATURE			XE_REG(0x138348)
+#define CRI_PLATFORM_ENERGY_STATUS		XE_REG(0x138458)
 
 #endif /* _XE_PCODE_REGS_H_ */
diff --git a/drivers/gpu/drm/xe/xe_hwmon.c b/drivers/gpu/drm/xe/xe_hwmon.c
index 1b587bd9487e..e1cff5700e7f 100644
--- a/drivers/gpu/drm/xe/xe_hwmon.c
+++ b/drivers/gpu/drm/xe/xe_hwmon.c
@@ -293,7 +293,15 @@ static struct xe_reg xe_hwmon_get_reg(struct xe_hwmon *hwmon, enum xe_hwmon_reg
 
 	switch (hwmon_reg) {
 	case REG_TEMP:
-		if (xe->info.platform == XE_BATTLEMAGE || xe->info.platform == XE_CRESCENTISLAND) {
+		if (xe->info.platform == XE_CRESCENTISLAND) {
+			if (channel == CHANNEL_PKG)
+				return CRI_PACKAGE_TEMPERATURE;
+			else if (channel == CHANNEL_VRAM)
+				return CRI_VRAM_TEMPERATURE;
+			else if (in_range(channel, CHANNEL_VRAM_N, hwmon->temp.vram_count) &&
+				 xe_hwmon_vram_channel_enabled(hwmon, channel - CHANNEL_VRAM_N))
+				return BMG_VRAM_TEMPERATURE_N(channel - CHANNEL_VRAM_N);
+		} else if (xe->info.platform == XE_BATTLEMAGE) {
 			if (channel == CHANNEL_PKG)
 				return BMG_PACKAGE_TEMPERATURE;
 			else if (channel == CHANNEL_VRAM)
-- 
2.25.1

Re: [PATCH v5 10/13] drm/xe/hwmon: use CRI-specific package and VRAM temperature registers

[sashiko-bot]

Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [Medium] drm/xe/hwmon: incorrect BMG register used for CRI per-VRAM channel temperatures
--

commit 8d77f2708804f58e62723e17d986cd5eb1877de7
Author: Karthik Poosa <karthik.poosa@intel.com>

drm/xe/hwmon: use CRI-specific package and VRAM temperature registers

This commit updates the hardware monitoring register accesses to use
Crescent Island (CRI) specific MMIO offsets for package and VRAM
temperatures, as they differ from Battlemage offsets.

> diff --git a/drivers/gpu/drm/xe/xe_hwmon.c b/drivers/gpu/drm/xe/xe_hwmon.c
> index 1b587bd9487e1..e1cff5700e7f9 100644
> --- a/drivers/gpu/drm/xe/xe_hwmon.c
> +++ b/drivers/gpu/drm/xe/xe_hwmon.c
> @@ -293,7 +293,15 @@ static struct xe_reg xe_hwmon_get_reg(struct xe_hwmon *hwmon, enum xe_hwmon_reg
>  
>  	switch (hwmon_reg) {
>  	case REG_TEMP:
> -		if (xe->info.platform == XE_BATTLEMAGE || xe->info.platform == XE_CRESCENTISLAND) {
> +		if (xe->info.platform == XE_CRESCENTISLAND) {
> +			if (channel == CHANNEL_PKG)
> +				return CRI_PACKAGE_TEMPERATURE;
> +			else if (channel == CHANNEL_VRAM)
> +				return CRI_VRAM_TEMPERATURE;
> +			else if (in_range(channel, CHANNEL_VRAM_N, hwmon->temp.vram_count) &&
> +				 xe_hwmon_vram_channel_enabled(hwmon, channel - CHANNEL_VRAM_N))
> +				return BMG_VRAM_TEMPERATURE_N(channel - CHANNEL_VRAM_N);

[Severity: Medium]
Does Crescent Island actually use the Battlemage register offset for
per-channel VRAM temperatures?

If a monitoring daemon reads a sysfs temperature attribute corresponding
to a specific VRAM channel (e.g., temp3_input mapping to CHANNEL_VRAM_N)
on a Crescent Island device, xe_hwmon_get_reg() will return the
BMG_VRAM_TEMPERATURE_N macro in the XE_CRESCENTISLAND branch.

The commit message explicitly notes that Crescent Island uses different MMIO
offsets for package and VRAM temperatures. While the aggregate CHANNEL_PKG
and CHANNEL_VRAM cases were updated to use the new CRI_ macros, the
CHANNEL_VRAM_N fallback still uses the BMG_VRAM_TEMPERATURE_N macro.

Will this cause hardware monitoring tools to read incorrect temperature data
for individual VRAM channels on Crescent Island since it accesses the
Battlemage MMIO offset?

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20260924111156.2628915-1-karthik.poosa@intel.com?part=10

Re: [PATCH v5 10/13] drm/xe/hwmon: use CRI-specific package and VRAM temperature registers

[Poosa, Karthik]

[-- Attachment #1: Type: text/plain, Size: 2469 bytes --]


On 24-09-2026 16:57, sashiko-bot@kernel.org wrote:
> Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
> - [Medium] drm/xe/hwmon: incorrect BMG register used for CRI per-VRAM channel temperatures
> --
>
> commit 8d77f2708804f58e62723e17d986cd5eb1877de7
> Author: Karthik Poosa<karthik.poosa@intel.com>
>
> drm/xe/hwmon: use CRI-specific package and VRAM temperature registers
>
> This commit updates the hardware monitoring register accesses to use
> Crescent Island (CRI) specific MMIO offsets for package and VRAM
> temperatures, as they differ from Battlemage offsets.
>
>> diff --git a/drivers/gpu/drm/xe/xe_hwmon.c b/drivers/gpu/drm/xe/xe_hwmon.c
>> index 1b587bd9487e1..e1cff5700e7f9 100644
>> --- a/drivers/gpu/drm/xe/xe_hwmon.c
>> +++ b/drivers/gpu/drm/xe/xe_hwmon.c
>> @@ -293,7 +293,15 @@ static struct xe_reg xe_hwmon_get_reg(struct xe_hwmon *hwmon, enum xe_hwmon_reg
>>   
>>   	switch (hwmon_reg) {
>>   	case REG_TEMP:
>> -		if (xe->info.platform == XE_BATTLEMAGE || xe->info.platform == XE_CRESCENTISLAND) {
>> +		if (xe->info.platform == XE_CRESCENTISLAND) {
>> +			if (channel == CHANNEL_PKG)
>> +				return CRI_PACKAGE_TEMPERATURE;
>> +			else if (channel == CHANNEL_VRAM)
>> +				return CRI_VRAM_TEMPERATURE;
>> +			else if (in_range(channel, CHANNEL_VRAM_N, hwmon->temp.vram_count) &&
>> +				 xe_hwmon_vram_channel_enabled(hwmon, channel - CHANNEL_VRAM_N))
>> +				return BMG_VRAM_TEMPERATURE_N(channel - CHANNEL_VRAM_N);
> [Severity: Medium]
> Does Crescent Island actually use the Battlemage register offset for
> per-channel VRAM temperatures?
>
> If a monitoring daemon reads a sysfs temperature attribute corresponding
> to a specific VRAM channel (e.g., temp3_input mapping to CHANNEL_VRAM_N)
> on a Crescent Island device, xe_hwmon_get_reg() will return the
> BMG_VRAM_TEMPERATURE_N macro in the XE_CRESCENTISLAND branch.
>
> The commit message explicitly notes that Crescent Island uses different MMIO
> offsets for package and VRAM temperatures. While the aggregate CHANNEL_PKG
> and CHANNEL_VRAM cases were updated to use the new CRI_ macros, the
> CHANNEL_VRAM_N fallback still uses the BMG_VRAM_TEMPERATURE_N macro.
>
> Will this cause hardware monitoring tools to read incorrect temperature data
> for individual VRAM channels on Crescent Island since it accesses the
> Battlemage MMIO offset?
>
>
CRI VRAM individual temperature offset is different, I shall at 
CRI_VRAM_TEMPERATURE_N for it.

[-- Attachment #2: Type: text/html, Size: 3249 bytes --]

[PATCH v5 11/13] drm/xe/hwmon: Decode CRI temperature registers as IEEE-754

[Karthik Poosa]

CRI temperature registers encode package and VRAM temperatures as
IEEE-754 floating-point values. Decode these values before exposing
them through hwmon.
 
Use integer-based IEEE-754 decoding since kernel code does not use
floating-point operations and hwmon reports integer temperatures.

v2: Reject temperatures that overflow long on 32-bit.

v3: Replace magic numbers in xe_hwmon_temperature_decode() with named
    REG_GENMASK()/REG_BIT() defines and use REG_FIELD_GET() for
    extraction. (Rodrigo)

Signed-off-by: Karthik Poosa <karthik.poosa@intel.com>
Assisted-by: LLM
---
 drivers/gpu/drm/xe/xe_hwmon.c | 92 +++++++++++++++++++++++++++++------
 1 file changed, 78 insertions(+), 14 deletions(-)

diff --git a/drivers/gpu/drm/xe/xe_hwmon.c b/drivers/gpu/drm/xe/xe_hwmon.c
index e1cff5700e7f..c411cd375aa1 100644
--- a/drivers/gpu/drm/xe/xe_hwmon.c
+++ b/drivers/gpu/drm/xe/xe_hwmon.c
@@ -1240,6 +1240,69 @@ xe_hwmon_temp_is_visible(struct xe_hwmon *hwmon, u32 attr, int channel)
 	}
 }
 
+#define IEEE754_SIGN		REG_BIT(31)
+#define IEEE754_EXP_MASK	REG_GENMASK(30, 23)
+#define IEEE754_MANTISSA_MASK	REG_GENMASK(22, 0)
+#define IEEE754_EXP_BIAS	127 /* Exponent bias to obtain the actual exponent */
+#define IEEE754_MANTISSA_BITS	23 /* Mantissa width and implicit leading-1 bit position */
+#define IEEE754_EXP_SPECIAL	0xff /* reserved exponent value encoding infinity or NaN */
+
+/**
+ * xe_hwmon_temperature_decode - Decode an IEEE-754 temperature register value
+ * @reg_val: The raw register value to decode
+ *
+ * IEEE-754 single-precision format:
+ *
+ *  31 30                         23 22                         0
+ * +--+-----------------------------+----------------------------+
+ * | S|          exponent           |          fraction          |
+ * +--+-----------------------------+----------------------------+
+ *
+ * value = (-1)^S * 1.fraction * 2^(exponent - 127)
+ *
+ * Return: 0 on success or an error if @reg_val is non-finite or cannot be
+ * represented in millidegrees Celsius.
+ */
+static int xe_hwmon_temperature_decode(u32 reg_val, long *temperature)
+{
+	u32 exponent = REG_FIELD_GET(IEEE754_EXP_MASK, reg_val);
+	u32 mantissa = REG_FIELD_GET(IEEE754_MANTISSA_MASK, reg_val);
+	s64 value;
+	int shift;
+
+	/* Exponent 0xff encodes infinity or NaN. */
+	if (exponent == IEEE754_EXP_SPECIAL)
+		return -EINVAL;
+
+	/* Subnormal values are smaller than one millidegree Celsius. */
+	if (!exponent) {
+		*temperature = 0;
+		return 0;
+	}
+
+	value = (s64)(mantissa | BIT(IEEE754_MANTISSA_BITS)) * MILLIDEGREE_PER_DEGREE;
+	shift = exponent - (IEEE754_EXP_BIAS + IEEE754_MANTISSA_BITS);
+	if (shift >= 0) {
+		if (shift >= BITS_PER_LONG || value > (LONG_MAX >> shift))
+			return -ERANGE;
+		value <<= shift;
+	} else if (shift > -64) {
+		value >>= -shift;
+	} else {
+		value = 0;
+	}
+
+	/* Ensure the magnitude fits in long, which is 32-bit on some arches. */
+	if (value > LONG_MAX)
+		return -ERANGE;
+
+	if (reg_val & IEEE754_SIGN)
+		value = -value;
+
+	*temperature = value;
+	return 0;
+}
+
 static int
 xe_hwmon_temp_read(struct xe_hwmon *hwmon, u32 attr, int channel, long *val)
 {
@@ -1249,26 +1312,27 @@ xe_hwmon_temp_read(struct xe_hwmon *hwmon, u32 attr, int channel, long *val)
 	switch (attr) {
 	case hwmon_temp_input:
 		switch (channel) {
-		case CHANNEL_PKG:
-		case CHANNEL_VRAM:
-			reg_val = xe_mmio_read32(mmio, xe_hwmon_get_reg(hwmon, REG_TEMP, channel));
-
-			/* HW register value is in degrees Celsius, convert to millidegrees. */
-			*val = REG_FIELD_GET(TEMP_MASK, reg_val) * MILLIDEGREE_PER_DEGREE;
-			return 0;
 		case CHANNEL_MCTRL:
 			return get_mc_temp(hwmon, val);
 		case CHANNEL_PCIE:
 			return get_pcie_temp(hwmon, val);
+		case CHANNEL_PKG:
+		case CHANNEL_VRAM:
 		case CHANNEL_VRAM_N...CHANNEL_VRAM_N_MAX:
 			reg_val = xe_mmio_read32(mmio, xe_hwmon_get_reg(hwmon, REG_TEMP, channel));
-			/*
-			 * This temperature format is 24 bit [31:8] signed integer and 8 bit
-			 * [7:0] fraction.
-			 */
-			*val = (s32)(REG_FIELD_GET(TEMP_MASK_VRAM_N, reg_val)) *
-				(REG_FIELD_GET(TEMP_SIGN_MASK, reg_val) ? -1 : 1) *
-				 MILLIDEGREE_PER_DEGREE;
+			if (hwmon->xe->info.platform >= XE_CRESCENTISLAND) {
+				return xe_hwmon_temperature_decode((u32)reg_val, val);
+			} else if (channel >= CHANNEL_VRAM_N) {
+				/*
+				 * This temperature format is 24 bit [31:8] signed integer and 8 bit
+				 * [7:0] fraction for platforms before CRI.
+				 */
+				*val = (s32)REG_FIELD_GET(TEMP_MASK_VRAM_N, reg_val) *
+					(REG_FIELD_GET(TEMP_SIGN_MASK, reg_val) ? -1 : 1) *
+					MILLIDEGREE_PER_DEGREE;
+			} else {
+				*val = REG_FIELD_GET(TEMP_MASK, reg_val) * MILLIDEGREE_PER_DEGREE;
+			}
 			return 0;
 		default:
 			return -EOPNOTSUPP;
-- 
2.25.1

Re: [PATCH v5 11/13] drm/xe/hwmon: Decode CRI temperature registers as IEEE-754

[sashiko-bot]

Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [Medium] hwmon: xe: incorrect IEEE-754 decoding applied to VRAM_N on Crescent Island
--

commit 8039331718fb03f6dfcbe8bbe7a3375383a0c5d2
Author: Karthik Poosa <karthik.poosa@intel.com>

drm/xe/hwmon: Decode CRI temperature registers as IEEE-754

This commit decodes the package and VRAM temperatures on Crescent Island
from an IEEE-754 floating-point format to integer millidegrees.

> diff --git a/drivers/gpu/drm/xe/xe_hwmon.c b/drivers/gpu/drm/xe/xe_hwmon.c
> index e1cff5700e7f9..c411cd375aa1b 100644
> --- a/drivers/gpu/drm/xe/xe_hwmon.c
> +++ b/drivers/gpu/drm/xe/xe_hwmon.c

[ ... ]

> @@ -1249,26 +1312,27 @@ xe_hwmon_temp_read(struct xe_hwmon *hwmon, u32 attr, int channel, long *val)
>  	switch (attr) {
>  	case hwmon_temp_input:
>  		switch (channel) {
> -		case CHANNEL_PKG:
> -		case CHANNEL_VRAM:
> -			reg_val = xe_mmio_read32(mmio, xe_hwmon_get_reg(hwmon, REG_TEMP, channel));
> -
> -			/* HW register value is in degrees Celsius, convert to millidegrees. */
> -			*val = REG_FIELD_GET(TEMP_MASK, reg_val) * MILLIDEGREE_PER_DEGREE;
> -			return 0;
>  		case CHANNEL_MCTRL:
>  			return get_mc_temp(hwmon, val);
>  		case CHANNEL_PCIE:
>  			return get_pcie_temp(hwmon, val);
> +		case CHANNEL_PKG:
> +		case CHANNEL_VRAM:
>  		case CHANNEL_VRAM_N...CHANNEL_VRAM_N_MAX:
>  			reg_val = xe_mmio_read32(mmio, xe_hwmon_get_reg(hwmon, REG_TEMP, channel));
> -			/*
> -			 * This temperature format is 24 bit [31:8] signed integer and 8 bit
> -			 * [7:0] fraction.
> -			 */
> -			*val = (s32)(REG_FIELD_GET(TEMP_MASK_VRAM_N, reg_val)) *
> -				(REG_FIELD_GET(TEMP_SIGN_MASK, reg_val) ? -1 : 1) *
> -				 MILLIDEGREE_PER_DEGREE;
> +			if (hwmon->xe->info.platform >= XE_CRESCENTISLAND) {
> +				return xe_hwmon_temperature_decode((u32)reg_val, val);

[Severity: Medium]
Will this indiscriminately apply IEEE-754 decoding to all VRAM channels on
Crescent Island, including CHANNEL_VRAM_N?

Looking at xe_hwmon_get_reg(), VRAM_N on XE_CRESCENTISLAND still uses
the legacy BMG_VRAM_TEMPERATURE_N registers:

	case REG_TEMP:
		if (xe->info.platform == XE_CRESCENTISLAND) {
			if (channel == CHANNEL_PKG)
				...
			else if (in_range(channel, CHANNEL_VRAM_N, hwmon->temp.vram_count) &&
				 xe_hwmon_vram_channel_enabled(hwmon, channel - CHANNEL_VRAM_N))
				return BMG_VRAM_TEMPERATURE_N(channel - CHANNEL_VRAM_N);

Since BMG_VRAM_TEMPERATURE_N registers encode temperatures in a 24.8
fixed-point format, parsing them as IEEE-754 floating-point values will
result in incorrectly reporting sensor values when reading tempN_input via
sysfs.

Could this condition be narrowed to exclude CHANNEL_VRAM_N?

> +			} else if (channel >= CHANNEL_VRAM_N) {
> +				/*
> +				 * This temperature format is 24 bit [31:8] signed integer and 8 bit
> +				 * [7:0] fraction for platforms before CRI.
> +				 */
> +				*val = (s32)REG_FIELD_GET(TEMP_MASK_VRAM_N, reg_val) *
> +					(REG_FIELD_GET(TEMP_SIGN_MASK, reg_val) ? -1 : 1) *
> +					MILLIDEGREE_PER_DEGREE;
> +			} else {
> +				*val = REG_FIELD_GET(TEMP_MASK, reg_val) * MILLIDEGREE_PER_DEGREE;
> +			}
>  			return 0;
>  		default:
>  			return -EOPNOTSUPP;

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20260924111156.2628915-1-karthik.poosa@intel.com?part=11

[PATCH v5 12/13] drm/xe/hwmon: Update memory controller temperature offset for CRI

[Karthik Poosa]

On CRI the memory controller temperatures moved in the READ_THERMAL_DATA
output: they now occupy bytes 16..19 instead of starting at byte 2.

Read and average the CRI memory controller sensors from bytes 16..19,
keeping the existing byte 2..count-1 range for earlier platforms. Only
the group(s) covering the used bytes are fetched.

Signed-off-by: Karthik Poosa <karthik.poosa@intel.com>
---
 drivers/gpu/drm/xe/xe_hwmon.c | 19 ++++++++++++++++---
 1 file changed, 16 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/xe/xe_hwmon.c b/drivers/gpu/drm/xe/xe_hwmon.c
index c411cd375aa1..fef2166989ba 100644
--- a/drivers/gpu/drm/xe/xe_hwmon.c
+++ b/drivers/gpu/drm/xe/xe_hwmon.c
@@ -109,6 +109,10 @@ enum sensor_attr_power {
 /* Index of memory controller in READ_THERMAL_DATA output */
 #define TEMP_INDEX_MCTRL	2
 
+/* On CRI the memory controller temperatures are READ_THERMAL_DATA bytes 16..19. */
+#define CRI_TEMP_INDEX_MCTRL	16
+#define CRI_TEMP_MCTRL_COUNT	4
+
 /* Mailbox sentinel reported for an unavailable temperature sensor */
 #define TEMP_MBX_INVALID	0xFF
 
@@ -964,10 +968,19 @@ static int mbx_temp_decode(u8 value)
 static int get_mc_temp(struct xe_hwmon *hwmon, long *val)
 {
 	struct xe_tile *root_tile = xe_device_get_root_tile(hwmon->xe);
-	int ret, i, count = 0;
+	int ret, i, start, end, count = 0;
 	s32 average = 0;
 
-	for (i = 0; i < DIV_ROUND_UP(hwmon->temp.count, sizeof(u32)); i++) {
+	/* CRI relocated the memory controller temperatures to READ_THERMAL_DATA bytes 16..19. */
+	if (hwmon->xe->info.platform >= XE_CRESCENTISLAND) {
+		start = CRI_TEMP_INDEX_MCTRL;
+		end = CRI_TEMP_INDEX_MCTRL + CRI_TEMP_MCTRL_COUNT;
+	} else {
+		start = TEMP_INDEX_MCTRL;
+		end = hwmon->temp.count - 1;
+	}
+
+	for (i = start / sizeof(u32); i < DIV_ROUND_UP(end, sizeof(u32)); i++) {
 		ret = xe_pcode_read(root_tile, PCODE_MBOX(PCODE_THERMAL_INFO, READ_THERMAL_DATA, i),
 				    &hwmon->temp.dword[i], NULL);
 		if (ret)
@@ -976,7 +989,7 @@ static int get_mc_temp(struct xe_hwmon *hwmon, long *val)
 			hwmon->temp.dword[i]);
 	}
 
-	for (i = TEMP_INDEX_MCTRL; i < hwmon->temp.count - 1; i++) {
+	for (i = start; i < end; i++) {
 		if (!mbx_temp_valid(hwmon, hwmon->temp.value[i]))
 			continue;
 		average += mbx_temp_decode(hwmon->temp.value[i]);
-- 
2.25.1

[PATCH v5 13/13] drm/xe/hwmon: Update PCIE temperature sensor offset for CRI

[Karthik Poosa]

On Crescent Island, the PCIe temperature sensor is reported in
READ_THERMAL_DATA group 5, byte 0. Add support for reading the sensor
from this mailbox location.

Signed-off-by: Karthik Poosa <karthik.poosa@intel.com>
---
 drivers/gpu/drm/xe/xe_hwmon.c | 14 +++++++++++---
 1 file changed, 11 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/xe/xe_hwmon.c b/drivers/gpu/drm/xe/xe_hwmon.c
index fef2166989ba..f6860da0bf0c 100644
--- a/drivers/gpu/drm/xe/xe_hwmon.c
+++ b/drivers/gpu/drm/xe/xe_hwmon.c
@@ -113,6 +113,9 @@ enum sensor_attr_power {
 #define CRI_TEMP_INDEX_MCTRL	16
 #define CRI_TEMP_MCTRL_COUNT	4
 
+/* On CRI the PCIe temperature is READ_THERMAL_DATA byte 20 (group 5, low byte). */
+#define CRI_PCIE_SENSOR_GROUP_ID	5
+
 /* Mailbox sentinel reported for an unavailable temperature sensor */
 #define TEMP_MBX_INVALID	0xFF
 
@@ -1012,16 +1015,21 @@ static int get_mc_temp(struct xe_hwmon *hwmon, long *val)
 static int get_pcie_temp(struct xe_hwmon *hwmon, long *val)
 {
 	struct xe_tile *root_tile = xe_device_get_root_tile(hwmon->xe);
+	u32 group = PCIE_SENSOR_GROUP_ID;
 	u32 data = 0;
 	int ret;
 
+	/* CRI relocated the PCIe temperature to a different data group. */
+	if (hwmon->xe->info.platform == XE_CRESCENTISLAND)
+		group = CRI_PCIE_SENSOR_GROUP_ID;
+
 	ret = xe_pcode_read(root_tile, PCODE_MBOX(PCODE_THERMAL_INFO, READ_THERMAL_DATA,
-						  PCIE_SENSOR_GROUP_ID), &data, NULL);
+						  group), &data, NULL);
 	if (ret)
 		return ret;
 
-	/* Sensor offset is different for G21 */
-	if (hwmon->xe->info.subplatform != XE_SUBPLATFORM_BATTLEMAGE_G21)
+	if (hwmon->xe->info.subplatform != XE_SUBPLATFORM_BATTLEMAGE_G21 &&
+	    hwmon->xe->info.platform != XE_CRESCENTISLAND)
 		data = REG_FIELD_GET(PCIE_SENSOR_MASK, data);
 
 	data = REG_FIELD_GET(TEMP_MASK, data);
-- 
2.25.1

✓ CI.KUnit: success for drm/xe/hwmon: Update hwmon thermal mailbox (rev2)

[Patchwork]

== Series Details ==

Series: drm/xe/hwmon: Update hwmon thermal mailbox (rev2)
URL   : https://patchwork.freedesktop.org/series/174898/
State : success

== Summary ==

+ trap cleanup EXIT
+ kunitconfigs=('/kernel/drivers/gpu/tests/.kunitconfig' '/kernel/drivers/gpu/drm/xe/.kunitconfig' '/kernel/drivers/gpu/drm/tests/.kunitconfig' '/kernel/drivers/gpu/drm/ttm/tests/.kunitconfig' '/kernel/drivers/dma-buf/.kunitconfig')
+ for kcfg in "${kunitconfigs[@]}"
+ [[ ! -f /kernel/drivers/gpu/tests/.kunitconfig ]]
+ /kernel/tools/testing/kunit/kunit.py run --kunitconfig /kernel/drivers/gpu/tests/.kunitconfig
[11:38:19] Configuring KUnit Kernel ...
Generating .config ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
[11:38:23] Building KUnit Kernel ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
Building with:
$ make all compile_commands.json scripts_gdb ARCH=um O=.kunit --jobs=48
[11:38:43] Starting KUnit Kernel (1/1)...
[11:38:43] ============================================================
Running tests with:
$ .kunit/linux kunit.enable=1 mem=1G console=tty kunit_shutdown=halt
[11:38:43] ============= refcount_interrupt (4 subtests) ==============
[11:38:43] [PASSED] test_single_irq_change
[11:38:43] [PASSED] test_nested_irq_change
[11:38:43] [PASSED] test_multiple_irq_change
[11:38:43] [PASSED] test_irq_save
[11:38:43] =============== [PASSED] refcount_interrupt ================
[11:38:43] ================= gpu_buddy (14 subtests) ==================
[11:38:43] [PASSED] gpu_test_buddy_alloc_limit
[11:38:43] [PASSED] gpu_test_buddy_alloc_optimistic
[11:38:43] [PASSED] gpu_test_buddy_alloc_pessimistic
[11:38:43] [PASSED] gpu_test_buddy_alloc_pathological
[11:38:43] [PASSED] gpu_test_buddy_alloc_contiguous
[11:38:43] [PASSED] gpu_test_buddy_alloc_clear
[11:38:43] [PASSED] gpu_test_buddy_alloc_range
[11:38:44] [PASSED] gpu_test_buddy_alloc_range_bias
[11:38:44] [PASSED] gpu_test_buddy_fragmentation_performance
[11:38:45] [PASSED] gpu_test_buddy_dirty_tracker_performance
[11:38:45] [PASSED] gpu_test_buddy_alloc_exceeds_max_order
[11:38:45] [PASSED] gpu_test_buddy_offset_aligned_allocation
[11:38:45] [PASSED] gpu_test_buddy_subtree_offset_alignment_stress
[11:38:45] [PASSED] gpu_test_buddy_addr_to_block
[11:38:45] ==================== [PASSED] gpu_buddy ====================
[11:38:45] ============================================================
[11:38:45] Testing complete. Ran 18 tests: passed: 18
[11:38:45] Elapsed time: 26.601s total, 4.297s configuring, 20.436s building, 1.828s running

+ for kcfg in "${kunitconfigs[@]}"
+ [[ ! -f /kernel/drivers/gpu/drm/xe/.kunitconfig ]]
+ /kernel/tools/testing/kunit/kunit.py run --kunitconfig /kernel/drivers/gpu/drm/xe/.kunitconfig
[11:38:45] Configuring KUnit Kernel ...
Regenerating .config ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
[11:38:47] Building KUnit Kernel ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
Building with:
$ make all compile_commands.json scripts_gdb ARCH=um O=.kunit --jobs=48
[11:39:21] Starting KUnit Kernel (1/1)...
[11:39:21] ============================================================
Running tests with:
$ .kunit/linux kunit.enable=1 mem=1G console=tty kunit_shutdown=halt
[11:39:22] ============= refcount_interrupt (4 subtests) ==============
[11:39:22] [PASSED] test_single_irq_change
[11:39:22] [PASSED] test_nested_irq_change
[11:39:22] [PASSED] test_multiple_irq_change
[11:39:22] [PASSED] test_irq_save
[11:39:22] =============== [PASSED] refcount_interrupt ================
[11:39:22] ================== guc_buf (11 subtests) ===================
[11:39:22] [PASSED] test_smallest
[11:39:22] [PASSED] test_largest
[11:39:22] [PASSED] test_granular
[11:39:22] [PASSED] test_unique
[11:39:22] [PASSED] test_overlap
[11:39:22] [PASSED] test_reusable
[11:39:22] [PASSED] test_too_big
[11:39:22] [PASSED] test_flush
[11:39:22] [PASSED] test_lookup
[11:39:22] [PASSED] test_data
[11:39:22] [PASSED] test_class
[11:39:22] ===================== [PASSED] guc_buf =====================
[11:39:22] =================== guc_dbm (7 subtests) ===================
[11:39:22] [PASSED] test_empty
[11:39:22] [PASSED] test_default
[11:39:22] ======================== test_size  ========================
[11:39:22] [PASSED] 4
[11:39:22] [PASSED] 8
[11:39:22] [PASSED] 32
[11:39:22] [PASSED] 256
[11:39:22] ==================== [PASSED] test_size ====================
[11:39:22] ======================= test_reuse  ========================
[11:39:22] [PASSED] 4
[11:39:22] [PASSED] 8
[11:39:22] [PASSED] 32
[11:39:22] [PASSED] 256
[11:39:22] =================== [PASSED] test_reuse ====================
[11:39:22] =================== test_range_overlap  ====================
[11:39:22] [PASSED] 4
[11:39:22] [PASSED] 8
[11:39:22] [PASSED] 32
[11:39:22] [PASSED] 256
[11:39:22] =============== [PASSED] test_range_overlap ================
[11:39:22] =================== test_range_compact  ====================
[11:39:22] [PASSED] 4
[11:39:22] [PASSED] 8
[11:39:22] [PASSED] 32
[11:39:22] [PASSED] 256
[11:39:22] =============== [PASSED] test_range_compact ================
[11:39:22] ==================== test_range_spare  =====================
[11:39:22] [PASSED] 4
[11:39:22] [PASSED] 8
[11:39:22] [PASSED] 32
[11:39:22] [PASSED] 256
[11:39:22] ================ [PASSED] test_range_spare =================
[11:39:22] ===================== [PASSED] guc_dbm =====================
[11:39:22] =================== guc_idm (6 subtests) ===================
[11:39:22] [PASSED] bad_init
[11:39:22] [PASSED] no_init
[11:39:22] [PASSED] init_fini
[11:39:22] [PASSED] check_used
[11:39:22] [PASSED] check_quota
[11:39:22] [PASSED] check_all
[11:39:22] ===================== [PASSED] guc_idm =====================
[11:39:22] ============== guc_klv_helpers (13 subtests) ===============
[11:39:22] [PASSED] test_count
[11:39:22] [PASSED] test_encode_u32
[11:39:22] [PASSED] test_encode_u64
[11:39:22] [PASSED] test_encode_string
[11:39:22] [PASSED] test_encode_object_raw
[11:39:22] [PASSED] test_encode_object_klv
[11:39:22] [PASSED] test_encode_object_nested
[11:39:22] [PASSED] test_encode_object_basic
[11:39:22] ===================== test_decode_u16  =====================
[11:39:22] [PASSED] empty
[11:39:22] [PASSED] valid
[11:39:22] [PASSED] max
[11:39:22] [PASSED] big
[11:39:22] [PASSED] long
[11:39:22] ================= [PASSED] test_decode_u16 =================
[11:39:22] ===================== test_decode_u32  =====================
[11:39:22] [PASSED] empty
[11:39:22] [PASSED] valid
[11:39:22] [PASSED] max
[11:39:22] [PASSED] long
[11:39:22] ================= [PASSED] test_decode_u32 =================
[11:39:22] ===================== test_decode_u64  =====================
[11:39:22] [PASSED] empty
[11:39:22] [PASSED] short
[11:39:22] [PASSED] valid
[11:39:22] [PASSED] max
[11:39:22] [PASSED] long
[11:39:22] ================= [PASSED] test_decode_u64 =================
[11:39:22] ===================== test_decode_str  =====================
[11:39:22] [PASSED] empty
[11:39:22] [PASSED] one
[11:39:22] [PASSED] one_trash
[11:39:22] [PASSED] two
[11:39:22] [PASSED] two_trash
[11:39:22] [PASSED] three
[11:39:22] [PASSED] dword
[11:39:22] [PASSED] four
[11:39:22] [PASSED] five
[11:39:22] [PASSED] six
[11:39:22] [PASSED] seven
[11:39:22] [PASSED] qword
[11:39:22] ================= [PASSED] test_decode_str =================
[11:39:22] [PASSED] test_print
[11:39:22] ================= [PASSED] guc_klv_helpers =================
[11:39:22] =================== xe_log (4 subtests) ====================
[11:39:22] [PASSED] demo_cper
[11:39:22] [PASSED] demo_dmesg
[11:39:22] ======================= test_dmesg  ========================
[11:39:22] [PASSED] test_fatal
[11:39:22] [PASSED] test_fatal_tile
[11:39:22] [PASSED] test_fatal_gt
[11:39:22] [PASSED] test_fatal_comp
[11:39:22] [PASSED] test_fatal_comp_tile
[11:39:22] [PASSED] test_fatal_comp_gt
[11:39:22] [PASSED] test_fatal_all
[11:39:22] [PASSED] test_recoverable
[11:39:22] [PASSED] test_recoverable_tile
[11:39:22] [PASSED] test_recoverable_gt
[11:39:22] [PASSED] test_recoverable_comp
[11:39:22] [PASSED] test_recoverable_comp_tile
[11:39:22] [PASSED] test_recoverable_comp_gt
[11:39:22] [PASSED] test_recoverable_all
[11:39:22] [PASSED] test_info
[11:39:22] [PASSED] test_info_tile
[11:39:22] [PASSED] test_info_gt
[11:39:22] [PASSED] test_info_err
[11:39:22] [PASSED] test_info_comp
[11:39:22] [PASSED] test_info_comp_tile
[11:39:22] [PASSED] test_info_comp_gt
[11:39:22] [PASSED] test_info_all
[11:39:22] [PASSED] test_hw_fatal
[11:39:22] [PASSED] test_hw_recoverable
[11:39:22] [PASSED] test_hw_corrected
[11:39:22] [PASSED] test_hw_informational
[11:39:22] =================== [PASSED] test_dmesg ====================
[11:39:22] ====================== test_invalid  =======================
[11:39:22] [SKIPPED] no-component no-location no-warn (requires CONFIG_DRM_XE_DEBUG)
[11:39:22] [SKIPPED] reserved location (requires CONFIG_DRM_XE_DEBUG)
[11:39:22] [SKIPPED] unknown location (requires CONFIG_DRM_XE_DEBUG)
[11:39:22] [SKIPPED] nonzero-device-id location (requires CONFIG_DRM_XE_DEBUG)
[11:39:22] [SKIPPED] invalid-tile-id location (requires CONFIG_DRM_XE_DEBUG)
[11:39:22] [SKIPPED] invalid-gt-id location (requires CONFIG_DRM_XE_DEBUG)
[11:39:22] [SKIPPED] unknown component class (requires CONFIG_DRM_XE_DEBUG)
[11:39:22] [SKIPPED] unknown system component (requires CONFIG_DRM_XE_DEBUG)
[11:39:22] [SKIPPED] unknown hardware component (requires CONFIG_DRM_XE_DEBUG)
[11:39:22] [SKIPPED] unknown component and location (requires CONFIG_DRM_XE_DEBUG)
[11:39:22] ================== [SKIPPED] test_invalid ==================
[11:39:22] ===================== [PASSED] xe_log ======================
[11:39:22] ================== no_relay (3 subtests) ===================
[11:39:22] [PASSED] xe_drops_guc2pf_if_not_ready
[11:39:22] [PASSED] xe_drops_guc2vf_if_not_ready
[11:39:22] [PASSED] xe_rejects_send_if_not_ready
[11:39:22] ==================== [PASSED] no_relay =====================
[11:39:22] ================== pf_relay (14 subtests) ==================
[11:39:22] [PASSED] pf_rejects_guc2pf_too_short
[11:39:22] [PASSED] pf_rejects_guc2pf_too_long
[11:39:22] [PASSED] pf_rejects_guc2pf_no_payload
[11:39:22] [PASSED] pf_fails_no_payload
[11:39:22] [PASSED] pf_fails_bad_origin
[11:39:22] [PASSED] pf_fails_bad_type
[11:39:22] [PASSED] pf_txn_reports_error
[11:39:22] [PASSED] pf_txn_sends_pf2guc
[11:39:22] [PASSED] pf_sends_pf2guc
[11:39:22] [SKIPPED] pf_loopback_nop (requires CONFIG_DRM_XE_DEBUG_SRIOV)
[11:39:22] [SKIPPED] pf_loopback_echo (requires CONFIG_DRM_XE_DEBUG_SRIOV)
[11:39:22] [SKIPPED] pf_loopback_fail (requires CONFIG_DRM_XE_DEBUG_SRIOV)
[11:39:22] [SKIPPED] pf_loopback_busy (requires CONFIG_DRM_XE_DEBUG_SRIOV)
[11:39:22] [SKIPPED] pf_loopback_retry (requires CONFIG_DRM_XE_DEBUG_SRIOV)
[11:39:22] ==================== [PASSED] pf_relay =====================
[11:39:22] ================== vf_relay (3 subtests) ===================
[11:39:22] [PASSED] vf_rejects_guc2vf_too_short
[11:39:22] [PASSED] vf_rejects_guc2vf_too_long
[11:39:22] [PASSED] vf_rejects_guc2vf_no_payload
[11:39:22] ==================== [PASSED] vf_relay =====================
[11:39:22] ================ pf_gt_config (9 subtests) =================
[11:39:22] [PASSED] fair_contexts_1vf
[11:39:22] [PASSED] fair_doorbells_1vf
[11:39:22] [PASSED] fair_ggtt_1vf
[11:39:22] ====================== fair_vram_1vf  ======================
[11:39:22] [PASSED] 3.50 GiB
[11:39:22] [PASSED] 11.5 GiB
[11:39:22] [PASSED] 15.5 GiB
[11:39:22] [PASSED] 31.5 GiB
[11:39:22] [PASSED] 63.5 GiB
[11:39:22] [PASSED] 1.91 GiB
[11:39:22] ================== [PASSED] fair_vram_1vf ==================
[11:39:22] ================ fair_vram_1vf_admin_only  =================
[11:39:22] [PASSED] 3.50 GiB
[11:39:22] [PASSED] 11.5 GiB
[11:39:22] [PASSED] 15.5 GiB
[11:39:22] [PASSED] 31.5 GiB
[11:39:22] [PASSED] 63.5 GiB
[11:39:22] [PASSED] 1.91 GiB
[11:39:22] ============ [PASSED] fair_vram_1vf_admin_only =============
[11:39:22] ====================== fair_contexts  ======================
[11:39:22] [PASSED] 1 VF
[11:39:22] [PASSED] 2 VFs
[11:39:22] [PASSED] 3 VFs
[11:39:22] [PASSED] 4 VFs
[11:39:22] [PASSED] 5 VFs
[11:39:22] [PASSED] 6 VFs
[11:39:22] [PASSED] 7 VFs
[11:39:22] [PASSED] 8 VFs
[11:39:22] [PASSED] 9 VFs
[11:39:22] [PASSED] 10 VFs
[11:39:22] [PASSED] 11 VFs
[11:39:22] [PASSED] 12 VFs
[11:39:22] [PASSED] 13 VFs
[11:39:22] [PASSED] 14 VFs
[11:39:22] [PASSED] 15 VFs
[11:39:22] [PASSED] 16 VFs
[11:39:22] [PASSED] 17 VFs
[11:39:22] [PASSED] 18 VFs
[11:39:22] [PASSED] 19 VFs
[11:39:22] [PASSED] 20 VFs
[11:39:22] [PASSED] 21 VFs
[11:39:22] [PASSED] 22 VFs
[11:39:22] [PASSED] 23 VFs
[11:39:22] [PASSED] 24 VFs
[11:39:22] [PASSED] 25 VFs
[11:39:22] [PASSED] 26 VFs
[11:39:22] [PASSED] 27 VFs
[11:39:22] [PASSED] 28 VFs
[11:39:22] [PASSED] 29 VFs
[11:39:22] [PASSED] 30 VFs
[11:39:22] [PASSED] 31 VFs
[11:39:22] [PASSED] 32 VFs
[11:39:22] [PASSED] 33 VFs
[11:39:22] [PASSED] 34 VFs
[11:39:22] [PASSED] 35 VFs
[11:39:22] [PASSED] 36 VFs
[11:39:22] [PASSED] 37 VFs
[11:39:22] [PASSED] 38 VFs
[11:39:22] [PASSED] 39 VFs
[11:39:22] [PASSED] 40 VFs
[11:39:22] [PASSED] 41 VFs
[11:39:22] [PASSED] 42 VFs
[11:39:22] [PASSED] 43 VFs
[11:39:22] [PASSED] 44 VFs
[11:39:22] [PASSED] 45 VFs
[11:39:22] [PASSED] 46 VFs
[11:39:22] [PASSED] 47 VFs
[11:39:22] [PASSED] 48 VFs
[11:39:22] [PASSED] 49 VFs
[11:39:22] [PASSED] 50 VFs
[11:39:22] [PASSED] 51 VFs
[11:39:22] [PASSED] 52 VFs
[11:39:22] [PASSED] 53 VFs
[11:39:22] [PASSED] 54 VFs
[11:39:22] [PASSED] 55 VFs
[11:39:22] [PASSED] 56 VFs
[11:39:22] [PASSED] 57 VFs
[11:39:22] [PASSED] 58 VFs
[11:39:22] [PASSED] 59 VFs
[11:39:22] [PASSED] 60 VFs
[11:39:22] [PASSED] 61 VFs
[11:39:22] [PASSED] 62 VFs
[11:39:22] [PASSED] 63 VFs
[11:39:22] ================== [PASSED] fair_contexts ==================
[11:39:22] ===================== fair_doorbells  ======================
[11:39:22] [PASSED] 1 VF
[11:39:22] [PASSED] 2 VFs
[11:39:22] [PASSED] 3 VFs
[11:39:22] [PASSED] 4 VFs
[11:39:22] [PASSED] 5 VFs
[11:39:22] [PASSED] 6 VFs
[11:39:22] [PASSED] 7 VFs
[11:39:22] [PASSED] 8 VFs
[11:39:22] [PASSED] 9 VFs
[11:39:22] [PASSED] 10 VFs
[11:39:22] [PASSED] 11 VFs
[11:39:22] [PASSED] 12 VFs
[11:39:22] [PASSED] 13 VFs
[11:39:22] [PASSED] 14 VFs
[11:39:22] [PASSED] 15 VFs
[11:39:22] [PASSED] 16 VFs
[11:39:22] [PASSED] 17 VFs
[11:39:22] [PASSED] 18 VFs
[11:39:22] [PASSED] 19 VFs
[11:39:22] [PASSED] 20 VFs
[11:39:22] [PASSED] 21 VFs
[11:39:22] [PASSED] 22 VFs
[11:39:22] [PASSED] 23 VFs
[11:39:22] [PASSED] 24 VFs
[11:39:22] [PASSED] 25 VFs
[11:39:22] [PASSED] 26 VFs
[11:39:22] [PASSED] 27 VFs
[11:39:22] [PASSED] 28 VFs
[11:39:22] [PASSED] 29 VFs
[11:39:22] [PASSED] 30 VFs
[11:39:22] [PASSED] 31 VFs
[11:39:22] [PASSED] 32 VFs
[11:39:22] [PASSED] 33 VFs
[11:39:22] [PASSED] 34 VFs
[11:39:22] [PASSED] 35 VFs
[11:39:22] [PASSED] 36 VFs
[11:39:22] [PASSED] 37 VFs
[11:39:22] [PASSED] 38 VFs
[11:39:22] [PASSED] 39 VFs
[11:39:22] [PASSED] 40 VFs
[11:39:22] [PASSED] 41 VFs
[11:39:22] [PASSED] 42 VFs
[11:39:22] [PASSED] 43 VFs
[11:39:22] [PASSED] 44 VFs
[11:39:22] [PASSED] 45 VFs
[11:39:22] [PASSED] 46 VFs
[11:39:22] [PASSED] 47 VFs
[11:39:22] [PASSED] 48 VFs
[11:39:22] [PASSED] 49 VFs
[11:39:22] [PASSED] 50 VFs
[11:39:22] [PASSED] 51 VFs
[11:39:22] [PASSED] 52 VFs
[11:39:22] [PASSED] 53 VFs
[11:39:22] [PASSED] 54 VFs
[11:39:22] [PASSED] 55 VFs
[11:39:22] [PASSED] 56 VFs
[11:39:22] [PASSED] 57 VFs
[11:39:22] [PASSED] 58 VFs
[11:39:22] [PASSED] 59 VFs
[11:39:22] [PASSED] 60 VFs
[11:39:22] [PASSED] 61 VFs
[11:39:22] [PASSED] 62 VFs
[11:39:22] [PASSED] 63 VFs
[11:39:22] ================= [PASSED] fair_doorbells ==================
[11:39:22] ======================== fair_ggtt  ========================
[11:39:22] [PASSED] 1 VF
[11:39:22] [PASSED] 2 VFs
[11:39:22] [PASSED] 3 VFs
[11:39:22] [PASSED] 4 VFs
[11:39:22] [PASSED] 5 VFs
[11:39:22] [PASSED] 6 VFs
[11:39:22] [PASSED] 7 VFs
[11:39:22] [PASSED] 8 VFs
[11:39:22] [PASSED] 9 VFs
[11:39:22] [PASSED] 10 VFs
[11:39:22] [PASSED] 11 VFs
[11:39:22] [PASSED] 12 VFs
[11:39:22] [PASSED] 13 VFs
[11:39:22] [PASSED] 14 VFs
[11:39:22] [PASSED] 15 VFs
[11:39:22] [PASSED] 16 VFs
[11:39:22] [PASSED] 17 VFs
[11:39:22] [PASSED] 18 VFs
[11:39:22] [PASSED] 19 VFs
[11:39:22] [PASSED] 20 VFs
[11:39:22] [PASSED] 21 VFs
[11:39:22] [PASSED] 22 VFs
[11:39:22] [PASSED] 23 VFs
[11:39:22] [PASSED] 24 VFs
[11:39:22] [PASSED] 25 VFs
[11:39:22] [PASSED] 26 VFs
[11:39:22] [PASSED] 27 VFs
[11:39:22] [PASSED] 28 VFs
[11:39:22] [PASSED] 29 VFs
[11:39:22] [PASSED] 30 VFs
[11:39:22] [PASSED] 31 VFs
[11:39:22] [PASSED] 32 VFs
[11:39:22] [PASSED] 33 VFs
[11:39:22] [PASSED] 34 VFs
[11:39:22] [PASSED] 35 VFs
[11:39:22] [PASSED] 36 VFs
[11:39:22] [PASSED] 37 VFs
[11:39:22] [PASSED] 38 VFs
[11:39:22] [PASSED] 39 VFs
[11:39:22] [PASSED] 40 VFs
[11:39:22] [PASSED] 41 VFs
[11:39:22] [PASSED] 42 VFs
[11:39:22] [PASSED] 43 VFs
[11:39:22] [PASSED] 44 VFs
[11:39:22] [PASSED] 45 VFs
[11:39:22] [PASSED] 46 VFs
[11:39:22] [PASSED] 47 VFs
[11:39:22] [PASSED] 48 VFs
[11:39:22] [PASSED] 49 VFs
[11:39:22] [PASSED] 50 VFs
[11:39:22] [PASSED] 51 VFs
[11:39:22] [PASSED] 52 VFs
[11:39:22] [PASSED] 53 VFs
[11:39:22] [PASSED] 54 VFs
[11:39:22] [PASSED] 55 VFs
[11:39:22] [PASSED] 56 VFs
[11:39:22] [PASSED] 57 VFs
[11:39:22] [PASSED] 58 VFs
[11:39:22] [PASSED] 59 VFs
[11:39:22] [PASSED] 60 VFs
[11:39:22] [PASSED] 61 VFs
[11:39:22] [PASSED] 62 VFs
[11:39:22] [PASSED] 63 VFs
[11:39:22] ==================== [PASSED] fair_ggtt ====================
[11:39:22] ======================== fair_vram  ========================
[11:39:22] [PASSED] 1 VF
[11:39:22] [PASSED] 2 VFs
[11:39:22] [PASSED] 3 VFs
[11:39:22] [PASSED] 4 VFs
[11:39:22] [PASSED] 5 VFs
[11:39:22] [PASSED] 6 VFs
[11:39:22] [PASSED] 7 VFs
[11:39:22] [PASSED] 8 VFs
[11:39:22] [PASSED] 9 VFs
[11:39:22] [PASSED] 10 VFs
[11:39:22] [PASSED] 11 VFs
[11:39:22] [PASSED] 12 VFs
[11:39:22] [PASSED] 13 VFs
[11:39:22] [PASSED] 14 VFs
[11:39:22] [PASSED] 15 VFs
[11:39:22] [PASSED] 16 VFs
[11:39:22] [PASSED] 17 VFs
[11:39:22] [PASSED] 18 VFs
[11:39:22] [PASSED] 19 VFs
[11:39:22] [PASSED] 20 VFs
[11:39:22] [PASSED] 21 VFs
[11:39:22] [PASSED] 22 VFs
[11:39:22] [PASSED] 23 VFs
[11:39:22] [PASSED] 24 VFs
[11:39:22] [PASSED] 25 VFs
[11:39:22] [PASSED] 26 VFs
[11:39:22] [PASSED] 27 VFs
[11:39:22] [PASSED] 28 VFs
[11:39:22] [PASSED] 29 VFs
[11:39:22] [PASSED] 30 VFs
[11:39:22] [PASSED] 31 VFs
[11:39:22] [PASSED] 32 VFs
[11:39:22] [PASSED] 33 VFs
[11:39:22] [PASSED] 34 VFs
[11:39:22] [PASSED] 35 VFs
[11:39:22] [PASSED] 36 VFs
[11:39:22] [PASSED] 37 VFs
[11:39:22] [PASSED] 38 VFs
[11:39:22] [PASSED] 39 VFs
[11:39:22] [PASSED] 40 VFs
[11:39:22] [PASSED] 41 VFs
[11:39:22] [PASSED] 42 VFs
[11:39:22] [PASSED] 43 VFs
[11:39:22] [PASSED] 44 VFs
[11:39:22] [PASSED] 45 VFs
[11:39:22] [PASSED] 46 VFs
[11:39:22] [PASSED] 47 VFs
[11:39:22] [PASSED] 48 VFs
[11:39:22] [PASSED] 49 VFs
[11:39:22] [PASSED] 50 VFs
[11:39:22] [PASSED] 51 VFs
[11:39:22] [PASSED] 52 VFs
[11:39:22] [PASSED] 53 VFs
[11:39:22] [PASSED] 54 VFs
[11:39:22] [PASSED] 55 VFs
[11:39:22] [PASSED] 56 VFs
[11:39:22] [PASSED] 57 VFs
[11:39:22] [PASSED] 58 VFs
[11:39:22] [PASSED] 59 VFs
[11:39:22] [PASSED] 60 VFs
[11:39:22] [PASSED] 61 VFs
[11:39:22] [PASSED] 62 VFs
[11:39:22] [PASSED] 63 VFs
[11:39:22] ==================== [PASSED] fair_vram ====================
[11:39:22] ================== [PASSED] pf_gt_config ===================
[11:39:22] ===================== lmtt (1 subtest) =====================
[11:39:22] ======================== test_ops  =========================
[11:39:22] [PASSED] 2-level
[11:39:22] [PASSED] multi-level
[11:39:22] ==================== [PASSED] test_ops =====================
[11:39:22] ====================== [PASSED] lmtt =======================
[11:39:22] ================= sriov_packet (1 subtest) =================
[11:39:22] [PASSED] test_descriptor_init
[11:39:22] ================== [PASSED] sriov_packet ===================
[11:39:22] ================= pf_service (11 subtests) =================
[11:39:22] [PASSED] pf_negotiate_any
[11:39:22] [PASSED] pf_negotiate_base_match
[11:39:22] [PASSED] pf_negotiate_base_newer
[11:39:22] [PASSED] pf_negotiate_base_next
[11:39:22] [SKIPPED] pf_negotiate_base_older (no older minor)
[11:39:22] [PASSED] pf_negotiate_base_prev
[11:39:22] [PASSED] pf_negotiate_latest_match
[11:39:22] [PASSED] pf_negotiate_latest_newer
[11:39:22] [PASSED] pf_negotiate_latest_next
[11:39:22] [SKIPPED] pf_negotiate_latest_older (no older minor)
[11:39:22] [SKIPPED] pf_negotiate_latest_prev (no prev major)
[11:39:22] =================== [PASSED] pf_service ====================
[11:39:22] ================= xe_guc_g2g (2 subtests) ==================
[11:39:22] ============== xe_live_guc_g2g_kunit_default  ==============
[11:39:22] ========= [SKIPPED] xe_live_guc_g2g_kunit_default ==========
[11:39:22] ============== xe_live_guc_g2g_kunit_allmem  ===============
[11:39:22] ========== [SKIPPED] xe_live_guc_g2g_kunit_allmem ==========
[11:39:22] =================== [SKIPPED] xe_guc_g2g ===================
[11:39:22] =================== xe_mocs (2 subtests) ===================
[11:39:22] ================ xe_live_mocs_kernel_kunit  ================
[11:39:22] =========== [SKIPPED] xe_live_mocs_kernel_kunit ============
[11:39:22] ================ xe_live_mocs_reset_kunit  =================
[11:39:22] ============ [SKIPPED] xe_live_mocs_reset_kunit ============
[11:39:22] ==================== [SKIPPED] xe_mocs =====================
[11:39:22] ================= xe_migrate (2 subtests) ==================
[11:39:22] ================= xe_migrate_sanity_kunit  =================
[11:39:22] ============ [SKIPPED] xe_migrate_sanity_kunit =============
[11:39:22] ================== xe_validate_ccs_kunit  ==================
[11:39:22] ============= [SKIPPED] xe_validate_ccs_kunit ==============
[11:39:22] =================== [SKIPPED] xe_migrate ===================
[11:39:22] ================== xe_dma_buf (1 subtest) ==================
[11:39:22] ==================== xe_dma_buf_kunit  =====================
[11:39:22] ================ [SKIPPED] xe_dma_buf_kunit ================
[11:39:22] =================== [SKIPPED] xe_dma_buf ===================
[11:39:22] ================= xe_bo_shrink (1 subtest) =================
[11:39:22] =================== xe_bo_shrink_kunit  ====================
[11:39:22] =============== [SKIPPED] xe_bo_shrink_kunit ===============
[11:39:22] ================== [SKIPPED] xe_bo_shrink ==================
[11:39:22] ==================== xe_bo (2 subtests) ====================
[11:39:22] ================== xe_ccs_migrate_kunit  ===================
[11:39:22] ============== [SKIPPED] xe_ccs_migrate_kunit ==============
[11:39:22] ==================== xe_bo_evict_kunit  ====================
[11:39:22] =============== [SKIPPED] xe_bo_evict_kunit ================
[11:39:22] ===================== [SKIPPED] xe_bo ======================
[11:39:22] =================== xe_any (9 subtests) ====================
[11:39:22] [PASSED] test_to_xe
[11:39:22] [PASSED] test_to_dev
[11:39:22] [PASSED] test_to_pdev
[11:39:22] [PASSED] test_to_drm
[11:39:22] [PASSED] test_if_pdev
[11:39:22] [PASSED] test_if_xe
[11:39:22] [PASSED] test_if_tile
[11:39:22] [PASSED] test_if_gt
[11:39:22] [PASSED] test_to_id
[11:39:22] ===================== [PASSED] xe_any ======================
[11:39:22] ==================== args (13 subtests) ====================
[11:39:22] [PASSED] count_args_test
[11:39:22] [PASSED] call_args_example
[11:39:22] [PASSED] call_args_test
[11:39:22] [PASSED] drop_first_arg_example
[11:39:22] [PASSED] drop_first_arg_test
[11:39:22] [PASSED] first_arg_example
[11:39:22] [PASSED] first_arg_test
[11:39:22] [PASSED] last_arg_example
[11:39:22] [PASSED] last_arg_test
[11:39:22] [PASSED] pick_arg_example
[11:39:22] [PASSED] if_args_example
[11:39:22] [PASSED] if_args_test
[11:39:22] [PASSED] sep_comma_example
[11:39:22] ====================== [PASSED] args =======================
[11:39:22] =================== xe_pci (3 subtests) ====================
[11:39:22] ==================== check_graphics_ip  ====================
[11:39:22] [PASSED] 12.00 Xe_LP
[11:39:22] [PASSED] 12.10 Xe_LP+
[11:39:22] [PASSED] 12.55 Xe_HPG
[11:39:22] [PASSED] 12.60 Xe_HPC
[11:39:22] [PASSED] 12.70 Xe_LPG
[11:39:22] [PASSED] 12.71 Xe_LPG
[11:39:22] [PASSED] 12.74 Xe_LPG+
[11:39:22] [PASSED] 20.01 Xe2_HPG
[11:39:22] [PASSED] 20.02 Xe2_HPG
[11:39:22] [PASSED] 20.04 Xe2_LPG
[11:39:22] [PASSED] 30.00 Xe3_LPG
[11:39:22] [PASSED] 30.01 Xe3_LPG
[11:39:22] [PASSED] 30.03 Xe3_LPG
[11:39:22] [PASSED] 30.04 Xe3_LPG
[11:39:22] [PASSED] 30.05 Xe3_LPG
[11:39:22] [PASSED] 35.10 Xe3p_LPG
[11:39:22] [PASSED] 35.11 Xe3p_XPC
[11:39:22] ================ [PASSED] check_graphics_ip ================
[11:39:22] ===================== check_media_ip  ======================
[11:39:22] [PASSED] 12.00 Xe_M
[11:39:22] [PASSED] 12.55 Xe_HPM
[11:39:22] [PASSED] 13.00 Xe_LPM+
[11:39:22] [PASSED] 13.01 Xe2_HPM
[11:39:22] [PASSED] 20.00 Xe2_LPM
[11:39:22] [PASSED] 30.00 Xe3_LPM
[11:39:22] [PASSED] 30.02 Xe3_LPM
[11:39:22] [PASSED] 35.00 Xe3p_LPM
[11:39:22] [PASSED] 35.03 Xe3p_HPM
[11:39:22] ================= [PASSED] check_media_ip ==================
[11:39:22] =================== check_platform_desc  ===================
[11:39:22] [PASSED] 0x9A60 (TIGERLAKE)
[11:39:22] [PASSED] 0x9A68 (TIGERLAKE)
[11:39:22] [PASSED] 0x9A70 (TIGERLAKE)
[11:39:22] [PASSED] 0x9A40 (TIGERLAKE)
[11:39:22] [PASSED] 0x9A49 (TIGERLAKE)
[11:39:22] [PASSED] 0x9A59 (TIGERLAKE)
[11:39:22] [PASSED] 0x9A78 (TIGERLAKE)
[11:39:22] [PASSED] 0x9AC0 (TIGERLAKE)
[11:39:22] [PASSED] 0x9AC9 (TIGERLAKE)
[11:39:22] [PASSED] 0x9AD9 (TIGERLAKE)
[11:39:22] [PASSED] 0x9AF8 (TIGERLAKE)
[11:39:22] [PASSED] 0x4C80 (ROCKETLAKE)
[11:39:22] [PASSED] 0x4C8A (ROCKETLAKE)
[11:39:22] [PASSED] 0x4C8B (ROCKETLAKE)
[11:39:22] [PASSED] 0x4C8C (ROCKETLAKE)
[11:39:22] [PASSED] 0x4C90 (ROCKETLAKE)
[11:39:22] [PASSED] 0x4C9A (ROCKETLAKE)
[11:39:22] [PASSED] 0x4680 (ALDERLAKE_S)
[11:39:22] [PASSED] 0x4682 (ALDERLAKE_S)
[11:39:22] [PASSED] 0x4688 (ALDERLAKE_S)
[11:39:22] [PASSED] 0x468A (ALDERLAKE_S)
[11:39:22] [PASSED] 0x468B (ALDERLAKE_S)
[11:39:22] [PASSED] 0x4690 (ALDERLAKE_S)
[11:39:22] [PASSED] 0x4692 (ALDERLAKE_S)
[11:39:22] [PASSED] 0x4693 (ALDERLAKE_S)
[11:39:22] [PASSED] 0x46A0 (ALDERLAKE_P)
[11:39:22] [PASSED] 0x46A1 (ALDERLAKE_P)
[11:39:22] [PASSED] 0x46A2 (ALDERLAKE_P)
[11:39:22] [PASSED] 0x46A3 (ALDERLAKE_P)
[11:39:22] [PASSED] 0x46A6 (ALDERLAKE_P)
[11:39:22] [PASSED] 0x46A8 (ALDERLAKE_P)
[11:39:22] [PASSED] 0x46AA (ALDERLAKE_P)
[11:39:22] [PASSED] 0x462A (ALDERLAKE_P)
[11:39:22] [PASSED] 0x4626 (ALDERLAKE_P)
[11:39:22] [PASSED] 0x4628 (ALDERLAKE_P)
[11:39:22] [PASSED] 0x46B0 (ALDERLAKE_P)
[11:39:22] [PASSED] 0x46B1 (ALDERLAKE_P)
[11:39:22] [PASSED] 0x46B2 (ALDERLAKE_P)
[11:39:22] [PASSED] 0x46B3 (ALDERLAKE_P)
[11:39:22] [PASSED] 0x46C0 (ALDERLAKE_P)
[11:39:22] [PASSED] 0x46C1 (ALDERLAKE_P)
[11:39:22] [PASSED] 0x46C2 (ALDERLAKE_P)
[11:39:22] [PASSED] 0x46C3 (ALDERLAKE_P)
[11:39:22] [PASSED] 0x46D0 (ALDERLAKE_N)
[11:39:22] [PASSED] 0x46D1 (ALDERLAKE_N)
[11:39:22] [PASSED] 0x46D2 (ALDERLAKE_N)
[11:39:22] [PASSED] 0x46D3 (ALDERLAKE_N)
[11:39:22] [PASSED] 0x46D4 (ALDERLAKE_N)
[11:39:22] [PASSED] 0xA721 (ALDERLAKE_P)
[11:39:22] [PASSED] 0xA7A1 (ALDERLAKE_P)
[11:39:22] [PASSED] 0xA7A9 (ALDERLAKE_P)
[11:39:22] [PASSED] 0xA7AC (ALDERLAKE_P)
[11:39:22] [PASSED] 0xA7AD (ALDERLAKE_P)
[11:39:22] [PASSED] 0xA720 (ALDERLAKE_P)
[11:39:22] [PASSED] 0xA7A0 (ALDERLAKE_P)
[11:39:22] [PASSED] 0xA7A8 (ALDERLAKE_P)
[11:39:22] [PASSED] 0xA7AA (ALDERLAKE_P)
[11:39:22] [PASSED] 0xA7AB (ALDERLAKE_P)
[11:39:22] [PASSED] 0xA780 (ALDERLAKE_S)
[11:39:22] [PASSED] 0xA781 (ALDERLAKE_S)
[11:39:22] [PASSED] 0xA782 (ALDERLAKE_S)
[11:39:22] [PASSED] 0xA783 (ALDERLAKE_S)
[11:39:22] [PASSED] 0xA788 (ALDERLAKE_S)
[11:39:22] [PASSED] 0xA789 (ALDERLAKE_S)
[11:39:22] [PASSED] 0xA78A (ALDERLAKE_S)
[11:39:22] [PASSED] 0xA78B (ALDERLAKE_S)
[11:39:22] [PASSED] 0x4905 (DG1)
[11:39:22] [PASSED] 0x4906 (DG1)
[11:39:22] [PASSED] 0x4907 (DG1)
[11:39:22] [PASSED] 0x4908 (DG1)
[11:39:22] [PASSED] 0x4909 (DG1)
[11:39:22] [PASSED] 0x56C0 (DG2)
[11:39:22] [PASSED] 0x56C2 (DG2)
[11:39:22] [PASSED] 0x56C1 (DG2)
[11:39:22] [PASSED] 0x7D51 (METEORLAKE)
[11:39:22] [PASSED] 0x7DD1 (METEORLAKE)
[11:39:22] [PASSED] 0x7D41 (METEORLAKE)
[11:39:22] [PASSED] 0x7D67 (METEORLAKE)
[11:39:22] [PASSED] 0xB640 (METEORLAKE)
[11:39:22] [PASSED] 0x56A0 (DG2)
[11:39:22] [PASSED] 0x56A1 (DG2)
[11:39:22] [PASSED] 0x56A2 (DG2)
[11:39:22] [PASSED] 0x56BE (DG2)
[11:39:22] [PASSED] 0x56BF (DG2)
[11:39:22] [PASSED] 0x5690 (DG2)
[11:39:22] [PASSED] 0x5691 (DG2)
[11:39:22] [PASSED] 0x5692 (DG2)
[11:39:22] [PASSED] 0x56A5 (DG2)
[11:39:22] [PASSED] 0x56A6 (DG2)
[11:39:22] [PASSED] 0x56B0 (DG2)
[11:39:22] [PASSED] 0x56B1 (DG2)
[11:39:22] [PASSED] 0x56BA (DG2)
[11:39:22] [PASSED] 0x56BB (DG2)
[11:39:22] [PASSED] 0x56BC (DG2)
[11:39:22] [PASSED] 0x56BD (DG2)
[11:39:22] [PASSED] 0x5693 (DG2)
[11:39:22] [PASSED] 0x5694 (DG2)
[11:39:22] [PASSED] 0x5695 (DG2)
[11:39:22] [PASSED] 0x56A3 (DG2)
[11:39:22] [PASSED] 0x56A4 (DG2)
[11:39:22] [PASSED] 0x56B2 (DG2)
[11:39:22] [PASSED] 0x56B3 (DG2)
[11:39:22] [PASSED] 0x5696 (DG2)
[11:39:22] [PASSED] 0x5697 (DG2)
[11:39:22] [PASSED] 0xB69 (PVC)
[11:39:22] [PASSED] 0xB6E (PVC)
[11:39:22] [PASSED] 0xBD4 (PVC)
[11:39:22] [PASSED] 0xBD5 (PVC)
[11:39:22] [PASSED] 0xBD6 (PVC)
[11:39:22] [PASSED] 0xBD7 (PVC)
[11:39:22] [PASSED] 0xBD8 (PVC)
[11:39:22] [PASSED] 0xBD9 (PVC)
[11:39:22] [PASSED] 0xBDA (PVC)
[11:39:22] [PASSED] 0xBDB (PVC)
[11:39:22] [PASSED] 0xBE0 (PVC)
[11:39:22] [PASSED] 0xBE1 (PVC)
[11:39:22] [PASSED] 0xBE5 (PVC)
[11:39:22] [PASSED] 0x7D40 (METEORLAKE)
[11:39:22] [PASSED] 0x7D45 (METEORLAKE)
[11:39:22] [PASSED] 0x7D55 (METEORLAKE)
[11:39:22] [PASSED] 0x7D60 (METEORLAKE)
[11:39:22] [PASSED] 0x7DD5 (METEORLAKE)
[11:39:22] [PASSED] 0x6420 (LUNARLAKE)
[11:39:22] [PASSED] 0x64A0 (LUNARLAKE)
[11:39:22] [PASSED] 0x64B0 (LUNARLAKE)
[11:39:22] [PASSED] 0xE202 (BATTLEMAGE)
[11:39:22] [PASSED] 0xE209 (BATTLEMAGE)
[11:39:22] [PASSED] 0xE20B (BATTLEMAGE)
[11:39:22] [PASSED] 0xE20C (BATTLEMAGE)
[11:39:22] [PASSED] 0xE20D (BATTLEMAGE)
[11:39:22] [PASSED] 0xE210 (BATTLEMAGE)
[11:39:22] [PASSED] 0xE211 (BATTLEMAGE)
[11:39:22] [PASSED] 0xE212 (BATTLEMAGE)
[11:39:22] [PASSED] 0xE216 (BATTLEMAGE)
[11:39:22] [PASSED] 0xE220 (BATTLEMAGE)
[11:39:22] [PASSED] 0xE221 (BATTLEMAGE)
[11:39:22] [PASSED] 0xE222 (BATTLEMAGE)
[11:39:22] [PASSED] 0xE223 (BATTLEMAGE)
[11:39:22] [PASSED] 0xB080 (PANTHERLAKE)
[11:39:22] [PASSED] 0xB081 (PANTHERLAKE)
[11:39:22] [PASSED] 0xB082 (PANTHERLAKE)
[11:39:22] [PASSED] 0xB083 (PANTHERLAKE)
[11:39:22] [PASSED] 0xB084 (PANTHERLAKE)
[11:39:22] [PASSED] 0xB085 (PANTHERLAKE)
[11:39:22] [PASSED] 0xB086 (PANTHERLAKE)
[11:39:22] [PASSED] 0xB087 (PANTHERLAKE)
[11:39:22] [PASSED] 0xB08F (PANTHERLAKE)
[11:39:22] [PASSED] 0xB090 (PANTHERLAKE)
[11:39:22] [PASSED] 0xB0A0 (PANTHERLAKE)
[11:39:22] [PASSED] 0xB0B0 (PANTHERLAKE)
[11:39:22] [PASSED] 0xFD80 (PANTHERLAKE)
[11:39:22] [PASSED] 0xFD81 (PANTHERLAKE)
[11:39:22] [PASSED] 0xD740 (NOVALAKE_S)
[11:39:22] [PASSED] 0xD741 (NOVALAKE_S)
[11:39:22] [PASSED] 0xD742 (NOVALAKE_S)
[11:39:22] [PASSED] 0xD743 (NOVALAKE_S)
[11:39:22] [PASSED] 0xD745 (NOVALAKE_S)
[11:39:22] [PASSED] 0xD74A (NOVALAKE_S)
[11:39:22] [PASSED] 0xD74B (NOVALAKE_S)
[11:39:22] [PASSED] 0x674C (CRESCENTISLAND)
[11:39:22] [PASSED] 0x674D (CRESCENTISLAND)
[11:39:22] [PASSED] 0x674E (CRESCENTISLAND)
[11:39:22] [PASSED] 0x674F (CRESCENTISLAND)
[11:39:22] [PASSED] 0x6750 (CRESCENTISLAND)
[11:39:22] [PASSED] 0xD750 (NOVALAKE_P)
[11:39:22] [PASSED] 0xD751 (NOVALAKE_P)
[11:39:22] [PASSED] 0xD752 (NOVALAKE_P)
[11:39:22] [PASSED] 0xD753 (NOVALAKE_P)
[11:39:22] [PASSED] 0xD754 (NOVALAKE_P)
[11:39:22] [PASSED] 0xD755 (NOVALAKE_P)
[11:39:22] [PASSED] 0xD756 (NOVALAKE_P)
[11:39:22] [PASSED] 0xD757 (NOVALAKE_P)
[11:39:22] [PASSED] 0xD75F (NOVALAKE_P)
[11:39:22] =============== [PASSED] check_platform_desc ===============
[11:39:22] ===================== [PASSED] xe_pci ======================
[11:39:22] ============= xe_rtp_tables_test (5 subtests) ==============
[11:39:22] ================== xe_rtp_table_gt_test  ===================
[11:39:22] [PASSED] gt_was/14011060649
[11:39:22] [PASSED] gt_was/14011059788
[11:39:22] [PASSED] gt_was/14015795083
[11:39:22] [PASSED] gt_was/16021867713
[11:39:22] [PASSED] gt_was/14019449301
[11:39:22] [PASSED] gt_was/16028005424
[11:39:22] [PASSED] gt_was/14026578760
[11:39:22] [PASSED] gt_was/1409420604
[11:39:22] [PASSED] gt_was/1408615072
[11:39:22] [PASSED] gt_was/22010523718
[11:39:22] [PASSED] gt_was/14011006942
[11:39:22] [PASSED] gt_was/14014830051
[11:39:22] [PASSED] gt_was/18018781329
[11:39:22] [PASSED] gt_was/1509235366
[11:39:22] [PASSED] gt_was/18018781329
[11:39:22] [PASSED] gt_was/16016694945
[11:39:22] [PASSED] gt_was/14018575942
[11:39:22] [PASSED] gt_was/22016670082
[11:39:22] [PASSED] gt_was/22016670082
[11:39:22] [PASSED] gt_was/14017421178
[11:39:22] [PASSED] gt_was/16025250150
[11:39:22] [PASSED] gt_was/14021871409
[11:39:22] [PASSED] gt_was/16021865536
[11:39:22] [PASSED] gt_was/14021486841
[11:39:22] [PASSED] gt_was/14025160223
[11:39:22] [PASSED] gt_was/14026144927, 16029437861, 14026127056
[11:39:22] [PASSED] gt_was/14025635424
[11:39:22] [PASSED] gt_was/16028005424
[11:39:22] ============== [PASSED] xe_rtp_table_gt_test ===============
[11:39:22] ================== xe_rtp_table_gt_test  ===================
[11:39:22] [PASSED] gt_tunings/Tuning: Blend Fill Caching Optimization Disable
[11:39:22] [PASSED] gt_tunings/Tuning: 32B Access Enable
[11:39:22] [PASSED] gt_tunings/Tuning: L3 cache
[11:39:22] [PASSED] gt_tunings/Tuning: L3 cache - media
[11:39:22] [PASSED] gt_tunings/Tuning: Compression Overfetch
[11:39:22] [PASSED] gt_tunings/Tuning: Compression Overfetch - media
[11:39:22] [PASSED] gt_tunings/Tuning: Enable compressible partial write overfetch in L3
[11:39:22] [PASSED] gt_tunings/Tuning: Enable compressible partial write overfetch in L3 - media
[11:39:22] [PASSED] gt_tunings/Tuning: L2 Overfetch Compressible Only
[11:39:22] [PASSED] gt_tunings/Tuning: L2 Overfetch Compressible Only - media
[11:39:22] [PASSED] gt_tunings/Tuning: Stateless compression control
[11:39:22] [PASSED] gt_tunings/Tuning: Stateless compression control - media
[11:39:22] [PASSED] gt_tunings/Tuning: L3 RW flush all Cache
[11:39:22] [PASSED] gt_tunings/Tuning: L3 RW flush all cache - media
[11:39:22] [PASSED] gt_tunings/Tuning: Set STLB Bank Hash Mode to 4KB
[11:39:22] ============== [PASSED] xe_rtp_table_gt_test ===============
[11:39:22] ================== xe_rtp_table_oob_test  ==================
[11:39:22] [PASSED] oob_was/1607983814
[11:39:22] [PASSED] oob_was/16010904313
[11:39:22] [PASSED] oob_was/18022495364
[11:39:22] [PASSED] oob_was/22012773006
[11:39:22] [PASSED] oob_was/14014475959
[11:39:22] [PASSED] oob_was/22011391025
[11:39:22] [PASSED] oob_was/22012727170
[11:39:22] [PASSED] oob_was/22012727685
[11:39:22] [PASSED] oob_was/22016596838
[11:39:22] [PASSED] oob_was/18020744125
[11:39:22] [PASSED] oob_was/1409600907
[11:39:22] [PASSED] oob_was/22014953428
[11:39:22] [PASSED] oob_was/16017236439
[11:39:22] [PASSED] oob_was/14019821291
[11:39:22] [PASSED] oob_was/14015076503
[11:39:22] [PASSED] oob_was/14018913170
[11:39:22] [PASSED] oob_was/14018094691
[11:39:22] [PASSED] oob_was/18024947630
[11:39:22] [PASSED] oob_was/16022287689
[11:39:22] [PASSED] oob_was/13011645652
[11:39:22] [PASSED] oob_was/14022293748
[11:39:22] [PASSED] oob_was/22019794406
[11:39:22] [PASSED] oob_was/22019338487
[11:39:22] [PASSED] oob_was/16023588340
[11:39:22] [PASSED] oob_was/14019789679
[11:39:22] [PASSED] oob_was/14022866841
[11:39:22] [PASSED] oob_was/16021333562
[11:39:22] [PASSED] oob_was/14016712196
[11:39:22] [PASSED] oob_was/14015568240
[11:39:22] [PASSED] oob_was/18013179988
[11:39:22] [PASSED] oob_was/1508761755
[11:39:22] [PASSED] oob_was/16023105232
[11:39:22] [PASSED] oob_was/16026508708
[11:39:22] [PASSED] oob_was/14020001231
[11:39:22] [PASSED] oob_was/16023683509
[11:39:22] [PASSED] oob_was/14025515070
[11:39:22] [PASSED] oob_was/15015404425_disable
[11:39:22] [PASSED] oob_was/16026007364
[11:39:22] [PASSED] oob_was/14020316580
[11:39:22] [PASSED] oob_was/14025883347
[11:39:22] [PASSED] oob_was/16029380221
[11:39:22] [PASSED] oob_was/22022079272
[11:39:22] [PASSED] oob_was/16029897822
[11:39:22] [PASSED] oob_was/14027054324
[11:39:22] [PASSED] oob_was/14025941587
[11:39:22] ============== [PASSED] xe_rtp_table_oob_test ==============
[11:39:22] ================ xe_rtp_table_dev_oob_test  ================
[11:39:22] [PASSED] device_oob_was/22010954014
[11:39:22] [PASSED] device_oob_was/15015404425
[11:39:22] [PASSED] device_oob_was/22019338487_display
[11:39:22] [PASSED] device_oob_was/14022085890
[11:39:22] [PASSED] device_oob_was/14026539277
[11:39:22] [PASSED] device_oob_was/14026633728
[11:39:22] [PASSED] device_oob_was/14026746987
[11:39:22] [PASSED] device_oob_was/14026779378
[11:39:22] ============ [PASSED] xe_rtp_table_dev_oob_test ============
[11:39:22] ========== xe_rtp_table_missing_upper_bound_test  ==========
[11:39:22] [PASSED] register_whitelist/WaAllowPMDepthAndInvocationCountAccessFromUMD, 1408556865
[11:39:22] [PASSED] register_whitelist/1508744258, 14012131227, 1808121037
[11:39:22] [PASSED] register_whitelist/1806527549
[11:39:22] [PASSED] register_whitelist/allow_read_ctx_timestamp
[11:39:22] [PASSED] register_whitelist/allow_read_queue_timestamp
[11:39:22] [PASSED] register_whitelist/16014440446
[11:39:22] [PASSED] register_whitelist/16017236439
[11:39:22] [PASSED] register_whitelist/16020183090
[11:39:22] [PASSED] register_whitelist/14024997852
[11:39:22] [PASSED] register_whitelist/14024997852
[11:39:22] ====== [PASSED] xe_rtp_table_missing_upper_bound_test ======
[11:39:22] =============== [PASSED] xe_rtp_tables_test ================
[11:39:22] =================== xe_rtp (3 subtests) ====================
[11:39:22] =================== xe_rtp_rules_tests  ====================
[11:39:22] [PASSED] no
[11:39:22] [PASSED] yes
[11:39:22] [PASSED] no-and-no
[11:39:22] [PASSED] no-and-yes
[11:39:22] [PASSED] yes-and-no
[11:39:22] [PASSED] yes-and-yes
[11:39:22] [PASSED] no-or-no
[11:39:22] [PASSED] no-or-yes
[11:39:22] [PASSED] yes-or-no
[11:39:22] [PASSED] yes-or-yes
[11:39:22] [PASSED] no-yes-or-yes-no
[11:39:22] [PASSED] no-yes-or-yes-yes
[11:39:22] [PASSED] yes-yes-or-no-yes
[11:39:22] [PASSED] yes-yes-or-yes-yes
[11:39:22] [PASSED] no-no-or-yes-or-no
[11:39:22] [PASSED] or
[11:39:22] [PASSED] or-yes
[11:39:22] [PASSED] or-no
[11:39:22] [PASSED] yes-or
[11:39:22] [PASSED] no-or
[11:39:22] [PASSED] no-or-or-yes
[11:39:22] [PASSED] yes-or-or-no
[11:39:22] [PASSED] no-or-or-no
[11:39:22] [PASSED] missing-context-engine-class
[11:39:22] [PASSED] missing-context-engine-class-or-yes
[11:39:22] [PASSED] missing-context-engine-class-or-or-yes
[11:39:22] =============== [PASSED] xe_rtp_rules_tests ================
[11:39:22] =============== xe_rtp_process_to_sr_tests  ================
[11:39:22] [PASSED] coalesce-same-reg
[11:39:22] [PASSED] coalesce-same-reg-literal-and-func
[11:39:22] [PASSED] no-match-no-add
[11:39:22] [PASSED] two-regs-two-entries
[11:39:22] [PASSED] clr-one-set-other
[11:39:22] [PASSED] set-field
[11:39:22] [PASSED] conflict-duplicate
[11:39:22] [PASSED] conflict-not-disjoint
[11:39:22] [PASSED] conflict-not-disjoint-literal-and-func
[11:39:22] [PASSED] conflict-reg-type
[11:39:22] [PASSED] bad-mcr-reg-forced-to-regular
[11:39:22] [PASSED] bad-regular-reg-forced-to-mcr
[11:39:22] =========== [PASSED] xe_rtp_process_to_sr_tests ============
[11:39:22] ================== xe_rtp_process_tests  ===================
[11:39:22] [PASSED] active1
[11:39:22] [PASSED] active2
[11:39:22] [PASSED] active-inactive
[11:39:22] [PASSED] inactive-active
[11:39:22] [PASSED] inactive-active-inactive
[11:39:22] [PASSED] inactive-inactive-inactive
[11:39:22] ============== [PASSED] xe_rtp_process_tests ===============
[11:39:22] ===================== [PASSED] xe_rtp ======================
[11:39:22] ==================== xe_wa (1 subtest) =====================
[11:39:22] ======================== xe_wa_gt  =========================
[11:39:22] [PASSED] TIGERLAKE B0
[11:39:22] [PASSED] DG1 A0
[11:39:22] [PASSED] DG1 B0
[11:39:22] [PASSED] ALDERLAKE_S A0
[11:39:22] [PASSED] ALDERLAKE_S B0
[11:39:22] [PASSED] ALDERLAKE_S C0
[11:39:22] [PASSED] ALDERLAKE_S D0
[11:39:22] [PASSED] ALDERLAKE_P A0
[11:39:22] [PASSED] ALDERLAKE_P B0
[11:39:22] [PASSED] ALDERLAKE_P C0
[11:39:22] [PASSED] ALDERLAKE_S RPLS D0
[11:39:22] [PASSED] ALDERLAKE_P RPLU E0
[11:39:22] [PASSED] DG2 G10 C0
[11:39:22] [PASSED] DG2 G11 B1
[11:39:22] [PASSED] DG2 G12 A1
[11:39:22] [PASSED] METEORLAKE 12.70(Xe_LPG) A0 13.00(Xe_LPM+) A0
[11:39:22] [PASSED] METEORLAKE 12.71(Xe_LPG) A0 13.00(Xe_LPM+) A0
[11:39:22] [PASSED] METEORLAKE 12.74(Xe_LPG+) A0 13.00(Xe_LPM+) A0
[11:39:22] [PASSED] LUNARLAKE 20.04(Xe2_LPG) A0 20.00(Xe2_LPM) A0
[11:39:22] [PASSED] LUNARLAKE 20.04(Xe2_LPG) B0 20.00(Xe2_LPM) A0
[11:39:22] [PASSED] BATTLEMAGE 20.01(Xe2_HPG) A0 13.01(Xe2_HPM) A1
[11:39:22] [PASSED] PANTHERLAKE 30.00(Xe3_LPG) A0 30.00(Xe3_LPM) A0
[11:39:22] ==================== [PASSED] xe_wa_gt =====================
[11:39:22] ====================== [PASSED] xe_wa ======================
[11:39:22] ============================================================
[11:39:22] Testing complete. Ran 820 tests: passed: 792, skipped: 28
[11:39:22] Elapsed time: 36.825s total, 1.811s configuring, 34.248s building, 0.720s running

+ for kcfg in "${kunitconfigs[@]}"
+ [[ ! -f /kernel/drivers/gpu/drm/tests/.kunitconfig ]]
+ /kernel/tools/testing/kunit/kunit.py run --kunitconfig /kernel/drivers/gpu/drm/tests/.kunitconfig
[11:39:22] Configuring KUnit Kernel ...
Regenerating .config ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
[11:39:24] Building KUnit Kernel ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
Building with:
$ make all compile_commands.json scripts_gdb ARCH=um O=.kunit --jobs=48
[11:39:49] Starting KUnit Kernel (1/1)...
[11:39:49] ============================================================
Running tests with:
$ .kunit/linux kunit.enable=1 mem=1G console=tty kunit_shutdown=halt
[11:39:49] ============= refcount_interrupt (4 subtests) ==============
[11:39:49] [PASSED] test_single_irq_change
[11:39:49] [PASSED] test_nested_irq_change
[11:39:49] [PASSED] test_multiple_irq_change
[11:39:49] [PASSED] test_irq_save
[11:39:49] =============== [PASSED] refcount_interrupt ================
[11:39:49] ============ drm_test_pick_cmdline (2 subtests) ============
[11:39:49] [PASSED] drm_test_pick_cmdline_res_1920_1080_60
[11:39:49] =============== drm_test_pick_cmdline_named  ===============
[11:39:49] [PASSED] NTSC
[11:39:49] [PASSED] NTSC-J
[11:39:49] [PASSED] PAL
[11:39:49] [PASSED] PAL-M
[11:39:49] =========== [PASSED] drm_test_pick_cmdline_named ===========
[11:39:49] ============== [PASSED] drm_test_pick_cmdline ==============
[11:39:49] == drm_test_atomic_get_connector_for_encoder (1 subtest) ===
[11:39:49] [PASSED] drm_test_drm_atomic_get_connector_for_encoder
[11:39:49] ==== [PASSED] drm_test_atomic_get_connector_for_encoder ====
[11:39:49] =========== drm_validate_clone_mode (2 subtests) ===========
[11:39:49] ============== drm_test_check_in_clone_mode  ===============
[11:39:49] [PASSED] in_clone_mode
[11:39:49] [PASSED] not_in_clone_mode
[11:39:49] ========== [PASSED] drm_test_check_in_clone_mode ===========
[11:39:49] =============== drm_test_check_valid_clones  ===============
[11:39:49] [PASSED] not_in_clone_mode
[11:39:49] [PASSED] valid_clone
[11:39:49] [PASSED] invalid_clone
[11:39:49] =========== [PASSED] drm_test_check_valid_clones ===========
[11:39:49] ============= [PASSED] drm_validate_clone_mode =============
[11:39:49] ============= drm_validate_modeset (1 subtest) =============
[11:39:49] [PASSED] drm_test_check_connector_changed_modeset
[11:39:49] ============== [PASSED] drm_validate_modeset ===============
[11:39:49] ====== drm_test_bridge_get_current_state (1 subtest) =======
[11:39:49] [PASSED] drm_test_drm_bridge_get_current_state_atomic
[11:39:49] ======== [PASSED] drm_test_bridge_get_current_state ========
[11:39:49] ====== drm_test_bridge_helper_reset_crtc (3 subtests) ======
[11:39:49] [PASSED] drm_test_drm_bridge_helper_reset_crtc_atomic
[11:39:49] [PASSED] drm_test_drm_bridge_helper_reset_crtc_atomic_disabled
[11:39:49] [PASSED] drm_test_drm_bridge_helper_hdmi_output_bus_fmts
[11:39:49] ======== [PASSED] drm_test_bridge_helper_reset_crtc ========
[11:39:49] ============== drm_bridge_alloc (2 subtests) ===============
[11:39:49] [PASSED] drm_test_drm_bridge_alloc_basic
[11:39:49] [PASSED] drm_test_drm_bridge_alloc_get_put
[11:39:49] ================ [PASSED] drm_bridge_alloc =================
[11:39:49] ============= drm_bridge_bus_fmt (5 subtests) ==============
[11:39:49] [PASSED] drm_test_bridge_rgb_yuv_rgb
[11:39:49] [PASSED] drm_test_bridge_must_convert_to_yuv444
[11:39:49] [PASSED] drm_test_bridge_hdmi_auto_rgb
[11:39:49] [PASSED] drm_test_bridge_auto_first
[11:39:49] [PASSED] drm_test_bridge_rgb_yuv_no_path
[11:39:49] =============== [PASSED] drm_bridge_bus_fmt ================
[11:39:49] ============= drm_cmdline_parser (40 subtests) =============
[11:39:49] [PASSED] drm_test_cmdline_force_d_only
[11:39:49] [PASSED] drm_test_cmdline_force_D_only_dvi
[11:39:49] [PASSED] drm_test_cmdline_force_D_only_hdmi
[11:39:49] [PASSED] drm_test_cmdline_force_D_only_not_digital
[11:39:49] [PASSED] drm_test_cmdline_force_e_only
[11:39:49] [PASSED] drm_test_cmdline_res
[11:39:49] [PASSED] drm_test_cmdline_res_vesa
[11:39:49] [PASSED] drm_test_cmdline_res_vesa_rblank
[11:39:49] [PASSED] drm_test_cmdline_res_rblank
[11:39:49] [PASSED] drm_test_cmdline_res_bpp
[11:39:49] [PASSED] drm_test_cmdline_res_refresh
[11:39:49] [PASSED] drm_test_cmdline_res_bpp_refresh
[11:39:49] [PASSED] drm_test_cmdline_res_bpp_refresh_interlaced
[11:39:49] [PASSED] drm_test_cmdline_res_bpp_refresh_margins
[11:39:49] [PASSED] drm_test_cmdline_res_bpp_refresh_force_off
[11:39:49] [PASSED] drm_test_cmdline_res_bpp_refresh_force_on
[11:39:49] [PASSED] drm_test_cmdline_res_bpp_refresh_force_on_analog
[11:39:49] [PASSED] drm_test_cmdline_res_bpp_refresh_force_on_digital
[11:39:49] [PASSED] drm_test_cmdline_res_bpp_refresh_interlaced_margins_force_on
[11:39:49] [PASSED] drm_test_cmdline_res_margins_force_on
[11:39:49] [PASSED] drm_test_cmdline_res_vesa_margins
[11:39:49] [PASSED] drm_test_cmdline_name
[11:39:49] [PASSED] drm_test_cmdline_name_bpp
[11:39:49] [PASSED] drm_test_cmdline_name_option
[11:39:49] [PASSED] drm_test_cmdline_name_bpp_option
[11:39:49] [PASSED] drm_test_cmdline_rotate_0
[11:39:49] [PASSED] drm_test_cmdline_rotate_90
[11:39:49] [PASSED] drm_test_cmdline_rotate_180
[11:39:49] [PASSED] drm_test_cmdline_rotate_270
[11:39:49] [PASSED] drm_test_cmdline_hmirror
[11:39:49] [PASSED] drm_test_cmdline_vmirror
[11:39:49] [PASSED] drm_test_cmdline_margin_options
[11:39:49] [PASSED] drm_test_cmdline_multiple_options
[11:39:49] [PASSED] drm_test_cmdline_bpp_extra_and_option
[11:39:49] [PASSED] drm_test_cmdline_extra_and_option
[11:39:49] [PASSED] drm_test_cmdline_freestanding_options
[11:39:49] [PASSED] drm_test_cmdline_freestanding_force_e_and_options
[11:39:49] [PASSED] drm_test_cmdline_panel_orientation
[11:39:49] ================ drm_test_cmdline_invalid  =================
[11:39:49] [PASSED] margin_only
[11:39:49] [PASSED] interlace_only
[11:39:49] [PASSED] res_missing_x
[11:39:49] [PASSED] res_missing_y
[11:39:49] [PASSED] res_bad_y
[11:39:49] [PASSED] res_missing_y_bpp
[11:39:49] [PASSED] res_bad_bpp
[11:39:49] [PASSED] res_bad_refresh
[11:39:49] [PASSED] res_bpp_refresh_force_on_off
[11:39:49] [PASSED] res_invalid_mode
[11:39:49] [PASSED] res_bpp_wrong_place_mode
[11:39:49] [PASSED] name_bpp_refresh
[11:39:49] [PASSED] name_refresh
[11:39:49] [PASSED] name_refresh_wrong_mode
[11:39:49] [PASSED] name_refresh_invalid_mode
[11:39:49] [PASSED] rotate_multiple
[11:39:49] [PASSED] rotate_invalid_val
[11:39:49] [PASSED] rotate_truncated
[11:39:49] [PASSED] invalid_option
[11:39:49] [PASSED] invalid_tv_option
[11:39:49] [PASSED] truncated_tv_option
[11:39:49] ============ [PASSED] drm_test_cmdline_invalid =============
[11:39:49] =============== drm_test_cmdline_tv_options  ===============
[11:39:49] [PASSED] NTSC
[11:39:49] [PASSED] NTSC_443
[11:39:49] [PASSED] NTSC_J
[11:39:49] [PASSED] PAL
[11:39:49] [PASSED] PAL_M
[11:39:49] [PASSED] PAL_N
[11:39:49] [PASSED] SECAM
[11:39:49] [PASSED] MONO_525
[11:39:49] [PASSED] MONO_625
[11:39:49] =========== [PASSED] drm_test_cmdline_tv_options ===========
[11:39:49] =============== [PASSED] drm_cmdline_parser ================
[11:39:49] ========== drmm_connector_hdmi_init (20 subtests) ==========
[11:39:49] [PASSED] drm_test_connector_hdmi_init_valid
[11:39:49] [PASSED] drm_test_connector_hdmi_init_bpc_8
[11:39:49] [PASSED] drm_test_connector_hdmi_init_bpc_10
[11:39:49] [PASSED] drm_test_connector_hdmi_init_bpc_12
[11:39:49] [PASSED] drm_test_connector_hdmi_init_bpc_invalid
[11:39:49] [PASSED] drm_test_connector_hdmi_init_bpc_null
[11:39:49] [PASSED] drm_test_connector_hdmi_init_formats_empty
[11:39:49] [PASSED] drm_test_connector_hdmi_init_formats_no_rgb
[11:39:49] === drm_test_connector_hdmi_init_formats_yuv420_allowed  ===
[11:39:49] [PASSED] supported_formats=0x9 yuv420_allowed=1
[11:39:49] [PASSED] supported_formats=0x9 yuv420_allowed=0
[11:39:49] [PASSED] supported_formats=0x5 yuv420_allowed=1
[11:39:49] [PASSED] supported_formats=0x5 yuv420_allowed=0
[11:39:49] === [PASSED] drm_test_connector_hdmi_init_formats_yuv420_allowed ===
[11:39:49] [PASSED] drm_test_connector_hdmi_init_null_ddc
[11:39:49] [PASSED] drm_test_connector_hdmi_init_null_product
[11:39:49] [PASSED] drm_test_connector_hdmi_init_null_vendor
[11:39:49] [PASSED] drm_test_connector_hdmi_init_product_length_exact
[11:39:49] [PASSED] drm_test_connector_hdmi_init_product_length_too_long
[11:39:49] [PASSED] drm_test_connector_hdmi_init_product_valid
[11:39:49] [PASSED] drm_test_connector_hdmi_init_vendor_length_exact
[11:39:49] [PASSED] drm_test_connector_hdmi_init_vendor_length_too_long
[11:39:49] [PASSED] drm_test_connector_hdmi_init_vendor_valid
[11:39:49] ========= drm_test_connector_hdmi_init_type_valid  =========
[11:39:49] [PASSED] HDMI-A
[11:39:49] [PASSED] HDMI-B
[11:39:49] ===== [PASSED] drm_test_connector_hdmi_init_type_valid =====
[11:39:49] ======== drm_test_connector_hdmi_init_type_invalid  ========
[11:39:49] [PASSED] Unknown
[11:39:49] [PASSED] VGA
[11:39:49] [PASSED] DVI-I
[11:39:49] [PASSED] DVI-D
[11:39:49] [PASSED] DVI-A
[11:39:49] [PASSED] Composite
[11:39:49] [PASSED] SVIDEO
[11:39:49] [PASSED] LVDS
[11:39:49] [PASSED] Component
[11:39:49] [PASSED] DIN
[11:39:49] [PASSED] DP
[11:39:49] [PASSED] TV
[11:39:49] [PASSED] eDP
[11:39:49] [PASSED] Virtual
[11:39:49] [PASSED] DSI
[11:39:49] [PASSED] DPI
[11:39:49] [PASSED] Writeback
[11:39:49] [PASSED] SPI
[11:39:49] [PASSED] USB
[11:39:49] ==== [PASSED] drm_test_connector_hdmi_init_type_invalid ====
[11:39:49] ============ [PASSED] drmm_connector_hdmi_init =============
[11:39:49] ============= drmm_connector_init (3 subtests) =============
[11:39:49] [PASSED] drm_test_drmm_connector_init
[11:39:49] [PASSED] drm_test_drmm_connector_init_null_ddc
[11:39:49] ========= drm_test_drmm_connector_init_type_valid  =========
[11:39:49] [PASSED] Unknown
[11:39:49] [PASSED] VGA
[11:39:49] [PASSED] DVI-I
[11:39:49] [PASSED] DVI-D
[11:39:49] [PASSED] DVI-A
[11:39:49] [PASSED] Composite
[11:39:49] [PASSED] SVIDEO
[11:39:49] [PASSED] LVDS
[11:39:49] [PASSED] Component
[11:39:49] [PASSED] DIN
[11:39:49] [PASSED] DP
[11:39:49] [PASSED] HDMI-A
[11:39:49] [PASSED] HDMI-B
[11:39:49] [PASSED] TV
[11:39:49] [PASSED] eDP
[11:39:49] [PASSED] Virtual
[11:39:49] [PASSED] DSI
[11:39:49] [PASSED] DPI
[11:39:49] [PASSED] Writeback
[11:39:49] [PASSED] SPI
[11:39:49] [PASSED] USB
[11:39:49] ===== [PASSED] drm_test_drmm_connector_init_type_valid =====
[11:39:49] =============== [PASSED] drmm_connector_init ===============
[11:39:49] ========= drm_connector_dynamic_init (6 subtests) ==========
[11:39:49] [PASSED] drm_test_drm_connector_dynamic_init
[11:39:49] [PASSED] drm_test_drm_connector_dynamic_init_null_ddc
[11:39:49] [PASSED] drm_test_drm_connector_dynamic_init_not_added
[11:39:49] [PASSED] drm_test_drm_connector_dynamic_init_properties
[11:39:49] ===== drm_test_drm_connector_dynamic_init_type_valid  ======
[11:39:49] [PASSED] Unknown
[11:39:49] [PASSED] VGA
[11:39:49] [PASSED] DVI-I
[11:39:49] [PASSED] DVI-D
[11:39:49] [PASSED] DVI-A
[11:39:49] [PASSED] Composite
[11:39:49] [PASSED] SVIDEO
[11:39:49] [PASSED] LVDS
[11:39:49] [PASSED] Component
[11:39:49] [PASSED] DIN
[11:39:49] [PASSED] DP
[11:39:49] [PASSED] HDMI-A
[11:39:49] [PASSED] HDMI-B
[11:39:49] [PASSED] TV
[11:39:49] [PASSED] eDP
[11:39:49] [PASSED] Virtual
[11:39:49] [PASSED] DSI
[11:39:49] [PASSED] DPI
[11:39:49] [PASSED] Writeback
[11:39:49] [PASSED] SPI
[11:39:49] [PASSED] USB
[11:39:49] = [PASSED] drm_test_drm_connector_dynamic_init_type_valid ==
[11:39:49] ======== drm_test_drm_connector_dynamic_init_name  =========
[11:39:49] [PASSED] Unknown
[11:39:49] [PASSED] VGA
[11:39:49] [PASSED] DVI-I
[11:39:49] [PASSED] DVI-D
[11:39:49] [PASSED] DVI-A
[11:39:49] [PASSED] Composite
[11:39:49] [PASSED] SVIDEO
[11:39:49] [PASSED] LVDS
[11:39:49] [PASSED] Component
[11:39:49] [PASSED] DIN
[11:39:49] [PASSED] DP
[11:39:49] [PASSED] HDMI-A
[11:39:49] [PASSED] HDMI-B
[11:39:49] [PASSED] TV
[11:39:49] [PASSED] eDP
[11:39:49] [PASSED] Virtual
[11:39:49] [PASSED] DSI
[11:39:49] [PASSED] DPI
[11:39:49] [PASSED] Writeback
[11:39:49] [PASSED] SPI
[11:39:49] [PASSED] USB
[11:39:49] ==== [PASSED] drm_test_drm_connector_dynamic_init_name =====
[11:39:49] =========== [PASSED] drm_connector_dynamic_init ============
[11:39:49] ==== drm_connector_dynamic_register_early (4 subtests) =====
[11:39:49] [PASSED] drm_test_drm_connector_dynamic_register_early_on_list
[11:39:49] [PASSED] drm_test_drm_connector_dynamic_register_early_defer
[11:39:49] [PASSED] drm_test_drm_connector_dynamic_register_early_no_init
[11:39:49] [PASSED] drm_test_drm_connector_dynamic_register_early_no_mode_object
[11:39:49] ====== [PASSED] drm_connector_dynamic_register_early =======
[11:39:49] ======= drm_connector_dynamic_register (7 subtests) ========
[11:39:49] [PASSED] drm_test_drm_connector_dynamic_register_on_list
[11:39:49] [PASSED] drm_test_drm_connector_dynamic_register_no_defer
[11:39:49] [PASSED] drm_test_drm_connector_dynamic_register_no_init
[11:39:49] [PASSED] drm_test_drm_connector_dynamic_register_mode_object
[11:39:49] [PASSED] drm_test_drm_connector_dynamic_register_sysfs
[11:39:49] [PASSED] drm_test_drm_connector_dynamic_register_sysfs_name
[11:39:49] [PASSED] drm_test_drm_connector_dynamic_register_debugfs
[11:39:49] ========= [PASSED] drm_connector_dynamic_register ==========
[11:39:49] = drm_connector_attach_broadcast_rgb_property (2 subtests) =
[11:39:49] [PASSED] drm_test_drm_connector_attach_broadcast_rgb_property
[11:39:49] [PASSED] drm_test_drm_connector_attach_broadcast_rgb_property_hdmi_connector
[11:39:49] === [PASSED] drm_connector_attach_broadcast_rgb_property ===
[11:39:49] ========== drm_get_tv_mode_from_name (2 subtests) ==========
[11:39:49] ========== drm_test_get_tv_mode_from_name_valid  ===========
[11:39:49] [PASSED] NTSC
[11:39:49] [PASSED] NTSC-443
[11:39:49] [PASSED] NTSC-J
[11:39:49] [PASSED] PAL
[11:39:49] [PASSED] PAL-M
[11:39:49] [PASSED] PAL-N
[11:39:49] [PASSED] SECAM
[11:39:49] [PASSED] Mono
[11:39:49] ====== [PASSED] drm_test_get_tv_mode_from_name_valid =======
[11:39:49] [PASSED] drm_test_get_tv_mode_from_name_truncated
[11:39:49] ============ [PASSED] drm_get_tv_mode_from_name ============
[11:39:49] = drm_test_connector_hdmi_compute_mode_clock (12 subtests) =
[11:39:49] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb
[11:39:49] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_10bpc
[11:39:49] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_10bpc_vic_1
[11:39:49] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_12bpc
[11:39:49] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_12bpc_vic_1
[11:39:49] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_double
[11:39:49] = drm_test_connector_hdmi_compute_mode_clock_yuv420_valid  =
[11:39:49] [PASSED] VIC 96
[11:39:49] [PASSED] VIC 97
[11:39:49] [PASSED] VIC 101
[11:39:49] [PASSED] VIC 102
[11:39:49] [PASSED] VIC 106
[11:39:49] [PASSED] VIC 107
[11:39:49] === [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv420_valid ===
[11:39:49] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv420_10_bpc
[11:39:49] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv420_12_bpc
[11:39:49] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv422_8_bpc
[11:39:49] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv422_10_bpc
[11:39:49] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv422_12_bpc
[11:39:49] === [PASSED] drm_test_connector_hdmi_compute_mode_clock ====
[11:39:49] == drm_hdmi_connector_get_broadcast_rgb_name (2 subtests) ==
[11:39:49] === drm_test_drm_hdmi_connector_get_broadcast_rgb_name  ====
[11:39:49] [PASSED] Automatic
[11:39:49] [PASSED] Full
[11:39:49] [PASSED] Limited 16:235
[11:39:49] === [PASSED] drm_test_drm_hdmi_connector_get_broadcast_rgb_name ===
[11:39:49] [PASSED] drm_test_drm_hdmi_connector_get_broadcast_rgb_name_invalid
[11:39:49] ==== [PASSED] drm_hdmi_connector_get_broadcast_rgb_name ====
[11:39:49] == drm_hdmi_connector_get_output_format_name (2 subtests) ==
[11:39:49] === drm_test_drm_hdmi_connector_get_output_format_name  ====
[11:39:49] [PASSED] RGB
[11:39:49] [PASSED] YUV 4:2:0
[11:39:49] [PASSED] YUV 4:2:2
[11:39:49] [PASSED] YUV 4:4:4
[11:39:49] === [PASSED] drm_test_drm_hdmi_connector_get_output_format_name ===
[11:39:49] [PASSED] drm_test_drm_hdmi_connector_get_output_format_name_invalid
[11:39:49] ==== [PASSED] drm_hdmi_connector_get_output_format_name ====
[11:39:49] ============= drm_damage_helper (21 subtests) ==============
[11:39:49] [PASSED] drm_test_damage_iter_no_damage
[11:39:49] [PASSED] drm_test_damage_iter_no_damage_fractional_src
[11:39:49] [PASSED] drm_test_damage_iter_no_damage_src_moved
[11:39:49] [PASSED] drm_test_damage_iter_no_damage_fractional_src_moved
[11:39:49] [PASSED] drm_test_damage_iter_no_damage_not_visible
[11:39:49] [PASSED] drm_test_damage_iter_no_damage_no_crtc
[11:39:49] [PASSED] drm_test_damage_iter_no_damage_no_fb
[11:39:49] [PASSED] drm_test_damage_iter_simple_damage
[11:39:49] [PASSED] drm_test_damage_iter_single_damage
[11:39:49] [PASSED] drm_test_damage_iter_single_damage_intersect_src
[11:39:49] [PASSED] drm_test_damage_iter_single_damage_outside_src
[11:39:49] [PASSED] drm_test_damage_iter_single_damage_fractional_src
[11:39:49] [PASSED] drm_test_damage_iter_single_damage_intersect_fractional_src
[11:39:49] [PASSED] drm_test_damage_iter_single_damage_outside_fractional_src
[11:39:49] [PASSED] drm_test_damage_iter_single_damage_src_moved
[11:39:49] [PASSED] drm_test_damage_iter_single_damage_fractional_src_moved
[11:39:49] [PASSED] drm_test_damage_iter_damage
[11:39:49] [PASSED] drm_test_damage_iter_damage_one_intersect
[11:39:49] [PASSED] drm_test_damage_iter_damage_one_outside
[11:39:49] [PASSED] drm_test_damage_iter_damage_src_moved
[11:39:49] [PASSED] drm_test_damage_iter_damage_not_visible
[11:39:49] ================ [PASSED] drm_damage_helper ================
[11:39:49] ============== drm_dp_mst_helper (3 subtests) ==============
[11:39:49] ============== drm_test_dp_mst_calc_pbn_mode  ==============
[11:39:49] [PASSED] Clock 154000 BPP 30 DSC disabled
[11:39:49] [PASSED] Clock 234000 BPP 30 DSC disabled
[11:39:49] [PASSED] Clock 297000 BPP 24 DSC disabled
[11:39:49] [PASSED] Clock 332880 BPP 24 DSC enabled
[11:39:49] [PASSED] Clock 324540 BPP 24 DSC enabled
[11:39:49] ========== [PASSED] drm_test_dp_mst_calc_pbn_mode ==========
[11:39:49] ============== drm_test_dp_mst_calc_pbn_div  ===============
[11:39:49] [PASSED] Link rate 2000000 lane count 4
[11:39:49] [PASSED] Link rate 2000000 lane count 2
[11:39:49] [PASSED] Link rate 2000000 lane count 1
[11:39:49] [PASSED] Link rate 1350000 lane count 4
[11:39:49] [PASSED] Link rate 1350000 lane count 2
[11:39:49] [PASSED] Link rate 1350000 lane count 1
[11:39:49] [PASSED] Link rate 1000000 lane count 4
[11:39:49] [PASSED] Link rate 1000000 lane count 2
[11:39:49] [PASSED] Link rate 1000000 lane count 1
[11:39:49] [PASSED] Link rate 810000 lane count 4
[11:39:49] [PASSED] Link rate 810000 lane count 2
[11:39:49] [PASSED] Link rate 810000 lane count 1
[11:39:49] [PASSED] Link rate 540000 lane count 4
[11:39:49] [PASSED] Link rate 540000 lane count 2
[11:39:49] [PASSED] Link rate 540000 lane count 1
[11:39:49] [PASSED] Link rate 270000 lane count 4
[11:39:49] [PASSED] Link rate 270000 lane count 2
[11:39:49] [PASSED] Link rate 270000 lane count 1
[11:39:49] [PASSED] Link rate 162000 lane count 4
[11:39:49] [PASSED] Link rate 162000 lane count 2
[11:39:49] [PASSED] Link rate 162000 lane count 1
[11:39:49] ========== [PASSED] drm_test_dp_mst_calc_pbn_div ===========
[11:39:49] ========= drm_test_dp_mst_sideband_msg_req_decode  =========
[11:39:49] [PASSED] DP_ENUM_PATH_RESOURCES with port number
[11:39:49] [PASSED] DP_POWER_UP_PHY with port number
[11:39:49] [PASSED] DP_POWER_DOWN_PHY with port number
[11:39:49] [PASSED] DP_ALLOCATE_PAYLOAD with SDP stream sinks
[11:39:49] [PASSED] DP_ALLOCATE_PAYLOAD with port number
[11:39:49] [PASSED] DP_ALLOCATE_PAYLOAD with VCPI
[11:39:49] [PASSED] DP_ALLOCATE_PAYLOAD with PBN
[11:39:49] [PASSED] DP_QUERY_PAYLOAD with port number
[11:39:49] [PASSED] DP_QUERY_PAYLOAD with VCPI
[11:39:49] [PASSED] DP_REMOTE_DPCD_READ with port number
[11:39:49] [PASSED] DP_REMOTE_DPCD_READ with DPCD address
[11:39:49] [PASSED] DP_REMOTE_DPCD_READ with max number of bytes
[11:39:49] [PASSED] DP_REMOTE_DPCD_WRITE with port number
[11:39:49] [PASSED] DP_REMOTE_DPCD_WRITE with DPCD address
[11:39:49] [PASSED] DP_REMOTE_DPCD_WRITE with data array
[11:39:49] [PASSED] DP_REMOTE_I2C_READ with port number
[11:39:49] [PASSED] DP_REMOTE_I2C_READ with I2C device ID
[11:39:49] [PASSED] DP_REMOTE_I2C_READ with transactions array
[11:39:49] [PASSED] DP_REMOTE_I2C_WRITE with port number
[11:39:49] [PASSED] DP_REMOTE_I2C_WRITE with I2C device ID
[11:39:49] [PASSED] DP_REMOTE_I2C_WRITE with data array
[11:39:49] [PASSED] DP_QUERY_STREAM_ENC_STATUS with stream ID
[11:39:49] [PASSED] DP_QUERY_STREAM_ENC_STATUS with client ID
[11:39:49] [PASSED] DP_QUERY_STREAM_ENC_STATUS with stream event
[11:39:49] [PASSED] DP_QUERY_STREAM_ENC_STATUS with valid stream event
[11:39:49] [PASSED] DP_QUERY_STREAM_ENC_STATUS with stream behavior
[11:39:49] [PASSED] DP_QUERY_STREAM_ENC_STATUS with a valid stream behavior
[11:39:49] ===== [PASSED] drm_test_dp_mst_sideband_msg_req_decode =====
[11:39:49] ================ [PASSED] drm_dp_mst_helper ================
[11:39:49] ================== drm_exec (7 subtests) ===================
[11:39:49] [PASSED] sanitycheck
[11:39:49] [PASSED] test_lock
[11:39:49] [PASSED] test_lock_unlock
[11:39:49] [PASSED] test_duplicates
[11:39:49] [PASSED] test_prepare
[11:39:49] [PASSED] test_prepare_array
[11:39:49] [PASSED] test_multiple_loops
[11:39:49] ==================== [PASSED] drm_exec =====================
[11:39:49] =========== drm_format_helper_test (17 subtests) ===========
[11:39:49] ============== drm_test_fb_xrgb8888_to_gray8  ==============
[11:39:49] [PASSED] single_pixel_source_buffer
[11:39:49] [PASSED] single_pixel_clip_rectangle
[11:39:49] [PASSED] well_known_colors
[11:39:49] [PASSED] destination_pitch
[11:39:49] ========== [PASSED] drm_test_fb_xrgb8888_to_gray8 ==========
[11:39:49] ============= drm_test_fb_xrgb8888_to_rgb332  ==============
[11:39:49] [PASSED] single_pixel_source_buffer
[11:39:49] [PASSED] single_pixel_clip_rectangle
[11:39:49] [PASSED] well_known_colors
[11:39:49] [PASSED] destination_pitch
[11:39:49] ========= [PASSED] drm_test_fb_xrgb8888_to_rgb332 ==========
[11:39:49] ============= drm_test_fb_xrgb8888_to_rgb565  ==============
[11:39:49] [PASSED] single_pixel_source_buffer
[11:39:49] [PASSED] single_pixel_clip_rectangle
[11:39:49] [PASSED] well_known_colors
[11:39:49] [PASSED] destination_pitch
[11:39:49] ========= [PASSED] drm_test_fb_xrgb8888_to_rgb565 ==========
[11:39:49] ============ drm_test_fb_xrgb8888_to_xrgb1555  =============
[11:39:49] [PASSED] single_pixel_source_buffer
[11:39:49] [PASSED] single_pixel_clip_rectangle
[11:39:49] [PASSED] well_known_colors
[11:39:49] [PASSED] destination_pitch
[11:39:49] ======== [PASSED] drm_test_fb_xrgb8888_to_xrgb1555 =========
[11:39:49] ============ drm_test_fb_xrgb8888_to_argb1555  =============
[11:39:49] [PASSED] single_pixel_source_buffer
[11:39:49] [PASSED] single_pixel_clip_rectangle
[11:39:49] [PASSED] well_known_colors
[11:39:49] [PASSED] destination_pitch
[11:39:49] ======== [PASSED] drm_test_fb_xrgb8888_to_argb1555 =========
[11:39:49] ============ drm_test_fb_xrgb8888_to_rgba5551  =============
[11:39:49] [PASSED] single_pixel_source_buffer
[11:39:49] [PASSED] single_pixel_clip_rectangle
[11:39:49] [PASSED] well_known_colors
[11:39:49] [PASSED] destination_pitch
[11:39:49] ======== [PASSED] drm_test_fb_xrgb8888_to_rgba5551 =========
[11:39:49] ============= drm_test_fb_xrgb8888_to_rgb888  ==============
[11:39:49] [PASSED] single_pixel_source_buffer
[11:39:49] [PASSED] single_pixel_clip_rectangle
[11:39:49] [PASSED] well_known_colors
[11:39:49] [PASSED] destination_pitch
[11:39:49] ========= [PASSED] drm_test_fb_xrgb8888_to_rgb888 ==========
[11:39:49] ============= drm_test_fb_xrgb8888_to_bgr888  ==============
[11:39:49] [PASSED] single_pixel_source_buffer
[11:39:49] [PASSED] single_pixel_clip_rectangle
[11:39:49] [PASSED] well_known_colors
[11:39:49] [PASSED] destination_pitch
[11:39:49] ========= [PASSED] drm_test_fb_xrgb8888_to_bgr888 ==========
[11:39:49] ============ drm_test_fb_xrgb8888_to_argb8888  =============
[11:39:49] [PASSED] single_pixel_source_buffer
[11:39:49] [PASSED] single_pixel_clip_rectangle
[11:39:49] [PASSED] well_known_colors
[11:39:49] [PASSED] destination_pitch
[11:39:49] ======== [PASSED] drm_test_fb_xrgb8888_to_argb8888 =========
[11:39:49] =========== drm_test_fb_xrgb8888_to_xrgb2101010  ===========
[11:39:49] [PASSED] single_pixel_source_buffer
[11:39:49] [PASSED] single_pixel_clip_rectangle
[11:39:49] [PASSED] well_known_colors
[11:39:49] [PASSED] destination_pitch
[11:39:49] ======= [PASSED] drm_test_fb_xrgb8888_to_xrgb2101010 =======
[11:39:49] =========== drm_test_fb_xrgb8888_to_argb2101010  ===========
[11:39:49] [PASSED] single_pixel_source_buffer
[11:39:49] [PASSED] single_pixel_clip_rectangle
[11:39:49] [PASSED] well_known_colors
[11:39:49] [PASSED] destination_pitch
[11:39:49] ======= [PASSED] drm_test_fb_xrgb8888_to_argb2101010 =======
[11:39:49] ============== drm_test_fb_xrgb8888_to_mono  ===============
[11:39:49] [PASSED] single_pixel_source_buffer
[11:39:49] [PASSED] single_pixel_clip_rectangle
[11:39:49] [PASSED] well_known_colors
[11:39:49] [PASSED] destination_pitch
[11:39:49] ========== [PASSED] drm_test_fb_xrgb8888_to_mono ===========
[11:39:49] ==================== drm_test_fb_swab  =====================
[11:39:49] [PASSED] single_pixel_source_buffer
[11:39:49] [PASSED] single_pixel_clip_rectangle
[11:39:49] [PASSED] well_known_colors
[11:39:49] [PASSED] destination_pitch
[11:39:49] ================ [PASSED] drm_test_fb_swab =================
[11:39:49] ============ drm_test_fb_xrgb8888_to_xbgr8888  =============
[11:39:49] [PASSED] single_pixel_source_buffer
[11:39:49] [PASSED] single_pixel_clip_rectangle
[11:39:49] [PASSED] well_known_colors
[11:39:49] [PASSED] destination_pitch
[11:39:49] ======== [PASSED] drm_test_fb_xrgb8888_to_xbgr8888 =========
[11:39:49] ============ drm_test_fb_xrgb8888_to_abgr8888  =============
[11:39:49] [PASSED] single_pixel_source_buffer
[11:39:49] [PASSED] single_pixel_clip_rectangle
[11:39:49] [PASSED] well_known_colors
[11:39:49] [PASSED] destination_pitch
[11:39:49] ======== [PASSED] drm_test_fb_xrgb8888_to_abgr8888 =========
[11:39:49] ================= drm_test_fb_clip_offset  =================
[11:39:49] [PASSED] pass through
[11:39:49] [PASSED] horizontal offset
[11:39:49] [PASSED] vertical offset
[11:39:49] [PASSED] horizontal and vertical offset
[11:39:49] [PASSED] horizontal offset (custom pitch)
[11:39:49] [PASSED] vertical offset (custom pitch)
[11:39:49] [PASSED] horizontal and vertical offset (custom pitch)
[11:39:49] ============= [PASSED] drm_test_fb_clip_offset =============
[11:39:49] =================== drm_test_fb_memcpy  ====================
[11:39:49] [PASSED] single_pixel_source_buffer: XR24 little-endian (0x34325258)
[11:39:49] [PASSED] single_pixel_source_buffer: XRA8 little-endian (0x38415258)
[11:39:49] [PASSED] single_pixel_source_buffer: YU24 little-endian (0x34325559)
[11:39:49] [PASSED] single_pixel_clip_rectangle: XB24 little-endian (0x34324258)
[11:39:49] [PASSED] single_pixel_clip_rectangle: XRA8 little-endian (0x38415258)
[11:39:49] [PASSED] single_pixel_clip_rectangle: YU24 little-endian (0x34325559)
[11:39:49] [PASSED] well_known_colors: XB24 little-endian (0x34324258)
[11:39:49] [PASSED] well_known_colors: XRA8 little-endian (0x38415258)
[11:39:49] [PASSED] well_known_colors: YU24 little-endian (0x34325559)
[11:39:49] [PASSED] destination_pitch: XB24 little-endian (0x34324258)
[11:39:49] [PASSED] destination_pitch: XRA8 little-endian (0x38415258)
[11:39:49] [PASSED] destination_pitch: YU24 little-endian (0x34325559)
[11:39:49] =============== [PASSED] drm_test_fb_memcpy ================
[11:39:49] ============= [PASSED] drm_format_helper_test ==============
[11:39:49] ================= drm_format (18 subtests) =================
[11:39:49] [PASSED] drm_test_format_block_width_invalid
[11:39:49] [PASSED] drm_test_format_block_width_one_plane
[11:39:49] [PASSED] drm_test_format_block_width_two_plane
[11:39:49] [PASSED] drm_test_format_block_width_three_plane
[11:39:49] [PASSED] drm_test_format_block_width_tiled
[11:39:49] [PASSED] drm_test_format_block_height_invalid
[11:39:49] [PASSED] drm_test_format_block_height_one_plane
[11:39:49] [PASSED] drm_test_format_block_height_two_plane
[11:39:49] [PASSED] drm_test_format_block_height_three_plane
[11:39:49] [PASSED] drm_test_format_block_height_tiled
[11:39:49] [PASSED] drm_test_format_min_pitch_invalid
[11:39:49] [PASSED] drm_test_format_min_pitch_one_plane_8bpp
[11:39:49] [PASSED] drm_test_format_min_pitch_one_plane_16bpp
[11:39:49] [PASSED] drm_test_format_min_pitch_one_plane_24bpp
[11:39:49] [PASSED] drm_test_format_min_pitch_one_plane_32bpp
[11:39:49] [PASSED] drm_test_format_min_pitch_two_plane
[11:39:49] [PASSED] drm_test_format_min_pitch_three_plane_8bpp
[11:39:49] [PASSED] drm_test_format_min_pitch_tiled
[11:39:49] =================== [PASSED] drm_format ====================
[11:39:49] ============== drm_framebuffer (10 subtests) ===============
[11:39:49] ========== drm_test_framebuffer_check_src_coords  ==========
[11:39:49] [PASSED] Success: source fits into fb
[11:39:49] [PASSED] Fail: overflowing fb with x-axis coordinate
[11:39:49] [PASSED] Fail: overflowing fb with y-axis coordinate
[11:39:49] [PASSED] Fail: overflowing fb with source width
[11:39:49] [PASSED] Fail: overflowing fb with source height
[11:39:49] ====== [PASSED] drm_test_framebuffer_check_src_coords ======
[11:39:49] [PASSED] drm_test_framebuffer_cleanup
[11:39:49] =============== drm_test_framebuffer_create  ===============
[11:39:49] [PASSED] ABGR8888 normal sizes
[11:39:49] [PASSED] ABGR8888 max sizes
[11:39:49] [PASSED] ABGR8888 pitch greater than min required
[11:39:49] [PASSED] ABGR8888 pitch less than min required
[11:39:49] [PASSED] ABGR8888 Invalid width
[11:39:49] [PASSED] ABGR8888 Invalid buffer handle
[11:39:49] [PASSED] No pixel format
[11:39:49] [PASSED] ABGR8888 Width 0
[11:39:49] [PASSED] ABGR8888 Height 0
[11:39:49] [PASSED] ABGR8888 Out of bound height * pitch combination
[11:39:49] [PASSED] ABGR8888 Large buffer offset
[11:39:49] [PASSED] ABGR8888 Buffer offset for inexistent plane
[11:39:49] [PASSED] ABGR8888 Invalid flag
[11:39:49] [PASSED] ABGR8888 Set DRM_MODE_FB_MODIFIERS without modifiers
[11:39:49] [PASSED] ABGR8888 Valid buffer modifier
[11:39:49] [PASSED] ABGR8888 Invalid buffer modifier(DRM_FORMAT_MOD_SAMSUNG_64_32_TILE)
[11:39:49] [PASSED] ABGR8888 Extra pitches without DRM_MODE_FB_MODIFIERS
[11:39:49] [PASSED] ABGR8888 Extra pitches with DRM_MODE_FB_MODIFIERS
[11:39:49] [PASSED] NV12 Normal sizes
[11:39:49] [PASSED] NV12 Max sizes
[11:39:49] [PASSED] NV12 Invalid pitch
[11:39:49] [PASSED] NV12 Invalid modifier/missing DRM_MODE_FB_MODIFIERS flag
[11:39:49] [PASSED] NV12 different  modifier per-plane
[11:39:49] [PASSED] NV12 with DRM_FORMAT_MOD_SAMSUNG_64_32_TILE
[11:39:49] [PASSED] NV12 Valid modifiers without DRM_MODE_FB_MODIFIERS
[11:39:49] [PASSED] NV12 Modifier for inexistent plane
[11:39:49] [PASSED] NV12 Handle for inexistent plane
[11:39:49] [PASSED] NV12 Handle for inexistent plane without DRM_MODE_FB_MODIFIERS
[11:39:49] [PASSED] YVU420 DRM_MODE_FB_MODIFIERS set without modifier
[11:39:49] [PASSED] YVU420 Normal sizes
[11:39:49] [PASSED] YVU420 Max sizes
[11:39:49] [PASSED] YVU420 Invalid pitch
[11:39:49] [PASSED] YVU420 Different pitches
[11:39:49] [PASSED] YVU420 Different buffer offsets/pitches
[11:39:49] [PASSED] YVU420 Modifier set just for plane 0, without DRM_MODE_FB_MODIFIERS
[11:39:49] [PASSED] YVU420 Modifier set just for planes 0, 1, without DRM_MODE_FB_MODIFIERS
[11:39:49] [PASSED] YVU420 Modifier set just for plane 0, 1, with DRM_MODE_FB_MODIFIERS
[11:39:49] [PASSED] YVU420 Valid modifier
[11:39:49] [PASSED] YVU420 Different modifiers per plane
[11:39:49] [PASSED] YVU420 Modifier for inexistent plane
[11:39:49] [PASSED] YUV420_10BIT Invalid modifier(DRM_FORMAT_MOD_LINEAR)
[11:39:49] [PASSED] X0L2 Normal sizes
[11:39:49] [PASSED] X0L2 Max sizes
[11:39:49] [PASSED] X0L2 Invalid pitch
[11:39:49] [PASSED] X0L2 Pitch greater than minimum required
[11:39:49] [PASSED] X0L2 Handle for inexistent plane
[11:39:49] [PASSED] X0L2 Offset for inexistent plane, without DRM_MODE_FB_MODIFIERS set
[11:39:49] [PASSED] X0L2 Modifier without DRM_MODE_FB_MODIFIERS set
[11:39:49] [PASSED] X0L2 Valid modifier
[11:39:49] [PASSED] X0L2 Modifier for inexistent plane
[11:39:49] =========== [PASSED] drm_test_framebuffer_create ===========
[11:39:49] [PASSED] drm_test_framebuffer_free
[11:39:49] [PASSED] drm_test_framebuffer_init
[11:39:49] [PASSED] drm_test_framebuffer_init_bad_format
[11:39:49] [PASSED] drm_test_framebuffer_init_dev_mismatch
[11:39:49] [PASSED] drm_test_framebuffer_lookup
[11:39:49] [PASSED] drm_test_framebuffer_lookup_inexistent
[11:39:49] [PASSED] drm_test_framebuffer_modifiers_not_supported
[11:39:49] ================= [PASSED] drm_framebuffer =================
[11:39:49] ================ drm_gem_shmem (8 subtests) ================
[11:39:49] [PASSED] drm_gem_shmem_test_obj_create
[11:39:49] [PASSED] drm_gem_shmem_test_obj_create_private
[11:39:49] [PASSED] drm_gem_shmem_test_pin_pages
[11:39:49] [PASSED] drm_gem_shmem_test_vmap
[11:39:49] [PASSED] drm_gem_shmem_test_get_sg_table
[11:39:49] [PASSED] drm_gem_shmem_test_get_pages_sgt
[11:39:49] [PASSED] drm_gem_shmem_test_madvise
[11:39:49] [PASSED] drm_gem_shmem_test_purge
[11:39:49] ================== [PASSED] drm_gem_shmem ==================
[11:39:49] === drm_atomic_helper_connector_hdmi_check (29 subtests) ===
[11:39:49] [PASSED] drm_test_check_broadcast_rgb_auto_cea_mode
[11:39:49] [PASSED] drm_test_check_broadcast_rgb_auto_cea_mode_vic_1
[11:39:49] [PASSED] drm_test_check_broadcast_rgb_full_cea_mode
[11:39:49] [PASSED] drm_test_check_broadcast_rgb_full_cea_mode_vic_1
[11:39:49] [PASSED] drm_test_check_broadcast_rgb_limited_cea_mode
[11:39:49] [PASSED] drm_test_check_broadcast_rgb_limited_cea_mode_vic_1
[11:39:49] ====== drm_test_check_broadcast_rgb_cea_mode_yuv420  =======
[11:39:49] [PASSED] Automatic
[11:39:49] [PASSED] Full
[11:39:49] [PASSED] Limited 16:235
[11:39:49] == [PASSED] drm_test_check_broadcast_rgb_cea_mode_yuv420 ===
[11:39:49] [PASSED] drm_test_check_broadcast_rgb_crtc_mode_changed
[11:39:49] [PASSED] drm_test_check_broadcast_rgb_crtc_mode_not_changed
[11:39:49] [PASSED] drm_test_check_disable_connector
[11:39:49] [PASSED] drm_test_check_hdmi_funcs_reject_rate
[11:39:49] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_rgb
[11:39:49] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_yuv420
[11:39:49] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_ignore_yuv422
[11:39:49] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_ignore_yuv420
[11:39:49] [PASSED] drm_test_check_driver_unsupported_fallback_yuv420
[11:39:49] [PASSED] drm_test_check_output_bpc_crtc_mode_changed
[11:39:49] [PASSED] drm_test_check_output_bpc_crtc_mode_not_changed
[11:39:49] [PASSED] drm_test_check_output_bpc_dvi
[11:39:49] [PASSED] drm_test_check_output_bpc_format_vic_1
[11:39:49] [PASSED] drm_test_check_output_bpc_format_display_8bpc_only
[11:39:49] [PASSED] drm_test_check_output_bpc_format_display_rgb_only
[11:39:49] [PASSED] drm_test_check_output_bpc_format_driver_8bpc_only
[11:39:49] [PASSED] drm_test_check_output_bpc_format_driver_rgb_only
[11:39:49] [PASSED] drm_test_check_tmds_char_rate_rgb_8bpc
[11:39:49] [PASSED] drm_test_check_tmds_char_rate_rgb_10bpc
[11:39:49] [PASSED] drm_test_check_tmds_char_rate_rgb_12bpc
[11:39:49] ============ drm_test_check_hdmi_color_format  =============
[11:39:49] [PASSED] AUTO -> RGB
[11:39:49] [PASSED] YCBCR422 -> YUV422
[11:39:49] [PASSED] YCBCR420 -> YUV420
[11:39:49] [PASSED] YCBCR444 -> YUV444
[11:39:49] [PASSED] RGB -> RGB
[11:39:49] ======== [PASSED] drm_test_check_hdmi_color_format =========
[11:39:49] ======== drm_test_check_hdmi_color_format_420_only  ========
[11:39:49] [PASSED] RGB should fail
[11:39:49] [PASSED] YUV444 should fail
[11:39:49] [PASSED] YUV422 should fail
[11:39:49] [PASSED] YUV420 should work
[11:39:49] ==== [PASSED] drm_test_check_hdmi_color_format_420_only ====
[11:39:49] ===== [PASSED] drm_atomic_helper_connector_hdmi_check ======
[11:39:49] === drm_atomic_helper_connector_hdmi_reset (6 subtests) ====
[11:39:49] [PASSED] drm_test_check_broadcast_rgb_value
[11:39:49] [PASSED] drm_test_check_bpc_8_value
[11:39:49] [PASSED] drm_test_check_bpc_10_value
[11:39:49] [PASSED] drm_test_check_bpc_12_value
[11:39:49] [PASSED] drm_test_check_format_value
[11:39:49] [PASSED] drm_test_check_tmds_char_value
[11:39:49] ===== [PASSED] drm_atomic_helper_connector_hdmi_reset ======
[11:39:49] = drm_atomic_helper_connector_hdmi_mode_valid (7 subtests) =
[11:39:49] [PASSED] drm_test_check_mode_valid
[11:39:49] [PASSED] drm_test_check_mode_valid_reject
[11:39:49] [PASSED] drm_test_check_mode_valid_reject_rate
[11:39:49] [PASSED] drm_test_check_mode_valid_reject_max_clock
[11:39:49] [PASSED] drm_test_check_mode_valid_yuv420_only_max_clock
[11:39:49] [PASSED] drm_test_check_mode_valid_reject_yuv420_only_connector
[11:39:49] [PASSED] drm_test_check_mode_valid_accept_yuv420_also_connector_rgb
[11:39:49] === [PASSED] drm_atomic_helper_connector_hdmi_mode_valid ===
[11:39:49] = drm_atomic_helper_connector_hdmi_infoframes (5 subtests) =
[11:39:49] [PASSED] drm_test_check_infoframes
[11:39:49] [PASSED] drm_test_check_reject_avi_infoframe
[11:39:49] [PASSED] drm_test_check_reject_hdr_infoframe_bpc_8
[11:39:49] [PASSED] drm_test_check_reject_hdr_infoframe_bpc_10
[11:39:49] [PASSED] drm_test_check_reject_audio_infoframe
[11:39:49] === [PASSED] drm_atomic_helper_connector_hdmi_infoframes ===
[11:39:49] ================= drm_managed (2 subtests) =================
[11:39:49] [PASSED] drm_test_managed_release_action
[11:39:49] [PASSED] drm_test_managed_run_action
[11:39:49] =================== [PASSED] drm_managed ===================
[11:39:49] =================== drm_mm (6 subtests) ====================
[11:39:49] [PASSED] drm_test_mm_init
[11:39:49] [PASSED] drm_test_mm_debug
[11:39:49] [PASSED] drm_test_mm_align32
[11:39:49] [PASSED] drm_test_mm_align64
[11:39:49] [PASSED] drm_test_mm_lowest
[11:39:49] [PASSED] drm_test_mm_highest
[11:39:49] ===================== [PASSED] drm_mm ======================
[11:39:49] ============= drm_modes_analog_tv (5 subtests) =============
[11:39:49] [PASSED] drm_test_modes_analog_tv_mono_576i
[11:39:49] [PASSED] drm_test_modes_analog_tv_ntsc_480i
[11:39:49] [PASSED] drm_test_modes_analog_tv_ntsc_480i_inlined
[11:39:49] [PASSED] drm_test_modes_analog_tv_pal_576i
[11:39:49] [PASSED] drm_test_modes_analog_tv_pal_576i_inlined
[11:39:49] =============== [PASSED] drm_modes_analog_tv ===============
[11:39:49] ============== drm_panic_helper (3 subtests) ===============
[11:39:50] ============= drm_test_panic_screen_user_map  ==============
[11:39:50] [PASSED] Panic screen user, mode: 1024 x 768 	XR24 little-endian (0x34325258)
[11:39:50] [PASSED] Panic screen user, mode: 494 x 494 	XR24 little-endian (0x34325258)
[11:39:50] [PASSED] Panic screen user, mode: 1920 x 1080 	XR24 little-endian (0x34325258)
[11:39:50] [PASSED] Panic screen user, mode: 1024 x 768 	RG16 little-endian (0x36314752)
[11:39:50] [PASSED] Panic screen user, mode: 1024 x 768 	RG24 little-endian (0x34324752)
[11:39:50] [PASSED] Panic screen kmsg, mode: 1024 x 768 	XR24 little-endian (0x34325258)
[11:39:50] [PASSED] Panic screen kmsg, mode: 494 x 494 	XR24 little-endian (0x34325258)
[11:39:50] [PASSED] Panic screen kmsg, mode: 1920 x 1080 	XR24 little-endian (0x34325258)
[11:39:50] [PASSED] Panic screen kmsg, mode: 1024 x 768 	RG16 little-endian (0x36314752)
[11:39:50] [PASSED] Panic screen kmsg, mode: 1024 x 768 	RG24 little-endian (0x34324752)
[11:39:50] ========= [PASSED] drm_test_panic_screen_user_map ==========
[11:39:50] ============= drm_test_panic_screen_user_page  =============
[11:39:50] [PASSED] Panic screen user, mode: 1024 x 768 	XR24 little-endian (0x34325258)
[11:39:50] [PASSED] Panic screen user, mode: 494 x 494 	XR24 little-endian (0x34325258)
[11:39:50] [PASSED] Panic screen user, mode: 1920 x 1080 	XR24 little-endian (0x34325258)
[11:39:50] [PASSED] Panic screen user, mode: 1024 x 768 	RG16 little-endian (0x36314752)
[11:39:50] [PASSED] Panic screen user, mode: 1024 x 768 	RG24 little-endian (0x34324752)
[11:39:50] [PASSED] Panic screen kmsg, mode: 1024 x 768 	XR24 little-endian (0x34325258)
[11:39:50] [PASSED] Panic screen kmsg, mode: 494 x 494 	XR24 little-endian (0x34325258)
[11:39:50] [PASSED] Panic screen kmsg, mode: 1920 x 1080 	XR24 little-endian (0x34325258)
[11:39:50] [PASSED] Panic screen kmsg, mode: 1024 x 768 	RG16 little-endian (0x36314752)
[11:39:50] [PASSED] Panic screen kmsg, mode: 1024 x 768 	RG24 little-endian (0x34324752)
[11:39:50] ========= [PASSED] drm_test_panic_screen_user_page =========
[11:39:50] ========== drm_test_panic_screen_user_set_pixel  ===========
[11:39:50] [PASSED] Panic screen user, mode: 1024 x 768 	XR24 little-endian (0x34325258)
[11:39:50] [PASSED] Panic screen user, mode: 494 x 494 	XR24 little-endian (0x34325258)
[11:39:50] [PASSED] Panic screen user, mode: 1920 x 1080 	XR24 little-endian (0x34325258)
[11:39:50] [PASSED] Panic screen user, mode: 1024 x 768 	RG16 little-endian (0x36314752)
[11:39:50] [PASSED] Panic screen user, mode: 1024 x 768 	RG24 little-endian (0x34324752)
[11:39:50] [PASSED] Panic screen kmsg, mode: 1024 x 768 	XR24 little-endian (0x34325258)
[11:39:50] [PASSED] Panic screen kmsg, mode: 494 x 494 	XR24 little-endian (0x34325258)
[11:39:50] [PASSED] Panic screen kmsg, mode: 1920 x 1080 	XR24 little-endian (0x34325258)
[11:39:50] [PASSED] Panic screen kmsg, mode: 1024 x 768 	RG16 little-endian (0x36314752)
[11:39:50] [PASSED] Panic screen kmsg, mode: 1024 x 768 	RG24 little-endian (0x34324752)
[11:39:50] ====== [PASSED] drm_test_panic_screen_user_set_pixel =======
[11:39:50] ================ [PASSED] drm_panic_helper =================
[11:39:50] ============== drm_plane_helper (2 subtests) ===============
[11:39:50] =============== drm_test_check_plane_state  ================
[11:39:50] [PASSED] clipping_simple
[11:39:50] [PASSED] clipping_rotate_reflect
[11:39:50] [PASSED] positioning_simple
[11:39:50] [PASSED] upscaling
[11:39:50] [PASSED] downscaling
[11:39:50] [PASSED] rounding1
[11:39:50] [PASSED] rounding2
[11:39:50] [PASSED] rounding3
[11:39:50] [PASSED] rounding4
[11:39:50] =========== [PASSED] drm_test_check_plane_state ============
[11:39:50] =========== drm_test_check_invalid_plane_state  ============
[11:39:50] [PASSED] positioning_invalid
[11:39:50] [PASSED] upscaling_invalid
[11:39:50] [PASSED] downscaling_invalid
[11:39:50] ======= [PASSED] drm_test_check_invalid_plane_state ========
[11:39:50] ================ [PASSED] drm_plane_helper =================
[11:39:50] ====== drm_connector_helper_tv_get_modes (1 subtest) =======
[11:39:50] ====== drm_test_connector_helper_tv_get_modes_check  =======
[11:39:50] [PASSED] None
[11:39:50] [PASSED] PAL
[11:39:50] [PASSED] NTSC
[11:39:50] [PASSED] Both, NTSC Default
[11:39:50] [PASSED] Both, PAL Default
[11:39:50] [PASSED] Both, NTSC Default, with PAL on command-line
[11:39:50] [PASSED] Both, PAL Default, with NTSC on command-line
[11:39:50] == [PASSED] drm_test_connector_helper_tv_get_modes_check ===
[11:39:50] ======== [PASSED] drm_connector_helper_tv_get_modes ========
[11:39:50] ================== drm_rect (9 subtests) ===================
[11:39:50] [PASSED] drm_test_rect_clip_scaled_div_by_zero
[11:39:50] [PASSED] drm_test_rect_clip_scaled_not_clipped
[11:39:50] [PASSED] drm_test_rect_clip_scaled_clipped
[11:39:50] [PASSED] drm_test_rect_clip_scaled_signed_vs_unsigned
[11:39:50] ================= drm_test_rect_intersect  =================
[11:39:50] [PASSED] top-left x bottom-right: 2x2+1+1 x 2x2+0+0
[11:39:50] [PASSED] top-right x bottom-left: 2x2+0+0 x 2x2+1-1
[11:39:50] [PASSED] bottom-left x top-right: 2x2+1-1 x 2x2+0+0
[11:39:50] [PASSED] bottom-right x top-left: 2x2+0+0 x 2x2+1+1
[11:39:50] [PASSED] right x left: 2x1+0+0 x 3x1+1+0
[11:39:50] [PASSED] left x right: 3x1+1+0 x 2x1+0+0
[11:39:50] [PASSED] up x bottom: 1x2+0+0 x 1x3+0-1
[11:39:50] [PASSED] bottom x up: 1x3+0-1 x 1x2+0+0
[11:39:50] [PASSED] touching corner: 1x1+0+0 x 2x2+1+1
[11:39:50] [PASSED] touching side: 1x1+0+0 x 1x1+1+0
[11:39:50] [PASSED] equal rects: 2x2+0+0 x 2x2+0+0
[11:39:50] [PASSED] inside another: 2x2+0+0 x 1x1+1+1
[11:39:50] [PASSED] far away: 1x1+0+0 x 1x1+3+6
[11:39:50] [PASSED] points intersecting: 0x0+5+10 x 0x0+5+10
[11:39:50] [PASSED] points not intersecting: 0x0+0+0 x 0x0+5+10
[11:39:50] ============= [PASSED] drm_test_rect_intersect =============
[11:39:50] ================ drm_test_rect_calc_hscale  ================
[11:39:50] [PASSED] normal use
[11:39:50] [PASSED] out of max range
[11:39:50] [PASSED] out of min range
[11:39:50] [PASSED] zero dst
[11:39:50] [PASSED] negative src
[11:39:50] [PASSED] negative dst
[11:39:50] ============ [PASSED] drm_test_rect_calc_hscale ============
[11:39:50] ================ drm_test_rect_calc_vscale  ================
[11:39:50] [PASSED] normal use
[11:39:50] [PASSED] out of max range
[11:39:50] [PASSED] out of min range
[11:39:50] [PASSED] zero dst
[11:39:50] [PASSED] negative src
[11:39:50] [PASSED] negative dst
[11:39:50] ============ [PASSED] drm_test_rect_calc_vscale ============
[11:39:50] ================== drm_test_rect_rotate  ===================
[11:39:50] [PASSED] reflect-x
[11:39:50] [PASSED] reflect-y
[11:39:50] [PASSED] rotate-0
[11:39:50] [PASSED] rotate-90
[11:39:50] [PASSED] rotate-180
[11:39:50] [PASSED] rotate-270
[11:39:50] ============== [PASSED] drm_test_rect_rotate ===============
[11:39:50] ================ drm_test_rect_rotate_inv  =================
[11:39:50] [PASSED] reflect-x
[11:39:50] [PASSED] reflect-y
[11:39:50] [PASSED] rotate-0
[11:39:50] [PASSED] rotate-90
[11:39:50] [PASSED] rotate-180
[11:39:50] [PASSED] rotate-270
[11:39:50] ============ [PASSED] drm_test_rect_rotate_inv =============
[11:39:50] ==================== [PASSED] drm_rect =====================
[11:39:50] ============ drm_sysfb_modeset_test (1 subtest) ============
[11:39:50] ============ drm_test_sysfb_build_fourcc_list  =============
[11:39:50] [PASSED] no native formats
[11:39:50] [PASSED] XRGB8888 as native format
[11:39:50] [PASSED] remove duplicates
[11:39:50] [PASSED] convert alpha formats
[11:39:50] [PASSED] random formats
[11:39:50] ======== [PASSED] drm_test_sysfb_build_fourcc_list =========
[11:39:50] ============= [PASSED] drm_sysfb_modeset_test ==============
[11:39:50] ================== drm_fixp (2 subtests) ===================
[11:39:50] [PASSED] drm_test_int2fixp
[11:39:50] [PASSED] drm_test_sm2fixp
[11:39:50] ==================== [PASSED] drm_fixp =====================
[11:39:50] ============================================================
[11:39:50] Testing complete. Ran 671 tests: passed: 671
[11:39:50] Elapsed time: 27.506s total, 1.780s configuring, 25.260s building, 0.461s running

+ for kcfg in "${kunitconfigs[@]}"
+ [[ ! -f /kernel/drivers/gpu/drm/ttm/tests/.kunitconfig ]]
+ /kernel/tools/testing/kunit/kunit.py run --kunitconfig /kernel/drivers/gpu/drm/ttm/tests/.kunitconfig
[11:39:50] Configuring KUnit Kernel ...
Regenerating .config ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
[11:39:52] Building KUnit Kernel ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
Building with:
$ make all compile_commands.json scripts_gdb ARCH=um O=.kunit --jobs=48
[11:40:02] Starting KUnit Kernel (1/1)...
[11:40:02] ============================================================
Running tests with:
$ .kunit/linux kunit.enable=1 mem=1G console=tty kunit_shutdown=halt
[11:40:02] ============= refcount_interrupt (4 subtests) ==============
[11:40:02] [PASSED] test_single_irq_change
[11:40:02] [PASSED] test_nested_irq_change
[11:40:02] [PASSED] test_multiple_irq_change
[11:40:02] [PASSED] test_irq_save
[11:40:02] =============== [PASSED] refcount_interrupt ================
[11:40:02] ================= ttm_device (5 subtests) ==================
[11:40:02] [PASSED] ttm_device_init_basic
[11:40:02] [PASSED] ttm_device_init_multiple
[11:40:02] [PASSED] ttm_device_fini_basic
[11:40:02] [PASSED] ttm_device_init_no_vma_man
[11:40:02] ================== ttm_device_init_pools  ==================
[11:40:02] [PASSED] No DMA allocations, no DMA32 required
[11:40:02] [PASSED] DMA allocations, DMA32 required
[11:40:02] [PASSED] No DMA allocations, DMA32 required
[11:40:02] [PASSED] DMA allocations, no DMA32 required
[11:40:02] ============== [PASSED] ttm_device_init_pools ==============
[11:40:02] =================== [PASSED] ttm_device ====================
[11:40:02] ================== ttm_pool (8 subtests) ===================
[11:40:02] ================== ttm_pool_alloc_basic  ===================
[11:40:02] [PASSED] One page
[11:40:02] [PASSED] More than one page
[11:40:02] [PASSED] Above the allocation limit
[11:40:02] [PASSED] One page, with coherent DMA mappings enabled
[11:40:02] [PASSED] Above the allocation limit, with coherent DMA mappings enabled
[11:40:02] ============== [PASSED] ttm_pool_alloc_basic ===============
[11:40:02] ============== ttm_pool_alloc_basic_dma_addr  ==============
[11:40:02] [PASSED] One page
[11:40:02] [PASSED] More than one page
[11:40:02] [PASSED] Above the allocation limit
[11:40:02] [PASSED] One page, with coherent DMA mappings enabled
[11:40:02] [PASSED] Above the allocation limit, with coherent DMA mappings enabled
[11:40:02] ========== [PASSED] ttm_pool_alloc_basic_dma_addr ==========
[11:40:02] [PASSED] ttm_pool_alloc_order_caching_match
[11:40:02] [PASSED] ttm_pool_alloc_caching_mismatch
[11:40:02] [PASSED] ttm_pool_alloc_order_mismatch
[11:40:02] [PASSED] ttm_pool_free_dma_alloc
[11:40:02] [PASSED] ttm_pool_free_no_dma_alloc
[11:40:02] [PASSED] ttm_pool_fini_basic
[11:40:02] ==================== [PASSED] ttm_pool =====================
[11:40:02] ================ ttm_resource (8 subtests) =================
[11:40:02] ================= ttm_resource_init_basic  =================
[11:40:02] [PASSED] Init resource in TTM_PL_SYSTEM
[11:40:02] [PASSED] Init resource in TTM_PL_VRAM
[11:40:02] [PASSED] Init resource in a private placement
[11:40:02] [PASSED] Init resource in TTM_PL_SYSTEM, set placement flags
[11:40:02] ============= [PASSED] ttm_resource_init_basic =============
[11:40:02] [PASSED] ttm_resource_init_pinned
[11:40:02] [PASSED] ttm_resource_fini_basic
[11:40:02] [PASSED] ttm_resource_manager_init_basic
[11:40:02] [PASSED] ttm_resource_manager_usage_basic
[11:40:02] [PASSED] ttm_resource_manager_set_used_basic
[11:40:02] [PASSED] ttm_sys_man_alloc_basic
[11:40:02] [PASSED] ttm_sys_man_free_basic
[11:40:02] ================== [PASSED] ttm_resource ===================
[11:40:02] =================== ttm_tt (15 subtests) ===================
[11:40:02] ==================== ttm_tt_init_basic  ====================
[11:40:02] [PASSED] Page-aligned size
[11:40:02] [PASSED] Extra pages requested
[11:40:02] ================ [PASSED] ttm_tt_init_basic ================
[11:40:02] [PASSED] ttm_tt_init_misaligned
[11:40:02] [PASSED] ttm_tt_fini_basic
[11:40:02] [PASSED] ttm_tt_fini_sg
[11:40:02] [PASSED] ttm_tt_fini_shmem
[11:40:02] [PASSED] ttm_tt_create_basic
[11:40:02] [PASSED] ttm_tt_create_invalid_bo_type
[11:40:02] [PASSED] ttm_tt_create_ttm_exists
[11:40:02] [PASSED] ttm_tt_create_failed
[11:40:02] [PASSED] ttm_tt_destroy_basic
[11:40:02] [PASSED] ttm_tt_populate_null_ttm
[11:40:02] [PASSED] ttm_tt_populate_populated_ttm
[11:40:02] [PASSED] ttm_tt_unpopulate_basic
[11:40:02] [PASSED] ttm_tt_unpopulate_empty_ttm
[11:40:02] [PASSED] ttm_tt_swapin_basic
[11:40:02] ===================== [PASSED] ttm_tt ======================
[11:40:02] =================== ttm_bo (14 subtests) ===================
[11:40:02] =========== ttm_bo_reserve_optimistic_no_ticket  ===========
[11:40:02] [PASSED] Cannot be interrupted and sleeps
[11:40:02] [PASSED] Cannot be interrupted, locks straight away
[11:40:02] [PASSED] Can be interrupted, sleeps
[11:40:02] ======= [PASSED] ttm_bo_reserve_optimistic_no_ticket =======
[11:40:02] [PASSED] ttm_bo_reserve_locked_no_sleep
[11:40:02] [PASSED] ttm_bo_reserve_no_wait_ticket
[11:40:02] [PASSED] ttm_bo_reserve_double_resv
[11:40:02] [PASSED] ttm_bo_reserve_interrupted
[11:40:02] [PASSED] ttm_bo_reserve_deadlock
[11:40:02] [PASSED] ttm_bo_unreserve_basic
[11:40:02] [PASSED] ttm_bo_unreserve_pinned
[11:40:02] [PASSED] ttm_bo_unreserve_bulk
[11:40:02] [PASSED] ttm_bo_fini_basic
[11:40:02] [PASSED] ttm_bo_fini_shared_resv
[11:40:02] [PASSED] ttm_bo_pin_basic
[11:40:02] [PASSED] ttm_bo_pin_unpin_resource
[11:40:02] [PASSED] ttm_bo_multiple_pin_one_unpin
[11:40:02] ===================== [PASSED] ttm_bo ======================
[11:40:02] ============== ttm_bo_validate (22 subtests) ===============
[11:40:02] ============== ttm_bo_init_reserved_sys_man  ===============
[11:40:02] [PASSED] Buffer object for userspace
[11:40:02] [PASSED] Kernel buffer object
[11:40:02] [PASSED] Shared buffer object
[11:40:02] ========== [PASSED] ttm_bo_init_reserved_sys_man ===========
[11:40:02] ============== ttm_bo_init_reserved_mock_man  ==============
[11:40:02] [PASSED] Buffer object for userspace
[11:40:02] [PASSED] Kernel buffer object
[11:40:02] [PASSED] Shared buffer object
[11:40:02] ========== [PASSED] ttm_bo_init_reserved_mock_man ==========
[11:40:02] [PASSED] ttm_bo_init_reserved_resv
[11:40:02] ================== ttm_bo_validate_basic  ==================
[11:40:02] [PASSED] Buffer object for userspace
[11:40:02] [PASSED] Kernel buffer object
[11:40:02] [PASSED] Shared buffer object
[11:40:02] ============== [PASSED] ttm_bo_validate_basic ==============
[11:40:02] [PASSED] ttm_bo_validate_invalid_placement
[11:40:02] ============= ttm_bo_validate_same_placement  ==============
[11:40:02] [PASSED] System manager
[11:40:02] [PASSED] VRAM manager
[11:40:02] ========= [PASSED] ttm_bo_validate_same_placement ==========
[11:40:02] [PASSED] ttm_bo_validate_failed_alloc
[11:40:02] [PASSED] ttm_bo_validate_pinned
[11:40:02] [PASSED] ttm_bo_validate_busy_placement
[11:40:02] ================ ttm_bo_validate_multihop  =================
[11:40:02] [PASSED] Buffer object for userspace
[11:40:02] [PASSED] Kernel buffer object
[11:40:02] [PASSED] Shared buffer object
[11:40:02] ============ [PASSED] ttm_bo_validate_multihop =============
[11:40:02] ========== ttm_bo_validate_no_placement_signaled  ==========
[11:40:02] [PASSED] Buffer object in system domain, no page vector
[11:40:02] [PASSED] Buffer object in system domain with an existing page vector
[11:40:02] ====== [PASSED] ttm_bo_validate_no_placement_signaled ======
[11:40:02] ======== ttm_bo_validate_no_placement_not_signaled  ========
[11:40:02] [PASSED] Buffer object for userspace
[11:40:02] [PASSED] Kernel buffer object
[11:40:02] [PASSED] Shared buffer object
[11:40:02] ==== [PASSED] ttm_bo_validate_no_placement_not_signaled ====
[11:40:02] [PASSED] ttm_bo_validate_move_fence_signaled
[11:40:02] ========= ttm_bo_validate_move_fence_not_signaled  =========
[11:40:02] [PASSED] Waits for GPU
[11:40:02] [PASSED] Tries to lock straight away
[11:40:02] ===== [PASSED] ttm_bo_validate_move_fence_not_signaled =====
[11:40:02] [PASSED] ttm_bo_validate_swapout
[11:40:02] [PASSED] ttm_bo_validate_happy_evict
[11:40:02] [PASSED] ttm_bo_validate_all_pinned_evict
[11:40:02] [PASSED] ttm_bo_validate_allowed_only_evict
[11:40:02] [PASSED] ttm_bo_validate_deleted_evict
[11:40:02] [PASSED] ttm_bo_validate_busy_domain_evict
[11:40:02] [PASSED] ttm_bo_validate_evict_gutting
[11:40:02] [PASSED] ttm_bo_validate_recrusive_evict
[11:40:02] ================= [PASSED] ttm_bo_validate =================
[11:40:02] ============================================================
[11:40:02] Testing complete. Ran 106 tests: passed: 106
[11:40:02] Elapsed time: 12.334s total, 1.807s configuring, 10.261s building, 0.215s running

+ for kcfg in "${kunitconfigs[@]}"
+ [[ ! -f /kernel/drivers/dma-buf/.kunitconfig ]]
+ /kernel/tools/testing/kunit/kunit.py run --kunitconfig /kernel/drivers/dma-buf/.kunitconfig
[11:40:02] Configuring KUnit Kernel ...
Regenerating .config ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
[11:40:04] Building KUnit Kernel ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
Building with:
$ make all compile_commands.json scripts_gdb ARCH=um O=.kunit --jobs=48
[11:40:13] Starting KUnit Kernel (1/1)...
[11:40:13] ============================================================
Running tests with:
$ .kunit/linux kunit.enable=1 mem=1G console=tty kunit_shutdown=halt
[11:40:13] ============= refcount_interrupt (4 subtests) ==============
[11:40:13] [PASSED] test_single_irq_change
[11:40:13] [PASSED] test_nested_irq_change
[11:40:13] [PASSED] test_multiple_irq_change
[11:40:13] [PASSED] test_irq_save
[11:40:13] =============== [PASSED] refcount_interrupt ================
[11:40:13] =============== dma-buf-fence (12 subtests) ================
[11:40:13] [PASSED] test_sanitycheck
[11:40:13] [PASSED] test_signaling
[11:40:13] [PASSED] test_add_callback
[11:40:13] [PASSED] test_late_add_callback
[11:40:13] [PASSED] test_rm_callback
[11:40:13] [PASSED] test_late_rm_callback
[11:40:13] [PASSED] test_status
[11:40:13] [PASSED] test_error
[11:40:13] [PASSED] test_wait
[11:40:13] [PASSED] test_wait_timeout
[11:40:13] [PASSED] test_stub
[11:40:13] [SKIPPED] test_race_signal_callback (requires at least 2 CPUs)
[11:40:13] ================== [PASSED] dma-buf-fence ==================
[11:40:13] ============ dma-buf-fence-chain (11 subtests) =============
[11:40:13] [PASSED] test_sanitycheck
[11:40:13] [PASSED] test_find_seqno
[11:40:13] [PASSED] test_find_signaled
[11:40:13] [PASSED] test_find_out_of_order
[11:40:18] [PASSED] test_find_gap
[11:40:18] [PASSED] test_find_race
[11:40:18] [PASSED] test_signal_forward
[11:40:18] [PASSED] test_signal_backward
[11:40:18] [PASSED] test_wait_forward
[11:40:18] [PASSED] test_wait_backward
[11:40:18] [PASSED] test_wait_random
[11:40:18] =============== [PASSED] dma-buf-fence-chain ===============
[11:40:18] ============ dma-buf-fence-unwrap (10 subtests) ============
[11:40:18] [PASSED] test_sanitycheck
[11:40:18] [PASSED] test_unwrap_array
[11:40:18] [PASSED] test_unwrap_chain
[11:40:18] [PASSED] test_unwrap_chain_array
[11:40:18] [PASSED] test_unwrap_merge
[11:40:18] [PASSED] test_unwrap_merge_duplicate
[11:40:18] [PASSED] test_unwrap_merge_seqno
[11:40:18] [PASSED] test_unwrap_merge_order
[11:40:18] [PASSED] test_unwrap_merge_complex
[11:40:18] [PASSED] test_unwrap_merge_complex_seqno
[11:40:18] ============== [PASSED] dma-buf-fence-unwrap ===============
[11:40:18] ================ dma-buf-resv (5 subtests) =================
[11:40:18] [PASSED] test_sanitycheck
[11:40:18] ===================== test_signaling  ======================
[11:40:18] [PASSED] kernel
[11:40:18] [PASSED] write
[11:40:18] [PASSED] read
[11:40:18] [PASSED] bookkeep
[11:40:18] ================= [PASSED] test_signaling ==================
[11:40:18] ====================== test_for_each  ======================
[11:40:18] [PASSED] kernel
[11:40:18] [PASSED] write
[11:40:18] [PASSED] read
[11:40:18] [PASSED] bookkeep
[11:40:18] ================== [PASSED] test_for_each ==================
[11:40:18] ================= test_for_each_unlocked  ==================
[11:40:18] [PASSED] kernel
[11:40:18] [PASSED] write
[11:40:18] [PASSED] read
[11:40:18] [PASSED] bookkeep
[11:40:18] ============= [PASSED] test_for_each_unlocked ==============
[11:40:18] ===================== test_get_fences  =====================
[11:40:18] [PASSED] kernel
[11:40:18] [PASSED] write
[11:40:18] [PASSED] read
[11:40:18] [PASSED] bookkeep
[11:40:18] ================= [PASSED] test_get_fences =================
[11:40:18] ================== [PASSED] dma-buf-resv ===================
[11:40:18] ============================================================
[11:40:18] Testing complete. Ran 54 tests: passed: 53, skipped: 1
[11:40:18] Elapsed time: 15.786s total, 1.754s configuring, 8.659s building, 5.358s running

+ cleanup
++ stat -c %u:%g /kernel
+ chown -R 1003:1003 /kernel

✓ Xe.CI.BAT: success for drm/xe/hwmon: Update hwmon thermal mailbox (rev2)

[Patchwork]

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== Series Details ==

Series: drm/xe/hwmon: Update hwmon thermal mailbox (rev2)
URL   : https://patchwork.freedesktop.org/series/174898/
State : success

== Summary ==

CI Bug Log - changes from xe-5819-a61293e633b18c618fd2f7d508cf558db0f42227_BAT -> xe-pw-174898v2_BAT
====================================================

Summary
-------

  **SUCCESS**

  No regressions found.

  

Participating hosts (15 -> 15)
------------------------------

  No changes in participating hosts

Known issues
------------

  Here are the changes found in xe-pw-174898v2_BAT that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@xe_waitfence@reltime:
    - bat-ptl-2:          [PASS][1] -> [FAIL][2] ([Intel XE#9115])
   [1]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5819-a61293e633b18c618fd2f7d508cf558db0f42227/bat-ptl-2/igt@xe_waitfence@reltime.html
   [2]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-174898v2/bat-ptl-2/igt@xe_waitfence@reltime.html

  
#### Possible fixes ####

  * igt@xe_waitfence@reltime:
    - bat-wcl-1:          [FAIL][3] ([Intel XE#9115]) -> [PASS][4]
   [3]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5819-a61293e633b18c618fd2f7d508cf558db0f42227/bat-wcl-1/igt@xe_waitfence@reltime.html
   [4]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-174898v2/bat-wcl-1/igt@xe_waitfence@reltime.html

  
  [Intel XE#9115]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/9115


Build changes
-------------

  * Linux: xe-5819-a61293e633b18c618fd2f7d508cf558db0f42227 -> xe-pw-174898v2

  IGT_9111: 4aeabf104b136437d0ccc57caf32a752587d595c @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
  xe-5819-a61293e633b18c618fd2f7d508cf558db0f42227: a61293e633b18c618fd2f7d508cf558db0f42227
  xe-pw-174898v2: 174898v2

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-174898v2/index.html

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