* [PATCH v5 5/7] drm/xe/guc: add TDL, SLICE gfx registers to capture list
2026-10-22 13:29 [PATCH v5 0/7] drm/xe: Capture additional HW register state in devcoredump Nareshkumar Gollakoti
@ 2026-10-22 13:29 ` Nareshkumar Gollakoti
0 siblings, 0 replies; 23+ messages in thread
From: Nareshkumar Gollakoti @ 2026-10-22 13:29 UTC (permalink / raw)
To: intel-xe; +Cc: tejas.upadhyay, Nareshkumar Gollakoti
Add ROW_INSTDONE_TDL_GFX, SS_LSC_HDC_IDLE_TDL_GFX and SLICE_ARB_STATUS
register definitions and include them in the XeHPG extended GuC capture
register list.
v2:(Sashiko)
- Refactored ROW_INSTDONE_TDL_GFX to ROW_INSTDONE_TDL_GFX
- Add SLICE_ARB_STATUS register to xeHP register list
- Refactor commit message
Signed-off-by: Nareshkumar Gollakoti <naresh.kumar.g@intel.com>
---
drivers/gpu/drm/xe/regs/xe_gt_regs.h | 5 +++++
drivers/gpu/drm/xe/xe_guc_capture.c | 5 ++++-
2 files changed, 9 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/xe/regs/xe_gt_regs.h b/drivers/gpu/drm/xe/regs/xe_gt_regs.h
index e9eb0bd04af1..2e4cb4957479 100644
--- a/drivers/gpu/drm/xe/regs/xe_gt_regs.h
+++ b/drivers/gpu/drm/xe/regs/xe_gt_regs.h
@@ -533,6 +533,8 @@
#define PAGE_FLTRPTQ_HEAD_GAMCTRL XE_REG(0xcf90)
#define PAGE_FLTRPTQ_TAIL_GAMCTRL XE_REG(0xcf94)
+#define SLICE_ARB_STATUS XE_REG_MCR(0xd814)
+
#define HALF_SLICE_CHICKEN5 XE_REG_MCR(0xe188, XE_REG_OPTION_MASKED)
#define DISABLE_SAMPLE_G_PERFORMANCE REG_BIT(0)
@@ -597,6 +599,9 @@
#define EU_SYSTOLIC_LIC_THROTTLE_CTL_WITH_LOCK XE_REG_MCR(0xe534)
#define EU_SYSTOLIC_LIC_THROTTLE_CTL_LOCK_BIT REG_BIT(31)
+#define ROW_INSTDONE_TDL_GFX XE_REG_MCR(0xe580)
+#define SS_LSC_HDC_IDLE_TDL_GFX XE_REG_MCR(0xe584)
+
#define XEHP_HDC_CHICKEN0 XE_REG_MCR(0xe5f0, XE_REG_OPTION_MASKED)
#define LSC_L1_FLUSH_CTL_3D_DATAPORT_FLUSH_EVENTS_MASK REG_GENMASK(13, 11)
#define DIS_ATOMIC_CHAINING_TYPED_WRITES REG_BIT(3)
diff --git a/drivers/gpu/drm/xe/xe_guc_capture.c b/drivers/gpu/drm/xe/xe_guc_capture.c
index 3e99aef53b46..6a20eab0f820 100644
--- a/drivers/gpu/drm/xe/xe_guc_capture.c
+++ b/drivers/gpu/drm/xe/xe_guc_capture.c
@@ -376,7 +376,10 @@ static const struct __ext_steer_reg xehpg_extregs[] = {
{"SC_INSTDONE", XEHPG_SC_INSTDONE},
{"SC_INSTDONE_EXTRA", XEHPG_SC_INSTDONE_EXTRA},
{"SC_INSTDONE_EXTRA2", XEHPG_SC_INSTDONE_EXTRA2},
- {"INSTDONE_GEOM_SVGUNIT", XEHPG_INSTDONE_GEOM_SVGUNIT}
+ {"INSTDONE_GEOM_SVGUNIT", XEHPG_INSTDONE_GEOM_SVGUNIT},
+ {"ROW_INSTDONE_TDL_GFX", ROW_INSTDONE_TDL_GFX},
+ {"SS_LSC_HDC_IDLE_TDL_GFX", SS_LSC_HDC_IDLE_TDL_GFX},
+ {"SLICE_ARB_STATUS", SLICE_ARB_STATUS}
};
static void __fill_ext_reg(struct __guc_mmio_reg_descr *ext,
--
2.43.0
^ permalink raw reply related [flat|nested] 23+ messages in thread
* [PATCH v5 0/7] drm/xe: Capture additional HW register state in devcoredump
@ 2026-10-23 6:05 Nareshkumar Gollakoti
2026-10-23 6:05 ` [PATCH v5 1/7] drm/xe/devcoredump: Capture GT fuse registers " Nareshkumar Gollakoti
` (10 more replies)
0 siblings, 11 replies; 23+ messages in thread
From: Nareshkumar Gollakoti @ 2026-10-23 6:05 UTC (permalink / raw)
To: intel-xe; +Cc: tejas.upadhyay, Nareshkumar Gollakoti
This series extends the Xe devcoredump with additional hardware register
state to improve post-mortem debugging of GPU hangs and faults on Xe3p.
Today the devcoredump captures GuC log/CT, engine and submission state.
When triaging hangs it is often necessary to also know the static HW
configuration (fuses), GuC status/error state, GAM page-fault reporting
and L3 node status at the time of the hang. Collecting these at capture
time makes the dump self-contained and avoids relying on separate
probe-time logging.
To do this, the series adds a small generic MMIO register-dump helper
(descriptor list -> snapshot -> print/free) and uses it for several
register groups. Each group is captured for both the primary GT and,
where applicable, the media GT.
Registers requiring MCR steering are read through
xe_gt_mcr_unicast_read_any(); the remaining GAM registers use INSTANCE0
default steering and are read directly.
Snapshots are allocated with GFP_ATOMIC as capture runs inside the
dma_fence signalling section, matching the surrounding captures, and are
freed in the existing devcoredump teardown path.
Patches:
1 Add the generic reg-dump helpers and capture GT/media fuse registers.
2 Capture GT and media GuC status/error registers.
3 Print register offsets alongside names in the GuC engine capture
output (32- and 64-bit), easing cross-reference with the bspec.
4 Capture the GAM page-fault report head/tail registers.
5 Add the TDL gfx registers to the XeHPG extended GuC capture list.
6 Capture L3 node status registers (MCR, read via unicast_read_any()).
7 Capture additional engine state registers
Sample devcoredump output gains the following sections:
**** GT Fuse Register Dump ****
**** Media GT Fuse Register Dump ****
**** GT GuC Register Dump ****
**** Media GT GuC Register Dump ****
**** GAM PF Report ****
**** Node Status ****
**** Additional engine state registers ****
v3:(Sashiko)
- Use the LOW_DW MMIO offset when printing combined 64-bit register values
in capture snapshots
- Preserve the existing coredump register-name format and append register
address as trailing metadata
- Replace the render is not awake message with raw POWERGATE_ENABLE
bit-state output
- Move engine-class-specific registers out of COMMON_BASE_ENGINE_INSTANCE
into class-specific capture lists
v4:
- optimized APIs and reduced few structs(Tejas)
- Fixed CI hook error
v5:
- Fixed Null derefence possibilities and ensured proper forcewake scope
- refactor struct member documentation(Tejas)
Nareshkumar Gollakoti (7):
drm/xe/devcoredump: Capture GT fuse registers in devcoredump
drm/xe/devcoredump: Add GuC register snapshot to devcoredump
drm/xe/guc: Print register addresses in capture snapshot output
drm/xe: dump GAM page fault report registers in devcoredump
drm/xe/guc: add TDL,SLICE gfx registers to capture list
drm/xe: capture L3 node status registers in devcoredump
drm/xe/guc: capture additional engine state registers
drivers/gpu/drm/xe/regs/xe_engine_regs.h | 22 ++
drivers/gpu/drm/xe/regs/xe_gt_regs.h | 13 +
drivers/gpu/drm/xe/regs/xe_guc_regs.h | 5 +
drivers/gpu/drm/xe/xe_devcoredump.c | 328 +++++++++++++++++++++-
drivers/gpu/drm/xe/xe_devcoredump_types.h | 66 +++++
drivers/gpu/drm/xe/xe_guc_capture.c | 78 ++++-
6 files changed, 503 insertions(+), 9 deletions(-)
--
2.43.0
^ permalink raw reply [flat|nested] 23+ messages in thread
* [PATCH v5 1/7] drm/xe/devcoredump: Capture GT fuse registers in devcoredump
2026-10-23 6:05 [PATCH v5 0/7] drm/xe: Capture additional HW register state in devcoredump Nareshkumar Gollakoti
@ 2026-10-23 6:05 ` Nareshkumar Gollakoti
2026-10-23 13:27 ` Upadhyay, Tejas
2026-10-23 6:05 ` [PATCH v5 2/7] drm/xe/devcoredump: Add GuC register snapshot to devcoredump Nareshkumar Gollakoti
` (9 subsequent siblings)
10 siblings, 1 reply; 23+ messages in thread
From: Nareshkumar Gollakoti @ 2026-10-23 6:05 UTC (permalink / raw)
To: intel-xe; +Cc: tejas.upadhyay, Nareshkumar Gollakoti
Capture fuse-related GT register state in the Xe devcoredump to preserve
additional hardware configuration information for postmortem debugging.
Add generic register snapshot storage and helpers for capturing,
printing, and freeing MMIO register dumps. Use them to record both
primary GT and media GT fuse register state during devcoredump snapshot
collection and print the captured values in the coredump output.
Also add the required GT register definitions for RPM and mirror
copy-enable state used by the new dump paths.
v2:(Sashiko)
- Fix GT/media fuse snapshot capture to use the correct GT context.
- Add non-fault GT force wake for cross-GT register capture.
- Skip reading registers when SR-IOV VF.
- Skip media GT capture when media GT is absent.
- Add RPM snapshot print/free handling explicitly.
- Add POWERGATE_ENABLE register to get render awake status
v3:(Sashiko)
- Check RENDER_POWERGATE_ENABLE of POWERGATE_ENABLE register
- Replace "render is not awake" message with "render powergating
appears not enabled"
v4:
- Reduce multiple apis and optimize the suggest way of struct arrays(Tejas)
- Add document for struct xe_gt_regset gt member(Hook failure)
- Change struct reg_desc to header file
- Remove Graphics version check for these registers set
v5:
- Fix possible Null dereference using valid gt instead of q->gt(sashiko)
- refactor struct member commenting(Tejas)
- Avoid using xe3p naming as the regs are for all platforms
Signed-off-by: Nareshkumar Gollakoti <naresh.kumar.g@intel.com>
---
drivers/gpu/drm/xe/regs/xe_gt_regs.h | 2 +
drivers/gpu/drm/xe/xe_devcoredump.c | 228 +++++++++++++++++++++-
drivers/gpu/drm/xe/xe_devcoredump_types.h | 52 +++++
3 files changed, 281 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/xe/regs/xe_gt_regs.h b/drivers/gpu/drm/xe/regs/xe_gt_regs.h
index f5cd3a94e47f..e93895e0c731 100644
--- a/drivers/gpu/drm/xe/regs/xe_gt_regs.h
+++ b/drivers/gpu/drm/xe/regs/xe_gt_regs.h
@@ -22,6 +22,8 @@
#define MTL_CC_MASK REG_GENMASK(12, 9)
#define MTL_CRST 0xf
+#define RPM_GCD XE_REG(0xc98)
+
/* RPM unit config (Gen8+) */
#define RPM_CONFIG0 XE_REG(0xd00)
#define RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_MASK REG_GENMASK(5, 3)
diff --git a/drivers/gpu/drm/xe/xe_devcoredump.c b/drivers/gpu/drm/xe/xe_devcoredump.c
index 133cbe196d66..f59f93ba5949 100644
--- a/drivers/gpu/drm/xe/xe_devcoredump.c
+++ b/drivers/gpu/drm/xe/xe_devcoredump.c
@@ -25,6 +25,8 @@
#include "xe_pm.h"
#include "xe_sched_job.h"
#include "xe_vm.h"
+#include "xe_mmio.h"
+#include "regs/xe_gt_regs.h"
/**
* DOC: Xe device coredump
@@ -69,6 +71,179 @@
/* 1 hour timeout */
#define XE_COREDUMP_TIMEOUT_JIFFIES (60 * 60 * HZ)
+#define XE_REG_DESC(_reg, _name) { .reg = (_reg), .name = (_name) }
+
+static const struct xe_reg_desc xe_dbg_gt_fuse_reglist[] = {
+ XE_REG_DESC(XELP_GT_GEOMETRY_DSS_ENABLE, "GT_GEOMETRY_DSS_ENABLE"),
+ XE_REG_DESC(XEHP_GT_COMPUTE_DSS_ENABLE, "GT_COMPUTE_DSS_ENABLE"),
+ XE_REG_DESC(XELP_EU_ENABLE, "EU_ENABLE"),
+ XE_REG_DESC(MIRROR_FUSE1, "MIRROR_FUSE1"),
+ XE_REG_DESC(GT_VEBOX_VDBOX_DISABLE, "GT_VEBOX_VDBOX_DISABLE"),
+ XE_REG_DESC(SERVICE_COPY_ENABLE, "SERVICE_COPY_ENABLE"),
+ XE_REG_DESC(RESOURCE_COPY_ENABLE, "COPY_ENABLE_GTFS_GCD"),
+ XE_REG_DESC(XE2_GT_GEOMETRY_DSS_1, "GT_GEOMETRY_DSS_1"),
+ XE_REG_DESC(XE2_GT_GEOMETRY_DSS_2, "GT_GEOMETRY_DSS_2"),
+ XE_REG_DESC(XE2_GT_COMPUTE_DSS_2, "GT_COMPUTE_DSS_2"),
+ XE_REG_DESC(XEHPC_GT_COMPUTE_DSS_ENABLE_EXT, "GT_COMPUTE_DSS_ENABLE_EXT"),
+ XE_REG_DESC(XE3P_XPC_GT_GEOMETRY_DSS_3, "GT_GEOMETRY_DSS_3"),
+ XE_REG_DESC(XE3P_XPC_GT_COMPUTE_DSS_3, "GT_COMPUTE_DSS_3"),
+};
+
+static const struct xe_reg_desc xe_dbg_media_gt_fuse_reglist[] = {
+ XE_REG_DESC(SERVICE_COPY_ENABLE, "SERVICE_COPY_ENABLE"),
+ XE_REG_DESC(RESOURCE_COPY_ENABLE, "COPY_ENABLE_GTFS_GCD"),
+};
+
+static const struct xe_reg_desc xe_dbg_gt_rpm_reglist[] = {
+ XE_REG_DESC(RPM_GCD, "RPM_GCD"),
+ XE_REG_DESC(POWERGATE_ENABLE, "POWERGATE_ENABLE"),
+};
+
+static const struct xe_reg_desc xe_dbg_media_gt_rpm_reglist[] = {
+ XE_REG_DESC(RPM_GCD, "RPM_GCD"),
+};
+
+/**
+ * struct xe_gt_regset - Struct for register descriptor list for GT
+ *
+ * This struct is used to reference the corresponding reglist of
+ * Main GT and media GT
+ */
+struct xe_gt_regset {
+ /**
+ * @gt: GT array indexed by enum xe_gt_type starting at 1
+ * (UNINITIALIZED=0, MAIN=1, MEDIA=2)
+ */
+ struct xe_reg_desc_list gt[XE_MAX_GT_PER_TILE + 1];
+};
+
+/**
+ * enum xe_dbg_regset_type - debug register set types
+ * @XE_DBG_REGSET_FUSE: Fuse register set
+ * @XE_DBG_REGSET_RPM: RPM register set
+ * @XE_DBG_REGSET_MAX: Number of debug register set types
+ */
+enum xe_dbg_regset_type {
+ XE_DBG_REGSET_FUSE,
+ XE_DBG_REGSET_RPM,
+ XE_DBG_REGSET_MAX,
+};
+
+static const struct xe_gt_regset xe_dbg_regsets[XE_DBG_REGSET_MAX] = {
+ [XE_DBG_REGSET_FUSE] = {
+ .gt[XE_GT_TYPE_MAIN] = { xe_dbg_gt_fuse_reglist,
+ ARRAY_SIZE(xe_dbg_gt_fuse_reglist) },
+ .gt[XE_GT_TYPE_MEDIA] = { xe_dbg_media_gt_fuse_reglist,
+ ARRAY_SIZE(xe_dbg_media_gt_fuse_reglist) },
+ },
+ [XE_DBG_REGSET_RPM] = {
+ .gt[XE_GT_TYPE_MAIN] = { xe_dbg_gt_rpm_reglist,
+ ARRAY_SIZE(xe_dbg_gt_rpm_reglist) },
+ .gt[XE_GT_TYPE_MEDIA] = { xe_dbg_media_gt_rpm_reglist,
+ ARRAY_SIZE(xe_dbg_media_gt_rpm_reglist) },
+ },
+};
+
+static void xe_dbg_reg_snapshot_print(struct drm_printer *p,
+ const char *title,
+ const struct xe_dbg_reg_snapshot *snap)
+{
+ u32 i;
+
+ if (!snap)
+ return;
+
+ if (title)
+ drm_printf(p, "\n**** %s ****\n", title);
+
+ for (i = 0; i < snap->num_regs; i++)
+ drm_printf(p, " %s [0x%x] = 0x%08x\n",
+ snap->desc->regs[i].name,
+ snap->desc->regs[i].reg.addr,
+ snap->values[i]);
+}
+
+static void xe_dbg_reg_snapshot_free(struct xe_dbg_reg_snapshot *snap)
+{
+ kfree(snap);
+}
+
+static const u32 *xe_dbg_find_value(const struct xe_dbg_reg_snapshot *snap,
+ struct xe_reg reg)
+{
+ int i;
+
+ if (!snap)
+ return NULL;
+
+ for (i = 0; i < snap->num_regs; i++)
+ if (snap->desc->regs[i].reg.addr == reg.addr)
+ return &snap->values[i];
+
+ return NULL;
+}
+
+static void xe_gt_rpm_snapshot_print(struct drm_printer *p,
+ const char *title,
+ const struct xe_dbg_reg_snapshot *snap)
+{
+ const u32 *val;
+
+ xe_dbg_reg_snapshot_print(p, title, snap);
+
+ if (!snap)
+ return;
+
+ val = xe_dbg_find_value(snap, POWERGATE_ENABLE);
+ if (val && !(*val & RENDER_POWERGATE_ENABLE))
+ drm_puts(p, "render powergating appears not enabled\n");
+}
+
+static struct xe_dbg_reg_snapshot *
+xe_dbg_reg_snapshot_capture_target(struct xe_gt *gt,
+ const struct xe_reg_desc_list *reglist)
+{
+ struct xe_dbg_reg_snapshot *snap;
+ int i;
+
+ if (IS_SRIOV_VF(gt_to_xe(gt)))
+ return NULL;
+
+ snap = kmalloc(struct_size(snap, values, reglist->num_regs), GFP_ATOMIC);
+ if (!snap)
+ return NULL;
+
+ snap->desc = reglist;
+ snap->num_regs = reglist->num_regs;
+ for (i = 0; i < reglist->num_regs; i++)
+ snap->values[i] = xe_mmio_read32(>->mmio, reglist->regs[i].reg);
+
+ return snap;
+}
+
+static struct xe_dbg_reg_snapshot *
+xe_dbg_gt_snapshot_capture(struct xe_gt *fault_gt, struct xe_gt *other_gt,
+ enum xe_dbg_regset_type type,
+ enum xe_gt_type gt_type)
+{
+ struct xe_gt *target_gt;
+
+ if (!fault_gt || !fault_gt->tile)
+ return NULL;
+
+ target_gt = gt_type == XE_GT_TYPE_MEDIA ? fault_gt->tile->media_gt
+ : fault_gt->tile->primary_gt;
+ if (!target_gt)
+ return NULL;
+
+ /* non-fault GT needs the caller's confirmed forcewake */
+ if (target_gt != fault_gt && target_gt != other_gt)
+ return NULL;
+
+ return xe_dbg_reg_snapshot_capture_target(target_gt,
+ &xe_dbg_regsets[type].gt[gt_type]);
+}
+
static struct xe_device *coredump_to_xe(const struct xe_devcoredump *coredump)
{
return container_of(coredump, struct xe_device, devcoredump);
@@ -109,6 +284,11 @@ static ssize_t __xe_devcoredump_read(char *buffer, ssize_t count,
drm_printf(&p, "\n**** GT #%d ****\n", ss->gt->info.id);
drm_printf(&p, "\tTile: %d\n", ss->gt->tile->id);
+ xe_dbg_reg_snapshot_print(&p, "GT Fuse Register Dump", ss->gt_fuse);
+ xe_dbg_reg_snapshot_print(&p, "Media GT Fuse Register Dump", ss->media_fuse);
+ xe_gt_rpm_snapshot_print(&p, "GT RPM Register Dump", ss->gt_rpm);
+ xe_dbg_reg_snapshot_print(&p, "Media GT RPM Register Dump", ss->media_gt_rpm);
+
drm_puts(&p, "\n**** GuC Log ****\n");
xe_guc_log_snapshot_print(ss->guc.log, &p, ss->gt);
drm_puts(&p, "\n**** GuC CT ****\n");
@@ -146,6 +326,18 @@ static void xe_devcoredump_snapshot_free(struct xe_devcoredump_snapshot *ss)
xe_guc_ct_snapshot_free(ss->guc.ct);
ss->guc.ct = NULL;
+ xe_dbg_reg_snapshot_free(ss->gt_fuse);
+ ss->gt_fuse = NULL;
+
+ xe_dbg_reg_snapshot_free(ss->media_fuse);
+ ss->media_fuse = NULL;
+
+ xe_dbg_reg_snapshot_free(ss->gt_rpm);
+ ss->gt_rpm = NULL;
+
+ xe_dbg_reg_snapshot_free(ss->media_gt_rpm);
+ ss->media_gt_rpm = NULL;
+
if (!IS_ERR_OR_NULL(ss->gt))
xe_guc_capture_put_matched_nodes(&ss->gt->uc.guc);
ss->matched_node = NULL;
@@ -319,6 +511,27 @@ static void xe_devcoredump_deferred_snap_work(struct work_struct *work)
}
}
+static void xe_devcoredump_capture_gt_regs(struct xe_devcoredump_snapshot *ss,
+ struct xe_gt *gt, struct xe_gt *other_gt)
+{
+ ss->gt_fuse = xe_dbg_gt_snapshot_capture(gt,
+ other_gt,
+ XE_DBG_REGSET_FUSE,
+ XE_GT_TYPE_MAIN);
+ ss->media_fuse = xe_dbg_gt_snapshot_capture(gt,
+ other_gt,
+ XE_DBG_REGSET_FUSE,
+ XE_GT_TYPE_MEDIA);
+ ss->gt_rpm = xe_dbg_gt_snapshot_capture(gt,
+ other_gt,
+ XE_DBG_REGSET_RPM,
+ XE_GT_TYPE_MAIN);
+ ss->media_gt_rpm = xe_dbg_gt_snapshot_capture(gt,
+ other_gt,
+ XE_DBG_REGSET_RPM,
+ XE_GT_TYPE_MEDIA);
+}
+
static void devcoredump_snapshot(struct xe_devcoredump *coredump,
struct xe_gt *gt,
struct xe_exec_queue *q,
@@ -328,6 +541,7 @@ static void devcoredump_snapshot(struct xe_devcoredump *coredump,
struct xe_guc *guc = >->uc.guc;
const char *process_name = "no process";
bool cookie;
+ struct xe_gt *other_gt;
ss->snapshot_time = ktime_get_real();
ss->boot_time = ktime_get_boottime();
@@ -342,11 +556,23 @@ static void devcoredump_snapshot(struct xe_devcoredump *coredump,
ss->gt = gt;
INIT_WORK(&ss->work, xe_devcoredump_deferred_snap_work);
- /* keep going if fw fails as we still want to save the memory and SW data */
+ /* fw_ref_other must stay in scope through the register captures below */
CLASS(xe_force_wake, fw_ref)(gt_to_fw(gt), XE_FORCEWAKE_ALL);
cookie = dma_fence_begin_signalling();
+ other_gt = gt->tile->media_gt == gt ? gt->tile->primary_gt
+ : gt->tile->media_gt;
+ if (other_gt) {
+ CLASS(xe_force_wake, fw_ref_other)(gt_to_fw(other_gt),
+ XE_FORCEWAKE_ALL);
+ if (!xe_force_wake_ref_has_domain(fw_ref_other.domains, XE_FORCEWAKE_ALL))
+ other_gt = NULL;
+ xe_devcoredump_capture_gt_regs(ss, gt, other_gt);
+ } else {
+ xe_devcoredump_capture_gt_regs(ss, gt, NULL);
+ }
+
ss->guc.log = xe_guc_log_snapshot_capture(&guc->log, true);
ss->guc.ct = xe_guc_ct_snapshot_capture(&guc->ct);
diff --git a/drivers/gpu/drm/xe/xe_devcoredump_types.h b/drivers/gpu/drm/xe/xe_devcoredump_types.h
index a174385a6d83..e2fac33dce09 100644
--- a/drivers/gpu/drm/xe/xe_devcoredump_types.h
+++ b/drivers/gpu/drm/xe/xe_devcoredump_types.h
@@ -14,6 +14,48 @@
struct xe_device;
struct xe_gt;
+/**
+ * struct xe_reg_desc - Register descriptor struct to make reg list
+ *
+ * This struct is used as descriptor containing reg address and name
+ * of the register to dump its value during coredump for debug purpose.
+ */
+struct xe_reg_desc {
+ /** @reg: The register */
+ struct xe_reg reg;
+ /** @name: Name of the register */
+ const char *name;
+};
+
+/**
+ * struct xe_reg_desc_list - Struct for register descriptor list
+ *
+ * This struct is used to reference the corresponding reglist of
+ * various component
+ */
+struct xe_reg_desc_list {
+ /** @regs: Pointer to an array of register descriptors. */
+ const struct xe_reg_desc *regs;
+ /** @num_regs: number of registers in the descriptor list*/
+ u32 num_regs;
+};
+
+/**
+ * struct xe_dbg_reg_snapshot - Register snapshot
+ *
+ * This struct contains the register values captured at the time of the crash.
+ * It is used to store the register values in a human-readable format for
+ * debugging purposes.
+ */
+struct xe_dbg_reg_snapshot {
+ /** @desc: register descriptor list. */
+ const struct xe_reg_desc_list *desc;
+ /** @num_regs: Number of registers needed for capture. */
+ u32 num_regs;
+ /** @values: register values*/
+ u32 values[];
+};
+
/**
* struct xe_devcoredump_snapshot - Crash snapshot
*
@@ -35,6 +77,16 @@ struct xe_devcoredump_snapshot {
/** @gt: Affected GT, used by forcewake for delayed capture */
struct xe_gt *gt;
+
+ /** @gt_fuse: Fuse snapshot */
+ struct xe_dbg_reg_snapshot *gt_fuse;
+ /** @media_fuse: Media Fuse snapshot */
+ struct xe_dbg_reg_snapshot *media_fuse;
+ /** @gt_rpm: GT RPM snapshot */
+ struct xe_dbg_reg_snapshot *gt_rpm;
+ /** @media_gt_rpm: Media GT RPM snapshot */
+ struct xe_dbg_reg_snapshot *media_gt_rpm;
+
/** @work: Workqueue for deferred capture outside of signaling context */
struct work_struct work;
--
2.43.0
^ permalink raw reply related [flat|nested] 23+ messages in thread
* [PATCH v5 2/7] drm/xe/devcoredump: Add GuC register snapshot to devcoredump
2026-10-23 6:05 [PATCH v5 0/7] drm/xe: Capture additional HW register state in devcoredump Nareshkumar Gollakoti
2026-10-23 6:05 ` [PATCH v5 1/7] drm/xe/devcoredump: Capture GT fuse registers " Nareshkumar Gollakoti
@ 2026-10-23 6:05 ` Nareshkumar Gollakoti
2026-10-26 6:35 ` Upadhyay, Tejas
2026-10-23 6:05 ` [PATCH v5 3/7] drm/xe/guc: Print register addresses in capture snapshot output Nareshkumar Gollakoti
` (8 subsequent siblings)
10 siblings, 1 reply; 23+ messages in thread
From: Nareshkumar Gollakoti @ 2026-10-23 6:05 UTC (permalink / raw)
To: intel-xe; +Cc: tejas.upadhyay, Nareshkumar Gollakoti
Add support for capturing GuC register state as part of the xe
devcoredump snapshot.
Define a dedicated GuC register snapshot structure, record selected
GT and media GuC status/error registers during devcoredump capture,
and free the snapshot during teardown.
Keeping these register values in the devcoredump helps with
post-mortem analysis of GuC-related failures.
v2:(Sashiko)
- Reuse the generic target GT snapshot helper for GuC register capture
- Capture primary and media GuC registers using correct GT MMIO context
- Avoid reading the same on SR-IOV VF
- skip reading media GT GuC registers when media is not present
- drop hardcoded media register address macros
v5:
- Rebase as per patch1 changes
Signed-off-by: Nareshkumar Gollakoti <naresh.kumar.g@intel.com>
---
drivers/gpu/drm/xe/regs/xe_guc_regs.h | 5 ++++
drivers/gpu/drm/xe/xe_devcoredump.c | 35 +++++++++++++++++++++++
drivers/gpu/drm/xe/xe_devcoredump_types.h | 5 ++++
3 files changed, 45 insertions(+)
diff --git a/drivers/gpu/drm/xe/regs/xe_guc_regs.h b/drivers/gpu/drm/xe/regs/xe_guc_regs.h
index 5faac8316b66..c13ee6e21e37 100644
--- a/drivers/gpu/drm/xe/regs/xe_guc_regs.h
+++ b/drivers/gpu/drm/xe/regs/xe_guc_regs.h
@@ -150,6 +150,11 @@
#define GUC_INTR_SW_INT_1 REG_BIT(1)
#define GUC_INTR_SW_INT_0 REG_BIT(0)
+#define GUC_DEVICEID XE_REG(0xc008)
+#define GUC_SHIM_ERR_TRAP XE_REG(0xc070)
+#define GUC_HW_FATL_ERR XE_REG(0xc598)
+#define GUC_HW_NOTIFY_ERR XE_REG(0xc59c)
+
#define GUC_NUM_DOORBELLS 256
/* format of the HW-monitored doorbell cacheline */
diff --git a/drivers/gpu/drm/xe/xe_devcoredump.c b/drivers/gpu/drm/xe/xe_devcoredump.c
index f59f93ba5949..49a7c020a161 100644
--- a/drivers/gpu/drm/xe/xe_devcoredump.c
+++ b/drivers/gpu/drm/xe/xe_devcoredump.c
@@ -27,6 +27,7 @@
#include "xe_vm.h"
#include "xe_mmio.h"
#include "regs/xe_gt_regs.h"
+#include "regs/xe_guc_regs.h"
/**
* DOC: Xe device coredump
@@ -73,6 +74,16 @@
#define XE_REG_DESC(_reg, _name) { .reg = (_reg), .name = (_name) }
+static const struct xe_reg_desc xe_dbg_gt_guc_reglist[] = {
+ XE_REG_DESC(GUC_STATUS, "GUC_STATUS"),
+ XE_REG_DESC(GUC_WOPCM_SIZE, "GUC_WOPCM_SIZE"),
+ XE_REG_DESC(GUC_DEVICEID, "GUC_DEVICEID"),
+ XE_REG_DESC(DMA_CTRL, "DMA_CTRL"),
+ XE_REG_DESC(GUC_HW_FATL_ERR, "GUC_HW_FATL_ERR"),
+ XE_REG_DESC(GUC_HW_NOTIFY_ERR, "GUC_HW_NOTIFY_ERR"),
+ XE_REG_DESC(GUC_SHIM_ERR_TRAP, "GUC_SHIM_ERR_TRAP"),
+};
+
static const struct xe_reg_desc xe_dbg_gt_fuse_reglist[] = {
XE_REG_DESC(XELP_GT_GEOMETRY_DSS_ENABLE, "GT_GEOMETRY_DSS_ENABLE"),
XE_REG_DESC(XEHP_GT_COMPUTE_DSS_ENABLE, "GT_COMPUTE_DSS_ENABLE"),
@@ -121,11 +132,13 @@ struct xe_gt_regset {
* enum xe_dbg_regset_type - debug register set types
* @XE_DBG_REGSET_FUSE: Fuse register set
* @XE_DBG_REGSET_RPM: RPM register set
+ * @XE_DBG_REGSET_GUC: GUC register set
* @XE_DBG_REGSET_MAX: Number of debug register set types
*/
enum xe_dbg_regset_type {
XE_DBG_REGSET_FUSE,
XE_DBG_REGSET_RPM,
+ XE_DBG_REGSET_GUC,
XE_DBG_REGSET_MAX,
};
@@ -142,6 +155,12 @@ static const struct xe_gt_regset xe_dbg_regsets[XE_DBG_REGSET_MAX] = {
.gt[XE_GT_TYPE_MEDIA] = { xe_dbg_media_gt_rpm_reglist,
ARRAY_SIZE(xe_dbg_media_gt_rpm_reglist) },
},
+ [XE_DBG_REGSET_GUC] = {
+ .gt[XE_GT_TYPE_MAIN] = { xe_dbg_gt_guc_reglist,
+ ARRAY_SIZE(xe_dbg_gt_guc_reglist) },
+ .gt[XE_GT_TYPE_MEDIA] = { xe_dbg_gt_guc_reglist,
+ ARRAY_SIZE(xe_dbg_gt_guc_reglist) },
+ },
};
static void xe_dbg_reg_snapshot_print(struct drm_printer *p,
@@ -288,6 +307,8 @@ static ssize_t __xe_devcoredump_read(char *buffer, ssize_t count,
xe_dbg_reg_snapshot_print(&p, "Media GT Fuse Register Dump", ss->media_fuse);
xe_gt_rpm_snapshot_print(&p, "GT RPM Register Dump", ss->gt_rpm);
xe_dbg_reg_snapshot_print(&p, "Media GT RPM Register Dump", ss->media_gt_rpm);
+ xe_dbg_reg_snapshot_print(&p, "GT GuC Register Dump", ss->gt_guc_reg);
+ xe_dbg_reg_snapshot_print(&p, "Media GT GuC Register Dump", ss->media_gt_guc_reg);
drm_puts(&p, "\n**** GuC Log ****\n");
xe_guc_log_snapshot_print(ss->guc.log, &p, ss->gt);
@@ -338,6 +359,12 @@ static void xe_devcoredump_snapshot_free(struct xe_devcoredump_snapshot *ss)
xe_dbg_reg_snapshot_free(ss->media_gt_rpm);
ss->media_gt_rpm = NULL;
+ xe_dbg_reg_snapshot_free(ss->gt_guc_reg);
+ ss->gt_guc_reg = NULL;
+
+ xe_dbg_reg_snapshot_free(ss->media_gt_guc_reg);
+ ss->media_gt_guc_reg = NULL;
+
if (!IS_ERR_OR_NULL(ss->gt))
xe_guc_capture_put_matched_nodes(&ss->gt->uc.guc);
ss->matched_node = NULL;
@@ -530,6 +557,14 @@ static void xe_devcoredump_capture_gt_regs(struct xe_devcoredump_snapshot *ss,
other_gt,
XE_DBG_REGSET_RPM,
XE_GT_TYPE_MEDIA);
+ ss->gt_guc_reg = xe_dbg_gt_snapshot_capture(gt,
+ other_gt,
+ XE_DBG_REGSET_GUC,
+ XE_GT_TYPE_MAIN);
+ ss->media_gt_guc_reg = xe_dbg_gt_snapshot_capture(gt,
+ other_gt,
+ XE_DBG_REGSET_GUC,
+ XE_GT_TYPE_MEDIA);
}
static void devcoredump_snapshot(struct xe_devcoredump *coredump,
diff --git a/drivers/gpu/drm/xe/xe_devcoredump_types.h b/drivers/gpu/drm/xe/xe_devcoredump_types.h
index e2fac33dce09..52db64640f89 100644
--- a/drivers/gpu/drm/xe/xe_devcoredump_types.h
+++ b/drivers/gpu/drm/xe/xe_devcoredump_types.h
@@ -87,6 +87,11 @@ struct xe_devcoredump_snapshot {
/** @media_gt_rpm: Media GT RPM snapshot */
struct xe_dbg_reg_snapshot *media_gt_rpm;
+ /** @gt_guc_reg: gt guc reg snapshot */
+ struct xe_dbg_reg_snapshot *gt_guc_reg;
+ /** @media_gt_guc_reg: media gt guc reg snapshot */
+ struct xe_dbg_reg_snapshot *media_gt_guc_reg;
+
/** @work: Workqueue for deferred capture outside of signaling context */
struct work_struct work;
--
2.43.0
^ permalink raw reply related [flat|nested] 23+ messages in thread
* [PATCH v5 3/7] drm/xe/guc: Print register addresses in capture snapshot output
2026-10-23 6:05 [PATCH v5 0/7] drm/xe: Capture additional HW register state in devcoredump Nareshkumar Gollakoti
2026-10-23 6:05 ` [PATCH v5 1/7] drm/xe/devcoredump: Capture GT fuse registers " Nareshkumar Gollakoti
2026-10-23 6:05 ` [PATCH v5 2/7] drm/xe/devcoredump: Add GuC register snapshot to devcoredump Nareshkumar Gollakoti
@ 2026-10-23 6:05 ` Nareshkumar Gollakoti
2026-10-23 13:14 ` Upadhyay, Tejas
2026-10-26 6:37 ` Upadhyay, Tejas
2026-10-23 6:05 ` [PATCH v5 4/7] drm/xe: dump GAM page fault report registers in devcoredump Nareshkumar Gollakoti
` (7 subsequent siblings)
10 siblings, 2 replies; 23+ messages in thread
From: Nareshkumar Gollakoti @ 2026-10-23 6:05 UTC (permalink / raw)
To: intel-xe; +Cc: tejas.upadhyay, Nareshkumar Gollakoti
Include register offsets in GuC capture snapshot print output for both
32-bit and 64-bit registers.
When dumping captured engine register state, print each register name
alongside its MMIO offset to make the snapshot output easier to
cross-reference with register definitions and hardware debug
documentation.
This improves postmortem analysis without changing capture contents.
v2:(Sashiko)
- Ensure lower DWORD prints
v3:(Sashiko)
- Use the LOW_DW MMIO offset(capture in last_address) when combined 64bit
register values in the dump instead of HI_SW offset
- preserve existing coredump register-name format and append register
address as trailing metadata as a debug info and avoids disrupting
existing format
Signed-off-by: Nareshkumar Gollakoti <naresh.kumar.g@intel.com>
---
drivers/gpu/drm/xe/xe_guc_capture.c | 18 ++++++++++++++----
1 file changed, 14 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/xe/xe_guc_capture.c b/drivers/gpu/drm/xe/xe_guc_capture.c
index 5a4d085660a2..3e99aef53b46 100644
--- a/drivers/gpu/drm/xe/xe_guc_capture.c
+++ b/drivers/gpu/drm/xe/xe_guc_capture.c
@@ -1716,6 +1716,7 @@ snapshot_print_by_list_order(struct xe_hw_engine_snapshot *snapshot, struct drm_
struct xe_devcoredump_snapshot *devcore_snapshot = &devcoredump->snapshot;
struct gcap_reg_list_info *reginfo = NULL;
u32 i, last_value = 0;
+ u32 last_address = 0;
bool low32_ready = false;
if (!list || !list->list || list->num_regs == 0)
@@ -1743,6 +1744,7 @@ snapshot_print_by_list_order(struct xe_hw_engine_snapshot *snapshot, struct drm_
switch (reg_desc->data_type) {
case REG_64BIT_LOW_DW:
last_value = value;
+ last_address = reg_desc->reg.addr;
/*
* A 64 bit register define requires 2 consecutive
@@ -1774,7 +1776,11 @@ snapshot_print_by_list_order(struct xe_hw_engine_snapshot *snapshot, struct drm_
XE_WARN_ON(!low32_ready);
low32_ready = false;
- drm_printf(p, "\t%s: 0x%016llx\n", reg_desc->regname, value_qw);
+ drm_printf(p, "\t%s: 0x%016llx [addr=0x%x]\n",
+ reg_desc->regname,
+ value_qw,
+ last_address);
+
break;
}
@@ -1788,10 +1794,14 @@ snapshot_print_by_list_order(struct xe_hw_engine_snapshot *snapshot, struct drm_
XE_WARN_ON(low32_ready);
if (FIELD_GET(GUC_REGSET_STEERING_NEEDED, reg_desc->flags))
- drm_printf(p, "\t%s[%u]: 0x%08x\n", reg_desc->regname,
- reg_desc->dss_id, value);
+ drm_printf(p, "\t%s[%u]: 0x%08x [addr=0x%x]\n",
+ reg_desc->regname,
+ reg_desc->dss_id, value, reg_desc->reg.addr);
+
else
- drm_printf(p, "\t%s: 0x%08x\n", reg_desc->regname, value);
+ drm_printf(p, "\t%s: 0x%08x [addr=0x%x]\n",
+ reg_desc->regname, value, reg_desc->reg.addr);
+
break;
}
--
2.43.0
^ permalink raw reply related [flat|nested] 23+ messages in thread
* [PATCH v5 4/7] drm/xe: dump GAM page fault report registers in devcoredump
2026-10-23 6:05 [PATCH v5 0/7] drm/xe: Capture additional HW register state in devcoredump Nareshkumar Gollakoti
` (2 preceding siblings ...)
2026-10-23 6:05 ` [PATCH v5 3/7] drm/xe/guc: Print register addresses in capture snapshot output Nareshkumar Gollakoti
@ 2026-10-23 6:05 ` Nareshkumar Gollakoti
2026-10-23 6:31 ` sashiko-bot
2026-10-26 6:48 ` Upadhyay, Tejas
2026-10-23 6:05 ` [PATCH v5 5/7] drm/xe/guc: add TDL, SLICE gfx registers to capture list Nareshkumar Gollakoti
` (6 subsequent siblings)
10 siblings, 2 replies; 23+ messages in thread
From: Nareshkumar Gollakoti @ 2026-10-23 6:05 UTC (permalink / raw)
To: intel-xe; +Cc: tejas.upadhyay, Nareshkumar Gollakoti
Add PAGE_FLTRPTQ_HEAD_GAMCTRL and PAGE_FLTRPTQ_TAIL_GAMCTRL to the Xe
register definitions and capture them as part of the devcoredump
snapshot.
Include the register dump in the devcoredump output and release the
snapshot during cleanup so page fault report state is available for
post-mortem debugging.
v2:
- As design change made for previous patches. refactored this patch
as well to accommodate those changes.
- Add PF occurred print when the two register values are not equal
v4:
Refactored as per the patch1 change(Tejas)
v5:
Refactored as per patch1 changes
Signed-off-by: Nareshkumar Gollakoti <naresh.kumar.g@intel.com>
---
drivers/gpu/drm/xe/regs/xe_gt_regs.h | 3 ++
drivers/gpu/drm/xe/xe_devcoredump.c | 37 +++++++++++++++++++++++
drivers/gpu/drm/xe/xe_devcoredump_types.h | 3 ++
3 files changed, 43 insertions(+)
diff --git a/drivers/gpu/drm/xe/regs/xe_gt_regs.h b/drivers/gpu/drm/xe/regs/xe_gt_regs.h
index e93895e0c731..e9eb0bd04af1 100644
--- a/drivers/gpu/drm/xe/regs/xe_gt_regs.h
+++ b/drivers/gpu/drm/xe/regs/xe_gt_regs.h
@@ -530,6 +530,9 @@
#define LMEM_EN REG_BIT(31)
#define LMTT_DIR_PTR REG_GENMASK(30, 0) /* in multiples of 64KB */
+#define PAGE_FLTRPTQ_HEAD_GAMCTRL XE_REG(0xcf90)
+#define PAGE_FLTRPTQ_TAIL_GAMCTRL XE_REG(0xcf94)
+
#define HALF_SLICE_CHICKEN5 XE_REG_MCR(0xe188, XE_REG_OPTION_MASKED)
#define DISABLE_SAMPLE_G_PERFORMANCE REG_BIT(0)
diff --git a/drivers/gpu/drm/xe/xe_devcoredump.c b/drivers/gpu/drm/xe/xe_devcoredump.c
index 49a7c020a161..8d59f80e2929 100644
--- a/drivers/gpu/drm/xe/xe_devcoredump.c
+++ b/drivers/gpu/drm/xe/xe_devcoredump.c
@@ -114,6 +114,11 @@ static const struct xe_reg_desc xe_dbg_media_gt_rpm_reglist[] = {
XE_REG_DESC(RPM_GCD, "RPM_GCD"),
};
+static const struct xe_reg_desc xe_dbg_gam_pf_reglist[] = {
+ XE_REG_DESC(PAGE_FLTRPTQ_HEAD_GAMCTRL, "PAGE_FLTRPTQ_HEAD_GAMCTRL"),
+ XE_REG_DESC(PAGE_FLTRPTQ_TAIL_GAMCTRL, "PAGE_FLTRPTQ_TAIL_GAMCTRL"),
+};
+
/**
* struct xe_gt_regset - Struct for register descriptor list for GT
*
@@ -133,12 +138,14 @@ struct xe_gt_regset {
* @XE_DBG_REGSET_FUSE: Fuse register set
* @XE_DBG_REGSET_RPM: RPM register set
* @XE_DBG_REGSET_GUC: GUC register set
+ * @XE_DBG_REGSET_GAM_PF: GAM Pagefault registers set
* @XE_DBG_REGSET_MAX: Number of debug register set types
*/
enum xe_dbg_regset_type {
XE_DBG_REGSET_FUSE,
XE_DBG_REGSET_RPM,
XE_DBG_REGSET_GUC,
+ XE_DBG_REGSET_GAM_PF,
XE_DBG_REGSET_MAX,
};
@@ -161,6 +168,10 @@ static const struct xe_gt_regset xe_dbg_regsets[XE_DBG_REGSET_MAX] = {
.gt[XE_GT_TYPE_MEDIA] = { xe_dbg_gt_guc_reglist,
ARRAY_SIZE(xe_dbg_gt_guc_reglist) },
},
+ [XE_DBG_REGSET_GAM_PF] = {
+ .gt[XE_GT_TYPE_MAIN] = { xe_dbg_gam_pf_reglist,
+ ARRAY_SIZE(xe_dbg_gam_pf_reglist) },
+ },
};
static void xe_dbg_reg_snapshot_print(struct drm_printer *p,
@@ -202,6 +213,23 @@ static const u32 *xe_dbg_find_value(const struct xe_dbg_reg_snapshot *snap,
return NULL;
}
+static void xe_gam_pf_snapshot_print(struct drm_printer *p,
+ const char *title,
+ const struct xe_dbg_reg_snapshot *snap)
+{
+ const u32 *val1, *val2;
+
+ xe_dbg_reg_snapshot_print(p, title, snap);
+
+ if (!snap)
+ return;
+
+ val1 = xe_dbg_find_value(snap, PAGE_FLTRPTQ_HEAD_GAMCTRL);
+ val2 = xe_dbg_find_value(snap, PAGE_FLTRPTQ_TAIL_GAMCTRL);
+ if ((val1 && val2) && (*val1 != *val2))
+ drm_printf(p, "PF occurred, refer to dmesg log for PF info\n");
+}
+
static void xe_gt_rpm_snapshot_print(struct drm_printer *p,
const char *title,
const struct xe_dbg_reg_snapshot *snap)
@@ -315,6 +343,8 @@ static ssize_t __xe_devcoredump_read(char *buffer, ssize_t count,
drm_puts(&p, "\n**** GuC CT ****\n");
xe_guc_ct_snapshot_print(ss->guc.ct, &p, ss->gt);
+ xe_gam_pf_snapshot_print(&p, "GAM PF Report", ss->gam_pf_report);
+
drm_puts(&p, "\n**** Contexts ****\n");
xe_guc_exec_queue_snapshot_print(ss->ge, &p);
@@ -369,6 +399,9 @@ static void xe_devcoredump_snapshot_free(struct xe_devcoredump_snapshot *ss)
xe_guc_capture_put_matched_nodes(&ss->gt->uc.guc);
ss->matched_node = NULL;
+ xe_dbg_reg_snapshot_free(ss->gam_pf_report);
+ ss->gam_pf_report = NULL;
+
xe_guc_exec_queue_snapshot_free(ss->ge);
ss->ge = NULL;
@@ -565,6 +598,10 @@ static void xe_devcoredump_capture_gt_regs(struct xe_devcoredump_snapshot *ss,
other_gt,
XE_DBG_REGSET_GUC,
XE_GT_TYPE_MEDIA);
+ ss->gam_pf_report = xe_dbg_gt_snapshot_capture(gt,
+ other_gt,
+ XE_DBG_REGSET_GAM_PF,
+ XE_GT_TYPE_MAIN);
}
static void devcoredump_snapshot(struct xe_devcoredump *coredump,
diff --git a/drivers/gpu/drm/xe/xe_devcoredump_types.h b/drivers/gpu/drm/xe/xe_devcoredump_types.h
index 52db64640f89..34f224a6751f 100644
--- a/drivers/gpu/drm/xe/xe_devcoredump_types.h
+++ b/drivers/gpu/drm/xe/xe_devcoredump_types.h
@@ -103,6 +103,9 @@ struct xe_devcoredump_snapshot {
struct xe_guc_log_snapshot *log;
} guc;
+ /** @gam_pf_report: GAM PF report snapshot */
+ struct xe_dbg_reg_snapshot *gam_pf_report;
+
/** @ge: GuC Submission Engine snapshot */
struct xe_guc_submit_exec_queue_snapshot *ge;
--
2.43.0
^ permalink raw reply related [flat|nested] 23+ messages in thread
* [PATCH v5 5/7] drm/xe/guc: add TDL, SLICE gfx registers to capture list
2026-10-23 6:05 [PATCH v5 0/7] drm/xe: Capture additional HW register state in devcoredump Nareshkumar Gollakoti
` (3 preceding siblings ...)
2026-10-23 6:05 ` [PATCH v5 4/7] drm/xe: dump GAM page fault report registers in devcoredump Nareshkumar Gollakoti
@ 2026-10-23 6:05 ` Nareshkumar Gollakoti
2026-10-26 6:55 ` Upadhyay, Tejas
2026-10-23 6:05 ` [PATCH v5 6/7] drm/xe: capture L3 node status registers in devcoredump Nareshkumar Gollakoti
` (5 subsequent siblings)
10 siblings, 1 reply; 23+ messages in thread
From: Nareshkumar Gollakoti @ 2026-10-23 6:05 UTC (permalink / raw)
To: intel-xe; +Cc: tejas.upadhyay, Nareshkumar Gollakoti
Add ROW_INSTDONE_TDL_GFX, SS_LSC_HDC_IDLE_TDL_GFX and SLICE_ARB_STATUS
register definitions and include them in the XeHPG extended GuC capture
register list.
v2:(Sashiko)
- Refactored ROW_INSTDONE_TDL_GFX to ROW_INSTDONE_TDL_GFX
- Add SLICE_ARB_STATUS register to xeHP register list
- Refactor commit message
Signed-off-by: Nareshkumar Gollakoti <naresh.kumar.g@intel.com>
---
drivers/gpu/drm/xe/regs/xe_gt_regs.h | 5 +++++
drivers/gpu/drm/xe/xe_guc_capture.c | 5 ++++-
2 files changed, 9 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/xe/regs/xe_gt_regs.h b/drivers/gpu/drm/xe/regs/xe_gt_regs.h
index e9eb0bd04af1..2e4cb4957479 100644
--- a/drivers/gpu/drm/xe/regs/xe_gt_regs.h
+++ b/drivers/gpu/drm/xe/regs/xe_gt_regs.h
@@ -533,6 +533,8 @@
#define PAGE_FLTRPTQ_HEAD_GAMCTRL XE_REG(0xcf90)
#define PAGE_FLTRPTQ_TAIL_GAMCTRL XE_REG(0xcf94)
+#define SLICE_ARB_STATUS XE_REG_MCR(0xd814)
+
#define HALF_SLICE_CHICKEN5 XE_REG_MCR(0xe188, XE_REG_OPTION_MASKED)
#define DISABLE_SAMPLE_G_PERFORMANCE REG_BIT(0)
@@ -597,6 +599,9 @@
#define EU_SYSTOLIC_LIC_THROTTLE_CTL_WITH_LOCK XE_REG_MCR(0xe534)
#define EU_SYSTOLIC_LIC_THROTTLE_CTL_LOCK_BIT REG_BIT(31)
+#define ROW_INSTDONE_TDL_GFX XE_REG_MCR(0xe580)
+#define SS_LSC_HDC_IDLE_TDL_GFX XE_REG_MCR(0xe584)
+
#define XEHP_HDC_CHICKEN0 XE_REG_MCR(0xe5f0, XE_REG_OPTION_MASKED)
#define LSC_L1_FLUSH_CTL_3D_DATAPORT_FLUSH_EVENTS_MASK REG_GENMASK(13, 11)
#define DIS_ATOMIC_CHAINING_TYPED_WRITES REG_BIT(3)
diff --git a/drivers/gpu/drm/xe/xe_guc_capture.c b/drivers/gpu/drm/xe/xe_guc_capture.c
index 3e99aef53b46..6a20eab0f820 100644
--- a/drivers/gpu/drm/xe/xe_guc_capture.c
+++ b/drivers/gpu/drm/xe/xe_guc_capture.c
@@ -376,7 +376,10 @@ static const struct __ext_steer_reg xehpg_extregs[] = {
{"SC_INSTDONE", XEHPG_SC_INSTDONE},
{"SC_INSTDONE_EXTRA", XEHPG_SC_INSTDONE_EXTRA},
{"SC_INSTDONE_EXTRA2", XEHPG_SC_INSTDONE_EXTRA2},
- {"INSTDONE_GEOM_SVGUNIT", XEHPG_INSTDONE_GEOM_SVGUNIT}
+ {"INSTDONE_GEOM_SVGUNIT", XEHPG_INSTDONE_GEOM_SVGUNIT},
+ {"ROW_INSTDONE_TDL_GFX", ROW_INSTDONE_TDL_GFX},
+ {"SS_LSC_HDC_IDLE_TDL_GFX", SS_LSC_HDC_IDLE_TDL_GFX},
+ {"SLICE_ARB_STATUS", SLICE_ARB_STATUS}
};
static void __fill_ext_reg(struct __guc_mmio_reg_descr *ext,
--
2.43.0
^ permalink raw reply related [flat|nested] 23+ messages in thread
* [PATCH v5 6/7] drm/xe: capture L3 node status registers in devcoredump
2026-10-23 6:05 [PATCH v5 0/7] drm/xe: Capture additional HW register state in devcoredump Nareshkumar Gollakoti
` (4 preceding siblings ...)
2026-10-23 6:05 ` [PATCH v5 5/7] drm/xe/guc: add TDL, SLICE gfx registers to capture list Nareshkumar Gollakoti
@ 2026-10-23 6:05 ` Nareshkumar Gollakoti
2026-10-23 6:24 ` sashiko-bot
2026-10-23 6:05 ` [PATCH v5 7/7] drm/xe/guc: capture additional engine state registers Nareshkumar Gollakoti
` (4 subsequent siblings)
10 siblings, 1 reply; 23+ messages in thread
From: Nareshkumar Gollakoti @ 2026-10-23 6:05 UTC (permalink / raw)
To: intel-xe; +Cc: tejas.upadhyay, Nareshkumar Gollakoti
Add L3_NODE_IDLE and L3STAT_LBCF_GFX register definitions and include
them in the devcoredump snapshot as a node status section.
Extend the register descriptor to mark MCR registers so the snapshot
code can read them through xe_gt_mcr_unicast_read_any(), then print and
free the captured node status registers alongside the existing dump
sections.
v2:(Sashiko)
- change L3 node registers as XE_REG_MCR type
- identify mcr register type from reg.mcr
- As generic capture function ensure VF check this will not execute
on VF Mode.
v4:(Tejas)
- Add L3_NODE type into the enum as changed/added in initial patch
v5:
- Rebase
Signed-off-by: Nareshkumar Gollakoti <naresh.kumar.g@intel.com>
---
drivers/gpu/drm/xe/regs/xe_gt_regs.h | 3 +++
drivers/gpu/drm/xe/xe_devcoredump.c | 32 ++++++++++++++++++++---
drivers/gpu/drm/xe/xe_devcoredump_types.h | 10 +++++--
3 files changed, 40 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/xe/regs/xe_gt_regs.h b/drivers/gpu/drm/xe/regs/xe_gt_regs.h
index 2e4cb4957479..55f0eee4e20e 100644
--- a/drivers/gpu/drm/xe/regs/xe_gt_regs.h
+++ b/drivers/gpu/drm/xe/regs/xe_gt_regs.h
@@ -454,6 +454,9 @@
#define L3_ESC_MASK REG_BIT(0)
#define L3_ESC(value) REG_FIELD_PREP(L3_ESC_MASK, value)
+#define L3_NODE_IDLE XE_REG_MCR(0xb0b0)
+#define L3STAT_LBCF_GFX XE_REG_MCR(0xb128)
+
#define XEHP_L3NODEARBCFG XE_REG_MCR(0xb0b4)
#define XEHP_LNESPARE REG_BIT(19)
diff --git a/drivers/gpu/drm/xe/xe_devcoredump.c b/drivers/gpu/drm/xe/xe_devcoredump.c
index 8d59f80e2929..de9ef3e0cb5d 100644
--- a/drivers/gpu/drm/xe/xe_devcoredump.c
+++ b/drivers/gpu/drm/xe/xe_devcoredump.c
@@ -28,6 +28,7 @@
#include "xe_mmio.h"
#include "regs/xe_gt_regs.h"
#include "regs/xe_guc_regs.h"
+#include "xe_gt_mcr.h"
/**
* DOC: Xe device coredump
@@ -73,6 +74,7 @@
#define XE_COREDUMP_TIMEOUT_JIFFIES (60 * 60 * HZ)
#define XE_REG_DESC(_reg, _name) { .reg = (_reg), .name = (_name) }
+#define XE_REG_DESC_MCR(_reg, _name) { .mcr_reg = (_reg), .name = (_name) }
static const struct xe_reg_desc xe_dbg_gt_guc_reglist[] = {
XE_REG_DESC(GUC_STATUS, "GUC_STATUS"),
@@ -119,6 +121,11 @@ static const struct xe_reg_desc xe_dbg_gam_pf_reglist[] = {
XE_REG_DESC(PAGE_FLTRPTQ_TAIL_GAMCTRL, "PAGE_FLTRPTQ_TAIL_GAMCTRL"),
};
+static const struct xe_reg_desc xe_dbg_l3_node_reglist[] = {
+ XE_REG_DESC_MCR(L3_NODE_IDLE, "L3_NODE_IDLE"),
+ XE_REG_DESC_MCR(L3STAT_LBCF_GFX, "L3STAT_LBCF_GFX"),
+};
+
/**
* struct xe_gt_regset - Struct for register descriptor list for GT
*
@@ -139,6 +146,7 @@ struct xe_gt_regset {
* @XE_DBG_REGSET_RPM: RPM register set
* @XE_DBG_REGSET_GUC: GUC register set
* @XE_DBG_REGSET_GAM_PF: GAM Pagefault registers set
+ * @XE_DBG_REGSET_L3_NODE: L3 Node register Set
* @XE_DBG_REGSET_MAX: Number of debug register set types
*/
enum xe_dbg_regset_type {
@@ -146,6 +154,7 @@ enum xe_dbg_regset_type {
XE_DBG_REGSET_RPM,
XE_DBG_REGSET_GUC,
XE_DBG_REGSET_GAM_PF,
+ XE_DBG_REGSET_L3_NODE,
XE_DBG_REGSET_MAX,
};
@@ -172,6 +181,10 @@ static const struct xe_gt_regset xe_dbg_regsets[XE_DBG_REGSET_MAX] = {
.gt[XE_GT_TYPE_MAIN] = { xe_dbg_gam_pf_reglist,
ARRAY_SIZE(xe_dbg_gam_pf_reglist) },
},
+ [XE_DBG_REGSET_L3_NODE] = {
+ .gt[XE_GT_TYPE_MAIN] = { xe_dbg_l3_node_reglist,
+ ARRAY_SIZE(xe_dbg_l3_node_reglist) },
+ },
};
static void xe_dbg_reg_snapshot_print(struct drm_printer *p,
@@ -262,8 +275,13 @@ xe_dbg_reg_snapshot_capture_target(struct xe_gt *gt,
snap->desc = reglist;
snap->num_regs = reglist->num_regs;
- for (i = 0; i < reglist->num_regs; i++)
- snap->values[i] = xe_mmio_read32(>->mmio, reglist->regs[i].reg);
+ for (i = 0; i < reglist->num_regs; i++) {
+ if (reglist->regs[i].reg.mcr)
+ snap->values[i] = xe_gt_mcr_unicast_read_any(gt,
+ reglist->regs[i].mcr_reg);
+ else
+ snap->values[i] = xe_mmio_read32(>->mmio, reglist->regs[i].reg);
+ }
return snap;
}
@@ -345,6 +363,8 @@ static ssize_t __xe_devcoredump_read(char *buffer, ssize_t count,
xe_gam_pf_snapshot_print(&p, "GAM PF Report", ss->gam_pf_report);
+ xe_dbg_reg_snapshot_print(&p, "Node Status", ss->ns);
+
drm_puts(&p, "\n**** Contexts ****\n");
xe_guc_exec_queue_snapshot_print(ss->ge, &p);
@@ -402,6 +422,9 @@ static void xe_devcoredump_snapshot_free(struct xe_devcoredump_snapshot *ss)
xe_dbg_reg_snapshot_free(ss->gam_pf_report);
ss->gam_pf_report = NULL;
+ xe_dbg_reg_snapshot_free(ss->ns);
+ ss->ns = NULL;
+
xe_guc_exec_queue_snapshot_free(ss->ge);
ss->ge = NULL;
@@ -602,6 +625,10 @@ static void xe_devcoredump_capture_gt_regs(struct xe_devcoredump_snapshot *ss,
other_gt,
XE_DBG_REGSET_GAM_PF,
XE_GT_TYPE_MAIN);
+ ss->ns = xe_dbg_gt_snapshot_capture(gt,
+ other_gt,
+ XE_DBG_REGSET_L3_NODE,
+ XE_GT_TYPE_MAIN);
}
static void devcoredump_snapshot(struct xe_devcoredump *coredump,
@@ -653,7 +680,6 @@ static void devcoredump_snapshot(struct xe_devcoredump *coredump,
if (job)
ss->job = xe_sched_job_snapshot_capture(job);
ss->vm = xe_vm_snapshot_capture(q->vm);
-
xe_engine_snapshot_capture_for_queue(q);
}
diff --git a/drivers/gpu/drm/xe/xe_devcoredump_types.h b/drivers/gpu/drm/xe/xe_devcoredump_types.h
index 34f224a6751f..6cbecad43c42 100644
--- a/drivers/gpu/drm/xe/xe_devcoredump_types.h
+++ b/drivers/gpu/drm/xe/xe_devcoredump_types.h
@@ -21,8 +21,12 @@ struct xe_gt;
* of the register to dump its value during coredump for debug purpose.
*/
struct xe_reg_desc {
- /** @reg: The register */
- struct xe_reg reg;
+ union {
+ /** @reg: The register */
+ struct xe_reg reg;
+ /** @mcr_reg: The mcr register */
+ struct xe_reg_mcr mcr_reg;
+ };
/** @name: Name of the register */
const char *name;
};
@@ -105,6 +109,8 @@ struct xe_devcoredump_snapshot {
/** @gam_pf_report: GAM PF report snapshot */
struct xe_dbg_reg_snapshot *gam_pf_report;
+ /** @ns: Node status snapshot */
+ struct xe_dbg_reg_snapshot *ns;
/** @ge: GuC Submission Engine snapshot */
struct xe_guc_submit_exec_queue_snapshot *ge;
--
2.43.0
^ permalink raw reply related [flat|nested] 23+ messages in thread
* [PATCH v5 7/7] drm/xe/guc: capture additional engine state registers
2026-10-23 6:05 [PATCH v5 0/7] drm/xe: Capture additional HW register state in devcoredump Nareshkumar Gollakoti
` (5 preceding siblings ...)
2026-10-23 6:05 ` [PATCH v5 6/7] drm/xe: capture L3 node status registers in devcoredump Nareshkumar Gollakoti
@ 2026-10-23 6:05 ` Nareshkumar Gollakoti
2026-10-23 6:26 ` sashiko-bot
2026-10-26 9:15 ` Upadhyay, Tejas
2026-10-23 6:14 ` ✗ CI.checkpatch: warning for drm/xe: Capture additional HW register state in devcoredump (rev6) Patchwork
` (3 subsequent siblings)
10 siblings, 2 replies; 23+ messages in thread
From: Nareshkumar Gollakoti @ 2026-10-23 6:05 UTC (permalink / raw)
To: intel-xe; +Cc: tejas.upadhyay, Nareshkumar Gollakoti
Add a wider set of engine state registers to GuC error capture to improve
post-mortem debugging of engine hangs and reset-related failures.
Define the missing register offsets in xe_engine_regs.h and include them in
the GuC capture list. The additional registers cover reset state, front-end
and back-end FSM state, power state, batch buffer state, instruction state,
preemption status, and related chicken/debug controls.
This provides more complete engine context in capture dumps, which should
help root-cause analysis when investigating GuC-reported engine failures.
v3:(Sashiko)
- Move FF_SLICE_CS_CHICKEN1/2 out of COMMON_BASE_ENGINE_INSTANCE
- Add XE3P_RC_SLICE_INSTANCE and include it only in xe3p_rc_inst_regs[]
- Add XE_BCS_RCS_ENGINE_INSTANCE for registers shared only by
BCS/RCS paths
- Include XE_BCS_RCS_ENGINE_INSTANCE only in
xe_blt_inst_regs[] and xe3p_rc_inst_regs[]
- Keep COMMON_BASE_ENGINE_INSTANCE limited to registers
valid across all engine classes
v5:(Sashiko)
- Keep RING_EXECLIST_* in COMMON_BASE_ENGINE_INSTANCE
- Drop XE_BCS_RCS_ENGINE_INSTANCE
- BCS_SWCTRL only on xe3p_blt_inst_regs
- CS_DEBUG_MODE1/CS_CHICKEN1/CS_PREEMPTION_STATUS only on xe3p_rc_inst_regs
Signed-off-by: Nareshkumar Gollakoti <naresh.kumar.g@intel.com>
---
drivers/gpu/drm/xe/regs/xe_engine_regs.h | 22 +++++++++
drivers/gpu/drm/xe/xe_guc_capture.c | 57 ++++++++++++++++++++++--
2 files changed, 76 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/xe/regs/xe_engine_regs.h b/drivers/gpu/drm/xe/regs/xe_engine_regs.h
index 94033982e694..9f328b1b18f5 100644
--- a/drivers/gpu/drm/xe/regs/xe_engine_regs.h
+++ b/drivers/gpu/drm/xe/regs/xe_engine_regs.h
@@ -60,6 +60,8 @@
#define RING_START_UDW(base) XE_REG((base) + 0x48)
+#define RING_CSFE_GLB_CHICKEN3(base) XE_REG((base) + 0x4c)
+
#define RING_PSMI_CTL(base) XE_REG((base) + 0x50, XE_REG_OPTION_MASKED)
#define RC_SEMA_IDLE_MSG_DISABLE REG_BIT(12)
#define WAIT_FOR_EVENT_POWER_DOWN_DISABLE REG_BIT(7)
@@ -72,6 +74,7 @@
#define RING_DMA_FADD_UDW(base) XE_REG((base) + 0x60)
#define RING_IPEHR(base) XE_REG((base) + 0x68)
#define RING_INSTDONE(base) XE_REG((base) + 0x6c)
+#define RING_INSTPS(base) XE_REG((base) + 0x70)
#define RING_ACTHD(base) XE_REG((base) + 0x74)
#define RING_DMA_FADD(base) XE_REG((base) + 0x78)
#define RING_HWS_PGA(base) XE_REG((base) + 0x80)
@@ -102,6 +105,8 @@
#define SELECTIVE_READ_GROUP REG_GENMASK(29, 23)
#define SELECTIVE_READ_INSTANCE REG_GENMASK(22, 16)
+#define RESET_CTRL(base) XE_REG((base) + 0xd0)
+
/*
* CMD_CCTL read/write fields take a MOCS value and _not_ a table index.
* The lsb of each can be considered a separate enabling bit for encryption.
@@ -123,15 +128,21 @@
#define FF_SLICE_CS_CHICKEN1(base) XE_REG((base) + 0xe0, XE_REG_OPTION_MASKED)
#define FFSC_PERCTX_PREEMPT_CTRL REG_BIT(14)
+#define FF_SLICE_CS_CHICKEN2(base) XE_REG((base) + 0xe4, XE_REG_OPTION_MASKED)
+
#define CS_DEBUG_MODE1(base) XE_REG((base) + 0xec, XE_REG_OPTION_MASKED)
#define FF_DOP_CLOCK_GATE_DISABLE REG_BIT(1)
#define REPLAY_MODE_GRANULARITY REG_BIT(0)
#define INDIRECT_RING_STATE(base) XE_REG((base) + 0x108)
+#define RING_BB_STATE(base) XE_REG((base) + 0x110)
+
#define RING_BBADDR(base) XE_REG((base) + 0x140)
#define RING_BBADDR_UDW(base) XE_REG((base) + 0x168)
+#define RING_BB_ADDR_DIFF(base) XE_REG((base) + 0x154)
+
#define PR_CTR_CTRL(base) XE_REG((base) + 0x178)
#define CTR_COUNT_SELECT_FF REG_BIT(31)
#define CTR_LOGIC_OP_MASK REG_GENMASK(30, 0)
@@ -148,6 +159,8 @@
#define BLIT_CCTL_DST_MOCS_MASK REG_GENMASK(14, 9)
#define BLIT_CCTL_SRC_MOCS_MASK REG_GENMASK(6, 1)
+#define RING_CSBEFSM3(base) XE_REG((base) + 0x224)
+
#define RING_EXECLIST_STATUS_LO(base) XE_REG((base) + 0x234)
#define RING_EXECLIST_STATUS_HI(base) XE_REG((base) + 0x234 + 4)
@@ -169,9 +182,16 @@
#define GFX_MSIX_INTERRUPT_ENABLE REG_BIT(13)
#define GFX_DISABLE_LEGACY_MODE REG_BIT(3)
+#define RING_CSFESM(base) XE_REG((base) + 0x2a0)
+#define RING_CSFESM2(base) XE_REG((base) + 0x2a4)
+#define RING_CSFESM3(base) XE_REG((base) + 0x2a8)
+#define RING_CSPWRFSM(base) XE_REG((base) + 0x2ac)
+
#define RING_CSMQDEBUG(base) XE_REG((base) + 0x2b0)
#define CURRENT_ACTIVE_QUEUE_ID_MASK REG_GENMASK(7, 0)
+#define RING_CSBEFSM(base) XE_REG((base) + 0x2bc)
+
#define RING_QUEUE_TIMESTAMP(base) XE_REG((base) + 0x4c0)
#define RING_QUEUE_TIMESTAMP_UDW(base) XE_REG((base) + 0x4c0 + 4)
@@ -217,6 +237,8 @@
#define PREEMPT_GPGPU_LEVEL_MASK PREEMPT_GPGPU_LEVEL(1, 1)
#define PREEMPT_3D_OBJECT_LEVEL REG_BIT(0)
+#define CS_PREEMPTION_STATUS(base) XE_REG((base) + 0x5ac)
+
#define CS_GPR_DATA(base, n) XE_REG((base) + 0x600 + (n) * 4)
#define CS_GPR_REG(base, n) CS_GPR_DATA((base), (n) * 2)
#define CS_GPR_REG_UDW(base, n) CS_GPR_DATA((base), (n) * 2 + 1)
diff --git a/drivers/gpu/drm/xe/xe_guc_capture.c b/drivers/gpu/drm/xe/xe_guc_capture.c
index 6a20eab0f820..2e13df97e106 100644
--- a/drivers/gpu/drm/xe/xe_guc_capture.c
+++ b/drivers/gpu/drm/xe/xe_guc_capture.c
@@ -150,6 +150,33 @@ struct __guc_capture_parsed_output {
#define XE3P_BASE_ENGINE_INSTANCE \
{ RING_CSMQDEBUG(0), REG_32BIT, 0, 0, 0, "CSMQDEBUG"}
+#define XE3P_CS_DEBUG_INSTANCE \
+ { RESET_CTRL(0), REG_32BIT, 0, 0, 0, "RESET_CTRL"}, \
+ { RING_CSBEFSM3(0), REG_32BIT, 0, 0, 0, "RING_CSBEFSM3"}, \
+ { RING_CSFESM(0), REG_32BIT, 0, 0, 0, "RING_CSFESM"}, \
+ { RING_CSFESM2(0), REG_32BIT, 0, 0, 0, "RING_CSFESM2"}, \
+ { RING_CSFESM3(0), REG_32BIT, 0, 0, 0, "RING_CSFESM3"}, \
+ { RING_CSPWRFSM(0), REG_32BIT, 0, 0, 0, "RING_CSPWRFSM"}, \
+ { RING_CSBEFSM(0), REG_32BIT, 0, 0, 0, "RING_CSBEFSM"}, \
+ { RING_CSFE_GLB_CHICKEN3(0), REG_32BIT, 0, 0, 0, "RING_CSFE_GLB_CHICKEN3"}, \
+ { RING_PSMI_CTL(0), REG_32BIT, 0, 0, 0, "RING_PSMI_CTL"}, \
+ { RING_INSTPS(0), REG_32BIT, 0, 0, 0, "RING_INSTPS"}, \
+ { RING_BB_ADDR_DIFF(0), REG_32BIT, 0, 0, 0, "RING_BB_ADDR_DIFF"}, \
+ { RING_BB_STATE(0), REG_32BIT, 0, 0, 0, "RING_BB_STATE"}
+
+/*
+ * CS_CHICKEN1 has GPGPU/3D preempt bits; keep with RCS/CCS only.
+ * RCS+CCS share GUC_CAPTURE_LIST_CLASS_RENDER_COMPUTE, so these cannot
+ * be RCS-only.
+ */
+#define XE3P_RC_CS_PREEMPT_INSTANCE \
+ { CS_DEBUG_MODE1(0), REG_32BIT, 0, 0, 0, "CS_DEBUG_MODE1"}, \
+ { CS_CHICKEN1(0), REG_32BIT, 0, 0, 0, "CS_CHICKEN1"}, \
+ { CS_PREEMPTION_STATUS(0), REG_32BIT, 0, 0, 0, "CS_PREEMPTION_STATUS"}
+
+#define XE3P_BCS_ONLY_INSTANCE \
+ { BCS_SWCTRL(0), REG_32BIT, 0, 0, 0, "BCS_SWCTRL"}
+
/* XE_LP Global */
static const struct __guc_mmio_reg_descr xe_lp_global_regs[] = {
COMMON_XELP_BASE_GLOBAL,
@@ -186,9 +213,12 @@ static const struct __guc_mmio_reg_descr xe_vec_inst_regs[] = {
COMMON_BASE_ENGINE_INSTANCE,
};
+#define XE_BLT_INST_REGS \
+ COMMON_BASE_ENGINE_INSTANCE
+
/* Blitter Per-Engine-Instance */
static const struct __guc_mmio_reg_descr xe_blt_inst_regs[] = {
- COMMON_BASE_ENGINE_INSTANCE,
+ XE_BLT_INST_REGS,
};
/* XE_LP - GSC Per-Engine-Instance */
@@ -200,6 +230,15 @@ static const struct __guc_mmio_reg_descr xe_lp_gsc_inst_regs[] = {
static const struct __guc_mmio_reg_descr xe3p_rc_inst_regs[] = {
COMMON_BASE_ENGINE_INSTANCE,
XE3P_BASE_ENGINE_INSTANCE,
+ XE3P_CS_DEBUG_INSTANCE,
+ XE3P_RC_CS_PREEMPT_INSTANCE,
+};
+
+/* Xe3p Blitter Per-Engine-Instance */
+static const struct __guc_mmio_reg_descr xe3p_blt_inst_regs[] = {
+ XE_BLT_INST_REGS,
+ XE3P_CS_DEBUG_INSTANCE,
+ XE3P_BCS_ONLY_INSTANCE,
};
/*
@@ -264,7 +303,7 @@ static const struct __guc_mmio_reg_descr_group xe3p_lists[] = {
MAKE_REGLIST(xe_vec_class_regs, PF, ENGINE_CLASS, GUC_CAPTURE_LIST_CLASS_VIDEOENHANCE),
MAKE_REGLIST(xe_vec_inst_regs, PF, ENGINE_INSTANCE, GUC_CAPTURE_LIST_CLASS_VIDEOENHANCE),
MAKE_REGLIST(empty_regs_list, PF, ENGINE_CLASS, GUC_CAPTURE_LIST_CLASS_BLITTER),
- MAKE_REGLIST(xe_blt_inst_regs, PF, ENGINE_INSTANCE, GUC_CAPTURE_LIST_CLASS_BLITTER),
+ MAKE_REGLIST(xe3p_blt_inst_regs, PF, ENGINE_INSTANCE, GUC_CAPTURE_LIST_CLASS_BLITTER),
MAKE_REGLIST(empty_regs_list, PF, ENGINE_CLASS, GUC_CAPTURE_LIST_CLASS_GSC_OTHER),
MAKE_REGLIST(xe_lp_gsc_inst_regs, PF, ENGINE_INSTANCE, GUC_CAPTURE_LIST_CLASS_GSC_OTHER),
MAKE_REGLIST(empty_regs_list, PF, ENGINE_CLASS, GUC_CAPTURE_LIST_CLASS_PAGING),
@@ -377,9 +416,12 @@ static const struct __ext_steer_reg xehpg_extregs[] = {
{"SC_INSTDONE_EXTRA", XEHPG_SC_INSTDONE_EXTRA},
{"SC_INSTDONE_EXTRA2", XEHPG_SC_INSTDONE_EXTRA2},
{"INSTDONE_GEOM_SVGUNIT", XEHPG_INSTDONE_GEOM_SVGUNIT},
+};
+
+static const struct __ext_steer_reg xe2_extregs[] = {
{"ROW_INSTDONE_TDL_GFX", ROW_INSTDONE_TDL_GFX},
{"SS_LSC_HDC_IDLE_TDL_GFX", SS_LSC_HDC_IDLE_TDL_GFX},
- {"SLICE_ARB_STATUS", SLICE_ARB_STATUS}
+ {"SLICE_ARB_STATUS", SLICE_ARB_STATUS},
};
static void __fill_ext_reg(struct __guc_mmio_reg_descr *ext,
@@ -422,6 +464,8 @@ static int guc_capture_get_steer_reg_num(struct xe_device *xe)
if (GRAPHICS_VERx100(xe) >= 1255)
num += ARRAY_SIZE(xehpg_extregs);
+ if (GRAPHICS_VER(xe) >= 20)
+ num += ARRAY_SIZE(xe2_extregs);
return num;
}
@@ -434,6 +478,7 @@ static void guc_capture_alloc_steered_lists(struct xe_guc *guc)
const struct __guc_mmio_reg_descr_group *lists = guc->capture->reglists;
const struct __guc_mmio_reg_descr_group *list;
struct __guc_mmio_reg_descr_group *extlists;
+ bool has_xe2_extregs = GRAPHICS_VER(gt_to_xe(gt)) >= 20;
struct __guc_mmio_reg_descr *extarray;
bool has_xehpg_extregs = GRAPHICS_VERx100(gt_to_xe(gt)) >= 1255;
struct drm_device *drm = >_to_xe(gt)->drm;
@@ -504,6 +549,12 @@ static void guc_capture_alloc_steered_lists(struct xe_guc *guc)
__fill_ext_reg(extarray, &xehpg_extregs[i], dss, slice, subslice);
++extarray;
}
+
+ if (has_xe2_extregs)
+ for (i = 0; i < ARRAY_SIZE(xe2_extregs); ++i) {
+ __fill_ext_reg(extarray, &xe2_extregs[i], dss, slice, subslice);
+ ++extarray;
+ }
}
extlists[0].num_regs = total;
--
2.43.0
^ permalink raw reply related [flat|nested] 23+ messages in thread
* ✗ CI.checkpatch: warning for drm/xe: Capture additional HW register state in devcoredump (rev6)
2026-10-23 6:05 [PATCH v5 0/7] drm/xe: Capture additional HW register state in devcoredump Nareshkumar Gollakoti
` (6 preceding siblings ...)
2026-10-23 6:05 ` [PATCH v5 7/7] drm/xe/guc: capture additional engine state registers Nareshkumar Gollakoti
@ 2026-10-23 6:14 ` Patchwork
2026-10-23 6:16 ` ✓ CI.KUnit: success " Patchwork
` (2 subsequent siblings)
10 siblings, 0 replies; 23+ messages in thread
From: Patchwork @ 2026-10-23 6:14 UTC (permalink / raw)
To: Nareshkumar Gollakoti; +Cc: intel-xe
== Series Details ==
Series: drm/xe: Capture additional HW register state in devcoredump (rev6)
URL : https://patchwork.freedesktop.org/series/172150/
State : warning
== Summary ==
+ KERNEL=/kernel
+ git clone https://gitlab.freedesktop.org/drm/maintainer-tools mt
Cloning into 'mt'...
warning: redirecting to https://gitlab.freedesktop.org/drm/maintainer-tools.git/
+ git -C mt rev-list -n1 origin/master
3009867cd31863246e4afc138520a7a8bd37bb11
+ cd /kernel
+ git config --global --add safe.directory /kernel
+ git log -n1
commit 3e857f8281fcf2cb47471e1eb2fdc8ee937725e8
Author: Nareshkumar Gollakoti <naresh.kumar.g@intel.com>
Date: Fri Oct 23 11:35:54 2026 +0530
drm/xe/guc: capture additional engine state registers
Add a wider set of engine state registers to GuC error capture to improve
post-mortem debugging of engine hangs and reset-related failures.
Define the missing register offsets in xe_engine_regs.h and include them in
the GuC capture list. The additional registers cover reset state, front-end
and back-end FSM state, power state, batch buffer state, instruction state,
preemption status, and related chicken/debug controls.
This provides more complete engine context in capture dumps, which should
help root-cause analysis when investigating GuC-reported engine failures.
v3:(Sashiko)
- Move FF_SLICE_CS_CHICKEN1/2 out of COMMON_BASE_ENGINE_INSTANCE
- Add XE3P_RC_SLICE_INSTANCE and include it only in xe3p_rc_inst_regs[]
- Add XE_BCS_RCS_ENGINE_INSTANCE for registers shared only by
BCS/RCS paths
- Include XE_BCS_RCS_ENGINE_INSTANCE only in
xe_blt_inst_regs[] and xe3p_rc_inst_regs[]
- Keep COMMON_BASE_ENGINE_INSTANCE limited to registers
valid across all engine classes
v5:(Sashiko)
- Keep RING_EXECLIST_* in COMMON_BASE_ENGINE_INSTANCE
- Drop XE_BCS_RCS_ENGINE_INSTANCE
- BCS_SWCTRL only on xe3p_blt_inst_regs
- CS_DEBUG_MODE1/CS_CHICKEN1/CS_PREEMPTION_STATUS only on xe3p_rc_inst_regs
Signed-off-by: Nareshkumar Gollakoti <naresh.kumar.g@intel.com>
+ /mt/dim checkpatch 2b2e3642e6d2095bbaae7b552da1c5ad164047a5 drm-intel
940dfdd22208 drm/xe/devcoredump: Capture GT fuse registers in devcoredump
51412ba19bfd drm/xe/devcoredump: Add GuC register snapshot to devcoredump
d236bc8580c0 drm/xe/guc: Print register addresses in capture snapshot output
fc82b5d067d6 drm/xe: dump GAM page fault report registers in devcoredump
91ea80f9bbf0 drm/xe/guc: add TDL, SLICE gfx registers to capture list
4774661c01ca drm/xe: capture L3 node status registers in devcoredump
3e857f8281fc drm/xe/guc: capture additional engine state registers
-:130: ERROR:COMPLEX_MACRO: Macros with complex values should be enclosed in parentheses
#130: FILE: drivers/gpu/drm/xe/xe_guc_capture.c:153:
+#define XE3P_CS_DEBUG_INSTANCE \
+ { RESET_CTRL(0), REG_32BIT, 0, 0, 0, "RESET_CTRL"}, \
+ { RING_CSBEFSM3(0), REG_32BIT, 0, 0, 0, "RING_CSBEFSM3"}, \
+ { RING_CSFESM(0), REG_32BIT, 0, 0, 0, "RING_CSFESM"}, \
+ { RING_CSFESM2(0), REG_32BIT, 0, 0, 0, "RING_CSFESM2"}, \
+ { RING_CSFESM3(0), REG_32BIT, 0, 0, 0, "RING_CSFESM3"}, \
+ { RING_CSPWRFSM(0), REG_32BIT, 0, 0, 0, "RING_CSPWRFSM"}, \
+ { RING_CSBEFSM(0), REG_32BIT, 0, 0, 0, "RING_CSBEFSM"}, \
+ { RING_CSFE_GLB_CHICKEN3(0), REG_32BIT, 0, 0, 0, "RING_CSFE_GLB_CHICKEN3"}, \
+ { RING_PSMI_CTL(0), REG_32BIT, 0, 0, 0, "RING_PSMI_CTL"}, \
+ { RING_INSTPS(0), REG_32BIT, 0, 0, 0, "RING_INSTPS"}, \
+ { RING_BB_ADDR_DIFF(0), REG_32BIT, 0, 0, 0, "RING_BB_ADDR_DIFF"}, \
+ { RING_BB_STATE(0), REG_32BIT, 0, 0, 0, "RING_BB_STATE"}
BUT SEE:
do {} while (0) advice is over-stated in a few situations:
The more obvious case is macros, like MODULE_PARM_DESC, invoked at
file-scope, where C disallows code (it must be in functions). See
$exceptions if you have one to add by name.
More troublesome is declarative macros used at top of new scope,
like DECLARE_PER_CPU. These might just compile with a do-while-0
wrapper, but would be incorrect. Most of these are handled by
detecting struct,union,etc declaration primitives in $exceptions.
Theres also macros called inside an if (block), which "return" an
expression. These cannot do-while, and need a ({}) wrapper.
Enjoy this qualification while we work to improve our heuristics.
-:138: WARNING:LONG_LINE: line length of 108 exceeds 100 columns
#138: FILE: drivers/gpu/drm/xe/xe_guc_capture.c:161:
+ { RING_CSFE_GLB_CHICKEN3(0), REG_32BIT, 0, 0, 0, "RING_CSFE_GLB_CHICKEN3"}, \
-:141: WARNING:LONG_LINE: line length of 103 exceeds 100 columns
#141: FILE: drivers/gpu/drm/xe/xe_guc_capture.c:164:
+ { RING_BB_ADDR_DIFF(0), REG_32BIT, 0, 0, 0, "RING_BB_ADDR_DIFF"}, \
-:149: ERROR:COMPLEX_MACRO: Macros with complex values should be enclosed in parentheses
#149: FILE: drivers/gpu/drm/xe/xe_guc_capture.c:172:
+#define XE3P_RC_CS_PREEMPT_INSTANCE \
+ { CS_DEBUG_MODE1(0), REG_32BIT, 0, 0, 0, "CS_DEBUG_MODE1"}, \
+ { CS_CHICKEN1(0), REG_32BIT, 0, 0, 0, "CS_CHICKEN1"}, \
+ { CS_PREEMPTION_STATUS(0), REG_32BIT, 0, 0, 0, "CS_PREEMPTION_STATUS"}
BUT SEE:
do {} while (0) advice is over-stated in a few situations:
The more obvious case is macros, like MODULE_PARM_DESC, invoked at
file-scope, where C disallows code (it must be in functions). See
$exceptions if you have one to add by name.
More troublesome is declarative macros used at top of new scope,
like DECLARE_PER_CPU. These might just compile with a do-while-0
wrapper, but would be incorrect. Most of these are handled by
detecting struct,union,etc declaration primitives in $exceptions.
Theres also macros called inside an if (block), which "return" an
expression. These cannot do-while, and need a ({}) wrapper.
Enjoy this qualification while we work to improve our heuristics.
-:152: WARNING:LONG_LINE: line length of 103 exceeds 100 columns
#152: FILE: drivers/gpu/drm/xe/xe_guc_capture.c:175:
+ { CS_PREEMPTION_STATUS(0), REG_32BIT, 0, 0, 0, "CS_PREEMPTION_STATUS"}
total: 2 errors, 3 warnings, 0 checks, 185 lines checked
^ permalink raw reply [flat|nested] 23+ messages in thread
* ✓ CI.KUnit: success for drm/xe: Capture additional HW register state in devcoredump (rev6)
2026-10-23 6:05 [PATCH v5 0/7] drm/xe: Capture additional HW register state in devcoredump Nareshkumar Gollakoti
` (7 preceding siblings ...)
2026-10-23 6:14 ` ✗ CI.checkpatch: warning for drm/xe: Capture additional HW register state in devcoredump (rev6) Patchwork
@ 2026-10-23 6:16 ` Patchwork
2026-10-23 6:56 ` ✓ Xe.CI.BAT: " Patchwork
2026-10-23 8:26 ` ✗ Xe.CI.FULL: failure " Patchwork
10 siblings, 0 replies; 23+ messages in thread
From: Patchwork @ 2026-10-23 6:16 UTC (permalink / raw)
To: Nareshkumar Gollakoti; +Cc: intel-xe
== Series Details ==
Series: drm/xe: Capture additional HW register state in devcoredump (rev6)
URL : https://patchwork.freedesktop.org/series/172150/
State : success
== Summary ==
+ trap cleanup EXIT
+ kunitconfigs=('/kernel/drivers/gpu/tests/.kunitconfig' '/kernel/drivers/gpu/drm/xe/.kunitconfig' '/kernel/drivers/gpu/drm/tests/.kunitconfig' '/kernel/drivers/gpu/drm/ttm/tests/.kunitconfig' '/kernel/drivers/dma-buf/.kunitconfig')
+ for kcfg in "${kunitconfigs[@]}"
+ [[ ! -f /kernel/drivers/gpu/tests/.kunitconfig ]]
+ /kernel/tools/testing/kunit/kunit.py run --kunitconfig /kernel/drivers/gpu/tests/.kunitconfig
[06:14:47] Configuring KUnit Kernel ...
Generating .config ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
[06:14:52] Building KUnit Kernel ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
Building with:
$ make all compile_commands.json scripts_gdb ARCH=um O=.kunit --jobs=48
[06:15:12] Starting KUnit Kernel (1/1)...
[06:15:12] ============================================================
Running tests with:
$ .kunit/linux kunit.enable=1 mem=1G console=tty kunit_shutdown=halt
[06:15:12] ================= gpu_buddy (14 subtests) ==================
[06:15:12] [PASSED] gpu_test_buddy_alloc_limit
[06:15:12] [PASSED] gpu_test_buddy_alloc_optimistic
[06:15:12] [PASSED] gpu_test_buddy_alloc_pessimistic
[06:15:12] [PASSED] gpu_test_buddy_alloc_pathological
[06:15:12] [PASSED] gpu_test_buddy_alloc_contiguous
[06:15:12] [PASSED] gpu_test_buddy_alloc_clear
[06:15:12] [PASSED] gpu_test_buddy_alloc_range
[06:15:12] [PASSED] gpu_test_buddy_alloc_range_bias
[06:15:13] [PASSED] gpu_test_buddy_fragmentation_performance
[06:15:14] [PASSED] gpu_test_buddy_dirty_tracker_performance
[06:15:14] [PASSED] gpu_test_buddy_alloc_exceeds_max_order
[06:15:14] [PASSED] gpu_test_buddy_offset_aligned_allocation
[06:15:14] [PASSED] gpu_test_buddy_subtree_offset_alignment_stress
[06:15:14] [PASSED] gpu_test_buddy_addr_to_block
[06:15:14] ==================== [PASSED] gpu_buddy ====================
[06:15:14] ============================================================
[06:15:14] Testing complete. Ran 14 tests: passed: 14
[06:15:14] Elapsed time: 26.517s total, 4.453s configuring, 20.197s building, 1.825s running
+ for kcfg in "${kunitconfigs[@]}"
+ [[ ! -f /kernel/drivers/gpu/drm/xe/.kunitconfig ]]
+ /kernel/tools/testing/kunit/kunit.py run --kunitconfig /kernel/drivers/gpu/drm/xe/.kunitconfig
[06:15:14] Configuring KUnit Kernel ...
Regenerating .config ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
[06:15:16] Building KUnit Kernel ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
Building with:
$ make all compile_commands.json scripts_gdb ARCH=um O=.kunit --jobs=48
[06:15:55] Starting KUnit Kernel (1/1)...
[06:15:55] ============================================================
Running tests with:
$ .kunit/linux kunit.enable=1 mem=1G console=tty kunit_shutdown=halt
[06:15:55] ================== guc_buf (11 subtests) ===================
[06:15:55] [PASSED] test_smallest
[06:15:55] [PASSED] test_largest
[06:15:55] [PASSED] test_granular
[06:15:55] [PASSED] test_unique
[06:15:55] [PASSED] test_overlap
[06:15:55] [PASSED] test_reusable
[06:15:55] [PASSED] test_too_big
[06:15:55] [PASSED] test_flush
[06:15:55] [PASSED] test_lookup
[06:15:55] [PASSED] test_data
[06:15:55] [PASSED] test_class
[06:15:55] ===================== [PASSED] guc_buf =====================
[06:15:55] =================== guc_dbm (7 subtests) ===================
[06:15:55] [PASSED] test_empty
[06:15:55] [PASSED] test_default
[06:15:55] ======================== test_size ========================
[06:15:55] [PASSED] 4
[06:15:55] [PASSED] 8
[06:15:55] [PASSED] 32
[06:15:55] [PASSED] 256
[06:15:55] ==================== [PASSED] test_size ====================
[06:15:55] ======================= test_reuse ========================
[06:15:55] [PASSED] 4
[06:15:55] [PASSED] 8
[06:15:55] [PASSED] 32
[06:15:55] [PASSED] 256
[06:15:55] =================== [PASSED] test_reuse ====================
[06:15:55] =================== test_range_overlap ====================
[06:15:55] [PASSED] 4
[06:15:55] [PASSED] 8
[06:15:55] [PASSED] 32
[06:15:55] [PASSED] 256
[06:15:55] =============== [PASSED] test_range_overlap ================
[06:15:55] =================== test_range_compact ====================
[06:15:55] [PASSED] 4
[06:15:55] [PASSED] 8
[06:15:55] [PASSED] 32
[06:15:55] [PASSED] 256
[06:15:55] =============== [PASSED] test_range_compact ================
[06:15:55] ==================== test_range_spare =====================
[06:15:55] [PASSED] 4
[06:15:55] [PASSED] 8
[06:15:55] [PASSED] 32
[06:15:55] [PASSED] 256
[06:15:55] ================ [PASSED] test_range_spare =================
[06:15:55] ===================== [PASSED] guc_dbm =====================
[06:15:55] ================== guc_idm (22 subtests) ===================
[06:15:55] [PASSED] bad_init
[06:15:55] [PASSED] no_init
[06:15:55] [PASSED] init_fini
[06:15:55] [PASSED] check_init_small
[06:15:55] [PASSED] check_init_shared
[06:15:55] [PASSED] check_used
[06:15:55] [PASSED] check_quota
[06:15:55] [PASSED] check_all
[06:15:55] [PASSED] check_limits
[06:15:55] [PASSED] check_overlap
[06:15:55] [PASSED] check_overlap_alloc
[06:15:55] [PASSED] check_overlap_release
[06:15:55] [PASSED] check_overlap_partial_init
[06:15:55] [PASSED] check_overlap_partial_shared_range_blocking
[06:15:55] [PASSED] check_used_usable
[06:15:55] [PASSED] check_used_shareable
[06:15:55] [PASSED] check_used_mixed
[06:15:55] [PASSED] check_release_usable_range
[06:15:55] [PASSED] check_release_shareable_range
[06:15:55] [PASSED] check_split_boundaries
[06:15:55] [PASSED] check_shareable_spare
[06:15:55] [PASSED] check_shareable_spare_fragmented_tail
[06:15:55] ===================== [PASSED] guc_idm =====================
[06:15:55] ============== guc_klv_helpers (13 subtests) ===============
[06:15:55] [PASSED] test_count
[06:15:55] [PASSED] test_encode_u32
[06:15:55] [PASSED] test_encode_u64
[06:15:55] [PASSED] test_encode_string
[06:15:55] [PASSED] test_encode_object_raw
[06:15:55] [PASSED] test_encode_object_klv
[06:15:55] [PASSED] test_encode_object_nested
[06:15:55] [PASSED] test_encode_object_basic
[06:15:55] ===================== test_decode_u16 =====================
[06:15:55] [PASSED] empty
[06:15:55] [PASSED] valid
[06:15:55] [PASSED] max
[06:15:55] [PASSED] big
[06:15:55] [PASSED] long
[06:15:55] ================= [PASSED] test_decode_u16 =================
[06:15:55] ===================== test_decode_u32 =====================
[06:15:55] [PASSED] empty
[06:15:55] [PASSED] valid
[06:15:55] [PASSED] max
[06:15:55] [PASSED] long
[06:15:55] ================= [PASSED] test_decode_u32 =================
[06:15:55] ===================== test_decode_u64 =====================
[06:15:55] [PASSED] empty
[06:15:55] [PASSED] short
[06:15:55] [PASSED] valid
[06:15:55] [PASSED] max
[06:15:55] [PASSED] long
[06:15:55] ================= [PASSED] test_decode_u64 =================
[06:15:55] ===================== test_decode_str =====================
[06:15:55] [PASSED] empty
[06:15:55] [PASSED] one
[06:15:55] [PASSED] one_trash
[06:15:55] [PASSED] two
[06:15:55] [PASSED] two_trash
[06:15:55] [PASSED] three
[06:15:55] [PASSED] dword
[06:15:55] [PASSED] four
[06:15:55] [PASSED] five
[06:15:55] [PASSED] six
[06:15:55] [PASSED] seven
[06:15:55] [PASSED] qword
[06:15:55] ================= [PASSED] test_decode_str =================
[06:15:55] [PASSED] test_print
[06:15:55] ================= [PASSED] guc_klv_helpers =================
[06:15:55] =================== xe_log (4 subtests) ====================
[06:15:55] [PASSED] demo_cper
[06:15:55] [PASSED] demo_dmesg
[06:15:55] ======================= test_dmesg ========================
[06:15:55] [PASSED] test_fatal
[06:15:55] [PASSED] test_fatal_tile
[06:15:55] [PASSED] test_fatal_gt
[06:15:55] [PASSED] test_fatal_comp
[06:15:55] [PASSED] test_fatal_comp_tile
[06:15:55] [PASSED] test_fatal_comp_gt
[06:15:55] [PASSED] test_fatal_all
[06:15:55] [PASSED] test_recoverable
[06:15:55] [PASSED] test_recoverable_tile
[06:15:55] [PASSED] test_recoverable_gt
[06:15:55] [PASSED] test_recoverable_comp
[06:15:55] [PASSED] test_recoverable_comp_tile
[06:15:55] [PASSED] test_recoverable_comp_gt
[06:15:55] [PASSED] test_recoverable_all
[06:15:55] [PASSED] test_info
[06:15:55] [PASSED] test_info_tile
[06:15:55] [PASSED] test_info_gt
[06:15:55] [PASSED] test_info_err
[06:15:55] [PASSED] test_info_comp
[06:15:55] [PASSED] test_info_comp_tile
[06:15:55] [PASSED] test_info_comp_gt
[06:15:55] [PASSED] test_info_all
[06:15:55] [PASSED] test_hw_fatal
[06:15:55] [PASSED] test_hw_recoverable
[06:15:55] [PASSED] test_hw_corrected
[06:15:55] [PASSED] test_hw_informational
[06:15:55] =================== [PASSED] test_dmesg ====================
[06:15:55] ====================== test_invalid =======================
[06:15:55] [SKIPPED] no-component no-location no-warn (requires CONFIG_DRM_XE_DEBUG)
[06:15:55] [SKIPPED] reserved location (requires CONFIG_DRM_XE_DEBUG)
[06:15:55] [SKIPPED] unknown location (requires CONFIG_DRM_XE_DEBUG)
[06:15:55] [SKIPPED] nonzero-device-id location (requires CONFIG_DRM_XE_DEBUG)
[06:15:55] [SKIPPED] invalid-tile-id location (requires CONFIG_DRM_XE_DEBUG)
[06:15:55] [SKIPPED] invalid-gt-id location (requires CONFIG_DRM_XE_DEBUG)
[06:15:55] [SKIPPED] unknown component class (requires CONFIG_DRM_XE_DEBUG)
[06:15:55] [SKIPPED] unknown system component (requires CONFIG_DRM_XE_DEBUG)
[06:15:55] [SKIPPED] unknown hardware component (requires CONFIG_DRM_XE_DEBUG)
[06:15:55] [SKIPPED] unknown component and location (requires CONFIG_DRM_XE_DEBUG)
[06:15:55] ================== [SKIPPED] test_invalid ==================
[06:15:55] ===================== [PASSED] xe_log ======================
[06:15:55] ================== no_relay (3 subtests) ===================
[06:15:55] [PASSED] xe_drops_guc2pf_if_not_ready
[06:15:55] [PASSED] xe_drops_guc2vf_if_not_ready
[06:15:55] [PASSED] xe_rejects_send_if_not_ready
[06:15:55] ==================== [PASSED] no_relay =====================
[06:15:55] ================== pf_relay (14 subtests) ==================
[06:15:55] [PASSED] pf_rejects_guc2pf_too_short
[06:15:55] [PASSED] pf_rejects_guc2pf_too_long
[06:15:55] [PASSED] pf_rejects_guc2pf_no_payload
[06:15:55] [PASSED] pf_fails_no_payload
[06:15:55] [PASSED] pf_fails_bad_origin
[06:15:55] [PASSED] pf_fails_bad_type
[06:15:55] [PASSED] pf_txn_reports_error
[06:15:55] [PASSED] pf_txn_sends_pf2guc
[06:15:55] [PASSED] pf_sends_pf2guc
[06:15:55] [SKIPPED] pf_loopback_nop (requires CONFIG_DRM_XE_DEBUG_SRIOV)
[06:15:55] [SKIPPED] pf_loopback_echo (requires CONFIG_DRM_XE_DEBUG_SRIOV)
[06:15:55] [SKIPPED] pf_loopback_fail (requires CONFIG_DRM_XE_DEBUG_SRIOV)
[06:15:55] [SKIPPED] pf_loopback_busy (requires CONFIG_DRM_XE_DEBUG_SRIOV)
[06:15:55] [SKIPPED] pf_loopback_retry (requires CONFIG_DRM_XE_DEBUG_SRIOV)
[06:15:55] ==================== [PASSED] pf_relay =====================
[06:15:55] ================== vf_relay (3 subtests) ===================
[06:15:55] [PASSED] vf_rejects_guc2vf_too_short
[06:15:55] [PASSED] vf_rejects_guc2vf_too_long
[06:15:55] [PASSED] vf_rejects_guc2vf_no_payload
[06:15:55] ==================== [PASSED] vf_relay =====================
[06:15:55] ================ pf_gt_config (9 subtests) =================
[06:15:55] [PASSED] fair_contexts_1vf
[06:15:55] [PASSED] fair_doorbells_1vf
[06:15:55] [PASSED] fair_ggtt_1vf
[06:15:55] ====================== fair_vram_1vf ======================
[06:15:55] [PASSED] 3.50 GiB
[06:15:55] [PASSED] 11.5 GiB
[06:15:55] [PASSED] 15.5 GiB
[06:15:55] [PASSED] 31.5 GiB
[06:15:55] [PASSED] 63.5 GiB
[06:15:55] [PASSED] 1.91 GiB
[06:15:55] ================== [PASSED] fair_vram_1vf ==================
[06:15:55] ================ fair_vram_1vf_admin_only =================
[06:15:55] [PASSED] 3.50 GiB
[06:15:55] [PASSED] 11.5 GiB
[06:15:55] [PASSED] 15.5 GiB
[06:15:55] [PASSED] 31.5 GiB
[06:15:55] [PASSED] 63.5 GiB
[06:15:55] [PASSED] 1.91 GiB
[06:15:55] ============ [PASSED] fair_vram_1vf_admin_only =============
[06:15:55] ====================== fair_contexts ======================
[06:15:55] [PASSED] 1 VF
[06:15:55] [PASSED] 2 VFs
[06:15:55] [PASSED] 3 VFs
[06:15:55] [PASSED] 4 VFs
[06:15:55] [PASSED] 5 VFs
[06:15:55] [PASSED] 6 VFs
[06:15:55] [PASSED] 7 VFs
[06:15:55] [PASSED] 8 VFs
[06:15:55] [PASSED] 9 VFs
[06:15:55] [PASSED] 10 VFs
[06:15:55] [PASSED] 11 VFs
[06:15:55] [PASSED] 12 VFs
[06:15:55] [PASSED] 13 VFs
[06:15:55] [PASSED] 14 VFs
[06:15:55] [PASSED] 15 VFs
[06:15:55] [PASSED] 16 VFs
[06:15:55] [PASSED] 17 VFs
[06:15:55] [PASSED] 18 VFs
[06:15:55] [PASSED] 19 VFs
[06:15:55] [PASSED] 20 VFs
[06:15:55] [PASSED] 21 VFs
[06:15:55] [PASSED] 22 VFs
[06:15:55] [PASSED] 23 VFs
[06:15:55] [PASSED] 24 VFs
[06:15:55] [PASSED] 25 VFs
[06:15:55] [PASSED] 26 VFs
[06:15:55] [PASSED] 27 VFs
[06:15:55] [PASSED] 28 VFs
[06:15:55] [PASSED] 29 VFs
[06:15:55] [PASSED] 30 VFs
[06:15:55] [PASSED] 31 VFs
[06:15:55] [PASSED] 32 VFs
[06:15:55] [PASSED] 33 VFs
[06:15:55] [PASSED] 34 VFs
[06:15:55] [PASSED] 35 VFs
[06:15:55] [PASSED] 36 VFs
[06:15:55] [PASSED] 37 VFs
[06:15:55] [PASSED] 38 VFs
[06:15:55] [PASSED] 39 VFs
[06:15:55] [PASSED] 40 VFs
[06:15:55] [PASSED] 41 VFs
[06:15:55] [PASSED] 42 VFs
[06:15:55] [PASSED] 43 VFs
[06:15:55] [PASSED] 44 VFs
[06:15:55] [PASSED] 45 VFs
[06:15:55] [PASSED] 46 VFs
[06:15:55] [PASSED] 47 VFs
[06:15:55] [PASSED] 48 VFs
[06:15:55] [PASSED] 49 VFs
[06:15:55] [PASSED] 50 VFs
[06:15:55] [PASSED] 51 VFs
[06:15:55] [PASSED] 52 VFs
[06:15:55] [PASSED] 53 VFs
[06:15:55] [PASSED] 54 VFs
[06:15:55] [PASSED] 55 VFs
[06:15:55] [PASSED] 56 VFs
[06:15:55] [PASSED] 57 VFs
[06:15:55] [PASSED] 58 VFs
[06:15:55] [PASSED] 59 VFs
[06:15:55] [PASSED] 60 VFs
[06:15:55] [PASSED] 61 VFs
[06:15:55] [PASSED] 62 VFs
[06:15:55] [PASSED] 63 VFs
[06:15:55] ================== [PASSED] fair_contexts ==================
[06:15:55] ===================== fair_doorbells ======================
[06:15:55] [PASSED] 1 VF
[06:15:55] [PASSED] 2 VFs
[06:15:55] [PASSED] 3 VFs
[06:15:55] [PASSED] 4 VFs
[06:15:55] [PASSED] 5 VFs
[06:15:55] [PASSED] 6 VFs
[06:15:55] [PASSED] 7 VFs
[06:15:55] [PASSED] 8 VFs
[06:15:55] [PASSED] 9 VFs
[06:15:55] [PASSED] 10 VFs
[06:15:55] [PASSED] 11 VFs
[06:15:55] [PASSED] 12 VFs
[06:15:55] [PASSED] 13 VFs
[06:15:55] [PASSED] 14 VFs
[06:15:55] [PASSED] 15 VFs
[06:15:55] [PASSED] 16 VFs
[06:15:55] [PASSED] 17 VFs
[06:15:55] [PASSED] 18 VFs
[06:15:55] [PASSED] 19 VFs
[06:15:55] [PASSED] 20 VFs
[06:15:55] [PASSED] 21 VFs
[06:15:55] [PASSED] 22 VFs
[06:15:55] [PASSED] 23 VFs
[06:15:55] [PASSED] 24 VFs
[06:15:55] [PASSED] 25 VFs
[06:15:55] [PASSED] 26 VFs
[06:15:55] [PASSED] 27 VFs
[06:15:55] [PASSED] 28 VFs
[06:15:55] [PASSED] 29 VFs
[06:15:55] [PASSED] 30 VFs
[06:15:55] [PASSED] 31 VFs
[06:15:55] [PASSED] 32 VFs
[06:15:55] [PASSED] 33 VFs
[06:15:55] [PASSED] 34 VFs
[06:15:55] [PASSED] 35 VFs
[06:15:55] [PASSED] 36 VFs
[06:15:55] [PASSED] 37 VFs
[06:15:55] [PASSED] 38 VFs
[06:15:55] [PASSED] 39 VFs
[06:15:55] [PASSED] 40 VFs
[06:15:55] [PASSED] 41 VFs
[06:15:55] [PASSED] 42 VFs
[06:15:55] [PASSED] 43 VFs
[06:15:55] [PASSED] 44 VFs
[06:15:55] [PASSED] 45 VFs
[06:15:55] [PASSED] 46 VFs
[06:15:55] [PASSED] 47 VFs
[06:15:55] [PASSED] 48 VFs
[06:15:55] [PASSED] 49 VFs
[06:15:55] [PASSED] 50 VFs
[06:15:55] [PASSED] 51 VFs
[06:15:55] [PASSED] 52 VFs
[06:15:55] [PASSED] 53 VFs
[06:15:55] [PASSED] 54 VFs
[06:15:55] [PASSED] 55 VFs
[06:15:55] [PASSED] 56 VFs
[06:15:55] [PASSED] 57 VFs
[06:15:55] [PASSED] 58 VFs
[06:15:55] [PASSED] 59 VFs
[06:15:55] [PASSED] 60 VFs
[06:15:55] [PASSED] 61 VFs
[06:15:55] [PASSED] 62 VFs
[06:15:55] [PASSED] 63 VFs
[06:15:55] ================= [PASSED] fair_doorbells ==================
[06:15:55] ======================== fair_ggtt ========================
[06:15:55] [PASSED] 1 VF
[06:15:55] [PASSED] 2 VFs
[06:15:55] [PASSED] 3 VFs
[06:15:55] [PASSED] 4 VFs
[06:15:55] [PASSED] 5 VFs
[06:15:55] [PASSED] 6 VFs
[06:15:55] [PASSED] 7 VFs
[06:15:55] [PASSED] 8 VFs
[06:15:55] [PASSED] 9 VFs
[06:15:55] [PASSED] 10 VFs
[06:15:55] [PASSED] 11 VFs
[06:15:55] [PASSED] 12 VFs
[06:15:55] [PASSED] 13 VFs
[06:15:55] [PASSED] 14 VFs
[06:15:55] [PASSED] 15 VFs
[06:15:55] [PASSED] 16 VFs
[06:15:55] [PASSED] 17 VFs
[06:15:55] [PASSED] 18 VFs
[06:15:55] [PASSED] 19 VFs
[06:15:55] [PASSED] 20 VFs
[06:15:55] [PASSED] 21 VFs
[06:15:55] [PASSED] 22 VFs
[06:15:55] [PASSED] 23 VFs
[06:15:55] [PASSED] 24 VFs
[06:15:55] [PASSED] 25 VFs
[06:15:55] [PASSED] 26 VFs
[06:15:55] [PASSED] 27 VFs
[06:15:55] [PASSED] 28 VFs
[06:15:55] [PASSED] 29 VFs
[06:15:55] [PASSED] 30 VFs
[06:15:55] [PASSED] 31 VFs
[06:15:55] [PASSED] 32 VFs
[06:15:55] [PASSED] 33 VFs
[06:15:55] [PASSED] 34 VFs
[06:15:55] [PASSED] 35 VFs
[06:15:55] [PASSED] 36 VFs
[06:15:55] [PASSED] 37 VFs
[06:15:55] [PASSED] 38 VFs
[06:15:55] [PASSED] 39 VFs
[06:15:55] [PASSED] 40 VFs
[06:15:55] [PASSED] 41 VFs
[06:15:55] [PASSED] 42 VFs
[06:15:55] [PASSED] 43 VFs
[06:15:55] [PASSED] 44 VFs
[06:15:55] [PASSED] 45 VFs
[06:15:55] [PASSED] 46 VFs
[06:15:55] [PASSED] 47 VFs
[06:15:55] [PASSED] 48 VFs
[06:15:55] [PASSED] 49 VFs
[06:15:55] [PASSED] 50 VFs
[06:15:55] [PASSED] 51 VFs
[06:15:55] [PASSED] 52 VFs
[06:15:55] [PASSED] 53 VFs
[06:15:55] [PASSED] 54 VFs
[06:15:55] [PASSED] 55 VFs
[06:15:55] [PASSED] 56 VFs
[06:15:55] [PASSED] 57 VFs
[06:15:55] [PASSED] 58 VFs
[06:15:55] [PASSED] 59 VFs
[06:15:55] [PASSED] 60 VFs
[06:15:55] [PASSED] 61 VFs
[06:15:55] [PASSED] 62 VFs
[06:15:55] [PASSED] 63 VFs
[06:15:55] ==================== [PASSED] fair_ggtt ====================
[06:15:55] ======================== fair_vram ========================
[06:15:55] [PASSED] 1 VF
[06:15:55] [PASSED] 2 VFs
[06:15:55] [PASSED] 3 VFs
[06:15:55] [PASSED] 4 VFs
[06:15:55] [PASSED] 5 VFs
[06:15:55] [PASSED] 6 VFs
[06:15:55] [PASSED] 7 VFs
[06:15:55] [PASSED] 8 VFs
[06:15:55] [PASSED] 9 VFs
[06:15:55] [PASSED] 10 VFs
[06:15:55] [PASSED] 11 VFs
[06:15:55] [PASSED] 12 VFs
[06:15:55] [PASSED] 13 VFs
[06:15:55] [PASSED] 14 VFs
[06:15:55] [PASSED] 15 VFs
[06:15:55] [PASSED] 16 VFs
[06:15:55] [PASSED] 17 VFs
[06:15:55] [PASSED] 18 VFs
[06:15:55] [PASSED] 19 VFs
[06:15:55] [PASSED] 20 VFs
[06:15:55] [PASSED] 21 VFs
[06:15:55] [PASSED] 22 VFs
[06:15:55] [PASSED] 23 VFs
[06:15:55] [PASSED] 24 VFs
[06:15:55] [PASSED] 25 VFs
[06:15:55] [PASSED] 26 VFs
[06:15:55] [PASSED] 27 VFs
[06:15:55] [PASSED] 28 VFs
[06:15:55] [PASSED] 29 VFs
[06:15:55] [PASSED] 30 VFs
[06:15:55] [PASSED] 31 VFs
[06:15:55] [PASSED] 32 VFs
[06:15:55] [PASSED] 33 VFs
[06:15:55] [PASSED] 34 VFs
[06:15:55] [PASSED] 35 VFs
[06:15:55] [PASSED] 36 VFs
[06:15:55] [PASSED] 37 VFs
[06:15:55] [PASSED] 38 VFs
[06:15:55] [PASSED] 39 VFs
[06:15:55] [PASSED] 40 VFs
[06:15:55] [PASSED] 41 VFs
[06:15:55] [PASSED] 42 VFs
[06:15:55] [PASSED] 43 VFs
[06:15:55] [PASSED] 44 VFs
[06:15:55] [PASSED] 45 VFs
[06:15:55] [PASSED] 46 VFs
[06:15:55] [PASSED] 47 VFs
[06:15:55] [PASSED] 48 VFs
[06:15:55] [PASSED] 49 VFs
[06:15:55] [PASSED] 50 VFs
[06:15:55] [PASSED] 51 VFs
[06:15:55] [PASSED] 52 VFs
[06:15:55] [PASSED] 53 VFs
[06:15:55] [PASSED] 54 VFs
[06:15:55] [PASSED] 55 VFs
[06:15:55] [PASSED] 56 VFs
[06:15:55] [PASSED] 57 VFs
[06:15:55] [PASSED] 58 VFs
[06:15:55] [PASSED] 59 VFs
[06:15:55] [PASSED] 60 VFs
[06:15:55] [PASSED] 61 VFs
[06:15:55] [PASSED] 62 VFs
[06:15:55] [PASSED] 63 VFs
[06:15:55] ==================== [PASSED] fair_vram ====================
[06:15:55] ================== [PASSED] pf_gt_config ===================
[06:15:55] ===================== lmtt (1 subtest) =====================
[06:15:55] ======================== test_ops =========================
[06:15:55] [PASSED] 2-level
[06:15:55] [PASSED] multi-level
[06:15:55] ==================== [PASSED] test_ops =====================
[06:15:55] ====================== [PASSED] lmtt =======================
[06:15:55] ================= sriov_packet (1 subtest) =================
[06:15:55] [PASSED] test_descriptor_init
[06:15:55] ================== [PASSED] sriov_packet ===================
[06:15:55] ================= pf_service (11 subtests) =================
[06:15:55] [PASSED] pf_negotiate_any
[06:15:55] [PASSED] pf_negotiate_base_match
[06:15:55] [PASSED] pf_negotiate_base_newer
[06:15:55] [PASSED] pf_negotiate_base_next
[06:15:55] [SKIPPED] pf_negotiate_base_older (no older minor)
[06:15:55] [PASSED] pf_negotiate_base_prev
[06:15:55] [PASSED] pf_negotiate_latest_match
[06:15:55] [PASSED] pf_negotiate_latest_newer
[06:15:55] [PASSED] pf_negotiate_latest_next
[06:15:55] [SKIPPED] pf_negotiate_latest_older (no older minor)
[06:15:55] [SKIPPED] pf_negotiate_latest_prev (no prev major)
[06:15:55] =================== [PASSED] pf_service ====================
[06:15:55] ================= xe_guc_g2g (2 subtests) ==================
[06:15:55] ============== xe_live_guc_g2g_kunit_default ==============
[06:15:55] ========= [SKIPPED] xe_live_guc_g2g_kunit_default ==========
[06:15:55] ============== xe_live_guc_g2g_kunit_allmem ===============
[06:15:55] ========== [SKIPPED] xe_live_guc_g2g_kunit_allmem ==========
[06:15:55] =================== [SKIPPED] xe_guc_g2g ===================
[06:15:55] =================== xe_mocs (2 subtests) ===================
[06:15:55] ================ xe_live_mocs_kernel_kunit ================
[06:15:55] =========== [SKIPPED] xe_live_mocs_kernel_kunit ============
[06:15:55] ================ xe_live_mocs_reset_kunit =================
[06:15:55] ============ [SKIPPED] xe_live_mocs_reset_kunit ============
[06:15:55] ==================== [SKIPPED] xe_mocs =====================
[06:15:55] ================= xe_migrate (3 subtests) ==================
[06:15:55] ================= xe_migrate_sanity_kunit =================
[06:15:55] ============ [SKIPPED] xe_migrate_sanity_kunit =============
[06:15:55] ================== xe_validate_ccs_kunit ==================
[06:15:55] ============= [SKIPPED] xe_validate_ccs_kunit ==============
[06:15:55] ============= xe_migrate_access_memory_kunit ==============
[06:15:55] ========= [SKIPPED] xe_migrate_access_memory_kunit =========
[06:15:55] =================== [SKIPPED] xe_migrate ===================
[06:15:55] ================== xe_dma_buf (1 subtest) ==================
[06:15:55] ==================== xe_dma_buf_kunit =====================
[06:15:55] ================ [SKIPPED] xe_dma_buf_kunit ================
[06:15:55] =================== [SKIPPED] xe_dma_buf ===================
[06:15:55] ================= xe_bo_shrink (1 subtest) =================
[06:15:55] =================== xe_bo_shrink_kunit ====================
[06:15:55] =============== [SKIPPED] xe_bo_shrink_kunit ===============
[06:15:55] ================== [SKIPPED] xe_bo_shrink ==================
[06:15:55] ==================== xe_bo (2 subtests) ====================
[06:15:55] ================== xe_ccs_migrate_kunit ===================
[06:15:55] ============== [SKIPPED] xe_ccs_migrate_kunit ==============
[06:15:55] ==================== xe_bo_evict_kunit ====================
[06:15:55] =============== [SKIPPED] xe_bo_evict_kunit ================
[06:15:55] ===================== [SKIPPED] xe_bo ======================
[06:15:55] =================== xe_any (9 subtests) ====================
[06:15:55] [PASSED] test_to_xe
[06:15:55] [PASSED] test_to_dev
[06:15:55] [PASSED] test_to_pdev
[06:15:55] [PASSED] test_to_drm
[06:15:55] [PASSED] test_if_pdev
[06:15:55] [PASSED] test_if_xe
[06:15:55] [PASSED] test_if_tile
[06:15:55] [PASSED] test_if_gt
[06:15:55] [PASSED] test_to_id
[06:15:55] ===================== [PASSED] xe_any ======================
[06:15:55] ==================== args (13 subtests) ====================
[06:15:55] [PASSED] count_args_test
[06:15:55] [PASSED] call_args_example
[06:15:55] [PASSED] call_args_test
[06:15:55] [PASSED] drop_first_arg_example
[06:15:55] [PASSED] drop_first_arg_test
[06:15:55] [PASSED] first_arg_example
[06:15:55] [PASSED] first_arg_test
[06:15:55] [PASSED] last_arg_example
[06:15:55] [PASSED] last_arg_test
[06:15:55] [PASSED] pick_arg_example
[06:15:55] [PASSED] if_args_example
[06:15:55] [PASSED] if_args_test
[06:15:55] [PASSED] sep_comma_example
[06:15:55] ====================== [PASSED] args =======================
[06:15:55] =================== xe_pci (3 subtests) ====================
[06:15:55] ==================== check_graphics_ip ====================
[06:15:55] [PASSED] 12.00 Xe_LP
[06:15:55] [PASSED] 12.10 Xe_LP+
[06:15:55] [PASSED] 12.55 Xe_HPG
[06:15:55] [PASSED] 12.60 Xe_HPC
[06:15:55] [PASSED] 12.70 Xe_LPG
[06:15:55] [PASSED] 12.71 Xe_LPG
[06:15:55] [PASSED] 12.74 Xe_LPG+
[06:15:55] [PASSED] 20.01 Xe2_HPG
[06:15:55] [PASSED] 20.02 Xe2_HPG
[06:15:55] [PASSED] 20.04 Xe2_LPG
[06:15:55] [PASSED] 30.00 Xe3_LPG
[06:15:55] [PASSED] 30.01 Xe3_LPG
[06:15:55] [PASSED] 30.03 Xe3_LPG
[06:15:55] [PASSED] 30.04 Xe3_LPG
[06:15:55] [PASSED] 30.05 Xe3_LPG
[06:15:55] [PASSED] 35.10 Xe3p_LPG
[06:15:55] [PASSED] 35.11 Xe3p_XPC
[06:15:55] ================ [PASSED] check_graphics_ip ================
[06:15:55] ===================== check_media_ip ======================
[06:15:55] [PASSED] 12.00 Xe_M
[06:15:55] [PASSED] 12.55 Xe_HPM
[06:15:55] [PASSED] 13.00 Xe_LPM+
[06:15:55] [PASSED] 13.01 Xe2_HPM
[06:15:55] [PASSED] 20.00 Xe2_LPM
[06:15:55] [PASSED] 30.00 Xe3_LPM
[06:15:55] [PASSED] 30.02 Xe3_LPM
[06:15:55] [PASSED] 35.00 Xe3p_LPM
[06:15:55] [PASSED] 35.03 Xe3p_HPM
[06:15:55] ================= [PASSED] check_media_ip ==================
[06:15:55] =================== check_platform_desc ===================
[06:15:55] [PASSED] 0x9A60 (TIGERLAKE)
[06:15:55] [PASSED] 0x9A68 (TIGERLAKE)
[06:15:55] [PASSED] 0x9A70 (TIGERLAKE)
[06:15:55] [PASSED] 0x9A40 (TIGERLAKE)
[06:15:55] [PASSED] 0x9A49 (TIGERLAKE)
[06:15:55] [PASSED] 0x9A59 (TIGERLAKE)
[06:15:55] [PASSED] 0x9A78 (TIGERLAKE)
[06:15:55] [PASSED] 0x9AC0 (TIGERLAKE)
[06:15:55] [PASSED] 0x9AC9 (TIGERLAKE)
[06:15:55] [PASSED] 0x9AD9 (TIGERLAKE)
[06:15:55] [PASSED] 0x9AF8 (TIGERLAKE)
[06:15:55] [PASSED] 0x4C80 (ROCKETLAKE)
[06:15:55] [PASSED] 0x4C8A (ROCKETLAKE)
[06:15:55] [PASSED] 0x4C8B (ROCKETLAKE)
[06:15:55] [PASSED] 0x4C8C (ROCKETLAKE)
[06:15:55] [PASSED] 0x4C90 (ROCKETLAKE)
[06:15:55] [PASSED] 0x4C9A (ROCKETLAKE)
[06:15:55] [PASSED] 0x4680 (ALDERLAKE_S)
[06:15:55] [PASSED] 0x4682 (ALDERLAKE_S)
[06:15:55] [PASSED] 0x4688 (ALDERLAKE_S)
[06:15:55] [PASSED] 0x468A (ALDERLAKE_S)
[06:15:55] [PASSED] 0x468B (ALDERLAKE_S)
[06:15:55] [PASSED] 0x4690 (ALDERLAKE_S)
[06:15:55] [PASSED] 0x4692 (ALDERLAKE_S)
[06:15:55] [PASSED] 0x4693 (ALDERLAKE_S)
[06:15:55] [PASSED] 0x46A0 (ALDERLAKE_P)
[06:15:55] [PASSED] 0x46A1 (ALDERLAKE_P)
[06:15:55] [PASSED] 0x46A2 (ALDERLAKE_P)
[06:15:55] [PASSED] 0x46A3 (ALDERLAKE_P)
[06:15:55] [PASSED] 0x46A6 (ALDERLAKE_P)
[06:15:55] [PASSED] 0x46A8 (ALDERLAKE_P)
[06:15:55] [PASSED] 0x46AA (ALDERLAKE_P)
[06:15:55] [PASSED] 0x462A (ALDERLAKE_P)
[06:15:55] [PASSED] 0x4626 (ALDERLAKE_P)
[06:15:55] [PASSED] 0x4628 (ALDERLAKE_P)
[06:15:55] [PASSED] 0x46B0 (ALDERLAKE_P)
[06:15:55] [PASSED] 0x46B1 (ALDERLAKE_P)
[06:15:55] [PASSED] 0x46B2 (ALDERLAKE_P)
[06:15:55] [PASSED] 0x46B3 (ALDERLAKE_P)
[06:15:55] [PASSED] 0x46C0 (ALDERLAKE_P)
[06:15:55] [PASSED] 0x46C1 (ALDERLAKE_P)
[06:15:55] [PASSED] 0x46C2 (ALDERLAKE_P)
[06:15:55] [PASSED] 0x46C3 (ALDERLAKE_P)
[06:15:55] [PASSED] 0x46D0 (ALDERLAKE_N)
[06:15:55] [PASSED] 0x46D1 (ALDERLAKE_N)
[06:15:55] [PASSED] 0x46D2 (ALDERLAKE_N)
[06:15:55] [PASSED] 0x46D3 (ALDERLAKE_N)
[06:15:55] [PASSED] 0x46D4 (ALDERLAKE_N)
[06:15:55] [PASSED] 0xA721 (ALDERLAKE_P)
[06:15:55] [PASSED] 0xA7A1 (ALDERLAKE_P)
[06:15:55] [PASSED] 0xA7A9 (ALDERLAKE_P)
[06:15:55] [PASSED] 0xA7AC (ALDERLAKE_P)
[06:15:55] [PASSED] 0xA7AD (ALDERLAKE_P)
[06:15:55] [PASSED] 0xA720 (ALDERLAKE_P)
[06:15:55] [PASSED] 0xA7A0 (ALDERLAKE_P)
[06:15:55] [PASSED] 0xA7A8 (ALDERLAKE_P)
[06:15:55] [PASSED] 0xA7AA (ALDERLAKE_P)
[06:15:55] [PASSED] 0xA7AB (ALDERLAKE_P)
[06:15:55] [PASSED] 0xA780 (ALDERLAKE_S)
[06:15:55] [PASSED] 0xA781 (ALDERLAKE_S)
[06:15:55] [PASSED] 0xA782 (ALDERLAKE_S)
[06:15:55] [PASSED] 0xA783 (ALDERLAKE_S)
[06:15:55] [PASSED] 0xA788 (ALDERLAKE_S)
[06:15:55] [PASSED] 0xA789 (ALDERLAKE_S)
[06:15:55] [PASSED] 0xA78A (ALDERLAKE_S)
[06:15:55] [PASSED] 0xA78B (ALDERLAKE_S)
[06:15:55] [PASSED] 0x4905 (DG1)
[06:15:55] [PASSED] 0x4906 (DG1)
[06:15:55] [PASSED] 0x4907 (DG1)
[06:15:55] [PASSED] 0x4908 (DG1)
[06:15:55] [PASSED] 0x4909 (DG1)
[06:15:55] [PASSED] 0x56C0 (DG2)
[06:15:55] [PASSED] 0x56C2 (DG2)
[06:15:55] [PASSED] 0x56C1 (DG2)
[06:15:55] [PASSED] 0x7D51 (METEORLAKE)
[06:15:55] [PASSED] 0x7DD1 (METEORLAKE)
[06:15:55] [PASSED] 0x7D41 (METEORLAKE)
[06:15:55] [PASSED] 0x7D67 (METEORLAKE)
[06:15:55] [PASSED] 0xB640 (METEORLAKE)
[06:15:55] [PASSED] 0x56A0 (DG2)
[06:15:55] [PASSED] 0x56A1 (DG2)
[06:15:55] [PASSED] 0x56A2 (DG2)
[06:15:55] [PASSED] 0x56BE (DG2)
[06:15:55] [PASSED] 0x56BF (DG2)
[06:15:55] [PASSED] 0x5690 (DG2)
[06:15:55] [PASSED] 0x5691 (DG2)
[06:15:55] [PASSED] 0x5692 (DG2)
[06:15:55] [PASSED] 0x56A5 (DG2)
[06:15:55] [PASSED] 0x56A6 (DG2)
[06:15:55] [PASSED] 0x56B0 (DG2)
[06:15:55] [PASSED] 0x56B1 (DG2)
[06:15:55] [PASSED] 0x56BA (DG2)
[06:15:55] [PASSED] 0x56BB (DG2)
[06:15:55] [PASSED] 0x56BC (DG2)
[06:15:55] [PASSED] 0x56BD (DG2)
[06:15:55] [PASSED] 0x5693 (DG2)
[06:15:55] [PASSED] 0x5694 (DG2)
[06:15:55] [PASSED] 0x5695 (DG2)
[06:15:55] [PASSED] 0x56A3 (DG2)
[06:15:55] [PASSED] 0x56A4 (DG2)
[06:15:55] [PASSED] 0x56B2 (DG2)
[06:15:55] [PASSED] 0x56B3 (DG2)
[06:15:55] [PASSED] 0x5696 (DG2)
[06:15:55] [PASSED] 0x5697 (DG2)
[06:15:55] [PASSED] 0xB69 (PVC)
[06:15:55] [PASSED] 0xB6E (PVC)
[06:15:55] [PASSED] 0xBD4 (PVC)
[06:15:55] [PASSED] 0xBD5 (PVC)
[06:15:55] [PASSED] 0xBD6 (PVC)
[06:15:55] [PASSED] 0xBD7 (PVC)
[06:15:55] [PASSED] 0xBD8 (PVC)
[06:15:55] [PASSED] 0xBD9 (PVC)
[06:15:55] [PASSED] 0xBDA (PVC)
[06:15:55] [PASSED] 0xBDB (PVC)
[06:15:55] [PASSED] 0xBE0 (PVC)
[06:15:55] [PASSED] 0xBE1 (PVC)
[06:15:55] [PASSED] 0xBE5 (PVC)
[06:15:55] [PASSED] 0x7D40 (METEORLAKE)
[06:15:55] [PASSED] 0x7D45 (METEORLAKE)
[06:15:55] [PASSED] 0x7D55 (METEORLAKE)
[06:15:55] [PASSED] 0x7D60 (METEORLAKE)
[06:15:55] [PASSED] 0x7DD5 (METEORLAKE)
[06:15:55] [PASSED] 0x6420 (LUNARLAKE)
[06:15:55] [PASSED] 0x64A0 (LUNARLAKE)
[06:15:55] [PASSED] 0x64B0 (LUNARLAKE)
[06:15:55] [PASSED] 0xE202 (BATTLEMAGE)
[06:15:55] [PASSED] 0xE209 (BATTLEMAGE)
[06:15:55] [PASSED] 0xE20B (BATTLEMAGE)
[06:15:55] [PASSED] 0xE20C (BATTLEMAGE)
[06:15:55] [PASSED] 0xE20D (BATTLEMAGE)
[06:15:56] [PASSED] 0xE210 (BATTLEMAGE)
[06:15:56] [PASSED] 0xE211 (BATTLEMAGE)
[06:15:56] [PASSED] 0xE212 (BATTLEMAGE)
[06:15:56] [PASSED] 0xE216 (BATTLEMAGE)
[06:15:56] [PASSED] 0xE220 (BATTLEMAGE)
[06:15:56] [PASSED] 0xE221 (BATTLEMAGE)
[06:15:56] [PASSED] 0xE222 (BATTLEMAGE)
[06:15:56] [PASSED] 0xE223 (BATTLEMAGE)
[06:15:56] [PASSED] 0xB080 (PANTHERLAKE)
[06:15:56] [PASSED] 0xB081 (PANTHERLAKE)
[06:15:56] [PASSED] 0xB082 (PANTHERLAKE)
[06:15:56] [PASSED] 0xB083 (PANTHERLAKE)
[06:15:56] [PASSED] 0xB084 (PANTHERLAKE)
[06:15:56] [PASSED] 0xB085 (PANTHERLAKE)
[06:15:56] [PASSED] 0xB086 (PANTHERLAKE)
[06:15:56] [PASSED] 0xB087 (PANTHERLAKE)
[06:15:56] [PASSED] 0xB08F (PANTHERLAKE)
[06:15:56] [PASSED] 0xB090 (PANTHERLAKE)
[06:15:56] [PASSED] 0xB0A0 (PANTHERLAKE)
[06:15:56] [PASSED] 0xB0A1 (PANTHERLAKE)
[06:15:56] [PASSED] 0xB0B0 (PANTHERLAKE)
[06:15:56] [PASSED] 0xFD80 (PANTHERLAKE)
[06:15:56] [PASSED] 0xFD81 (PANTHERLAKE)
[06:15:56] [PASSED] 0xD740 (NOVALAKE_S)
[06:15:56] [PASSED] 0xD741 (NOVALAKE_S)
[06:15:56] [PASSED] 0xD742 (NOVALAKE_S)
[06:15:56] [PASSED] 0xD743 (NOVALAKE_S)
[06:15:56] [PASSED] 0xD745 (NOVALAKE_S)
[06:15:56] [PASSED] 0xD74A (NOVALAKE_S)
[06:15:56] [PASSED] 0xD74B (NOVALAKE_S)
[06:15:56] [PASSED] 0x674C (CRESCENTISLAND)
[06:15:56] [PASSED] 0x674D (CRESCENTISLAND)
[06:15:56] [PASSED] 0x674E (CRESCENTISLAND)
[06:15:56] [PASSED] 0x674F (CRESCENTISLAND)
[06:15:56] [PASSED] 0x6750 (CRESCENTISLAND)
[06:15:56] [PASSED] 0x6751 (CRESCENTISLAND)
[06:15:56] [PASSED] 0xD750 (NOVALAKE_P)
[06:15:56] [PASSED] 0xD751 (NOVALAKE_P)
[06:15:56] [PASSED] 0xD752 (NOVALAKE_P)
[06:15:56] [PASSED] 0xD753 (NOVALAKE_P)
[06:15:56] [PASSED] 0xD754 (NOVALAKE_P)
[06:15:56] [PASSED] 0xD755 (NOVALAKE_P)
[06:15:56] [PASSED] 0xD756 (NOVALAKE_P)
[06:15:56] [PASSED] 0xD757 (NOVALAKE_P)
[06:15:56] [PASSED] 0xD75F (NOVALAKE_P)
[06:15:56] =============== [PASSED] check_platform_desc ===============
[06:15:56] ===================== [PASSED] xe_pci ======================
[06:15:56] ============= xe_rtp_tables_test (5 subtests) ==============
[06:15:56] ================== xe_rtp_table_gt_test ===================
[06:15:56] [PASSED] gt_was/14011060649
[06:15:56] [PASSED] gt_was/14011059788
[06:15:56] [PASSED] gt_was/14015795083
[06:15:56] [PASSED] gt_was/16021867713
[06:15:56] [PASSED] gt_was/14019449301
[06:15:56] [PASSED] gt_was/16028005424
[06:15:56] [PASSED] gt_was/14026578760
[06:15:56] [PASSED] gt_was/1409420604
[06:15:56] [PASSED] gt_was/1408615072
[06:15:56] [PASSED] gt_was/22010523718
[06:15:56] [PASSED] gt_was/14011006942
[06:15:56] [PASSED] gt_was/14014830051
[06:15:56] [PASSED] gt_was/18018781329
[06:15:56] [PASSED] gt_was/1509235366
[06:15:56] [PASSED] gt_was/18018781329
[06:15:56] [PASSED] gt_was/16016694945
[06:15:56] [PASSED] gt_was/14018575942
[06:15:56] [PASSED] gt_was/22016670082
[06:15:56] [PASSED] gt_was/22016670082
[06:15:56] [PASSED] gt_was/14017421178
[06:15:56] [PASSED] gt_was/16025250150
[06:15:56] [PASSED] gt_was/14021871409
[06:15:56] [PASSED] gt_was/16021865536
[06:15:56] [PASSED] gt_was/14021486841
[06:15:56] [PASSED] gt_was/14025160223
[06:15:56] [PASSED] gt_was/14026144927, 16029437861, 14026127056
[06:15:56] [PASSED] gt_was/14025635424
[06:15:56] [PASSED] gt_was/16028005424
[06:15:56] ============== [PASSED] xe_rtp_table_gt_test ===============
[06:15:56] ================== xe_rtp_table_gt_test ===================
[06:15:56] [PASSED] gt_tunings/Tuning: Blend Fill Caching Optimization Disable
[06:15:56] [PASSED] gt_tunings/Tuning: 32B Access Enable
[06:15:56] [PASSED] gt_tunings/Tuning: L3 cache
[06:15:56] [PASSED] gt_tunings/Tuning: L3 cache - media
[06:15:56] [PASSED] gt_tunings/Tuning: Compression Overfetch
[06:15:56] [PASSED] gt_tunings/Tuning: Compression Overfetch - media
[06:15:56] [PASSED] gt_tunings/Tuning: Enable compressible partial write overfetch in L3
[06:15:56] [PASSED] gt_tunings/Tuning: Enable compressible partial write overfetch in L3 - media
[06:15:56] [PASSED] gt_tunings/Tuning: L2 Overfetch Compressible Only
[06:15:56] [PASSED] gt_tunings/Tuning: L2 Overfetch Compressible Only - media
[06:15:56] [PASSED] gt_tunings/Tuning: Stateless compression control
[06:15:56] [PASSED] gt_tunings/Tuning: Stateless compression control - media
[06:15:56] [PASSED] gt_tunings/Tuning: L3 RW flush all Cache
[06:15:56] [PASSED] gt_tunings/Tuning: L3 RW flush all cache - media
[06:15:56] [PASSED] gt_tunings/Tuning: Set STLB Bank Hash Mode to 4KB
[06:15:56] [PASSED] gt_tunings/Tuning: Force All Non-Compressible Memory Reads to be 256B Overfetches
[06:15:56] ============== [PASSED] xe_rtp_table_gt_test ===============
[06:15:56] ================== xe_rtp_table_oob_test ==================
[06:15:56] [PASSED] oob_was/1607983814
[06:15:56] [PASSED] oob_was/16010904313
[06:15:56] [PASSED] oob_was/18022495364
[06:15:56] [PASSED] oob_was/22012773006
[06:15:56] [PASSED] oob_was/14014475959
[06:15:56] [PASSED] oob_was/22011391025
[06:15:56] [PASSED] oob_was/22012727170
[06:15:56] [PASSED] oob_was/22012727685
[06:15:56] [PASSED] oob_was/22016596838
[06:15:56] [PASSED] oob_was/18020744125
[06:15:56] [PASSED] oob_was/1409600907
[06:15:56] [PASSED] oob_was/22014953428
[06:15:56] [PASSED] oob_was/16017236439
[06:15:56] [PASSED] oob_was/14019821291
[06:15:56] [PASSED] oob_was/14015076503
[06:15:56] [PASSED] oob_was/22016122933
[06:15:56] [PASSED] oob_was/14018913170
[06:15:56] [PASSED] oob_was/14018094691
[06:15:56] [PASSED] oob_was/18024947630
[06:15:56] [PASSED] oob_was/16022287689
[06:15:56] [PASSED] oob_was/13011645652
[06:15:56] [PASSED] oob_was/14022293748
[06:15:56] [PASSED] oob_was/22019794406
[06:15:56] [PASSED] oob_was/22019338487
[06:15:56] [PASSED] oob_was/16023588340
[06:15:56] [PASSED] oob_was/14019789679
[06:15:56] [PASSED] oob_was/14022866841
[06:15:56] [PASSED] oob_was/16021333562
[06:15:56] [PASSED] oob_was/14016712196
[06:15:56] [PASSED] oob_was/14015568240
[06:15:56] [PASSED] oob_was/18013179988
[06:15:56] [PASSED] oob_was/1508761755
[06:15:56] [PASSED] oob_was/16023105232
[06:15:56] [PASSED] oob_was/16026508708
[06:15:56] [PASSED] oob_was/14020001231
[06:15:56] [PASSED] oob_was/16023683509
[06:15:56] [PASSED] oob_was/14025515070
[06:15:56] [PASSED] oob_was/15015404425_disable
[06:15:56] [PASSED] oob_was/16026007364
[06:15:56] [PASSED] oob_was/14020316580
[06:15:56] [PASSED] oob_was/14025883347
[06:15:56] [PASSED] oob_was/16029380221
[06:15:56] [PASSED] oob_was/22022079272
[06:15:56] [PASSED] oob_was/16029897822
[06:15:56] [PASSED] oob_was/14027054324
[06:15:56] [PASSED] oob_was/14025941587
[06:15:56] [PASSED] oob_was/16030224309
[06:15:56] ============== [PASSED] xe_rtp_table_oob_test ==============
[06:15:56] ================ xe_rtp_table_dev_oob_test ================
[06:15:56] [PASSED] device_oob_was/22010954014
[06:15:56] [PASSED] device_oob_was/15015404425
[06:15:56] [PASSED] device_oob_was/22019338487_display
[06:15:56] [PASSED] device_oob_was/14022085890
[06:15:56] [PASSED] device_oob_was/14026539277
[06:15:56] [PASSED] device_oob_was/14026633728
[06:15:56] [PASSED] device_oob_was/14026746987
[06:15:56] [PASSED] device_oob_was/14026779378
[06:15:56] ============ [PASSED] xe_rtp_table_dev_oob_test ============
[06:15:56] ========== xe_rtp_table_missing_upper_bound_test ==========
[06:15:56] [PASSED] register_whitelist/WaAllowPMDepthAndInvocationCountAccessFromUMD, 1408556865
[06:15:56] [PASSED] register_whitelist/1508744258, 14012131227, 1808121037
[06:15:56] [PASSED] register_whitelist/1806527549
[06:15:56] [PASSED] register_whitelist/allow_read_ctx_timestamp
[06:15:56] [PASSED] register_whitelist/allow_read_queue_timestamp
[06:15:56] [PASSED] register_whitelist/16014440446
[06:15:56] [PASSED] register_whitelist/16017236439
[06:15:56] [PASSED] register_whitelist/16020183090
[06:15:56] [PASSED] register_whitelist/14024997852
[06:15:56] [PASSED] register_whitelist/14024997852
[06:15:56] ====== [PASSED] xe_rtp_table_missing_upper_bound_test ======
[06:15:56] =============== [PASSED] xe_rtp_tables_test ================
[06:15:56] =================== xe_rtp (3 subtests) ====================
[06:15:56] =================== xe_rtp_rules_tests ====================
[06:15:56] [PASSED] no
[06:15:56] [PASSED] yes
[06:15:56] [PASSED] no-and-no
[06:15:56] [PASSED] no-and-yes
[06:15:56] [PASSED] yes-and-no
[06:15:56] [PASSED] yes-and-yes
[06:15:56] [PASSED] no-or-no
[06:15:56] [PASSED] no-or-yes
[06:15:56] [PASSED] yes-or-no
[06:15:56] [PASSED] yes-or-yes
[06:15:56] [PASSED] no-yes-or-yes-no
[06:15:56] [PASSED] no-yes-or-yes-yes
[06:15:56] [PASSED] yes-yes-or-no-yes
[06:15:56] [PASSED] yes-yes-or-yes-yes
[06:15:56] [PASSED] no-no-or-yes-or-no
[06:15:56] [PASSED] or
[06:15:56] [PASSED] or-yes
[06:15:56] [PASSED] or-no
[06:15:56] [PASSED] yes-or
[06:15:56] [PASSED] no-or
[06:15:56] [PASSED] no-or-or-yes
[06:15:56] [PASSED] yes-or-or-no
[06:15:56] [PASSED] no-or-or-no
[06:15:56] [PASSED] missing-context-engine-class
[06:15:56] [PASSED] missing-context-engine-class-or-yes
[06:15:56] [PASSED] missing-context-engine-class-or-or-yes
[06:15:56] =============== [PASSED] xe_rtp_rules_tests ================
[06:15:56] =============== xe_rtp_process_to_sr_tests ================
[06:15:56] [PASSED] coalesce-same-reg
[06:15:56] [PASSED] coalesce-same-reg-literal-and-func
[06:15:56] [PASSED] no-match-no-add
[06:15:56] [PASSED] two-regs-two-entries
[06:15:56] [PASSED] clr-one-set-other
[06:15:56] [PASSED] set-field
[06:15:56] [PASSED] conflict-duplicate
[06:15:56] [PASSED] conflict-not-disjoint
[06:15:56] [PASSED] conflict-not-disjoint-literal-and-func
[06:15:56] [PASSED] conflict-reg-type
[06:15:56] [PASSED] bad-mcr-reg-forced-to-regular
[06:15:56] [PASSED] bad-regular-reg-forced-to-mcr
[06:15:56] =========== [PASSED] xe_rtp_process_to_sr_tests ============
[06:15:56] ================== xe_rtp_process_tests ===================
[06:15:56] [PASSED] active1
[06:15:56] [PASSED] active2
[06:15:56] [PASSED] active-inactive
[06:15:56] [PASSED] inactive-active
[06:15:56] [PASSED] inactive-active-inactive
[06:15:56] [PASSED] inactive-inactive-inactive
[06:15:56] ============== [PASSED] xe_rtp_process_tests ===============
[06:15:56] ===================== [PASSED] xe_rtp ======================
[06:15:56] ==================== xe_wa (1 subtest) =====================
[06:15:56] ======================== xe_wa_gt =========================
[06:15:56] [PASSED] TIGERLAKE B0
[06:15:56] [PASSED] DG1 A0
[06:15:56] [PASSED] DG1 B0
[06:15:56] [PASSED] ALDERLAKE_S A0
[06:15:56] [PASSED] ALDERLAKE_S B0
[06:15:56] [PASSED] ALDERLAKE_S C0
[06:15:56] [PASSED] ALDERLAKE_S D0
[06:15:56] [PASSED] ALDERLAKE_P A0
[06:15:56] [PASSED] ALDERLAKE_P B0
[06:15:56] [PASSED] ALDERLAKE_P C0
[06:15:56] [PASSED] ALDERLAKE_S RPLS D0
[06:15:56] [PASSED] ALDERLAKE_P RPLU E0
[06:15:56] [PASSED] DG2 G10 C0
[06:15:56] [PASSED] DG2 G11 B1
[06:15:56] [PASSED] DG2 G12 A1
[06:15:56] [PASSED] METEORLAKE 12.70(Xe_LPG) A0 13.00(Xe_LPM+) A0
[06:15:56] [PASSED] METEORLAKE 12.71(Xe_LPG) A0 13.00(Xe_LPM+) A0
[06:15:56] [PASSED] METEORLAKE 12.74(Xe_LPG+) A0 13.00(Xe_LPM+) A0
[06:15:56] [PASSED] LUNARLAKE 20.04(Xe2_LPG) A0 20.00(Xe2_LPM) A0
[06:15:56] [PASSED] LUNARLAKE 20.04(Xe2_LPG) B0 20.00(Xe2_LPM) A0
[06:15:56] [PASSED] BATTLEMAGE 20.01(Xe2_HPG) A0 13.01(Xe2_HPM) A1
[06:15:56] [PASSED] PANTHERLAKE 30.00(Xe3_LPG) A0 30.00(Xe3_LPM) A0
[06:15:56] ==================== [PASSED] xe_wa_gt =====================
[06:15:56] ====================== [PASSED] xe_wa ======================
[06:15:56] ============================================================
[06:15:56] Testing complete. Ran 838 tests: passed: 809, skipped: 29
[06:15:56] Elapsed time: 41.498s total, 1.896s configuring, 38.837s building, 0.726s running
+ for kcfg in "${kunitconfigs[@]}"
+ [[ ! -f /kernel/drivers/gpu/drm/tests/.kunitconfig ]]
+ /kernel/tools/testing/kunit/kunit.py run --kunitconfig /kernel/drivers/gpu/drm/tests/.kunitconfig
[06:15:56] Configuring KUnit Kernel ...
Regenerating .config ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
[06:15:58] Building KUnit Kernel ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
Building with:
$ make all compile_commands.json scripts_gdb ARCH=um O=.kunit --jobs=48
[06:16:22] Starting KUnit Kernel (1/1)...
[06:16:22] ============================================================
Running tests with:
$ .kunit/linux kunit.enable=1 mem=1G console=tty kunit_shutdown=halt
[06:16:23] ============ drm_test_pick_cmdline (2 subtests) ============
[06:16:23] [PASSED] drm_test_pick_cmdline_res_1920_1080_60
[06:16:23] =============== drm_test_pick_cmdline_named ===============
[06:16:23] [PASSED] NTSC
[06:16:23] [PASSED] NTSC-J
[06:16:23] [PASSED] PAL
[06:16:23] [PASSED] PAL-M
[06:16:23] =========== [PASSED] drm_test_pick_cmdline_named ===========
[06:16:23] ============== [PASSED] drm_test_pick_cmdline ==============
[06:16:23] == drm_test_atomic_get_connector_for_encoder (1 subtest) ===
[06:16:23] [PASSED] drm_test_drm_atomic_get_connector_for_encoder
[06:16:23] ==== [PASSED] drm_test_atomic_get_connector_for_encoder ====
[06:16:23] =========== drm_validate_clone_mode (2 subtests) ===========
[06:16:23] ============== drm_test_check_in_clone_mode ===============
[06:16:23] [PASSED] in_clone_mode
[06:16:23] [PASSED] not_in_clone_mode
[06:16:23] ========== [PASSED] drm_test_check_in_clone_mode ===========
[06:16:23] =============== drm_test_check_valid_clones ===============
[06:16:23] [PASSED] not_in_clone_mode
[06:16:23] [PASSED] valid_clone
[06:16:23] [PASSED] invalid_clone
[06:16:23] =========== [PASSED] drm_test_check_valid_clones ===========
[06:16:23] ============= [PASSED] drm_validate_clone_mode =============
[06:16:23] ============= drm_validate_modeset (1 subtest) =============
[06:16:23] [PASSED] drm_test_check_connector_changed_modeset
[06:16:23] ============== [PASSED] drm_validate_modeset ===============
[06:16:23] ====== drm_test_bridge_get_current_state (1 subtest) =======
[06:16:23] [PASSED] drm_test_drm_bridge_get_current_state_atomic
[06:16:23] ======== [PASSED] drm_test_bridge_get_current_state ========
[06:16:23] ====== drm_test_bridge_helper_reset_crtc (3 subtests) ======
[06:16:23] [PASSED] drm_test_drm_bridge_helper_reset_crtc_atomic
[06:16:23] [PASSED] drm_test_drm_bridge_helper_reset_crtc_atomic_disabled
[06:16:23] [PASSED] drm_test_drm_bridge_helper_hdmi_output_bus_fmts
[06:16:23] ======== [PASSED] drm_test_bridge_helper_reset_crtc ========
[06:16:23] ============== drm_bridge_alloc (2 subtests) ===============
[06:16:23] [PASSED] drm_test_drm_bridge_alloc_basic
[06:16:23] [PASSED] drm_test_drm_bridge_alloc_get_put
[06:16:23] ================ [PASSED] drm_bridge_alloc =================
[06:16:23] ============= drm_bridge_bus_fmt (5 subtests) ==============
[06:16:23] [PASSED] drm_test_bridge_rgb_yuv_rgb
[06:16:23] [PASSED] drm_test_bridge_must_convert_to_yuv444
[06:16:23] [PASSED] drm_test_bridge_hdmi_auto_rgb
[06:16:23] [PASSED] drm_test_bridge_auto_first
[06:16:23] [PASSED] drm_test_bridge_rgb_yuv_no_path
[06:16:23] =============== [PASSED] drm_bridge_bus_fmt ================
[06:16:23] ============= drm_cmdline_parser (40 subtests) =============
[06:16:23] [PASSED] drm_test_cmdline_force_d_only
[06:16:23] [PASSED] drm_test_cmdline_force_D_only_dvi
[06:16:23] [PASSED] drm_test_cmdline_force_D_only_hdmi
[06:16:23] [PASSED] drm_test_cmdline_force_D_only_not_digital
[06:16:23] [PASSED] drm_test_cmdline_force_e_only
[06:16:23] [PASSED] drm_test_cmdline_res
[06:16:23] [PASSED] drm_test_cmdline_res_vesa
[06:16:23] [PASSED] drm_test_cmdline_res_vesa_rblank
[06:16:23] [PASSED] drm_test_cmdline_res_rblank
[06:16:23] [PASSED] drm_test_cmdline_res_bpp
[06:16:23] [PASSED] drm_test_cmdline_res_refresh
[06:16:23] [PASSED] drm_test_cmdline_res_bpp_refresh
[06:16:23] [PASSED] drm_test_cmdline_res_bpp_refresh_interlaced
[06:16:23] [PASSED] drm_test_cmdline_res_bpp_refresh_margins
[06:16:23] [PASSED] drm_test_cmdline_res_bpp_refresh_force_off
[06:16:23] [PASSED] drm_test_cmdline_res_bpp_refresh_force_on
[06:16:23] [PASSED] drm_test_cmdline_res_bpp_refresh_force_on_analog
[06:16:23] [PASSED] drm_test_cmdline_res_bpp_refresh_force_on_digital
[06:16:23] [PASSED] drm_test_cmdline_res_bpp_refresh_interlaced_margins_force_on
[06:16:23] [PASSED] drm_test_cmdline_res_margins_force_on
[06:16:23] [PASSED] drm_test_cmdline_res_vesa_margins
[06:16:23] [PASSED] drm_test_cmdline_name
[06:16:23] [PASSED] drm_test_cmdline_name_bpp
[06:16:23] [PASSED] drm_test_cmdline_name_option
[06:16:23] [PASSED] drm_test_cmdline_name_bpp_option
[06:16:23] [PASSED] drm_test_cmdline_rotate_0
[06:16:23] [PASSED] drm_test_cmdline_rotate_90
[06:16:23] [PASSED] drm_test_cmdline_rotate_180
[06:16:23] [PASSED] drm_test_cmdline_rotate_270
[06:16:23] [PASSED] drm_test_cmdline_hmirror
[06:16:23] [PASSED] drm_test_cmdline_vmirror
[06:16:23] [PASSED] drm_test_cmdline_margin_options
[06:16:23] [PASSED] drm_test_cmdline_multiple_options
[06:16:23] [PASSED] drm_test_cmdline_bpp_extra_and_option
[06:16:23] [PASSED] drm_test_cmdline_extra_and_option
[06:16:23] [PASSED] drm_test_cmdline_freestanding_options
[06:16:23] [PASSED] drm_test_cmdline_freestanding_force_e_and_options
[06:16:23] [PASSED] drm_test_cmdline_panel_orientation
[06:16:23] ================ drm_test_cmdline_invalid =================
[06:16:23] [PASSED] margin_only
[06:16:23] [PASSED] interlace_only
[06:16:23] [PASSED] res_missing_x
[06:16:23] [PASSED] res_missing_y
[06:16:23] [PASSED] res_bad_y
[06:16:23] [PASSED] res_missing_y_bpp
[06:16:23] [PASSED] res_bad_bpp
[06:16:23] [PASSED] res_bad_refresh
[06:16:23] [PASSED] res_bpp_refresh_force_on_off
[06:16:23] [PASSED] res_invalid_mode
[06:16:23] [PASSED] res_bpp_wrong_place_mode
[06:16:23] [PASSED] name_bpp_refresh
[06:16:23] [PASSED] name_refresh
[06:16:23] [PASSED] name_refresh_wrong_mode
[06:16:23] [PASSED] name_refresh_invalid_mode
[06:16:23] [PASSED] rotate_multiple
[06:16:23] [PASSED] rotate_invalid_val
[06:16:23] [PASSED] rotate_truncated
[06:16:23] [PASSED] invalid_option
[06:16:23] [PASSED] invalid_tv_option
[06:16:23] [PASSED] truncated_tv_option
[06:16:23] ============ [PASSED] drm_test_cmdline_invalid =============
[06:16:23] =============== drm_test_cmdline_tv_options ===============
[06:16:23] [PASSED] NTSC
[06:16:23] [PASSED] NTSC_443
[06:16:23] [PASSED] NTSC_J
[06:16:23] [PASSED] PAL
[06:16:23] [PASSED] PAL_M
[06:16:23] [PASSED] PAL_N
[06:16:23] [PASSED] SECAM
[06:16:23] [PASSED] MONO_525
[06:16:23] [PASSED] MONO_625
[06:16:23] =========== [PASSED] drm_test_cmdline_tv_options ===========
[06:16:23] =============== [PASSED] drm_cmdline_parser ================
[06:16:23] ========== drmm_connector_hdmi_init (20 subtests) ==========
[06:16:23] [PASSED] drm_test_connector_hdmi_init_valid
[06:16:23] [PASSED] drm_test_connector_hdmi_init_bpc_8
[06:16:23] [PASSED] drm_test_connector_hdmi_init_bpc_10
[06:16:23] [PASSED] drm_test_connector_hdmi_init_bpc_12
[06:16:23] [PASSED] drm_test_connector_hdmi_init_bpc_invalid
[06:16:23] [PASSED] drm_test_connector_hdmi_init_bpc_null
[06:16:23] [PASSED] drm_test_connector_hdmi_init_formats_empty
[06:16:23] [PASSED] drm_test_connector_hdmi_init_formats_no_rgb
[06:16:23] === drm_test_connector_hdmi_init_formats_yuv420_allowed ===
[06:16:23] [PASSED] supported_formats=0x9 yuv420_allowed=1
[06:16:23] [PASSED] supported_formats=0x9 yuv420_allowed=0
[06:16:23] [PASSED] supported_formats=0x5 yuv420_allowed=1
[06:16:23] [PASSED] supported_formats=0x5 yuv420_allowed=0
[06:16:23] === [PASSED] drm_test_connector_hdmi_init_formats_yuv420_allowed ===
[06:16:23] [PASSED] drm_test_connector_hdmi_init_null_ddc
[06:16:23] [PASSED] drm_test_connector_hdmi_init_null_product
[06:16:23] [PASSED] drm_test_connector_hdmi_init_null_vendor
[06:16:23] [PASSED] drm_test_connector_hdmi_init_product_length_exact
[06:16:23] [PASSED] drm_test_connector_hdmi_init_product_length_too_long
[06:16:23] [PASSED] drm_test_connector_hdmi_init_product_valid
[06:16:23] [PASSED] drm_test_connector_hdmi_init_vendor_length_exact
[06:16:23] [PASSED] drm_test_connector_hdmi_init_vendor_length_too_long
[06:16:23] [PASSED] drm_test_connector_hdmi_init_vendor_valid
[06:16:23] ========= drm_test_connector_hdmi_init_type_valid =========
[06:16:23] [PASSED] HDMI-A
[06:16:23] [PASSED] HDMI-B
[06:16:23] ===== [PASSED] drm_test_connector_hdmi_init_type_valid =====
[06:16:23] ======== drm_test_connector_hdmi_init_type_invalid ========
[06:16:23] [PASSED] Unknown
[06:16:23] [PASSED] VGA
[06:16:23] [PASSED] DVI-I
[06:16:23] [PASSED] DVI-D
[06:16:23] [PASSED] DVI-A
[06:16:23] [PASSED] Composite
[06:16:23] [PASSED] SVIDEO
[06:16:23] [PASSED] LVDS
[06:16:23] [PASSED] Component
[06:16:23] [PASSED] DIN
[06:16:23] [PASSED] DP
[06:16:23] [PASSED] TV
[06:16:23] [PASSED] eDP
[06:16:23] [PASSED] Virtual
[06:16:23] [PASSED] DSI
[06:16:23] [PASSED] DPI
[06:16:23] [PASSED] Writeback
[06:16:23] [PASSED] SPI
[06:16:23] [PASSED] USB
[06:16:23] ==== [PASSED] drm_test_connector_hdmi_init_type_invalid ====
[06:16:23] ============ [PASSED] drmm_connector_hdmi_init =============
[06:16:23] ============= drmm_connector_init (3 subtests) =============
[06:16:23] [PASSED] drm_test_drmm_connector_init
[06:16:23] [PASSED] drm_test_drmm_connector_init_null_ddc
[06:16:23] ========= drm_test_drmm_connector_init_type_valid =========
[06:16:23] [PASSED] Unknown
[06:16:23] [PASSED] VGA
[06:16:23] [PASSED] DVI-I
[06:16:23] [PASSED] DVI-D
[06:16:23] [PASSED] DVI-A
[06:16:23] [PASSED] Composite
[06:16:23] [PASSED] SVIDEO
[06:16:23] [PASSED] LVDS
[06:16:23] [PASSED] Component
[06:16:23] [PASSED] DIN
[06:16:23] [PASSED] DP
[06:16:23] [PASSED] HDMI-A
[06:16:23] [PASSED] HDMI-B
[06:16:23] [PASSED] TV
[06:16:23] [PASSED] eDP
[06:16:23] [PASSED] Virtual
[06:16:23] [PASSED] DSI
[06:16:23] [PASSED] DPI
[06:16:23] [PASSED] Writeback
[06:16:23] [PASSED] SPI
[06:16:23] [PASSED] USB
[06:16:23] ===== [PASSED] drm_test_drmm_connector_init_type_valid =====
[06:16:23] =============== [PASSED] drmm_connector_init ===============
[06:16:23] ========= drm_connector_dynamic_init (6 subtests) ==========
[06:16:23] [PASSED] drm_test_drm_connector_dynamic_init
[06:16:23] [PASSED] drm_test_drm_connector_dynamic_init_null_ddc
[06:16:23] [PASSED] drm_test_drm_connector_dynamic_init_not_added
[06:16:23] [PASSED] drm_test_drm_connector_dynamic_init_properties
[06:16:23] ===== drm_test_drm_connector_dynamic_init_type_valid ======
[06:16:23] [PASSED] Unknown
[06:16:23] [PASSED] VGA
[06:16:23] [PASSED] DVI-I
[06:16:23] [PASSED] DVI-D
[06:16:23] [PASSED] DVI-A
[06:16:23] [PASSED] Composite
[06:16:23] [PASSED] SVIDEO
[06:16:23] [PASSED] LVDS
[06:16:23] [PASSED] Component
[06:16:23] [PASSED] DIN
[06:16:23] [PASSED] DP
[06:16:23] [PASSED] HDMI-A
[06:16:23] [PASSED] HDMI-B
[06:16:23] [PASSED] TV
[06:16:23] [PASSED] eDP
[06:16:23] [PASSED] Virtual
[06:16:23] [PASSED] DSI
[06:16:23] [PASSED] DPI
[06:16:23] [PASSED] Writeback
[06:16:23] [PASSED] SPI
[06:16:23] [PASSED] USB
[06:16:23] = [PASSED] drm_test_drm_connector_dynamic_init_type_valid ==
[06:16:23] ======== drm_test_drm_connector_dynamic_init_name =========
[06:16:23] [PASSED] Unknown
[06:16:23] [PASSED] VGA
[06:16:23] [PASSED] DVI-I
[06:16:23] [PASSED] DVI-D
[06:16:23] [PASSED] DVI-A
[06:16:23] [PASSED] Composite
[06:16:23] [PASSED] SVIDEO
[06:16:23] [PASSED] LVDS
[06:16:23] [PASSED] Component
[06:16:23] [PASSED] DIN
[06:16:23] [PASSED] DP
[06:16:23] [PASSED] HDMI-A
[06:16:23] [PASSED] HDMI-B
[06:16:23] [PASSED] TV
[06:16:23] [PASSED] eDP
[06:16:23] [PASSED] Virtual
[06:16:23] [PASSED] DSI
[06:16:23] [PASSED] DPI
[06:16:23] [PASSED] Writeback
[06:16:23] [PASSED] SPI
[06:16:23] [PASSED] USB
[06:16:23] ==== [PASSED] drm_test_drm_connector_dynamic_init_name =====
[06:16:23] =========== [PASSED] drm_connector_dynamic_init ============
[06:16:23] ==== drm_connector_dynamic_register_early (4 subtests) =====
[06:16:23] [PASSED] drm_test_drm_connector_dynamic_register_early_on_list
[06:16:23] [PASSED] drm_test_drm_connector_dynamic_register_early_defer
[06:16:23] [PASSED] drm_test_drm_connector_dynamic_register_early_no_init
[06:16:23] [PASSED] drm_test_drm_connector_dynamic_register_early_no_mode_object
[06:16:23] ====== [PASSED] drm_connector_dynamic_register_early =======
[06:16:23] ======= drm_connector_dynamic_register (7 subtests) ========
[06:16:23] [PASSED] drm_test_drm_connector_dynamic_register_on_list
[06:16:23] [PASSED] drm_test_drm_connector_dynamic_register_no_defer
[06:16:23] [PASSED] drm_test_drm_connector_dynamic_register_no_init
[06:16:23] [PASSED] drm_test_drm_connector_dynamic_register_mode_object
[06:16:23] [PASSED] drm_test_drm_connector_dynamic_register_sysfs
[06:16:23] [PASSED] drm_test_drm_connector_dynamic_register_sysfs_name
[06:16:23] [PASSED] drm_test_drm_connector_dynamic_register_debugfs
[06:16:23] ========= [PASSED] drm_connector_dynamic_register ==========
[06:16:23] = drm_connector_attach_broadcast_rgb_property (2 subtests) =
[06:16:23] [PASSED] drm_test_drm_connector_attach_broadcast_rgb_property
[06:16:23] [PASSED] drm_test_drm_connector_attach_broadcast_rgb_property_hdmi_connector
[06:16:23] === [PASSED] drm_connector_attach_broadcast_rgb_property ===
[06:16:23] ========== drm_get_tv_mode_from_name (2 subtests) ==========
[06:16:23] ========== drm_test_get_tv_mode_from_name_valid ===========
[06:16:23] [PASSED] NTSC
[06:16:23] [PASSED] NTSC-443
[06:16:23] [PASSED] NTSC-J
[06:16:23] [PASSED] PAL
[06:16:23] [PASSED] PAL-M
[06:16:23] [PASSED] PAL-N
[06:16:23] [PASSED] SECAM
[06:16:23] [PASSED] Mono
[06:16:23] ====== [PASSED] drm_test_get_tv_mode_from_name_valid =======
[06:16:23] [PASSED] drm_test_get_tv_mode_from_name_truncated
[06:16:23] ============ [PASSED] drm_get_tv_mode_from_name ============
[06:16:23] = drm_test_connector_hdmi_compute_mode_clock (12 subtests) =
[06:16:23] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb
[06:16:23] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_10bpc
[06:16:23] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_10bpc_vic_1
[06:16:23] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_12bpc
[06:16:23] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_12bpc_vic_1
[06:16:23] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_double
[06:16:23] = drm_test_connector_hdmi_compute_mode_clock_yuv420_valid =
[06:16:23] [PASSED] VIC 96
[06:16:23] [PASSED] VIC 97
[06:16:23] [PASSED] VIC 101
[06:16:23] [PASSED] VIC 102
[06:16:23] [PASSED] VIC 106
[06:16:23] [PASSED] VIC 107
[06:16:23] === [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv420_valid ===
[06:16:23] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv420_10_bpc
[06:16:23] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv420_12_bpc
[06:16:23] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv422_8_bpc
[06:16:23] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv422_10_bpc
[06:16:23] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv422_12_bpc
[06:16:23] === [PASSED] drm_test_connector_hdmi_compute_mode_clock ====
[06:16:23] == drm_hdmi_connector_get_broadcast_rgb_name (2 subtests) ==
[06:16:23] === drm_test_drm_hdmi_connector_get_broadcast_rgb_name ====
[06:16:23] [PASSED] Automatic
[06:16:23] [PASSED] Full
[06:16:23] [PASSED] Limited 16:235
[06:16:23] === [PASSED] drm_test_drm_hdmi_connector_get_broadcast_rgb_name ===
[06:16:23] [PASSED] drm_test_drm_hdmi_connector_get_broadcast_rgb_name_invalid
[06:16:23] ==== [PASSED] drm_hdmi_connector_get_broadcast_rgb_name ====
[06:16:23] == drm_hdmi_connector_get_output_format_name (2 subtests) ==
[06:16:23] === drm_test_drm_hdmi_connector_get_output_format_name ====
[06:16:23] [PASSED] RGB
[06:16:23] [PASSED] YUV 4:2:0
[06:16:23] [PASSED] YUV 4:2:2
[06:16:23] [PASSED] YUV 4:4:4
[06:16:23] === [PASSED] drm_test_drm_hdmi_connector_get_output_format_name ===
[06:16:23] [PASSED] drm_test_drm_hdmi_connector_get_output_format_name_invalid
[06:16:23] ==== [PASSED] drm_hdmi_connector_get_output_format_name ====
[06:16:23] ============= drm_damage_helper (21 subtests) ==============
[06:16:23] [PASSED] drm_test_damage_iter_no_damage
[06:16:23] [PASSED] drm_test_damage_iter_no_damage_fractional_src
[06:16:23] [PASSED] drm_test_damage_iter_no_damage_src_moved
[06:16:23] [PASSED] drm_test_damage_iter_no_damage_fractional_src_moved
[06:16:23] [PASSED] drm_test_damage_iter_no_damage_not_visible
[06:16:23] [PASSED] drm_test_damage_iter_no_damage_no_crtc
[06:16:23] [PASSED] drm_test_damage_iter_no_damage_no_fb
[06:16:23] [PASSED] drm_test_damage_iter_simple_damage
[06:16:23] [PASSED] drm_test_damage_iter_single_damage
[06:16:23] [PASSED] drm_test_damage_iter_single_damage_intersect_src
[06:16:23] [PASSED] drm_test_damage_iter_single_damage_outside_src
[06:16:23] [PASSED] drm_test_damage_iter_single_damage_fractional_src
[06:16:23] [PASSED] drm_test_damage_iter_single_damage_intersect_fractional_src
[06:16:23] [PASSED] drm_test_damage_iter_single_damage_outside_fractional_src
[06:16:23] [PASSED] drm_test_damage_iter_single_damage_src_moved
[06:16:23] [PASSED] drm_test_damage_iter_single_damage_fractional_src_moved
[06:16:23] [PASSED] drm_test_damage_iter_damage
[06:16:23] [PASSED] drm_test_damage_iter_damage_one_intersect
[06:16:23] [PASSED] drm_test_damage_iter_damage_one_outside
[06:16:23] [PASSED] drm_test_damage_iter_damage_src_moved
[06:16:23] [PASSED] drm_test_damage_iter_damage_not_visible
[06:16:23] ================ [PASSED] drm_damage_helper ================
[06:16:23] ============== drm_dp_mst_helper (3 subtests) ==============
[06:16:23] ============== drm_test_dp_mst_calc_pbn_mode ==============
[06:16:23] [PASSED] Clock 154000 BPP 30 DSC disabled
[06:16:23] [PASSED] Clock 234000 BPP 30 DSC disabled
[06:16:23] [PASSED] Clock 297000 BPP 24 DSC disabled
[06:16:23] [PASSED] Clock 332880 BPP 24 DSC enabled
[06:16:23] [PASSED] Clock 324540 BPP 24 DSC enabled
[06:16:23] ========== [PASSED] drm_test_dp_mst_calc_pbn_mode ==========
[06:16:23] ============== drm_test_dp_mst_calc_pbn_div ===============
[06:16:23] [PASSED] Link rate 2000000 lane count 4
[06:16:23] [PASSED] Link rate 2000000 lane count 2
[06:16:23] [PASSED] Link rate 2000000 lane count 1
[06:16:23] [PASSED] Link rate 1350000 lane count 4
[06:16:23] [PASSED] Link rate 1350000 lane count 2
[06:16:23] [PASSED] Link rate 1350000 lane count 1
[06:16:23] [PASSED] Link rate 1000000 lane count 4
[06:16:23] [PASSED] Link rate 1000000 lane count 2
[06:16:23] [PASSED] Link rate 1000000 lane count 1
[06:16:23] [PASSED] Link rate 810000 lane count 4
[06:16:23] [PASSED] Link rate 810000 lane count 2
[06:16:23] [PASSED] Link rate 810000 lane count 1
[06:16:23] [PASSED] Link rate 540000 lane count 4
[06:16:23] [PASSED] Link rate 540000 lane count 2
[06:16:23] [PASSED] Link rate 540000 lane count 1
[06:16:23] [PASSED] Link rate 270000 lane count 4
[06:16:23] [PASSED] Link rate 270000 lane count 2
[06:16:23] [PASSED] Link rate 270000 lane count 1
[06:16:23] [PASSED] Link rate 162000 lane count 4
[06:16:23] [PASSED] Link rate 162000 lane count 2
[06:16:23] [PASSED] Link rate 162000 lane count 1
[06:16:23] ========== [PASSED] drm_test_dp_mst_calc_pbn_div ===========
[06:16:23] ========= drm_test_dp_mst_sideband_msg_req_decode =========
[06:16:23] [PASSED] DP_ENUM_PATH_RESOURCES with port number
[06:16:23] [PASSED] DP_POWER_UP_PHY with port number
[06:16:23] [PASSED] DP_POWER_DOWN_PHY with port number
[06:16:23] [PASSED] DP_ALLOCATE_PAYLOAD with SDP stream sinks
[06:16:23] [PASSED] DP_ALLOCATE_PAYLOAD with port number
[06:16:23] [PASSED] DP_ALLOCATE_PAYLOAD with VCPI
[06:16:23] [PASSED] DP_ALLOCATE_PAYLOAD with PBN
[06:16:23] [PASSED] DP_QUERY_PAYLOAD with port number
[06:16:23] [PASSED] DP_QUERY_PAYLOAD with VCPI
[06:16:23] [PASSED] DP_REMOTE_DPCD_READ with port number
[06:16:23] [PASSED] DP_REMOTE_DPCD_READ with DPCD address
[06:16:23] [PASSED] DP_REMOTE_DPCD_READ with max number of bytes
[06:16:23] [PASSED] DP_REMOTE_DPCD_WRITE with port number
[06:16:23] [PASSED] DP_REMOTE_DPCD_WRITE with DPCD address
[06:16:23] [PASSED] DP_REMOTE_DPCD_WRITE with data array
[06:16:23] [PASSED] DP_REMOTE_I2C_READ with port number
[06:16:23] [PASSED] DP_REMOTE_I2C_READ with I2C device ID
[06:16:23] [PASSED] DP_REMOTE_I2C_READ with transactions array
[06:16:23] [PASSED] DP_REMOTE_I2C_WRITE with port number
[06:16:23] [PASSED] DP_REMOTE_I2C_WRITE with I2C device ID
[06:16:23] [PASSED] DP_REMOTE_I2C_WRITE with data array
[06:16:23] [PASSED] DP_QUERY_STREAM_ENC_STATUS with stream ID
[06:16:23] [PASSED] DP_QUERY_STREAM_ENC_STATUS with client ID
[06:16:23] [PASSED] DP_QUERY_STREAM_ENC_STATUS with stream event
[06:16:23] [PASSED] DP_QUERY_STREAM_ENC_STATUS with valid stream event
[06:16:23] [PASSED] DP_QUERY_STREAM_ENC_STATUS with stream behavior
[06:16:23] [PASSED] DP_QUERY_STREAM_ENC_STATUS with a valid stream behavior
[06:16:23] ===== [PASSED] drm_test_dp_mst_sideband_msg_req_decode =====
[06:16:23] ================ [PASSED] drm_dp_mst_helper ================
[06:16:23] ================== drm_exec (7 subtests) ===================
[06:16:23] [PASSED] sanitycheck
[06:16:23] [PASSED] test_lock
[06:16:23] [PASSED] test_lock_unlock
[06:16:23] [PASSED] test_duplicates
[06:16:23] [PASSED] test_prepare
[06:16:23] [PASSED] test_prepare_array
[06:16:23] [PASSED] test_multiple_loops
[06:16:23] ==================== [PASSED] drm_exec =====================
[06:16:23] =========== drm_format_helper_test (17 subtests) ===========
[06:16:23] ============== drm_test_fb_xrgb8888_to_gray8 ==============
[06:16:23] [PASSED] single_pixel_source_buffer
[06:16:23] [PASSED] single_pixel_clip_rectangle
[06:16:23] [PASSED] well_known_colors
[06:16:23] [PASSED] destination_pitch
[06:16:23] ========== [PASSED] drm_test_fb_xrgb8888_to_gray8 ==========
[06:16:23] ============= drm_test_fb_xrgb8888_to_rgb332 ==============
[06:16:23] [PASSED] single_pixel_source_buffer
[06:16:23] [PASSED] single_pixel_clip_rectangle
[06:16:23] [PASSED] well_known_colors
[06:16:23] [PASSED] destination_pitch
[06:16:23] ========= [PASSED] drm_test_fb_xrgb8888_to_rgb332 ==========
[06:16:23] ============= drm_test_fb_xrgb8888_to_rgb565 ==============
[06:16:23] [PASSED] single_pixel_source_buffer
[06:16:23] [PASSED] single_pixel_clip_rectangle
[06:16:23] [PASSED] well_known_colors
[06:16:23] [PASSED] destination_pitch
[06:16:23] ========= [PASSED] drm_test_fb_xrgb8888_to_rgb565 ==========
[06:16:23] ============ drm_test_fb_xrgb8888_to_xrgb1555 =============
[06:16:23] [PASSED] single_pixel_source_buffer
[06:16:23] [PASSED] single_pixel_clip_rectangle
[06:16:23] [PASSED] well_known_colors
[06:16:23] [PASSED] destination_pitch
[06:16:23] ======== [PASSED] drm_test_fb_xrgb8888_to_xrgb1555 =========
[06:16:23] ============ drm_test_fb_xrgb8888_to_argb1555 =============
[06:16:23] [PASSED] single_pixel_source_buffer
[06:16:23] [PASSED] single_pixel_clip_rectangle
[06:16:23] [PASSED] well_known_colors
[06:16:23] [PASSED] destination_pitch
[06:16:23] ======== [PASSED] drm_test_fb_xrgb8888_to_argb1555 =========
[06:16:23] ============ drm_test_fb_xrgb8888_to_rgba5551 =============
[06:16:23] [PASSED] single_pixel_source_buffer
[06:16:23] [PASSED] single_pixel_clip_rectangle
[06:16:23] [PASSED] well_known_colors
[06:16:23] [PASSED] destination_pitch
[06:16:23] ======== [PASSED] drm_test_fb_xrgb8888_to_rgba5551 =========
[06:16:23] ============= drm_test_fb_xrgb8888_to_rgb888 ==============
[06:16:23] [PASSED] single_pixel_source_buffer
[06:16:23] [PASSED] single_pixel_clip_rectangle
[06:16:23] [PASSED] well_known_colors
[06:16:23] [PASSED] destination_pitch
[06:16:23] ========= [PASSED] drm_test_fb_xrgb8888_to_rgb888 ==========
[06:16:23] ============= drm_test_fb_xrgb8888_to_bgr888 ==============
[06:16:23] [PASSED] single_pixel_source_buffer
[06:16:23] [PASSED] single_pixel_clip_rectangle
[06:16:23] [PASSED] well_known_colors
[06:16:23] [PASSED] destination_pitch
[06:16:23] ========= [PASSED] drm_test_fb_xrgb8888_to_bgr888 ==========
[06:16:23] ============ drm_test_fb_xrgb8888_to_argb8888 =============
[06:16:23] [PASSED] single_pixel_source_buffer
[06:16:23] [PASSED] single_pixel_clip_rectangle
[06:16:23] [PASSED] well_known_colors
[06:16:23] [PASSED] destination_pitch
[06:16:23] ======== [PASSED] drm_test_fb_xrgb8888_to_argb8888 =========
[06:16:23] =========== drm_test_fb_xrgb8888_to_xrgb2101010 ===========
[06:16:23] [PASSED] single_pixel_source_buffer
[06:16:23] [PASSED] single_pixel_clip_rectangle
[06:16:23] [PASSED] well_known_colors
[06:16:23] [PASSED] destination_pitch
[06:16:23] ======= [PASSED] drm_test_fb_xrgb8888_to_xrgb2101010 =======
[06:16:23] =========== drm_test_fb_xrgb8888_to_argb2101010 ===========
[06:16:23] [PASSED] single_pixel_source_buffer
[06:16:23] [PASSED] single_pixel_clip_rectangle
[06:16:23] [PASSED] well_known_colors
[06:16:23] [PASSED] destination_pitch
[06:16:23] ======= [PASSED] drm_test_fb_xrgb8888_to_argb2101010 =======
[06:16:23] ============== drm_test_fb_xrgb8888_to_mono ===============
[06:16:23] [PASSED] single_pixel_source_buffer
[06:16:23] [PASSED] single_pixel_clip_rectangle
[06:16:23] [PASSED] well_known_colors
[06:16:23] [PASSED] destination_pitch
[06:16:23] ========== [PASSED] drm_test_fb_xrgb8888_to_mono ===========
[06:16:23] ==================== drm_test_fb_swab =====================
[06:16:23] [PASSED] single_pixel_source_buffer
[06:16:23] [PASSED] single_pixel_clip_rectangle
[06:16:23] [PASSED] well_known_colors
[06:16:23] [PASSED] destination_pitch
[06:16:23] ================ [PASSED] drm_test_fb_swab =================
[06:16:23] ============ drm_test_fb_xrgb8888_to_xbgr8888 =============
[06:16:23] [PASSED] single_pixel_source_buffer
[06:16:23] [PASSED] single_pixel_clip_rectangle
[06:16:23] [PASSED] well_known_colors
[06:16:23] [PASSED] destination_pitch
[06:16:23] ======== [PASSED] drm_test_fb_xrgb8888_to_xbgr8888 =========
[06:16:23] ============ drm_test_fb_xrgb8888_to_abgr8888 =============
[06:16:23] [PASSED] single_pixel_source_buffer
[06:16:23] [PASSED] single_pixel_clip_rectangle
[06:16:23] [PASSED] well_known_colors
[06:16:23] [PASSED] destination_pitch
[06:16:23] ======== [PASSED] drm_test_fb_xrgb8888_to_abgr8888 =========
[06:16:23] ================= drm_test_fb_clip_offset =================
[06:16:23] [PASSED] pass through
[06:16:23] [PASSED] horizontal offset
[06:16:23] [PASSED] vertical offset
[06:16:23] [PASSED] horizontal and vertical offset
[06:16:23] [PASSED] horizontal offset (custom pitch)
[06:16:23] [PASSED] vertical offset (custom pitch)
[06:16:23] [PASSED] horizontal and vertical offset (custom pitch)
[06:16:23] ============= [PASSED] drm_test_fb_clip_offset =============
[06:16:23] =================== drm_test_fb_memcpy ====================
[06:16:23] [PASSED] single_pixel_source_buffer: XR24 little-endian (0x34325258)
[06:16:23] [PASSED] single_pixel_source_buffer: XRA8 little-endian (0x38415258)
[06:16:23] [PASSED] single_pixel_source_buffer: YU24 little-endian (0x34325559)
[06:16:23] [PASSED] single_pixel_clip_rectangle: XB24 little-endian (0x34324258)
[06:16:23] [PASSED] single_pixel_clip_rectangle: XRA8 little-endian (0x38415258)
[06:16:23] [PASSED] single_pixel_clip_rectangle: YU24 little-endian (0x34325559)
[06:16:23] [PASSED] well_known_colors: XB24 little-endian (0x34324258)
[06:16:23] [PASSED] well_known_colors: XRA8 little-endian (0x38415258)
[06:16:23] [PASSED] well_known_colors: YU24 little-endian (0x34325559)
[06:16:23] [PASSED] destination_pitch: XB24 little-endian (0x34324258)
[06:16:23] [PASSED] destination_pitch: XRA8 little-endian (0x38415258)
[06:16:23] [PASSED] destination_pitch: YU24 little-endian (0x34325559)
[06:16:23] =============== [PASSED] drm_test_fb_memcpy ================
[06:16:23] ============= [PASSED] drm_format_helper_test ==============
[06:16:23] ================= drm_format (18 subtests) =================
[06:16:23] [PASSED] drm_test_format_block_width_invalid
[06:16:23] [PASSED] drm_test_format_block_width_one_plane
[06:16:23] [PASSED] drm_test_format_block_width_two_plane
[06:16:23] [PASSED] drm_test_format_block_width_three_plane
[06:16:23] [PASSED] drm_test_format_block_width_tiled
[06:16:23] [PASSED] drm_test_format_block_height_invalid
[06:16:23] [PASSED] drm_test_format_block_height_one_plane
[06:16:23] [PASSED] drm_test_format_block_height_two_plane
[06:16:23] [PASSED] drm_test_format_block_height_three_plane
[06:16:23] [PASSED] drm_test_format_block_height_tiled
[06:16:23] [PASSED] drm_test_format_min_pitch_invalid
[06:16:23] [PASSED] drm_test_format_min_pitch_one_plane_8bpp
[06:16:23] [PASSED] drm_test_format_min_pitch_one_plane_16bpp
[06:16:23] [PASSED] drm_test_format_min_pitch_one_plane_24bpp
[06:16:23] [PASSED] drm_test_format_min_pitch_one_plane_32bpp
[06:16:23] [PASSED] drm_test_format_min_pitch_two_plane
[06:16:23] [PASSED] drm_test_format_min_pitch_three_plane_8bpp
[06:16:23] [PASSED] drm_test_format_min_pitch_tiled
[06:16:23] =================== [PASSED] drm_format ====================
[06:16:23] ============== drm_framebuffer (10 subtests) ===============
[06:16:23] ========== drm_test_framebuffer_check_src_coords ==========
[06:16:23] [PASSED] Success: source fits into fb
[06:16:23] [PASSED] Fail: overflowing fb with x-axis coordinate
[06:16:23] [PASSED] Fail: overflowing fb with y-axis coordinate
[06:16:23] [PASSED] Fail: overflowing fb with source width
[06:16:23] [PASSED] Fail: overflowing fb with source height
[06:16:23] ====== [PASSED] drm_test_framebuffer_check_src_coords ======
[06:16:23] [PASSED] drm_test_framebuffer_cleanup
[06:16:23] =============== drm_test_framebuffer_create ===============
[06:16:23] [PASSED] ABGR8888 normal sizes
[06:16:23] [PASSED] ABGR8888 max sizes
[06:16:23] [PASSED] ABGR8888 pitch greater than min required
[06:16:23] [PASSED] ABGR8888 pitch less than min required
[06:16:23] [PASSED] ABGR8888 Invalid width
[06:16:23] [PASSED] ABGR8888 Invalid buffer handle
[06:16:23] [PASSED] No pixel format
[06:16:23] [PASSED] ABGR8888 Width 0
[06:16:23] [PASSED] ABGR8888 Height 0
[06:16:23] [PASSED] ABGR8888 Out of bound height * pitch combination
[06:16:23] [PASSED] ABGR8888 Large buffer offset
[06:16:23] [PASSED] ABGR8888 Buffer offset for inexistent plane
[06:16:23] [PASSED] ABGR8888 Invalid flag
[06:16:23] [PASSED] ABGR8888 Set DRM_MODE_FB_MODIFIERS without modifiers
[06:16:23] [PASSED] ABGR8888 Valid buffer modifier
[06:16:23] [PASSED] ABGR8888 Invalid buffer modifier(DRM_FORMAT_MOD_SAMSUNG_64_32_TILE)
[06:16:23] [PASSED] ABGR8888 Extra pitches without DRM_MODE_FB_MODIFIERS
[06:16:23] [PASSED] ABGR8888 Extra pitches with DRM_MODE_FB_MODIFIERS
[06:16:23] [PASSED] NV12 Normal sizes
[06:16:23] [PASSED] NV12 Max sizes
[06:16:23] [PASSED] NV12 Invalid pitch
[06:16:23] [PASSED] NV12 Invalid modifier/missing DRM_MODE_FB_MODIFIERS flag
[06:16:23] [PASSED] NV12 different modifier per-plane
[06:16:23] [PASSED] NV12 with DRM_FORMAT_MOD_SAMSUNG_64_32_TILE
[06:16:23] [PASSED] NV12 Valid modifiers without DRM_MODE_FB_MODIFIERS
[06:16:23] [PASSED] NV12 Modifier for inexistent plane
[06:16:23] [PASSED] NV12 Handle for inexistent plane
[06:16:23] [PASSED] NV12 Handle for inexistent plane without DRM_MODE_FB_MODIFIERS
[06:16:23] [PASSED] YVU420 DRM_MODE_FB_MODIFIERS set without modifier
[06:16:23] [PASSED] YVU420 Normal sizes
[06:16:23] [PASSED] YVU420 Max sizes
[06:16:23] [PASSED] YVU420 Invalid pitch
[06:16:23] [PASSED] YVU420 Different pitches
[06:16:23] [PASSED] YVU420 Different buffer offsets/pitches
[06:16:23] [PASSED] YVU420 Modifier set just for plane 0, without DRM_MODE_FB_MODIFIERS
[06:16:23] [PASSED] YVU420 Modifier set just for planes 0, 1, without DRM_MODE_FB_MODIFIERS
[06:16:23] [PASSED] YVU420 Modifier set just for plane 0, 1, with DRM_MODE_FB_MODIFIERS
[06:16:23] [PASSED] YVU420 Valid modifier
[06:16:23] [PASSED] YVU420 Different modifiers per plane
[06:16:23] [PASSED] YVU420 Modifier for inexistent plane
[06:16:23] [PASSED] YUV420_10BIT Invalid modifier(DRM_FORMAT_MOD_LINEAR)
[06:16:23] [PASSED] X0L2 Normal sizes
[06:16:23] [PASSED] X0L2 Max sizes
[06:16:23] [PASSED] X0L2 Invalid pitch
[06:16:23] [PASSED] X0L2 Pitch greater than minimum required
[06:16:23] [PASSED] X0L2 Handle for inexistent plane
[06:16:23] [PASSED] X0L2 Offset for inexistent plane, without DRM_MODE_FB_MODIFIERS set
[06:16:23] [PASSED] X0L2 Modifier without DRM_MODE_FB_MODIFIERS set
[06:16:23] [PASSED] X0L2 Valid modifier
[06:16:23] [PASSED] X0L2 Modifier for inexistent plane
[06:16:23] =========== [PASSED] drm_test_framebuffer_create ===========
[06:16:23] [PASSED] drm_test_framebuffer_free
[06:16:23] [PASSED] drm_test_framebuffer_init
[06:16:23] [PASSED] drm_test_framebuffer_init_bad_format
[06:16:23] [PASSED] drm_test_framebuffer_init_dev_mismatch
[06:16:23] [PASSED] drm_test_framebuffer_lookup
[06:16:23] [PASSED] drm_test_framebuffer_lookup_inexistent
[06:16:23] [PASSED] drm_test_framebuffer_modifiers_not_supported
[06:16:23] ================= [PASSED] drm_framebuffer =================
[06:16:23] ================ drm_gem_shmem (8 subtests) ================
[06:16:23] [PASSED] drm_gem_shmem_test_obj_create
[06:16:23] [PASSED] drm_gem_shmem_test_obj_create_private
[06:16:23] [PASSED] drm_gem_shmem_test_pin_pages
[06:16:23] [PASSED] drm_gem_shmem_test_vmap
[06:16:23] [PASSED] drm_gem_shmem_test_get_sg_table
[06:16:23] [PASSED] drm_gem_shmem_test_get_pages_sgt
[06:16:23] [PASSED] drm_gem_shmem_test_madvise
[06:16:23] [PASSED] drm_gem_shmem_test_purge
[06:16:23] ================== [PASSED] drm_gem_shmem ==================
[06:16:23] === drm_atomic_helper_connector_hdmi_check (29 subtests) ===
[06:16:23] [PASSED] drm_test_check_broadcast_rgb_auto_cea_mode
[06:16:23] [PASSED] drm_test_check_broadcast_rgb_auto_cea_mode_vic_1
[06:16:23] [PASSED] drm_test_check_broadcast_rgb_full_cea_mode
[06:16:23] [PASSED] drm_test_check_broadcast_rgb_full_cea_mode_vic_1
[06:16:23] [PASSED] drm_test_check_broadcast_rgb_limited_cea_mode
[06:16:23] [PASSED] drm_test_check_broadcast_rgb_limited_cea_mode_vic_1
[06:16:23] ====== drm_test_check_broadcast_rgb_cea_mode_yuv420 =======
[06:16:23] [PASSED] Automatic
[06:16:23] [PASSED] Full
[06:16:23] [PASSED] Limited 16:235
[06:16:23] == [PASSED] drm_test_check_broadcast_rgb_cea_mode_yuv420 ===
[06:16:23] [PASSED] drm_test_check_broadcast_rgb_crtc_mode_changed
[06:16:23] [PASSED] drm_test_check_broadcast_rgb_crtc_mode_not_changed
[06:16:23] [PASSED] drm_test_check_disable_connector
[06:16:23] [PASSED] drm_test_check_hdmi_funcs_reject_rate
[06:16:23] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_rgb
[06:16:23] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_yuv420
[06:16:23] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_ignore_yuv422
[06:16:23] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_ignore_yuv420
[06:16:23] [PASSED] drm_test_check_driver_unsupported_fallback_yuv420
[06:16:23] [PASSED] drm_test_check_output_bpc_crtc_mode_changed
[06:16:23] [PASSED] drm_test_check_output_bpc_crtc_mode_not_changed
[06:16:23] [PASSED] drm_test_check_output_bpc_dvi
[06:16:23] [PASSED] drm_test_check_output_bpc_format_vic_1
[06:16:23] [PASSED] drm_test_check_output_bpc_format_display_8bpc_only
[06:16:23] [PASSED] drm_test_check_output_bpc_format_display_rgb_only
[06:16:23] [PASSED] drm_test_check_output_bpc_format_driver_8bpc_only
[06:16:23] [PASSED] drm_test_check_output_bpc_format_driver_rgb_only
[06:16:23] [PASSED] drm_test_check_tmds_char_rate_rgb_8bpc
[06:16:23] [PASSED] drm_test_check_tmds_char_rate_rgb_10bpc
[06:16:23] [PASSED] drm_test_check_tmds_char_rate_rgb_12bpc
[06:16:23] ============ drm_test_check_hdmi_color_format =============
[06:16:23] [PASSED] AUTO -> RGB
[06:16:23] [PASSED] YCBCR422 -> YUV422
[06:16:23] [PASSED] YCBCR420 -> YUV420
[06:16:23] [PASSED] YCBCR444 -> YUV444
[06:16:23] [PASSED] RGB -> RGB
[06:16:23] ======== [PASSED] drm_test_check_hdmi_color_format =========
[06:16:23] ======== drm_test_check_hdmi_color_format_420_only ========
[06:16:23] [PASSED] RGB should fail
[06:16:23] [PASSED] YUV444 should fail
[06:16:23] [PASSED] YUV422 should fail
[06:16:23] [PASSED] YUV420 should work
[06:16:23] ==== [PASSED] drm_test_check_hdmi_color_format_420_only ====
[06:16:23] ===== [PASSED] drm_atomic_helper_connector_hdmi_check ======
[06:16:23] === drm_atomic_helper_connector_hdmi_reset (6 subtests) ====
[06:16:23] [PASSED] drm_test_check_broadcast_rgb_value
[06:16:23] [PASSED] drm_test_check_bpc_8_value
[06:16:23] [PASSED] drm_test_check_bpc_10_value
[06:16:23] [PASSED] drm_test_check_bpc_12_value
[06:16:23] [PASSED] drm_test_check_format_value
[06:16:23] [PASSED] drm_test_check_tmds_char_value
[06:16:23] ===== [PASSED] drm_atomic_helper_connector_hdmi_reset ======
[06:16:23] = drm_atomic_helper_connector_hdmi_mode_valid (7 subtests) =
[06:16:23] [PASSED] drm_test_check_mode_valid
[06:16:23] [PASSED] drm_test_check_mode_valid_reject
[06:16:23] [PASSED] drm_test_check_mode_valid_reject_rate
[06:16:23] [PASSED] drm_test_check_mode_valid_reject_max_clock
[06:16:23] [PASSED] drm_test_check_mode_valid_yuv420_only_max_clock
[06:16:23] [PASSED] drm_test_check_mode_valid_reject_yuv420_only_connector
[06:16:23] [PASSED] drm_test_check_mode_valid_accept_yuv420_also_connector_rgb
[06:16:23] === [PASSED] drm_atomic_helper_connector_hdmi_mode_valid ===
[06:16:23] = drm_atomic_helper_connector_hdmi_infoframes (5 subtests) =
[06:16:23] [PASSED] drm_test_check_infoframes
[06:16:23] [PASSED] drm_test_check_reject_avi_infoframe
[06:16:23] [PASSED] drm_test_check_reject_hdr_infoframe_bpc_8
[06:16:23] [PASSED] drm_test_check_reject_hdr_infoframe_bpc_10
[06:16:23] [PASSED] drm_test_check_reject_audio_infoframe
[06:16:23] === [PASSED] drm_atomic_helper_connector_hdmi_infoframes ===
[06:16:23] ================= drm_managed (2 subtests) =================
[06:16:23] [PASSED] drm_test_managed_release_action
[06:16:23] [PASSED] drm_test_managed_run_action
[06:16:23] =================== [PASSED] drm_managed ===================
[06:16:23] =================== drm_mm (6 subtests) ====================
[06:16:23] [PASSED] drm_test_mm_init
[06:16:23] [PASSED] drm_test_mm_debug
[06:16:23] [PASSED] drm_test_mm_align32
[06:16:23] [PASSED] drm_test_mm_align64
[06:16:23] [PASSED] drm_test_mm_lowest
[06:16:23] [PASSED] drm_test_mm_highest
[06:16:23] ===================== [PASSED] drm_mm ======================
[06:16:23] ============= drm_modes_analog_tv (5 subtests) =============
[06:16:23] [PASSED] drm_test_modes_analog_tv_mono_576i
[06:16:23] [PASSED] drm_test_modes_analog_tv_ntsc_480i
[06:16:23] [PASSED] drm_test_modes_analog_tv_ntsc_480i_inlined
[06:16:23] [PASSED] drm_test_modes_analog_tv_pal_576i
[06:16:23] [PASSED] drm_test_modes_analog_tv_pal_576i_inlined
[06:16:23] =============== [PASSED] drm_modes_analog_tv ===============
[06:16:23] ============== drm_panic_helper (3 subtests) ===============
[06:16:23] ============= drm_test_panic_screen_user_map ==============
[06:16:23] [PASSED] Panic screen user, mode: 1024 x 768 XR24 little-endian (0x34325258)
[06:16:23] [PASSED] Panic screen user, mode: 494 x 494 XR24 little-endian (0x34325258)
[06:16:23] [PASSED] Panic screen user, mode: 1920 x 1080 XR24 little-endian (0x34325258)
[06:16:23] [PASSED] Panic screen user, mode: 1024 x 768 RG16 little-endian (0x36314752)
[06:16:23] [PASSED] Panic screen user, mode: 1024 x 768 RG24 little-endian (0x34324752)
[06:16:23] [PASSED] Panic screen kmsg, mode: 1024 x 768 XR24 little-endian (0x34325258)
[06:16:23] [PASSED] Panic screen kmsg, mode: 494 x 494 XR24 little-endian (0x34325258)
[06:16:23] [PASSED] Panic screen kmsg, mode: 1920 x 1080 XR24 little-endian (0x34325258)
[06:16:23] [PASSED] Panic screen kmsg, mode: 1024 x 768 RG16 little-endian (0x36314752)
[06:16:23] [PASSED] Panic screen kmsg, mode: 1024 x 768 RG24 little-endian (0x34324752)
[06:16:23] ========= [PASSED] drm_test_panic_screen_user_map ==========
[06:16:23] ============= drm_test_panic_screen_user_page =============
[06:16:23] [PASSED] Panic screen user, mode: 1024 x 768 XR24 little-endian (0x34325258)
[06:16:23] [PASSED] Panic screen user, mode: 494 x 494 XR24 little-endian (0x34325258)
[06:16:23] [PASSED] Panic screen user, mode: 1920 x 1080 XR24 little-endian (0x34325258)
[06:16:23] [PASSED] Panic screen user, mode: 1024 x 768 RG16 little-endian (0x36314752)
[06:16:23] [PASSED] Panic screen user, mode: 1024 x 768 RG24 little-endian (0x34324752)
[06:16:23] [PASSED] Panic screen kmsg, mode: 1024 x 768 XR24 little-endian (0x34325258)
[06:16:23] [PASSED] Panic screen kmsg, mode: 494 x 494 XR24 little-endian (0x34325258)
[06:16:23] [PASSED] Panic screen kmsg, mode: 1920 x 1080 XR24 little-endian (0x34325258)
[06:16:23] [PASSED] Panic screen kmsg, mode: 1024 x 768 RG16 little-endian (0x36314752)
[06:16:23] [PASSED] Panic screen kmsg, mode: 1024 x 768 RG24 little-endian (0x34324752)
[06:16:23] ========= [PASSED] drm_test_panic_screen_user_page =========
[06:16:23] ========== drm_test_panic_screen_user_set_pixel ===========
[06:16:23] [PASSED] Panic screen user, mode: 1024 x 768 XR24 little-endian (0x34325258)
[06:16:23] [PASSED] Panic screen user, mode: 494 x 494 XR24 little-endian (0x34325258)
[06:16:23] [PASSED] Panic screen user, mode: 1920 x 1080 XR24 little-endian (0x34325258)
[06:16:23] [PASSED] Panic screen user, mode: 1024 x 768 RG16 little-endian (0x36314752)
[06:16:23] [PASSED] Panic screen user, mode: 1024 x 768 RG24 little-endian (0x34324752)
[06:16:23] [PASSED] Panic screen kmsg, mode: 1024 x 768 XR24 little-endian (0x34325258)
[06:16:23] [PASSED] Panic screen kmsg, mode: 494 x 494 XR24 little-endian (0x34325258)
[06:16:23] [PASSED] Panic screen kmsg, mode: 1920 x 1080 XR24 little-endian (0x34325258)
[06:16:23] [PASSED] Panic screen kmsg, mode: 1024 x 768 RG16 little-endian (0x36314752)
[06:16:23] [PASSED] Panic screen kmsg, mode: 1024 x 768 RG24 little-endian (0x34324752)
[06:16:23] ====== [PASSED] drm_test_panic_screen_user_set_pixel =======
[06:16:23] ================ [PASSED] drm_panic_helper =================
[06:16:23] ============== drm_plane_helper (2 subtests) ===============
[06:16:23] =============== drm_test_check_plane_state ================
[06:16:23] [PASSED] clipping_simple
[06:16:23] [PASSED] clipping_rotate_reflect
[06:16:23] [PASSED] positioning_simple
[06:16:23] [PASSED] upscaling
[06:16:23] [PASSED] downscaling
[06:16:23] [PASSED] rounding1
[06:16:23] [PASSED] rounding2
[06:16:23] [PASSED] rounding3
[06:16:23] [PASSED] rounding4
[06:16:23] =========== [PASSED] drm_test_check_plane_state ============
[06:16:23] =========== drm_test_check_invalid_plane_state ============
[06:16:23] [PASSED] positioning_invalid
[06:16:23] [PASSED] upscaling_invalid
[06:16:23] [PASSED] downscaling_invalid
[06:16:23] ======= [PASSED] drm_test_check_invalid_plane_state ========
[06:16:23] ================ [PASSED] drm_plane_helper =================
[06:16:23] ====== drm_connector_helper_tv_get_modes (1 subtest) =======
[06:16:23] ====== drm_test_connector_helper_tv_get_modes_check =======
[06:16:23] [PASSED] None
[06:16:23] [PASSED] PAL
[06:16:23] [PASSED] NTSC
[06:16:23] [PASSED] Both, NTSC Default
[06:16:23] [PASSED] Both, PAL Default
[06:16:23] [PASSED] Both, NTSC Default, with PAL on command-line
[06:16:23] [PASSED] Both, PAL Default, with NTSC on command-line
[06:16:23] == [PASSED] drm_test_connector_helper_tv_get_modes_check ===
[06:16:23] ======== [PASSED] drm_connector_helper_tv_get_modes ========
[06:16:23] ================== drm_rect (9 subtests) ===================
[06:16:23] [PASSED] drm_test_rect_clip_scaled_div_by_zero
[06:16:23] [PASSED] drm_test_rect_clip_scaled_not_clipped
[06:16:23] [PASSED] drm_test_rect_clip_scaled_clipped
[06:16:23] [PASSED] drm_test_rect_clip_scaled_signed_vs_unsigned
[06:16:23] ================= drm_test_rect_intersect =================
[06:16:23] [PASSED] top-left x bottom-right: 2x2+1+1 x 2x2+0+0
[06:16:23] [PASSED] top-right x bottom-left: 2x2+0+0 x 2x2+1-1
[06:16:23] [PASSED] bottom-left x top-right: 2x2+1-1 x 2x2+0+0
[06:16:23] [PASSED] bottom-right x top-left: 2x2+0+0 x 2x2+1+1
[06:16:23] [PASSED] right x left: 2x1+0+0 x 3x1+1+0
[06:16:23] [PASSED] left x right: 3x1+1+0 x 2x1+0+0
[06:16:23] [PASSED] up x bottom: 1x2+0+0 x 1x3+0-1
[06:16:23] [PASSED] bottom x up: 1x3+0-1 x 1x2+0+0
[06:16:23] [PASSED] touching corner: 1x1+0+0 x 2x2+1+1
[06:16:23] [PASSED] touching side: 1x1+0+0 x 1x1+1+0
[06:16:23] [PASSED] equal rects: 2x2+0+0 x 2x2+0+0
[06:16:23] [PASSED] inside another: 2x2+0+0 x 1x1+1+1
[06:16:23] [PASSED] far away: 1x1+0+0 x 1x1+3+6
[06:16:23] [PASSED] points intersecting: 0x0+5+10 x 0x0+5+10
[06:16:23] [PASSED] points not intersecting: 0x0+0+0 x 0x0+5+10
[06:16:23] ============= [PASSED] drm_test_rect_intersect =============
[06:16:23] ================ drm_test_rect_calc_hscale ================
[06:16:23] [PASSED] normal use
[06:16:23] [PASSED] out of max range
[06:16:23] [PASSED] out of min range
[06:16:23] [PASSED] zero dst
[06:16:23] [PASSED] negative src
[06:16:23] [PASSED] negative dst
[06:16:23] ============ [PASSED] drm_test_rect_calc_hscale ============
[06:16:23] ================ drm_test_rect_calc_vscale ================
[06:16:23] [PASSED] normal use
[06:16:23] [PASSED] out of max range
[06:16:23] [PASSED] out of min range
[06:16:23] [PASSED] zero dst
[06:16:23] [PASSED] negative src
[06:16:23] [PASSED] negative dst
[06:16:23] ============ [PASSED] drm_test_rect_calc_vscale ============
[06:16:23] ================== drm_test_rect_rotate ===================
[06:16:23] [PASSED] reflect-x
[06:16:23] [PASSED] reflect-y
[06:16:23] [PASSED] rotate-0
[06:16:23] [PASSED] rotate-90
[06:16:23] [PASSED] rotate-180
[06:16:23] [PASSED] rotate-270
[06:16:23] ============== [PASSED] drm_test_rect_rotate ===============
[06:16:23] ================ drm_test_rect_rotate_inv =================
[06:16:23] [PASSED] reflect-x
[06:16:23] [PASSED] reflect-y
[06:16:23] [PASSED] rotate-0
[06:16:23] [PASSED] rotate-90
[06:16:23] [PASSED] rotate-180
[06:16:23] [PASSED] rotate-270
[06:16:23] ============ [PASSED] drm_test_rect_rotate_inv =============
[06:16:23] ==================== [PASSED] drm_rect =====================
[06:16:23] ============ drm_sysfb_modeset_test (1 subtest) ============
[06:16:23] ============ drm_test_sysfb_build_fourcc_list =============
[06:16:23] [PASSED] no native formats
[06:16:23] [PASSED] XRGB8888 as native format
[06:16:23] [PASSED] remove duplicates
[06:16:23] [PASSED] convert alpha formats
[06:16:23] [PASSED] random formats
[06:16:23] ======== [PASSED] drm_test_sysfb_build_fourcc_list =========
[06:16:23] ============= [PASSED] drm_sysfb_modeset_test ==============
[06:16:23] ================== drm_fixp (2 subtests) ===================
[06:16:23] [PASSED] drm_test_int2fixp
[06:16:23] [PASSED] drm_test_sm2fixp
[06:16:23] ==================== [PASSED] drm_fixp =====================
[06:16:23] ============================================================
[06:16:23] Testing complete. Ran 667 tests: passed: 667
[06:16:23] Elapsed time: 27.116s total, 1.835s configuring, 24.865s building, 0.413s running
+ for kcfg in "${kunitconfigs[@]}"
+ [[ ! -f /kernel/drivers/gpu/drm/ttm/tests/.kunitconfig ]]
+ /kernel/tools/testing/kunit/kunit.py run --kunitconfig /kernel/drivers/gpu/drm/ttm/tests/.kunitconfig
[06:16:23] Configuring KUnit Kernel ...
Regenerating .config ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
[06:16:25] Building KUnit Kernel ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
Building with:
$ make all compile_commands.json scripts_gdb ARCH=um O=.kunit --jobs=48
[06:16:35] Starting KUnit Kernel (1/1)...
[06:16:35] ============================================================
Running tests with:
$ .kunit/linux kunit.enable=1 mem=1G console=tty kunit_shutdown=halt
[06:16:35] ================= ttm_device (5 subtests) ==================
[06:16:35] [PASSED] ttm_device_init_basic
[06:16:35] [PASSED] ttm_device_init_multiple
[06:16:35] [PASSED] ttm_device_fini_basic
[06:16:35] [PASSED] ttm_device_init_no_vma_man
[06:16:35] ================== ttm_device_init_pools ==================
[06:16:35] [PASSED] No DMA allocations, no DMA32 required
[06:16:35] [PASSED] DMA allocations, DMA32 required
[06:16:35] [PASSED] No DMA allocations, DMA32 required
[06:16:35] [PASSED] DMA allocations, no DMA32 required
[06:16:35] ============== [PASSED] ttm_device_init_pools ==============
[06:16:35] =================== [PASSED] ttm_device ====================
[06:16:35] ================== ttm_pool (8 subtests) ===================
[06:16:35] ================== ttm_pool_alloc_basic ===================
[06:16:35] [PASSED] One page
[06:16:35] [PASSED] More than one page
[06:16:35] [PASSED] Above the allocation limit
[06:16:35] [PASSED] One page, with coherent DMA mappings enabled
[06:16:35] [PASSED] Above the allocation limit, with coherent DMA mappings enabled
[06:16:35] ============== [PASSED] ttm_pool_alloc_basic ===============
[06:16:35] ============== ttm_pool_alloc_basic_dma_addr ==============
[06:16:35] [PASSED] One page
[06:16:35] [PASSED] More than one page
[06:16:35] [PASSED] Above the allocation limit
[06:16:35] [PASSED] One page, with coherent DMA mappings enabled
[06:16:35] [PASSED] Above the allocation limit, with coherent DMA mappings enabled
[06:16:35] ========== [PASSED] ttm_pool_alloc_basic_dma_addr ==========
[06:16:35] [PASSED] ttm_pool_alloc_order_caching_match
[06:16:35] [PASSED] ttm_pool_alloc_caching_mismatch
[06:16:35] [PASSED] ttm_pool_alloc_order_mismatch
[06:16:35] [PASSED] ttm_pool_free_dma_alloc
[06:16:35] [PASSED] ttm_pool_free_no_dma_alloc
[06:16:35] [PASSED] ttm_pool_fini_basic
[06:16:35] ==================== [PASSED] ttm_pool =====================
[06:16:35] ================ ttm_resource (8 subtests) =================
[06:16:35] ================= ttm_resource_init_basic =================
[06:16:35] [PASSED] Init resource in TTM_PL_SYSTEM
[06:16:35] [PASSED] Init resource in TTM_PL_VRAM
[06:16:35] [PASSED] Init resource in a private placement
[06:16:35] [PASSED] Init resource in TTM_PL_SYSTEM, set placement flags
[06:16:35] ============= [PASSED] ttm_resource_init_basic =============
[06:16:35] [PASSED] ttm_resource_init_pinned
[06:16:35] [PASSED] ttm_resource_fini_basic
[06:16:35] [PASSED] ttm_resource_manager_init_basic
[06:16:35] [PASSED] ttm_resource_manager_usage_basic
[06:16:35] [PASSED] ttm_resource_manager_set_used_basic
[06:16:35] [PASSED] ttm_sys_man_alloc_basic
[06:16:35] [PASSED] ttm_sys_man_free_basic
[06:16:35] ================== [PASSED] ttm_resource ===================
[06:16:35] =================== ttm_tt (15 subtests) ===================
[06:16:35] ==================== ttm_tt_init_basic ====================
[06:16:35] [PASSED] Page-aligned size
[06:16:35] [PASSED] Extra pages requested
[06:16:35] ================ [PASSED] ttm_tt_init_basic ================
[06:16:35] [PASSED] ttm_tt_init_misaligned
[06:16:35] [PASSED] ttm_tt_fini_basic
[06:16:35] [PASSED] ttm_tt_fini_sg
[06:16:35] [PASSED] ttm_tt_fini_shmem
[06:16:35] [PASSED] ttm_tt_create_basic
[06:16:35] [PASSED] ttm_tt_create_invalid_bo_type
[06:16:35] [PASSED] ttm_tt_create_ttm_exists
[06:16:35] [PASSED] ttm_tt_create_failed
[06:16:35] [PASSED] ttm_tt_destroy_basic
[06:16:35] [PASSED] ttm_tt_populate_null_ttm
[06:16:35] [PASSED] ttm_tt_populate_populated_ttm
[06:16:35] [PASSED] ttm_tt_unpopulate_basic
[06:16:35] [PASSED] ttm_tt_unpopulate_empty_ttm
[06:16:35] [PASSED] ttm_tt_swapin_basic
[06:16:35] ===================== [PASSED] ttm_tt ======================
[06:16:35] =================== ttm_bo (14 subtests) ===================
[06:16:35] =========== ttm_bo_reserve_optimistic_no_ticket ===========
[06:16:35] [PASSED] Cannot be interrupted and sleeps
[06:16:35] [PASSED] Cannot be interrupted, locks straight away
[06:16:35] [PASSED] Can be interrupted, sleeps
[06:16:35] ======= [PASSED] ttm_bo_reserve_optimistic_no_ticket =======
[06:16:35] [PASSED] ttm_bo_reserve_locked_no_sleep
[06:16:35] [PASSED] ttm_bo_reserve_no_wait_ticket
[06:16:35] [PASSED] ttm_bo_reserve_double_resv
[06:16:35] [PASSED] ttm_bo_reserve_interrupted
[06:16:35] [PASSED] ttm_bo_reserve_deadlock
[06:16:35] [PASSED] ttm_bo_unreserve_basic
[06:16:35] [PASSED] ttm_bo_unreserve_pinned
[06:16:35] [PASSED] ttm_bo_unreserve_bulk
[06:16:35] [PASSED] ttm_bo_fini_basic
[06:16:35] [PASSED] ttm_bo_fini_shared_resv
[06:16:35] [PASSED] ttm_bo_pin_basic
[06:16:35] [PASSED] ttm_bo_pin_unpin_resource
[06:16:35] [PASSED] ttm_bo_multiple_pin_one_unpin
[06:16:35] ===================== [PASSED] ttm_bo ======================
[06:16:35] ============== ttm_bo_validate (22 subtests) ===============
[06:16:35] ============== ttm_bo_init_reserved_sys_man ===============
[06:16:35] [PASSED] Buffer object for userspace
[06:16:35] [PASSED] Kernel buffer object
[06:16:35] [PASSED] Shared buffer object
[06:16:35] ========== [PASSED] ttm_bo_init_reserved_sys_man ===========
[06:16:35] ============== ttm_bo_init_reserved_mock_man ==============
[06:16:35] [PASSED] Buffer object for userspace
[06:16:35] [PASSED] Kernel buffer object
[06:16:35] [PASSED] Shared buffer object
[06:16:35] ========== [PASSED] ttm_bo_init_reserved_mock_man ==========
[06:16:35] [PASSED] ttm_bo_init_reserved_resv
[06:16:35] ================== ttm_bo_validate_basic ==================
[06:16:35] [PASSED] Buffer object for userspace
[06:16:35] [PASSED] Kernel buffer object
[06:16:35] [PASSED] Shared buffer object
[06:16:35] ============== [PASSED] ttm_bo_validate_basic ==============
[06:16:35] [PASSED] ttm_bo_validate_invalid_placement
[06:16:35] ============= ttm_bo_validate_same_placement ==============
[06:16:35] [PASSED] System manager
[06:16:35] [PASSED] VRAM manager
[06:16:35] ========= [PASSED] ttm_bo_validate_same_placement ==========
[06:16:35] [PASSED] ttm_bo_validate_failed_alloc
[06:16:35] [PASSED] ttm_bo_validate_pinned
[06:16:35] [PASSED] ttm_bo_validate_busy_placement
[06:16:35] ================ ttm_bo_validate_multihop =================
[06:16:35] [PASSED] Buffer object for userspace
[06:16:35] [PASSED] Kernel buffer object
[06:16:35] [PASSED] Shared buffer object
[06:16:35] ============ [PASSED] ttm_bo_validate_multihop =============
[06:16:35] ========== ttm_bo_validate_no_placement_signaled ==========
[06:16:35] [PASSED] Buffer object in system domain, no page vector
[06:16:35] [PASSED] Buffer object in system domain with an existing page vector
[06:16:35] ====== [PASSED] ttm_bo_validate_no_placement_signaled ======
[06:16:35] ======== ttm_bo_validate_no_placement_not_signaled ========
[06:16:35] [PASSED] Buffer object for userspace
[06:16:35] [PASSED] Kernel buffer object
[06:16:35] [PASSED] Shared buffer object
[06:16:35] ==== [PASSED] ttm_bo_validate_no_placement_not_signaled ====
[06:16:35] [PASSED] ttm_bo_validate_move_fence_signaled
[06:16:35] ========= ttm_bo_validate_move_fence_not_signaled =========
[06:16:35] [PASSED] Waits for GPU
[06:16:35] [PASSED] Tries to lock straight away
[06:16:35] ===== [PASSED] ttm_bo_validate_move_fence_not_signaled =====
[06:16:35] [PASSED] ttm_bo_validate_swapout
[06:16:35] [PASSED] ttm_bo_validate_happy_evict
[06:16:35] [PASSED] ttm_bo_validate_all_pinned_evict
[06:16:35] [PASSED] ttm_bo_validate_allowed_only_evict
[06:16:35] [PASSED] ttm_bo_validate_deleted_evict
[06:16:35] [PASSED] ttm_bo_validate_busy_domain_evict
[06:16:35] [PASSED] ttm_bo_validate_evict_gutting
[06:16:35] [PASSED] ttm_bo_validate_recrusive_evict
[06:16:35] ================= [PASSED] ttm_bo_validate =================
[06:16:35] ============================================================
[06:16:35] Testing complete. Ran 102 tests: passed: 102
[06:16:35] Elapsed time: 12.254s total, 1.855s configuring, 10.184s building, 0.180s running
+ for kcfg in "${kunitconfigs[@]}"
+ [[ ! -f /kernel/drivers/dma-buf/.kunitconfig ]]
+ /kernel/tools/testing/kunit/kunit.py run --kunitconfig /kernel/drivers/dma-buf/.kunitconfig
[06:16:35] Configuring KUnit Kernel ...
Regenerating .config ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
[06:16:37] Building KUnit Kernel ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
Building with:
$ make all compile_commands.json scripts_gdb ARCH=um O=.kunit --jobs=48
[06:16:46] Starting KUnit Kernel (1/1)...
[06:16:46] ============================================================
Running tests with:
$ .kunit/linux kunit.enable=1 mem=1G console=tty kunit_shutdown=halt
[06:16:46] =============== dma-buf-fence (12 subtests) ================
[06:16:46] [PASSED] test_sanitycheck
[06:16:46] [PASSED] test_signaling
[06:16:46] [PASSED] test_add_callback
[06:16:46] [PASSED] test_late_add_callback
[06:16:46] [PASSED] test_rm_callback
[06:16:46] [PASSED] test_late_rm_callback
[06:16:46] [PASSED] test_status
[06:16:46] [PASSED] test_error
[06:16:46] [PASSED] test_wait
[06:16:46] [PASSED] test_wait_timeout
[06:16:46] [PASSED] test_stub
[06:16:46] [SKIPPED] test_race_signal_callback (requires at least 2 CPUs)
[06:16:46] ================== [PASSED] dma-buf-fence ==================
[06:16:46] ============ dma-buf-fence-chain (11 subtests) =============
[06:16:46] [PASSED] test_sanitycheck
[06:16:46] [PASSED] test_find_seqno
[06:16:46] [PASSED] test_find_signaled
[06:16:46] [PASSED] test_find_out_of_order
[06:16:51] [PASSED] test_find_gap
[06:16:51] [PASSED] test_find_race
[06:16:51] [PASSED] test_signal_forward
[06:16:51] [PASSED] test_signal_backward
[06:16:51] [PASSED] test_wait_forward
[06:16:51] [PASSED] test_wait_backward
[06:16:51] [PASSED] test_wait_random
[06:16:51] =============== [PASSED] dma-buf-fence-chain ===============
[06:16:51] ============ dma-buf-fence-unwrap (11 subtests) ============
[06:16:51] [PASSED] test_sanitycheck
[06:16:51] [PASSED] test_unwrap_array
[06:16:51] [PASSED] test_unwrap_chain
[06:16:51] [PASSED] test_unwrap_chain_array
[06:16:51] [PASSED] test_unwrap_merge
[06:16:51] [PASSED] test_unwrap_merge_duplicate
[06:16:51] [PASSED] test_unwrap_merge_seqno
[06:16:51] [PASSED] test_unwrap_merge_order
[06:16:51] [PASSED] test_unwrap_merge_complex
[06:16:51] [PASSED] test_unwrap_merge_complex_seqno
[06:16:51] [PASSED] test_dedup_empty
[06:16:51] ============== [PASSED] dma-buf-fence-unwrap ===============
[06:16:51] ================ dma-buf-resv (5 subtests) =================
[06:16:51] [PASSED] test_sanitycheck
[06:16:51] ===================== test_signaling ======================
[06:16:51] [PASSED] kernel
[06:16:51] [PASSED] write
[06:16:51] [PASSED] read
[06:16:51] [PASSED] bookkeep
[06:16:51] ================= [PASSED] test_signaling ==================
[06:16:51] ====================== test_for_each ======================
[06:16:51] [PASSED] kernel
[06:16:51] [PASSED] write
[06:16:51] [PASSED] read
[06:16:51] [PASSED] bookkeep
[06:16:51] ================== [PASSED] test_for_each ==================
[06:16:51] ================= test_for_each_unlocked ==================
[06:16:51] [PASSED] kernel
[06:16:51] [PASSED] write
[06:16:51] [PASSED] read
[06:16:51] [PASSED] bookkeep
[06:16:51] ============= [PASSED] test_for_each_unlocked ==============
[06:16:51] ===================== test_get_fences =====================
[06:16:51] [PASSED] kernel
[06:16:51] [PASSED] write
[06:16:51] [PASSED] read
[06:16:51] [PASSED] bookkeep
[06:16:51] ================= [PASSED] test_get_fences =================
[06:16:51] ================== [PASSED] dma-buf-resv ===================
[06:16:51] ============================================================
[06:16:51] Testing complete. Ran 51 tests: passed: 50, skipped: 1
[06:16:51] Elapsed time: 15.943s total, 1.859s configuring, 8.813s building, 5.261s running
+ cleanup
++ stat -c %u:%g /kernel
+ chown -R 1003:1003 /kernel
^ permalink raw reply [flat|nested] 23+ messages in thread
* Re: [PATCH v5 6/7] drm/xe: capture L3 node status registers in devcoredump
2026-10-23 6:05 ` [PATCH v5 6/7] drm/xe: capture L3 node status registers in devcoredump Nareshkumar Gollakoti
@ 2026-10-23 6:24 ` sashiko-bot
0 siblings, 0 replies; 23+ messages in thread
From: sashiko-bot @ 2026-10-23 6:24 UTC (permalink / raw)
To: Nareshkumar Gollakoti, intel-xe
Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [Medium] drm/xe: unconditional MCR read of L3_NODE_IDLE in devcoredump warns on Xe_LP
--
commit a9405a6ae4ac2ac19e20c8fe6b73ddfd266de12d
Author: Nareshkumar Gollakoti <naresh.kumar.g@intel.com>
drm/xe: capture L3 node status registers in devcoredump
This commit adds the L3_NODE_IDLE and L3STAT_LBCF_GFX register definitions
and includes them as a node status section in the devcoredump snapshot. It
also extends struct xe_reg_desc to support MCR registers so they can be read
via xe_gt_mcr_unicast_read_any() during snapshot capture.
> diff --git a/drivers/gpu/drm/xe/regs/xe_gt_regs.h b/drivers/gpu/drm/xe/regs/xe_gt_regs.h
> index 2e4cb4957479f..55f0eee4e20e8 100644
> --- a/drivers/gpu/drm/xe/regs/xe_gt_regs.h
> +++ b/drivers/gpu/drm/xe/regs/xe_gt_regs.h
> @@ -454,6 +454,9 @@
> #define L3_ESC_MASK REG_BIT(0)
> #define L3_ESC(value) REG_FIELD_PREP(L3_ESC_MASK, value)
>
> +#define L3_NODE_IDLE XE_REG_MCR(0xb0b0)
> +#define L3STAT_LBCF_GFX XE_REG_MCR(0xb128)
> +
> #define XEHP_L3NODEARBCFG XE_REG_MCR(0xb0b4)
> #define XEHP_LNESPARE REG_BIT(19)
>
> diff --git a/drivers/gpu/drm/xe/xe_devcoredump.c b/drivers/gpu/drm/xe/xe_devcoredump.c
> index 8d59f80e2929f..de9ef3e0cb5dd 100644
> --- a/drivers/gpu/drm/xe/xe_devcoredump.c
> +++ b/drivers/gpu/drm/xe/xe_devcoredump.c
[ ... ]
> @@ -119,6 +121,11 @@ static const struct xe_reg_desc xe_dbg_gam_pf_reglist[] = {
> XE_REG_DESC(PAGE_FLTRPTQ_TAIL_GAMCTRL, "PAGE_FLTRPTQ_TAIL_GAMCTRL"),
> };
>
> +static const struct xe_reg_desc xe_dbg_l3_node_reglist[] = {
> + XE_REG_DESC_MCR(L3_NODE_IDLE, "L3_NODE_IDLE"),
> + XE_REG_DESC_MCR(L3STAT_LBCF_GFX, "L3STAT_LBCF_GFX"),
> +};
[ ... ]
> @@ -262,8 +275,13 @@ xe_dbg_reg_snapshot_capture_target(struct xe_gt *gt,
>
> snap->desc = reglist;
> snap->num_regs = reglist->num_regs;
> - for (i = 0; i < reglist->num_regs; i++)
> - snap->values[i] = xe_mmio_read32(>->mmio, reglist->regs[i].reg);
> + for (i = 0; i < reglist->num_regs; i++) {
> + if (reglist->regs[i].reg.mcr)
> + snap->values[i] = xe_gt_mcr_unicast_read_any(gt,
> + reglist->regs[i].mcr_reg);
> + else
> + snap->values[i] = xe_mmio_read32(>->mmio, reglist->regs[i].reg);
> + }
>
> return snap;
> }
[ ... ]
> @@ -602,6 +625,10 @@ static void xe_devcoredump_capture_gt_regs(struct xe_devcoredump_snapshot *ss,
> other_gt,
> XE_DBG_REGSET_GAM_PF,
> XE_GT_TYPE_MAIN);
> + ss->ns = xe_dbg_gt_snapshot_capture(gt,
> + other_gt,
> + XE_DBG_REGSET_L3_NODE,
> + XE_GT_TYPE_MAIN);
> }
[Severity: Medium]
Will capturing XE_DBG_REGSET_L3_NODE unconditionally on all platforms trigger
a kernel warning in xe_gt_mcr_get_nonterminated_steering() when a devcoredump
is taken on Xe_LP platforms (such as TGL, RKL, DG1, or ADL)?
L3_NODE_IDLE is defined at offset 0xb0b0 with XE_REG_MCR(), which statically
sets reg.mcr = 1 in xe_dbg_l3_node_reglist[]. During a GPU hang or job
timeout, the capture path runs:
devcoredump_snapshot()
-> xe_devcoredump_capture_gt_regs()
-> xe_dbg_gt_snapshot_capture()
-> xe_dbg_reg_snapshot_capture_target()
-> xe_gt_mcr_unicast_read_any(gt, L3_NODE_IDLE)
-> xe_gt_mcr_get_nonterminated_steering()
However, on pre-Xe_HP platforms (GRAPHICS_VERx100(xe) < 1250), the
0x00b000-0x00b0ff LNCF/NODE range is not an MCR range. In
drivers/gpu/drm/xe/xe_gt_mcr.c:xe_gt_mcr_init_early(), only the L3BANK
(0x00b100-0x00b3ff) and DSS steering tables are registered:
} else {
gt->steering[L3BANK].ranges = xelp_l3bank_steering_table;
gt->steering[DSS].ranges = xelp_dss_steering_table;
}
When xe_gt_mcr_get_nonterminated_steering() looks up 0xb0b0 on those
platforms, it does not find it in any steering table, fires xe_gt_WARN(), and
steers MCR_SELECTOR to (0, 0) for a non-MCR register:
xe_gt_WARN(gt, true,
"Did not find MCR register %#x in any MCR steering table\n",
reg.addr);
*group = 0;
*instance = 0;
Should xe_dbg_reg_snapshot_capture_target() check xe_gt_mcr_check_reg() (or
should XE_DBG_REGSET_L3_NODE capture be gated on platform version) before
calling xe_gt_mcr_unicast_read_any()?
--
Sashiko AI review · https://sashiko.dev/#/patchset/20261023060554.2643515-1-naresh.kumar.g@intel.com?part=6
^ permalink raw reply [flat|nested] 23+ messages in thread
* Re: [PATCH v5 7/7] drm/xe/guc: capture additional engine state registers
2026-10-23 6:05 ` [PATCH v5 7/7] drm/xe/guc: capture additional engine state registers Nareshkumar Gollakoti
@ 2026-10-23 6:26 ` sashiko-bot
2026-10-26 9:15 ` Upadhyay, Tejas
1 sibling, 0 replies; 23+ messages in thread
From: sashiko-bot @ 2026-10-23 6:26 UTC (permalink / raw)
To: Nareshkumar Gollakoti, intel-xe
Thank you for your contribution! Sashiko AI review found 2 potential issue(s) to consider:
- [Medium] drm/xe/guc: unused FF_SLICE_CS_CHICKEN2 definition and missing capture entry
- [Medium] drm/xe/guc: use xe3p_blt_inst_regs for GUC_CAPTURE_LIST_CLASS_PAGING on Xe3p
--
commit 3bf1615b3ab8603f52d531a35c295135f10f2aa4
Author: Nareshkumar Gollakoti <naresh.kumar.g@intel.com>
drm/xe/guc: capture additional engine state registers
This commit defines additional engine state register offsets in
xe_engine_regs.h and includes them in the GuC error capture lists for Xe3p
render/compute and blitter engines, while also splitting out xe2_extregs[]
for steered register capture.
> diff --git a/drivers/gpu/drm/xe/regs/xe_engine_regs.h b/drivers/gpu/drm/xe/regs/xe_engine_regs.h
> index 94033982e6944..9f328b1b18f57 100644
> --- a/drivers/gpu/drm/xe/regs/xe_engine_regs.h
> +++ b/drivers/gpu/drm/xe/regs/xe_engine_regs.h
[ ... ]
> @@ -123,15 +128,21 @@
> #define FF_SLICE_CS_CHICKEN1(base) XE_REG((base) + 0xe0, XE_REG_OPTION_MASKED)
> #define FFSC_PERCTX_PREEMPT_CTRL REG_BIT(14)
>
> +#define FF_SLICE_CS_CHICKEN2(base) XE_REG((base) + 0xe4, XE_REG_OPTION_MASKED)
[ ... ]
> diff --git a/drivers/gpu/drm/xe/xe_guc_capture.c b/drivers/gpu/drm/xe/xe_guc_capture.c
> index 6a20eab0f8204..2e13df97e1068 100644
> --- a/drivers/gpu/drm/xe/xe_guc_capture.c
> +++ b/drivers/gpu/drm/xe/xe_guc_capture.c
[ ... ]
> @@ -200,6 +230,15 @@ static const struct __guc_mmio_reg_descr xe_lp_gsc_inst_regs[] = {
> static const struct __guc_mmio_reg_descr xe3p_rc_inst_regs[] = {
> COMMON_BASE_ENGINE_INSTANCE,
> XE3P_BASE_ENGINE_INSTANCE,
> + XE3P_CS_DEBUG_INSTANCE,
> + XE3P_RC_CS_PREEMPT_INSTANCE,
> +};
[Severity: Medium]
Was FF_SLICE_CS_CHICKEN2 (along with FF_SLICE_CS_CHICKEN1) accidentally
dropped from xe3p_rc_inst_regs[] in drivers/gpu/drm/xe/xe_guc_capture.c?
The commit message notes that the new register definitions in
drivers/gpu/drm/xe/regs/xe_engine_regs.h are included in the GuC capture
list, and the v3 changelog specifically mentions adding
XE3P_RC_SLICE_INSTANCE with FF_SLICE_CS_CHICKEN1 and FF_SLICE_CS_CHICKEN2 to
xe3p_rc_inst_regs[].
However, XE3P_RC_SLICE_INSTANCE is absent from drivers/gpu/drm/xe/xe_guc_capture.c,
which leaves FF_SLICE_CS_CHICKEN2 completely unused and omits both registers
when GuC error capture initializes xe3p_rc_inst_regs[] for
GUC_CAPTURE_LIST_CLASS_RENDER_COMPUTE.
> +
> +/* Xe3p Blitter Per-Engine-Instance */
> +static const struct __guc_mmio_reg_descr xe3p_blt_inst_regs[] = {
> + XE_BLT_INST_REGS,
> + XE3P_CS_DEBUG_INSTANCE,
> + XE3P_BCS_ONLY_INSTANCE,
> };
>
> /*
> @@ -264,7 +303,7 @@ static const struct __guc_mmio_reg_descr_group xe3p_lists[] = {
> MAKE_REGLIST(xe_vec_class_regs, PF, ENGINE_CLASS, GUC_CAPTURE_LIST_CLASS_VIDEOENHANCE),
> MAKE_REGLIST(xe_vec_inst_regs, PF, ENGINE_INSTANCE, GUC_CAPTURE_LIST_CLASS_VIDEOENHANCE),
> MAKE_REGLIST(empty_regs_list, PF, ENGINE_CLASS, GUC_CAPTURE_LIST_CLASS_BLITTER),
> - MAKE_REGLIST(xe_blt_inst_regs, PF, ENGINE_INSTANCE, GUC_CAPTURE_LIST_CLASS_BLITTER),
> + MAKE_REGLIST(xe3p_blt_inst_regs, PF, ENGINE_INSTANCE, GUC_CAPTURE_LIST_CLASS_BLITTER),
> MAKE_REGLIST(empty_regs_list, PF, ENGINE_CLASS, GUC_CAPTURE_LIST_CLASS_GSC_OTHER),
> MAKE_REGLIST(xe_lp_gsc_inst_regs, PF, ENGINE_INSTANCE, GUC_CAPTURE_LIST_CLASS_GSC_OTHER),
> MAKE_REGLIST(empty_regs_list, PF, ENGINE_CLASS, GUC_CAPTURE_LIST_CLASS_PAGING),
[Severity: Medium]
Should the GUC_CAPTURE_LIST_CLASS_PAGING entry right below this in
xe3p_lists[] also be updated from xe_blt_inst_regs to xe3p_blt_inst_regs?
In drivers/gpu/drm/xe/xe_guc_capture.c:xe3p_lists[]:
MAKE_REGLIST(empty_regs_list, PF, ENGINE_CLASS, GUC_CAPTURE_LIST_CLASS_BLITTER),
MAKE_REGLIST(xe3p_blt_inst_regs, PF, ENGINE_INSTANCE, GUC_CAPTURE_LIST_CLASS_BLITTER),
MAKE_REGLIST(empty_regs_list, PF, ENGINE_CLASS, GUC_CAPTURE_LIST_CLASS_GSC_OTHER),
MAKE_REGLIST(xe_lp_gsc_inst_regs, PF, ENGINE_INSTANCE, GUC_CAPTURE_LIST_CLASS_GSC_OTHER),
MAKE_REGLIST(empty_regs_list, PF, ENGINE_CLASS, GUC_CAPTURE_LIST_CLASS_PAGING),
MAKE_REGLIST(xe_blt_inst_regs, PF, ENGINE_INSTANCE, GUC_CAPTURE_LIST_CLASS_PAGING),
When xe_guc_has_paging_engine() in drivers/gpu/drm/xe/xe_guc.c is true on
Xe3p platforms, xe_hwe_to_guc_class() maps the USM-reserved physical BCS
engine (gt->usm.paging_hwe0) to GUC_PAGING_CLASS, which
xe_hwe_to_guc_capture_class() maps to GUC_CAPTURE_LIST_CLASS_PAGING.
Leaving GUC_CAPTURE_LIST_CLASS_PAGING pointing to xe_blt_inst_regs means
both ADS capture list population (guc_capture_prep_lists() ->
xe_guc_capture_getlist()) and manual engine snapshots
(xe_engine_manual_capture() -> xe_guc_capture_get_reg_desc_list()) for the
paging BCS engine will omit XE3P_CS_DEBUG_INSTANCE and
XE3P_BCS_ONLY_INSTANCE.
--
Sashiko AI review · https://sashiko.dev/#/patchset/20261023060554.2643515-1-naresh.kumar.g@intel.com?part=7
^ permalink raw reply [flat|nested] 23+ messages in thread
* Re: [PATCH v5 4/7] drm/xe: dump GAM page fault report registers in devcoredump
2026-10-23 6:05 ` [PATCH v5 4/7] drm/xe: dump GAM page fault report registers in devcoredump Nareshkumar Gollakoti
@ 2026-10-23 6:31 ` sashiko-bot
2026-10-26 6:48 ` Upadhyay, Tejas
1 sibling, 0 replies; 23+ messages in thread
From: sashiko-bot @ 2026-10-23 6:31 UTC (permalink / raw)
To: Nareshkumar Gollakoti, intel-xe
Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [Medium] drm/xe: unsteered MCR read of GAMCTRL PF queue registers in devcoredump
--
commit 1da764eb534ebe0a6ed34a1262b84f79a5f87633
Author: Nareshkumar Gollakoti <naresh.kumar.g@intel.com>
drm/xe: dump GAM page fault report registers in devcoredump
This commit adds definitions for PAGE_FLTRPTQ_HEAD_GAMCTRL and
PAGE_FLTRPTQ_TAIL_GAMCTRL and captures them during devcoredump snapshots.
It also prints the captured values in the devcoredump output along with a
page fault notice when the head and tail registers differ.
> diff --git a/drivers/gpu/drm/xe/regs/xe_gt_regs.h b/drivers/gpu/drm/xe/regs/xe_gt_regs.h
> index e93895e0c731a..e9eb0bd04af10 100644
> --- a/drivers/gpu/drm/xe/regs/xe_gt_regs.h
> +++ b/drivers/gpu/drm/xe/regs/xe_gt_regs.h
> @@ -530,6 +530,9 @@
> #define LMEM_EN REG_BIT(31)
> #define LMTT_DIR_PTR REG_GENMASK(30, 0) /* in multiples of 64KB */
>
> +#define PAGE_FLTRPTQ_HEAD_GAMCTRL XE_REG(0xcf90)
> +#define PAGE_FLTRPTQ_TAIL_GAMCTRL XE_REG(0xcf94)
> +
> #define HALF_SLICE_CHICKEN5 XE_REG_MCR(0xe188, XE_REG_OPTION_MASKED)
> #define DISABLE_SAMPLE_G_PERFORMANCE REG_BIT(0)
>
> diff --git a/drivers/gpu/drm/xe/xe_devcoredump.c b/drivers/gpu/drm/xe/xe_devcoredump.c
> index 49a7c020a1615..8d59f80e2929f 100644
> --- a/drivers/gpu/drm/xe/xe_devcoredump.c
> +++ b/drivers/gpu/drm/xe/xe_devcoredump.c
> @@ -114,6 +114,11 @@ static const struct xe_reg_desc xe_dbg_media_gt_rpm_reglist[] = {
> XE_REG_DESC(RPM_GCD, "RPM_GCD"),
> };
>
> +static const struct xe_reg_desc xe_dbg_gam_pf_reglist[] = {
> + XE_REG_DESC(PAGE_FLTRPTQ_HEAD_GAMCTRL, "PAGE_FLTRPTQ_HEAD_GAMCTRL"),
> + XE_REG_DESC(PAGE_FLTRPTQ_TAIL_GAMCTRL, "PAGE_FLTRPTQ_TAIL_GAMCTRL"),
> +};
[Severity: Medium]
Should PAGE_FLTRPTQ_HEAD_GAMCTRL (0xcf90) and PAGE_FLTRPTQ_TAIL_GAMCTRL
(0xcf94) be defined as MCR registers with XE_REG_MCR() and captured via
steered MCR reads instead of raw xe_mmio_read32()?
In drivers/gpu/drm/xe/xe_gt_mcr.c, the 0x00C800 to 0x00CFFF GAM/GAMCTRL
range is listed in the INSTANCE0 steering tables across Xe platforms (such
as xehpc_instance0_steering_table, xelpg_instance0_steering_table,
xe2lpg_instance0_steering_table, xe3p_lpg_instance0_steering_table, and
xe3p_xpc_instance0_steering_table):
drivers/gpu/drm/xe/xe_gt_mcr.c:
{ 0x00C800, 0x00CFFF }, /* GAMCTRL */
Because rw_with_mcr_steering() leaves the last-used group and instance
programmed in MCR_SELECTOR / MTL_MCR_SELECTOR (and on GRAPHICS_VERx100(xe)
>= 1270, MTL_MCR_SELECTOR is shared with GuC and serialized via
gt->mcr_lock and STEER_SEMAPHORE), reading these registers in
devcoredump_snapshot() -> xe_devcoredump_capture_gt_regs() ->
xe_dbg_gt_snapshot_capture() -> xe_dbg_reg_snapshot_capture_target() via
unsteered xe_mmio_read32() can race with concurrent MCR steering or target
a terminated non-(0, 0) GAMCTRL instance. When that happens, both reads
return 0x00000000 and xe_gam_pf_snapshot_print() will not print the page
fault message even if a fault occurred.
Even with the subsequent patch in the series ("drm/xe: capture L3 node
status registers in devcoredump") adding XE_REG_DESC_MCR() and updating
xe_dbg_reg_snapshot_capture_target() to call xe_gt_mcr_unicast_read_any()
for MCR descriptors, PAGE_FLTRPTQ_HEAD_GAMCTRL and
PAGE_FLTRPTQ_TAIL_GAMCTRL remain defined with XE_REG() and XE_REG_DESC(),
so they still bypass xe_gt_mcr_unicast_read_any().
Additionally, on Xe3p+ platforms where xe_guc_using_main_gamctrl_queues()
is true (GT_VER(gt) >= 35), xe_guc_upload() switches hardware and GuC to
the unicast Main GAMCTRL queues:
drivers/gpu/drm/xe/xe_guc.c:xe_guc_upload() {
if (xe_guc_using_main_gamctrl_queues(guc))
xe_mmio_write32(>->mmio, MAIN_GAMCTRL_MODE, MAIN_GAMCTRL_QUEUE_SELECT);
}
On those platforms, are 0xcf90 and 0xcf94 still the active page fault
reporting queue registers to capture in xe_devcoredump_capture_gt_regs()?
--
Sashiko AI review · https://sashiko.dev/#/patchset/20261023060554.2643515-1-naresh.kumar.g@intel.com?part=4
^ permalink raw reply [flat|nested] 23+ messages in thread
* ✓ Xe.CI.BAT: success for drm/xe: Capture additional HW register state in devcoredump (rev6)
2026-10-23 6:05 [PATCH v5 0/7] drm/xe: Capture additional HW register state in devcoredump Nareshkumar Gollakoti
` (8 preceding siblings ...)
2026-10-23 6:16 ` ✓ CI.KUnit: success " Patchwork
@ 2026-10-23 6:56 ` Patchwork
2026-10-23 8:26 ` ✗ Xe.CI.FULL: failure " Patchwork
10 siblings, 0 replies; 23+ messages in thread
From: Patchwork @ 2026-10-23 6:56 UTC (permalink / raw)
To: Nareshkumar Gollakoti; +Cc: intel-xe
[-- Attachment #1: Type: text/plain, Size: 936 bytes --]
== Series Details ==
Series: drm/xe: Capture additional HW register state in devcoredump (rev6)
URL : https://patchwork.freedesktop.org/series/172150/
State : success
== Summary ==
CI Bug Log - changes from xe-6001-55c6bb0b4d006ee415abe9f048014f7bcc90ae6f_BAT -> xe-pw-172150v6_BAT
====================================================
Summary
-------
**SUCCESS**
No regressions found.
Participating hosts (15 -> 15)
------------------------------
No changes in participating hosts
Changes
-------
No changes found
Build changes
-------------
* IGT: IGT_9159 -> IGT_9160
* Linux: xe-6001-55c6bb0b4d006ee415abe9f048014f7bcc90ae6f -> xe-pw-172150v6
IGT_9159: 9159
IGT_9160: 9160
xe-6001-55c6bb0b4d006ee415abe9f048014f7bcc90ae6f: 55c6bb0b4d006ee415abe9f048014f7bcc90ae6f
xe-pw-172150v6: 172150v6
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-172150v6/index.html
[-- Attachment #2: Type: text/html, Size: 1498 bytes --]
^ permalink raw reply [flat|nested] 23+ messages in thread
* ✗ Xe.CI.FULL: failure for drm/xe: Capture additional HW register state in devcoredump (rev6)
2026-10-23 6:05 [PATCH v5 0/7] drm/xe: Capture additional HW register state in devcoredump Nareshkumar Gollakoti
` (9 preceding siblings ...)
2026-10-23 6:56 ` ✓ Xe.CI.BAT: " Patchwork
@ 2026-10-23 8:26 ` Patchwork
10 siblings, 0 replies; 23+ messages in thread
From: Patchwork @ 2026-10-23 8:26 UTC (permalink / raw)
To: Nareshkumar Gollakoti; +Cc: intel-xe
[-- Attachment #1: Type: text/plain, Size: 45550 bytes --]
== Series Details ==
Series: drm/xe: Capture additional HW register state in devcoredump (rev6)
URL : https://patchwork.freedesktop.org/series/172150/
State : failure
== Summary ==
CI Bug Log - changes from xe-6001-55c6bb0b4d006ee415abe9f048014f7bcc90ae6f_FULL -> xe-pw-172150v6_FULL
====================================================
Summary
-------
**FAILURE**
Serious unknown changes coming with xe-pw-172150v6_FULL absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in xe-pw-172150v6_FULL, please notify your bug team (I915-ci-infra@lists.freedesktop.org) to allow them
to document this new failure mode, which will reduce false positives in CI.
Participating hosts (3 -> 3)
------------------------------
No changes in participating hosts
Possible new issues
-------------------
Here are the unknown changes that may have been introduced in xe-pw-172150v6_FULL:
### IGT changes ###
#### Possible regressions ####
* igt@kms_async_flips@async-flip-dpms:
- shard-bmg: [PASS][1] -> [DMESG-WARN][2] +1 other test dmesg-warn
[1]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-6001-55c6bb0b4d006ee415abe9f048014f7bcc90ae6f/shard-bmg-1/igt@kms_async_flips@async-flip-dpms.html
[2]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-172150v6/shard-bmg-5/igt@kms_async_flips@async-flip-dpms.html
New tests
---------
New tests have been introduced between xe-6001-55c6bb0b4d006ee415abe9f048014f7bcc90ae6f_FULL and xe-pw-172150v6_FULL:
### New IGT tests (2) ###
* igt@xe_oa@tail-address-wrap@oam-2-1m:
- Statuses : 1 pass(s)
- Exec time: [0.12] s
* igt@xe_oa@tail-address-wrap@sag-1-1m:
- Statuses : 1 pass(s)
- Exec time: [0.12] s
Known issues
------------
Here are the changes found in xe-pw-172150v6_FULL that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@intel_hwmon@hwmon-read:
- shard-ptl: NOTRUN -> [SKIP][3] ([Intel XE#7225])
[3]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-172150v6/shard-ptl-3/igt@intel_hwmon@hwmon-read.html
* igt@intel_hwmon@hwmon-write:
- shard-bmg: [PASS][4] -> [FAIL][5] ([Intel XE#8583])
[4]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-6001-55c6bb0b4d006ee415abe9f048014f7bcc90ae6f/shard-bmg-5/igt@intel_hwmon@hwmon-write.html
[5]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-172150v6/shard-bmg-7/igt@intel_hwmon@hwmon-write.html
* igt@kms_big_fb@4-tiled-64bpp-rotate-270:
- shard-bmg: NOTRUN -> [SKIP][6] ([Intel XE#2327])
[6]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-172150v6/shard-bmg-10/igt@kms_big_fb@4-tiled-64bpp-rotate-270.html
* igt@kms_big_fb@4-tiled-max-hw-stride-32bpp-rotate-180-hflip-async-flip:
- shard-ptl: NOTRUN -> [SKIP][7] ([Intel XE#6925])
[7]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-172150v6/shard-ptl-3/igt@kms_big_fb@4-tiled-max-hw-stride-32bpp-rotate-180-hflip-async-flip.html
* igt@kms_big_fb@linear-16bpp-rotate-90:
- shard-ptl: NOTRUN -> [SKIP][8] ([Intel XE#5901]) +1 other test skip
[8]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-172150v6/shard-ptl-6/igt@kms_big_fb@linear-16bpp-rotate-90.html
* igt@kms_big_fb@linear-max-hw-stride-64bpp-rotate-180-hflip:
- shard-bmg: NOTRUN -> [SKIP][9] ([Intel XE#7059] / [Intel XE#7085])
[9]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-172150v6/shard-bmg-9/igt@kms_big_fb@linear-max-hw-stride-64bpp-rotate-180-hflip.html
- shard-ptl: NOTRUN -> [SKIP][10] ([Intel XE#7085])
[10]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-172150v6/shard-ptl-1/igt@kms_big_fb@linear-max-hw-stride-64bpp-rotate-180-hflip.html
* igt@kms_big_fb@x-tiled-8bpp-rotate-180:
- shard-lnl: [PASS][11] -> [ABORT][12] ([Intel XE#4760])
[11]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-6001-55c6bb0b4d006ee415abe9f048014f7bcc90ae6f/shard-lnl-6/igt@kms_big_fb@x-tiled-8bpp-rotate-180.html
[12]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-172150v6/shard-lnl-8/igt@kms_big_fb@x-tiled-8bpp-rotate-180.html
* igt@kms_big_fb@y-tiled-addfb-size-offset-overflow:
- shard-bmg: NOTRUN -> [SKIP][13] ([Intel XE#607] / [Intel XE#7361])
[13]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-172150v6/shard-bmg-9/igt@kms_big_fb@y-tiled-addfb-size-offset-overflow.html
- shard-ptl: NOTRUN -> [SKIP][14] ([Intel XE#5851])
[14]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-172150v6/shard-ptl-1/igt@kms_big_fb@y-tiled-addfb-size-offset-overflow.html
* igt@kms_big_fb@y-tiled-addfb-size-overflow:
- shard-ptl: NOTRUN -> [SKIP][15] ([Intel XE#5855])
[15]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-172150v6/shard-ptl-3/igt@kms_big_fb@y-tiled-addfb-size-overflow.html
* igt@kms_big_fb@yf-tiled-64bpp-rotate-90:
- shard-bmg: NOTRUN -> [SKIP][16] ([Intel XE#1124]) +1 other test skip
[16]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-172150v6/shard-bmg-4/igt@kms_big_fb@yf-tiled-64bpp-rotate-90.html
* igt@kms_big_fb@yf-tiled-max-hw-stride-32bpp-rotate-180-hflip-async-flip:
- shard-ptl: NOTRUN -> [SKIP][17] ([Intel XE#5808]) +9 other tests skip
[17]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-172150v6/shard-ptl-5/igt@kms_big_fb@yf-tiled-max-hw-stride-32bpp-rotate-180-hflip-async-flip.html
* igt@kms_bw@connected-linear-tiling-2-displays-target-2560x1440p:
- shard-ptl: NOTRUN -> [SKIP][18] ([Intel XE#7679])
[18]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-172150v6/shard-ptl-6/igt@kms_bw@connected-linear-tiling-2-displays-target-2560x1440p.html
* igt@kms_bw@linear-tiling-1-displays-target-1920x1080p:
- shard-bmg: NOTRUN -> [SKIP][19] ([Intel XE#367])
[19]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-172150v6/shard-bmg-1/igt@kms_bw@linear-tiling-1-displays-target-1920x1080p.html
* igt@kms_bw@linear-tiling-4-displays-target-3840x2160p:
- shard-ptl: NOTRUN -> [SKIP][20] ([Intel XE#367])
[20]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-172150v6/shard-ptl-1/igt@kms_bw@linear-tiling-4-displays-target-3840x2160p.html
* igt@kms_ccs@crc-primary-basic-4-tiled-mtl-rc-ccs:
- shard-bmg: NOTRUN -> [SKIP][21] ([Intel XE#2887]) +3 other tests skip
[21]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-172150v6/shard-bmg-5/igt@kms_ccs@crc-primary-basic-4-tiled-mtl-rc-ccs.html
* igt@kms_ccs@crc-primary-rotation-180-4-tiled-lnl-ccs@pipe-b-dp-2:
- shard-bmg: NOTRUN -> [SKIP][22] ([Intel XE#2652]) +3 other tests skip
[22]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-172150v6/shard-bmg-1/igt@kms_ccs@crc-primary-rotation-180-4-tiled-lnl-ccs@pipe-b-dp-2.html
* igt@kms_ccs@crc-primary-rotation-180-y-tiled-gen12-mc-ccs:
- shard-ptl: NOTRUN -> [SKIP][23] ([Intel XE#5822]) +12 other tests skip
[23]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-172150v6/shard-ptl-5/igt@kms_ccs@crc-primary-rotation-180-y-tiled-gen12-mc-ccs.html
* igt@kms_ccs@crc-primary-suspend-4-tiled-bmg-ccs@pipe-a-edp-1:
- shard-ptl: NOTRUN -> [SKIP][24] ([Intel XE#5823] / [Intel XE#6918]) +4 other tests skip
[24]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-172150v6/shard-ptl-4/igt@kms_ccs@crc-primary-suspend-4-tiled-bmg-ccs@pipe-a-edp-1.html
* igt@kms_ccs@crc-primary-suspend-4-tiled-mtl-mc-ccs:
- shard-bmg: NOTRUN -> [SKIP][25] ([Intel XE#3432]) +1 other test skip
[25]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-172150v6/shard-bmg-8/igt@kms_ccs@crc-primary-suspend-4-tiled-mtl-mc-ccs.html
* igt@kms_chamelium_color@ctm-negative:
- shard-ptl: NOTRUN -> [SKIP][26] ([Intel XE#5824]) +1 other test skip
[26]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-172150v6/shard-ptl-5/igt@kms_chamelium_color@ctm-negative.html
* igt@kms_chamelium_edid@dp-edid-change-during-hibernate:
- shard-ptl: NOTRUN -> [SKIP][27] ([Intel XE#2252]) +5 other tests skip
[27]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-172150v6/shard-ptl-8/igt@kms_chamelium_edid@dp-edid-change-during-hibernate.html
* igt@kms_chamelium_edid@dp-edid-resolution-list:
- shard-bmg: NOTRUN -> [SKIP][28] ([Intel XE#2252]) +1 other test skip
[28]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-172150v6/shard-bmg-7/igt@kms_chamelium_edid@dp-edid-resolution-list.html
* igt@kms_chamelium_sharpness_filter@filter-basic:
- shard-ptl: NOTRUN -> [SKIP][29] ([Intel XE#6507])
[29]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-172150v6/shard-ptl-1/igt@kms_chamelium_sharpness_filter@filter-basic.html
* igt@kms_content_protection@dp-mst-type-1:
- shard-bmg: NOTRUN -> [SKIP][30] ([Intel XE#2390] / [Intel XE#6974])
[30]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-172150v6/shard-bmg-1/igt@kms_content_protection@dp-mst-type-1.html
- shard-ptl: NOTRUN -> [SKIP][31] ([Intel XE#5832] / [Intel XE#6974])
[31]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-172150v6/shard-ptl-1/igt@kms_content_protection@dp-mst-type-1.html
* igt@kms_content_protection@legacy:
- shard-ptl: NOTRUN -> [SKIP][32] ([Intel XE#7642]) +2 other tests skip
[32]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-172150v6/shard-ptl-2/igt@kms_content_protection@legacy.html
* igt@kms_cursor_crc@cursor-offscreen-256x85:
- shard-bmg: NOTRUN -> [SKIP][33] ([Intel XE#2320])
[33]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-172150v6/shard-bmg-1/igt@kms_cursor_crc@cursor-offscreen-256x85.html
* igt@kms_cursor_crc@cursor-random-128x42:
- shard-ptl: NOTRUN -> [SKIP][34] ([Intel XE#5900]) +1 other test skip
[34]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-172150v6/shard-ptl-3/igt@kms_cursor_crc@cursor-random-128x42.html
* igt@kms_cursor_legacy@cursora-vs-flipb-atomic-transitions-varying-size:
- shard-ptl: NOTRUN -> [SKIP][35] ([Intel XE#5962]) +1 other test skip
[35]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-172150v6/shard-ptl-8/igt@kms_cursor_legacy@cursora-vs-flipb-atomic-transitions-varying-size.html
* igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions:
- shard-bmg: [PASS][36] -> [FAIL][37] ([Intel XE#7809])
[36]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-6001-55c6bb0b4d006ee415abe9f048014f7bcc90ae6f/shard-bmg-6/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions.html
[37]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-172150v6/shard-bmg-6/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions.html
* igt@kms_display_modes@extended-mode-basic:
- shard-ptl: NOTRUN -> [SKIP][38] ([Intel XE#4302])
[38]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-172150v6/shard-ptl-7/igt@kms_display_modes@extended-mode-basic.html
* igt@kms_dsc@dsc-with-bpc-bigjoiner:
- shard-bmg: NOTRUN -> [SKIP][39] ([Intel XE#8265]) +2 other tests skip
[39]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-172150v6/shard-bmg-3/igt@kms_dsc@dsc-with-bpc-bigjoiner.html
* igt@kms_dsc@dsc-with-output-formats-with-bpc:
- shard-ptl: NOTRUN -> [SKIP][40] ([Intel XE#5907]) +3 other tests skip
[40]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-172150v6/shard-ptl-4/igt@kms_dsc@dsc-with-output-formats-with-bpc.html
* igt@kms_flip@2x-dpms-vs-vblank-race-interruptible:
- shard-ptl: NOTRUN -> [SKIP][41] ([Intel XE#2316]) +2 other tests skip
[41]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-172150v6/shard-ptl-7/igt@kms_flip@2x-dpms-vs-vblank-race-interruptible.html
* igt@kms_flip@2x-flip-vs-blocking-wf-vblank:
- shard-bmg: [PASS][42] -> [FAIL][43] ([Intel XE#5408] / [Intel XE#6266]) +1 other test fail
[42]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-6001-55c6bb0b4d006ee415abe9f048014f7bcc90ae6f/shard-bmg-1/igt@kms_flip@2x-flip-vs-blocking-wf-vblank.html
[43]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-172150v6/shard-bmg-5/igt@kms_flip@2x-flip-vs-blocking-wf-vblank.html
* igt@kms_flip@flip-vs-expired-vblank@c-edp1:
- shard-lnl: [PASS][44] -> [FAIL][45] ([Intel XE#301] / [Intel XE#3149]) +1 other test fail
[44]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-6001-55c6bb0b4d006ee415abe9f048014f7bcc90ae6f/shard-lnl-5/igt@kms_flip@flip-vs-expired-vblank@c-edp1.html
[45]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-172150v6/shard-lnl-2/igt@kms_flip@flip-vs-expired-vblank@c-edp1.html
* igt@kms_flip_scaled_crc@flip-32bpp-yftile-to-64bpp-yftile-downscaling:
- shard-ptl: NOTRUN -> [SKIP][46] ([Intel XE#7178]) +3 other tests skip
[46]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-172150v6/shard-ptl-6/igt@kms_flip_scaled_crc@flip-32bpp-yftile-to-64bpp-yftile-downscaling.html
- shard-bmg: NOTRUN -> [SKIP][47] ([Intel XE#7178] / [Intel XE#7351])
[47]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-172150v6/shard-bmg-3/igt@kms_flip_scaled_crc@flip-32bpp-yftile-to-64bpp-yftile-downscaling.html
* igt@kms_flip_scaled_crc@flip-64bpp-linear-to-32bpp-linear-downscaling:
- shard-ptl: NOTRUN -> [SKIP][48] ([Intel XE#5828]) +3 other tests skip
[48]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-172150v6/shard-ptl-1/igt@kms_flip_scaled_crc@flip-64bpp-linear-to-32bpp-linear-downscaling.html
* igt@kms_flip_scaled_crc@flip-p016-linear-to-p016-linear-reflect-x:
- shard-bmg: NOTRUN -> [SKIP][49] ([Intel XE#7179])
[49]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-172150v6/shard-bmg-4/igt@kms_flip_scaled_crc@flip-p016-linear-to-p016-linear-reflect-x.html
- shard-ptl: NOTRUN -> [SKIP][50] ([Intel XE#7179])
[50]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-172150v6/shard-ptl-7/igt@kms_flip_scaled_crc@flip-p016-linear-to-p016-linear-reflect-x.html
* igt@kms_frontbuffer_tracking@drrs-rgb101010-draw-mmap-wc:
- shard-ptl: NOTRUN -> [SKIP][51] ([Intel XE#5800] / [Intel XE#6312]) +8 other tests skip
[51]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-172150v6/shard-ptl-3/igt@kms_frontbuffer_tracking@drrs-rgb101010-draw-mmap-wc.html
* igt@kms_frontbuffer_tracking@fbc-2p-primscrn-pri-indfb-draw-mmap-wc:
- shard-bmg: NOTRUN -> [SKIP][52] ([Intel XE#4141]) +3 other tests skip
[52]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-172150v6/shard-bmg-7/igt@kms_frontbuffer_tracking@fbc-2p-primscrn-pri-indfb-draw-mmap-wc.html
* igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-pri-indfb-draw-blt:
- shard-ptl: NOTRUN -> [SKIP][53] ([Intel XE#5812]) +53 other tests skip
[53]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-172150v6/shard-ptl-4/igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-pri-indfb-draw-blt.html
* igt@kms_frontbuffer_tracking@fbc-argb161616f-draw-blt:
- shard-ptl: NOTRUN -> [SKIP][54] ([Intel XE#7061] / [Intel XE#7356]) +2 other tests skip
[54]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-172150v6/shard-ptl-5/igt@kms_frontbuffer_tracking@fbc-argb161616f-draw-blt.html
* igt@kms_frontbuffer_tracking@fbcdrrs-argb161616f-draw-render:
- shard-bmg: NOTRUN -> [SKIP][55] ([Intel XE#7061] / [Intel XE#7356])
[55]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-172150v6/shard-bmg-4/igt@kms_frontbuffer_tracking@fbcdrrs-argb161616f-draw-render.html
* igt@kms_frontbuffer_tracking@fbcdrrshdr-1p-offscreen-pri-indfb-draw-blt:
- shard-ptl: NOTRUN -> [SKIP][56] ([Intel XE#6312]) +9 other tests skip
[56]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-172150v6/shard-ptl-5/igt@kms_frontbuffer_tracking@fbcdrrshdr-1p-offscreen-pri-indfb-draw-blt.html
* igt@kms_frontbuffer_tracking@fbcdrrshdr-1p-primscrn-pri-shrfb-draw-render:
- shard-bmg: NOTRUN -> [SKIP][57] ([Intel XE#2311]) +16 other tests skip
[57]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-172150v6/shard-bmg-6/igt@kms_frontbuffer_tracking@fbcdrrshdr-1p-primscrn-pri-shrfb-draw-render.html
* igt@kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-cur-indfb-draw-blt:
- shard-bmg: NOTRUN -> [SKIP][58] ([Intel XE#2313]) +18 other tests skip
[58]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-172150v6/shard-bmg-7/igt@kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-cur-indfb-draw-blt.html
* igt@kms_frontbuffer_tracking@fbcpsrhdr-abgr161616f-draw-mmap-wc:
- shard-bmg: NOTRUN -> [SKIP][59] ([Intel XE#7061]) +1 other test skip
[59]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-172150v6/shard-bmg-3/igt@kms_frontbuffer_tracking@fbcpsrhdr-abgr161616f-draw-mmap-wc.html
* igt@kms_frontbuffer_tracking@fbcpsrhdr-rgb565-draw-blt:
- shard-ptl: NOTRUN -> [SKIP][60] ([Intel XE#7865]) +12 other tests skip
[60]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-172150v6/shard-ptl-4/igt@kms_frontbuffer_tracking@fbcpsrhdr-rgb565-draw-blt.html
* igt@kms_frontbuffer_tracking@psrhdr-argb161616f-draw-render:
- shard-ptl: NOTRUN -> [SKIP][61] ([Intel XE#7061]) +3 other tests skip
[61]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-172150v6/shard-ptl-1/igt@kms_frontbuffer_tracking@psrhdr-argb161616f-draw-render.html
* igt@kms_hdmi_audio_bw@audio-bw-hblank80:
- shard-bmg: [PASS][62] -> [FAIL][63] ([Intel XE#9313])
[62]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-6001-55c6bb0b4d006ee415abe9f048014f7bcc90ae6f/shard-bmg-6/igt@kms_hdmi_audio_bw@audio-bw-hblank80.html
[63]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-172150v6/shard-bmg-5/igt@kms_hdmi_audio_bw@audio-bw-hblank80.html
* igt@kms_hdmi_audio_bw@dpms-audio-recovery:
- shard-ptl: NOTRUN -> [SKIP][64] ([Intel XE#9312])
[64]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-172150v6/shard-ptl-2/igt@kms_hdmi_audio_bw@dpms-audio-recovery.html
* igt@kms_joiner@basic-big-joiner:
- shard-ptl: NOTRUN -> [SKIP][65] ([Intel XE#6901]) +1 other test skip
[65]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-172150v6/shard-ptl-1/igt@kms_joiner@basic-big-joiner.html
* igt@kms_plane@pixel-format-y-tiled-gen12-rc-ccs-cc-modifier:
- shard-bmg: NOTRUN -> [SKIP][66] ([Intel XE#7283])
[66]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-172150v6/shard-bmg-8/igt@kms_plane@pixel-format-y-tiled-gen12-rc-ccs-cc-modifier.html
- shard-ptl: NOTRUN -> [SKIP][67] ([Intel XE#7283]) +2 other tests skip
[67]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-172150v6/shard-ptl-8/igt@kms_plane@pixel-format-y-tiled-gen12-rc-ccs-cc-modifier.html
* igt@kms_plane_lowres@tiling-yf:
- shard-bmg: NOTRUN -> [SKIP][68] ([Intel XE#2393])
[68]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-172150v6/shard-bmg-2/igt@kms_plane_lowres@tiling-yf.html
- shard-ptl: NOTRUN -> [SKIP][69] ([Intel XE#5946])
[69]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-172150v6/shard-ptl-8/igt@kms_plane_lowres@tiling-yf.html
* igt@kms_plane_scaling@plane-downscale-factor-0-5-with-pixel-format@pipe-b:
- shard-ptl: NOTRUN -> [SKIP][70] ([Intel XE#6886]) +9 other tests skip
[70]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-172150v6/shard-ptl-1/igt@kms_plane_scaling@plane-downscale-factor-0-5-with-pixel-format@pipe-b.html
* igt@kms_pm_dc@dc5-psr-suspend-resume:
- shard-lnl: [PASS][71] -> [FAIL][72] ([Intel XE#8399])
[71]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-6001-55c6bb0b4d006ee415abe9f048014f7bcc90ae6f/shard-lnl-5/igt@kms_pm_dc@dc5-psr-suspend-resume.html
[72]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-172150v6/shard-lnl-5/igt@kms_pm_dc@dc5-psr-suspend-resume.html
* igt@kms_pm_rpm@modeset-lpsp-stress-no-wait:
- shard-bmg: NOTRUN -> [SKIP][73] ([Intel XE#1439] / [Intel XE#3141] / [Intel XE#7383] / [Intel XE#836])
[73]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-172150v6/shard-bmg-6/igt@kms_pm_rpm@modeset-lpsp-stress-no-wait.html
* igt@kms_psr2_sf@fbc-pr-plane-move-sf-dmg-area:
- shard-ptl: NOTRUN -> [SKIP][74] ([Intel XE#7304]) +1 other test skip
[74]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-172150v6/shard-ptl-1/igt@kms_psr2_sf@fbc-pr-plane-move-sf-dmg-area.html
* igt@kms_psr2_sf@fbc-psr2-cursor-plane-move-continuous-exceed-sf:
- shard-bmg: NOTRUN -> [SKIP][75] ([Intel XE#1489]) +1 other test skip
[75]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-172150v6/shard-bmg-8/igt@kms_psr2_sf@fbc-psr2-cursor-plane-move-continuous-exceed-sf.html
* igt@kms_psr2_sf@fbc-psr2-overlay-plane-update-continuous-sf:
- shard-ptl: NOTRUN -> [SKIP][76] ([Intel XE#5858] / [Intel XE#7304]) +3 other tests skip
[76]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-172150v6/shard-ptl-8/igt@kms_psr2_sf@fbc-psr2-overlay-plane-update-continuous-sf.html
* igt@kms_psr2_sf@fbc-psr2-overlay-plane-update-continuous-sf@pipe-a-edp-1:
- shard-ptl: NOTRUN -> [SKIP][77] ([Intel XE#5858]) +1 other test skip
[77]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-172150v6/shard-ptl-8/igt@kms_psr2_sf@fbc-psr2-overlay-plane-update-continuous-sf@pipe-a-edp-1.html
* igt@kms_psr@fbc-pr-sprite-plane-move:
- shard-ptl: NOTRUN -> [SKIP][78] ([Intel XE#1406])
[78]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-172150v6/shard-ptl-7/igt@kms_psr@fbc-pr-sprite-plane-move.html
* igt@kms_psr@fbc-psr-basic:
- shard-bmg: NOTRUN -> [SKIP][79] ([Intel XE#2234] / [Intel XE#2850]) +1 other test skip
[79]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-172150v6/shard-bmg-3/igt@kms_psr@fbc-psr-basic.html
* igt@kms_psr@fbc-psr2-dpms:
- shard-ptl: NOTRUN -> [SKIP][80] ([Intel XE#1406] / [Intel XE#5835]) +1 other test skip
[80]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-172150v6/shard-ptl-8/igt@kms_psr@fbc-psr2-dpms.html
* igt@kms_rotation_crc@bad-pixel-format:
- shard-bmg: NOTRUN -> [SKIP][81] ([Intel XE#3904] / [Intel XE#7342]) +2 other tests skip
[81]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-172150v6/shard-bmg-7/igt@kms_rotation_crc@bad-pixel-format.html
* igt@kms_rotation_crc@primary-y-tiled-reflect-x-90:
- shard-ptl: NOTRUN -> [SKIP][82] ([Intel XE#5821]) +2 other tests skip
[82]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-172150v6/shard-ptl-8/igt@kms_rotation_crc@primary-y-tiled-reflect-x-90.html
* igt@kms_vrr@flip-basic-fastset:
- shard-ptl: NOTRUN -> [FAIL][83] ([Intel XE#4227] / [Intel XE#7397])
[83]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-172150v6/shard-ptl-5/igt@kms_vrr@flip-basic-fastset.html
* igt@kms_vrr@flip-basic-fastset@pipe-a-edp-1:
- shard-ptl: NOTRUN -> [FAIL][84] ([Intel XE#6293] / [Intel XE#7397])
[84]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-172150v6/shard-ptl-5/igt@kms_vrr@flip-basic-fastset@pipe-a-edp-1.html
* igt@xe_ccs@vm-bind-fault-mode-decompress:
- shard-ptl: NOTRUN -> [SKIP][85] ([Intel XE#7644])
[85]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-172150v6/shard-ptl-3/igt@xe_ccs@vm-bind-fault-mode-decompress.html
* igt@xe_evict@evict-beng-threads-large-multi-vm:
- shard-ptl: NOTRUN -> [SKIP][86] ([Intel XE#5764]) +5 other tests skip
[86]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-172150v6/shard-ptl-6/igt@xe_evict@evict-beng-threads-large-multi-vm.html
* igt@xe_evict@evict-mixed-many-threads-small:
- shard-bmg: NOTRUN -> [INCOMPLETE][87] ([Intel XE#6321] / [Intel XE#8355])
[87]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-172150v6/shard-bmg-4/igt@xe_evict@evict-mixed-many-threads-small.html
* igt@xe_evict_ccs@evict-overcommit-standalone-instantfree-samefd:
- shard-ptl: NOTRUN -> [SKIP][88] ([Intel XE#6144]) +1 other test skip
[88]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-172150v6/shard-ptl-1/igt@xe_evict_ccs@evict-overcommit-standalone-instantfree-samefd.html
* igt@xe_exec_balancer@once-virtual-rebind:
- shard-ptl: NOTRUN -> [SKIP][89] ([Intel XE#7482]) +13 other tests skip
[89]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-172150v6/shard-ptl-2/igt@xe_exec_balancer@once-virtual-rebind.html
* igt@xe_exec_basic@multigpu-many-execqueues-many-vm-basic-defer-bind:
- shard-bmg: NOTRUN -> [SKIP][90] ([Intel XE#2322] / [Intel XE#7372])
[90]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-172150v6/shard-bmg-1/igt@xe_exec_basic@multigpu-many-execqueues-many-vm-basic-defer-bind.html
* igt@xe_exec_basic@multigpu-no-exec-bindexecqueue-userptr-rebind:
- shard-ptl: NOTRUN -> [SKIP][91] ([Intel XE#5575] / [Intel XE#7484]) +5 other tests skip
[91]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-172150v6/shard-ptl-4/igt@xe_exec_basic@multigpu-no-exec-bindexecqueue-userptr-rebind.html
* igt@xe_exec_fault_mode@many-execqueues-multi-queue-userptr:
- shard-bmg: NOTRUN -> [SKIP][92] ([Intel XE#8374]) +3 other tests skip
[92]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-172150v6/shard-bmg-10/igt@xe_exec_fault_mode@many-execqueues-multi-queue-userptr.html
* igt@xe_exec_fault_mode@once-multi-queue-userptr-rebind:
- shard-ptl: NOTRUN -> [SKIP][93] ([Intel XE#8374]) +9 other tests skip
[93]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-172150v6/shard-ptl-8/igt@xe_exec_fault_mode@once-multi-queue-userptr-rebind.html
* igt@xe_exec_multi_queue@max-queues-basic:
- shard-bmg: NOTRUN -> [SKIP][94] ([Intel XE#8364]) +11 other tests skip
[94]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-172150v6/shard-bmg-6/igt@xe_exec_multi_queue@max-queues-basic.html
* igt@xe_exec_multi_queue@one-queue-preempt-mode-fault-close-fd-smem:
- shard-ptl: NOTRUN -> [SKIP][95] ([Intel XE#8364]) +19 other tests skip
[95]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-172150v6/shard-ptl-2/igt@xe_exec_multi_queue@one-queue-preempt-mode-fault-close-fd-smem.html
* igt@xe_exec_reset@gt-stress-reset-memory-pressure:
- shard-lnl: [PASS][96] -> [DMESG-WARN][97] ([Intel XE#8652])
[96]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-6001-55c6bb0b4d006ee415abe9f048014f7bcc90ae6f/shard-lnl-4/igt@xe_exec_reset@gt-stress-reset-memory-pressure.html
[97]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-172150v6/shard-lnl-6/igt@xe_exec_reset@gt-stress-reset-memory-pressure.html
* igt@xe_exec_reset@gt-stress-reset-pm-transition:
- shard-bmg: [PASS][98] -> [DMESG-WARN][99] ([Intel XE#8652])
[98]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-6001-55c6bb0b4d006ee415abe9f048014f7bcc90ae6f/shard-bmg-2/igt@xe_exec_reset@gt-stress-reset-pm-transition.html
[99]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-172150v6/shard-bmg-7/igt@xe_exec_reset@gt-stress-reset-pm-transition.html
* igt@xe_exec_reset@multi-queue-cancel:
- shard-ptl: NOTRUN -> [SKIP][100] ([Intel XE#8369])
[100]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-172150v6/shard-ptl-7/igt@xe_exec_reset@multi-queue-cancel.html
- shard-bmg: NOTRUN -> [SKIP][101] ([Intel XE#8369])
[101]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-172150v6/shard-bmg-10/igt@xe_exec_reset@multi-queue-cancel.html
* igt@xe_exec_threads@threads-multi-queue-mixed-shared-vm-basic:
- shard-bmg: NOTRUN -> [SKIP][102] ([Intel XE#8378]) +2 other tests skip
[102]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-172150v6/shard-bmg-2/igt@xe_exec_threads@threads-multi-queue-mixed-shared-vm-basic.html
* igt@xe_exec_threads@threads-multi-queue-shared-vm-basic:
- shard-ptl: NOTRUN -> [SKIP][103] ([Intel XE#8378]) +4 other tests skip
[103]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-172150v6/shard-ptl-3/igt@xe_exec_threads@threads-multi-queue-shared-vm-basic.html
* igt@xe_fault_injection@probe-fail-guc-xe_guc_ct_send_recv:
- shard-lnl: [PASS][104] -> [ABORT][105] ([Intel XE#6652])
[104]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-6001-55c6bb0b4d006ee415abe9f048014f7bcc90ae6f/shard-lnl-2/igt@xe_fault_injection@probe-fail-guc-xe_guc_ct_send_recv.html
[105]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-172150v6/shard-lnl-3/igt@xe_fault_injection@probe-fail-guc-xe_guc_ct_send_recv.html
* igt@xe_live_ktest@xe_bo@xe_bo_evict_kunit:
- shard-ptl: NOTRUN -> [SKIP][106] ([Intel XE#5775])
[106]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-172150v6/shard-ptl-1/igt@xe_live_ktest@xe_bo@xe_bo_evict_kunit.html
* igt@xe_live_ktest@xe_bo@xe_ccs_migrate_kunit:
- shard-bmg: NOTRUN -> [SKIP][107] ([Intel XE#2229])
[107]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-172150v6/shard-bmg-9/igt@xe_live_ktest@xe_bo@xe_ccs_migrate_kunit.html
* igt@xe_media_fill@media-fill:
- shard-bmg: NOTRUN -> [SKIP][108] ([Intel XE#2459] / [Intel XE#2596] / [Intel XE#7321] / [Intel XE#7453])
[108]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-172150v6/shard-bmg-10/igt@xe_media_fill@media-fill.html
- shard-ptl: NOTRUN -> [SKIP][109] ([Intel XE#5830] / [Intel XE#7453])
[109]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-172150v6/shard-ptl-7/igt@xe_media_fill@media-fill.html
* igt@xe_multigpu_svm@mgpu-coherency-conflict:
- shard-bmg: NOTRUN -> [SKIP][110] ([Intel XE#6964]) +1 other test skip
[110]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-172150v6/shard-bmg-1/igt@xe_multigpu_svm@mgpu-coherency-conflict.html
- shard-ptl: NOTRUN -> [SKIP][111] ([Intel XE#6964]) +1 other test skip
[111]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-172150v6/shard-ptl-1/igt@xe_multigpu_svm@mgpu-coherency-conflict.html
* igt@xe_page_reclaim@binds-full-pd:
- shard-bmg: NOTRUN -> [SKIP][112] ([Intel XE#7793])
[112]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-172150v6/shard-bmg-7/igt@xe_page_reclaim@binds-full-pd.html
- shard-ptl: NOTRUN -> [SKIP][113] ([Intel XE#7793])
[113]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-172150v6/shard-ptl-3/igt@xe_page_reclaim@binds-full-pd.html
* igt@xe_peer2peer@read:
- shard-ptl: NOTRUN -> [SKIP][114] ([Intel XE#6588])
[114]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-172150v6/shard-ptl-6/igt@xe_peer2peer@read.html
* igt@xe_pm@d3cold-multiple-execs:
- shard-bmg: NOTRUN -> [SKIP][115] ([Intel XE#2284] / [Intel XE#7370])
[115]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-172150v6/shard-bmg-7/igt@xe_pm@d3cold-multiple-execs.html
- shard-ptl: NOTRUN -> [SKIP][116] ([Intel XE#5741])
[116]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-172150v6/shard-ptl-4/igt@xe_pm@d3cold-multiple-execs.html
* igt@xe_pm@s4-basic:
- shard-lnl: [PASS][117] -> [ABORT][118] ([Intel XE#9362]) +2 other tests abort
[117]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-6001-55c6bb0b4d006ee415abe9f048014f7bcc90ae6f/shard-lnl-6/igt@xe_pm@s4-basic.html
[118]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-172150v6/shard-lnl-6/igt@xe_pm@s4-basic.html
* igt@xe_pm@s4-basic-exec:
- shard-ptl: [PASS][119] -> [ABORT][120] ([Intel XE#9362]) +1 other test abort
[119]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-6001-55c6bb0b4d006ee415abe9f048014f7bcc90ae6f/shard-ptl-8/igt@xe_pm@s4-basic-exec.html
[120]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-172150v6/shard-ptl-4/igt@xe_pm@s4-basic-exec.html
* igt@xe_pm_residency@aspm_link_residency:
- shard-ptl: NOTRUN -> [SKIP][121] ([Intel XE#7271])
[121]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-172150v6/shard-ptl-8/igt@xe_pm_residency@aspm_link_residency.html
* igt@xe_pm_residency@gt-c6-freeze@gt1:
- shard-bmg: [PASS][122] -> [FAIL][123] ([Intel XE#9254])
[122]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-6001-55c6bb0b4d006ee415abe9f048014f7bcc90ae6f/shard-bmg-5/igt@xe_pm_residency@gt-c6-freeze@gt1.html
[123]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-172150v6/shard-bmg-9/igt@xe_pm_residency@gt-c6-freeze@gt1.html
* igt@xe_query@multigpu-query-invalid-query:
- shard-bmg: NOTRUN -> [SKIP][124] ([Intel XE#944]) +1 other test skip
[124]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-172150v6/shard-bmg-2/igt@xe_query@multigpu-query-invalid-query.html
* igt@xe_query@multigpu-query-oa-units:
- shard-ptl: NOTRUN -> [SKIP][125] ([Intel XE#6019]) +2 other tests skip
[125]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-172150v6/shard-ptl-8/igt@xe_query@multigpu-query-oa-units.html
* igt@xe_sriov_flr@flr-vfs-parallel:
- shard-bmg: [PASS][126] -> [FAIL][127] ([Intel XE#6569])
[126]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-6001-55c6bb0b4d006ee415abe9f048014f7bcc90ae6f/shard-bmg-3/igt@xe_sriov_flr@flr-vfs-parallel.html
[127]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-172150v6/shard-bmg-10/igt@xe_sriov_flr@flr-vfs-parallel.html
#### Possible fixes ####
* igt@kms_bw@linear-tiling-1-displays-target-2560x1440p:
- shard-bmg: [SKIP][128] ([Intel XE#367]) -> [PASS][129]
[128]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-6001-55c6bb0b4d006ee415abe9f048014f7bcc90ae6f/shard-bmg-1/igt@kms_bw@linear-tiling-1-displays-target-2560x1440p.html
[129]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-172150v6/shard-bmg-7/igt@kms_bw@linear-tiling-1-displays-target-2560x1440p.html
* igt@kms_hdmi_audio_bw@audio-bw-hblank160:
- shard-bmg: [FAIL][130] ([Intel XE#9313]) -> [PASS][131]
[130]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-6001-55c6bb0b4d006ee415abe9f048014f7bcc90ae6f/shard-bmg-5/igt@kms_hdmi_audio_bw@audio-bw-hblank160.html
[131]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-172150v6/shard-bmg-9/igt@kms_hdmi_audio_bw@audio-bw-hblank160.html
* igt@kms_hdr@invalid-hdr:
- shard-bmg: [SKIP][132] ([Intel XE#1503]) -> [PASS][133]
[132]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-6001-55c6bb0b4d006ee415abe9f048014f7bcc90ae6f/shard-bmg-5/igt@kms_hdr@invalid-hdr.html
[133]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-172150v6/shard-bmg-8/igt@kms_hdr@invalid-hdr.html
* igt@xe_exec_threads@threads-hang-userptr-invalidate-race:
- shard-lnl: [FAIL][134] ([Intel XE#9096]) -> [PASS][135]
[134]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-6001-55c6bb0b4d006ee415abe9f048014f7bcc90ae6f/shard-lnl-6/igt@xe_exec_threads@threads-hang-userptr-invalidate-race.html
[135]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-172150v6/shard-lnl-4/igt@xe_exec_threads@threads-hang-userptr-invalidate-race.html
* igt@xe_pm@s4-exec-after:
- shard-ptl: [ABORT][136] ([Intel XE#9362]) -> [PASS][137]
[136]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-6001-55c6bb0b4d006ee415abe9f048014f7bcc90ae6f/shard-ptl-4/igt@xe_pm@s4-exec-after.html
[137]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-172150v6/shard-ptl-7/igt@xe_pm@s4-exec-after.html
* igt@xe_pm_residency@gt-c6-freeze@gt0:
- shard-bmg: [FAIL][138] ([Intel XE#9254]) -> [PASS][139]
[138]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-6001-55c6bb0b4d006ee415abe9f048014f7bcc90ae6f/shard-bmg-5/igt@xe_pm_residency@gt-c6-freeze@gt0.html
[139]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-172150v6/shard-bmg-9/igt@xe_pm_residency@gt-c6-freeze@gt0.html
#### Warnings ####
* igt@kms_tiled_display@basic-test-pattern:
- shard-bmg: [FAIL][140] ([Intel XE#1729] / [Intel XE#7424]) -> [SKIP][141] ([Intel XE#2426] / [Intel XE#5848])
[140]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-6001-55c6bb0b4d006ee415abe9f048014f7bcc90ae6f/shard-bmg-10/igt@kms_tiled_display@basic-test-pattern.html
[141]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-172150v6/shard-bmg-2/igt@kms_tiled_display@basic-test-pattern.html
[Intel XE#1124]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1124
[Intel XE#1406]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1406
[Intel XE#1439]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1439
[Intel XE#1489]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1489
[Intel XE#1503]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1503
[Intel XE#1729]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1729
[Intel XE#2229]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2229
[Intel XE#2234]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2234
[Intel XE#2252]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2252
[Intel XE#2284]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2284
[Intel XE#2311]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2311
[Intel XE#2313]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2313
[Intel XE#2316]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2316
[Intel XE#2320]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2320
[Intel XE#2322]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2322
[Intel XE#2327]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2327
[Intel XE#2390]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2390
[Intel XE#2393]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2393
[Intel XE#2426]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2426
[Intel XE#2459]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2459
[Intel XE#2596]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2596
[Intel XE#2652]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2652
[Intel XE#2850]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2850
[Intel XE#2887]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2887
[Intel XE#301]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/301
[Intel XE#3141]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3141
[Intel XE#3149]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3149
[Intel XE#3432]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3432
[Intel XE#367]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/367
[Intel XE#3904]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3904
[Intel XE#4141]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4141
[Intel XE#4227]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4227
[Intel XE#4302]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4302
[Intel XE#4760]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4760
[Intel XE#5408]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5408
[Intel XE#5575]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5575
[Intel XE#5741]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5741
[Intel XE#5764]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5764
[Intel XE#5775]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5775
[Intel XE#5800]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5800
[Intel XE#5808]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5808
[Intel XE#5812]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5812
[Intel XE#5821]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5821
[Intel XE#5822]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5822
[Intel XE#5823]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5823
[Intel XE#5824]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5824
[Intel XE#5828]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5828
[Intel XE#5830]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5830
[Intel XE#5832]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5832
[Intel XE#5835]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5835
[Intel XE#5848]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5848
[Intel XE#5851]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5851
[Intel XE#5855]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5855
[Intel XE#5858]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5858
[Intel XE#5900]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5900
[Intel XE#5901]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5901
[Intel XE#5907]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5907
[Intel XE#5946]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5946
[Intel XE#5962]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5962
[Intel XE#6019]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6019
[Intel XE#607]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/607
[Intel XE#6144]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6144
[Intel XE#6266]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6266
[Intel XE#6293]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6293
[Intel XE#6312]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6312
[Intel XE#6321]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6321
[Intel XE#6507]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6507
[Intel XE#6569]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6569
[Intel XE#6588]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6588
[Intel XE#6652]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6652
[Intel XE#6886]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6886
[Intel XE#6901]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6901
[Intel XE#6918]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6918
[Intel XE#6925]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6925
[Intel XE#6964]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6964
[Intel XE#6974]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6974
[Intel XE#7059]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7059
[Intel XE#7061]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7061
[Intel XE#7085]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7085
[Intel XE#7178]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7178
[Intel XE#7179]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7179
[Intel XE#7225]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7225
[Intel XE#7271]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7271
[Intel XE#7283]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7283
[Intel XE#7304]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7304
[Intel XE#7321]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7321
[Intel XE#7342]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7342
[Intel XE#7351]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7351
[Intel XE#7356]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7356
[Intel XE#7361]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7361
[Intel XE#7370]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7370
[Intel XE#7372]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7372
[Intel XE#7383]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7383
[Intel XE#7397]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7397
[Intel XE#7424]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7424
[Intel XE#7453]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7453
[Intel XE#7482]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7482
[Intel XE#7484]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7484
[Intel XE#7642]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7642
[Intel XE#7644]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7644
[Intel XE#7679]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7679
[Intel XE#7793]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7793
[Intel XE#7809]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7809
[Intel XE#7865]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7865
[Intel XE#8265]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/8265
[Intel XE#8355]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/8355
[Intel XE#836]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/836
[Intel XE#8364]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/8364
[Intel XE#8369]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/8369
[Intel XE#8374]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/8374
[Intel XE#8378]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/8378
[Intel XE#8399]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/8399
[Intel XE#8583]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/8583
[Intel XE#8652]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/8652
[Intel XE#9096]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/9096
[Intel XE#9254]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/9254
[Intel XE#9312]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/9312
[Intel XE#9313]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/9313
[Intel XE#9362]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/9362
[Intel XE#944]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/944
Build changes
-------------
* IGT: IGT_9159 -> IGT_9160
* Linux: xe-6001-55c6bb0b4d006ee415abe9f048014f7bcc90ae6f -> xe-pw-172150v6
IGT_9159: 9159
IGT_9160: 9160
xe-6001-55c6bb0b4d006ee415abe9f048014f7bcc90ae6f: 55c6bb0b4d006ee415abe9f048014f7bcc90ae6f
xe-pw-172150v6: 172150v6
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-172150v6/index.html
[-- Attachment #2: Type: text/html, Size: 50433 bytes --]
^ permalink raw reply [flat|nested] 23+ messages in thread
* RE: [PATCH v5 3/7] drm/xe/guc: Print register addresses in capture snapshot output
2026-10-23 6:05 ` [PATCH v5 3/7] drm/xe/guc: Print register addresses in capture snapshot output Nareshkumar Gollakoti
@ 2026-10-23 13:14 ` Upadhyay, Tejas
2026-10-26 6:37 ` Upadhyay, Tejas
1 sibling, 0 replies; 23+ messages in thread
From: Upadhyay, Tejas @ 2026-10-23 13:14 UTC (permalink / raw)
To: Kumar G, Naresh, intel-xe@lists.freedesktop.org
> -----Original Message-----
> From: Kumar G, Naresh <naresh.kumar.g@intel.com>
> Sent: 23 October 2026 11:36
> To: intel-xe@lists.freedesktop.org
> Cc: Upadhyay, Tejas <tejas.upadhyay@intel.com>; Kumar G, Naresh
> <naresh.kumar.g@intel.com>
> Subject: [PATCH v5 3/7] drm/xe/guc: Print register addresses in capture
> snapshot output
>
> Include register offsets in GuC capture snapshot print output for both 32-bit
> and 64-bit registers.
>
> When dumping captured engine register state, print each register name
> alongside its MMIO offset to make the snapshot output easier to cross-
> reference with register definitions and hardware debug documentation.
>
> This improves postmortem analysis without changing capture contents.
>
> v2:(Sashiko)
> - Ensure lower DWORD prints
>
> v3:(Sashiko)
> - Use the LOW_DW MMIO offset(capture in last_address) when combined
> 64bit
> register values in the dump instead of HI_SW offset
> - preserve existing coredump register-name format and append register
> address as trailing metadata as a debug info and avoids disrupting
> existing format
>
> Signed-off-by: Nareshkumar Gollakoti <naresh.kumar.g@intel.com>
> ---
> drivers/gpu/drm/xe/xe_guc_capture.c | 18 ++++++++++++++----
> 1 file changed, 14 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/gpu/drm/xe/xe_guc_capture.c
> b/drivers/gpu/drm/xe/xe_guc_capture.c
> index 5a4d085660a2..3e99aef53b46 100644
> --- a/drivers/gpu/drm/xe/xe_guc_capture.c
> +++ b/drivers/gpu/drm/xe/xe_guc_capture.c
> @@ -1716,6 +1716,7 @@ snapshot_print_by_list_order(struct
> xe_hw_engine_snapshot *snapshot, struct drm_
> struct xe_devcoredump_snapshot *devcore_snapshot =
> &devcoredump->snapshot;
> struct gcap_reg_list_info *reginfo = NULL;
> u32 i, last_value = 0;
> + u32 last_address = 0;
> bool low32_ready = false;
>
> if (!list || !list->list || list->num_regs == 0) @@ -1743,6 +1744,7 @@
> snapshot_print_by_list_order(struct xe_hw_engine_snapshot *snapshot,
> struct drm_
> switch (reg_desc->data_type) {
> case REG_64BIT_LOW_DW:
> last_value = value;
> + last_address = reg_desc->reg.addr;
>
> /*
> * A 64 bit register define requires 2 consecutive @@ -
> 1774,7 +1776,11 @@ snapshot_print_by_list_order(struct
> xe_hw_engine_snapshot *snapshot, struct drm_
> XE_WARN_ON(!low32_ready);
> low32_ready = false;
>
> - drm_printf(p, "\t%s: 0x%016llx\n", reg_desc-
> >regname, value_qw);
> + drm_printf(p, "\t%s: 0x%016llx [addr=0x%x]\n",
> + reg_desc->regname,
> + value_qw,
> + last_address);
> +
> break;
> }
>
> @@ -1788,10 +1794,14 @@ snapshot_print_by_list_order(struct
> xe_hw_engine_snapshot *snapshot, struct drm_
> XE_WARN_ON(low32_ready);
>
> if (FIELD_GET(GUC_REGSET_STEERING_NEEDED,
> reg_desc->flags))
> - drm_printf(p, "\t%s[%u]: 0x%08x\n",
> reg_desc->regname,
> - reg_desc->dss_id, value);
> + drm_printf(p, "\t%s[%u]: 0x%08x
> [addr=0x%x]\n",
> + reg_desc->regname,
> + reg_desc->dss_id, value, reg_desc-
> >reg.addr);
> +
> else
> - drm_printf(p, "\t%s: 0x%08x\n", reg_desc-
> >regname, value);
> + drm_printf(p, "\t%s: 0x%08x [addr=0x%x]\n",
> + reg_desc->regname, value,
> reg_desc->reg.addr);
> +
Extra newline? With that fixed,
LGTM,
Reviewed-by: Tejas Upadhyay <tejas.upadhyay@intel.com>
Tejas
>
> break;
> }
> --
> 2.43.0
^ permalink raw reply [flat|nested] 23+ messages in thread
* RE: [PATCH v5 1/7] drm/xe/devcoredump: Capture GT fuse registers in devcoredump
2026-10-23 6:05 ` [PATCH v5 1/7] drm/xe/devcoredump: Capture GT fuse registers " Nareshkumar Gollakoti
@ 2026-10-23 13:27 ` Upadhyay, Tejas
0 siblings, 0 replies; 23+ messages in thread
From: Upadhyay, Tejas @ 2026-10-23 13:27 UTC (permalink / raw)
To: Kumar G, Naresh, intel-xe@lists.freedesktop.org
> -----Original Message-----
> From: Kumar G, Naresh <naresh.kumar.g@intel.com>
> Sent: 23 October 2026 11:36
> To: intel-xe@lists.freedesktop.org
> Cc: Upadhyay, Tejas <tejas.upadhyay@intel.com>; Kumar G, Naresh
> <naresh.kumar.g@intel.com>
> Subject: [PATCH v5 1/7] drm/xe/devcoredump: Capture GT fuse registers in
> devcoredump
>
> Capture fuse-related GT register state in the Xe devcoredump to preserve
> additional hardware configuration information for postmortem debugging.
>
> Add generic register snapshot storage and helpers for capturing, printing, and
> freeing MMIO register dumps. Use them to record both primary GT and media
> GT fuse register state during devcoredump snapshot collection and print the
> captured values in the coredump output.
>
> Also add the required GT register definitions for RPM and mirror copy-enable
> state used by the new dump paths.
>
> v2:(Sashiko)
> - Fix GT/media fuse snapshot capture to use the correct GT context.
> - Add non-fault GT force wake for cross-GT register capture.
> - Skip reading registers when SR-IOV VF.
> - Skip media GT capture when media GT is absent.
> - Add RPM snapshot print/free handling explicitly.
> - Add POWERGATE_ENABLE register to get render awake status
>
> v3:(Sashiko)
> - Check RENDER_POWERGATE_ENABLE of POWERGATE_ENABLE register
> - Replace "render is not awake" message with "render powergating
> appears not enabled"
>
> v4:
> - Reduce multiple apis and optimize the suggest way of struct arrays(Tejas)
> - Add document for struct xe_gt_regset gt member(Hook failure)
> - Change struct reg_desc to header file
> - Remove Graphics version check for these registers set
>
> v5:
> - Fix possible Null dereference using valid gt instead of q->gt(sashiko)
> - refactor struct member commenting(Tejas)
> - Avoid using xe3p naming as the regs are for all platforms
>
> Signed-off-by: Nareshkumar Gollakoti <naresh.kumar.g@intel.com>
> ---
> drivers/gpu/drm/xe/regs/xe_gt_regs.h | 2 +
> drivers/gpu/drm/xe/xe_devcoredump.c | 228
> +++++++++++++++++++++-
> drivers/gpu/drm/xe/xe_devcoredump_types.h | 52 +++++
> 3 files changed, 281 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/xe/regs/xe_gt_regs.h
> b/drivers/gpu/drm/xe/regs/xe_gt_regs.h
> index f5cd3a94e47f..e93895e0c731 100644
> --- a/drivers/gpu/drm/xe/regs/xe_gt_regs.h
> +++ b/drivers/gpu/drm/xe/regs/xe_gt_regs.h
> @@ -22,6 +22,8 @@
> #define MTL_CC_MASK
> REG_GENMASK(12, 9)
> #define MTL_CRST 0xf
>
> +#define RPM_GCD
> XE_REG(0xc98)
#define MIRROR_PM_DEBUG ? Please make sure you use spec name as is. Apply this to everywhere in this series.
> +
> /* RPM unit config (Gen8+) */
> #define RPM_CONFIG0
> XE_REG(0xd00)
> #define RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_MASK
> REG_GENMASK(5, 3)
> diff --git a/drivers/gpu/drm/xe/xe_devcoredump.c
> b/drivers/gpu/drm/xe/xe_devcoredump.c
> index 133cbe196d66..f59f93ba5949 100644
> --- a/drivers/gpu/drm/xe/xe_devcoredump.c
> +++ b/drivers/gpu/drm/xe/xe_devcoredump.c
> @@ -25,6 +25,8 @@
> #include "xe_pm.h"
> #include "xe_sched_job.h"
> #include "xe_vm.h"
> +#include "xe_mmio.h"
> +#include "regs/xe_gt_regs.h"
>
> /**
> * DOC: Xe device coredump
> @@ -69,6 +71,179 @@
> /* 1 hour timeout */
> #define XE_COREDUMP_TIMEOUT_JIFFIES (60 * 60 * HZ)
>
> +#define XE_REG_DESC(_reg, _name) { .reg = (_reg), .name = (_name) }
> +
> +static const struct xe_reg_desc xe_dbg_gt_fuse_reglist[] = {
> + XE_REG_DESC(XELP_GT_GEOMETRY_DSS_ENABLE,
> "GT_GEOMETRY_DSS_ENABLE"),
> + XE_REG_DESC(XEHP_GT_COMPUTE_DSS_ENABLE,
> "GT_COMPUTE_DSS_ENABLE"),
> + XE_REG_DESC(XELP_EU_ENABLE, "EU_ENABLE"),
> + XE_REG_DESC(MIRROR_FUSE1, "MIRROR_FUSE1"),
> + XE_REG_DESC(GT_VEBOX_VDBOX_DISABLE,
> "GT_VEBOX_VDBOX_DISABLE"),
> + XE_REG_DESC(SERVICE_COPY_ENABLE, "SERVICE_COPY_ENABLE"),
> + XE_REG_DESC(RESOURCE_COPY_ENABLE,
> "COPY_ENABLE_GTFS_GCD"),
> + XE_REG_DESC(XE2_GT_GEOMETRY_DSS_1, "GT_GEOMETRY_DSS_1"),
> + XE_REG_DESC(XE2_GT_GEOMETRY_DSS_2, "GT_GEOMETRY_DSS_2"),
> + XE_REG_DESC(XE2_GT_COMPUTE_DSS_2, "GT_COMPUTE_DSS_2"),
> + XE_REG_DESC(XEHPC_GT_COMPUTE_DSS_ENABLE_EXT,
> "GT_COMPUTE_DSS_ENABLE_EXT"),
> + XE_REG_DESC(XE3P_XPC_GT_GEOMETRY_DSS_3,
> "GT_GEOMETRY_DSS_3"),
> + XE_REG_DESC(XE3P_XPC_GT_COMPUTE_DSS_3,
> "GT_COMPUTE_DSS_3"), };
> +
> +static const struct xe_reg_desc xe_dbg_media_gt_fuse_reglist[] = {
> + XE_REG_DESC(SERVICE_COPY_ENABLE, "SERVICE_COPY_ENABLE"),
> + XE_REG_DESC(RESOURCE_COPY_ENABLE,
> "COPY_ENABLE_GTFS_GCD"), };
> +
> +static const struct xe_reg_desc xe_dbg_gt_rpm_reglist[] = {
> + XE_REG_DESC(RPM_GCD, "RPM_GCD"),
> + XE_REG_DESC(POWERGATE_ENABLE, "POWERGATE_ENABLE"), };
> +
> +static const struct xe_reg_desc xe_dbg_media_gt_rpm_reglist[] = {
> + XE_REG_DESC(RPM_GCD, "RPM_GCD"),
> +};
> +
> +/**
> + * struct xe_gt_regset - Struct for register descriptor list for GT
> + *
> + * This struct is used to reference the corresponding reglist of
> + * Main GT and media GT
> + */
> +struct xe_gt_regset {
> + /**
> + * @gt: GT array indexed by enum xe_gt_type starting at 1
> + * (UNINITIALIZED=0, MAIN=1, MEDIA=2)
> + */
> + struct xe_reg_desc_list gt[XE_MAX_GT_PER_TILE + 1]; };
> +
> +/**
> + * enum xe_dbg_regset_type - debug register set types
> + * @XE_DBG_REGSET_FUSE: Fuse register set
> + * @XE_DBG_REGSET_RPM: RPM register set
> + * @XE_DBG_REGSET_MAX: Number of debug register set types */ enum
> +xe_dbg_regset_type {
> + XE_DBG_REGSET_FUSE,
> + XE_DBG_REGSET_RPM,
> + XE_DBG_REGSET_MAX,
> +};
> +
> +static const struct xe_gt_regset xe_dbg_regsets[XE_DBG_REGSET_MAX] = {
> + [XE_DBG_REGSET_FUSE] = {
> + .gt[XE_GT_TYPE_MAIN] = { xe_dbg_gt_fuse_reglist,
> + ARRAY_SIZE(xe_dbg_gt_fuse_reglist)
> },
> + .gt[XE_GT_TYPE_MEDIA] = { xe_dbg_media_gt_fuse_reglist,
> +
> ARRAY_SIZE(xe_dbg_media_gt_fuse_reglist) },
> + },
> + [XE_DBG_REGSET_RPM] = {
> + .gt[XE_GT_TYPE_MAIN] = { xe_dbg_gt_rpm_reglist,
> + ARRAY_SIZE(xe_dbg_gt_rpm_reglist)
> },
> + .gt[XE_GT_TYPE_MEDIA] = { xe_dbg_media_gt_rpm_reglist,
> +
> ARRAY_SIZE(xe_dbg_media_gt_rpm_reglist) },
> + },
> +};
> +
> +static void xe_dbg_reg_snapshot_print(struct drm_printer *p,
> + const char *title,
> + const struct xe_dbg_reg_snapshot *snap) {
> + u32 i;
> +
> + if (!snap)
> + return;
> +
> + if (title)
> + drm_printf(p, "\n**** %s ****\n", title);
> +
> + for (i = 0; i < snap->num_regs; i++)
> + drm_printf(p, " %s [0x%x] = 0x%08x\n",
> + snap->desc->regs[i].name,
> + snap->desc->regs[i].reg.addr,
> + snap->values[i]);
> +}
> +
> +static void xe_dbg_reg_snapshot_free(struct xe_dbg_reg_snapshot *snap)
> +{
> + kfree(snap);
> +}
> +
> +static const u32 *xe_dbg_find_value(const struct xe_dbg_reg_snapshot
> *snap,
> + struct xe_reg reg)
> +{
> + int i;
> +
> + if (!snap)
> + return NULL;
> +
> + for (i = 0; i < snap->num_regs; i++)
> + if (snap->desc->regs[i].reg.addr == reg.addr)
> + return &snap->values[i];
> +
> + return NULL;
> +}
> +
> +static void xe_gt_rpm_snapshot_print(struct drm_printer *p,
> + const char *title,
> + const struct xe_dbg_reg_snapshot *snap) {
> + const u32 *val;
> +
> + xe_dbg_reg_snapshot_print(p, title, snap);
> +
> + if (!snap)
> + return;
> +
> + val = xe_dbg_find_value(snap, POWERGATE_ENABLE);
> + if (val && !(*val & RENDER_POWERGATE_ENABLE))
> + drm_puts(p, "render powergating appears not enabled\n"); }
> +
> +static struct xe_dbg_reg_snapshot *
> +xe_dbg_reg_snapshot_capture_target(struct xe_gt *gt,
> + const struct xe_reg_desc_list *reglist) {
> + struct xe_dbg_reg_snapshot *snap;
> + int i;
> +
> + if (IS_SRIOV_VF(gt_to_xe(gt)))
> + return NULL;
> +
> + snap = kmalloc(struct_size(snap, values, reglist->num_regs),
> GFP_ATOMIC);
> + if (!snap)
> + return NULL;
> +
> + snap->desc = reglist;
> + snap->num_regs = reglist->num_regs;
> + for (i = 0; i < reglist->num_regs; i++)
> + snap->values[i] = xe_mmio_read32(>->mmio, reglist-
> >regs[i].reg);
> +
> + return snap;
> +}
> +
> +static struct xe_dbg_reg_snapshot *
> +xe_dbg_gt_snapshot_capture(struct xe_gt *fault_gt, struct xe_gt *other_gt,
> + enum xe_dbg_regset_type type,
> + enum xe_gt_type gt_type)
> +{
> + struct xe_gt *target_gt;
> +
> + if (!fault_gt || !fault_gt->tile)
> + return NULL;
> +
> + target_gt = gt_type == XE_GT_TYPE_MEDIA ? fault_gt->tile->media_gt
> + : fault_gt->tile->primary_gt;
> + if (!target_gt)
> + return NULL;
> +
> + /* non-fault GT needs the caller's confirmed forcewake */
> + if (target_gt != fault_gt && target_gt != other_gt)
> + return NULL;
> +
> + return xe_dbg_reg_snapshot_capture_target(target_gt,
> +
> &xe_dbg_regsets[type].gt[gt_type]);
> +}
> +
> static struct xe_device *coredump_to_xe(const struct xe_devcoredump
> *coredump) {
> return container_of(coredump, struct xe_device, devcoredump); @@
> -109,6 +284,11 @@ static ssize_t __xe_devcoredump_read(char *buffer,
> ssize_t count,
> drm_printf(&p, "\n**** GT #%d ****\n", ss->gt->info.id);
> drm_printf(&p, "\tTile: %d\n", ss->gt->tile->id);
>
> + xe_dbg_reg_snapshot_print(&p, "GT Fuse Register Dump", ss-
> >gt_fuse);
> + xe_dbg_reg_snapshot_print(&p, "Media GT Fuse Register Dump", ss-
> >media_fuse);
> + xe_gt_rpm_snapshot_print(&p, "GT RPM Register Dump", ss-
> >gt_rpm);
> + xe_dbg_reg_snapshot_print(&p, "Media GT RPM Register Dump",
> +ss->media_gt_rpm);
> +
> drm_puts(&p, "\n**** GuC Log ****\n");
> xe_guc_log_snapshot_print(ss->guc.log, &p, ss->gt);
> drm_puts(&p, "\n**** GuC CT ****\n");
> @@ -146,6 +326,18 @@ static void xe_devcoredump_snapshot_free(struct
> xe_devcoredump_snapshot *ss)
> xe_guc_ct_snapshot_free(ss->guc.ct);
> ss->guc.ct = NULL;
>
> + xe_dbg_reg_snapshot_free(ss->gt_fuse);
> + ss->gt_fuse = NULL;
> +
> + xe_dbg_reg_snapshot_free(ss->media_fuse);
> + ss->media_fuse = NULL;
> +
> + xe_dbg_reg_snapshot_free(ss->gt_rpm);
> + ss->gt_rpm = NULL;
> +
> + xe_dbg_reg_snapshot_free(ss->media_gt_rpm);
> + ss->media_gt_rpm = NULL;
> +
> if (!IS_ERR_OR_NULL(ss->gt))
> xe_guc_capture_put_matched_nodes(&ss->gt->uc.guc);
> ss->matched_node = NULL;
> @@ -319,6 +511,27 @@ static void
> xe_devcoredump_deferred_snap_work(struct work_struct *work)
> }
> }
>
> +static void xe_devcoredump_capture_gt_regs(struct
> xe_devcoredump_snapshot *ss,
> + struct xe_gt *gt, struct xe_gt
> *other_gt) {
> + ss->gt_fuse = xe_dbg_gt_snapshot_capture(gt,
> + other_gt,
> + XE_DBG_REGSET_FUSE,
> + XE_GT_TYPE_MAIN);
> + ss->media_fuse = xe_dbg_gt_snapshot_capture(gt,
> + other_gt,
> + XE_DBG_REGSET_FUSE,
> + XE_GT_TYPE_MEDIA);
> + ss->gt_rpm = xe_dbg_gt_snapshot_capture(gt,
> + other_gt,
> + XE_DBG_REGSET_RPM,
> + XE_GT_TYPE_MAIN);
> + ss->media_gt_rpm = xe_dbg_gt_snapshot_capture(gt,
> + other_gt,
> + XE_DBG_REGSET_RPM,
> + XE_GT_TYPE_MEDIA);
> +}
> +
> static void devcoredump_snapshot(struct xe_devcoredump *coredump,
> struct xe_gt *gt,
> struct xe_exec_queue *q,
> @@ -328,6 +541,7 @@ static void devcoredump_snapshot(struct
> xe_devcoredump *coredump,
> struct xe_guc *guc = >->uc.guc;
> const char *process_name = "no process";
> bool cookie;
> + struct xe_gt *other_gt;
>
> ss->snapshot_time = ktime_get_real();
> ss->boot_time = ktime_get_boottime();
> @@ -342,11 +556,23 @@ static void devcoredump_snapshot(struct
> xe_devcoredump *coredump,
> ss->gt = gt;
> INIT_WORK(&ss->work, xe_devcoredump_deferred_snap_work);
>
> - /* keep going if fw fails as we still want to save the memory and SW
> data */
> + /* fw_ref_other must stay in scope through the register captures
> below
> +*/
May be misplaced comment? Needed below?
Tejas
> CLASS(xe_force_wake, fw_ref)(gt_to_fw(gt), XE_FORCEWAKE_ALL);
>
> cookie = dma_fence_begin_signalling();
>
> + other_gt = gt->tile->media_gt == gt ? gt->tile->primary_gt
> + : gt->tile->media_gt;
> + if (other_gt) {
> + CLASS(xe_force_wake, fw_ref_other)(gt_to_fw(other_gt),
> + XE_FORCEWAKE_ALL);
> + if (!xe_force_wake_ref_has_domain(fw_ref_other.domains,
> XE_FORCEWAKE_ALL))
> + other_gt = NULL;
> + xe_devcoredump_capture_gt_regs(ss, gt, other_gt);
> + } else {
> + xe_devcoredump_capture_gt_regs(ss, gt, NULL);
> + }
> +
> ss->guc.log = xe_guc_log_snapshot_capture(&guc->log, true);
> ss->guc.ct = xe_guc_ct_snapshot_capture(&guc->ct);
>
> diff --git a/drivers/gpu/drm/xe/xe_devcoredump_types.h
> b/drivers/gpu/drm/xe/xe_devcoredump_types.h
> index a174385a6d83..e2fac33dce09 100644
> --- a/drivers/gpu/drm/xe/xe_devcoredump_types.h
> +++ b/drivers/gpu/drm/xe/xe_devcoredump_types.h
> @@ -14,6 +14,48 @@
> struct xe_device;
> struct xe_gt;
>
> +/**
> + * struct xe_reg_desc - Register descriptor struct to make reg list
> + *
> + * This struct is used as descriptor containing reg address and name
> + * of the register to dump its value during coredump for debug purpose.
> + */
> +struct xe_reg_desc {
> + /** @reg: The register */
> + struct xe_reg reg;
> + /** @name: Name of the register */
> + const char *name;
> +};
> +
> +/**
> + * struct xe_reg_desc_list - Struct for register descriptor list
> + *
> + * This struct is used to reference the corresponding reglist of
> + * various component
> + */
> +struct xe_reg_desc_list {
> + /** @regs: Pointer to an array of register descriptors. */
> + const struct xe_reg_desc *regs;
> + /** @num_regs: number of registers in the descriptor list*/
> + u32 num_regs;
> +};
> +
> +/**
> + * struct xe_dbg_reg_snapshot - Register snapshot
> + *
> + * This struct contains the register values captured at the time of the crash.
> + * It is used to store the register values in a human-readable format
> +for
> + * debugging purposes.
> + */
> +struct xe_dbg_reg_snapshot {
> + /** @desc: register descriptor list. */
> + const struct xe_reg_desc_list *desc;
> + /** @num_regs: Number of registers needed for capture. */
> + u32 num_regs;
> + /** @values: register values*/
> + u32 values[];
> +};
> +
> /**
> * struct xe_devcoredump_snapshot - Crash snapshot
> *
> @@ -35,6 +77,16 @@ struct xe_devcoredump_snapshot {
>
> /** @gt: Affected GT, used by forcewake for delayed capture */
> struct xe_gt *gt;
> +
> + /** @gt_fuse: Fuse snapshot */
> + struct xe_dbg_reg_snapshot *gt_fuse;
> + /** @media_fuse: Media Fuse snapshot */
> + struct xe_dbg_reg_snapshot *media_fuse;
> + /** @gt_rpm: GT RPM snapshot */
> + struct xe_dbg_reg_snapshot *gt_rpm;
> + /** @media_gt_rpm: Media GT RPM snapshot */
> + struct xe_dbg_reg_snapshot *media_gt_rpm;
> +
> /** @work: Workqueue for deferred capture outside of signaling
> context */
> struct work_struct work;
>
> --
> 2.43.0
^ permalink raw reply [flat|nested] 23+ messages in thread
* RE: [PATCH v5 2/7] drm/xe/devcoredump: Add GuC register snapshot to devcoredump
2026-10-23 6:05 ` [PATCH v5 2/7] drm/xe/devcoredump: Add GuC register snapshot to devcoredump Nareshkumar Gollakoti
@ 2026-10-26 6:35 ` Upadhyay, Tejas
0 siblings, 0 replies; 23+ messages in thread
From: Upadhyay, Tejas @ 2026-10-26 6:35 UTC (permalink / raw)
To: Kumar G, Naresh, intel-xe@lists.freedesktop.org
> -----Original Message-----
> From: Kumar G, Naresh <naresh.kumar.g@intel.com>
> Sent: 23 October 2026 11:36
> To: intel-xe@lists.freedesktop.org
> Cc: Upadhyay, Tejas <tejas.upadhyay@intel.com>; Kumar G, Naresh
> <naresh.kumar.g@intel.com>
> Subject: [PATCH v5 2/7] drm/xe/devcoredump: Add GuC register snapshot to
> devcoredump
>
> Add support for capturing GuC register state as part of the xe devcoredump
> snapshot.
>
> Define a dedicated GuC register snapshot structure, record selected GT and
> media GuC status/error registers during devcoredump capture, and free the
> snapshot during teardown.
>
> Keeping these register values in the devcoredump helps with post-mortem
> analysis of GuC-related failures.
>
> v2:(Sashiko)
> - Reuse the generic target GT snapshot helper for GuC register capture
> - Capture primary and media GuC registers using correct GT MMIO context
> - Avoid reading the same on SR-IOV VF
> - skip reading media GT GuC registers when media is not present
> - drop hardcoded media register address macros
>
> v5:
> - Rebase as per patch1 changes
>
> Signed-off-by: Nareshkumar Gollakoti <naresh.kumar.g@intel.com>
> ---
> drivers/gpu/drm/xe/regs/xe_guc_regs.h | 5 ++++
> drivers/gpu/drm/xe/xe_devcoredump.c | 35
> +++++++++++++++++++++++
> drivers/gpu/drm/xe/xe_devcoredump_types.h | 5 ++++
> 3 files changed, 45 insertions(+)
>
> diff --git a/drivers/gpu/drm/xe/regs/xe_guc_regs.h
> b/drivers/gpu/drm/xe/regs/xe_guc_regs.h
> index 5faac8316b66..c13ee6e21e37 100644
> --- a/drivers/gpu/drm/xe/regs/xe_guc_regs.h
> +++ b/drivers/gpu/drm/xe/regs/xe_guc_regs.h
> @@ -150,6 +150,11 @@
> #define GUC_INTR_SW_INT_1 REG_BIT(1)
> #define GUC_INTR_SW_INT_0 REG_BIT(0)
>
> +#define GUC_DEVICEID XE_REG(0xc008)
> +#define GUC_SHIM_ERR_TRAP XE_REG(0xc070)
> +#define GUC_HW_FATL_ERR XE_REG(0xc598)
> +#define GUC_HW_NOTIFY_ERR XE_REG(0xc59c)
> +
Same comment for right GUC register names, with that this LGTM,
Reviewed-by: Tejas Upadhyay <tejas.upadhyay@intel.com>
Tejas
> #define GUC_NUM_DOORBELLS 256
>
> /* format of the HW-monitored doorbell cacheline */ diff --git
> a/drivers/gpu/drm/xe/xe_devcoredump.c
> b/drivers/gpu/drm/xe/xe_devcoredump.c
> index f59f93ba5949..49a7c020a161 100644
> --- a/drivers/gpu/drm/xe/xe_devcoredump.c
> +++ b/drivers/gpu/drm/xe/xe_devcoredump.c
> @@ -27,6 +27,7 @@
> #include "xe_vm.h"
> #include "xe_mmio.h"
> #include "regs/xe_gt_regs.h"
> +#include "regs/xe_guc_regs.h"
>
> /**
> * DOC: Xe device coredump
> @@ -73,6 +74,16 @@
>
> #define XE_REG_DESC(_reg, _name) { .reg = (_reg), .name = (_name) }
>
> +static const struct xe_reg_desc xe_dbg_gt_guc_reglist[] = {
> + XE_REG_DESC(GUC_STATUS, "GUC_STATUS"),
> + XE_REG_DESC(GUC_WOPCM_SIZE, "GUC_WOPCM_SIZE"),
> + XE_REG_DESC(GUC_DEVICEID, "GUC_DEVICEID"),
> + XE_REG_DESC(DMA_CTRL, "DMA_CTRL"),
> + XE_REG_DESC(GUC_HW_FATL_ERR, "GUC_HW_FATL_ERR"),
> + XE_REG_DESC(GUC_HW_NOTIFY_ERR, "GUC_HW_NOTIFY_ERR"),
> + XE_REG_DESC(GUC_SHIM_ERR_TRAP, "GUC_SHIM_ERR_TRAP"),
> +};
> +
> static const struct xe_reg_desc xe_dbg_gt_fuse_reglist[] = {
> XE_REG_DESC(XELP_GT_GEOMETRY_DSS_ENABLE,
> "GT_GEOMETRY_DSS_ENABLE"),
> XE_REG_DESC(XEHP_GT_COMPUTE_DSS_ENABLE,
> "GT_COMPUTE_DSS_ENABLE"), @@ -121,11 +132,13 @@ struct
> xe_gt_regset {
> * enum xe_dbg_regset_type - debug register set types
> * @XE_DBG_REGSET_FUSE: Fuse register set
> * @XE_DBG_REGSET_RPM: RPM register set
> + * @XE_DBG_REGSET_GUC: GUC register set
> * @XE_DBG_REGSET_MAX: Number of debug register set types
> */
> enum xe_dbg_regset_type {
> XE_DBG_REGSET_FUSE,
> XE_DBG_REGSET_RPM,
> + XE_DBG_REGSET_GUC,
> XE_DBG_REGSET_MAX,
> };
>
> @@ -142,6 +155,12 @@ static const struct xe_gt_regset
> xe_dbg_regsets[XE_DBG_REGSET_MAX] = {
> .gt[XE_GT_TYPE_MEDIA] = { xe_dbg_media_gt_rpm_reglist,
>
> ARRAY_SIZE(xe_dbg_media_gt_rpm_reglist) },
> },
> + [XE_DBG_REGSET_GUC] = {
> + .gt[XE_GT_TYPE_MAIN] = { xe_dbg_gt_guc_reglist,
> + ARRAY_SIZE(xe_dbg_gt_guc_reglist) },
> + .gt[XE_GT_TYPE_MEDIA] = { xe_dbg_gt_guc_reglist,
> + ARRAY_SIZE(xe_dbg_gt_guc_reglist)
> },
> + },
> };
>
> static void xe_dbg_reg_snapshot_print(struct drm_printer *p, @@ -288,6
> +307,8 @@ static ssize_t __xe_devcoredump_read(char *buffer, ssize_t count,
> xe_dbg_reg_snapshot_print(&p, "Media GT Fuse Register Dump", ss-
> >media_fuse);
> xe_gt_rpm_snapshot_print(&p, "GT RPM Register Dump", ss-
> >gt_rpm);
> xe_dbg_reg_snapshot_print(&p, "Media GT RPM Register Dump", ss-
> >media_gt_rpm);
> + xe_dbg_reg_snapshot_print(&p, "GT GuC Register Dump", ss-
> >gt_guc_reg);
> + xe_dbg_reg_snapshot_print(&p, "Media GT GuC Register Dump",
> +ss->media_gt_guc_reg);
>
> drm_puts(&p, "\n**** GuC Log ****\n");
> xe_guc_log_snapshot_print(ss->guc.log, &p, ss->gt); @@ -338,6
> +359,12 @@ static void xe_devcoredump_snapshot_free(struct
> xe_devcoredump_snapshot *ss)
> xe_dbg_reg_snapshot_free(ss->media_gt_rpm);
> ss->media_gt_rpm = NULL;
>
> + xe_dbg_reg_snapshot_free(ss->gt_guc_reg);
> + ss->gt_guc_reg = NULL;
> +
> + xe_dbg_reg_snapshot_free(ss->media_gt_guc_reg);
> + ss->media_gt_guc_reg = NULL;
> +
> if (!IS_ERR_OR_NULL(ss->gt))
> xe_guc_capture_put_matched_nodes(&ss->gt->uc.guc);
> ss->matched_node = NULL;
> @@ -530,6 +557,14 @@ static void xe_devcoredump_capture_gt_regs(struct
> xe_devcoredump_snapshot *ss,
> other_gt,
> XE_DBG_REGSET_RPM,
> XE_GT_TYPE_MEDIA);
> + ss->gt_guc_reg = xe_dbg_gt_snapshot_capture(gt,
> + other_gt,
> + XE_DBG_REGSET_GUC,
> + XE_GT_TYPE_MAIN);
> + ss->media_gt_guc_reg = xe_dbg_gt_snapshot_capture(gt,
> + other_gt,
> +
> XE_DBG_REGSET_GUC,
> +
> XE_GT_TYPE_MEDIA);
> }
>
> static void devcoredump_snapshot(struct xe_devcoredump *coredump, diff -
> -git a/drivers/gpu/drm/xe/xe_devcoredump_types.h
> b/drivers/gpu/drm/xe/xe_devcoredump_types.h
> index e2fac33dce09..52db64640f89 100644
> --- a/drivers/gpu/drm/xe/xe_devcoredump_types.h
> +++ b/drivers/gpu/drm/xe/xe_devcoredump_types.h
> @@ -87,6 +87,11 @@ struct xe_devcoredump_snapshot {
> /** @media_gt_rpm: Media GT RPM snapshot */
> struct xe_dbg_reg_snapshot *media_gt_rpm;
>
> + /** @gt_guc_reg: gt guc reg snapshot */
> + struct xe_dbg_reg_snapshot *gt_guc_reg;
> + /** @media_gt_guc_reg: media gt guc reg snapshot */
> + struct xe_dbg_reg_snapshot *media_gt_guc_reg;
> +
> /** @work: Workqueue for deferred capture outside of signaling
> context */
> struct work_struct work;
>
> --
> 2.43.0
^ permalink raw reply [flat|nested] 23+ messages in thread
* RE: [PATCH v5 3/7] drm/xe/guc: Print register addresses in capture snapshot output
2026-10-23 6:05 ` [PATCH v5 3/7] drm/xe/guc: Print register addresses in capture snapshot output Nareshkumar Gollakoti
2026-10-23 13:14 ` Upadhyay, Tejas
@ 2026-10-26 6:37 ` Upadhyay, Tejas
1 sibling, 0 replies; 23+ messages in thread
From: Upadhyay, Tejas @ 2026-10-26 6:37 UTC (permalink / raw)
To: Kumar G, Naresh, intel-xe@lists.freedesktop.org
> -----Original Message-----
> From: Kumar G, Naresh <naresh.kumar.g@intel.com>
> Sent: 23 October 2026 11:36
> To: intel-xe@lists.freedesktop.org
> Cc: Upadhyay, Tejas <tejas.upadhyay@intel.com>; Kumar G, Naresh
> <naresh.kumar.g@intel.com>
> Subject: [PATCH v5 3/7] drm/xe/guc: Print register addresses in capture
> snapshot output
>
> Include register offsets in GuC capture snapshot print output for both 32-bit
> and 64-bit registers.
>
> When dumping captured engine register state, print each register name
> alongside its MMIO offset to make the snapshot output easier to cross-
> reference with register definitions and hardware debug documentation.
>
> This improves postmortem analysis without changing capture contents.
>
> v2:(Sashiko)
> - Ensure lower DWORD prints
>
> v3:(Sashiko)
> - Use the LOW_DW MMIO offset(capture in last_address) when combined
> 64bit
> register values in the dump instead of HI_SW offset
> - preserve existing coredump register-name format and append register
> address as trailing metadata as a debug info and avoids disrupting
> existing format
>
> Signed-off-by: Nareshkumar Gollakoti <naresh.kumar.g@intel.com>
Adding offset as requirement posted, LGTM,
Reviewed-by: Tejas Upadhyay <tejas.upadhyay@intel.com>
Tejas
> ---
> drivers/gpu/drm/xe/xe_guc_capture.c | 18 ++++++++++++++----
> 1 file changed, 14 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/gpu/drm/xe/xe_guc_capture.c
> b/drivers/gpu/drm/xe/xe_guc_capture.c
> index 5a4d085660a2..3e99aef53b46 100644
> --- a/drivers/gpu/drm/xe/xe_guc_capture.c
> +++ b/drivers/gpu/drm/xe/xe_guc_capture.c
> @@ -1716,6 +1716,7 @@ snapshot_print_by_list_order(struct
> xe_hw_engine_snapshot *snapshot, struct drm_
> struct xe_devcoredump_snapshot *devcore_snapshot =
> &devcoredump->snapshot;
> struct gcap_reg_list_info *reginfo = NULL;
> u32 i, last_value = 0;
> + u32 last_address = 0;
> bool low32_ready = false;
>
> if (!list || !list->list || list->num_regs == 0) @@ -1743,6 +1744,7 @@
> snapshot_print_by_list_order(struct xe_hw_engine_snapshot *snapshot,
> struct drm_
> switch (reg_desc->data_type) {
> case REG_64BIT_LOW_DW:
> last_value = value;
> + last_address = reg_desc->reg.addr;
>
> /*
> * A 64 bit register define requires 2 consecutive @@ -
> 1774,7 +1776,11 @@ snapshot_print_by_list_order(struct
> xe_hw_engine_snapshot *snapshot, struct drm_
> XE_WARN_ON(!low32_ready);
> low32_ready = false;
>
> - drm_printf(p, "\t%s: 0x%016llx\n", reg_desc-
> >regname, value_qw);
> + drm_printf(p, "\t%s: 0x%016llx [addr=0x%x]\n",
> + reg_desc->regname,
> + value_qw,
> + last_address);
> +
> break;
> }
>
> @@ -1788,10 +1794,14 @@ snapshot_print_by_list_order(struct
> xe_hw_engine_snapshot *snapshot, struct drm_
> XE_WARN_ON(low32_ready);
>
> if (FIELD_GET(GUC_REGSET_STEERING_NEEDED,
> reg_desc->flags))
> - drm_printf(p, "\t%s[%u]: 0x%08x\n",
> reg_desc->regname,
> - reg_desc->dss_id, value);
> + drm_printf(p, "\t%s[%u]: 0x%08x
> [addr=0x%x]\n",
> + reg_desc->regname,
> + reg_desc->dss_id, value, reg_desc-
> >reg.addr);
> +
> else
> - drm_printf(p, "\t%s: 0x%08x\n", reg_desc-
> >regname, value);
> + drm_printf(p, "\t%s: 0x%08x [addr=0x%x]\n",
> + reg_desc->regname, value,
> reg_desc->reg.addr);
> +
>
> break;
> }
> --
> 2.43.0
^ permalink raw reply [flat|nested] 23+ messages in thread
* RE: [PATCH v5 4/7] drm/xe: dump GAM page fault report registers in devcoredump
2026-10-23 6:05 ` [PATCH v5 4/7] drm/xe: dump GAM page fault report registers in devcoredump Nareshkumar Gollakoti
2026-10-23 6:31 ` sashiko-bot
@ 2026-10-26 6:48 ` Upadhyay, Tejas
1 sibling, 0 replies; 23+ messages in thread
From: Upadhyay, Tejas @ 2026-10-26 6:48 UTC (permalink / raw)
To: Kumar G, Naresh, intel-xe@lists.freedesktop.org
> -----Original Message-----
> From: Kumar G, Naresh <naresh.kumar.g@intel.com>
> Sent: 23 October 2026 11:36
> To: intel-xe@lists.freedesktop.org
> Cc: Upadhyay, Tejas <tejas.upadhyay@intel.com>; Kumar G, Naresh
> <naresh.kumar.g@intel.com>
> Subject: [PATCH v5 4/7] drm/xe: dump GAM page fault report registers in
> devcoredump
>
> Add PAGE_FLTRPTQ_HEAD_GAMCTRL and PAGE_FLTRPTQ_TAIL_GAMCTRL to
> the Xe register definitions and capture them as part of the devcoredump
> snapshot.
>
> Include the register dump in the devcoredump output and release the
> snapshot during cleanup so page fault report state is available for post-
> mortem debugging.
>
> v2:
> - As design change made for previous patches. refactored this patch
> as well to accommodate those changes.
> - Add PF occurred print when the two register values are not equal
>
> v4:
> Refactored as per the patch1 change(Tejas)
>
> v5:
> Refactored as per patch1 changes
>
> Signed-off-by: Nareshkumar Gollakoti <naresh.kumar.g@intel.com>
> ---
> drivers/gpu/drm/xe/regs/xe_gt_regs.h | 3 ++
> drivers/gpu/drm/xe/xe_devcoredump.c | 37
> +++++++++++++++++++++++
> drivers/gpu/drm/xe/xe_devcoredump_types.h | 3 ++
> 3 files changed, 43 insertions(+)
>
> diff --git a/drivers/gpu/drm/xe/regs/xe_gt_regs.h
> b/drivers/gpu/drm/xe/regs/xe_gt_regs.h
> index e93895e0c731..e9eb0bd04af1 100644
> --- a/drivers/gpu/drm/xe/regs/xe_gt_regs.h
> +++ b/drivers/gpu/drm/xe/regs/xe_gt_regs.h
> @@ -530,6 +530,9 @@
> #define LMEM_EN REG_BIT(31)
> #define LMTT_DIR_PTR REG_GENMASK(30,
> 0) /* in multiples of 64KB */
>
> +#define PAGE_FLTRPTQ_HEAD_GAMCTRL XE_REG(0xcf90)
> +#define PAGE_FLTRPTQ_TAIL_GAMCTRL XE_REG(0xcf94)
Apart from all other previous comments applied here, PAGE_FLTRPTQ_HEAD_GAMCTRL (0xcf90) and PAGE_FLTRPTQ_TAIL_GAMCTRL (0xcf94) fall inside a documented MCR (multicast/replicated) address range, so you need XE_REG_MCR
Tejas
> +
> #define HALF_SLICE_CHICKEN5 XE_REG_MCR(0xe188,
> XE_REG_OPTION_MASKED)
> #define DISABLE_SAMPLE_G_PERFORMANCE REG_BIT(0)
>
> diff --git a/drivers/gpu/drm/xe/xe_devcoredump.c
> b/drivers/gpu/drm/xe/xe_devcoredump.c
> index 49a7c020a161..8d59f80e2929 100644
> --- a/drivers/gpu/drm/xe/xe_devcoredump.c
> +++ b/drivers/gpu/drm/xe/xe_devcoredump.c
> @@ -114,6 +114,11 @@ static const struct xe_reg_desc
> xe_dbg_media_gt_rpm_reglist[] = {
> XE_REG_DESC(RPM_GCD, "RPM_GCD"),
> };
>
> +static const struct xe_reg_desc xe_dbg_gam_pf_reglist[] = {
> + XE_REG_DESC(PAGE_FLTRPTQ_HEAD_GAMCTRL,
> "PAGE_FLTRPTQ_HEAD_GAMCTRL"),
> + XE_REG_DESC(PAGE_FLTRPTQ_TAIL_GAMCTRL,
> "PAGE_FLTRPTQ_TAIL_GAMCTRL"),
> +};
> +
> /**
> * struct xe_gt_regset - Struct for register descriptor list for GT
> *
> @@ -133,12 +138,14 @@ struct xe_gt_regset {
> * @XE_DBG_REGSET_FUSE: Fuse register set
> * @XE_DBG_REGSET_RPM: RPM register set
> * @XE_DBG_REGSET_GUC: GUC register set
> + * @XE_DBG_REGSET_GAM_PF: GAM Pagefault registers set
> * @XE_DBG_REGSET_MAX: Number of debug register set types
> */
> enum xe_dbg_regset_type {
> XE_DBG_REGSET_FUSE,
> XE_DBG_REGSET_RPM,
> XE_DBG_REGSET_GUC,
> + XE_DBG_REGSET_GAM_PF,
> XE_DBG_REGSET_MAX,
> };
>
> @@ -161,6 +168,10 @@ static const struct xe_gt_regset
> xe_dbg_regsets[XE_DBG_REGSET_MAX] = {
> .gt[XE_GT_TYPE_MEDIA] = { xe_dbg_gt_guc_reglist,
> ARRAY_SIZE(xe_dbg_gt_guc_reglist)
> },
> },
> + [XE_DBG_REGSET_GAM_PF] = {
> + .gt[XE_GT_TYPE_MAIN] = { xe_dbg_gam_pf_reglist,
> + ARRAY_SIZE(xe_dbg_gam_pf_reglist)
> },
> + },
> };
>
> static void xe_dbg_reg_snapshot_print(struct drm_printer *p, @@ -202,6
> +213,23 @@ static const u32 *xe_dbg_find_value(const struct
> xe_dbg_reg_snapshot *snap,
> return NULL;
> }
>
> +static void xe_gam_pf_snapshot_print(struct drm_printer *p,
> + const char *title,
> + const struct xe_dbg_reg_snapshot *snap) {
> + const u32 *val1, *val2;
> +
> + xe_dbg_reg_snapshot_print(p, title, snap);
> +
> + if (!snap)
> + return;
> +
> + val1 = xe_dbg_find_value(snap, PAGE_FLTRPTQ_HEAD_GAMCTRL);
> + val2 = xe_dbg_find_value(snap, PAGE_FLTRPTQ_TAIL_GAMCTRL);
> + if ((val1 && val2) && (*val1 != *val2))
> + drm_printf(p, "PF occurred, refer to dmesg log for PF info\n");
> }
> +
> static void xe_gt_rpm_snapshot_print(struct drm_printer *p,
> const char *title,
> const struct xe_dbg_reg_snapshot *snap)
> @@ -315,6 +343,8 @@ static ssize_t __xe_devcoredump_read(char *buffer,
> ssize_t count,
> drm_puts(&p, "\n**** GuC CT ****\n");
> xe_guc_ct_snapshot_print(ss->guc.ct, &p, ss->gt);
>
> + xe_gam_pf_snapshot_print(&p, "GAM PF Report", ss-
> >gam_pf_report);
> +
> drm_puts(&p, "\n**** Contexts ****\n");
> xe_guc_exec_queue_snapshot_print(ss->ge, &p);
>
> @@ -369,6 +399,9 @@ static void xe_devcoredump_snapshot_free(struct
> xe_devcoredump_snapshot *ss)
> xe_guc_capture_put_matched_nodes(&ss->gt->uc.guc);
> ss->matched_node = NULL;
>
> + xe_dbg_reg_snapshot_free(ss->gam_pf_report);
> + ss->gam_pf_report = NULL;
> +
> xe_guc_exec_queue_snapshot_free(ss->ge);
> ss->ge = NULL;
>
> @@ -565,6 +598,10 @@ static void xe_devcoredump_capture_gt_regs(struct
> xe_devcoredump_snapshot *ss,
> other_gt,
>
> XE_DBG_REGSET_GUC,
>
> XE_GT_TYPE_MEDIA);
> + ss->gam_pf_report = xe_dbg_gt_snapshot_capture(gt,
> + other_gt,
> +
> XE_DBG_REGSET_GAM_PF,
> + XE_GT_TYPE_MAIN);
> }
>
> static void devcoredump_snapshot(struct xe_devcoredump *coredump, diff -
> -git a/drivers/gpu/drm/xe/xe_devcoredump_types.h
> b/drivers/gpu/drm/xe/xe_devcoredump_types.h
> index 52db64640f89..34f224a6751f 100644
> --- a/drivers/gpu/drm/xe/xe_devcoredump_types.h
> +++ b/drivers/gpu/drm/xe/xe_devcoredump_types.h
> @@ -103,6 +103,9 @@ struct xe_devcoredump_snapshot {
> struct xe_guc_log_snapshot *log;
> } guc;
>
> + /** @gam_pf_report: GAM PF report snapshot */
> + struct xe_dbg_reg_snapshot *gam_pf_report;
> +
> /** @ge: GuC Submission Engine snapshot */
> struct xe_guc_submit_exec_queue_snapshot *ge;
>
> --
> 2.43.0
^ permalink raw reply [flat|nested] 23+ messages in thread
* RE: [PATCH v5 5/7] drm/xe/guc: add TDL, SLICE gfx registers to capture list
2026-10-23 6:05 ` [PATCH v5 5/7] drm/xe/guc: add TDL, SLICE gfx registers to capture list Nareshkumar Gollakoti
@ 2026-10-26 6:55 ` Upadhyay, Tejas
0 siblings, 0 replies; 23+ messages in thread
From: Upadhyay, Tejas @ 2026-10-26 6:55 UTC (permalink / raw)
To: Kumar G, Naresh, intel-xe@lists.freedesktop.org
> -----Original Message-----
> From: Kumar G, Naresh <naresh.kumar.g@intel.com>
> Sent: 23 October 2026 11:36
> To: intel-xe@lists.freedesktop.org
> Cc: Upadhyay, Tejas <tejas.upadhyay@intel.com>; Kumar G, Naresh
> <naresh.kumar.g@intel.com>
> Subject: [PATCH v5 5/7] drm/xe/guc: add TDL,SLICE gfx registers to capture list
>
> Add ROW_INSTDONE_TDL_GFX, SS_LSC_HDC_IDLE_TDL_GFX and
> SLICE_ARB_STATUS register definitions and include them in the XeHPG
> extended GuC capture register list.
>
> v2:(Sashiko)
> - Refactored ROW_INSTDONE_TDL_GFX to ROW_INSTDONE_TDL_GFX
> - Add SLICE_ARB_STATUS register to xeHP register list
> - Refactor commit message
>
> Signed-off-by: Nareshkumar Gollakoti <naresh.kumar.g@intel.com>
With addressing register name comments, this LGTM :
Reviewed-by: Tejas Upadhyay <tejas.upadhyay@intel.com>
Tejas
> ---
> drivers/gpu/drm/xe/regs/xe_gt_regs.h | 5 +++++
> drivers/gpu/drm/xe/xe_guc_capture.c | 5 ++++-
> 2 files changed, 9 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/xe/regs/xe_gt_regs.h
> b/drivers/gpu/drm/xe/regs/xe_gt_regs.h
> index e9eb0bd04af1..2e4cb4957479 100644
> --- a/drivers/gpu/drm/xe/regs/xe_gt_regs.h
> +++ b/drivers/gpu/drm/xe/regs/xe_gt_regs.h
> @@ -533,6 +533,8 @@
> #define PAGE_FLTRPTQ_HEAD_GAMCTRL XE_REG(0xcf90)
> #define PAGE_FLTRPTQ_TAIL_GAMCTRL XE_REG(0xcf94)
>
> +#define SLICE_ARB_STATUS XE_REG_MCR(0xd814)
> +
> #define HALF_SLICE_CHICKEN5 XE_REG_MCR(0xe188,
> XE_REG_OPTION_MASKED)
> #define DISABLE_SAMPLE_G_PERFORMANCE REG_BIT(0)
>
> @@ -597,6 +599,9 @@
> #define EU_SYSTOLIC_LIC_THROTTLE_CTL_WITH_LOCK
> XE_REG_MCR(0xe534)
> #define EU_SYSTOLIC_LIC_THROTTLE_CTL_LOCK_BIT REG_BIT(31)
>
> +#define ROW_INSTDONE_TDL_GFX
> XE_REG_MCR(0xe580)
> +#define SS_LSC_HDC_IDLE_TDL_GFX
> XE_REG_MCR(0xe584)
> +
> #define XEHP_HDC_CHICKEN0
> XE_REG_MCR(0xe5f0, XE_REG_OPTION_MASKED)
> #define LSC_L1_FLUSH_CTL_3D_DATAPORT_FLUSH_EVENTS_MASK
> REG_GENMASK(13, 11)
> #define DIS_ATOMIC_CHAINING_TYPED_WRITES REG_BIT(3)
> diff --git a/drivers/gpu/drm/xe/xe_guc_capture.c
> b/drivers/gpu/drm/xe/xe_guc_capture.c
> index 3e99aef53b46..6a20eab0f820 100644
> --- a/drivers/gpu/drm/xe/xe_guc_capture.c
> +++ b/drivers/gpu/drm/xe/xe_guc_capture.c
> @@ -376,7 +376,10 @@ static const struct __ext_steer_reg xehpg_extregs[]
> = {
> {"SC_INSTDONE", XEHPG_SC_INSTDONE},
> {"SC_INSTDONE_EXTRA",
> XEHPG_SC_INSTDONE_EXTRA},
> {"SC_INSTDONE_EXTRA2",
> XEHPG_SC_INSTDONE_EXTRA2},
> - {"INSTDONE_GEOM_SVGUNIT",
> XEHPG_INSTDONE_GEOM_SVGUNIT}
> + {"INSTDONE_GEOM_SVGUNIT",
> XEHPG_INSTDONE_GEOM_SVGUNIT},
> + {"ROW_INSTDONE_TDL_GFX", ROW_INSTDONE_TDL_GFX},
> + {"SS_LSC_HDC_IDLE_TDL_GFX", SS_LSC_HDC_IDLE_TDL_GFX},
> + {"SLICE_ARB_STATUS", SLICE_ARB_STATUS}
> };
>
> static void __fill_ext_reg(struct __guc_mmio_reg_descr *ext,
> --
> 2.43.0
^ permalink raw reply [flat|nested] 23+ messages in thread
* RE: [PATCH v5 7/7] drm/xe/guc: capture additional engine state registers
2026-10-23 6:05 ` [PATCH v5 7/7] drm/xe/guc: capture additional engine state registers Nareshkumar Gollakoti
2026-10-23 6:26 ` sashiko-bot
@ 2026-10-26 9:15 ` Upadhyay, Tejas
1 sibling, 0 replies; 23+ messages in thread
From: Upadhyay, Tejas @ 2026-10-26 9:15 UTC (permalink / raw)
To: Kumar G, Naresh, intel-xe@lists.freedesktop.org
> -----Original Message-----
> From: Kumar G, Naresh <naresh.kumar.g@intel.com>
> Sent: 23 October 2026 11:36
> To: intel-xe@lists.freedesktop.org
> Cc: Upadhyay, Tejas <tejas.upadhyay@intel.com>; Kumar G, Naresh
> <naresh.kumar.g@intel.com>
> Subject: [PATCH v5 7/7] drm/xe/guc: capture additional engine state registers
>
> Add a wider set of engine state registers to GuC error capture to improve post-
> mortem debugging of engine hangs and reset-related failures.
>
> Define the missing register offsets in xe_engine_regs.h and include them in the
> GuC capture list. The additional registers cover reset state, front-end and back-
> end FSM state, power state, batch buffer state, instruction state, preemption
> status, and related chicken/debug controls.
>
> This provides more complete engine context in capture dumps, which should
> help root-cause analysis when investigating GuC-reported engine failures.
>
> v3:(Sashiko)
> - Move FF_SLICE_CS_CHICKEN1/2 out of
> COMMON_BASE_ENGINE_INSTANCE
> - Add XE3P_RC_SLICE_INSTANCE and include it only in xe3p_rc_inst_regs[]
> - Add XE_BCS_RCS_ENGINE_INSTANCE for registers shared only by
> BCS/RCS paths
> - Include XE_BCS_RCS_ENGINE_INSTANCE only in
> xe_blt_inst_regs[] and xe3p_rc_inst_regs[]
> - Keep COMMON_BASE_ENGINE_INSTANCE limited to registers
> valid across all engine classes
>
> v5:(Sashiko)
> - Keep RING_EXECLIST_* in COMMON_BASE_ENGINE_INSTANCE
> - Drop XE_BCS_RCS_ENGINE_INSTANCE
> - BCS_SWCTRL only on xe3p_blt_inst_regs
> - CS_DEBUG_MODE1/CS_CHICKEN1/CS_PREEMPTION_STATUS only on
> xe3p_rc_inst_regs
>
> Signed-off-by: Nareshkumar Gollakoti <naresh.kumar.g@intel.com>
> ---
> drivers/gpu/drm/xe/regs/xe_engine_regs.h | 22 +++++++++
> drivers/gpu/drm/xe/xe_guc_capture.c | 57 ++++++++++++++++++++++--
> 2 files changed, 76 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/gpu/drm/xe/regs/xe_engine_regs.h
> b/drivers/gpu/drm/xe/regs/xe_engine_regs.h
> index 94033982e694..9f328b1b18f5 100644
> --- a/drivers/gpu/drm/xe/regs/xe_engine_regs.h
> +++ b/drivers/gpu/drm/xe/regs/xe_engine_regs.h
> @@ -60,6 +60,8 @@
>
Can you check below, I see they are missed :
1. 0xe4 (FF_SLICE_CS_CHICKEN2) is defined but not wired
2. Ring buffer section: 0x14c is missing
3. BB registers section: 0x150 and 0x170 are both missing
4. Also double check mcr/non-mcr, just for double verification.
Tejas
> #define RING_START_UDW(base) XE_REG((base) +
> 0x48)
>
> +#define RING_CSFE_GLB_CHICKEN3(base) XE_REG((base) +
> 0x4c)
> +
> #define RING_PSMI_CTL(base) XE_REG((base) + 0x50,
> XE_REG_OPTION_MASKED)
> #define RC_SEMA_IDLE_MSG_DISABLE REG_BIT(12)
> #define WAIT_FOR_EVENT_POWER_DOWN_DISABLE REG_BIT(7)
> @@ -72,6 +74,7 @@
> #define RING_DMA_FADD_UDW(base) XE_REG((base) +
> 0x60)
> #define RING_IPEHR(base) XE_REG((base) + 0x68)
> #define RING_INSTDONE(base) XE_REG((base) +
> 0x6c)
> +#define RING_INSTPS(base) XE_REG((base) + 0x70)
> #define RING_ACTHD(base) XE_REG((base) + 0x74)
> #define RING_DMA_FADD(base) XE_REG((base) +
> 0x78)
> #define RING_HWS_PGA(base) XE_REG((base) + 0x80)
> @@ -102,6 +105,8 @@
> #define SELECTIVE_READ_GROUP REG_GENMASK(29,
> 23)
> #define SELECTIVE_READ_INSTANCE REG_GENMASK(22, 16)
>
> +#define RESET_CTRL(base) XE_REG((base) + 0xd0)
> +
> /*
> * CMD_CCTL read/write fields take a MOCS value and _not_ a table index.
> * The lsb of each can be considered a separate enabling bit for encryption.
> @@ -123,15 +128,21 @@
> #define FF_SLICE_CS_CHICKEN1(base) XE_REG((base) + 0xe0,
> XE_REG_OPTION_MASKED)
> #define FFSC_PERCTX_PREEMPT_CTRL REG_BIT(14)
>
> +#define FF_SLICE_CS_CHICKEN2(base) XE_REG((base) + 0xe4,
> XE_REG_OPTION_MASKED)
> +
> #define CS_DEBUG_MODE1(base) XE_REG((base) + 0xec,
> XE_REG_OPTION_MASKED)
> #define FF_DOP_CLOCK_GATE_DISABLE REG_BIT(1)
> #define REPLAY_MODE_GRANULARITY REG_BIT(0)
>
> #define INDIRECT_RING_STATE(base) XE_REG((base) + 0x108)
>
> +#define RING_BB_STATE(base) XE_REG((base) + 0x110)
> +
> #define RING_BBADDR(base) XE_REG((base) + 0x140)
> #define RING_BBADDR_UDW(base) XE_REG((base) +
> 0x168)
>
> +#define RING_BB_ADDR_DIFF(base) XE_REG((base) +
> 0x154)
> +
> #define PR_CTR_CTRL(base) XE_REG((base) + 0x178)
> #define CTR_COUNT_SELECT_FF REG_BIT(31)
> #define CTR_LOGIC_OP_MASK REG_GENMASK(30,
> 0)
> @@ -148,6 +159,8 @@
> #define BLIT_CCTL_DST_MOCS_MASK REG_GENMASK(14, 9)
> #define BLIT_CCTL_SRC_MOCS_MASK REG_GENMASK(6, 1)
>
> +#define RING_CSBEFSM3(base) XE_REG((base) +
> 0x224)
> +
> #define RING_EXECLIST_STATUS_LO(base) XE_REG((base) +
> 0x234)
> #define RING_EXECLIST_STATUS_HI(base) XE_REG((base) +
> 0x234 + 4)
>
> @@ -169,9 +182,16 @@
> #define GFX_MSIX_INTERRUPT_ENABLE REG_BIT(13)
> #define GFX_DISABLE_LEGACY_MODE REG_BIT(3)
>
> +#define RING_CSFESM(base) XE_REG((base) + 0x2a0)
> +#define RING_CSFESM2(base) XE_REG((base) + 0x2a4)
> +#define RING_CSFESM3(base) XE_REG((base) + 0x2a8)
> +#define RING_CSPWRFSM(base) XE_REG((base) +
> 0x2ac)
> +
> #define RING_CSMQDEBUG(base) XE_REG((base) +
> 0x2b0)
> #define CURRENT_ACTIVE_QUEUE_ID_MASK REG_GENMASK(7, 0)
>
> +#define RING_CSBEFSM(base) XE_REG((base) + 0x2bc)
> +
> #define RING_QUEUE_TIMESTAMP(base) XE_REG((base) +
> 0x4c0)
> #define RING_QUEUE_TIMESTAMP_UDW(base)
> XE_REG((base) + 0x4c0 + 4)
>
> @@ -217,6 +237,8 @@
> #define PREEMPT_GPGPU_LEVEL_MASK
> PREEMPT_GPGPU_LEVEL(1, 1)
> #define PREEMPT_3D_OBJECT_LEVEL REG_BIT(0)
>
> +#define CS_PREEMPTION_STATUS(base) XE_REG((base) +
> 0x5ac)
> +
> #define CS_GPR_DATA(base, n) XE_REG((base) + 0x600 + (n) *
> 4)
> #define CS_GPR_REG(base, n) CS_GPR_DATA((base), (n) * 2)
> #define CS_GPR_REG_UDW(base, n) CS_GPR_DATA((base),
> (n) * 2 + 1)
> diff --git a/drivers/gpu/drm/xe/xe_guc_capture.c
> b/drivers/gpu/drm/xe/xe_guc_capture.c
> index 6a20eab0f820..2e13df97e106 100644
> --- a/drivers/gpu/drm/xe/xe_guc_capture.c
> +++ b/drivers/gpu/drm/xe/xe_guc_capture.c
> @@ -150,6 +150,33 @@ struct __guc_capture_parsed_output { #define
> XE3P_BASE_ENGINE_INSTANCE \
> { RING_CSMQDEBUG(0), REG_32BIT, 0, 0,
> 0, "CSMQDEBUG"}
>
> +#define XE3P_CS_DEBUG_INSTANCE \
> + { RESET_CTRL(0), REG_32BIT, 0, 0, 0,
> "RESET_CTRL"}, \
> + { RING_CSBEFSM3(0), REG_32BIT, 0, 0, 0,
> "RING_CSBEFSM3"}, \
> + { RING_CSFESM(0), REG_32BIT, 0, 0, 0,
> "RING_CSFESM"}, \
> + { RING_CSFESM2(0), REG_32BIT, 0, 0, 0,
> "RING_CSFESM2"}, \
> + { RING_CSFESM3(0), REG_32BIT, 0, 0, 0,
> "RING_CSFESM3"}, \
> + { RING_CSPWRFSM(0), REG_32BIT, 0, 0, 0,
> "RING_CSPWRFSM"}, \
> + { RING_CSBEFSM(0), REG_32BIT, 0, 0, 0,
> "RING_CSBEFSM"}, \
> + { RING_CSFE_GLB_CHICKEN3(0), REG_32BIT, 0, 0,
> 0, "RING_CSFE_GLB_CHICKEN3"}, \
> + { RING_PSMI_CTL(0), REG_32BIT, 0, 0, 0,
> "RING_PSMI_CTL"}, \
> + { RING_INSTPS(0), REG_32BIT, 0, 0, 0,
> "RING_INSTPS"}, \
> + { RING_BB_ADDR_DIFF(0), REG_32BIT, 0, 0,
> 0, "RING_BB_ADDR_DIFF"}, \
> + { RING_BB_STATE(0), REG_32BIT, 0, 0, 0,
> "RING_BB_STATE"}
> +
> +/*
> + * CS_CHICKEN1 has GPGPU/3D preempt bits; keep with RCS/CCS only.
> + * RCS+CCS share GUC_CAPTURE_LIST_CLASS_RENDER_COMPUTE, so these
> cannot
> + * be RCS-only.
> + */
> +#define XE3P_RC_CS_PREEMPT_INSTANCE \
> + { CS_DEBUG_MODE1(0), REG_32BIT, 0, 0,
> 0, "CS_DEBUG_MODE1"}, \
> + { CS_CHICKEN1(0), REG_32BIT, 0, 0, 0,
> "CS_CHICKEN1"}, \
> + { CS_PREEMPTION_STATUS(0), REG_32BIT, 0, 0, 0,
> "CS_PREEMPTION_STATUS"}
> +
> +#define XE3P_BCS_ONLY_INSTANCE \
> + { BCS_SWCTRL(0), REG_32BIT, 0, 0, 0,
> "BCS_SWCTRL"}
> +
> /* XE_LP Global */
> static const struct __guc_mmio_reg_descr xe_lp_global_regs[] = {
> COMMON_XELP_BASE_GLOBAL,
> @@ -186,9 +213,12 @@ static const struct __guc_mmio_reg_descr
> xe_vec_inst_regs[] = {
> COMMON_BASE_ENGINE_INSTANCE,
> };
>
> +#define XE_BLT_INST_REGS \
> + COMMON_BASE_ENGINE_INSTANCE
> +
> /* Blitter Per-Engine-Instance */
> static const struct __guc_mmio_reg_descr xe_blt_inst_regs[] = {
> - COMMON_BASE_ENGINE_INSTANCE,
> + XE_BLT_INST_REGS,
> };
>
> /* XE_LP - GSC Per-Engine-Instance */
> @@ -200,6 +230,15 @@ static const struct __guc_mmio_reg_descr
> xe_lp_gsc_inst_regs[] = { static const struct __guc_mmio_reg_descr
> xe3p_rc_inst_regs[] = {
> COMMON_BASE_ENGINE_INSTANCE,
> XE3P_BASE_ENGINE_INSTANCE,
> + XE3P_CS_DEBUG_INSTANCE,
> + XE3P_RC_CS_PREEMPT_INSTANCE,
> +};
> +
> +/* Xe3p Blitter Per-Engine-Instance */
> +static const struct __guc_mmio_reg_descr xe3p_blt_inst_regs[] = {
> + XE_BLT_INST_REGS,
> + XE3P_CS_DEBUG_INSTANCE,
> + XE3P_BCS_ONLY_INSTANCE,
> };
>
> /*
> @@ -264,7 +303,7 @@ static const struct __guc_mmio_reg_descr_group
> xe3p_lists[] = {
> MAKE_REGLIST(xe_vec_class_regs, PF, ENGINE_CLASS,
> GUC_CAPTURE_LIST_CLASS_VIDEOENHANCE),
> MAKE_REGLIST(xe_vec_inst_regs, PF, ENGINE_INSTANCE,
> GUC_CAPTURE_LIST_CLASS_VIDEOENHANCE),
> MAKE_REGLIST(empty_regs_list, PF, ENGINE_CLASS,
> GUC_CAPTURE_LIST_CLASS_BLITTER),
> - MAKE_REGLIST(xe_blt_inst_regs, PF, ENGINE_INSTANCE,
> GUC_CAPTURE_LIST_CLASS_BLITTER),
> + MAKE_REGLIST(xe3p_blt_inst_regs, PF, ENGINE_INSTANCE,
> +GUC_CAPTURE_LIST_CLASS_BLITTER),
> MAKE_REGLIST(empty_regs_list, PF, ENGINE_CLASS,
> GUC_CAPTURE_LIST_CLASS_GSC_OTHER),
> MAKE_REGLIST(xe_lp_gsc_inst_regs, PF, ENGINE_INSTANCE,
> GUC_CAPTURE_LIST_CLASS_GSC_OTHER),
> MAKE_REGLIST(empty_regs_list, PF, ENGINE_CLASS,
> GUC_CAPTURE_LIST_CLASS_PAGING), @@ -377,9 +416,12 @@ static const
> struct __ext_steer_reg xehpg_extregs[] = {
> {"SC_INSTDONE_EXTRA",
> XEHPG_SC_INSTDONE_EXTRA},
> {"SC_INSTDONE_EXTRA2",
> XEHPG_SC_INSTDONE_EXTRA2},
> {"INSTDONE_GEOM_SVGUNIT",
> XEHPG_INSTDONE_GEOM_SVGUNIT},
> +};
> +
> +static const struct __ext_steer_reg xe2_extregs[] = {
> {"ROW_INSTDONE_TDL_GFX", ROW_INSTDONE_TDL_GFX},
> {"SS_LSC_HDC_IDLE_TDL_GFX", SS_LSC_HDC_IDLE_TDL_GFX},
> - {"SLICE_ARB_STATUS", SLICE_ARB_STATUS}
> + {"SLICE_ARB_STATUS", SLICE_ARB_STATUS},
> };
>
> static void __fill_ext_reg(struct __guc_mmio_reg_descr *ext, @@ -422,6
> +464,8 @@ static int guc_capture_get_steer_reg_num(struct xe_device *xe)
>
> if (GRAPHICS_VERx100(xe) >= 1255)
> num += ARRAY_SIZE(xehpg_extregs);
> + if (GRAPHICS_VER(xe) >= 20)
> + num += ARRAY_SIZE(xe2_extregs);
>
> return num;
> }
> @@ -434,6 +478,7 @@ static void guc_capture_alloc_steered_lists(struct
> xe_guc *guc)
> const struct __guc_mmio_reg_descr_group *lists = guc->capture-
> >reglists;
> const struct __guc_mmio_reg_descr_group *list;
> struct __guc_mmio_reg_descr_group *extlists;
> + bool has_xe2_extregs = GRAPHICS_VER(gt_to_xe(gt)) >= 20;
> struct __guc_mmio_reg_descr *extarray;
> bool has_xehpg_extregs = GRAPHICS_VERx100(gt_to_xe(gt)) >= 1255;
> struct drm_device *drm = >_to_xe(gt)->drm; @@ -504,6 +549,12
> @@ static void guc_capture_alloc_steered_lists(struct xe_guc *guc)
> __fill_ext_reg(extarray, &xehpg_extregs[i],
> dss, slice, subslice);
> ++extarray;
> }
> +
> + if (has_xe2_extregs)
> + for (i = 0; i < ARRAY_SIZE(xe2_extregs); ++i) {
> + __fill_ext_reg(extarray, &xe2_extregs[i], dss,
> slice, subslice);
> + ++extarray;
> + }
> }
>
> extlists[0].num_regs = total;
> --
> 2.43.0
^ permalink raw reply [flat|nested] 23+ messages in thread
end of thread, other threads:[~2026-10-26 9:15 UTC | newest]
Thread overview: 23+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2026-10-23 6:05 [PATCH v5 0/7] drm/xe: Capture additional HW register state in devcoredump Nareshkumar Gollakoti
2026-10-23 6:05 ` [PATCH v5 1/7] drm/xe/devcoredump: Capture GT fuse registers " Nareshkumar Gollakoti
2026-10-23 13:27 ` Upadhyay, Tejas
2026-10-23 6:05 ` [PATCH v5 2/7] drm/xe/devcoredump: Add GuC register snapshot to devcoredump Nareshkumar Gollakoti
2026-10-26 6:35 ` Upadhyay, Tejas
2026-10-23 6:05 ` [PATCH v5 3/7] drm/xe/guc: Print register addresses in capture snapshot output Nareshkumar Gollakoti
2026-10-23 13:14 ` Upadhyay, Tejas
2026-10-26 6:37 ` Upadhyay, Tejas
2026-10-23 6:05 ` [PATCH v5 4/7] drm/xe: dump GAM page fault report registers in devcoredump Nareshkumar Gollakoti
2026-10-23 6:31 ` sashiko-bot
2026-10-26 6:48 ` Upadhyay, Tejas
2026-10-23 6:05 ` [PATCH v5 5/7] drm/xe/guc: add TDL, SLICE gfx registers to capture list Nareshkumar Gollakoti
2026-10-26 6:55 ` Upadhyay, Tejas
2026-10-23 6:05 ` [PATCH v5 6/7] drm/xe: capture L3 node status registers in devcoredump Nareshkumar Gollakoti
2026-10-23 6:24 ` sashiko-bot
2026-10-23 6:05 ` [PATCH v5 7/7] drm/xe/guc: capture additional engine state registers Nareshkumar Gollakoti
2026-10-23 6:26 ` sashiko-bot
2026-10-26 9:15 ` Upadhyay, Tejas
2026-10-23 6:14 ` ✗ CI.checkpatch: warning for drm/xe: Capture additional HW register state in devcoredump (rev6) Patchwork
2026-10-23 6:16 ` ✓ CI.KUnit: success " Patchwork
2026-10-23 6:56 ` ✓ Xe.CI.BAT: " Patchwork
2026-10-23 8:26 ` ✗ Xe.CI.FULL: failure " Patchwork
-- strict thread matches above, loose matches on Subject: below --
2026-10-22 13:29 [PATCH v5 0/7] drm/xe: Capture additional HW register state in devcoredump Nareshkumar Gollakoti
2026-10-22 13:29 ` [PATCH v5 5/7] drm/xe/guc: add TDL, SLICE gfx registers to capture list Nareshkumar Gollakoti
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